CPU Component documentation

Component name - Name of the component.
CPU type - CPU type
Clock settings - MCU Clock settings
- Clock frequency [MHz] - Frequency of the crystal or the external clock. The crystal should be in the range of 30kHz-100kHz and the external clock should be in the range of 0.0001-32MHz.
- Clock input pin - Clock input properties.
  - Pin name - Clock input pin name (for information only).
  - Pin signal - Clock input signal name.
- Clock output pin - Clock output properties.
  - Pin name - Clock output pin name (for information only).
  - Pin signal - Clock output signal name.
- Low-power modes settings - Low-power modes settings.
  - STOP instruction enabled - This property enables the STOP instruction.
    The following items are available only if the group is enabled (the value is "yes"):
    - Oscillator Enable In Stop Mode - If this property is "yes" then the oscillator will be enabled in the STOP mode.
    - Recovery from Stop Mode after - This property enables the CPU to exit the stop mode with a delay of 32 CGMXCLK cycles instead of a 4096 CGMXCLK cycle delay.
- CPU mode selection - CPU mode. This property is necessary for the correct CPU's internal timing.
  There are 2 modes:
  - Monitor mode - The following items are displayed in this mode:
    - PTC3 pin level - Logical value of PTC3 pin. The value on this pin is used by the processor when entering Monitor mode. For details see the datasheet of a particular device.
  - User mode - There are no items in this mode.
Maskable CPU interrupts - Enable/disable CPU maskable interrupts. This item modifies Interrupt Mask Bit I in Condition Code CPU register CCR.
Internal peripherals - Internal peripherals settings.
- ADC - This is a global setting specific for the CPU component, which is not visible in this component but may be mirrored into another components.
  - Conversion AD prescaler - Selection of the AD conversion prescaler.
  - ADC asynchro Clock Prescaler - Selection of the ADC asynchro clock conversion prescaler (in Low-power mode is divided by 2].
- I/O module - I/O ports' settings
  - PORT B - LED drive settings for all pins of PORT B.
    - LED drive for PTB2 - This property is used to enable LED drive capability.
    - LED drive for PTB3 - This property is used to enable LED drive capability.
    - LED drive for PTB4 - This property is used to enable LED drive capability.
    - LED drive for PTB5 - This property is used to enable LED drive capability.
- LVI module - This property enables/disables low voltage monitoring on the Vdd pin.
  The following items are available only if the group is enabled (the value is "Enabled"):
  - LVI operation - This property defines operation performed upon detection of a low voltage condition.
    There are 3 modes:
    - Reset - Reset is generated upon detection of a low voltage condition. There are no items in this mode.
    - Interrupt - Interrupt is generated when LVI detector state is changed. The following items are displayed in this mode:
      - Interrupt name - Interrupt vector that is invoked from the Low Voltage Detect interrupt (for information only).
    - Polling mode - No operation is done after detection of low voltage condition. You can use GetLowVoltageFlag() method to to get current status of the LVI output. There are no items in this mode.
  - LVI trip point - This property selects the voltage operating mode of the LVI module.
  - LVI in stop mode - This property enables/disables LVI module in the stop mode.
CPU interrupts - Interrupts allocated by CPU bean
- SWI - This property enables/disables generation of SWI interrupt service routine.
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Interrupt - Software Interrupt (for information only)
- PLL lock status changed - This property enables/disables generation of PLL interrupt and its' interrupt service routine (PLL must be turn on to enable PLL interrupt).
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Interrupt - Clock monitor interrupt. (for information only)
Enabled speed modes - Enabled speed modes
- High speed mode - High speed mode support (always enabled)
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Internal bus clock - The internal bus clock [MHz]. Maximum bus frequency is 8.0MHz for 5-V control and 4.0MHz for 3-V control. This property can be modified only if the PLL is enabled.
  - PLL clock - PLL clock (Enabled/Disabled)
    The following items are available only if the group is enabled (the value is "Enabled"):
    - PLL clock frequency - PLL clock frequency [MHz]. The value of PLL clock frequency depends on the bus clock frequency (for information only).
    - PLL bandwidth control - Selects automatic or manual bandwidth control.
    - PLL mode - Selects acquisition or tracking mode.
  - Clock source selections in high speed mode - This is a global setting specific for the CPU component, which is not visible in this component but may be mirrored into another components.
    - ADC clock source in high speed mode - ADC clock source.
- Low speed mode - Low speed mode support
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Internal bus clock - The internal bus clock [MHz]. Maximum bus frequency is 8.0MHz for 5-V control and 4.0MHz for 3-V control. This property can be modified only if the PLL is enabled.
  - PLL clock - PLL clock (Enabled/Disabled)
    The following items are available only if the group is enabled (the value is "Enabled"):
    - PLL clock frequency - PLL clock frequency [MHz]. The value of PLL clock frequency depends on the bus clock frequency (for information only).
    - PLL bandwidth control - Selects automatic or manual bandwidth control.
    - PLL mode - Selects acquisition or tracking mode.
  - Clock source selections in low speed mode - This is a global setting specific for the CPU component, which is not visible in this component but may be mirrored into another components.
    - ADC clock source in low speed mode - ADC clock source.
- Slow speed mode - Slow speed mode support
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Internal bus clock - The internal bus clock [MHz]. Maximum bus frequency is 8.0MHz for 5-V control and 4.0MHz for 3-V control. This property can be modified only if the PLL is enabled.
  - PLL clock - PLL clock (Enabled/Disabled)
    The following items are available only if the group is enabled (the value is "Enabled"):
    - PLL clock frequency - PLL clock frequency [MHz]. The value of PLL clock frequency depends on the bus clock frequency (for information only).
    - PLL bandwidth control - Selects automatic or manual bandwidth control.
    - PLL mode - Selects acquisition or tracking mode.
  - Clock source selections in slow speed mode - This is a global setting specific for the CPU component, which is not visible in this component but may be mirrored into another components.
    - ADC clock source in slow speed mode - ADC clock source.

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