CPU documentation - General info

Clock settings - MCU Clock settings
- Oscillator frequency [MHz] - Frequency of the crystal or the external clock. The crystal should be in the range of 1-6MHz and the external clock should be in the range of 0.0001-6MHz.
- Clock input pin - Clock input properties.
  - Pin name - Clock input pin name (for information only).
- Clock output pin - Clock output properties.
  - Pin name - Clock output pin name (for information only).
- Internal bus clock - The internal bus clock [MHz]. Maximum bus frequency is 3 MHz.
- Low-power modes settings - Low-power modes settings.
  - STOP instruction enabled - STOP instruction enabled
    The following items are available only if the group is enabled (the value is "Enabled"):
    - Recovery from Stop Mode after - This property enables the CPU to exit the stop mode with a delay of 32 CGMXCLK cycles instead of a 4096 CGMXCLK cycle delay.
- CPU mode selection - CPU mode. This property is necessary for the correct CPU's internal timing.
  There are 2 modes:
  - Monitor mode - The following items are displayed in this mode:
    - PTA3 pin level - Logical value of PTA3 pin. The value on this pin is used by the processor when entering Monitor mode. For details see the datasheet of a particular device.
  - User mode - There are no items in this mode.
Maskable CPU interrupts - Enable/disable CPU maskable interrupts. This item modifies Interrupt Mask Bit I in Condition Code CPU register CCR.
Internal peripherals - Internal peripherals settings.
- I/O module - I/O ports' settings
  - PORT D - LED drive settings for all pins of PORT D.
    - LED drive for PTD2 - PTD5 - This property is used to enable LED drive capability of PTD2-PTD5 pins.
    - IR LED drive for PTD0 - PTD1 - This property is used to enable IR LED drive capability of PTD0-PTD1 pins.
- LVI module - LVI module settings.
  - Circuit for Vdd - This property enables/disables low voltage monitoring on the Vdd pin.
    There are 2 modes:
    - Enabled - The following items are displayed in this mode:
      - LVI Operating Mode - Operating mode of the LVI module.
    - Disabled - There are no items in this mode.
  - Circuit for Vreg - This property enables/disables low voltage monitoring on the Vreg pin.
CPU interrupts - Interrupts allocated by CPU bean
- Reset vector - Reset vector settings.
  - Interrupt - Interrupt associated with the reset vector (for information only)
  - ISR name - Name of the reset vector - routine, that initializes CPU after reset.
- SWI - This property enables/disables generation of SWI interrupt service routine.
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Interrupt - Software Interrupt (for information only)
  - ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
    The user code of the routine should handle all respective interrupt flags correctly.

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