MC68HC908GR32A_32
 
General Info



CPU beans



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CPU MC68HC908GR32A_32
Freescale HC08 family : MC68HC908GR32A in 32 pin package
Device Initialization
(Description of the CPU component parameters.)
  • Clock settings - MCU Clock settings
    • Oscillator frequency [MHz] - Frequency of the crystal or the external clock. The crystal should be in the range of 1-8MHz and the external clock should be in the range of 0.0001-32MHz for 5-V control and 0.0001-16MHz for 3-V control.
    • Clock input pin - Clock input properties.
      • Pin name - Clock input pin name (for information only).
    • Clock output pin - Clock output properties.
      • Pin name - Clock output pin name (for information only).
    • MCLK output clock - MCLK output clock settings.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Clock output pin - MCLK output clock pin (for information only)
      • Clock output frequency - Bus clock prescaler

        There are 6 options:
        • Bus clock: Bus clock frequency
        • Bus clock divided by 2: Bus clock frequency divided by 2
        • Bus clock divided by 4: Bus clock frequency divided by 4
        • Crystal frequency: Crystal frequency
        • Crystal frequency divided by 2: Crystal frequency divided by 2
        • Crystal frequency divided by 4: Crystal frequency divided by 4

    • Low-power modes settings - Low-power modes settings.
      • STOP instruction enabled - STOP instruction enabled
        The following items are available only if the group is enabled (the value is "Enabled"):
        • Oscillator Enable In Stop Mode - This property enables the oscillator to continue operation during stop mode. Setting this property to "yes" allows the oscillator to operate continuously even during stop mode.
        • Recovery from Stop Mode after - This property enables the CPU to exit the stop mode with a delay of 32 CGMXCLK cycles instead of a 4096 CGMXCLK cycle delay.
    • CPU mode selection - CPU mode. This property is necessary for the correct CPU's internal timing.
      There are 2 modes:
      • Monitor mode - The following items are displayed in this mode:
        • PTB4 pin level - Logical value of PTB4 pin. The value on this pin is used by the processor when entering Monitor mode. For details see the datasheet of a particular device.
      • User mode - There are no items in this mode.
    • PLL clock - PLL clock (Enabled/Disabled)
      The following items are available only if the group is enabled (the value is "Enabled"):
      • PLL clock frequency - PLL clock frequency [MHz]. The value of PLL clock frequency depends on the bus clock frequency (for information only).
      • PLL bandwidth control - Selects automatic or manual bandwidth control.
      • PLL mode - Selects acquisition or tracking mode.
    • Internal bus clock - The internal bus clock [MHz]. Maximum bus frequency is 8.2MHz for 5-V control and 4.1MHz for 3-V control. This property can be modified only if the PLL is enabled.
  • Maskable CPU interrupts - Enable/disable CPU maskable interrupts. This item modifies Interrupt Mask Bit I in Condition Code CPU register CCR.
  • Internal peripherals - Internal peripherals settings.
    • LVI module - This property enables/disables low voltage monitoring on the Vdd pin.
      The following items are available only if the group is enabled (the value is "Enabled"):
    • TBM module - TBM settings
      • TBM prescaler - Extra TBM prescaler.
        This item modifies the TMBCLKSEL bit in the CONFIG2 register.
  • CPU interrupts - Interrupts allocated by CPU bean
    • Reset vector - Reset vector settings.
      • Interrupt - Interrupt associated with the reset vector (for information only)
      • ISR name - Name of the reset vector - routine, that initializes CPU after reset.
    • PLL lock status changed - This property enables/disables generation of PLL interrupt and its' interrupt service routine (PLL must be turn on to enable PLL interrupt).
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Interrupt - Clock monitor interrupt. (for information only)
      • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
        The user code of the routine should handle all respective interrupt flags correctly.
    • SWI - This property enables/disables generation of SWI interrupt service routine.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Interrupt - Software Interrupt (for information only)
      • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
        The user code of the routine should handle all respective interrupt flags correctly.

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