CPU Component documentation

Component name - Name of the component.
CPU type - CPU type
Clock settings - MCU Clock settings
- Oscillator frequency [MHz] - Frequency of the main crystal. Crystal should be in the range of 1-16MHz.
- Clock input pin - Clock input properties.
  - Pin name - Clock input pin name (for information only).
  - Pin signal - Clock input signal name.
- Clock output pin - Clock output properties.
  - Pin name - Clock output pin name (for information only).
  - Pin signal - Clock output signal name.
- MCLK output clock - This property enables/disables MCLK to be an output signal. MCLK is the same frequency as the bus clock.
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Clock output pin - MCLK output clock pin (for information only)
  - Clock output pin signal - Signal name of the clock output pin
- Low-power modes settings - Low-power modes settings.
  - STOP instruction enabled - STOP instruction enabled
    The following items are available only if the group is enabled (the value is "Enabled"):
    - Recovery from Stop Mode after - This property enables the CPU to exit the stop mode with a delay of 32 CGMXCLK cycles instead of a 4096 CGMXCLK cycle delay.
- CPU mode selection - CPU mode. This property is necessary for the correct CPU's internal timing.
  There are 2 modes:
  - Monitor mode - The following items are displayed in this mode:
    - PTC3 pin level - Logical value of PTC3 pin. The value on this pin is used by the processor when entering Monitor mode. For details see the datasheet of a particular device.
  - User mode - There are no items in this mode.
Maskable CPU interrupts - Enable/disable CPU maskable interrupts. This item modifies Interrupt Mask Bit I in Condition Code CPU register CCR.
Internal peripherals - Internal peripherals settings.
- EEPROM source clock. - This is a global setting specific for the CPU component, which is not visible in this component but may be mirrored into another components.
  - Clock source - This property selects the reference clock source for the EEPROM timebase divider. This item modifies the EEDIVCLK bit in the CONFIG2 register.
- LVI module - This property enables/disables low voltage monitoring on the Vdd pin.
  The following items are available only if the group is enabled (the value is "Enabled"):
  - LVI resets - This property enables/disables generating of LVI resets.
  - LVI in stop mode - This property enables/disables LVI module in the stop mode.
CPU interrupts - Interrupts allocated by CPU bean
- PLL lock status changed - This property enables/disables generation of PLL interrupt and its' interrupt service routine (PLL must be turn on to enable PLL interrupt).
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Interrupt - Clock monitor interrupt. (for information only)
- SWI - This property enables/disables generation of SWI interrupt service routine.
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Interrupt - Software Interrupt (for information only)
Enabled speed modes - Enabled speed modes
- High speed mode - High speed mode support (always enabled)
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Internal bus clock - The internal bus clock [MHz]. Maximum bus frequency is 8.4MHz. This property can be modified only if the PLL is enabled.
  - PLL clock - PLL clock (Enabled/Disabled)
    The following items are available only if the group is enabled (the value is "Enabled"):
    - PLL clock frequency - PLL clock frequency [MHz]. The value of PLL clock frequency depends on the bus clock frequency (for information only).
    - PLL bandwidth control - Selects automatic or manual bandwidth control.
    - PLL mode - Selects acquisition or tracking mode.
- Low speed mode - Low speed mode support
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Internal bus clock - The internal bus clock [MHz]. Maximum bus frequency is 8.4MHz. This property can be modified only if the PLL is enabled.
  - PLL clock - PLL clock (Enabled/Disabled)
    The following items are available only if the group is enabled (the value is "Enabled"):
    - PLL clock frequency - PLL clock frequency [MHz]. The value of PLL clock frequency depends on the bus clock frequency (for information only).
    - PLL bandwidth control - Selects automatic or manual bandwidth control.
    - PLL mode - Selects acquisition or tracking mode.
- Slow speed mode - Slow speed mode support
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Internal bus clock - The internal bus clock [MHz]. Maximum bus frequency is 8.4MHz. This property can be modified only if the PLL is enabled.
  - PLL clock - PLL clock (Enabled/Disabled)
    The following items are available only if the group is enabled (the value is "Enabled"):
    - PLL clock frequency - PLL clock frequency [MHz]. The value of PLL clock frequency depends on the bus clock frequency (for information only).
    - PLL bandwidth control - Selects automatic or manual bandwidth control.
    - PLL mode - Selects acquisition or tracking mode.

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