CPU documentation - General info

Clock settings - MCU Clock settings
- Source CPU clock - The clock source for the internal bus clock. If the Internal and the External clock sources are enabled identical clock source must be specified for all speed modes.
- Internal Clock - If this property is enabled the internal clock is allowed for MCU timing.
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Internal oscillator frequency [kHz] - Frequency of the internal oscillator.
- External clock - If this property is enabled, an external clock is allowed for MCU timing.
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Clock source - Possible external clock sources (external crystal, external RC oscillator or external clock).
    There are 2 modes:
    - External crystal - The following items are displayed in this mode:
      - Oscillator frequency [MHz] - Frequency of the crystal or the external clock.
        The crystal should be 32.768 kHz for MC68HC908AP64 and 1-8 MHz for MC68HC908AP64A.
        The external clock should be in the range of 0.0001- 16MHz for MC68HC908AP64 and 0.0001 - 32 MHz for MC68HC908AP64A.
      - Clock input pin - Clock input properties.
        
        Pin name - Clock input pin name (for information only).
      - Clock output pin - Clock output properties.
        
        Pin name - Clock output pin name (for information only).
    - External RC oscillator - See External crystal mode for items available in this mode.
- Internal bus clock - The internal bus clock [MHz]. Maximum bus frequency is 8.0 MHz. The bus clock can be specified only if the PLL clock is enabled.
- PLL clock - PLL clock (Enabled/Disabled)
  The following items are available only if the group is enabled (the value is "Enabled"):
  - PLL clock frequency - PLL clock frequency [MHz]. The value of PLL clock frequency depends on the bus clock frequency (for information only).
  - PLL bandwidth control - Selects automatic or manual bandwidth control.
  - PLL mode - Selects acquisition or tracking mode.
- Low-power modes settings - Low-power modes settings.
  - STOP instruction enabled - This property enables the STOP instruction.
    The following items are available only if the group is enabled (the value is "yes"):
    - Internal oscillator in stop mode - This property disables/enables the internal oscillator during stop mode.
    - Ext. RC oscillator in stop mode - This property enables/disables the external RC oscillator during stop mode. This is useful for driving the real time clock module that allows to generate periodic wake-up in the stop mode. If this property is disabled the external XTAL oscillator will be disabled during stop mode.
    - Ext. crystal oscillator in stop mode - This property enables/disables the external crystal (XTAL) oscillator during stop mode. This is useful for driving the real time clock module that allows to generate periodic wake-up in the stop mode. If this property is disabled the external XTAL oscillator will be disabled during stop mode.
    - Recovery from Stop Mode after - This property enables the CPU to exit the stop mode with a delay of 32 ICLK cycles instead of a 4096 ICLK cycle delay.
- CPU mode selection - CPU mode. This property is necessary for the correct CPU's internal timing.
  There are 2 modes:
  - Monitor mode - The following items are displayed in this mode:
    - PTB0 pin level - Logical value of PTB0 pin. The value on this pin is used by the processor when entering Monitor mode. For details see the datasheet of a particular device.
  - User mode - There are no items in this mode.
Maskable CPU interrupts - Enable/disable CPU maskable interrupts. This item modifies Interrupt Mask Bit I in Condition Code CPU register CCR.
Internal peripherals - Internal peripherals settings.
- I/O module - I/O ports' settings
  - PORT A - LED drive settings for all pins of PORT A.
    - LED drive for PTA0 - PTA7 This property is used to enable LED drive capability.
- LVI module - Low-voltage inhibit (LVI) module settings.
  - Vdd LVI - This property enables/disables low voltage monitoring on the Vdd pin.
  - LVI in stop mode - This property enables/disables LVI module in the stop mode.
  - LVI resets - This property enables/disables generating of LVI resets.
  - Vreg LVI - This property enables/disables low voltage monitoring on the Vreg pin.
- TBM module - TBM settings
  - TBM clock source - This property selects which oscillator output to be driven out as OSCCLK to the timebase module (TBM).
    This property modifies the OSCCLK1and OSCCLK0 bits in the CONFIG2 register.
CPU interrupts - Interrupts allocated by CPU bean
- Reset vector - Reset vector settings.
  - Interrupt - Interrupt associated with the reset vector (for information only)
  - ISR name - Name of the reset vector - routine, that initializes CPU after reset.
- PLL lock status changed - This property enables/disables generation of PLL interrupt and its' interrupt service routine (PLL must be turn on to enable PLL interrupt).
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Interrupt - Clock monitor interrupt. (for information only)
  - ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
    The user code of the routine should handle all respective interrupt flags correctly.
- SWI - This property enables/disables generation of SWI interrupt service routine.
  The following items are available only if the group is enabled (the value is "Enabled"):
  - Interrupt - Software Interrupt (for information only)
  - ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
    The user code of the routine should handle all respective interrupt flags correctly.

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