This component (in cooperation with similar device as SynchroSlave) implements a serial synchronous master-slave communication. Only two devices can communicate - one of them is a MASTER and the other one is a SLAVE.

The SPI bus specifies four logic signals:

• SPSCK — Serial Clock (output from master)
• MOSI/SIMO — Master Output, Slave Input (output from master)
• MISO/SOMI — Master Input, Slave Output (output from slave)
• SS — Slave Select (active low; output from master)

Alternative naming conventions are also widely used:

• SCLK, SCK, CLK — Serial Clock (output from master)
• SDI, DI, SI — Serial Data In
• SDO, DO, SO — Serial Data Out
• nCS, CS, nSS, STE — Chip Select, Slave Transmit Enable (active low; output from master)

The difference between the master and slave is that the master generates the clock signal while the slave receives it. Consequently, if the master has no data to send to slave and needs to receive data from the slave, it still has to transmit a character. For example a reserved character called "empty character" that may be ignored by slave (see properties Empty character and Ignore empty char. ).
This component allows to set an empty character to cut such a character after the reception of it.

That also applies vice versa - if the slave has no data, it sends an empty character to the master.

The type of the user type ComponentName_TComData is a byte if the number of information bits ( Width property) is less than or equal to 8. If the number of information bits is greater than 8, the type of the user type ComponentName_TComData is a word.

---

SW overrun behavior

• If the poling mode is used already received data will not be lost.
• If the interrupt mode is used and data buffer (Input buffer size property) is greater than 0 then already received data will not be lost, too.
• But if the interrupt mode is used and data buffer (Input buffer size property) is equal to 0 new data replace the older one.

---

Configuring Clock edge and Shift clock idle polarity properties

The pictures below show posible settings and their influence on the SPI communication operation.
The Clock edge property defines edge on which new logical value of data is moved to line, this edge is in pictures marked by red point.
If Clock edge is set to Falling edge and Shift clock idle polarity is set to Low or Clock edge is set to Rising edge and Shift clock idle polarity is set to High (picture 3 and 4; CPHA = 0), the first data bit transfer to line starts with falling edge on the SS line, in picture marked by green point. In this case the SS connection is demanded.
In other two cases (picture 1 and 2; CPHA = 1) the first data bit transfer to line starts with first edge on the CLK line.
If the target architecture uses CPOL (Clock polarity) and CPHA (Clock phase) bits, you can find the corresponding values in the pictures.

---