SyncProc
 
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Component SyncProc
Sync Processor
Component Level: High
Category: CPU Internal Peripherals-Display
Properties:
(Properties are parameters of the component. Please see the Embedded Components page for more information.)
  • Component name - Name of the component.
  • Sync Processor channel - Sync Processor Channel.
  • Interrupt service/event - Component uses the interrupt service sync processing. If this property is set to "Enabled", the component functionality (e.g. event calling) depends on the interrupt service and will not operate if the CPU interrupts are disabled. For details please refer to chapter "interrupt service in the component's generated code".
    The following items are available only if the group is enabled (the value is "Enabled"):
    • Interrupt - Interrupt generated by the Sync Processor.
    • Interrupt priority - This property determines an interrupt priority of the SyncProc interrupt.
    • VSync interrupt on - Specifies the triggering edge of Vsync interrupt.

      There are 4 options:
      • rising or falling edge: One of the following edge type will be selected: rising or falling
      • rising edge: Rising edge required
      • falling edge: Falling edge required
      • both edges: Both edges (rising and falling) required

  • Polarity det. pulse width - Select polarity detection pulse width. The Hsync polarity detection circuit measures the length of high and low period of the HSYNC input.
  • Fast horiz. freq. count - Set to shorten the measurement cycle of the horizontal frequency. If enabled then Number of Hsync pulses is counted in an 8ms window. If disabled then Number of Hsync pulses is counted in an 32ms window.
  • Sync output mode - Select mode of Sync output pins.

    There are 3 options:
    • VSYNC and HSYNC inputs: Sync outputs follow sync inputs VSYNC and HSYNC
    • HSYNCO from composite input: HSYNCO follows the composite sync input and VSYNCO is the extracted Vsync (3 to 14ms delay to composite input),
    • Free-running: Free-running pulse

  • Free-Running options - Select the frequencies of the internal generated free-running sync pulses for output to HSYNCO and VSYNCO pins.
  • Output pol. depend od sync input - Select if output polarity depend on sync input. If it is selected Yes, then sync outputs VSYNCO/HSYNCO have same or inverted polarity as sync inputs (depend on properties Hsync/Vsync polarity). If it is selected no, polarity of sync outputs VSYNCO/HSYNCO depend on properties Hsync/Vsync polarity only.
  • Other Sync Processor pins - Connections of the SyncProc.
  • Composite input - Enable/Disable composite (Sync-On-Green) input. This item is available if "HSYNCO from composite input" is selected in the Sync output mode property.
    The following items are available only if the group is enabled (the value is "Enabled"):
  • HSync output pin - Enable/Disable HSync output pin.
    The following items are available only if the group is enabled (the value is "Enabled"):
    • Pin - Pin reserved for Hsync output.
    • Pin signal - Signal name of HSync pin.
    • HSync polarity - Set polarity of Hsync output.

      There are 2 options:
      • Same as sync input: Same polarity as sync input
      • Inverted of sync input: Inverted polarity of sync input

  • VSync output pin - Enable/Disable VSync output pin.
    The following items are available only if the group is enabled (the value is "Enabled"):
    • Pin - Pin reserved for Vsync output.
    • Pin signal - Signal name of VSync pin.
    • VSync polarity - Set polarity of Vsync output.

      There are 2 options:
      • Same as sync input: Same polarity as sync input
      • Inverted of sync input: Inverted polarity of sync input

  • Clamp output - Enable/Disable Clamp Pulse Output.
    The following items are available only if the group is enabled (the value is "Enabled"):
    • Pin - Pin reserved for Clamp Output.
    • Pin Signal - Signal name of Clamp pin.
    • Clamp Polarity - Set polarity of the clamp pulse.
    • Back Porch - Defines the triggering edge of the clamp pulse output relative to the HSYNC input.
    • Pulse Width - Set output clamp pulse width.
  • These settings are supported only for MC68HC908LD64 derivatives.
    • DE output - DE pulse output.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Pin - DE output from the SyncProc.
      • Pin signal - Signal name of the DE pin.
    • DCLK output - Pixel clock output.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Pin - DCLK output from the SyncProc.
      • Pin signal - Signal name of the DCLK pin.
      • Phase adjustment - Adjust the DCLK output phase. Each increment adds approximately 2 to 3ns delay to the DCLK output.
  • Initialization - Initial settings (after power-on or reset).
  • CPU clock/speed selection - Settings for the CPU speed modes: if the component is supported or not.
    For details about speed modes please refer to page Speed Modes Support.

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