This component emulates an I2C communication interface, which is based on the Philips I2C-bus specification version 2.0. The interface uses two general-purpose I/O pins, first for the Serial Data line (SDA), second for the Serial Clock line (SCL). Clock pulses of SCL are generated by software and no other hardware device is used by this component.

Operating modes features:

MASTER

• Single master communication only (no other master is allowed on the bus)
• The combined format of communication possible (see Automatic stop condition property)
• 7-bit slave addressing (10-bit addressing can be made as well)
• No wait state initiated when a slave device holds the SCL line low
• No bus error detection provided

SLAVE - this operating mode is not implemented yet

• 7-bit slave addressing
• General call address detection not provided
• The combined format of communication not provided
• The stop condition detection not provided

Notice: The clock for the component is generated by software so its frequency and the whole timing of the component is usually slower than selected.
There is only guaranteed that the clock frequency won't exceed the selected one.
The amount of slow down is determined by the communication code overhead and influences that slow down the program execution speed (e.g. interrupts processed during the transer, memory wait-states etc....)