Init_SyncProc
 
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Init Code Usage

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Component Init_SyncProc for HC08
Sync Processor
Component Level: Peripheral Initialization
Category: CPU Internal Peripherals-Peripheral Initialization
Properties:
(Properties are parameters of the component. Please see the Embedded Components page for more information.)
  • Component name - Name of the component.
  • Device - Selection of the Sync Processor device module.
  • Settings - Common Sync Processor module settings.
    • Clock settings - Clock/timing settings of the module.
      • These settings are supported only for MC68HC908LD64 derivatives.
        • Free-Running mode select - Free Running Video Mode Select.
          This item modifies the HVOCR[1:0] bits in the HVOCR register.
        • Multiplier - Multiplier Select.
          This item modifies the MUL[7:4] bits in the PPG register.
        • VCO Range - VCO Range Select.
          This item modifies the VRS[7:4] bits in the PPG register.
        • Free-Running options - Selected Free-Running mode (for information only). Value is available only if combination of the Free-Running mode, Multiplier and VCO Range is correct.
        • PLL - Activate PLL.
          This item modifies the PLLON bit in the PCTL register.
        • Base Clock - Selects either the crystal oscillator output (OSCXCLK) or the VCO clock (CGMVCLK) as base clock.
          This item modifies the BCS bit in the PCTL register.
        • Bandwidth Control - Selects automatic or manual bandwidth control.
          This item modifies the AUTO bit in the PBWC register.
        • PLL mode - Controls whether the PLL is in acquisition or tracking mode.
          This item modifies the ACQ bit in the PBWC register.
        • DCLK phase adjustment - Adjust the DCLK output phase. Each increment adds approximately 2 to 3ns delay to the DCLK output.
          This item modifies the DCLKPH[1:0] bits in the HVOCR register.
      • These settings are supported only for MC68HC908BD48 derivatives.
        • Free-Running options - Free-Running HSYNC and VSYNC options.
          This item modifies the HVOCR[2:0] bits in the HVOCR register.
      • Clamp Pulse Width - Set clamp output pulse width.
        This item modifies the CPW[1:0] bits in the VFHR register.
      • Polarity detection pulse width - Select polarity detection pulse width. The Hsync polarity detection circuit measures the length of high and low period of the HSYNC input.
        This item modifies the HPS[0:1] bits in the SPCR1 register.
    • Outputs generated - Select output signals for sync output pins.
      This item modifies the SOUT bit in the SPIOCR register.
    • These settings are supported only for MC68HC908BD48 derivatives.
      • Clamp Pulse Output - Enable/disable clamp pulse output circuitry.
        This item modifies the CLAMPOE bit in the SPIOCR register.
    • Fast horizontal freq count - Set to shorten the measurement cycle of the horizontal frequency. If enabled then number of Hsync pulses is counted in an 8ms window. If disabled then number of Hsync pulses is counted in an 32ms window.
      This item modifies the FSHF bit in the SPCR1 register.
    • Auto polarity - Auto polarity of sync output. Together with HSync polarity and VSync polarity controls the output polarity of sync outputs (HSYNCO, VSYNCO or HOUT, VOUT). If Auto polarity set to yes, then sync outputs have the same or inverted polarity as sync inputs. Otherwise the polarity depend on properties Hsync, Vsync polarity only.
      This item modifies the ATPOL bit in the SPCR1 register.
    • HSync polarity - Set polarity of Hsync output. Meaning of this polarity setting depends on Auto polarity setting. When Auto polarity is set to yes the HSync polarity setting means negative or positive sync output. Otherwise it means the same or inverted polarity of sync input.
      This item modifies the HINVO bit in the SPCSR register.

      There are 2 options:
      • Negative or Same as sync input: Negative or Same polarity as sync input
      • Positive or Inverted of sync input: Positive or Inverted polarity of sync input

    • VSync polarity - Set polarity of Vsync output. Meaning of this polarity setting depends on Auto polarity setting. When Auto polarity is set to yes the VSync polarity setting means negative or positive sync output. Otherwise it means the same or inverted polarity of sync input.
      This item modifies the VINVO bit in the SPCSR register.

      There are 2 options:
      • Negative or Same as sync input: Negative or Same polarity as sync input
      • Positive or Inverted of sync input: Positive or Inverted polarity of sync input

    • Clamp polarity - Set polarity of the clamp output pulses.
      This item modifies the COINV bit in the SPIOCR register.
    • Back Porch - Back porch defines the triggering edge of the Clamp pulse output relative to the HSYNC input.
      This item modifies the BPOR bit in the SPIOCR register.
  • Pins - Module pins/signals settings.
    • VSync input pin - Vertical synchronization input to the SyncProc.
    • VSync input pin signal - Signal name of the VSync pin.
    • Composite input pin - Enable/disable composite input pin.
      Note: On the MC68HC908BD48 derivative when the SOG pin is used as composite input then SOG function should be also enabled.
      This item modifies the COMP bit in the SPCSR register.
      The following items are available only if the group is enabled (the value is "Enabled"):
    • HSync output pin - Enable/Disable HSync output pin.
      MC68HC908BD48: This item modifies the HSYNCOE bit in the CONFIG0 register.
      MC68HC908LD64: This item modifies the HOUTE bit in the PDCR register.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Pin - Pin reserved for Hsync output.
      • Pin signal - Signal name of HSync pin.
    • VSync output pin - Enable/disable VSync output pin.
      MC68HC908BD48: This item modifies the VSYNCOE bit in the CONFIG0 register.
      MC68HC908LD64: This item modifies the VOUTE bit in the PDCR register.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Pin - Pin reserved for Vsync output.
      • Pin signal - Signal name of VSync pin.
    • CLAMP output pin - Enable/disable clamp output pin.
      MC68HC908DB48: This item modifies the CLAMPE bit in the PDCR register.
      MC68HC908LD64: This item modifies the ELS0B, ELS0A bits in the TSC0 register.
      The following items are available only if the group is enabled (the value is "Enabled"):
      • Pin - Pin reserved for Clamp Output.
      • Pin signal - Signal name of Clamp pin.
    • These settings are supported only for MC68HC908LD64 derivatives.
      • DE output - DE pulse output.
        This item modifies the DEE bit in the PDCR register
        The following items are available only if the group is enabled (the value is "Enabled"):
        • Pin - Pin reserved for DE output from the SyncProc.
        • Pin signal - Signal name of the DE pin.
      • DCLK output - Pixel clock output.
        This item modifies the DCLKE bit in the PDCR register.
        The following items are available only if the group is enabled (the value is "Enabled"):
        • Pin - Pin reserved for DCLK output from the SyncProc.
        • Pin signal - Signal name of the DCLK pin.
  • Interrupts - Interrupts settings of the module.
    • VSync interrupt - VSync interrupt settings.
      • Interrupt - Interrupt vector (for information only).
      • Low VSync interrupt - Enable/disable Low VSync interrupt.
        This item modifies the LVSIE bit in the SPCR1 register.
      • VSync interrupt - Enable/disable VSync interrupt.
        This item modifies the VSIE bit in the SPCSR register.
      • VSync interrupt Edge - Specifies the triggering edge of Vsync interrupt.
        This item modifies the VEDGE bit in the SPCSR register.

        There are 2 options:
        • Rising edge: VSIF bit will be set by rising edge of Vsync.
        • Falling edge: VSIF bit will be set by falling edge of Vsync.

      • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
        The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
    • These settings are supported only for MC68HC908LD64 derivatives.
      • PLL interrupt - PLL interrupt settings.
        • Interrupt - Interrupt vector (for information only).
        • PLL interrupt - Enable/disable PLL interrupt.
          This item modifies the PLLIE bit in the PCTL register.
        • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
          The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
  • Initialization - Initialization options of the module.
    • Call Init method - The Init method of the component may be called after power-on or reset (in initialization code) by PE.
      yes - The Init method is called by PE
      no - The Init method is not called by PE, it should be called in user's code.

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