Init_SPI
 
General Info



Init.Components



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Component icon
Component Init_SPI for RS08
Serial Peripheral Interface (SPI)
Device Initialization
(Description of the component parameters.)
  • Device - Selection of the SPI device module.
  • Settings - Common SPI module settings.
    • Clock settings - Clock/timing module settings.
      • Baud Rate Prescaler Divisor - Select one of the eight divisors for the SPI baud rate prescaler used for setting of SPI communication frequency.
        This item modifies the SPPR[2:0] bits in the SPIBR register.
      • Baud Rate Divisor - Select one of the eight divisors for the SPI baud rate divider used for setting of SPI communication frequency.
        This item modifies the SPR[2:0] bits in the SPIBR register if the maximum value of prescaler is less then 512, else it modifies the SPR[3:0] bits in the SPIBR register.
      • Frequency - SPI communication speed (for information only).
        This item is influenced by the following properties: Baud Rate Prescaler Divisor, Baud Rate Divisor.
    • Mode Select - Select master/slave mode.
      This item modifies the MSTR bit in the SPIC1 register.
    • Clock Polarity - Select polarity of the SPI clock signal. This property determines the logic state of the SCK pin between transmissions.
      To transmit data between SPI modules, the SPI modules must have identical Clock polarity values.
      This item modifies the CPOL bit in the SPIC1 register.

      There are 2 options:
      • active-high: Active-high clocks selected. In idle state SCK is low.
      • active-low: Active-low clocks selected. In idle state SCK is high.

    • Clock Phase - Select phase of the SPI clock signal. This property determines the edge used for data sampling (and the edge used for data sending).
      This item modifies the CPHA bit in the SPIC1 register.

      There are 2 options:
      • Second edge: Sampling of data occurs at even edges (2,4,6,...,16) of the SCK clock.
      • First edge: Sampling of data occurs at odd edges (1,3,5,...,15) of the SCK clock.

    • Data shift order - Select the order in which data will be shifted out of MOSI. (Possible values: MSB first/LSB first).
      This item modifies the LSBFE bit in the SPIC1 register.
    • Bidirectional mode - Enable/disable the bidirectional mode.
      This item modifies the SPC0 bit in the SPIC2 register.
    • Output enable in Bidirect. - Select yes/no if the SPI data output has to be enabled in bidirectional mode.
      This item modifies the BIDIROE bit in the SPIC2 register.
    • SS pin function - Select the function of the Slave Select pin in master mode. In slave mode the SS pin always acts as the low-true slave select input.
      This item modifies the SSOE bit in the SPIC1 register and the MODFEN bit in the SPIC2 register.

      There are 3 options:
      • General Purpose I/O: The pin is not used by SPI.
      • Slave Select input for mode fault: The pin acts as the mode fault input.
      • Automatic Slave Select output: The pin acts as the slave select output.

    • Stop in Wait Mode - Enable/disable Stop in Wait Mode.
      This item modifies the SPISWAI bit in the SPIC2 register.
    • Settings only if SPI support the data width selection feature.
      • Data length - Select either an 8- or 16-bit SPI data transmission length.
        This item modifies the SPIMODE bit in the SPIC2 register.

        There are 2 options:
        • 8 bits: 8-bit SPI shift register, match register, and buffers.
        • 16 bits: 16-bit SPI shift register, match register, and buffers.

    • Settings only if SPI support the match feature.
      • Match value - This property defines the hardware compare value. When the value received in the SPI data receive buffer equals this value the SPI match flag (SPIMF resp. SPMF) is set.
        This item modifies the SPIM register.
    • Settings only if SPI support input filter
      • Input filter on SPI pins - The filter restricts the SPI data rate to 6 MHz, but protects the SPI from noise during data transfers.
        This item modifies the SPIxFE bit in the SOPT2 register.
    • Settings only if SPI support FIFO feature.
      • FIFO Mode - This bit enables the SPI to utilise a 64bit FIFO (8bytes or 4 16-bitwords) for both transmit and receive buffers.
        This item modifies the FIFOMODE bit in the SPIxC3 register.
        The following items are available only if the group is enabled (the value is "Enabled"):
        • Settings only if SPI supports FIFO interrupt clearing by extra register SPIxCI.
          • Interrupts cleared by - This property selects the mechanism by which SPRF, SPTEF, TNEAREF, RNFULLF interrupts gets cleared: Interrupts gets cleared when respective flags gets cleared depending on the state of FIFOs or by writing to the SPIxCI respective bits.
            This item modifies the INTCLR bit in the SPIxC3 register and is available only if the FIFO Mode is Enabled.

            There are 2 options:
            • state of FIFOs: Interrupts gets cleared when respective flags gets cleared depending on the state of FIFOs.
            • SPIxCI bits: Interrupts gets cleared by writing to the SPIxCI respective bits.

        • Tx FIFO Nearly Empty Water Mark - This property selects the mark after which TNEAREF flag is asserted.
          This item modifies the TNEAREF_MARK bit in the SPIxC3 register and is available only if the FIFO Mode is Enabled.

          There are 2 options:
          • 16bits or less: TNEAREF is set when Transmit FIFO has16bits or less.
          • 32bits or less: TNEAREF is set when Transmit FIFO has 32bits or less.

        • Rx FIFO Nearly Full Water Mark - This property selects the mark after which RNFULLF flag is asserted.
          This item modifies the RNFULLF_MARK bit in the SPIxC3 register and is available only if the FIFO Mode is Enabled.

          There are 2 options:
          • 48bits or more: RNFULLF is set when Receive FIFO has 48bits or more.
          • 32bits or more: RNFULLF is set when Receive FIFO has 32bits or more.

  • Pins - Module pins/signals settings.
    • SCK pin - Clock signal pin.
    • MISO pin allocation - Enable/disable allocation of the MISO (Master In/Slave Out) pin. Allocated pin is exclusively used by this peripheral and cannot be used by any other device.
      The following items are available only if the group is enabled (the value is "Enabled"):
    • MOSI pin allocation - Enable/disable allocation of the MOSI (Master Out/Slave In) pin. Allocated pin is exclusively used by this peripheral and cannot be used by any other device.
      The following items are available only if the group is enabled (the value is "Enabled"):
    • SS pin allocation - Enable/disable allocation of the SS (Slave Select) pin. Allocated pin is exclusively used by this peripheral and cannot be used by any other device.
      The following items are available only if the group is enabled (the value is "Enabled"):
  • Interrupts/DMA - Interrupt settings of the module.
    • Settings only if CPU supports interrupts
      • Interrupt - Interrupt vector (for information only).
      • Settings only if CPU supports interrup priority.
    • Receive and fault interrupt - Enable/disable SPI Interrupt for SPI receive buffer full and mode fault events.
      This item modifies the SPIE bit in the SPIC1 register.
    • Settings only if SPI support DMA
      • Receive DMA - This property enables receive DMA and disables interrupt request from SPRF flag a vice versa.
        This item modifies RXDMAE bit in SPIxC2 register.
    • Transmit interrupt - Enable/disable SPI Transmit Interrupt for SPI transmit buffer empty.
      This item modifies the SPTIE bit in the SPIC1 register.
    • Settings only if SPI support DMA
      • Transmit DMA - This property enables receive DMA and disables interrupt request from SPTEF flag a vice versa. Fault interrupt isn't affected.
        This item modifies TXDMAE bit in SPIxC2 register.
    • Settings only if SPI support the match feature.
      • Match interrupt - Enable/disable SPI Match Interrupt for SPI receive data buffer hardware match function.
        This item modifies the SPMIE bit in the SPIC2 register.
    • Settings only if SPI support FIFO feature.
      • Tx FIFO Nearly Empty Interrupt - Enable/disable SPI Transmit FIFO Nearly Empty Interrupt in the FIFO mode.
        This item modifies the TNEARIEN bit in the SPIxC3 register.
      • Rx FIFO Nearly Full Interrupt - Enable/disable SPI Receive FIFO Nearly Full Interrupt in the FIFO mode.
        This item modifies the RNFULLIEN bit in the SPIxC3 register.
    • Settings only if CPU supports interrupts
      • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
        The user code of the routine should handle all respective interrupt flags correctly.
  • Initialization - Initialization options of the module.
    • Enable SPI system - Select yes/no to enable SPI system.
      This item modifies the SPE bit in the SPIC1 register.

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