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Component
Init_SLIC for HCS08
Slave LIN Interface Controller (SLIC)
Component Level: Peripheral Initialization
Properties:
(Properties are parameters of the component. Please see the Embedded Components page for more information.)
- Component name - Name of the component.
- Device - Selection of the SLIC device module.
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Settings - Common SLIC module settings.
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Clock setting - Clock/timing settings of the module.
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SLIC clock - SLIC clock (for information only). The frequency of the SLIC clock must be between 2 MHz and 20 MHz, factoring in worst case possible numbers due to untrimmed process variations, as well as temperature and voltage variations in oscillator frequency. This will guarantee greater than 1.5% accuracy for all LIN messages from 1–20 kbps. The faster this input clock is, the greater the resulting accuracy and the higher the possible bit rates at which the SLIC can send and receive. In LIN systems, the bit rates will not exceed 20 kbps; however, the SLIC module is capable of much higher speeds without any configuration changes, for cases such as high-speed downloads for reprogramming of FLASH memory or diagnostics in a test environment where radiated emissions requirements are not as stringent. In these situations, the user may choose to run faster than the 20 kbps limit which is imposed by the LIN specification for EMC reasons.
The SLIC clock is identical to the Bus clock of the selected cpu. -
Digital RX filter prescaler - Digital RX Filter Clock Prescaler. These bits configure the effective filter width for the digital receive filter circuit. The RXFP bits control the maximum number of SLIC clock counts required for the filter to change state, which determines the total maximum filter delay. Any pulse which is smaller than the maximum filter delay value will be rejected by the filter and ignored as noise. For this reason, the user must choose the prescaler value appropriately to ensure that all valid message traffic is able to pass the filter for the desired bit rate.
This item modifies the RXFP[2:0] bit in the SLCC2 register. -
Maximum filter delay - Maximum receive filter delay (for information only). The SLIC module provides a degree of low-pass filtering of the receive input. This filter delay value indicates that for a particular setup, only pulses of which are greater than the filter delay will pass the filter.
This item is influenced by the following properties: Digital RX filter prescaler -
UART Byte transfer mode - Byte transmit mode bypasses the normal LIN message framing and checksum monitoring and allows the user to send and receive single bytes in a method similar to a half-duplex UART. When enabled, this mode reads the bit time register (SLCBT) value and assumes this is the value corresponding to the number of SLIC clock counts for one bit time to establish the desired UART bit rate. The user software must initialize this register prior to sending or receiving data, based on the input clock selection, prescaler stage choice, and desired bit rate. BTM forces the data length in SLCDLC to one byte (DLC = 0x00) and disables the checksum circuitry so that CHKMOD has no effect. BTM sets up the SLIC module to send and receive one byte at a time, with 8-bit data, no parity, and one stop bit (8-N-1). This is the most commonly used setup for UART communications and should work for most applications. This is fixed in the SLIC and is not configurable.
This item modifies the BTM bit in the SLCC2 register.
The following items are available only if the group is enabled (the value is "Enabled"):
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Bit time register - Bit time value sets the number of SLIC clocks that equals one bit time in byte transfer mode. This item is enabled and valid only if the UART Byte transfer mode property is enabled.
This item modifies the SLCBTH and SLCBTL register. -
Baudrate - Baudrate (for information only).
This item is influenced by the following property: Bit time register .
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Bit time register - Bit time value sets the number of SLIC clocks that equals one bit time in byte transfer mode. This item is enabled and valid only if the UART Byte transfer mode property is enabled.
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SLIC clock - SLIC clock (for information only). The frequency of the SLIC clock must be between 2 MHz and 20 MHz, factoring in worst case possible numbers due to untrimmed process variations, as well as temperature and voltage variations in oscillator frequency. This will guarantee greater than 1.5% accuracy for all LIN messages from 1–20 kbps. The faster this input clock is, the greater the resulting accuracy and the higher the possible bit rates at which the SLIC can send and receive. In LIN systems, the bit rates will not exceed 20 kbps; however, the SLIC module is capable of much higher speeds without any configuration changes, for cases such as high-speed downloads for reprogramming of FLASH memory or diagnostics in a test environment where radiated emissions requirements are not as stringent. In these situations, the user may choose to run faster than the 20 kbps limit which is imposed by the LIN specification for EMC reasons.
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SLIC in Wait mode - Enable/Disable running of SLIC communication in Wait mode. This bit can only be written once out of reset state.
This item modifies the SLCWCM bit in the SLCC2 register. -
Bit error detection - This property allows to disable bit error detection circuitry. Bit error detection monitors the received bits to determine if they match the state of the corresponding transmitted bits. When bit error detection is enabled and a mismatch between transmitted bit and received bit is detected, a bit error is reported to the user through the SLCSV register and a SLIC interrupt is generated (if SLIC interruptis enabled).
This item modifies the BEDD bit in the SLCC1 register.
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Clock setting - Clock/timing settings of the module.
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Pins - Module pins/signals settings.
- RxD pin - Receiver input pin used for communication.
- RxD pin signal - Signal name of RxD pin.
- TxD pin - Transmitter output pin used for communication.
- TxD pin signal - Signal name of TxD pin.
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Interrupts - Interrupts settings of the module.
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SLIC interrupt - Interrupt settings.
- Interrupt - Interrupt vector (for information only).
- SLIC interrupt - Enable/Disable SLIC interrupt. This item modifies the SLCIE bit in the SLCC1 register.
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ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
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SLIC interrupt - Interrupt settings.
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Initialization - Initialization options of the module.
- Call Init method - The Init method of the component may be called after power-on or reset (in initialization code) by PE. yes - The Init method is called by PE. no - The Init method is not called by PE, it should be called in user's code.
- SLIC module - SLIC module enable. This item modifies the SLCE bit in the SLCC2 register.