Init_SCI
 
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Init Code Usage

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Component Init_SCI for RS08
Serial Communications Interface (SCI)
Component Level: Peripheral Initialization
Category: CPU Internal Peripherals-Peripheral Initialization
Properties:
(Properties are parameters of the component. Please see the Embedded Components page for more information.)
  • Component name - Name of the component.
  • Device - Selection of the SCI device module.
  • Settings - Common SCI module settings.
    • Clock settings - Clock/timing settings of the module.
      • Baud rate divisor - Baud rate divisor value used for setting SCI communication speed. The baud rate generator is disabled when this property is equal to 0.
        This item modifies SBR[12:0] bits in the SCIxBD register.
      • Settings only if SCI support baudrate fine adjust feature.
        • Baud rate fine adjust - This property sets the BRFA value for fine adjust of baud rate.
          Baud rate is figured: SCI baudrate = SCI module clock / (16 * (Baud rate divisor property value + (Baud rate fine adjust property value / 32)))
          This item modifies BRFA[4:0] bits in the SCIxC4 register.
      • Baud rate - Actual baud rate of the SCI device (for information only).
        This item is influenced by the following properties: Baud Rate divisor.
    • Loop mode - Enable/disable loop mode operation. In loop mode the transmitter output is internally connected to receiver input.
      This item modifies the LOOPS bit in the SCIxC1 register.
    • Receiver source - This setting has no meaning or effect unless the loop mode is enabled. When the loop mode is enabled the receiver input is internally connected to the TxD pin and this setting determines whether this connection is connected to the transmitter output (single-wire mode) or not (loop mode).
      This item modifies the RSRC bit in the SCIxC1 register.

      There are 2 options:
      • Loop mode: If loop mode is enabled, the loop mode selects internal loop back mode and the SCI does not use the RxD1 or TxD1 pins.
      • Single-wire mode: Single-wire SCI mode where the TxD1 pin is connected to the transmitter output and receiver input.

    • TxD pin direction - This property determines the direction of data at the TxD pin, if single-wire mode is set, see "Receiver source" property.
      This item modifies the TXDIR bit in the SCIxC3 register.
    • Data Format - This property determines whether SCI characters are eight or nine bits long.
      This item modifies the M bit in SCIxC1 register.
    • Stop in Wait mode - Enable/disable running of SCI communication in Wait mode.
      This item modifies the SCISWAI bit in the SCIxC1 register.
    • Wake up - Select the wake up condition of the SCI.
      This item modifies the WAKE bit in SCIxC1 register.
    • Idle character counting - The property determines when the receiver starts counting logic 1s as idle character bits.
      This item modifies the ILT bit in the SCIxC1 register.

      There are 2 options:
      • After start bit: Idle character bit count begins after start bit.
      • After stop bit: Idle character bit count begins after stop bit.

    • Settings supported for Freescale HCS08 AC, DE, DN, DV, DZ, EL, EN, FL, IB, IC, JE, JM, JS, LG, LH, LL, MM, MP, QB, QE, SC, SE, SG, SH and SV and RS08 and ColdFireV1 derivatives only.
      • Receive Wake Up Idle Detect - Select, whether the idle character that wakes up the receiver sets the IDLE bit.
        This item modifies the RWUID bit in the SCIxS2 register.

        There are 2 options:
        • Don't set IDLE bit: During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character.
        • Set IDLE bit: During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character.

    • Parity - Select the parity of the data bits.
      This item modifies the PT and PE bits in the SCIxC1 register.
    • Send break - Enable/disable send break. If the property is enabled, the transmitter continuously transmits break characters with no logic 1s.
      This item modifies the SBK bit in SCIxC2 register.
    • Receiver wakeup - This property places the SCI receiver in a standby state where it waits for automatic hardware detection of a selected wakeup condition.
      This item modifies the RWU bit in SCIxC2 register.

      There are 2 options:
      • Normal operation: Normal SCI receiver operation.
      • Standby mode: SCI receiver in standby waiting for wakeup condition.

    • Settings supported for Freescale HCS08 AC, AW, DE, DN, DV, DZ, EL, EN, FL, IB, IC, JE, JM, JS, LC, LG, LH, LL, MM, MP, QB, QE, QG, SC, SE, SG, SH and SV and RS08 and ColdFireV1 derivatives only.
      • Break character generation length - Select the length of the generated break character.
        This item modifies the BRK13 bit in SCIxS2 register.

        There are 2 options:
        • 10 or 11 bits: Break character is 10 bit times (11 if M=1)
        • 13 or 14 bits: Break character is 13 bit times (14 if M=1)

      • Transmitter output - Set the transmitter output Not inverted or Inverted to reverse the polarity of transmitted data.
        This item modifies the TXINV bit in SCIxC3 register.
    • Settings supported for Freescale HCS08 AC, DE, DN, DV, DZ, EL, EN, FL, IB, IC, JE, JM, JS, LG, LH, LL, MM, MP, QB, QE, SC, SE, SG, SH and SV and RS08 and ColdFireV1 derivatives only.
      • Receiver input - Set the receiver input Not inverted or Inverted to reverse the polarity of received data.
        This item modifies the RXINV bit in SCIxS2 register.
      • LIN Break detection - This property is used to select a longer break character detection length. While Enabled, framing error (FE) and receive data register full (RDRF) flags are prevented from setting.
        This item modifies the LBKDE bit in the SCIxS2 register.

        There are 2 options:
        • Disabled: Break character is detected at length of 10 bit times (11 if M = 1).
        • Enabled: Break character is detected at length of 11 bit times (12 if M = 1).

    • Settings only if SCI support TX modulation.
      • Modulate TX output - Enable/disable TX output modulation with the time base selected via TX modulation time base property.
        This item modifies the MODTXx bit in the SIMIPS2 register.
      • TX modulation time base - Select the source of TX modulation time base.
        This item modifies the MTBASEx bits in the SIMIPS2 register.
    • Settings only if SCI supports TX output drive strength boosting.
      • Tx output drive strength - Selects the TX output drive strength.
        This item modifies the SCIx_PAD bit in the SOPTn register.

        There are 2 options:
        • Single-pad drive strength: Normal pad drive strength.
        • Dual-pads bounding drive strength: Boost pad drive strength by connecting two pads together.

    • Settings only if SCI support the address match feature.
      • Match address settings - These properties have meaning, only if the address mark wakeup in the Wake up property is selected. Match address operation provides a means to ignore transmissions intended only for other receivers without interrupting the CPU to determine if the marked address is valid.
        • Match address 1 - This property enables/disables the match address 1 feature.
          This item modifies the MAEN1 bit in SCIxC4 register.
        • Match address 1 value - This property defines the hardware address 1 compare value. A frame received by the RX pin with a logic 1 in the most significant bit (msb) position is considered an address and is compared with the associated SCIxMA1 or SCIxMA2 register.
          The frame is only transferred to the receive buffer, and RDRF is set, if the comparison matches. All subsequent frames received with a logic 0 in the most significant bit positions are considered to be data associated with the address and are transferred to the receive buffer, and the RDRF flag is set.
          This item modifies the SCIxMA1 register.
        • Match address 2 - This property enables/disables the match address 2 feature.
          This item modifies the MAEN2 bit in SCIxC4 register.
        • Match address 2 value - This property defines the hardware address 2 compare value. A frame received by the RX pin with a logic 1 in the most significant bit (msb) position is considered an address and is compared with the associated SCIxMA1 or SCIxMA2 register.
          The frame is only transferred to the receive buffer, and RDRF is set, if the comparison matches. All subsequent frames received with a logic 0 in the most significant bit positions are considered to be data associated with the address and are transferred to the receive buffer, and the RDRF flag is set.
          This item modifies the SCIxMA2 register.
  • Pins - Module pins/signals settings.
    • RxD pin allocation - Enable/disable allocation of the RxD pin. Allocated pin is exclusively used by this peripheral and cannot be used by any other device.
      The following items are available only if the group is enabled (the value is "Enabled"):
    • TxD pin allocation - Enable/disable allocation of the TxD pin. Allocated pin is exclusively used by this peripheral and cannot be used by any other device.
      The following items are available only if the group is enabled (the value is "Enabled"):
    • Settings only if SCI support Fixed/Mixed mode.
      • Mixed mode - Switches between fixed/mixed mode.
        This item modifies the SCIMS bit in SOPTn register.
        Pins selected above is used for SCI channel selection and modifies the SCICS bit in SOPTn register.
        The following items are available only if the group is enabled (the value is "Enabled"):
        • RxD pin allocation - Enable/disable allocation of the RxD pin. Allocated pin is exclusively used by this peripheral and cannot be used by any other device.
          The following items are available only if the group is enabled (the value is "Enabled"):
        • TxD pin allocation - Enable/disable allocation of the TxD pin. Allocated pin is exclusively used by this peripheral and cannot be used by any other device.
          The following items are available only if the group is enabled (the value is "Enabled"):
  • Interrupts/DMA - Interrupt/DMA settings of the module.
    • Settings only if SCI support OR interrupt.
      • OR interrupt - OR interrupt settings
        • Settings only if CPU supports interrupts
          • Interrupt - Interrupt vector (for information only)
          • Settings only if CPU supports interrup priority.
        • OR interrupt - Enable/disable OR interrupt.
          This interrupt replace all 3 SCI interrupts, this is made for set all SCI device on the same interrupt level of priority.
          This item modifies the SCIxDO bit in the INTC_ORMR register.
        • Settings only if CPU supports interrupts
          • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
            The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
    • Tx interrupt - Tx interrupt settings
      • Settings only if CPU supports interrupts
        • Interrupt - Interrupt vector (for information only)
        • Settings only if CPU supports interrup priority.
      • Transmit request - Enable/disable SCI Transmitter interrupt request or DMA request if supported.
        This item modifies the TIE bit in the SCIxC2 register.
      • Settings only if SCI support DMA request from transmitter.
        • Transmit request type - Switch request type between interrupt and DMA. Transmit request property must be also enabled to generate request.
          This item modifies the TDMAS bit in the SCIxC5 register.

          There are 2 options:
          • interrupt: TDRE flag generates interrupt requests
          • DMA: TDRE flag generates DMA requests

      • Transmission complete interrupt - Enable/disable SCI Transmission complete interrupt.
        This item modifies the TCIE bit in the SCIxC2 register.
      • Settings only if CPU supports interrupts
        • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
          The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
    • Rx interrupt - Rx interrupt settings
      • Settings only if CPU supports interrupts
        • Interrupt - Interrupt vector (for information only)
        • Settings only if CPU supports interrup priority.
      • Receive request - Enable/disable SCI Receive interrupt request or DMA request if supported.
        This item modifies the RIE bit in the SCIxC2 register.
      • Settings only if SCI support DMA request from receiver.
        • Receive request type - Switch request type between interrupt and DMA. Receive request property must be also enabled to generate request.
          This item modifies the RDMAS bit in the SCIxC5 register.

          There are 2 options:
          • interrupt: RDRF flag generates interrupt requests
          • DMA: RDRF flag generates DMA requests

      • Idle line interrupt - Enable/disable SCI Idle line interrupt.
        This item modifies the ILIE bit in the SCIxC2 register.
      • Settings supported for Freescale HCS08 AC, DE, DN, DV, DZ, EL, EN, FL, IB, IC, JE, JM, JS, LG, LH, LL, MM, MP, QB, QE, SC, SE, SG, SH and SV and RS08 and ColdFireV1 derivatives only.
        • LIN Break detect interrupt - Enable/disable SCI LIN Break detect interrupt.
          This item modifies the LBKDIE bit in the SCIxBDH register.
        • Input active edge interrupt - Enable/disable SCI RxD Input Active Edge interrupt.
          This item modifies the RXEDGIE bit in the SCIxBDH register.
      • Settings only if CPU supports interrupts
        • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
          The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
    • Error interrupt - Error interrupt group
      • Settings only if CPU supports interrupts
        • Interrupt - Interrupt vector (for information only)
        • Settings only if CPU supports interrup priority.
      • Receive framing error interrupt - Enable/disable SCI Receive framing interrupt.
        This item modifies the FEIE bit in the SCIxC3 register.
      • Receive noise error interrupt - Enable/disable SCI Receive noise error interrupt.
        This item modifies the NEIE bit in the SCIxC3 register.
      • Receive overrun interrupt - Enable/disable SCI Receive overrun interrupt.
        This item modifies the ORIE bit in the SCIxC3 register.
      • Receive parity error interrupt - Enable/disable SCI Receive parity error interrupt.
        This item modifies the PEIE bit in the SCIxC3 register.
      • Settings only if CPU supports interrupts
        • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
          The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
  • Initialization - Initialization options of the module.
    • Call Init method - The Init method of the component may be called after a power-on or reset (in initialization code) by PE.
      yes - The Init method is called by PE
      no - The Init method is not called by PE, it should be called in the user's code
    • Transmitter - SCI transmitter enable.
      This item modifies the TE bit in the SCIxC2 register.
    • Receiver - SCI receiver enable.
      This item modifies the RE bit in the SCIxC2 register.

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