Component documentation

Device - Selection of the SCI module device.
Settings - Common SCI module settings.
- Clock settings - Clock/timing settings of the module.
  - Setting supported for Freescale HC08 LJ12, LK24 and AP64 derivatives only.
    - Baud clock input - Select the source clock for the baud rate generator.
      This item modifies the CKS bit in SCBR register for infrared SCI module and the SCIBDSRC bit in CONFIG2 register for SCI module.
      
      There are 2 options:
      - CGMXCLK: CGMXCLK used as clock source for ESCI.
      - Bus clock: Internal data bus clock used as clock source for ESCI.
  - Setting supported for Freescale HC08 GP32, GR8, KX2, KX8 and SR12 derivatives only.
    - Baud clock input - Select the source clock for the baud rate generator.
      This item modifies the SCIBDSRC bit in the CONFIG2 register.
      
      There are 2 options:
      - CGMXCLK: CGMXCLK used as clock source for ESCI.
      - Bus clock: Internal data bus clock used as clock source for ESCI.
  - Settings supported for Freescale HC08 EY16, EY16A, GR16, GR16A, GR32A, GR60A, GT16, GZ16, GZ32, GZ60, QB8 and QC16 derivatives only.
    - Settings supported for Freescale HC08 EY16, EY16A, GR16, GR16A, GR32A, GR60A, GZ16, GZ32, GZ60, QB8 and QC16 derivatives only.
      - ESCI baud rate clock source - Select the clock source used for the ESCI.
        This item modifies the ESCIBDSRC bit in the CONFIG2 register.
        
        There are 2 options:
        
        CGMXCLK: CGMXCLK used as clock source for ESCI.
        
        Bus clock: Internal data bus clock used as clock source for ESCI.
    - Prescaler divisor - Select the prescaler divisor.
      This item modifies the PDS[2:0] bits in the SCPSC register.
    - Prescaler divisor fine adjust - Select the number of the clocks inserted in each 32 output cycle frame to achieve more timing resolution on average prescaler frequency.
      This item modifies the PSSB[4:0] bits in the SCPSC register.
  - Baud rate prescaler - Select the baud rate register prescaler divisor.
    This item modifies the SCP[1:0] bits in the SCBR register.
  - Baud rate divisor - Select the ESCI/SCI/IRSCI baud rate divisor.
    This item modifies the SCR[2:0] bits in the SCBR register.
  - Baud rate - Actual baud rate of the SCI device (for information only).
    This item is influenced by the following properties (if they are present for the selected CPU): Baud clock input, ESCI baud rate clock source, Baud rate prescaler, Baud rate divisor, Prescaler divisor and Prescaler divisor fine adjust.
- Loop Mode - Enable/disable loop mode operation. In loop mode the RxD pin is disconnected from the SCI and the transmitter output goes into the receiver input.
  This item modifies the LOOPS bit in the SCC1 register.
- Data Format - This property determines whether ESCI/SCI/IRSCI characters are eight or nine bits long.
  This item modifies the M bit in the SCC1 register.
- Settings for Freescale HC08 EY16, EY16A, GR16, GR16A, GR32A, GR60A, GT16, GZ16, GZ32, GZ60, QB8 and QC16 derivatives.
  - LIN break symbol receive - Select the enhanced ESCI features for slave nodes in the local interconnect network (LIN) protocol.
    This item modifies the LINR bit in the SCBR register.
    
    There are 2 options:
    - Normal ESCI functionality: Normal ESCI functionality.
    - 11/12-bit break detect: 11/12-bit break detect enabled for LIN receiver. The value of this item is influenced by the following properties: Data Format, bit M
  - Settings for Freescale HC08 EY16A, GR16, GR16A, GR32A, GR60A, GZ16, GZ32, GZ60, QB8 and QC16 derivatives.
    - LIN break symbol transmit - Select the enhanced ESCI features for master nodes in the local interconnect network (LIN) protocol.
      This item modifies the LINT bit in the SCBR register.
      
      There are 2 options:
      - Normal ESCI functionality: Normal ESCI functionality
      - 13-bit generation enabled: 13-bit generation enabled for LIN transmitter.
  - Arbiter mode - Select the mode of the arbiter module.
    This item modifies the AM1 and AM0 bits in the SCIACTL register.
  - Arbiter counter - Select the arbiter counter clock source.
    This item modifies the ACLK bit in the SCIACTL register.
    
    There are 2 options:
    - Bus clock div. 4: Arbiter counter is clocked with the bus clock divided by four.
    - 1/2 of ESCI input clock: Arbiter counter is clocked with one half of the ESCI input clock generated by the ESCI prescaler.
- Wake up - This property determines which condition wakes up the ESCI/SCI/IRSCI.
  This item modifies the WAKE bit in the SCC1 register.
  
  There are 2 options:
  - Idle line wakeup: An idle condition on the RxD pin
  - Address mark wakeup: A 1 (address mark) in the MSB position of a received character
- Idle character counting - This property determines when the SCI starts counting logic 1s as idle character bits.
  This item modifies the ILTY bit in the SCC1 register.
  
  There are 2 options:
  - After start bit: Idle character bit count begins after start bit.
  - After stop bit: Idle character bit count begins after stop bit.
- Parity - Enable the ESCI/SCI/IRSCI parity function and select which parity will be used.
  This item modifies the PEN and PTY bits in the SCC1 register.
- Send break - Enable/disable send break. If enabled the transmitter continuously transmits break characters with no logic 1s.
  This item modifies the SBK bit in the SCC2 register.
- Receiver wake up mode - This property puts the receiver in a standby state during which receiver interrupts are disabled.
  This item modifies the RWU bit in the SCC2 register.
- Settings not supported for Freescale HC08 LJ12 and LK24 derivatives.
  - Transmitter output - Set transmitter output Not inverted or Inverted to reverse the polarity of transmitted data.
    Note: setting is not available for infrared SCI module.
    This item modifies the TXINV bit in the SCC1 register.
- Setting supported for LJ12, LK24 and AP64 derivatives only.
  - Transmitter narrow pulse - Select the infrared transmitter narrow pulse width.
    This item modifies the TNP1 and TNP0 bits in the SCIRCR register.
- Setting supported for Freescale HC08 EY16A derivative only.
  - Slew Rate Control - The property enables or disables slew rate control for TxD.
    This item modifies the ESCISRE bit in the CONFIG3 register.
Pins - Module pins/signals settings
- Settings not supported for Freescale MC68HC908JB12 (20 pin package) derivative.
  - RxD pin - Receiver input pin used for communication.
- TxD pin - Transmitter input pin used for communication.
Interrupts - Interrupts settings of the module.
- Tx interrupt - Tx interrupt settings
  - Interrupt - Interrupt vector (for information only)
  - Transmit interrupt - Enable/disable SCI Transmitter interrupt.
    This item modifies the SCTIE bit in the SCC2 register.
  - Transmission complete interrupt - Enable/disable SCI Transmission complete interrupt.
    This item modifies the TCIE bit in the SCC2 register.
  - ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
    The user code of the routine should handle all respective interrupt flags correctly.
- Rx interrupt - Rx interrupt settings
  - Interrupt - Interrupt vector (for information only)
  - Receive interrupt - Enable/disable SCI Receive interrupt.
    This item modifies the SCRIE bit in the SCC2 register.
  - Idle line interrupt - Enable/disable SCI Idle line interrupt.
    This item modifies the ILIE bit in the SCC2 register.
  - ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
    The user code of the routine should handle all respective interrupt flags correctly.
- Error interrupt - Error interrupt settings
  - Interrupt - Interrupt vector (for information only)
  - Receive framing error interrupt - Enable/disable SCI Receive framing interrupt.
    This item modifies the FEIE bit in the SCC3 register.
  - Receive noise error interrupt - Enable/disable SCI Receive noise error interrupt.
    This item modifies the NEIE bit in the SCC3 register.
  - Receive overrun interrupt - Enable/disable SCI Receive overrun interrupt.
    This item modifies the ORIE bit in the SCC3 register.
  - Receive parity error interrupt - Enable/disable SCI Receive parity error interrupt.
    This item modifies the PEIE bit in the SCC3 register.
  - ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
    The user code of the routine should handle all respective interrupt flags correctly.
Initialization - Initialization option of the module.
- SCI enable - Select yes to enable the SCI module and the SCI baud rate generator.
  This item modifies the ENSCI bit in SCC1 register.
- Transmitter enable - Select yes to enable SCI transmitter.
  This item modifies the TE bit in the SCC2 register.
- Receiver enable - Select yes to enable SCI receiver.
  This item modifies the RE bit in the SCC2 register.
- Settings for LJ12, LK24 and AP64 derivatives.
  - IR enable - Select yes to enable the infrared sub-module for encoding and decoding the SCI data stream (property available only for infrared SCI module).
    This item modifies IREN bit in the IRSCIRCR register.

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