Init_MSCAN
 
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Init Code Usage

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Component Init_MSCAN for HCS08
Motorola Scalable Controller Area Network (MSCAN)
Component Level: Peripheral Initialization
Category: CPU Internal Peripherals-Peripheral Initialization
Properties:
(Properties are parameters of the component. Please see the Embedded Components page for more information.)
  • Component name - Name of the component.
  • Device - Selection of the CAN communication device module.
  • Settings - Common MSCAN module settings.
    • Clock settings - Clock/timing settings of the module.
      • Clock Source - This item defines the clock source for the MSCAN module.
        This item modifies the CLKSRC bit in the CANCTL1 register.

        There are 2 options:
        • Oscillator Clock: The MSCAN clock source is the Oscillator Clock.
        • Bus Clock: The MSCAN clock source is the Bus Clock.

      • Baud Rate Prescaler - This item determines the time quanta (Tq) clock that is used to build up the individual bit timing.
        This item modifies BRP[5:0] bits in the CANBTR0 register.
      • Synchr. Jump Width - The synchronization jump width defines the maximum number of time quanta (Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the bus.
        This item modifies SJW0 and SJW1 bits in the CANBTR0 register.
      • Sampling - This item determines the number of samples of the serial bus to be taken per bit time.
        This item modifies the SAMP bit in the CANBTR1 register.

        There are 2 options:
        • Three samples per bit: If set, three samples per bit are taken; the regular one (sample point) and two preceding samples using a majority rule.
        • One sample per bit: Only one sample is taken per bit - recommended for higher bit rates.

      • Time Segment 1 - Time segments within the bit time fix the number of clock cycles per bit time and the location of the sample point (in time quanta clock cycles).
        This item modifies TSEG1[3:0] bits in the CANBTR1 register.
      • Time Segment 2 - Time segments within the bit time fix the number of clock cycles per bit time and the location of the sample point (in time quanta clock cycles).
        This item modifies TSEG2[2:0] bits in the CANBTR1 register.
      • CAN frequency - CAN module frequency. This item is influenced by the following properties: Baud Rate Prescaler, Clock source. For information only.
      • Time quantum - Time quantum value. This item is influenced by the following properties:Baud Rate Prescaler, Clock source. For information only.
      • Bit rate - Communication bit rate. This item is influenced by the following properties:Baud Rate Prescaler, Time Segment 1, Time Segment 2, Clock source. For information only.
    • CAN Stops in Wait Mode - Enabling of the bit allows lower power consumption in Wait Mode by disabling all the clocks at the bus interface to the MSCAN module.
      This item modifies the CSWAI bit in the CANCTL0 register.
    • Wake-Up Mode - This item allows the MSCAN to restart from Sleep Mode when traffic on CAN is detected. This item also defines whether the integrated low-pass filter is applied to protect the MSCAN from spurious wake-up.
      This item modifies the WUPE bit in the CANCTL0 register and the WUPM bit in the CANCTL1 register.

      There are 3 options:
      • None: Wake-Up disabled - The MSCAN ignores traffic on CAN.
      • On dominant pulse (length Twup): MSCAN wakes-up the CPU only in case of a dominant pulse on the bus which has a length of Twup.
      • On any recessive to dominant edge: MSCAN wakes-up the CPU after any recessive to dominant edge on the CAN bus.

    • Loop Back Test Mode - When this item is set, the MSCAN performs an internal loop back which can be used for self test operation.
      This item modifies the LOOPB bit in the CANCTL1 register.
    • Listen Only Mode - This item configures the MSCAN as a bus monitor.
      This item modifies the LISTEN bit in the CANCTL1 register.

      There are 2 options:
      • Normal operation: Normal operation
      • Activated: When the bit is set, all valid CAN messages with matching ID are received, but no acknowledgement or error frames are sent out.

    • Sleep Mode Request - This item requests the MSCAN to enter Sleep Mode, which is an internal power saving mode.
      This item modifies the SLPRQ bit in the CANCTL0 register.
    • Time Stamp - This item activates an internal 16-bit free running timer that is clocked by the bit clock (for 16-bit time stamp).
      This item modifies the TIME bit in the CANCTL0 register.
    • Bus-off recovery mode - The property configures the bus-off state recovery mode.
      This item modifies the BORM bit in the CANCTL1 register.

      There are 2 options:
      • Automatic: Automatic bus-off recovery
      • User: Bus-off recovery upon user request

    • Acceptance mode - This item defines the identifier acceptance filter organization.
      This item modifies IDAM0 and IDAM1 bits in the CANIDAC register.
    • Rx acceptance ID(1st bank) - Specifies which of the corresponding bits in the receiver acceptance ID are relevant for acceptance filtering.
      This item modifies all bits in the CANIDAR0 register up to CANIDAR3 register.
    • Rx acceptance ID(2nd bank) - Specifies which of the corresponding bits in the receiver acceptance ID are relevant for acceptance filtering.
      This item modifies all bits in the CANIDAR4 register up to CANIDAR7 register.
    • Rx acceptance ID mask (1st bank) - On reception, the frame is only accepted to read by CPU if it passes the criteria in the receiver acceptance ID and the receiver acceptance ID mask.
      This item modifies all bits in the CANIDMR0 register up to CANIDMR3 register.
    • Rx acceptance ID mask (2nd bank) - On reception, the frame is only accepted to read by CPU if it passes the criteria in the receiver acceptance ID and the receiver acceptance ID mask.
      This item modifies all bits in the CANIDMR4 register up to CANIDMR7 register.
  • Pins - Module pins/signals settings
    • RXCAN pin - Settings related to RX pin of the CAN channel.
      • RXCAN pin - Receiver input pin used for communication. Pin selection may modify the MODRR register.
      • RXCAN pin signal - Signal name of RXCAN pin.
    • TXCAN pin - Settings related to TX pin of the CAN channel.
      • TXCAN pin - Transmitter output pin used for communication. Pin selection may modify the MODRR register.
      • TXCAN pin signal - Signal name of RXCAN pin.
  • Interrupts - Interrupts settings of the module.
    • Wake up - Wake up interrupt settings.
      • Wake up interrupt - Wake up interrupt enable.
        This item modifies the WUPIE bit in the CANRIER register.
      • Interrupt - Interrupt vector (for information only).
      • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
        Note: The routine must handle all interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
    • Error - Selected Error interrupt settings.
      • Error Interrupt - Interrupt vector (for information only).
      • Status Change Interrupt - Status Change interrupt enable.
        This item modifies the CSCIE bit in the CANRIER register.
      • Receiver Status Change - This item controls the sensitivity level in which receiver state changes are causing CSCIF interrupts.
        This item modifies RSTATE[1:0] bits in the CANRIER register.

        There are 4 options:
        • do not generate: Do not generate any CSCIF interrupt caused by receiver state changes.
        • On ' Bus-Off ' state: Generate CSCIF interrupt only if the receiver enters or leaves "Bus-Off" state. Discard other receiver state changes for generating CSCIF interrupt.
        • On "RxErr" or "Bus-Off" state: Generate CSCIF interrupt only if the receiver enters or leaves "RxErr" or "Bus-Off" state. Discard other receiver state changes for generating CSCIF interrupt.
        • On all state changes: Generate CSCIF interrupt on all state changes.

      • Transmitter Status Change - This item controls the sensitivity level in which transmitter state changes are causing CSCIF interrupts.
        This item modifies TSTATE[1:0] bits in the CANRIER register.

        There are 4 options:
        • do not generate: Do not generate any CSCIF interrupt caused by transmitter state changes.
        • On "Bus-Off" state: Generate CSCIF interrupt only if the transmitter enters or leaves "Bus-Off" state. Discard other transmitter state changes for generating CSCIF interrupt.
        • On "TxErr" or "Bus-Off" state: Generate CSCIF interrupt only if the transmitter enters or leaves "TxErr" or "Bus-Off" state. Discard other transmitter state changes for generating CSCIF interrupt.
        • On all state changes: Generate CSCIF interrupt on all state changes.

      • Overrun Interrupt - Overrun Interrupt enable.
        This item modifies the OVRIE bit in the CANRIER register.
      • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
        Note: The routine must handle all interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
    • Receiver Full - Receiver Full interrupt settings.
      • Receiver Full - Receiver Full interrupt enable.
        This item modifies the RXFIE bit in the CANRIER register.
      • Receiver Interrupt - Interrupt vector (for information only).
      • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
        Note: The routine must handle all interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
    • Transmitter empty - Selected Transmitter empty interrupt settings.
      • Transmitter Interrupt - Interrupt vector (for information only).
      • Tx Empty Interrupt 0 - Transmitter Empty Interrupt 0 Enable.
        This item modifies the TXEIE0 bit in the CANTIER register.
      • Tx Empty Interrupt 1 - Transmitter Empty Interrupt 1 Enable.
        This item modifies the TXEIE1 bit in the CANTIER register.
      • Tx Empty Interrupt 2 - Transmitter Empty Interrupt 2 Enable.
        This item modifies the TXEIE2 bit in the CANTIER register.
      • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
        Note: The routine must handle all interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
  • Initialization - Initialization options of the module.
    • Call Init method - The Init method of the component may be called after power-on or reset (in initialization code) by PE.
      yes - The Init method is called by PE.
      no - The Init method is not called by PE, it should be called in user's code.
    • CAN Enable - CAN Enable.
      This item modifies the CANE bit in the CANCTL1 register.
    • Initial status - Initialization mode request. CAN module will stay in this status after initialization completition.
      This item modifies the INITRQ bit in the CANCTL0 register.

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