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Component
Init_MSCAN for HC08
Motorola Scalable Controller Area Network (MSCAN)
Properties:
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Component name - Name of the component.
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Device - Selection of the MSCAN device module.
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Settings - Common MSCAN module settings.
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Clock settings - Clock/timing settings of the module.
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Clock source - The property selects MSCAN Clock Source. CGMOUT clock source equals to bus clock * 2. CGMXCLK/2 clock source equals to oscillator clock/2.
This item modifies the CLKSRC bit in the CMCR1 register.
There are 2 options:
- CGMXCLK/2: Oscilator clock/2
- CGMOUT: Bus clock * 2
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Baud rate prescaler - The property determines the time quanta (Tq) clock, which is used to build the individual bit timing.
This item modifies the BRP[5:0] bits in CBTR0 register.
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Sync jump width - The property defines the maximum number of time quanta (Tq) clock cycles by which a bit may be shortened, or lengthened, to achieve resynchronization on data transitions on the bus.
This item modifies the SJW[1:0] bits in CBTR0 register.
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Sampling - The property determines the number of serial bus samples to be taken per bit time.
This item modifies the SAMP bit in CBTR1 register.
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Time Segment 1 - Time segments within the bit time fix the number of clock cycles per bit time and the location of the sample point ( in time quanta clock cycles.).
This item modifies TSEG1[3:0] bits in the CBTR1 register.
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Time Segment 2 - Time segments within the bit time fix the number of clock cycles per bit time and the location of the sample point ( in time quanta clock cycles.).
This item modifies TSEG2[2:0] bits in the CBTR1 register.
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CAN input clock frequency - CAN module input clock frequency (for information only).
This item is influenced by the following properties: Baud rate prescaler, Clock source.
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Time quantum - Duration of one Time quantum (for information only). Number of time quanta per bit is given by the equation (TimeSegment1+TimeSegment2+1)
This item is influenced by the following properties: Baud rate prescaler, Clock source.
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Bit rate - Communication bit rate (for information only). Number of time quanta per bit is given by the equation (TimeSegment1+TimeSegment2+1)
This item is influenced by the following properties: Baud rate prescaler, Clock source, Time segment 1, Time segment 2.
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Timer connected - The property is used to establish a link between the MSCAN and the on-chip timer.
This item modifies the TLNKEN bit in CMCR0 register.
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Loop back self-test - When the property is set, MSCAN performs internal loop back, which can be used for self-test operation. The bit stream output of the transmitter is fed back to the receiver internally,
This item modifies the LOOPB bit in CMCR1 register.
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Wakeup mode - The property defines whether the integrated low-pass filter is applied to protect the MSCAN from spurious wakeups.
This item modifies the WUPM bit in CMCR1 register.
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Acceptance mode - The property defines the identifier acceptance filter organization.
This item modifies the IDAM[1:0] bits in CIDAC register.
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Rx acceptance ID - On reception, the frame is only accepted to read by CPU if it passes the criteria in the receiver acceptance ID. The property specifies the value of IDR register that should pass the acceptance filter. The value will be written to the acceptance code registers CIDAR0-CIDAR3 after a reset. The most significant byte of the acceptance code will be written to the CIDAR0 register and the least significant byte of the acceptance code will be written to the CIDAR3 register.
This item modifies all bits in the CIDAR3 to CIDAR0 registers.
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Rx acceptance ID mask - Specifies which of the corresponding bits in the receiver acceptance ID are relevant for acceptance filtering.
This mask will be written to the acceptance mask registers CIDMR0-CIDMR3 after a reset. The most significant byte of the acceptance mask will be written to the CIDMR0 register and the least significant byte of the acceptance mask will be written to the CIDMR3 register.
This item modifies all bits in the CIDMR0 register up to CIDMR3 register.
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Pins - Module pins/signals settings.
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Interrupts - Interrupts settings of the module.
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Wake Up - Wake-up interrupt settings.
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Interrupt - Interrupt vector (for information only).
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Wakeup interrupt - Enable/disable Wake up interrupt.
This item modifies the WUPIE bit in the CRIER register.
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ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
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Error - Common Error interrupt settings.
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Interrupt - Interrupt vector (for information only).
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Receiver warning interrupt - Enable/disable Receiver Warning interrupt.
This item modifies the RWRNIE bit in the CRIER register.
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Transmitter warning interrupt - Enable/disable Transmitter Warning interrupt.
This item modifies the TWRNIE bit in the CRIER register.
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Receive error passive interrupt - Enable/disable Receive Error Passive interrupt.
This item modifies the RERRIE bit in the CRIER register.
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Transmitter error passive interrupt - Enable/disable Transmitter Error Passive interrupt.
This item modifies the TERRIE bit in the CRIER register.
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Bus-Off interrupt - Enable/disable Bus-Off interrupt.
This item modifies the BOFFIE bit in the CRIER register.
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Overrun interrupt - Enable/disable Overrun interrupt.
This item modifies the OVRIE bit in the CRIER register.
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ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
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Transmitter empty - Transmitter empty interrupt settings.
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Interrupt - Interrupt vector (for information only).
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Tx empty interrupt 0 - Enable/disable Transmitter Empty interrupt 0.
This item modifies the TXEIE0 bit in the CTCR register.
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Tx empty interrupt 1 - Enable/disable Transmitter Empty interrupt 1.
This item modifies the TXEIE1 bit in the CTCR register.
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Tx empty interrupt 2 - Enable/disable Transmitter Empty interrupt 2.
This item modifies the TXEIE2 bit in the CTCR register.
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ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
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Receiver Full - Receiver Full interrupt settings.
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Interrupt - Interrupt vector (for information only).
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Receiver interrupt - Enable/disable Receiver Full interrupt.
This item modifies the RXFIE bit in the CRIER register.
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ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
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Initialization - Initialization options of the module.
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Call Init method - The Init method of the component may be called after power-on or reset (in initialization code) by PE.
yes - The Init method is called by PE
no - The Init method is not called by PE, it should be called in user's code.
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Initial status - The property requests the MSCAN to go into operational mode and synchronize to the CAN bus.
This item modifies the SFTRES bit in CMCR0 register.
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