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Component
Init_IIC for RS08
Inter-IC Bus (IIC)
Properties:
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Component name - Name of the component.
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Device - Selection of the IIC device module.
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Settings - Common IIC module settings.
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Clock settings - Clock/timing settings of the module.
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Multiplier Factor - The property selects the multiplier factor mul. This factor is used along with the SCL divider to generate the IIC baud rate.
This item modifies MULT[1:0] bits in the IICF register.
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Clock rate - The property selects SCL divider and the SDA hold value..
This item modifies ICR[5:0] bits in the IICF register.
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SCL frequency - IIC baud rate (for information only).
This item is influenced by the following properties:Multiplier factor, Clock rate.
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SDA Hold - SDA hold (for information only).
This item is influenced by the following properties:Multiplier factor, Clock rate.
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Settings only if IIC supports Slave baudrate control.
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Slave baud rate control - If enabled, slave baud rate is independent from Mater baud rate. This will force clock stretching on SCL line on very fast IIC modes.
This item modifies SBRC bit in the IICC2 register.
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Settings only if IIC supports 10. bit addressing mode and general call.
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General call address - The property enables general call address reception. Enabling this property is available only if IIC module supports general call address.
This item modifies the GCAEN bit in the IICC2 register (only if the IIC module supports this feature and contains this register).
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Address mode - The property controls number of bits used for the slave address. 10-bit addressing enabled only if supported by the IIC module.
This item modifies ADEXT bit in the IICC2 register (only if the IIC module supports this feature and contains this register).
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Address - The property selects specific slave address to be used by the IIC module. This is the address the module will respond to when addressed as a slave.
This item modifies AD[7:1] (ADDR[7:1) on some derivatives] bits in the IICA register (IICA1 on some derivatives) and if 10-bit addressing is used this item also modifies AD[10:8] bits (ADDR[10:8) on some derivatives] in the IICC2 register.
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Transfer direction - The property selects transfer direction.
This item modifies TX bit in the IICC (IICC1 on some derivatives) register.
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Transmit Acknowledge - The property specifies whether an acknowledge signal will be sent out to the bus after receiving one data byte for both master and slave receivers.
This item modifies TXAK bit in the IICC (IICC1 on some derivatives) register.
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Settings only if CPU support DMA.
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Settings only if IIC supports Wakeup from stop mode.
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Wake-up - The module can wake-up from low power mode.
This item modifies WUEN bit in the IICC1 register.
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Settings only if IIC supports Glitch filter feature
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Noise (glitch) filter factor - The value controls the width of the glitch (in multiples of 1/2 of bus clock cycle) the filter should absorb. This item modifies IICFLT register.
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Settings only if IIC support SMBus features.
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Fast acknowledge - If enabled, user is able to issue an ACK or NACK according to the result of received byte. Writing 0 to TXAK after receiving a data byte will generate ACK, writing 1 to TXAK will generate NACK. If this property is disabled, ACK or NACK will be send out on following receiving data byte. This item modifies FACK bit in IICSMB register.
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Alert response address - If enabled, SMBus alert response address will address the deviceas well. This item modifies ALERTEN bit in IICSMB register.
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Second address - Enables second address matching (default address). This item modifies SIICAEN bit in IICSMB register.
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Second address value - Second slave address used by the SMBus. This Item modifies IICA2 register.
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SCL low Timeout counter clock select - Selects clock source of Timeou counter. This item modifies TCKSEL bit in IICSMB register.
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SCL low Timeout counter - The value determimes the timeout period of SCL in low state. This item modifies IICSLTH and IICSLTL registers.
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SCL low Timeout - SCL low timeout value (for information only). The value is affected by SCL low Timeout counter and SCL low Timeout counter clock select.
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Pins - Module pins/signals settings.
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SDA pin - Bidirectional Serial Data line (SDA).
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SDA pin signal - Signal name of SDA pin.
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SCL pin - Bidirectional Serial Clock Line (SCL).
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SCL pin signal - Signal name of SCL pin.
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Settings only if IIC supports High drive select on the PAD.
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High drive select - The setting controls High drive capability of the PAD.
This item modifies HDRS bit in the IICC2 register.
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Interrupts - Interrupts settings of module.
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Settings only if CPU supports interrupts.
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Interrupt - Interrupt vector (for information only)
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Settings only if interrupt support priority setting.
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IIC interrupt - Enable/Disable IIC interrupt.
This item modifies IICIE bit in the IICC (IICC1 on some derivatives) register.
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Settings only if IIC supports SDA low timeout feature.
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SDA low, SCL high timeout interrupt - Enable/Disable interrupt for SCL high and SDA low timeout. "IIC interrupt" property must be enabled as well.
This item modifies SHTF2IE bit in the IICSMB register.
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Settings only if CPU supports interrupts.
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ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
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Initialization - Initialization options of the module.
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Call Init method - The Init method of the component may be called after power-on or reset (in initialization code) by PE.
yes - The Init method is called by PE
no - The Init method is not called by PE, it should be called in user's code
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Module Enable - The property enables/disables IIC module.
This item modifies IICEN bit in the IICC register (IICC1 on some derivatives).
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