Init_FEC
 
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Component Init_FEC for COLDFIREV1
Fast Ethernet Controller (FEC)
Component Level: Peripheral Initialization
Category: CPU Internal Peripherals-Peripheral Initialization
Properties:
(Properties are parameters of the component. Please see the Embedded Components page for more information.)
  • Component name - Name of the component.
  • Device - FEC Device module
  • Settings - Common FEC module settings.
    • Clock settings - Clock/timing settings of the module.
      • MII speed divisor - Specifies MII speed divisor value that controls the MII management interface clock (FEC_MDC) relative to the system clock.
      • MII clock frequency - Expected MII clock frequency (for information only). This item is influenced by the MII speed divisor property.
        The value is calculated using the formula:
        Clock frequency = Internal FEC clock source frequency * (1 / (MII speed divisor * 2)).
        Note:Internal FEC clock source = MCGOUT
    • Address settings - Address recognition settings of the module.
      • Physical address (high) - Specifies the high part (bytes 4 and 5) of the 48-bit individual address used in the address recognition process to compare with destination address (DA) field of the received frames with an individual DA. In addition this address is used in bytes 4 through 5 of the 6-byte source address field when transmitting PAUSE frames.
      • Physical address (low) - Specifies the low part (bytes 0, 1, 2 and 3) of the 48-bit individual address used in the address recognition process to compare with destination address (DA) field of the received frames with and individual DA. In addition this address is used in bytes 0 through 3 of the 6-byte source address field when transmitting PAUSE frames.
      • Unicast address hash (high) - Specifies the high part of the 64-bit individual address hash table used in the address recognition process to check for possible match with unicast address (DA field of received frames) with and individual DA.
        Bit 31 of this value contains hash index bit 63, bit 0 contains hash index bit 32.
      • Unicast address hash (low) - Specifies the low part of the 64-bit individual address hash table used in the address recognition process to check for possible match with unicast address (DA field of received frames) with and individual DA.
        Bit 31 of this value contains hash index bit 31, bit 0 contains hash index bit 0.
      • Multicast address hash (high) - Specifies the high part of the 64-bit group address hash table used in the address recognition process to check for possible match with multicast address (DA field of received frames).
        Bit 31 of this value contains hash index bit 63, bit 0 contains hash index bit 32.
      • Multicast address hash (low) - Specifies the low part of the 64-bit group address hash table used in the address recognition process to check for possible match with multicast address (DA field of received frames).
        Bit 31 of this value contains hash index bit 31, bit 0 contains hash index bit 0.
    • MII interface mode - Specifies Media Independent Interface (MII) mode. Selects external interface mode for both transmit and receive blocks. Current selected mode influence the availability of pins/signals settings (See the Pins group).

      There are 2 options:
      • 7-Wire: 7-Wire mode selected (used only for serial 10 Mbps)
      • MII mode: MII mode selected

    • Operation mode select - Specifies the FEC operation mode. Full duplex mode is intended for use on point to point links between switches or end node to switch. Half duplex mode is used in connections between an end node and a repeater or between repeaters. When configured for full duplex mode, the flow control may be enabled and frames are transmitted independent of carrier sense and collision inputs.
      This bit should only be modified when FEC module is disabled (ETHER_EN is deasserted).

      There are 2 options:
      • Half duplex: Half duplex operation mode selected
      • Full duplex: Full duplex operation mode selected

    • Flow control - Enables flow control. When enabled, the receiver will detect PAUSE frames. Upon PAUSE frame detection, the transmitter will stop transmitting data frames for a given duration.

      There are 2 options:
      • Disabled: Flow control is disabled
      • Enabled: Flow control is enabled

    • Preamble drop - Disables preamble (32 1's) to be prefixed to the MII management frame when enabled. The MII standard allows the preamble to be dropped if the attached PHY device(s) does not require it. If disabled then preamble (32 1's) will be prepended to the MII management frame.

      There are 2 options:
      • Disabled: Preamble generation prefixed to the frame is enabled (dropping is disabled)
      • Enabled: No preamble prefixed to the frame is generated (dropping is enabled)

    • Promiscuous mode - Enables promiscuous mode. When enabled, all frames are accepted regardless of address matching.

      There are 2 options:
      • Disabled: Promiscuous mode is disabled
      • Enabled: Promiscuous mode is enabled

    • Receive on transmit - Disables receive on transmit. Set to disabled for disabling reception of frames while transmitting, normally used for half duplex mode. When enabled the receive path operates independently of transmit, that is used for full duplex or to monitor transmit activity in half duplex mode.

      There are 2 options:
      • Disabled: Reception of frames while transmitting is disabled
      • Enabled: Receive path operates independently of transmit

    • Internal loopback - Internal loopback. If enabled, transmitted frames are looped back internal to the device and the transmit output signals are not asserted. The system clock is substituted for the ETXCLK when loopback is enabled. Receive on transmit must be set to enabled when enabling internal loopback.

      There are 2 options:
      • Disabled: Internal loopback is disabled
      • Enabled: Internal loopback is enabled

    • Heartbeat control - Enables heartbeat control. If enabled, the heartbeat check is performed following end of transmission and the HB bit in the status register will be set if the collision input does not assert within the heartbeat window.
      This bit should only be modified when FEC module is disabled (ETHER_EN is deasserted).

      There are 2 options:
      • Disabled: Heartbeat control is disabled
      • Enabled: Heartbeat control is enabled

    • Frames settings - Common frames settings of the module.
      • Broadcast frame - Specifies if broadcast frame rejected or accepted. If set to rejected, frames with destination address DA = FF_FF_FF_FF_FF_FF_FF_FF are rejected unless the promiscuous mode is selected. If set to rejected simultaneously with promiscuous mode selected (BC_REJ and PROM = 1), frames with broadcast DA are accepted and the 'miss' bit is set in the receive buffer descriptor.

        There are 2 options:
        • Rejected: Frame with DA is rejected
        • Accepted: Frame with DA is accepted

      • Maximum frame length - Specifies maximum frame length. Resets to decimal 1518. Length is measured starting at destination address (DA) and includes the CRC at the end of the frame. Frames longer than this value causes the BABT (transmit frames) or BABR (receive frames) interrupt to occur. In case of longer receive frames also the LG bit in the end of frame receive buffer descriptor is set.
        The recommended default value to be programmed by the user is 1518 or 1522 (if VLAN tags are supported).
      • Pause frame duration - Specifies the pause frame duration field used in transmission of a PAUSE frame. When another node detects a PAUSE frame, that node pauses transmission for the duration specified by this value.
    • FIFO/buffer settings - Common FIFO and buffer settings of the module.
      • Watermark value - Watermark value specifies the number of bytes written to transmit FIFO before transmission of a frame begins.

        There are 3 options:
        • 64 bytes: 64 bytes written
        • 128 bytes: 128 bytes written
        • 192 bytes: 192 bytes written

      • Receive buffer size - Specifies the receive buffer size in bytes. Entered value dictates the maximum size of all receive buffers. Because receive frames are truncated at 2k-1 bytes, only bits 10-4 of the register are used. This value should take into consideration that receive CRC is always written into the last receive buffer. To allow one maximum size frame per buffer, the value must be set to or larger than Max frame length. The value must be evenly divisible by 16. To ensure this, bits 3-0 are forced low. To minimize bus utilization (descriptor fetches) it is recommended that entered value be greater or equal to 256 bytes.
        Note: The value is not affected by reset, thus it must be initialized by the user.

        There are 128 options:
        • 0 bytes: 0 bytes
        • 16 bytes: 16 bytes
        • 32 bytes: 32 bytes
        • 48 bytes: 48 bytes
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      • FIFO receive start address - Entered value indicate the starting address of the receive FIFO. This value marks the boundary between the transmit and receive FIFO's.
        The transmit FIFO uses addresses from the start of the FIFO to the location four bytes before the address programmed into the FIFO Receive
        Start Register (FRSRn). The receive FIFO uses addresses from FRSRn to FRBRn inclusive.
        Note: Hardware initializes the FRSRn register at reset. It only needs to be written to change the default value. ItemLevel=BASIC
      • Receive buffer start descriptor - This group covers all settings of the receive buffer start address.
        • External object declaration - Declaration of an external object(s) that can be used to define current descriptor address (e.g. extern byte My_Buffer[]). If not empty this value will be generated into the source code of the bean 'as is' before the definition of the Init() method. It can be also use to include user specific header file (e.g. #include "My_definition.h").
          This item doesn't modify any register.
        • Receive buffer start address - Expression used to initialize Receive Descriptor Ring Start register (ERDSRn). It provides a pointer to the start of the circular receive buffer descriptor queue in external memory. This pointer must be 32-bit aligned. However, it is recommended it be made 128-bit aligned (evenly divisible by 16). It can be entered any expression that evaluates as 32-bit unsigned integer.
          ItemLevel=BASIC
      • Transmit buffer start descriptor - This group covers all settings of the transmit buffer start address.
        • External object declaration - Declaration of an external object(s) that can be used to define current descriptor address (e.g. extern byte My_Buffer[]). If not empty this value will be generated into the source code of the bean 'as is' before the definition of the Init() method. It can be also use to include user specific header file (e.g. #include "My_definition.h").
          This item doesn't modify any register.
        • Transmit buffer start address - Expression used to initialize Transmit Descriptor Ring Start register (ETDSRn). It provides a pointer to the start of the circular transmit buffer descriptor queue in external memory. This pointer must be 32-bit aligned. However, it is recommended it be made 128-bit aligned (evenly divisible by 16). It can be entered any expression that evaluates as 32-bit unsigned integer.
          ItemLevel=BASIC
  • Pins - Module pins/signals settings.
    • MII PHY - Media Independent Interface (MII) pins/signals settings (for information only).
      Interface mode can be changed by selection of MII interface mode property.
      There are 3 modes:
      • 7-Wire - 7-Wire mode selected (use only for serial 10 Mbps).
        The following items are displayed in this mode:
        • Ethernet transmit - Ethernet transmit pins/signals settings.
          • TXCLK pin - Enable/Disable allocation of the FEC_TXCLK pin. Input clock signal on this pin provides a timing reference for FEC_TXEN and FEC_TXD0 in the 7-wire interface mode.
            The following items are available only if the group is enabled (the value is "Enabled"):
          • TXEN pin - Enable/Disable allocation of the FEC_TXEN pin. Signal on this pin indicates when valid nibbles are present on the MII. This signal is asserted with the first nibble of a preamble and is negated before the first FEC_TXCLK following the final nibble of the frame.
            The following items are available only if the group is enabled (the value is "Enabled"):
          • COL pin - Enable/Disable allocation of the FEC_COL pin. Signal on this pin asserted upon detection of a collision and remains asserted while the collision persists. This signal is not defined for full duplex mode.
            The following items are available only if the group is enabled (the value is "Enabled"):
          • TXD0 pin - Enable/Disable allocation of the FEC_TXD0 pin. Signal on this pin contains the serial output Ethernet data valid only during the assertion of the FEC_TXEN.
            The following items are available only if the group is enabled (the value is "Enabled"):
        • Ethernet receive - Ethernet receive pins/signals settings.
          • RXCLK pin - Enable/Disable allocation of the FEC_RXCLK pin. Signal on this pin provides a timing reference for the FEC_RXDV and FEC_RXD0 in the 7-wire interface mode.
            The following items are available only if the group is enabled (the value is "Enabled"):
          • RXDV pin - Enable/Disable allocation of the FEC_RXDV pin. Asserting the FEC_RXDV input indicates PHY has valid nibbles present on the MII. FEC_RXDV must remain asserted from the first recovered nibble of the frame through to the last nibble. Assertion of FEC_RXDV must start no later than the SFD and exclude any EOF.
            The following items are available only if the group is enabled (the value is "Enabled"):
          • RXD0 pin - Enable/Disable allocation of the FEC_RXD0 pin. Signal on this pin contains the Ethernet input data transferred from the PHY to the media access controller when FEC_RXDV is asserted.
            The following items are available only if the group is enabled (the value is "Enabled"):
      • MII mode - MII mode selected.
        The following items are displayed in this mode:
        • Ethernet transmit - Ethernet transmit pins/signals settings.
          • TXCLK pin - Enable/Disable allocation of the FEC_TXCLK pin. Input clock signal on this pin provides a timing reference for FEC_TXEN, FEC_TXD[3:0] and FEC_TXER in the MII interface mode.
            The following items are available only if the group is enabled (the value is "Enabled"):
          • TXEN pin - Enable/Disable allocation of the FEC_TXEN pin. This signal is asserted with the first nibble of a preamble and is negated before the first FEC_TXCLK following the final nibble of the frame.
            The following items are available only if the group is enabled (the value is "Enabled"):
          • TXER pin - Enable/Disable allocation of the FEC_TXER pin. When signal on this pin asserted for one or more clock cycles while the FEC_TXEN is also asserted, PHY sends one or more illegal symbols. Signal has no effect at 10Mpbs or when FEC_TXEN is negated.
            The following items are available only if the group is enabled (the value is "Enabled"):
          • CRS pin - Enable/Disable allocation of the FEC_CRS pin. When carrier sense signal on this pin asserted, indicates transmit or receive medium is not idle.
            The following items are available only if the group is enabled (the value is "Enabled"):
          • COL pin - Enable/Disable allocation of the FEC_COL pin. Signal on this pin asserted upon detection of a collision and remains asserted while the collision persists. This signal is not defined for full duplex mode.
            The following items are available only if the group is enabled (the value is "Enabled"):
          • TXD0 pin - Enable/Disable allocation of the FEC_TXD0 pin. Signal on this pin contains the serial output Ethernet data valid only during the assertion of the FEC_TXEN.
            The following items are available only if the group is enabled (the value is "Enabled"):
          • TXD1 pin - Enable/Disable allocation of the FEC_TXD1 pin. Signal on this pin contains the serial output Ethernet data valid only during the assertion of the FEC_TXEN.
            The following items are available only if the group is enabled (the value is "Enabled"):
          • TXD2 pin - Enable/Disable allocation of the FEC_TXD2 pin. Signal on this pin contains the serial output Ethernet data valid only during the assertion of the FEC_TXEN.
            The following items are available only if the group is enabled (the value is "Enabled"):
          • TXD3 pin - Enable/Disable allocation of the FEC_TXD3 pin. Signal on this pin contains the serial output Ethernet data valid only during the assertion of the FEC_TXEN.
            The following items are available only if the group is enabled (the value is "Enabled"):
        • Ethernet receive - Ethernet receive pins/signals settings.
          • RXCLK pin - Enable/Disable allocation of the FEC_RXCLK pin. Signal on this pin provides a timing reference for the FEC_RXDV, FEC_RXD[3:0] and FEC_RXER in the MII interface mode.
            The following items are available only if the group is enabled (the value is "Enabled"):
          • RXDV pin - Enable/Disable allocation of the FEC_RXDV pin. Asserting the FEC_RXDV input indicates PHY has valid nibbles present on the MII. FEC_RXDV must remain asserted from the first recovered nibble of the frame through to the last nibble. Assertion of FEC_RXDV must start no later than the SFD and exclude any EOF.
            The following items are available only if the group is enabled (the value is "Enabled"):
          • RXER pin - Enable/Disable allocation of the FEC_RXER pin. When signal on this pin asserted with FEC_RXDV, indicates PHY detects an error in the current frame. When FEC_RXDV is not asserted, FEC_RXER has no effect.
            The following items are available only if the group is enabled (the value is "Enabled"):
          • RXD0 pin - Enable/Disable allocation of the FEC_RXD0 pin. Signal on this pin contains the Ethernet input data transferred from the PHY to the media access controller when FEC_RXDV is asserted.
            The following items are available only if the group is enabled (the value is "Enabled"):
          • RXD1 pin - Enable/Disable allocation of the FEC_RXD1 pin. Signal on this pin contains the Ethernet input data transferred from the PHY to the media access controller when FEC_RXDV is asserted.
            The following items are available only if the group is enabled (the value is "Enabled"):
          • RXD2 pin - Enable/Disable allocation of the FEC_RXD2 pin. Signal on this pin contains the Ethernet input data transferred from the PHY to the media access controller when FEC_RXDV is asserted.
            The following items are available only if the group is enabled (the value is "Enabled"):
          • RXD3 pin - Enable/Disable allocation of the FEC_RXD3 pin. Signal on this pin contains the Ethernet input data transferred from the PHY to the media access controller when FEC_RXDV is asserted.
            The following items are available only if the group is enabled (the value is "Enabled"):
        • Media independent (MII) - Media independent interface (MII) pins/signals settings.
          • MDC pin - Enable/Disable allocation of the FEC_MDC pin. Output clock signal on this pin provides a timing reference to the PHY for data transfers on the FEC_MDIO signal.
            The following items are available only if the group is enabled (the value is "Enabled"):
          • MDIO pin - Enable/Disable allocation of the FEC_MDIO pin. Transfers control information between the external PHY and the media-access controller. Data is synchronous to the FEC_MDC.
            Note: This signal is an input after reset. When FEC operates in 10Mbps 7-wire interface mode, this signal should be connected to VSS.
            The following items are available only if the group is enabled (the value is "Enabled"):
            • Pin - FEC Management data input/output pin.
            • Pin signal - Signal name of Pin
      • RMII mode - RMII mode selected.
        There are no items in this mode.
  • Interrupts - Interrupts settings of the module.
    • Other interrupt request - FEC Other interrupt request settings.
      • Interrupt - Interrupt vector (for information only).
      • Only if priority supported
      • ISR Name - Name of the interrupt service routine (ISR) invoked by this interrupt vector. The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
      • Other interrupt request - Enable/Disable Other interrupt request. This interrupt request can be configured to either enable the OR'd version of the interrupt request or the separate individual requests.

        There are 2 options:
        • Enabled: FEC Other interrupt is enabled
        • Disabled: FEC Other is disabled

    • Transmit frame - FEC Transmit frame interrupt settings.
      • Interrupt - Interrupt vector (for information only).
      • Only if priority supported
      • ISR Name - Name of the interrupt service routine (ISR) invoked by this interrupt vector. The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
      • Transmit frame - Enable/Disable transmit frame interrupt.

        There are 2 options:
        • Enabled: Transmit frame interrupt is enabled
        • Disabled: Transmit frame interrupt is disabled

    • Transmit buffer - FEC Transmit buffer interrupt settings.
      • Interrupt - Interrupt vector (for information only).
      • Only if priority supported
      • ISR Name - Name of the interrupt service routine (ISR) invoked by this interrupt vector. The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
      • Transmit buffer - Enable/Disable transmit buffer interrupt.

        There are 2 options:
        • Enabled: Transmit buffer interrupt is enabled
        • Disabled: Transmit buffer interrupt is disabled

    • Receive frame - FEC Receive frame interrupt settings.
      • Interrupt - Interrupt vector (for information only).
      • Only if priority supported
      • ISR Name - Name of the interrupt service routine (ISR) invoked by this interrupt vector. The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
      • Receive frame - Enable/Disable receive frame interrupt.

        There are 2 options:
        • Enabled: Receive frame interrupt is enabled
        • Disabled: Receive frame interrupt is disabled

    • Receive buffer - FEC Receive buffer interrupt settings.
      • Interrupt - Interrupt vector (for information only).
      • Only if priority supported
      • ISR Name - Name of the interrupt service routine (ISR) invoked by this interrupt vector. The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
      • Receive buffer - Enable/Disable receive buffer interrupt.

        There are 2 options:
        • Enabled: Receive buffer interrupt is enabled
        • Disabled: Receive buffer interrupt is disabled

    • Transmit FIFO underrun - FEC Transmit FIFO underrun interrupt settings.
      • Interrupt - Interrupt vector (for information only).
      • Only if priority supported
      • ISR Name - Name of the interrupt service routine (ISR) invoked by this interrupt vector. The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
      • Transmit FIFO underrun - Enable/Disable transmit FIFO underrun interrupt.

        There are 2 options:
        • Enabled: Transmit FIFO underrun interrupt is enabled
        • Disabled: Transmit FIFO underrun interrupt is disabled

    • Collision retry limit - FEC Collision retry limit interrupt settings.
      • Interrupt - Interrupt vector (for information only).
      • Only if priority supported
      • ISR Name - Name of the interrupt service routine (ISR) invoked by this interrupt vector. The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
      • Collision retry limit - Enable/Disable collision retry limit interrupt.

        There are 2 options:
        • Enabled: Collision retry limit interrupt is enabled
        • Disabled: Collision retry limit interrupt is disabled

    • Media independent - FEC Media Independent Interface (MII) interrupt settings.
      • Interrupt - Interrupt vector (for information only).
      • Only if priority supported
      • ISR Name - Name of the interrupt service routine (ISR) invoked by this interrupt vector. The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
      • Media independent interface - Enable/Disable Media Independent Interface (MII) interrupt.

        There are 2 options:
        • Enabled: Media Independent Interface interrupt is enabled
        • Disabled: Media Independent Interface interrupt is disabled

    • Late collision - FEC Late collision interrupt settings.
      • Interrupt - Interrupt vector (for information only).
      • Only if priority supported
      • ISR Name - Name of the interrupt service routine (ISR) invoked by this interrupt vector. The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
      • Late collision - Enable/Disable late collision interrupt.

        There are 2 options:
        • Enabled: Late collision interrupt is enabled
        • Disabled: Late collision interrupt is disabled

    • Heartbeat error - FEC Heartbeat error interrupt settings.
      • Interrupt - Interrupt vector (for information only).
      • Only if priority supported
      • ISR Name - Name of the interrupt service routine (ISR) invoked by this interrupt vector. The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
      • Heartbeat error - Enable/Disable heartbeat error interrupt.

        There are 2 options:
        • Enabled: Heartbeat error interrupt is enabled
        • Disabled: Heartbeat error interrupt is disabled

    • Graceful stop complete - FEC Graceful stop complete interrupt settings.
      • Interrupt - Interrupt vector (for information only).
      • Only if priority supported
      • ISR Name - Name of the interrupt service routine (ISR) invoked by this interrupt vector. The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
      • Graceful stop complete - Enable/Disable graceful stop complete interrupt.

        There are 2 options:
        • Enabled: Graceful stop complete interrupt is enabled
        • Disabled: Graceful stop complete interrupt is disabled

    • Ethernet bus error - FEC Ethernet bus error interrupt settings.
      • Interrupt - Interrupt vector (for information only).
      • Only if priority supported
      • ISR Name - Name of the interrupt service routine (ISR) invoked by this interrupt vector. The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
      • Ethernet bus error - Enable/Disable ethernet bus error interrupt.

        There are 2 options:
        • Enabled: Ethernet bus error interrupt is enabled
        • Disabled: Ethernet bus error interrupt is disabled

    • Babbling transmit error - FEC Babbling transmit error interrupt settings.
      • Interrupt - Interrupt vector (for information only).
      • Only if priority supported
      • ISR Name - Name of the interrupt service routine (ISR) invoked by this interrupt vector. The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
      • Babbling transmit error - Enable/Disable babbling transmit error interrupt.

        There are 2 options:
        • Enabled: Babbling transmit error interrupt is enabled
        • Disabled: Babbling transmit error interrupt is disabled

    • Babbling receive error - FEC Babbling receive error interrupt settings.
      • Interrupt - Interrupt vector (for information only).
      • Only if priority supported
      • ISR Name - Name of the interrupt service routine (ISR) invoked by this interrupt vector. The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
      • Babbling receive error - Enable/Disable babbling receive error interrupt.

        There are 2 options:
        • Enabled: Babbling receive error interrupt is enabled
        • Disabled: Babbling receive error interrupt is disabled

  • Initialization - Initialization options of the module.
    • Enable FEC - Enable/Disable FEC module reception and transmission. When disabled, any actual reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. The buffer descriptor(s) for an aborted transmit frame are not updated after disabling the module and following is reset: the DMA, buffer descriptor and FIFO control logic, including the buffer descriptor and FIFO pointers.
      Note: Hardware alters the ETHER_EN bit setting under the following conditions:
      - software reset was performed (by setting the RESET bit), in which case the FEC module is disabled (ETHER_EN = 0)
      - an error condition causes the Ethernet bus error (EIRn[EBERR] = 1), in which case the FEC module is disabled (ETHER_EN = 0)

      There are 2 options:
      • yes: FEC module transceiver is enabled
      • no: FEC module transceiver is disabled

    • Call Init method - The Init method of the component may be called after a power-on or reset (in initialization code) by PE.
      yes - The Init method is called by PE.
      no - The Init method is not called by PE, it should be called in the user's code.

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