Init_DMA
 
General Info



Init.Components



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Component Init_DMA for COLDFIREV1
Direct memory access (DMA)
Device Initialization
(Description of the component parameters.)
  • Device - DMA Device module
  • Settings - Common DMA module settings
    • DMA request source - This item selects the DMA request source.
    • Auto disable external request - Disable request. DMA hardware automatically clears the corresponding DCRn[ERQ] bit when the byte count register reaches zero.

      There are 2 options:
      • Enabled: ERQ bit is cleared when the BCR is exhausted
      • Disabled: ERQ bit is not affected.

    • Transfer mode - This item selects a transfer mode.

      There are 2 options:
      • Cycle-steal: Forces a single read/write transfer per request.
      • Continuous: DMA continuously makes read/write transfers until the BCR decrements to 0.

    • Auto align - Enables/disables auto align feature. AA and SIZE determine whether the source or destination is auto-aligned, that is, transfers are optimized based on the address and size.

      There are 2 options:
      • Enabled: If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.
      • Disabled: Auto-align disabled.

    • Channel links settings - Settings of channel link
      • Link channel control - This item sets link channel control. Allows DMA channels to have their transfers linked. The current DMA channel triggesr a DMA request to the linked channels (LCH1 or LCH2).

        There are 4 options:
        • No link: No channel-to-channel linking
        • LCH1 after each cycle steal transfer and LCH2 after BCR=0: Perform a link to channel LCH1 after each cycle steal transfer followed by a link to LCH2 after BCR decrements to 0
        • LCH1 after each cycle steal transfer: Perform a link to channel LCH1 after each cycle steal transfer
        • LCH1 after BCR=0: Perform a link to channel LCH1 after BCR decrements to 0

      • Link channel 1 (LCH1) - This property selects the DMA channel assigned as link channel 1. The link channel number cannot be the same as the currently executing channel, and generates a configuration error if this is attempted (DSRn[CE] is set).
      • Link channel 2 (LCH2) - This property selects the DMA channel assigned as link channel 2. The link channel number cannot be the same as the currently executing channel, and generates a configuration error if this is attempted (DSRn[CE] is set).
    • Data source - This group covers all settings of the data source
      • External object declaration - Declaration of an external object(s) that can be used to define source address (e.g extern unsigned char My_Buffer[]). If not empty this value will be generated into the source code of the component 'as is' before the definition of the DMAx_Init() method. It can be also use to include user specific header file (e.g. #include "My_definition.h").
      • Address - Expression used to initialize Source address register(SARn). It can any expression that evaluates as 32-bit unsigned integer. (e.g. number - 0x12545678, address of a register - (unsigned long)&URB1, external variable address (unsigned long)& My_Variable,...).
      • Address increment - This property controls whether a source address increments after each successful transfer.

        There are 2 options:
        • Enabled: The SAR increments by 1, 2, 4 as determined by the transfer size.
        • Disabled: No change to SAR after a successful transfer.

      • Data size - This property determines the data size of the source bus cycle for the DMA controller.

        There are 3 options:
        • Longword: 4 bytes
        • Byte: 1 byte
        • Word: 2 bytes

      • Address modulo - This property defines the size of the source data circular buffer used by the DMA Controller. If enabled, the buffer base address will be located on a boundary of the buffer size. The value of this boundary is based upon the initial source address (SAR). The base address should be aligned to a 0-modulo-(circular buffer size) boundary. Misaligned buffers are not possible. The boundary is forced to the value determined by the upper address bits in the field selection.
    • Data destination - This group covers all settings of the data destination
      • External object declaration - Declaration of an external object(s) that can be used to define destination address (e.g extern unsigned char My_Buffer[]). If not empty this value will be generated into the source code of the component 'as is' before the definition of the DMAx_Init() method. It can be also use to include user specific header file (e.g. #include "My_definition.h").
      • Address - Expression used to initialize Destination address register(DARn). It can any expression that evaluates as 32-bit unsigned integer. (e.g. number - 0x12545678, address of a register - (unsigned long)&URB1, external variable address (unsigned long)& My_Variable,...).
      • Address increment - This property controls whether a destination address increments after each successful transfer.

        There are 2 options:
        • Enabled: The DAR increments by 1, 2, 4 depending upon the size of the transfer.
        • Disabled: No change to DAR after a successful transfer.

      • Data size - This property determines the data size of the destination bus cycle for the DMA controller.

        There are 3 options:
        • Longword: 4 bytes
        • Byte: 1 byte
        • Word: 2 bytes

      • Address modulo - This property defines the size of the destination data circular buffer used by the DMA Controller. If enabled, the buffer base address will be located on a boundary of the buffer size. The value of this boundary is based upon the initial destination address (DAR). The base address should be aligned to a 0-modulo(circular buffer size) boundary. Misaligned buffers are not possible. The boundary will be forced to the value determined by the upper address bits in the field selection.
    • Byte count - This property defines number of bytes to be transferred.
  • Interrupts - Interrupts settings of the module
    • DMA interrupt - DMA interrupt
      • Interrupt - Interrupt vector (for information only).
      • Only if priority supported
      • DMA interrupt - Enables DMA interrupt

        There are 2 options:
        • Disabled: DMA interrupt request disabled
        • Enabled: DMA interrupt request enabled

      • ISR Name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
        Note: The routine must handle all interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
  • Initialization - Initialization options of the module
    • Start DMA transfer - Start DMA transfer by SW(set START bit to '1').

      There are 2 options:
      • yes: Start DMA transfer in the initialization method.
      • no: Don't start DMA transfer in the initialization method.

    • Enable peripheral request - Enables/disables peripherals request.

      There are 2 options:
      • yes: Enables peripheral request to initiate transfer defined by 'DMA request source' property. A software-initiated request (initiated by setting the DMACRn[START]) is always enabled.
      • no: External request is ignored.

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