Init_ADC
 
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Component Init_ADC for HCS08
Analog-to-Digital Converter (ADC)
Component Level: Peripheral Initialization
Category: CPU Internal Peripherals-Peripheral Initialization
Properties:
(Properties are parameters of the component. Please see the Embedded Components page for more information.)
  • Component name - Name of the component.
  • Device - Selection of the ADC device module.
  • Settings - Common ADC module settings
    • Clock settings - Clock/timing settings of the module
      • Setting supported for GB60, GB60A, GT60, GT60A, GT16A and MC1321x derivatives only.
        • Prescaler - This property determines the prescaled factor for the ATD conversion clock.
          This item modifies PRS[3:0] bits in the ATD1C register.
      • Settings only if ADC support Low power mode.
        • Input clock select - Selects the input clock source to generate internal clock.
          This item modifies ADICLK[1:0] bits of the ADCxCFG resp. ADCxCFG1 register.
        • Prescaler - This property selects the divide ratio used by the ADC to generate the internal ADC clock.
          This item modifies the ADIV[1:0] bits in the ADCxCFG resp. ADCxCFG1 register.
        • Settings only if ADC support High speed mode
          • High-speed conversion mode - This property enable/disable high speed conversion mode for ADC. In this mode ADC can run at higher conversion frequency, but ADC conversion takes 4 additional ADCK cycles.
            This item modifies ADHSC bit of the ADCxCFG2 register.
        • Settings only if ADC support Asynchro clock output enable/disable
          • Asynchro clock output - This property Enable/Disable asynchronous clock and clock output regardless of ADC state.
            This property influenced conversion time if the asynchro clock is selected as ADC clock - total conversion time is shortened by 5 us.
            This item modifies ADACKEN bit of the ADCxCFG2 register.
        • Long sample time - Selects between long and short sample time.
          This item modifies bit ADLSMP in the ADCxCFG resp. ADCxCFG1 register.
        • Settings only if ADC support extended long sample time selection
          • Long sample time length - Select length of the sample time in units of ADC conversion clock cycles. This selection affects the total conversion time and the A/D conversion accuracy ( a longer sample time results in a better accuracy).
            This item modifies ADLSTS[1:0] bits in ADCxCFG2 register.

            There are 4 options:
            • 20: 20 extra ADCK cycles added to sampling time
            • 12: 12 extra ADCK cycles added to sampling time
            • 6: 6 extra ADCK cycles added to sampling time
            • 2: 2 extra ADCK cycles added to sampling time

      • Frequency - Calculated ADC clock frequency (for information only).
        GB60, GB60A, GT60, GT60A, GT16A, MC1321x: This item is influenced by the following properties: Prescaler.
        Other derivatives: This item is influenced by the following properties: Prescaler, Input clock select.
      • ADC timing details - ADC timing details (for information only).
        Values:
        • Short - Conversion time for current settings is visible only.
        • Complex - Conversion time (SingleEnded; Differential mode) for Single and Continuous conversion and for HW average in these modes are visible on the same time and the current settings is signed in the third column.

        There are 2 modes:
        • Short - The following items are displayed in this mode:
          • Conversion time -

            Calculated ADC conversion time (for information only).

            For Conversion mode property set to Single conversion, the value is the maximum total conversion time of a single or 1st continuous conversion.

            For Conversion mode property set to Continuous conversion, the value is the conversion time of a subsequent conversion.

            This item is influenced by the following properties:

            GB60, GB60A, GT60, GT60A, GT16A, MC1321x: This item is influenced by the following properties: Prescaler, Conversion mode, Result data format.

            Other derivatives: This item is influenced by the following properties: Prescaler, Input clock select, Long sample time, Conversion mode, Result data format and Internal bus clock of the selected cpu.

        • Complex - The following items are displayed in this mode:
          • Single conversion time -

            Calculated ADC conversion time (for information only).

            The value is the maximum total conversion time of a single or 1st continuous conversion.

            The value is formatted by this way Single ended mode; Differential mode - mode should be set different for each channel .

            This item is influenced by the following properties: Prescaler, Input clock select, Long sample time, Long sample time length, Result data format and Internal bus clock of the selected cpu.

          • Continuous conversion time -

            Calculated ADC conversion time (for information only).

            The value is the conversion time of a subsequent conversion. For information about time of fisrt conversion from sequence see the property above.

            The value is formatted by this way Single ended mode; Differential mode - mode should be set different for each channel .

            This item is influenced by the following properties: Prescaler, Input clock select, Long sample time, Long sample time length, Result data format and Internal bus clock of the selected cpu.

          • Settings only if ADC support HW average.
            • HW average single conversion time -

              Calculated ADC conversion time (for information only).

              The value is the maximum total conversion time of a single or 1st continuous conversion, resp. time from start of conversion to set COCO flag, when the HW average is used .

              The value is formatted by this way Single ended mode; Differential mode - mode should be set different for each channel .

              This item is influenced by the following properties: Prescaler, Input clock select, Long sample time, Long sample time length, HW average length, Result data format and Internal bus clock of the selected cpu.

            • HW average continuous conversion time -

              Calculated ADC conversion time (for information only).

              The value is the conversion time of a subsequent conversion, resp. time from start of conversion to set COCO flag, when the HW average is used . For information about time of first conversion from sequence see the property above.

              The value is formatted by this way Single ended mode; Differential mode - mode should be set different for each channel .

              This item is influenced by the following properties: Prescaler, Input clock select, Long sample time, Long sample time length, HW average length, Result data format and Internal bus clock of the selected cpu.

    • Settings only if ADC has more than one Conversion mode bit
      • Conversion mode - If continuous conversion is set - ADC will convert samples continuously and update the ADC data register at end of each conversion.
        If single conversion is set, only one conversion is enabled
        GB60, GB60A, GT60, GT60A, GT16A, MC1321x: This item modifies the ATDCO bit in the ATDSC register.
        Other derivatives: This item modifies the ADCO bit in the ADCxSC1 or ADCxSC3 register.
    • Settings only if ADC has only one Conversion mode bit
      • Conversion mode A - If continuous conversion is set - ADC will convert samples continuously and update the ADC data register at end of each conversion. If single conversion is set, only one conversion is enabled, two conversions will be performed if Back 2 back conversion is enabled. This item modifies the ADCO bit in the ADCxSC1A register.
      • Conversion mode B - If continuous conversion is set - ADC will convert samples continuously and update the ADC data register at end of each conversion.
        If single conversion is set, only one conversion is enabled
        This item modifies the ADCO bit in the ADCxSC1B register.
    • Settings only if ADC support Low power mode.
      • Settings not supported for RS08 SA derivatives.
        • Low power mode - Enables low power configuration (the power is reduced at the expense of maximum clock speed).
          This item modifies ADLPC bit in the ADCxCFG resp. ADCxCFG1 register.
      • Conversion trigger - Selects the type of trigger to be used for initiating conversion.
        This item modifies the ADTRG bit in the ADCSC2 register.
      • Hardware trigger select - Select which hardware trigger initiates conversion for the analog to digital converter when the hardware Conversion trigger is selected.
        If there is only one item the property is for information only and says what device should be properly configured to be used as ADC trigger.
        For other derivatives: This item modifies the ADHTS, resp. ADHWTS or ADCTRS or ADCHTS bit in the SOPT2 or SIMIPS register.

        There are 2 options:
        • RTC: Real Time Counter (RTC) overflow
        • IRQ: External Interrupt Request (IRQ) pin

      • Settings only if ADC support compare feature.
        • Compare Function - Compare function settings
          • Compare function - Enables or disables automatic compare function of ATD.
            This items modifies the ACFE bit in the ADCxSC2 register.
          • Compare type - Selects type of the compare function.
            This item modifies the ACFGT bit of the ADCxSC2 register.
            If value of property is "greater then or equal" it means in range mode: If Compare value <= Second compare value compare triggers when input is inside range inclusive endpoint; if Compare value > Second compare value compare triggers when input is outside range inclusive endpoint.
            If value of property is "less then " it means in range mode: If Compare value <= Second compare value compare triggers when input is outside range exclusive endpoint; if Compare value > Second compare value compare triggers when input is inside range exclusive endpoint.

            There are 2 options:
            • greater than or equal: Compare triggers when input is greater than or equal to compare level
            • less than: Compare triggers when input is less than compare level

          • Compare value - This property determines the upper/lower limit of the comparison.
            This item modifies the ADCxCV, resp. ADCxCVH and ADCxCVL registers.
          • Settings only if ADC support range compare.
            • Range compare - Enables or disables range compare function of ADC.
              This items modifies the ACREN bit in the ADCxSC2 register.
            • Second compare value - This property determines the upper/lower limit of the range comparison.
              This item modifies the ADCxCV2, resp. ADCxCV2H and ADCxCV2L registers.
    • Settings only if ADC support HW average.
      • HW average - Enables or disables HW average function of ADC.
        This items modifies the AVGE bit in the ADCxSC3 register.
      • HW average length - Determines how many ADC conversions will be averaged to create ADC result.
        This items modifies the AVGS bits in the ADCxSC3 register.

        There are 4 options:
        • 4 samples: Result is averaged from 4 samples.
        • 8 samples: Result is averaged from 8 samples.
        • 16 samples: Result is averaged from 16 samples.
        • 32 samples: Result is averaged from 32 samples.

    • Settings only if ADC support Voltage reference selection.
      • Voltage reference - The property selects the voltage reference source.
        This item modifies the REFSEL[1:0] bits in ADCxSC2 register.

        There are 3 options:
        • VREFH/VREFL: Default voltage reference pin pair (VREFH/VREFL).
        • VDDA/VSSA: Analog supply pin pair (VDDA/VSSA).
        • On-chip: On-chip bandgap reference.

    • Settings only if ADC support back to back conversion feature.
      • Back 2 back conversion - This property enables/disables back to back conversion. If it's disabled than A and B conversions are triggered independently with B conversions only triggerable via hardware trigger sources. if it's enabled B conversions occur immediately following A conversions, either by software or hardware triggered conversions.
        This items modifies BB bit in ADCxSC2 register.
  • Pins - Module pins/signals settings
  • Interrupts/DMA - Interrupts settings of the module
    • Conversion complete - Conversion complete interrupt settings
      • Settings only if CPU supports interrupts
        • Interrupt - Interrupt vector (for information only)
        • Settings only if CPU supports interrup priority.
          • Priority - Priority of the conversion complete interrupt.
      • ADC type - Type of ADC: Selects channel for initialization ADCxSC1n register, ADC16V1 or newer should have more then 1 independent trigger source and own COCOn flag and interrupt enable bit IENn and result register ADCxRn, where the n letter means A,B,C,... (for information only).
        There are 2 modes:
        • ADC12V1 or ADC10V1 or ADC8V1 - The following items are displayed in this mode:
          • Conversion complete interrupt - Enable/disable conversion complete interrupt. When is enabled, an interrupt is generated upon completion of an ATD conversion. At this time, the result registers contain the result data generated by the conversion. The interrupt will remain pending as long as the conversion complete flag is set. If this property is disabled, then the conversion complete flag bit must be polled to determine when the conversion is complete.
            GB60, GB60A, GT60, GT60A, GT16A, MC1321x: This item modifies the ATDIE bit in the ATDSC register.
            Other derivatives: This item modifies the AIEN bit in the ADCSC1 register.
          • Settings only if ADC support trigger C
            • Conversion complete C interrupt - Enable/disable conversion complete interrupt. When is enabled, an interrupt is generated upon completion of an ATD conversion. At this time, the result registers C contains the result data generated by the conversion. The interrupt will remain pending as long as the conversion complete flag is set. If this property is disabled, then the conversion complete flag bit must be polled to determine when the conversion is complete.
              This item modifies the AIENC, resp. AIEN bit in the ADCxSC1C register.
          • Settings only if ADC support trigger D
            • Conversion complete D interrupt - Enable/disable conversion complete interrupt. When is enabled, an interrupt is generated upon completion of an ATD conversion. At this time, the result registers D contains the result data generated by the conversion. The interrupt will remain pending as long as the conversion complete flag is set. If this property is disabled, then the conversion complete flag bit must be polled to determine when the conversion is complete.
              This item modifies the AIEND, resp. AIEN bit in the ADCxSC1D register.
          • Settings only if ADC support trigger E
            • Conversion complete E interrupt - Enable/disable conversion complete interrupt. When is enabled, an interrupt is generated upon completion of an ATD conversion. At this time, the result registers E contains the result data generated by the conversion. The interrupt will remain pending as long as the conversion complete flag is set. If this property is disabled, then the conversion complete flag bit must be polled to determine when the conversion is complete.
              This item modifies the AIENE, resp. AIEN bit in the ADCxSC1E register.
          • Settings only if ADC support trigger F
            • Conversion complete F interrupt - Enable/disable conversion complete interrupt. When is enabled, an interrupt is generated upon completion of an ATD conversion. At this time, the result registers F contains the result data generated by the conversion. The interrupt will remain pending as long as the conversion complete flag is set. If this property is disabled, then the conversion complete flag bit must be polled to determine when the conversion is complete.
              This item modifies the AIENF, resp. AIEN bit in the ADCxSC1F register.
          • Settings only if ADC support trigger G
            • Conversion complete G interrupt - Enable/disable conversion complete interrupt. When is enabled, an interrupt is generated upon completion of an ATD conversion. At this time, the result registers G contains the result data generated by the conversion. The interrupt will remain pending as long as the conversion complete flag is set. If this property is disabled, then the conversion complete flag bit must be polled to determine when the conversion is complete.
              This item modifies the AIENG, resp. AIEN bit in the ADCxSC1G register.
          • Settings only if ADC support trigger H
            • Conversion complete H interrupt - Enable/disable conversion complete interrupt. When is enabled, an interrupt is generated upon completion of an ATD conversion. At this time, the result registers H contains the result data generated by the conversion. The interrupt will remain pending as long as the conversion complete flag is set. If this property is disabled, then the conversion complete flag bit must be polled to determine when the conversion is complete.
              This item modifies the AIENH, resp. AIEN bit in the ADCxSC1H register.
        • ADC16V1 - The following items are displayed in this mode:
          • Settings only if ADC support trigger A
            • Conversion complete A interrupt - Enable/disable conversion complete interrupt. When is enabled, an interrupt is generated upon completion of an ATD conversion. At this time, the result registers A contains the result data generated by the conversion. The interrupt will remain pending as long as the conversion complete flag is set. If this property is disabled, then the conversion complete flag bit must be polled to determine when the conversion is complete.
              This item modifies the AIENA, resp. AIEN bit in the ADCxSC1A register.
          • Settings only if ADC support trigger B
            • Conversion complete B interrupt - Enable/disable conversion complete interrupt. When is enabled, an interrupt is generated upon completion of an ATD conversion. At this time, the result registers B contains the result data generated by the conversion. The interrupt will remain pending as long as the conversion complete flag is set. If this property is disabled, then the conversion complete flag bit must be polled to determine when the conversion is complete.
              This item modifies the AIENB, resp. AIEN bit in the ADCxSC1B register.
          • Settings only if ADC support trigger C
            • Conversion complete C interrupt - See previous modes for more details
          • Settings only if ADC support trigger D
            • Conversion complete D interrupt - See previous modes for more details
          • Settings only if ADC support trigger E
            • Conversion complete E interrupt - See previous modes for more details
          • Settings only if ADC support trigger F
            • Conversion complete F interrupt - See previous modes for more details
          • Settings only if ADC support trigger G
            • Conversion complete G interrupt - See previous modes for more details
          • Settings only if ADC support trigger H
            • Conversion complete H interrupt - See previous modes for more details
      • Settings only if ADC support DMA
        • Conversion complete DMA - This property enables receive DMA and disables interrupt request from COCOn flag and vice versa.
          This item modifies DMAEN bit in ADCxSC2 register.
      • Settings only if CPU supports interrupts
        • ISR name - Name of the interrupt service routine (ISR) invoked by this interrupt vector.
          The user code of the routine should handle all respective interrupt flags correctly. The routine must be implemented in the user code, it is not generated by Processor Expert. Find external prototypes of the ISRs in the component module header file.
  • Initialization - Initialization options of the module
    • ADC type - Type of ADC: Selects channel for initialization ADCxSC1n register, ADC16V1 or newer should have more then 1 independent trigger source and own COCOn flag and interrupt enable bit IENn and result register ADCxRn, where the n letter means A,B,C,... (for information only).
      There are 2 modes:
      • ADC12V1 or ADC10V1 or ADC8V1 - The following items are displayed in this mode:
        • Initial channel select - This item selects initial conversion source or disables module. If the selected channel is connected with an input pin the pin must be assigned to the ADC in Pins group. The ADC module will start conversion of the selected channel after startup.
          GB60, GB60A, GT60, GT60A, GT16A, MC1321x: This item modifies the ATDCH[4:0] bits in the ATDSC register.
          RS08SA12: This item modifies the ADCH[3:0] bits in the ADCSC1 register.
          Other derivatives: This item modifies the ADCH[4:0] bits in the ADCSC1 register.
        • Settings only if ADC support differential mode.
          • Differential mode - Enable/disable differential mode. This item modifies DIFFA bit in ADCxSC1A register.
      • ADC16V1 - The following items are displayed in this mode:
        • Settings only if ADC support trigger A
          • ADC part triggered by trigger A or sofware trigger - Group of items influencing part of the ADC triggered by trigger A or sofware trigger
            • Initial channel select A - This item selects initial conversion source or disables module. If the selected channel is connected with an input pin the pin must be assigned to the ADC in Pins group. The ADC module will start conversion of the selected channel after startup.
              This item modifies the ADCHA[4:0], resp. ADCH[4:0] bits in the ADCxSC1A register.
            • Settings only if ADC support differential mode.
              • Differential mode A - Enable/disable differential mode. This item modifies DIFFA bit in ADCxSC1A register.
        • Settings only if ADC support trigger B
          • ADC part triggered by trigger B - Group of items influencing part of the ADC triggered by trigger B
            • Initial channel select B - This item selects initial conversion source or disables module. If the selected channel is connected with an input pin the pin must be assigned to the ADC in Pins group. The ADC module will start conversion of the selected channel after startup.
              This item modifies the ADCHB[4:0], resp. ADCH[4:0] bits in the ADCxSC1B register.
            • Settings only if ADC support differential mode.
              • Differential mode B - Enable/disable differential mode. This item modifies DIFFB bit in ADCxSC1B register.
        • Settings only if ADC support trigger C
          • ADC part triggered by trigger C - Group of items influencing part of the ADC triggered by trigger C
            • Initial channel select C - This item selects initial conversion source or disables module. If the selected channel is connected with an input pin the pin must be assigned to the ADC in Pins group. The ADC module will start conversion of the selected channel after startup.
              This item modifies the ADCHC[4:0], resp. ADCH[4:0] bits in the ADCxSC1C register.
            • Settings only if ADC support differential mode.
              • Differential mode C - Enable/disable differential mode. This item modifies DIFFC bit in ADCxSC1C register.
        • Settings only if ADC support trigger D
          • ADC part triggered by trigger D - Group of items influencing part of the ADC triggered by trigger D
            • Initial channel select D - This item selects initial conversion source or disables module. If the selected channel is connected with an input pin the pin must be assigned to the ADC in Pins group. The ADC module will start conversion of the selected channel after startup.
              This item modifies the ADCHD[4:0], resp. ADCH[4:0] bits in the ADCxSC1D register.
            • Settings only if ADC support differential mode.
              • Differential mode D - Enable/disable differential mode. This item modifies DIFFD bit in ADCxSC1D register.
        • Settings only if ADC support trigger E
          • ADC part triggered by trigger E - Group of items influencing part of the ADC triggered by trigger E
            • Initial channel select E - This item selects initial conversion source or disables module. If the selected channel is connected with an input pin the pin must be assigned to the ADC in Pins group. The ADC module will start conversion of the selected channel after startup.
              This item modifies the ADCHE[4:0], resp. ADCH[4:0] bits in the ADCxSC1E register.
            • Settings only if ADC support differential mode.
              • Differential mode E - Enable/disable differential mode. This item modifies DIFFE bit in ADCxSC1E register.
        • Settings only if ADC support trigger F
          • ADC part triggered by trigger F - Group of items influencing part of the ADC triggered by trigger F
            • Initial channel select F - This item selects initial conversion source or disables module. If the selected channel is connected with an input pin the pin must be assigned to the ADC in Pins group. The ADC module will start conversion of the selected channel after startup.
              This item modifies the ADCHF[4:0], resp. ADCH[4:0] bits in the ADCxSC1F register.
            • Settings only if ADC support differential mode.
              • Differential mode F - Enable/disable differential mode. This item modifies DIFFF bit in ADCxSC1F register.
        • Settings only if ADC support trigger G
          • ADC part triggered by trigger G - Group of items influencing part of the ADC triggered by trigger G
            • Initial channel select G - This item selects initial conversion source or disables module. If the selected channel is connected with an input pin the pin must be assigned to the ADC in Pins group. The ADC module will start conversion of the selected channel after startup.
              This item modifies the ADCHG[4:0], resp. ADCH[4:0] bits in the ADCxSC1G register.
            • Settings only if ADC support differential mode.
              • Differential mode G - Enable/disable differential mode. This item modifies DIFFG bit in ADCxSC1G register.
        • Settings only if ADC support trigger H
          • ADC part triggered by trigger H - Group of items influencing part of the ADC triggered by trigger H
            • Initial channel select H - This item selects initial conversion source or disables module. If the selected channel is connected with an input pin the pin must be assigned to the ADC in Pins group. The ADC module will start conversion of the selected channel after startup.
              This item modifies the ADCHH[4:0], resp. ADCH[4:0] bits in the ADCxSC1H register.
            • Settings only if ADC support differential mode.
              • Differential mode H - Enable/disable differential mode. This item modifies DIFFH bit in ADCxSC1H register.
    • Call Init method - The Init method of the component may be called after power-on or reset (in initialization code) by PE.
      - yes The Init method is called by PE
      - no The Init method is not called by PE, it should be called in user s code
    • Setting supported for GB60, GB60A, GT60, GT60A, GT16A and MC1321x derivatives only.
      • Enable module - Module Power Up.
        This item modifies the ATDPU bit in the ATDC register.

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