FreescaleCAN
 
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Component FreescaleCAN
CAN communication for Freescale implementation
Component Level: High
Category: CPU Internal Peripherals-Communication
Properties:
(Properties are parameters of the component. Please see the Embedded Components page for more information.)
  • Component name - Component name
  • CAN channel - CAN channel
  • Interrupt service/event - Component may or may not be implemented using interrupts. If this property is set to "Enabled", the component functionality (e.g. sending and receiving data) depends on the interrupt service and will not operate if the CPU interrupts are disabled. For details please refer to chapter "interrupt service in the component's generated code".
    The following items are available only if the group is enabled (the value is "Enabled"):
  • Settings - Settings of the CAN
    • Rx pin - Receive pin
    • Rx pin signal - Input signal name
    • Tx pin - Transmit pin
    • Tx pin Signal - Output signal name
    • The settings not supported for DSP83x derivatives.
      • Settings supported for HC08 derivatives only.
        • Acceptance mode - The CPU sets these flags to define the identifier’s acceptance filter organization (see documentation about this chip). In "Filter closed" mode no messages will be accepted, thus the foreground buffer will never be reloaded.
      • Settings not supported for HC08 derivatives.
        • Acceptance mode - The CPU sets these flags to define the identifier’s acceptance filter organization (see documentation about this chip). In "Filter closed" mode no messages will be accepted, thus the foreground buffer will never be reloaded.
      • Acceptance codes - Contains settings of the receive acceptance codes for the message filtering.
        • Acceptance code 1 - Acceptance code for message filtering. On reception, each identifier of the message is compared with this acceptance code. Reception of a new message is signaled only if it passes the criteria in the identifier acceptance and identifier mask registers (see also Acceptance mask). This code will be written to the acceptance code registers (e.g. IDAR0-IDAR3) after a reset. The most significant byte of the acceptance code will be written to the (e.g. IDAR0) register and the least significant byte of the acceptance code will be written to the (e.g. IDAR3 register).
        • Settings not supported for HC08 derivatives.
          • Acceptance code 2 - Acceptance code for message filtering. On reception, each identifier of the message is compared with this acceptance code. Reception of a new message is signaled only if it passes the criteria in the identifier acceptance and identifier mask registers (see also Acceptance mask). This mask will be written to the acceptance code registers (e.g. IDAR4-IDAR7) after a reset. The most significant byte of the acceptance code will be written to the (e.g. IDAR4) register and the least significant byte of the acceptance code will be written to the (e.g. IDAR7 register).
      • Acceptance masks - Contains settings of the receive acceptance mask for the message filtering.
        • Acceptance mask 1 - Acceptance mask for message filtering. If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier’s acceptance register must be the same as its identifier bit before a match is detected. This mask will be written to the acceptance mask registers (e.g. IDMR0-IDMR3) after a reset. The most significant byte of the acceptance mask will be written to the (e.g. IDMR0) register and the least significant byte of the acceptance mask will be written to the (e.g. IDMR3 register).
        • Settings not supported for HC08 derivatives.
          • Acceptance mask 2 - Acceptance mask for message filtering. If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier’s acceptance register must be the same as its identifier bit before a match is detected. This mask will be written to the acceptance mask registers (e.g. IDMR4-IDMR7) after a reset. The most significant byte of the acceptance mask will be written to the (e.g. IDMR4) register and the least significant byte of the acceptance mask will be written to the (e.g. IDMR7 register).
    • Loop mode - When this bit is set, the CAN module performs an internal loop back which can be used for self test operation. The bit stream output of the transmitter is fed back to the receiver internally. The RXCAN input pin is ignored and the TXCAN output goes to the recessive state (logic ‘1’). The CAN module behaves as it does normally when transmitting and treats its own transmitted message as a message received from a remote node. In this state, the CAN module ignores the bit sent during the ACK slot in the CAN frame Acknowledge field to ensure proper reception of its own message. Both transmit and receive interrupts are generated.
    • Settings supported for Freescale 56800/E 56F803x and 56F82xx and HCS08 and HCS12 P and HCS12X and ColdFireV1 derivatives only.
      • Bus-Off recovery mode - The property configures the bus-off recovery mode. See also BusOffRecoveryRequest method.

        There are 2 options:
        • Automatic: Automatic bus-off recovery
        • User: Bus-off recovery upon user request

    • Settings supported for Freescale 56800/E 56F802x, 56F803x, 56F82xx and 56F83x and HCS08 and HCS12 and HCS12X and ColdFireV1 derivatives only.
      • Listen only mode - This property configures the CAN module as a bus monitor. When this property is set to "yes", all valid CAN messages with matching ID are received, but no acknowledgement or error frames are sent out. In addition, the error counters are frozen. Listen Only Mode supports applications which require "hot plugging" or throughput analysis. The CAN module is unable to transmit any messages, when Listen Only Mode is active.
    • Settings supported for Freescale 56800/E 56F802x, 56F803x and 56F82xx and HCS08 and HCS12 and HCS12X and ColdFireV1 derivatives only.
      • Time stamp - This bit activates an internal 16-bit wide free running timer which is clocked by the bit clock. If the timer is enabled, a 16-bit time stamp will be assigned to each transmitted/received message within the active Tx/Rx buffer. As soon as a message is acknowledged on CAN, the time stamp will be written to the highest bytes ($_E, $_F) in the appropriate buffer.
    • Wakeup - Enables wakeup function.
      The following items are available only if the group is enabled (the value is "Enabled"):
  • Timing - Timing of the CAN
    • CAN timing wizard - CAN timing wizard allows to set the communication speed and then the wizard calculates all necessary timing properties.
    • Time segment 1 - The length of the time segment 1 of a nominal bit time. It determines the sample point. Number of time quanta is equal to entered value + 1.
    • Time segment 2 - The length of the time segment 2 of a nominal bit time. It determines the sample point. Number of time quanta is equal to entered value + 1.
    • RSJ - Resynchronization jump width.
    • Samples per bit - This bit determines the number of serial bus samples to be taken per bit time.
    • Time quanta per bit - Number of time quanta per bit. The formula used to calculate the value is: Time quanta per bit = (PropSeg+1) + (TSeg1) + (TSeg2) + 1.
      Note: The propagation segment property may not be available on all CAN devices. It depends on HW implementation of the CAN module.
      This property is for information only.
    • Bit rate - Communication clock rate.
  • Initialization - Initialization of the CAN
  • CPU clock/speed selection - Settings for the CPU speed modes: if the component is supported or not
    For details about speed modes please refer to page Speed Modes Support.

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