Display Data Channel (DDC) is a standard defined by VESA for monitor devices. There are two levels of DDC, namely DDC level 1 (DDC1) and DDC level 2 (DDC2). This component encapsulates DDC1, which is unidirectional communication protocol between host computer and monitor. It is a serial communication interface with a clock and data line. The vertical sync (Vsync) from the host is used as the clock input. The data are continuously clocked out to the data line (SDA) by the rising edge of the Vsync input signal. Every nine clock pulses will complete one byte data transmission. The data bit generated on the ninth clock pulse is an acknowledge bit that should be discarded by the host. During communication, a falling transition on the SCL line can be detected to generate interrupt to the CPU.