/* Based on CPU DB MCF51EM128_100, version 3.00.041 (RegistersPrg V2.31) */ /* DataSheet : MCF51EM256RM Revision 6 6/30, 2009 */ #include /*lint -save -esym(765, *) */ /* * * * * 8-BIT REGISTERS * * * * * * * * * * * * * * * */ /* NV1FTRIM - macro for reading non volatile register Nonvolatile ICS Fine Trim 1; 0x000003FE */ /* Tip for register initialization in the user code: const byte NV1FTRIM_INIT @0x000003FE = ; */ /* NV1ICSTRM - macro for reading non volatile register Nonvolatile ICS Trim Register 1; 0x000003FF */ /* Tip for register initialization in the user code: const byte NV1ICSTRM_INIT @0x000003FF = ; */ /* NV1BACKKEY0 - macro for reading non volatile register Backdoor Comparison Key 0; 0x00000400 */ /* Tip for register initialization in the user code: const byte NV1BACKKEY0_INIT @0x00000400 = ; */ /* NV1BACKKEY1 - macro for reading non volatile register Backdoor Comparison Key 1; 0x00000401 */ /* Tip for register initialization in the user code: const byte NV1BACKKEY1_INIT @0x00000401 = ; */ /* NV1BACKKEY2 - macro for reading non volatile register Backdoor Comparison Key 2; 0x00000402 */ /* Tip for register initialization in the user code: const byte NV1BACKKEY2_INIT @0x00000402 = ; */ /* NV1BACKKEY3 - macro for reading non volatile register Backdoor Comparison Key 3; 0x00000403 */ /* Tip for register initialization in the user code: const byte NV1BACKKEY3_INIT @0x00000403 = ; */ /* NV1BACKKEY4 - macro for reading non volatile register Backdoor Comparison Key 4; 0x00000404 */ /* Tip for register initialization in the user code: const byte NV1BACKKEY4_INIT @0x00000404 = ; */ /* NV1BACKKEY5 - macro for reading non volatile register Backdoor Comparison Key 5; 0x00000405 */ /* Tip for register initialization in the user code: const byte NV1BACKKEY5_INIT @0x00000405 = ; */ /* NV1BACKKEY6 - macro for reading non volatile register Backdoor Comparison Key 6; 0x00000406 */ /* Tip for register initialization in the user code: const byte NV1BACKKEY6_INIT @0x00000406 = ; */ /* NV1BACKKEY7 - macro for reading non volatile register Backdoor Comparison Key 7; 0x00000407 */ /* Tip for register initialization in the user code: const byte NV1BACKKEY7_INIT @0x00000407 = ; */ /* NV1PROT - macro for reading non volatile register Nonvolatile Flash Protection Register; 0x0000040D */ /* Tip for register initialization in the user code: const byte NV1PROT_INIT @0x0000040D = ; */ /* NV1OPT - macro for reading non volatile register Nonvolatile Flash Options Register; 0x0000040F */ /* Tip for register initialization in the user code: const byte NV1OPT_INIT @0x0000040F = ; */ /* NV2FTRIM - macro for reading non volatile register Nonvolatile ICS Fine Trim 2; 0x000103FE */ /* Tip for register initialization in the user code: const byte NV2FTRIM_INIT @0x000103FE = ; */ /* NV2ICSTRM - macro for reading non volatile register Nonvolatile ICS Trim Register 2; 0x000103FF */ /* Tip for register initialization in the user code: const byte NV2ICSTRM_INIT @0x000103FF = ; */ /* NV2BACKKEY0 - macro for reading non volatile register Backdoor Comparison Key 0; 0x00010400 */ /* Tip for register initialization in the user code: const byte NV2BACKKEY0_INIT @0x00010400 = ; */ /* NV2BACKKEY1 - macro for reading non volatile register Backdoor Comparison Key 1; 0x00010401 */ /* Tip for register initialization in the user code: const byte NV2BACKKEY1_INIT @0x00010401 = ; */ /* NV2BACKKEY2 - macro for reading non volatile register Backdoor Comparison Key 2; 0x00010402 */ /* Tip for register initialization in the user code: const byte NV2BACKKEY2_INIT @0x00010402 = ; */ /* NV2BACKKEY3 - macro for reading non volatile register Backdoor Comparison Key 3; 0x00010403 */ /* Tip for register initialization in the user code: const byte NV2BACKKEY3_INIT @0x00010403 = ; */ /* NV2BACKKEY4 - macro for reading non volatile register Backdoor Comparison Key 4; 0x00010404 */ /* Tip for register initialization in the user code: const byte NV2BACKKEY4_INIT @0x00010404 = ; */ /* NV2BACKKEY5 - macro for reading non volatile register Backdoor Comparison Key 5; 0x00010405 */ /* Tip for register initialization in the user code: const byte NV2BACKKEY5_INIT @0x00010405 = ; */ /* NV2BACKKEY6 - macro for reading non volatile register Backdoor Comparison Key 6; 0x00010406 */ /* Tip for register initialization in the user code: const byte NV2BACKKEY6_INIT @0x00010406 = ; */ /* NV2BACKKEY7 - macro for reading non volatile register Backdoor Comparison Key 7; 0x00010407 */ /* Tip for register initialization in the user code: const byte NV2BACKKEY7_INIT @0x00010407 = ; */ /* NV2PROT - macro for reading non volatile register Nonvolatile Flash Protection Register; 0x0001040D */ /* Tip for register initialization in the user code: const byte NV2PROT_INIT @0x0001040D = ; */ /* NV2OPT - macro for reading non volatile register Nonvolatile Flash Options Register; 0x0001040F */ /* Tip for register initialization in the user code: const byte NV2OPT_INIT @0x0001040F = ; */ volatile PTADSTR _PTAD; /* Port A Data Register; 0xFFFF8000 */ volatile PTADDSTR _PTADD; /* Port A Data Direction Register; 0xFFFF8001 */ volatile PTASETSTR _PTASET; /* Port A Data Set Register; 0xFFFF8002 */ volatile PTACLRSTR _PTACLR; /* Port A Data Clear Register; 0xFFFF8003 */ volatile PTATOGSTR _PTATOG; /* Port A Toggle Register; 0xFFFF8004 */ volatile PTAPESTR _PTAPE; /* Port A Pull Enable Register; 0xFFFF8008 */ volatile PTASESTR _PTASE; /* Port A Slew Rate Enable Register; 0xFFFF8009 */ volatile PTADSSTR _PTADS; /* Port A Drive Strength Selection Register; 0xFFFF800A */ volatile PTAIFESTR _PTAIFE; /* Port A Input Filter Enable Register; 0xFFFF800B */ volatile PTBDSTR _PTBD; /* Port B Data Register; 0xFFFF8040 */ volatile PTBDDSTR _PTBDD; /* Port B Data Direction Register; 0xFFFF8041 */ volatile PTBSETSTR _PTBSET; /* Port B Data Set Register; 0xFFFF8042 */ volatile PTBCLRSTR _PTBCLR; /* Port B Data Clear Register; 0xFFFF8043 */ volatile PTBTOGSTR _PTBTOG; /* Port B Toggle Register; 0xFFFF8044 */ volatile PTBPESTR _PTBPE; /* Port B Pull Enable Register; 0xFFFF8048 */ volatile PTBSESTR _PTBSE; /* Port B Slew Rate Enable Register; 0xFFFF8049 */ volatile PTBDSSTR _PTBDS; /* Port B Drive Strength Selection Register; 0xFFFF804A */ volatile PTBIFESTR _PTBIFE; /* Port B Input Filter Enable Register; 0xFFFF804B */ volatile PTCDSTR _PTCD; /* Port C Data Register; 0xFFFF8080 */ volatile PTCDDSTR _PTCDD; /* Port C Data Direction Register; 0xFFFF8081 */ volatile PTCSETSTR _PTCSET; /* Port C Data Set Register; 0xFFFF8082 */ volatile PTCCLRSTR _PTCCLR; /* Port C Data Clear Register; 0xFFFF8083 */ volatile PTCTOGSTR _PTCTOG; /* Port C Toggle Register; 0xFFFF8084 */ volatile PTCPESTR _PTCPE; /* Port C Pull Enable Register; 0xFFFF8088 */ volatile PTCSESTR _PTCSE; /* Port C Slew Rate Enable Register; 0xFFFF8089 */ volatile PTCDSSTR _PTCDS; /* Port C Drive Strength Selection Register; 0xFFFF808A */ volatile PTCIFESTR _PTCIFE; /* Port C Input Filter Enable Register; 0xFFFF808B */ volatile PTDDSTR _PTDD; /* Port D Data Register; 0xFFFF80C0 */ volatile PTDDDSTR _PTDDD; /* Port D Data Direction Register; 0xFFFF80C1 */ volatile PTDSETSTR _PTDSET; /* Port D Data Set Register; 0xFFFF80C2 */ volatile PTDCLRSTR _PTDCLR; /* Port D Data Clear Register; 0xFFFF80C3 */ volatile PTDTOGSTR _PTDTOG; /* Port D Toggle Register; 0xFFFF80C4 */ volatile PTDPESTR _PTDPE; /* Port D Pull Enable Register; 0xFFFF80C8 */ volatile PTDSESTR _PTDSE; /* Port D Slew Rate Enable Register; 0xFFFF80C9 */ volatile PTDDSSTR _PTDDS; /* Port D Drive Strength Selection Register; 0xFFFF80CA */ volatile PTDIFESTR _PTDIFE; /* Port D Input Filter Enable Register; 0xFFFF80CB */ volatile PTEDSTR _PTED; /* Port E Data Register; 0xFFFF8100 */ volatile PTEDDSTR _PTEDD; /* Port E Data Direction Register; 0xFFFF8101 */ volatile PTESETSTR _PTESET; /* Port E Data Set Register; 0xFFFF8102 */ volatile PTECLRSTR _PTECLR; /* Port E Data Clear Register; 0xFFFF8103 */ volatile PTETOGSTR _PTETOG; /* Port E Toggle Register; 0xFFFF8104 */ volatile PTEPESTR _PTEPE; /* Port E Pull Enable Register; 0xFFFF8108 */ volatile PTESESTR _PTESE; /* Port E Slew Rate Enable Register; 0xFFFF8109 */ volatile PTEDSSTR _PTEDS; /* Port E Drive Strength Selection Register; 0xFFFF810A */ volatile PTEIFESTR _PTEIFE; /* Port E Input Filter Enable Register; 0xFFFF810B */ volatile PTFDSTR _PTFD; /* Port F Data Register; 0xFFFF8140 */ volatile PTFDDSTR _PTFDD; /* Port F Data Direction Register; 0xFFFF8141 */ volatile PTFSETSTR _PTFSET; /* Port F Data Set Register; 0xFFFF8142 */ volatile PTFCLRSTR _PTFCLR; /* Port F Data Clear Register; 0xFFFF8143 */ volatile PTFTOGSTR _PTFTOG; /* Port F Toggle Register; 0xFFFF8144 */ volatile PTFPESTR _PTFPE; /* Port F Pull Enable Register; 0xFFFF8148 */ volatile PTFSESTR _PTFSE; /* Port F Slew Rate Enable Register; 0xFFFF8149 */ volatile PTFDSSTR _PTFDS; /* Port F Drive Strength Selection Register; 0xFFFF814A */ volatile PTFIFESTR _PTFIFE; /* Port F Input Filter Enable Register; 0xFFFF814B */ volatile KBI1SCSTR _KBI1SC; /* KBI1 Status and Control Register; 0xFFFF8180 */ volatile KBI1PESTR _KBI1PE; /* KBI1 Pin Enable Register; 0xFFFF8181 */ volatile KBI1ESSTR _KBI1ES; /* KBI1 Edge Select Register; 0xFFFF8182 */ volatile KBI2SCSTR _KBI2SC; /* KBI2 Status and Control Register; 0xFFFF81A0 */ volatile KBI2PESTR _KBI2PE; /* KBI2 Pin Enable Register; 0xFFFF81A1 */ volatile KBI2ESSTR _KBI2ES; /* KBI2 Edge Select Register; 0xFFFF81A2 */ volatile IRQSCSTR _IRQSC; /* Interrupt request status and control register; 0xFFFF81C0 */ volatile PTAPF1STR _PTAPF1; /* Port A Routing Register 1; 0xFFFF8200 */ volatile PTAPF2STR _PTAPF2; /* Port A Routing Register 2; 0xFFFF8201 */ volatile PTBPF1STR _PTBPF1; /* Port B Routing Register 1; 0xFFFF8202 */ volatile PTBPF2STR _PTBPF2; /* Port B Routing Register 2; 0xFFFF8203 */ volatile PTCPF1STR _PTCPF1; /* Port C Routing Register 1; 0xFFFF8204 */ volatile PTCPF2STR _PTCPF2; /* Port C Routing Register 2; 0xFFFF8205 */ volatile PTDPF1STR _PTDPF1; /* Port D Routing Register 1; 0xFFFF8206 */ volatile PTDPF2STR _PTDPF2; /* Port D Routing Register 2; 0xFFFF8207 */ volatile PTEPF1STR _PTEPF1; /* Port E Routing Register 1; 0xFFFF8208 */ volatile PTEPF2STR _PTEPF2; /* Port E Routing Register 2; 0xFFFF8209 */ volatile PTFPF1STR _PTFPF1; /* Port F Routing Register 1; 0xFFFF820A */ volatile PTFPF2STR _PTFPF2; /* Port F Routing Register 2; 0xFFFF820B */ volatile LCDPF1STR _LCDPF1; /* LCD Pin Mux Control Register 1; 0xFFFF820C */ volatile LCDPF2STR _LCDPF2; /* LCD Pin Mux Control Register 1; 0xFFFF820D */ volatile ICSC1STR _ICSC1; /* ICS Control Register 1; 0xFFFF8220 */ volatile ICSC2STR _ICSC2; /* ICS Control Register 2; 0xFFFF8221 */ volatile ICSTRMSTR _ICSTRM; /* ICS Trim Register; 0xFFFF8222 */ volatile ICSSCSTR _ICSSC; /* ICS Status and Control Register; 0xFFFF8223 */ volatile CCSCTRLSTR _CCSCTRL; /* Clock Check & Select Control; 0xFFFF8240 */ volatile CCSTMR1STR _CCSTMR1; /* CCS XOSC1 Timer Register; 0xFFFF8241 */ volatile CCSTMR2STR _CCSTMR2; /* CCS XOSC2 Timer Register; 0xFFFF8242 */ volatile CCSTMRIRSTR _CCSTMRIR; /* CCS Internal Reference Clock Timer Register; 0xFFFF8243 */ volatile SRSSTR _SRS; /* System Reset Status Register; 0xFFFF8280 */ volatile SOPT1STR _SOPT1; /* System Options Register 1; 0xFFFF8281 */ volatile SOPT2STR _SOPT2; /* System Options Register 2; 0xFFFF8282 */ volatile SCGC1STR _SCGC1; /* System Clock Gating Control 1 Register; 0xFFFF8286 */ volatile SCGC2STR _SCGC2; /* System Clock Gating Control 2 Register; 0xFFFF8287 */ volatile SCGC3STR _SCGC3; /* System Clock Gating Control 3 Register; 0xFFFF8288 */ volatile SCGC4STR _SCGC4; /* System Clock Gating Control 4 Register; 0xFFFF8289 */ volatile SCGC5STR _SCGC5; /* System Clock Gating Control 5 Register; 0xFFFF828A */ volatile SIMCOSTR _SIMCO; /* SIM Clock Options Register; 0xFFFF828B */ volatile SIMIPS1STR _SIMIPS1; /* Internal Peripheral Select Register 1; 0xFFFF828D */ volatile SIMIPS2STR _SIMIPS2; /* Internal Peripheral Select Register 1; 0xFFFF828E */ volatile SPMSC1STR _SPMSC1; /* System Power Management Status and Control 1 Register; 0xFFFF82A0 */ volatile SPMSC2STR _SPMSC2; /* System Power Management Status and Control 2 Register; 0xFFFF82A1 */ volatile SPMSC3STR _SPMSC3; /* System Power Management Status and Control 3 Register; 0xFFFF82A3 */ volatile SCI1C1STR _SCI1C1; /* SCI1 Control Register 1; 0xFFFF82C2 */ volatile SCI1C2STR _SCI1C2; /* SCI1 Control Register 2; 0xFFFF82C3 */ volatile SCI1S1STR _SCI1S1; /* SCI1 Status Register 1; 0xFFFF82C4 */ volatile SCI1S2STR _SCI1S2; /* SCI1 Status Register 2; 0xFFFF82C5 */ volatile SCI1C3STR _SCI1C3; /* SCI1 Control Register 3; 0xFFFF82C6 */ volatile SCI1DSTR _SCI1D; /* SCI1 Data Register; 0xFFFF82C7 */ volatile SCI2C1STR _SCI2C1; /* SCI2 Control Register 1; 0xFFFF82E2 */ volatile SCI2C2STR _SCI2C2; /* SCI2 Control Register 2; 0xFFFF82E3 */ volatile SCI2S1STR _SCI2S1; /* SCI2 Status Register 1; 0xFFFF82E4 */ volatile SCI2S2STR _SCI2S2; /* SCI2 Status Register 2; 0xFFFF82E5 */ volatile SCI2C3STR _SCI2C3; /* SCI2 Control Register 3; 0xFFFF82E6 */ volatile SCI2DSTR _SCI2D; /* SCI2 Data Register; 0xFFFF82E7 */ volatile SCI3C1STR _SCI3C1; /* SCI3 Control Register 1; 0xFFFF8302 */ volatile SCI3C2STR _SCI3C2; /* SCI3 Control Register 2; 0xFFFF8303 */ volatile SCI3S1STR _SCI3S1; /* SCI3 Status Register 1; 0xFFFF8304 */ volatile SCI3S2STR _SCI3S2; /* SCI3 Status Register 2; 0xFFFF8305 */ volatile SCI3C3STR _SCI3C3; /* SCI3 Control Register 3; 0xFFFF8306 */ volatile SCI3DSTR _SCI3D; /* SCI3 Data Register; 0xFFFF8307 */ volatile SPI1C1STR _SPI1C1; /* SPI1 Control Register 1; 0xFFFF8320 */ volatile SPI1C2STR _SPI1C2; /* SPI1 Control Register 2; 0xFFFF8321 */ volatile SPI1BRSTR _SPI1BR; /* SPI1 Baud Rate Register; 0xFFFF8322 */ volatile SPI1SSTR _SPI1S; /* SPI1 Status Register; 0xFFFF8323 */ volatile SPI1C3STR _SPI1C3; /* SPI1 Control Register 3; 0xFFFF8328 */ volatile SPI1CISTR _SPI1CI; /* SPI1 Clear Interrupt Register; 0xFFFF8329 */ volatile SPI2C1STR _SPI2C1; /* SPI2 Control Register 1; 0xFFFF8340 */ volatile SPI2C2STR _SPI2C2; /* SPI2 Control Register 2; 0xFFFF8341 */ volatile SPI2BRSTR _SPI2BR; /* SPI2 Baud Rate Register; 0xFFFF8342 */ volatile SPI2SSTR _SPI2S; /* SPI2 Status Register; 0xFFFF8343 */ volatile SPI2DSTR _SPI2D; /* SPI2 Data Register; 0xFFFF8345 */ volatile SPI3C1STR _SPI3C1; /* SPI3 Control Register 1; 0xFFFF8360 */ volatile SPI3C2STR _SPI3C2; /* SPI3 Control Register 2; 0xFFFF8361 */ volatile SPI3BRSTR _SPI3BR; /* SPI3 Baud Rate Register; 0xFFFF8362 */ volatile SPI3SSTR _SPI3S; /* SPI3 Status Register; 0xFFFF8363 */ volatile SPI3DSTR _SPI3D; /* SPI3 Data Register; 0xFFFF8365 */ volatile IICA1STR _IICA1; /* IIC Address Register; 0xFFFF8380 */ volatile IICFSTR _IICF; /* IIC Frequency Divider Register; 0xFFFF8381 */ volatile IICC1STR _IICC1; /* IIC Control Register 1; 0xFFFF8382 */ volatile IICSSTR _IICS; /* IIC Status Register; 0xFFFF8383 */ volatile IICDSTR _IICD; /* IIC Data I/O Register; 0xFFFF8384 */ volatile IICC2STR _IICC2; /* IIC Control Register 2; 0xFFFF8385 */ volatile IICSMBSTR _IICSMB; /* SMBus Control and Status Register; 0xFFFF8386 */ volatile IICA2STR _IICA2; /* IIC Address Register 2; 0xFFFF8387 */ volatile IICFLTSTR _IICFLT; /* IIC Filter register; 0xFFFF838A */ volatile VREFTRMSTR _VREFTRM; /* VREF Trim Register; 0xFFFF83C0 */ volatile VREFSCSTR _VREFSC; /* VREF Control Register; 0xFFFF83C1 */ volatile ADC1SC1ASTR _ADC1SC1A; /* Status and Control Register 1A; 0xFFFF8400 */ volatile ADC1SC1BSTR _ADC1SC1B; /* Status and Control Register 1B; 0xFFFF8401 */ volatile ADC1CFG1STR _ADC1CFG1; /* Configuration Register 1; 0xFFFF8402 */ volatile ADC1CFG2STR _ADC1CFG2; /* Configuration Register 2; 0xFFFF8403 */ volatile ADC1SC2STR _ADC1SC2; /* Status and Control Register 2; 0xFFFF840C */ volatile ADC1SC3STR _ADC1SC3; /* Status and Control Register 3; 0xFFFF840D */ volatile ADC1CLPDSTR _ADC1CLPD; /* Plus-Side General Calibration Value D Register; 0xFFFF8414 */ volatile ADC1CLPSSTR _ADC1CLPS; /* Plus-Side General Calibration Value S Register; 0xFFFF8415 */ volatile ADC1CLP2STR _ADC1CLP2; /* Plus-Side General Calibration Value 2 Register; 0xFFFF841A */ volatile ADC1CLP1STR _ADC1CLP1; /* Plus-Side General Calibration Value 1 Register; 0xFFFF841B */ volatile ADC1CLP0STR _ADC1CLP0; /* Plus-Side General Calibration Value 0 Register; 0xFFFF841C */ volatile ADC1CLMDSTR _ADC1CLMD; /* Minus-Side General Calibration Value D Register; 0xFFFF841E */ volatile ADC1CLMSSTR _ADC1CLMS; /* Minus-Side General Calibration Value S Register; 0xFFFF841F */ volatile ADC1CLM2STR _ADC1CLM2; /* Minus-Side General Calibration Value 2 Register; 0xFFFF8424 */ volatile ADC1CLM1STR _ADC1CLM1; /* Minus-Side General Calibration Value 1 Register; 0xFFFF8425 */ volatile ADC1CLM0STR _ADC1CLM0; /* Minus-Side General Calibration Value 0 Register; 0xFFFF8426 */ volatile ADC2SC1ASTR _ADC2SC1A; /* Status and Control Register 1A; 0xFFFF8440 */ volatile ADC2SC1BSTR _ADC2SC1B; /* Status and Control Register 1B; 0xFFFF8441 */ volatile ADC2CFG1STR _ADC2CFG1; /* Configuration Register 1; 0xFFFF8442 */ volatile ADC2CFG2STR _ADC2CFG2; /* Configuration Register 2; 0xFFFF8443 */ volatile ADC2SC2STR _ADC2SC2; /* Status and Control Register 2; 0xFFFF844C */ volatile ADC2SC3STR _ADC2SC3; /* Status and Control Register 3; 0xFFFF844D */ volatile ADC2CLPDSTR _ADC2CLPD; /* Plus-Side General Calibration Value D Register; 0xFFFF8454 */ volatile ADC2CLPSSTR _ADC2CLPS; /* Plus-Side General Calibration Value S Register; 0xFFFF8455 */ volatile ADC2CLP2STR _ADC2CLP2; /* Plus-Side General Calibration Value 2 Register; 0xFFFF845A */ volatile ADC2CLP1STR _ADC2CLP1; /* Plus-Side General Calibration Value 1 Register; 0xFFFF845B */ volatile ADC2CLP0STR _ADC2CLP0; /* Plus-Side General Calibration Value 0 Register; 0xFFFF845C */ volatile ADC2CLMDSTR _ADC2CLMD; /* Minus-Side General Calibration Value D Register; 0xFFFF845E */ volatile ADC2CLMSSTR _ADC2CLMS; /* Minus-Side General Calibration Value S Register; 0xFFFF845F */ volatile ADC2CLM2STR _ADC2CLM2; /* Minus-Side General Calibration Value 2 Register; 0xFFFF8464 */ volatile ADC2CLM1STR _ADC2CLM1; /* Minus-Side General Calibration Value 1 Register; 0xFFFF8465 */ volatile ADC2CLM0STR _ADC2CLM0; /* Minus-Side General Calibration Value 0 Register; 0xFFFF8466 */ volatile ADC3SC1ASTR _ADC3SC1A; /* Status and Control Register 1A; 0xFFFF8480 */ volatile ADC3SC1BSTR _ADC3SC1B; /* Status and Control Register 1B; 0xFFFF8481 */ volatile ADC3CFG1STR _ADC3CFG1; /* Configuration Register 1; 0xFFFF8482 */ volatile ADC3CFG2STR _ADC3CFG2; /* Configuration Register 2; 0xFFFF8483 */ volatile ADC3SC2STR _ADC3SC2; /* Status and Control Register 2; 0xFFFF848C */ volatile ADC3SC3STR _ADC3SC3; /* Status and Control Register 3; 0xFFFF848D */ volatile ADC3CLPDSTR _ADC3CLPD; /* Plus-Side General Calibration Value D Register; 0xFFFF8494 */ volatile ADC3CLPSSTR _ADC3CLPS; /* Plus-Side General Calibration Value S Register; 0xFFFF8495 */ volatile ADC3CLP2STR _ADC3CLP2; /* Plus-Side General Calibration Value 2 Register; 0xFFFF849A */ volatile ADC3CLP1STR _ADC3CLP1; /* Plus-Side General Calibration Value 1 Register; 0xFFFF849B */ volatile ADC3CLP0STR _ADC3CLP0; /* Plus-Side General Calibration Value 0 Register; 0xFFFF849C */ volatile ADC3CLMDSTR _ADC3CLMD; /* Minus-Side General Calibration Value D Register; 0xFFFF849E */ volatile ADC3CLMSSTR _ADC3CLMS; /* Minus-Side General Calibration Value S Register; 0xFFFF849F */ volatile ADC3CLM2STR _ADC3CLM2; /* Minus-Side General Calibration Value 2 Register; 0xFFFF84A4 */ volatile ADC3CLM1STR _ADC3CLM1; /* Minus-Side General Calibration Value 1 Register; 0xFFFF84A5 */ volatile ADC3CLM0STR _ADC3CLM0; /* Minus-Side General Calibration Value 0 Register; 0xFFFF84A6 */ volatile ADC4SC1ASTR _ADC4SC1A; /* Status and Control Register 1A; 0xFFFF84C0 */ volatile ADC4SC1BSTR _ADC4SC1B; /* Status and Control Register 1B; 0xFFFF84C1 */ volatile ADC4CFG1STR _ADC4CFG1; /* Configuration Register 1; 0xFFFF84C2 */ volatile ADC4CFG2STR _ADC4CFG2; /* Configuration Register 2; 0xFFFF84C3 */ volatile ADC4SC2STR _ADC4SC2; /* Status and Control Register 2; 0xFFFF84CC */ volatile ADC4SC3STR _ADC4SC3; /* Status and Control Register 3; 0xFFFF84CD */ volatile ADC4CLPDSTR _ADC4CLPD; /* Plus-Side General Calibration Value D Register; 0xFFFF84D4 */ volatile ADC4CLPSSTR _ADC4CLPS; /* Plus-Side General Calibration Value S Register; 0xFFFF84D5 */ volatile ADC4CLP2STR _ADC4CLP2; /* Plus-Side General Calibration Value 2 Register; 0xFFFF84DA */ volatile ADC4CLP1STR _ADC4CLP1; /* Plus-Side General Calibration Value 1 Register; 0xFFFF84DB */ volatile ADC4CLP0STR _ADC4CLP0; /* Plus-Side General Calibration Value 0 Register; 0xFFFF84DC */ volatile ADC4CLMDSTR _ADC4CLMD; /* Minus-Side General Calibration Value D Register; 0xFFFF84DE */ volatile ADC4CLMSSTR _ADC4CLMS; /* Minus-Side General Calibration Value S Register; 0xFFFF84DF */ volatile ADC4CLM2STR _ADC4CLM2; /* Minus-Side General Calibration Value 2 Register; 0xFFFF84E4 */ volatile ADC4CLM1STR _ADC4CLM1; /* Minus-Side General Calibration Value 1 Register; 0xFFFF84E5 */ volatile ADC4CLM0STR _ADC4CLM0; /* Minus-Side General Calibration Value 0 Register; 0xFFFF84E6 */ volatile PRACMP1CSSTR _PRACMP1CS; /* PRACMP1 Control and Status Register; 0xFFFF8520 */ volatile PRACMP1C0STR _PRACMP1C0; /* PRACMP1 Control 0 Register; 0xFFFF8521 */ volatile PRACMP1C1STR _PRACMP1C1; /* PRACMP1 Control 1 Register; 0xFFFF8522 */ volatile PRACMP1C2STR _PRACMP1C2; /* PRACMP1 Control 2 Register; 0xFFFF8523 */ volatile PRACMP2CSSTR _PRACMP2CS; /* PRACMP2 Control and Status Register; 0xFFFF8540 */ volatile PRACMP2C0STR _PRACMP2C0; /* PRACMP2 Control 0 Register; 0xFFFF8541 */ volatile PRACMP2C1STR _PRACMP2C1; /* PRACMP2 Control 1 Register; 0xFFFF8542 */ volatile PRACMP2C2STR _PRACMP2C2; /* PRACMP2 Control 2 Register; 0xFFFF8543 */ volatile MTIM1SCSTR _MTIM1SC; /* MTIM Clock Configuration Register; 0xFFFF8560 */ volatile MTIM1CLKSTR _MTIM1CLK; /* MTIM Clock Configuration Register; 0xFFFF8561 */ volatile MTIM1CNTSTR _MTIM1CNT; /* MTIM Counter Register; 0xFFFF8562 */ volatile MTIM1MODSTR _MTIM1MOD; /* MTIM Modulo Register; 0xFFFF8563 */ volatile MTIM2SCSTR _MTIM2SC; /* MTIM Clock Configuration Register; 0xFFFF8580 */ volatile MTIM2CLKSTR _MTIM2CLK; /* MTIM Clock Configuration Register; 0xFFFF8581 */ volatile MTIM2CNTSTR _MTIM2CNT; /* MTIM Counter Register; 0xFFFF8582 */ volatile MTIM2MODSTR _MTIM2MOD; /* MTIM Modulo Register; 0xFFFF8583 */ volatile MTIM3SCSTR _MTIM3SC; /* MTIM16 Status and Control Register; 0xFFFF85A0 */ volatile MTIM3CLKSTR _MTIM3CLK; /* MTIM16 Clock Configuration Register; 0xFFFF85A1 */ volatile CRCHSTR _CRCH; /* CRC High Register; 0xFFFF85C0 */ volatile CRCLSTR _CRCL; /* CRC Low Register; 0xFFFF85C1 */ volatile TRANSPOSESTR _TRANSPOSE; /* CRC Transpose Register; 0xFFFF85C2 */ volatile TPMSCSTR _TPMSC; /* TPM Status and Control Register; 0xFFFF8600 */ volatile TPMC0SCSTR _TPMC0SC; /* TPM Timer Channel 0 Status and Control Register; 0xFFFF8605 */ volatile TPMC1SCSTR _TPMC1SC; /* TPM Timer Channel 1 Status and Control Register; 0xFFFF8608 */ volatile LCDC0STR _LCDC0; /* LCD Control Register 0; 0xFFFF8700 */ volatile LCDC1STR _LCDC1; /* LCD Control Register 1; 0xFFFF8701 */ volatile LCDSUPPLYSTR _LCDSUPPLY; /* LCD Voltage Supply Register; 0xFFFF8702 */ volatile LCDRVCSTR _LCDRVC; /* LCD Regulated Voltage Control Register; 0xFFFF8703 */ volatile LCDBCTLSTR _LCDBCTL; /* LCD Blink Control Register; 0xFFFF8704 */ volatile LCDSSTR _LCDS; /* LCD Status Register; 0xFFFF8705 */ volatile LCDPEN0STR _LCDPEN0; /* LCD Pin Enable Register 0; 0xFFFF8706 */ volatile LCDPEN1STR _LCDPEN1; /* LCD Pin Enable Register 1; 0xFFFF8707 */ volatile LCDPEN2STR _LCDPEN2; /* LCD Pin Enable Register 2; 0xFFFF8708 */ volatile LCDPEN3STR _LCDPEN3; /* LCD Pin Enable Register 3; 0xFFFF8709 */ volatile LCDPEN4STR _LCDPEN4; /* LCD Pin Enable Register 4; 0xFFFF870A */ volatile LCDPEN5STR _LCDPEN5; /* LCD Pin Enable Register 5; 0xFFFF870B */ volatile LCDBPEN0STR _LCDBPEN0; /* LCD Backplane Enable Register 0; 0xFFFF870E */ volatile LCDBPEN1STR _LCDBPEN1; /* LCD Backplane Enable Register 1; 0xFFFF870F */ volatile LCDBPEN2STR _LCDBPEN2; /* LCD Backplane Enable Register 2; 0xFFFF8710 */ volatile LCDBPEN3STR _LCDBPEN3; /* LCD Backplane Enable Register 3; 0xFFFF8711 */ volatile LCDBPEN4STR _LCDBPEN4; /* LCD Backplane Enable Register 4; 0xFFFF8712 */ volatile LCDBPEN5STR _LCDBPEN5; /* LCD Backplane Enable Register 5; 0xFFFF8713 */ volatile LCDWF0STR _LCDWF0; /* LCD Waveform Register 0; 0xFFFF8716 */ volatile LCDWF1STR _LCDWF1; /* LCD Waveform Register 1; 0xFFFF8717 */ volatile LCDWF2STR _LCDWF2; /* LCD Waveform Register 2; 0xFFFF8718 */ volatile LCDWF3STR _LCDWF3; /* LCD Waveform Register 3; 0xFFFF8719 */ volatile LCDWF4STR _LCDWF4; /* LCD Waveform Register 4; 0xFFFF871A */ volatile LCDWF5STR _LCDWF5; /* LCD Waveform Register 5; 0xFFFF871B */ volatile LCDWF6STR _LCDWF6; /* LCD Waveform Register 6; 0xFFFF871C */ volatile LCDWF7STR _LCDWF7; /* LCD Waveform Register 7; 0xFFFF871D */ volatile LCDWF8STR _LCDWF8; /* LCD Waveform Register 8; 0xFFFF871E */ volatile LCDWF9STR _LCDWF9; /* LCD Waveform Register 9; 0xFFFF871F */ volatile LCDWF10STR _LCDWF10; /* LCD Waveform Register 10; 0xFFFF8720 */ volatile LCDWF11STR _LCDWF11; /* LCD Waveform Register 11; 0xFFFF8721 */ volatile LCDWF12STR _LCDWF12; /* LCD Waveform Register 12; 0xFFFF8722 */ volatile LCDWF13STR _LCDWF13; /* LCD Waveform Register 13; 0xFFFF8723 */ volatile LCDWF14STR _LCDWF14; /* LCD Waveform Register 14; 0xFFFF8724 */ volatile LCDWF15STR _LCDWF15; /* LCD Waveform Register 15; 0xFFFF8725 */ volatile LCDWF16STR _LCDWF16; /* LCD Waveform Register 16; 0xFFFF8726 */ volatile LCDWF17STR _LCDWF17; /* LCD Waveform Register 17; 0xFFFF8727 */ volatile LCDWF18STR _LCDWF18; /* LCD Waveform Register 18; 0xFFFF8728 */ volatile LCDWF19STR _LCDWF19; /* LCD Waveform Register 19; 0xFFFF8729 */ volatile LCDWF20STR _LCDWF20; /* LCD Waveform Register 20; 0xFFFF872A */ volatile LCDWF21STR _LCDWF21; /* LCD Waveform Register 21; 0xFFFF872B */ volatile LCDWF22STR _LCDWF22; /* LCD Waveform Register 22; 0xFFFF872C */ volatile LCDWF23STR _LCDWF23; /* LCD Waveform Register 23; 0xFFFF872D */ volatile LCDWF24STR _LCDWF24; /* LCD Waveform Register 24; 0xFFFF872E */ volatile LCDWF25STR _LCDWF25; /* LCD Waveform Register 25; 0xFFFF872F */ volatile LCDWF26STR _LCDWF26; /* LCD Waveform Register 26; 0xFFFF8730 */ volatile LCDWF27STR _LCDWF27; /* LCD Waveform Register 27; 0xFFFF8731 */ volatile LCDWF28STR _LCDWF28; /* LCD Waveform Register 28; 0xFFFF8732 */ volatile LCDWF29STR _LCDWF29; /* LCD Waveform Register 29; 0xFFFF8733 */ volatile LCDWF30STR _LCDWF30; /* LCD Waveform Register 30; 0xFFFF8734 */ volatile LCDWF31STR _LCDWF31; /* LCD Waveform Register 31; 0xFFFF8735 */ volatile LCDWF32STR _LCDWF32; /* LCD Waveform Register 32; 0xFFFF8736 */ volatile LCDWF33STR _LCDWF33; /* LCD Waveform Register 33; 0xFFFF8737 */ volatile LCDWF34STR _LCDWF34; /* LCD Waveform Register 34; 0xFFFF8738 */ volatile LCDWF35STR _LCDWF35; /* LCD Waveform Register 35; 0xFFFF8739 */ volatile LCDWF36STR _LCDWF36; /* LCD Waveform Register 36; 0xFFFF873A */ volatile LCDWF37STR _LCDWF37; /* LCD Waveform Register 37; 0xFFFF873B */ volatile LCDWF38STR _LCDWF38; /* LCD Waveform Register 38; 0xFFFF873C */ volatile LCDWF39STR _LCDWF39; /* LCD Waveform Register 39; 0xFFFF873D */ volatile LCDWF40STR _LCDWF40; /* LCD Waveform Register 40; 0xFFFF873E */ volatile LCDWF41STR _LCDWF41; /* LCD Waveform Register 41; 0xFFFF873F */ volatile LCDWF42STR _LCDWF42; /* LCD Waveform Register 42; 0xFFFF8740 */ volatile LCDWF43STR _LCDWF43; /* LCD Waveform Register 43; 0xFFFF8741 */ volatile F1CDIVSTR _F1CDIV; /* FLASH Clock Divider Register; 0xFFFF8780 */ volatile F1OPTSTR _F1OPT; /* Flash Options Register; 0xFFFF8781 */ volatile F1CNFGSTR _F1CNFG; /* Flash Configuration Register; 0xFFFF8783 */ volatile F1PROTSTR _F1PROT; /* Flash Protection Register; 0xFFFF8784 */ volatile F1STATSTR _F1STAT; /* Flash Status Register; 0xFFFF8785 */ volatile F1CMDSTR _F1CMD; /* Flash Command Register; 0xFFFF8786 */ volatile F2CDIVSTR _F2CDIV; /* FLASH Clock Divider Register; 0xFFFF87A0 */ volatile F2OPTSTR _F2OPT; /* Flash Options Register; 0xFFFF87A1 */ volatile F2CNFGSTR _F2CNFG; /* Flash Configuration Register; 0xFFFF87A3 */ volatile F2PROTSTR _F2PROT; /* Flash Protection Register; 0xFFFF87A4 */ volatile F2STATSTR _F2STAT; /* Flash Status Register; 0xFFFF87A5 */ volatile F2CMDSTR _F2CMD; /* Flash Command Register; 0xFFFF87A6 */ volatile INTC_FRCSTR _INTC_FRC; /* INTC Force Interrupt Register; 0xFFFFFFD0 */ volatile INTC_PL6P7STR _INTC_PL6P7; /* INTC Programmable Level 6, Priority 7 Register; 0xFFFFFFD8 */ volatile INTC_PL6P6STR _INTC_PL6P6; /* INTC Programmable Level 6, Priority 6 Register; 0xFFFFFFD9 */ volatile INTC_WCRSTR _INTC_WCR; /* INTC Wake-up Control Register; 0xFFFFFFDB */ volatile INTC_SFRCSTR _INTC_SFRC; /* INTC Set Interrupt Force Register; 0xFFFFFFDE */ volatile INTC_CFRCSTR _INTC_CFRC; /* INTC Clear Interrupt Force Register; 0xFFFFFFDF */ volatile INTC_SWIACKSTR _INTC_SWIACK; /* INTC Software IACK Register; 0xFFFFFFE0 */ volatile INTC_LVL1IACKSTR _INTC_LVL1IACK; /* INTC Level 1 IACK Register; 0xFFFFFFE4 */ volatile INTC_LVL2IACKSTR _INTC_LVL2IACK; /* INTC Level 2 IACK Register; 0xFFFFFFE8 */ volatile INTC_LVL3IACKSTR _INTC_LVL3IACK; /* INTC Level 3 IACK Register; 0xFFFFFFEC */ volatile INTC_LVL4IACKSTR _INTC_LVL4IACK; /* INTC Level 4 IACK Register; 0xFFFFFFF0 */ volatile INTC_LVL5IACKSTR _INTC_LVL5IACK; /* INTC Level 5 IACK Register; 0xFFFFFFF4 */ volatile INTC_LVL6IACKSTR _INTC_LVL6IACK; /* INTC Level 6 IACK Register; 0xFFFFFFF8 */ volatile INTC_LVL7IACKSTR _INTC_LVL7IACK; /* INTC Level 7 IACK Register; 0xFFFFFFFC */ /* * * * * 16-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile RGPIO_DIRSTR _RGPIO_DIR; /* RGPIO Data Direction Register; 0x00C00000 */ volatile RGPIO_DATASTR _RGPIO_DATA; /* RGPIO Data Register; 0x00C00002 */ volatile RGPIO_ENBSTR _RGPIO_ENB; /* RGPIO Pin Enable Register; 0x00C00004 */ volatile RGPIO_CLRSTR _RGPIO_CLR; /* RGPIO Clear Data Register; 0x00C00006 */ volatile RGPIO_SETSTR _RGPIO_SET; /* RGPIO Set Data Register; 0x00C0000A */ volatile RGPIO_TOGSTR _RGPIO_TOG; /* RGPIO Toggle Data Register; 0x00C0000E */ volatile SDIDSTR _SDID; /* System Device Identification Register; 0xFFFF8284 */ volatile SCI1BDSTR _SCI1BD; /* SCI1 Baud Rate Register; 0xFFFF82C0 */ volatile SCI2BDSTR _SCI2BD; /* SCI2 Baud Rate Register; 0xFFFF82E0 */ volatile SCI3BDSTR _SCI3BD; /* SCI3 Baud Rate Register; 0xFFFF8300 */ volatile SPI1D16STR _SPI1D16; /* SPI1 Data Register; 0xFFFF8324 */ volatile SPI1MSTR _SPI1M; /* SPI1 Match Register; 0xFFFF8326 */ volatile IICSLTSTR _IICSLT; /* IIC SCL Low Time Out register; 0xFFFF8388 */ volatile ADC1RASTR _ADC1RA; /* Data Result Register A; 0xFFFF8404 */ volatile ADC1RBSTR _ADC1RB; /* Data Result Register B; 0xFFFF8406 */ volatile ADC1CV1STR _ADC1CV1; /* Compare Value 1 Register; 0xFFFF8408 */ volatile ADC1CV2STR _ADC1CV2; /* Compare Value 2 Register; 0xFFFF840A */ volatile ADC1OFSSTR _ADC1OFS; /* Offset Correction Register; 0xFFFF840E */ volatile ADC1PGSTR _ADC1PG; /* Plus-Side Gain Register; 0xFFFF8410 */ volatile ADC1MGSTR _ADC1MG; /* Minus-Side Gain Register; 0xFFFF8412 */ volatile ADC1CLP4STR _ADC1CLP4; /* Plus-Side General Calibration Value 4 Register; 0xFFFF8416 */ volatile ADC1CLP3STR _ADC1CLP3; /* Plus-Side General Calibration Value 3 Register; 0xFFFF8418 */ volatile ADC1CLM4STR _ADC1CLM4; /* Minus-Side General Calibration Value 4 Register; 0xFFFF8420 */ volatile ADC1CLM3STR _ADC1CLM3; /* Minus-Side General Calibration Value 3 Register; 0xFFFF8422 */ volatile ADC2RASTR _ADC2RA; /* Data Result Register A; 0xFFFF8444 */ volatile ADC2RBSTR _ADC2RB; /* Data Result Register B; 0xFFFF8446 */ volatile ADC2CV1STR _ADC2CV1; /* Compare Value 1 Register; 0xFFFF8448 */ volatile ADC2CV2STR _ADC2CV2; /* Compare Value 2 Register; 0xFFFF844A */ volatile ADC2OFSSTR _ADC2OFS; /* Offset Correction Register; 0xFFFF844E */ volatile ADC2PGSTR _ADC2PG; /* Plus-Side Gain Register; 0xFFFF8450 */ volatile ADC2MGSTR _ADC2MG; /* Minus-Side Gain Register; 0xFFFF8452 */ volatile ADC2CLP4STR _ADC2CLP4; /* Plus-Side General Calibration Value 4 Register; 0xFFFF8456 */ volatile ADC2CLP3STR _ADC2CLP3; /* Plus-Side General Calibration Value 3 Register; 0xFFFF8458 */ volatile ADC2CLM4STR _ADC2CLM4; /* Minus-Side General Calibration Value 4 Register; 0xFFFF8460 */ volatile ADC2CLM3STR _ADC2CLM3; /* Minus-Side General Calibration Value 3 Register; 0xFFFF8462 */ volatile ADC3RASTR _ADC3RA; /* Data Result Register A; 0xFFFF8484 */ volatile ADC3RBSTR _ADC3RB; /* Data Result Register B; 0xFFFF8486 */ volatile ADC3CV1STR _ADC3CV1; /* Compare Value 1 Register; 0xFFFF8488 */ volatile ADC3CV2STR _ADC3CV2; /* Compare Value 2 Register; 0xFFFF848A */ volatile ADC3OFSSTR _ADC3OFS; /* Offset Correction Register; 0xFFFF848E */ volatile ADC3PGSTR _ADC3PG; /* Plus-Side Gain Register; 0xFFFF8490 */ volatile ADC3MGSTR _ADC3MG; /* Minus-Side Gain Register; 0xFFFF8492 */ volatile ADC3CLP4STR _ADC3CLP4; /* Plus-Side General Calibration Value 4 Register; 0xFFFF8496 */ volatile ADC3CLP3STR _ADC3CLP3; /* Plus-Side General Calibration Value 3 Register; 0xFFFF8498 */ volatile ADC3CLM4STR _ADC3CLM4; /* Minus-Side General Calibration Value 4 Register; 0xFFFF84A0 */ volatile ADC3CLM3STR _ADC3CLM3; /* Minus-Side General Calibration Value 3 Register; 0xFFFF84A2 */ volatile ADC4RASTR _ADC4RA; /* Data Result Register A; 0xFFFF84C4 */ volatile ADC4RBSTR _ADC4RB; /* Data Result Register B; 0xFFFF84C6 */ volatile ADC4CV1STR _ADC4CV1; /* Compare Value 1 Register; 0xFFFF84C8 */ volatile ADC4CV2STR _ADC4CV2; /* Compare Value 2 Register; 0xFFFF84CA */ volatile ADC4OFSSTR _ADC4OFS; /* Offset Correction Register; 0xFFFF84CE */ volatile ADC4PGSTR _ADC4PG; /* Plus-Side Gain Register; 0xFFFF84D0 */ volatile ADC4MGSTR _ADC4MG; /* Minus-Side Gain Register; 0xFFFF84D2 */ volatile ADC4CLP4STR _ADC4CLP4; /* Plus-Side General Calibration Value 4 Register; 0xFFFF84D6 */ volatile ADC4CLP3STR _ADC4CLP3; /* Plus-Side General Calibration Value 3 Register; 0xFFFF84D8 */ volatile ADC4CLM4STR _ADC4CLM4; /* Minus-Side General Calibration Value 4 Register; 0xFFFF84E0 */ volatile ADC4CLM3STR _ADC4CLM3; /* Minus-Side General Calibration Value 3 Register; 0xFFFF84E2 */ volatile MTIM3CNTSTR _MTIM3CNT; /* MTIM16 Counter Register; 0xFFFF85A2 */ volatile MTIM3MODSTR _MTIM3MOD; /* MTIM16 Modulo Register; 0xFFFF85A4 */ volatile TPMCNTSTR _TPMCNT; /* TPM Timer Counter Register; 0xFFFF8601 */ volatile TPMMODSTR _TPMMOD; /* TPM Timer Counter Modulo Register; 0xFFFF8603 */ volatile TPMC0VSTR _TPMC0V; /* TPM Timer Channel 0 Value Register; 0xFFFF8606 */ volatile TPMC1VSTR _TPMC1V; /* TPM Timer Channel 1 Value Register; 0xFFFF8609 */ volatile IRTC_YEARMON_bcdSTR _IRTC_YEARMON_bcd; /* RTC Year and Month Counters Register (BCD format); 0xFFFF8640 */ volatile IRTC_DAYS_bcdSTR _IRTC_DAYS_bcd; /* RTC Days Counter Register (BCD format); 0xFFFF8642 */ volatile IRTC_HOURMIN_bcdSTR _IRTC_HOURMIN_bcd; /* RTC Hours and Minutes Counter Register (BCD format); 0xFFFF8644 */ volatile IRTC_SECONDS_bcdSTR _IRTC_SECONDS_bcd; /* RTC Seconds Counter Register (BCD format); 0xFFFF8646 */ volatile IRTC_ALM_YRMON_bcdSTR _IRTC_ALM_YRMON_bcd; /* RTC Year and Month Alarm Register (BCD format); 0xFFFF8648 */ volatile IRTC_ALM_DAYS_bcdSTR _IRTC_ALM_DAYS_bcd; /* RTC Day Alarm Register (BCD format); 0xFFFF864A */ volatile IRTC_ALM_HM_bcdSTR _IRTC_ALM_HM_bcd; /* RTC Hours and Minutes Alarm Register (BCD format); 0xFFFF864C */ volatile IRTC_ALM_SEC_bcdSTR _IRTC_ALM_SEC_bcd; /* RTC Seconds Alarm Register (BCD format); 0xFFFF864E */ volatile IRTC_CTRLSTR _IRTC_CTRL; /* RTC Control Register; 0xFFFF8650 */ volatile IRTC_STATUSSTR _IRTC_STATUS; /* RTC Status Register; 0xFFFF8652 */ volatile IRTC_ISRSTR _IRTC_ISR; /* RTC Interrupt Status Register; 0xFFFF8654 */ volatile IRTC_IERSTR _IRTC_IER; /* RTC Interrupt Enable Register; 0xFFFF8656 */ volatile IRTC_COUNT_DN_bcdSTR _IRTC_COUNT_DN_bcd; /* RTC Countdown (Minutes) Timer Register (BCD format); 0xFFFF8658 */ volatile IRTC_CFG_DATASTR _IRTC_CFG_DATA; /* RTC Configuration Data Register; 0xFFFF8660 */ volatile IRTC_DST_HOUR_bcdSTR _IRTC_DST_HOUR_bcd; /* RTC Daylight Saving Hour Register; 0xFFFF8662 */ volatile IRTC_DST_MNTH_bcdSTR _IRTC_DST_MNTH_bcd; /* RTC Daylight Saving Month Register; 0xFFFF8664 */ volatile IRTC_DST_DAY_bcdSTR _IRTC_DST_DAY_bcd; /* RTC Daylight Saving Day Register; 0xFFFF8666 */ volatile IRTC_COMPENSTR _IRTC_COMPEN; /* RTC Compensation Register; 0xFFFF8668 */ volatile IRTC_TTSR_MY_bcdSTR _IRTC_TTSR_MY_bcd; /* RTC Tamper Time Stamp Month & Year Register; 0xFFFF866A */ volatile IRTC_TTSR_DAY_bcdSTR _IRTC_TTSR_DAY_bcd; /* RTC Tamper Time Stamp Day Register; 0xFFFF866C */ volatile IRTC_TTSR_HM_bcdSTR _IRTC_TTSR_HM_bcd; /* RTC Tamper Time Stamp Hours & Minutes Register; 0xFFFF866E */ volatile IRTC_TTSR_SEC_bcdSTR _IRTC_TTSR_SEC_bcd; /* RTC Tamper Time Stamp Seconds Register; 0xFFFF8670 */ volatile IRTC_UP_CNTR_HSTR _IRTC_UP_CNTR_H; /* RTC Up-Counter Higher Register; 0xFFFF8672 */ volatile IRTC_UP_CNTR_LSTR _IRTC_UP_CNTR_L; /* RTC Up-Counter Lower Register; 0xFFFF8674 */ volatile PDBSCSTR _PDBSC; /* PDB Status and Control Register; 0xFFFFE000 */ volatile PDBMODSTR _PDBMOD; /* PDB Counter Modulus Register; 0xFFFFE002 */ volatile PDBCNTSTR _PDBCNT; /* PDB Counter Value Register; 0xFFFFE004 */ volatile PDBIDLYSTR _PDBIDLY; /* PDB Interrupt Delay Register; 0xFFFFE006 */ volatile PDBCH1CRSTR _PDBCH1CR; /* PDB Channel 1 Control Register; 0xFFFFE008 */ volatile PDBCH1DLYASTR _PDBCH1DLYA; /* PDB Channel 1 Delay A Register; 0xFFFFE00A */ volatile PDBCH1DLYBSTR _PDBCH1DLYB; /* PDB Channel 1 Delay B Register; 0xFFFFE00C */ volatile PDBCH2CRSTR _PDBCH2CR; /* PDB Channel 2 Control Register; 0xFFFFE010 */ volatile PDBCH2DLYASTR _PDBCH2DLYA; /* PDB Channel 2 Delay A Register; 0xFFFFE012 */ volatile PDBCH2DLYBSTR _PDBCH2DLYB; /* PDB Channel 2 Delay B Register; 0xFFFFE014 */ volatile PDBCH3CRSTR _PDBCH3CR; /* PDB Channel 3 Control Register; 0xFFFFE018 */ volatile PDBCH3DLYASTR _PDBCH3DLYA; /* PDB Channel 3 Delay A Register; 0xFFFFE01A */ volatile PDBCH3DLYBSTR _PDBCH3DLYB; /* PDB Channel 3 Delay B Register; 0xFFFFE01C */ volatile PDBCH4CRSTR _PDBCH4CR; /* PDB Channel 4 Control Register; 0xFFFFE020 */ volatile PDBCH4DLYASTR _PDBCH4DLYA; /* PDB Channel 4 Delay A Register; 0xFFFFE022 */ volatile PDBCH4DLYBSTR _PDBCH4DLYB; /* PDB Channel 4 Delay B Register; 0xFFFFE024 */ volatile byte StandbyRAM[32]; /* IRTC RAM */ /*lint -restore */ /* EOF */