/* Based on CPU DB MCF51EM128_100, version 3.00.041 (RegistersPrg V2.31) */ /* ** ################################################################### ** Filename : mcf51em128.h ** Processor : MCF51EM128CLL ** FileFormat: V2.31 ** DataSheet : MCF51EM256RM Revision 6 6/30, 2009 ** Compiler : CodeWarrior compiler ** Date/Time : 14.1.2010, 16:28 ** Abstract : ** This header implements the mapping of I/O devices. ** ** Copyright : 1997 - 2010 Freescale Semiconductor, Inc. All Rights Reserved. ** ** http : www.freescale.com ** mail : support@freescale.com ** ** CPU Registers Revisions: ** - 28.05.2009, V3.00.0: ** - Renamed PDB registers/bits: PDBSCR -> PDBSC; PDBCOUNT -> PDBCNT; PDBIDELAY -> PDBIDLY; PDBCHnDELA[DELAY] -> PDBCHnDLYA/B[DELAYA/B]. ** - Added bits PDBCHnCR[ERRB,ERRA]. ** - REASON: Changes in the RM (from Rev. 3 to Rev. 5). ** - 30.06.2009, V3.00.1: ** - Added REQN5 bit to INTC_PL6P{7,6} register. Added SOPT2 register, SPI1CI register, SPI1C3[INTCLR] bit. Added PDB_err interrupt. ** - REASON: Changes in the RM (from Rev. 5 to Rev. 6). ** - 6.11.2009, V3.00.2: ** - Removed bits PDBMOD[MOD0:15], PDBCNT[COUNT0:15]. ** - REASON: Access to individual bits of counter/value registers is useless (#7787 in Issue Manager). ** - 14.01.2010, V3.00.3: ** - Fixed bug in the ALM shortcut in the IRTC YRMON register. ** ** File-Format-Revisions: ** - 03.07.2008, V2.24 : ** - Added support for bits with name starting with number (like "1HZ") ** - 28.11.2008, V2.25 : ** - StandBy RAM array declaration for ANSI-C added ** - 1.12.2008, V2.26 : ** - Duplication of bit (or bit-group) name with register name is not marked as a problem, is register is internal only and it is not displayed in I/O map. ** - 17.3.2009, V2.27 : ** - Merged bit-group is not generated, if the name matches with another bit name in the register ** - 6.4.2009, V2.28 : ** - Fixed generation of merged bits for bit-groups with a digit at the end, if group-name is defined in CPUDB ** - 3.8.2009, V2.29 : ** - If there is just one bits group matching register name, single bits are not generated ** - 10.9.2009, V2.30 : ** - Fixed generation of registers arrays. ** - 15.10.2009, V2.31 : ** - Changes have not affected this file (because they are related to another family) ** ** Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific ** derivative device. To avoid extra current drain from floating input pins, the user’s reset ** initialization routine in the application program must either enable on-chip pull-up devices ** or change the direction of unconnected pins to outputs so the pins do not float. ** ################################################################### */ #ifndef _MCF51EM128_H #define _MCF51EM128_H /* Types definition */ typedef unsigned char byte; typedef unsigned short word; typedef unsigned long dword; /* Watchdog reset macro */ #ifndef __RESET_WATCHDOG #ifdef _lint #define __RESET_WATCHDOG() /* empty */ #else #define __RESET_WATCHDOG() (void)(SRS = 0x55, SRS = 0xAA) #endif #endif /* __RESET_WATCHDOG */ #pragma options align=packed /**************** interrupt vector numbers ****************/ #define VectorNumber_INITSP 0 #define VectorNumber_INITPC 1 #define VectorNumber_Vaccerr 2 #define VectorNumber_Vadderr 3 #define VectorNumber_Viinstr 4 #define VectorNumber_VReserved5 5 #define VectorNumber_VReserved6 6 #define VectorNumber_VReserved7 7 #define VectorNumber_Vprviol 8 #define VectorNumber_Vtrace 9 #define VectorNumber_Vunilaop 10 #define VectorNumber_Vunilfop 11 #define VectorNumber_Vdbgi 12 #define VectorNumber_VReserved13 13 #define VectorNumber_Vferror 14 #define VectorNumber_VReserved15 15 #define VectorNumber_VReserved16 16 #define VectorNumber_VReserved17 17 #define VectorNumber_VReserved18 18 #define VectorNumber_VReserved19 19 #define VectorNumber_VReserved20 20 #define VectorNumber_VReserved21 21 #define VectorNumber_VReserved22 22 #define VectorNumber_VReserved23 23 #define VectorNumber_Vspuri 24 #define VectorNumber_VReserved25 25 #define VectorNumber_VReserved26 26 #define VectorNumber_VReserved27 27 #define VectorNumber_VReserved28 28 #define VectorNumber_VReserved29 29 #define VectorNumber_VReserved30 30 #define VectorNumber_VReserved31 31 #define VectorNumber_Vtrap0 32 #define VectorNumber_Vtrap1 33 #define VectorNumber_Vtrap2 34 #define VectorNumber_Vtrap3 35 #define VectorNumber_Vtrap4 36 #define VectorNumber_Vtrap5 37 #define VectorNumber_Vtrap6 38 #define VectorNumber_Vtrap7 39 #define VectorNumber_Vtrap8 40 #define VectorNumber_Vtrap9 41 #define VectorNumber_Vtrap10 42 #define VectorNumber_Vtrap11 43 #define VectorNumber_Vtrap12 44 #define VectorNumber_Vtrap13 45 #define VectorNumber_Vtrap14 46 #define VectorNumber_Vtrap15 47 #define VectorNumber_VReserved48 48 #define VectorNumber_VReserved49 49 #define VectorNumber_VReserved50 50 #define VectorNumber_VReserved51 51 #define VectorNumber_VReserved52 52 #define VectorNumber_VReserved53 53 #define VectorNumber_VReserved54 54 #define VectorNumber_VReserved55 55 #define VectorNumber_VReserved56 56 #define VectorNumber_VReserved57 57 #define VectorNumber_VReserved58 58 #define VectorNumber_VReserved59 59 #define VectorNumber_VReserved60 60 #define VectorNumber_Vunsinstr 61 #define VectorNumber_VReserved62 62 #define VectorNumber_VReserved63 63 #define VectorNumber_Virq 64 #define VectorNumber_Vlvd 65 #define VectorNumber_VReserved66 66 #define VectorNumber_Vpdb_err 67 #define VectorNumber_Vpdb 68 #define VectorNumber_Vtpmch0 69 #define VectorNumber_Vtpmch1 70 #define VectorNumber_Vtpmovf 71 #define VectorNumber_VReserved72 72 #define VectorNumber_Vmtim2 73 #define VectorNumber_Vmtim3 74 #define VectorNumber_Vmtim1 75 #define VectorNumber_Vadc4 76 #define VectorNumber_Vadc3 77 #define VectorNumber_Vadc2 78 #define VectorNumber_Vadc1 79 #define VectorNumber_Vspi1 80 #define VectorNumber_Vspi2 81 #define VectorNumber_Vspi3 82 #define VectorNumber_Vsci1err 83 #define VectorNumber_Vsci1rx 84 #define VectorNumber_Vsci1tx 85 #define VectorNumber_VReserved86 86 #define VectorNumber_Vsci2err 87 #define VectorNumber_Vsci2rx 88 #define VectorNumber_Vsci2tx 89 #define VectorNumber_Vsci3err 90 #define VectorNumber_Vsci3rx 91 #define VectorNumber_Vsci3tx 92 #define VectorNumber_VReserved93 93 #define VectorNumber_VReserved94 94 #define VectorNumber_Viic 95 #define VectorNumber_Vcmp1 96 #define VectorNumber_Vcmp2 97 #define VectorNumber_VReserved98 98 #define VectorNumber_Vkbi1 99 #define VectorNumber_Vkbi2 100 #define VectorNumber_VReserved101 101 #define VectorNumber_Vrtc 102 #define VectorNumber_VL7swi 103 #define VectorNumber_VL6swi 104 #define VectorNumber_VL5swi 105 #define VectorNumber_VL4swi 106 #define VectorNumber_VL3swi 107 #define VectorNumber_VL2swi 108 #define VectorNumber_VL1swi 109 #define VectorNumber_Vlcd 110 #define VectorNumber_VReserved111 111 #define VectorNumber_Vftsr1 112 #define VectorNumber_Vftsr2 113 #define VectorNumber_VReserved114 114 /**************** interrupt vector table ****************/ #define INITSP 0x00000000 #define INITPC 0x00000004 #define Vaccerr 0x00000008 #define Vadderr 0x0000000C #define Viinstr 0x00000010 #define VReserved5 0x00000014 #define VReserved6 0x00000018 #define VReserved7 0x0000001C #define Vprviol 0x00000020 #define Vtrace 0x00000024 #define Vunilaop 0x00000028 #define Vunilfop 0x0000002C #define Vdbgi 0x00000030 #define VReserved13 0x00000034 #define Vferror 0x00000038 #define VReserved15 0x0000003C #define VReserved16 0x00000040 #define VReserved17 0x00000044 #define VReserved18 0x00000048 #define VReserved19 0x0000004C #define VReserved20 0x00000050 #define VReserved21 0x00000054 #define VReserved22 0x00000058 #define VReserved23 0x0000005C #define Vspuri 0x00000060 #define VReserved25 0x00000064 #define VReserved26 0x00000068 #define VReserved27 0x0000006C #define VReserved28 0x00000070 #define VReserved29 0x00000074 #define VReserved30 0x00000078 #define VReserved31 0x0000007C #define Vtrap0 0x00000080 #define Vtrap1 0x00000084 #define Vtrap2 0x00000088 #define Vtrap3 0x0000008C #define Vtrap4 0x00000090 #define Vtrap5 0x00000094 #define Vtrap6 0x00000098 #define Vtrap7 0x0000009C #define Vtrap8 0x000000A0 #define Vtrap9 0x000000A4 #define Vtrap10 0x000000A8 #define Vtrap11 0x000000AC #define Vtrap12 0x000000B0 #define Vtrap13 0x000000B4 #define Vtrap14 0x000000B8 #define Vtrap15 0x000000BC #define VReserved48 0x000000C0 #define VReserved49 0x000000C4 #define VReserved50 0x000000C8 #define VReserved51 0x000000CC #define VReserved52 0x000000D0 #define VReserved53 0x000000D4 #define VReserved54 0x000000D8 #define VReserved55 0x000000DC #define VReserved56 0x000000E0 #define VReserved57 0x000000E4 #define VReserved58 0x000000E8 #define VReserved59 0x000000EC #define VReserved60 0x000000F0 #define Vunsinstr 0x000000F4 #define VReserved62 0x000000F8 #define VReserved63 0x000000FC #define Virq 0x00000100 #define Vlvd 0x00000104 #define VReserved66 0x00000108 #define Vpdb_err 0x0000010C #define Vpdb 0x00000110 #define Vtpmch0 0x00000114 #define Vtpmch1 0x00000118 #define Vtpmovf 0x0000011C #define VReserved72 0x00000120 #define Vmtim2 0x00000124 #define Vmtim3 0x00000128 #define Vmtim1 0x0000012C #define Vadc4 0x00000130 #define Vadc3 0x00000134 #define Vadc2 0x00000138 #define Vadc1 0x0000013C #define Vspi1 0x00000140 #define Vspi2 0x00000144 #define Vspi3 0x00000148 #define Vsci1err 0x0000014C #define Vsci1rx 0x00000150 #define Vsci1tx 0x00000154 #define VReserved86 0x00000158 #define Vsci2err 0x0000015C #define Vsci2rx 0x00000160 #define Vsci2tx 0x00000164 #define Vsci3err 0x00000168 #define Vsci3rx 0x0000016C #define Vsci3tx 0x00000170 #define VReserved93 0x00000174 #define VReserved94 0x00000178 #define Viic 0x0000017C #define Vcmp1 0x00000180 #define Vcmp2 0x00000184 #define VReserved98 0x00000188 #define Vkbi1 0x0000018C #define Vkbi2 0x00000190 #define VReserved101 0x00000194 #define Vrtc 0x00000198 #define VL7swi 0x0000019C #define VL6swi 0x000001A0 #define VL5swi 0x000001A4 #define VL4swi 0x000001A8 #define VL3swi 0x000001AC #define VL2swi 0x000001B0 #define VL1swi 0x000001B4 #define Vlcd 0x000001B8 #define VReserved111 0x000001BC #define Vftsr1 0x000001C0 #define Vftsr2 0x000001C4 #define VReserved114 0x000001C8 /**************** registers I/O map ****************/ /*** NV1FTRIM - Nonvolatile ICS Fine Trim 1; 0x000003FE ***/ typedef union { byte Byte; struct { byte FTRIM :1; /* ICS Fine Trim */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } NV1FTRIMSTR; /* Tip for register initialization in the user code: const byte NV1FTRIM_INIT @0x000003FE = ; */ #define _NV1FTRIM (*(const NV1FTRIMSTR *)0x000003FE) #define NV1FTRIM _NV1FTRIM.Byte #define NV1FTRIM_FTRIM _NV1FTRIM.Bits.FTRIM #define NV1FTRIM_FTRIM_MASK 1 /*** NV1ICSTRM - Nonvolatile ICS Trim Register 1; 0x000003FF ***/ typedef union { byte Byte; struct { byte TRIM0 :1; /* ICS Trim Setting, bit 0 */ byte TRIM1 :1; /* ICS Trim Setting, bit 1 */ byte TRIM2 :1; /* ICS Trim Setting, bit 2 */ byte TRIM3 :1; /* ICS Trim Setting, bit 3 */ byte TRIM4 :1; /* ICS Trim Setting, bit 4 */ byte TRIM5 :1; /* ICS Trim Setting, bit 5 */ byte TRIM6 :1; /* ICS Trim Setting, bit 6 */ byte TRIM7 :1; /* ICS Trim Setting, bit 7 */ } Bits; } NV1ICSTRMSTR; /* Tip for register initialization in the user code: const byte NV1ICSTRM_INIT @0x000003FF = ; */ #define _NV1ICSTRM (*(const NV1ICSTRMSTR *)0x000003FF) #define NV1ICSTRM _NV1ICSTRM.Byte #define NV1ICSTRM_TRIM0 _NV1ICSTRM.Bits.TRIM0 #define NV1ICSTRM_TRIM1 _NV1ICSTRM.Bits.TRIM1 #define NV1ICSTRM_TRIM2 _NV1ICSTRM.Bits.TRIM2 #define NV1ICSTRM_TRIM3 _NV1ICSTRM.Bits.TRIM3 #define NV1ICSTRM_TRIM4 _NV1ICSTRM.Bits.TRIM4 #define NV1ICSTRM_TRIM5 _NV1ICSTRM.Bits.TRIM5 #define NV1ICSTRM_TRIM6 _NV1ICSTRM.Bits.TRIM6 #define NV1ICSTRM_TRIM7 _NV1ICSTRM.Bits.TRIM7 #define NV1ICSTRM_TRIM0_MASK 1 #define NV1ICSTRM_TRIM1_MASK 2 #define NV1ICSTRM_TRIM2_MASK 4 #define NV1ICSTRM_TRIM3_MASK 8 #define NV1ICSTRM_TRIM4_MASK 16 #define NV1ICSTRM_TRIM5_MASK 32 #define NV1ICSTRM_TRIM6_MASK 64 #define NV1ICSTRM_TRIM7_MASK 128 /*** NV1BACKKEY0 - Backdoor Comparison Key 0; 0x00000400 ***/ typedef union { byte Byte; struct { byte KEY0 :1; /* Backdoor Comparison Key 0 Bits, bit 0 */ byte KEY1 :1; /* Backdoor Comparison Key 0 Bits, bit 1 */ byte KEY2 :1; /* Backdoor Comparison Key 0 Bits, bit 2 */ byte KEY3 :1; /* Backdoor Comparison Key 0 Bits, bit 3 */ byte KEY4 :1; /* Backdoor Comparison Key 0 Bits, bit 4 */ byte KEY5 :1; /* Backdoor Comparison Key 0 Bits, bit 5 */ byte KEY6 :1; /* Backdoor Comparison Key 0 Bits, bit 6 */ byte KEY7 :1; /* Backdoor Comparison Key 0 Bits, bit 7 */ } Bits; } NV1BACKKEY0STR; /* Tip for register initialization in the user code: const byte NV1BACKKEY0_INIT @0x00000400 = ; */ #define _NV1BACKKEY0 (*(const NV1BACKKEY0STR *)0x00000400) #define NV1BACKKEY0 _NV1BACKKEY0.Byte #define NV1BACKKEY0_KEY0 _NV1BACKKEY0.Bits.KEY0 #define NV1BACKKEY0_KEY1 _NV1BACKKEY0.Bits.KEY1 #define NV1BACKKEY0_KEY2 _NV1BACKKEY0.Bits.KEY2 #define NV1BACKKEY0_KEY3 _NV1BACKKEY0.Bits.KEY3 #define NV1BACKKEY0_KEY4 _NV1BACKKEY0.Bits.KEY4 #define NV1BACKKEY0_KEY5 _NV1BACKKEY0.Bits.KEY5 #define NV1BACKKEY0_KEY6 _NV1BACKKEY0.Bits.KEY6 #define NV1BACKKEY0_KEY7 _NV1BACKKEY0.Bits.KEY7 /* NV1BACKKEY_ARR: Access 8 NV1BACKKEYx registers in an array */ #define NV1BACKKEY_ARR ((volatile byte *) &NV1BACKKEY0) #define NV1BACKKEY0_KEY0_MASK 1 #define NV1BACKKEY0_KEY1_MASK 2 #define NV1BACKKEY0_KEY2_MASK 4 #define NV1BACKKEY0_KEY3_MASK 8 #define NV1BACKKEY0_KEY4_MASK 16 #define NV1BACKKEY0_KEY5_MASK 32 #define NV1BACKKEY0_KEY6_MASK 64 #define NV1BACKKEY0_KEY7_MASK 128 /*** NV1BACKKEY1 - Backdoor Comparison Key 1; 0x00000401 ***/ typedef union { byte Byte; struct { byte KEY0 :1; /* Backdoor Comparison Key 1 Bits, bit 0 */ byte KEY1 :1; /* Backdoor Comparison Key 1 Bits, bit 1 */ byte KEY2 :1; /* Backdoor Comparison Key 1 Bits, bit 2 */ byte KEY3 :1; /* Backdoor Comparison Key 1 Bits, bit 3 */ byte KEY4 :1; /* Backdoor Comparison Key 1 Bits, bit 4 */ byte KEY5 :1; /* Backdoor Comparison Key 1 Bits, bit 5 */ byte KEY6 :1; /* Backdoor Comparison Key 1 Bits, bit 6 */ byte KEY7 :1; /* Backdoor Comparison Key 1 Bits, bit 7 */ } Bits; } NV1BACKKEY1STR; /* Tip for register initialization in the user code: const byte NV1BACKKEY1_INIT @0x00000401 = ; */ #define _NV1BACKKEY1 (*(const NV1BACKKEY1STR *)0x00000401) #define NV1BACKKEY1 _NV1BACKKEY1.Byte #define NV1BACKKEY1_KEY0 _NV1BACKKEY1.Bits.KEY0 #define NV1BACKKEY1_KEY1 _NV1BACKKEY1.Bits.KEY1 #define NV1BACKKEY1_KEY2 _NV1BACKKEY1.Bits.KEY2 #define NV1BACKKEY1_KEY3 _NV1BACKKEY1.Bits.KEY3 #define NV1BACKKEY1_KEY4 _NV1BACKKEY1.Bits.KEY4 #define NV1BACKKEY1_KEY5 _NV1BACKKEY1.Bits.KEY5 #define NV1BACKKEY1_KEY6 _NV1BACKKEY1.Bits.KEY6 #define NV1BACKKEY1_KEY7 _NV1BACKKEY1.Bits.KEY7 #define NV1BACKKEY1_KEY0_MASK 1 #define NV1BACKKEY1_KEY1_MASK 2 #define NV1BACKKEY1_KEY2_MASK 4 #define NV1BACKKEY1_KEY3_MASK 8 #define NV1BACKKEY1_KEY4_MASK 16 #define NV1BACKKEY1_KEY5_MASK 32 #define NV1BACKKEY1_KEY6_MASK 64 #define NV1BACKKEY1_KEY7_MASK 128 /*** NV1BACKKEY2 - Backdoor Comparison Key 2; 0x00000402 ***/ typedef union { byte Byte; struct { byte KEY0 :1; /* Backdoor Comparison Key 2 Bits, bit 0 */ byte KEY1 :1; /* Backdoor Comparison Key 2 Bits, bit 1 */ byte KEY2 :1; /* Backdoor Comparison Key 2 Bits, bit 2 */ byte KEY3 :1; /* Backdoor Comparison Key 2 Bits, bit 3 */ byte KEY4 :1; /* Backdoor Comparison Key 2 Bits, bit 4 */ byte KEY5 :1; /* Backdoor Comparison Key 2 Bits, bit 5 */ byte KEY6 :1; /* Backdoor Comparison Key 2 Bits, bit 6 */ byte KEY7 :1; /* Backdoor Comparison Key 2 Bits, bit 7 */ } Bits; } NV1BACKKEY2STR; /* Tip for register initialization in the user code: const byte NV1BACKKEY2_INIT @0x00000402 = ; */ #define _NV1BACKKEY2 (*(const NV1BACKKEY2STR *)0x00000402) #define NV1BACKKEY2 _NV1BACKKEY2.Byte #define NV1BACKKEY2_KEY0 _NV1BACKKEY2.Bits.KEY0 #define NV1BACKKEY2_KEY1 _NV1BACKKEY2.Bits.KEY1 #define NV1BACKKEY2_KEY2 _NV1BACKKEY2.Bits.KEY2 #define NV1BACKKEY2_KEY3 _NV1BACKKEY2.Bits.KEY3 #define NV1BACKKEY2_KEY4 _NV1BACKKEY2.Bits.KEY4 #define NV1BACKKEY2_KEY5 _NV1BACKKEY2.Bits.KEY5 #define NV1BACKKEY2_KEY6 _NV1BACKKEY2.Bits.KEY6 #define NV1BACKKEY2_KEY7 _NV1BACKKEY2.Bits.KEY7 #define NV1BACKKEY2_KEY0_MASK 1 #define NV1BACKKEY2_KEY1_MASK 2 #define NV1BACKKEY2_KEY2_MASK 4 #define NV1BACKKEY2_KEY3_MASK 8 #define NV1BACKKEY2_KEY4_MASK 16 #define NV1BACKKEY2_KEY5_MASK 32 #define NV1BACKKEY2_KEY6_MASK 64 #define NV1BACKKEY2_KEY7_MASK 128 /*** NV1BACKKEY3 - Backdoor Comparison Key 3; 0x00000403 ***/ typedef union { byte Byte; struct { byte KEY0 :1; /* Backdoor Comparison Key 3 Bits, bit 0 */ byte KEY1 :1; /* Backdoor Comparison Key 3 Bits, bit 1 */ byte KEY2 :1; /* Backdoor Comparison Key 3 Bits, bit 2 */ byte KEY3 :1; /* Backdoor Comparison Key 3 Bits, bit 3 */ byte KEY4 :1; /* Backdoor Comparison Key 3 Bits, bit 4 */ byte KEY5 :1; /* Backdoor Comparison Key 3 Bits, bit 5 */ byte KEY6 :1; /* Backdoor Comparison Key 3 Bits, bit 6 */ byte KEY7 :1; /* Backdoor Comparison Key 3 Bits, bit 7 */ } Bits; } NV1BACKKEY3STR; /* Tip for register initialization in the user code: const byte NV1BACKKEY3_INIT @0x00000403 = ; */ #define _NV1BACKKEY3 (*(const NV1BACKKEY3STR *)0x00000403) #define NV1BACKKEY3 _NV1BACKKEY3.Byte #define NV1BACKKEY3_KEY0 _NV1BACKKEY3.Bits.KEY0 #define NV1BACKKEY3_KEY1 _NV1BACKKEY3.Bits.KEY1 #define NV1BACKKEY3_KEY2 _NV1BACKKEY3.Bits.KEY2 #define NV1BACKKEY3_KEY3 _NV1BACKKEY3.Bits.KEY3 #define NV1BACKKEY3_KEY4 _NV1BACKKEY3.Bits.KEY4 #define NV1BACKKEY3_KEY5 _NV1BACKKEY3.Bits.KEY5 #define NV1BACKKEY3_KEY6 _NV1BACKKEY3.Bits.KEY6 #define NV1BACKKEY3_KEY7 _NV1BACKKEY3.Bits.KEY7 #define NV1BACKKEY3_KEY0_MASK 1 #define NV1BACKKEY3_KEY1_MASK 2 #define NV1BACKKEY3_KEY2_MASK 4 #define NV1BACKKEY3_KEY3_MASK 8 #define NV1BACKKEY3_KEY4_MASK 16 #define NV1BACKKEY3_KEY5_MASK 32 #define NV1BACKKEY3_KEY6_MASK 64 #define NV1BACKKEY3_KEY7_MASK 128 /*** NV1BACKKEY4 - Backdoor Comparison Key 4; 0x00000404 ***/ typedef union { byte Byte; struct { byte KEY0 :1; /* Backdoor Comparison Key 4 Bits, bit 0 */ byte KEY1 :1; /* Backdoor Comparison Key 4 Bits, bit 1 */ byte KEY2 :1; /* Backdoor Comparison Key 4 Bits, bit 2 */ byte KEY3 :1; /* Backdoor Comparison Key 4 Bits, bit 3 */ byte KEY4 :1; /* Backdoor Comparison Key 4 Bits, bit 4 */ byte KEY5 :1; /* Backdoor Comparison Key 4 Bits, bit 5 */ byte KEY6 :1; /* Backdoor Comparison Key 4 Bits, bit 6 */ byte KEY7 :1; /* Backdoor Comparison Key 4 Bits, bit 7 */ } Bits; } NV1BACKKEY4STR; /* Tip for register initialization in the user code: const byte NV1BACKKEY4_INIT @0x00000404 = ; */ #define _NV1BACKKEY4 (*(const NV1BACKKEY4STR *)0x00000404) #define NV1BACKKEY4 _NV1BACKKEY4.Byte #define NV1BACKKEY4_KEY0 _NV1BACKKEY4.Bits.KEY0 #define NV1BACKKEY4_KEY1 _NV1BACKKEY4.Bits.KEY1 #define NV1BACKKEY4_KEY2 _NV1BACKKEY4.Bits.KEY2 #define NV1BACKKEY4_KEY3 _NV1BACKKEY4.Bits.KEY3 #define NV1BACKKEY4_KEY4 _NV1BACKKEY4.Bits.KEY4 #define NV1BACKKEY4_KEY5 _NV1BACKKEY4.Bits.KEY5 #define NV1BACKKEY4_KEY6 _NV1BACKKEY4.Bits.KEY6 #define NV1BACKKEY4_KEY7 _NV1BACKKEY4.Bits.KEY7 #define NV1BACKKEY4_KEY0_MASK 1 #define NV1BACKKEY4_KEY1_MASK 2 #define NV1BACKKEY4_KEY2_MASK 4 #define NV1BACKKEY4_KEY3_MASK 8 #define NV1BACKKEY4_KEY4_MASK 16 #define NV1BACKKEY4_KEY5_MASK 32 #define NV1BACKKEY4_KEY6_MASK 64 #define NV1BACKKEY4_KEY7_MASK 128 /*** NV1BACKKEY5 - Backdoor Comparison Key 5; 0x00000405 ***/ typedef union { byte Byte; struct { byte KEY0 :1; /* Backdoor Comparison Key 5 Bits, bit 0 */ byte KEY1 :1; /* Backdoor Comparison Key 5 Bits, bit 1 */ byte KEY2 :1; /* Backdoor Comparison Key 5 Bits, bit 2 */ byte KEY3 :1; /* Backdoor Comparison Key 5 Bits, bit 3 */ byte KEY4 :1; /* Backdoor Comparison Key 5 Bits, bit 4 */ byte KEY5 :1; /* Backdoor Comparison Key 5 Bits, bit 5 */ byte KEY6 :1; /* Backdoor Comparison Key 5 Bits, bit 6 */ byte KEY7 :1; /* Backdoor Comparison Key 5 Bits, bit 7 */ } Bits; } NV1BACKKEY5STR; /* Tip for register initialization in the user code: const byte NV1BACKKEY5_INIT @0x00000405 = ; */ #define _NV1BACKKEY5 (*(const NV1BACKKEY5STR *)0x00000405) #define NV1BACKKEY5 _NV1BACKKEY5.Byte #define NV1BACKKEY5_KEY0 _NV1BACKKEY5.Bits.KEY0 #define NV1BACKKEY5_KEY1 _NV1BACKKEY5.Bits.KEY1 #define NV1BACKKEY5_KEY2 _NV1BACKKEY5.Bits.KEY2 #define NV1BACKKEY5_KEY3 _NV1BACKKEY5.Bits.KEY3 #define NV1BACKKEY5_KEY4 _NV1BACKKEY5.Bits.KEY4 #define NV1BACKKEY5_KEY5 _NV1BACKKEY5.Bits.KEY5 #define NV1BACKKEY5_KEY6 _NV1BACKKEY5.Bits.KEY6 #define NV1BACKKEY5_KEY7 _NV1BACKKEY5.Bits.KEY7 #define NV1BACKKEY5_KEY0_MASK 1 #define NV1BACKKEY5_KEY1_MASK 2 #define NV1BACKKEY5_KEY2_MASK 4 #define NV1BACKKEY5_KEY3_MASK 8 #define NV1BACKKEY5_KEY4_MASK 16 #define NV1BACKKEY5_KEY5_MASK 32 #define NV1BACKKEY5_KEY6_MASK 64 #define NV1BACKKEY5_KEY7_MASK 128 /*** NV1BACKKEY6 - Backdoor Comparison Key 6; 0x00000406 ***/ typedef union { byte Byte; struct { byte KEY0 :1; /* Backdoor Comparison Key 6 Bits, bit 0 */ byte KEY1 :1; /* Backdoor Comparison Key 6 Bits, bit 1 */ byte KEY2 :1; /* Backdoor Comparison Key 6 Bits, bit 2 */ byte KEY3 :1; /* Backdoor Comparison Key 6 Bits, bit 3 */ byte KEY4 :1; /* Backdoor Comparison Key 6 Bits, bit 4 */ byte KEY5 :1; /* Backdoor Comparison Key 6 Bits, bit 5 */ byte KEY6 :1; /* Backdoor Comparison Key 6 Bits, bit 6 */ byte KEY7 :1; /* Backdoor Comparison Key 6 Bits, bit 7 */ } Bits; } NV1BACKKEY6STR; /* Tip for register initialization in the user code: const byte NV1BACKKEY6_INIT @0x00000406 = ; */ #define _NV1BACKKEY6 (*(const NV1BACKKEY6STR *)0x00000406) #define NV1BACKKEY6 _NV1BACKKEY6.Byte #define NV1BACKKEY6_KEY0 _NV1BACKKEY6.Bits.KEY0 #define NV1BACKKEY6_KEY1 _NV1BACKKEY6.Bits.KEY1 #define NV1BACKKEY6_KEY2 _NV1BACKKEY6.Bits.KEY2 #define NV1BACKKEY6_KEY3 _NV1BACKKEY6.Bits.KEY3 #define NV1BACKKEY6_KEY4 _NV1BACKKEY6.Bits.KEY4 #define NV1BACKKEY6_KEY5 _NV1BACKKEY6.Bits.KEY5 #define NV1BACKKEY6_KEY6 _NV1BACKKEY6.Bits.KEY6 #define NV1BACKKEY6_KEY7 _NV1BACKKEY6.Bits.KEY7 #define NV1BACKKEY6_KEY0_MASK 1 #define NV1BACKKEY6_KEY1_MASK 2 #define NV1BACKKEY6_KEY2_MASK 4 #define NV1BACKKEY6_KEY3_MASK 8 #define NV1BACKKEY6_KEY4_MASK 16 #define NV1BACKKEY6_KEY5_MASK 32 #define NV1BACKKEY6_KEY6_MASK 64 #define NV1BACKKEY6_KEY7_MASK 128 /*** NV1BACKKEY7 - Backdoor Comparison Key 7; 0x00000407 ***/ typedef union { byte Byte; struct { byte KEY0 :1; /* Backdoor Comparison Key 7 Bits, bit 0 */ byte KEY1 :1; /* Backdoor Comparison Key 7 Bits, bit 1 */ byte KEY2 :1; /* Backdoor Comparison Key 7 Bits, bit 2 */ byte KEY3 :1; /* Backdoor Comparison Key 7 Bits, bit 3 */ byte KEY4 :1; /* Backdoor Comparison Key 7 Bits, bit 4 */ byte KEY5 :1; /* Backdoor Comparison Key 7 Bits, bit 5 */ byte KEY6 :1; /* Backdoor Comparison Key 7 Bits, bit 6 */ byte KEY7 :1; /* Backdoor Comparison Key 7 Bits, bit 7 */ } Bits; } NV1BACKKEY7STR; /* Tip for register initialization in the user code: const byte NV1BACKKEY7_INIT @0x00000407 = ; */ #define _NV1BACKKEY7 (*(const NV1BACKKEY7STR *)0x00000407) #define NV1BACKKEY7 _NV1BACKKEY7.Byte #define NV1BACKKEY7_KEY0 _NV1BACKKEY7.Bits.KEY0 #define NV1BACKKEY7_KEY1 _NV1BACKKEY7.Bits.KEY1 #define NV1BACKKEY7_KEY2 _NV1BACKKEY7.Bits.KEY2 #define NV1BACKKEY7_KEY3 _NV1BACKKEY7.Bits.KEY3 #define NV1BACKKEY7_KEY4 _NV1BACKKEY7.Bits.KEY4 #define NV1BACKKEY7_KEY5 _NV1BACKKEY7.Bits.KEY5 #define NV1BACKKEY7_KEY6 _NV1BACKKEY7.Bits.KEY6 #define NV1BACKKEY7_KEY7 _NV1BACKKEY7.Bits.KEY7 #define NV1BACKKEY7_KEY0_MASK 1 #define NV1BACKKEY7_KEY1_MASK 2 #define NV1BACKKEY7_KEY2_MASK 4 #define NV1BACKKEY7_KEY3_MASK 8 #define NV1BACKKEY7_KEY4_MASK 16 #define NV1BACKKEY7_KEY5_MASK 32 #define NV1BACKKEY7_KEY6_MASK 64 #define NV1BACKKEY7_KEY7_MASK 128 /*** NV1PROT - Nonvolatile Flash Protection Register; 0x0000040D ***/ typedef union { byte Byte; struct { byte FPOPEN :1; /* Flash Protection Open */ byte FPS0 :1; /* Flash Protection Size, bit 0 */ byte FPS1 :1; /* Flash Protection Size, bit 1 */ byte FPS2 :1; /* Flash Protection Size, bit 2 */ byte FPS3 :1; /* Flash Protection Size, bit 3 */ byte FPS4 :1; /* Flash Protection Size, bit 4 */ byte FPS5 :1; /* Flash Protection Size, bit 5 */ byte FPS6 :1; /* Flash Protection Size, bit 6 */ } Bits; struct { byte :1; byte grpFPS :7; } MergedBits; } NV1PROTSTR; /* Tip for register initialization in the user code: const byte NV1PROT_INIT @0x0000040D = ; */ #define _NV1PROT (*(const NV1PROTSTR *)0x0000040D) #define NV1PROT _NV1PROT.Byte #define NV1PROT_FPOPEN _NV1PROT.Bits.FPOPEN #define NV1PROT_FPS0 _NV1PROT.Bits.FPS0 #define NV1PROT_FPS1 _NV1PROT.Bits.FPS1 #define NV1PROT_FPS2 _NV1PROT.Bits.FPS2 #define NV1PROT_FPS3 _NV1PROT.Bits.FPS3 #define NV1PROT_FPS4 _NV1PROT.Bits.FPS4 #define NV1PROT_FPS5 _NV1PROT.Bits.FPS5 #define NV1PROT_FPS6 _NV1PROT.Bits.FPS6 #define NV1PROT_FPS _NV1PROT.MergedBits.grpFPS #define NV1PROT_FPOPEN_MASK 1 #define NV1PROT_FPS0_MASK 2 #define NV1PROT_FPS1_MASK 4 #define NV1PROT_FPS2_MASK 8 #define NV1PROT_FPS3_MASK 16 #define NV1PROT_FPS4_MASK 32 #define NV1PROT_FPS5_MASK 64 #define NV1PROT_FPS6_MASK 128 #define NV1PROT_FPS_MASK 254 #define NV1PROT_FPS_BITNUM 1 /*** NV1OPT - Nonvolatile Flash Options Register; 0x0000040F ***/ typedef union { byte Byte; struct { byte SEC0 :1; /* Flash Security Bit 0 */ byte SEC1 :1; /* Flash Security Bit 1 */ byte :1; byte :1; byte :1; byte :1; byte KEYEN0 :1; /* Backdoor Key Security Enable Bit 0 */ byte KEYEN1 :1; /* Backdoor Key Security Enable Bit 1 */ } Bits; struct { byte grpSEC :2; byte :1; byte :1; byte :1; byte :1; byte grpKEYEN :2; } MergedBits; } NV1OPTSTR; /* Tip for register initialization in the user code: const byte NV1OPT_INIT @0x0000040F = ; */ #define _NV1OPT (*(const NV1OPTSTR *)0x0000040F) #define NV1OPT _NV1OPT.Byte #define NV1OPT_SEC0 _NV1OPT.Bits.SEC0 #define NV1OPT_SEC1 _NV1OPT.Bits.SEC1 #define NV1OPT_KEYEN0 _NV1OPT.Bits.KEYEN0 #define NV1OPT_KEYEN1 _NV1OPT.Bits.KEYEN1 #define NV1OPT_SEC _NV1OPT.MergedBits.grpSEC #define NV1OPT_KEYEN _NV1OPT.MergedBits.grpKEYEN #define NV1OPT_SEC0_MASK 1 #define NV1OPT_SEC1_MASK 2 #define NV1OPT_KEYEN0_MASK 64 #define NV1OPT_KEYEN1_MASK 128 #define NV1OPT_SEC_MASK 3 #define NV1OPT_SEC_BITNUM 0 #define NV1OPT_KEYEN_MASK 192 #define NV1OPT_KEYEN_BITNUM 6 /*** NV2FTRIM - Nonvolatile ICS Fine Trim 2; 0x000103FE ***/ typedef union { byte Byte; struct { byte FTRIM :1; /* ICS Fine Trim */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } NV2FTRIMSTR; /* Tip for register initialization in the user code: const byte NV2FTRIM_INIT @0x000103FE = ; */ #define _NV2FTRIM (*(const NV2FTRIMSTR *)0x000103FE) #define NV2FTRIM _NV2FTRIM.Byte #define NV2FTRIM_FTRIM _NV2FTRIM.Bits.FTRIM #define NV2FTRIM_FTRIM_MASK 1 /*** NV2ICSTRM - Nonvolatile ICS Trim Register 2; 0x000103FF ***/ typedef union { byte Byte; struct { byte TRIM0 :1; /* ICS Trim Setting, bit 0 */ byte TRIM1 :1; /* ICS Trim Setting, bit 1 */ byte TRIM2 :1; /* ICS Trim Setting, bit 2 */ byte TRIM3 :1; /* ICS Trim Setting, bit 3 */ byte TRIM4 :1; /* ICS Trim Setting, bit 4 */ byte TRIM5 :1; /* ICS Trim Setting, bit 5 */ byte TRIM6 :1; /* ICS Trim Setting, bit 6 */ byte TRIM7 :1; /* ICS Trim Setting, bit 7 */ } Bits; } NV2ICSTRMSTR; /* Tip for register initialization in the user code: const byte NV2ICSTRM_INIT @0x000103FF = ; */ #define _NV2ICSTRM (*(const NV2ICSTRMSTR *)0x000103FF) #define NV2ICSTRM _NV2ICSTRM.Byte #define NV2ICSTRM_TRIM0 _NV2ICSTRM.Bits.TRIM0 #define NV2ICSTRM_TRIM1 _NV2ICSTRM.Bits.TRIM1 #define NV2ICSTRM_TRIM2 _NV2ICSTRM.Bits.TRIM2 #define NV2ICSTRM_TRIM3 _NV2ICSTRM.Bits.TRIM3 #define NV2ICSTRM_TRIM4 _NV2ICSTRM.Bits.TRIM4 #define NV2ICSTRM_TRIM5 _NV2ICSTRM.Bits.TRIM5 #define NV2ICSTRM_TRIM6 _NV2ICSTRM.Bits.TRIM6 #define NV2ICSTRM_TRIM7 _NV2ICSTRM.Bits.TRIM7 #define NV2ICSTRM_TRIM0_MASK 1 #define NV2ICSTRM_TRIM1_MASK 2 #define NV2ICSTRM_TRIM2_MASK 4 #define NV2ICSTRM_TRIM3_MASK 8 #define NV2ICSTRM_TRIM4_MASK 16 #define NV2ICSTRM_TRIM5_MASK 32 #define NV2ICSTRM_TRIM6_MASK 64 #define NV2ICSTRM_TRIM7_MASK 128 /*** NV2BACKKEY0 - Backdoor Comparison Key 0; 0x00010400 ***/ typedef union { byte Byte; struct { byte KEY0 :1; /* Backdoor Comparison Key 0 Bits, bit 0 */ byte KEY1 :1; /* Backdoor Comparison Key 0 Bits, bit 1 */ byte KEY2 :1; /* Backdoor Comparison Key 0 Bits, bit 2 */ byte KEY3 :1; /* Backdoor Comparison Key 0 Bits, bit 3 */ byte KEY4 :1; /* Backdoor Comparison Key 0 Bits, bit 4 */ byte KEY5 :1; /* Backdoor Comparison Key 0 Bits, bit 5 */ byte KEY6 :1; /* Backdoor Comparison Key 0 Bits, bit 6 */ byte KEY7 :1; /* Backdoor Comparison Key 0 Bits, bit 7 */ } Bits; } NV2BACKKEY0STR; /* Tip for register initialization in the user code: const byte NV2BACKKEY0_INIT @0x00010400 = ; */ #define _NV2BACKKEY0 (*(const NV2BACKKEY0STR *)0x00010400) #define NV2BACKKEY0 _NV2BACKKEY0.Byte #define NV2BACKKEY0_KEY0 _NV2BACKKEY0.Bits.KEY0 #define NV2BACKKEY0_KEY1 _NV2BACKKEY0.Bits.KEY1 #define NV2BACKKEY0_KEY2 _NV2BACKKEY0.Bits.KEY2 #define NV2BACKKEY0_KEY3 _NV2BACKKEY0.Bits.KEY3 #define NV2BACKKEY0_KEY4 _NV2BACKKEY0.Bits.KEY4 #define NV2BACKKEY0_KEY5 _NV2BACKKEY0.Bits.KEY5 #define NV2BACKKEY0_KEY6 _NV2BACKKEY0.Bits.KEY6 #define NV2BACKKEY0_KEY7 _NV2BACKKEY0.Bits.KEY7 /* NV2BACKKEY_ARR: Access 8 NV2BACKKEYx registers in an array */ #define NV2BACKKEY_ARR ((volatile byte *) &NV2BACKKEY0) #define NV2BACKKEY0_KEY0_MASK 1 #define NV2BACKKEY0_KEY1_MASK 2 #define NV2BACKKEY0_KEY2_MASK 4 #define NV2BACKKEY0_KEY3_MASK 8 #define NV2BACKKEY0_KEY4_MASK 16 #define NV2BACKKEY0_KEY5_MASK 32 #define NV2BACKKEY0_KEY6_MASK 64 #define NV2BACKKEY0_KEY7_MASK 128 /*** NV2BACKKEY1 - Backdoor Comparison Key 1; 0x00010401 ***/ typedef union { byte Byte; struct { byte KEY0 :1; /* Backdoor Comparison Key 1 Bits, bit 0 */ byte KEY1 :1; /* Backdoor Comparison Key 1 Bits, bit 1 */ byte KEY2 :1; /* Backdoor Comparison Key 1 Bits, bit 2 */ byte KEY3 :1; /* Backdoor Comparison Key 1 Bits, bit 3 */ byte KEY4 :1; /* Backdoor Comparison Key 1 Bits, bit 4 */ byte KEY5 :1; /* Backdoor Comparison Key 1 Bits, bit 5 */ byte KEY6 :1; /* Backdoor Comparison Key 1 Bits, bit 6 */ byte KEY7 :1; /* Backdoor Comparison Key 1 Bits, bit 7 */ } Bits; } NV2BACKKEY1STR; /* Tip for register initialization in the user code: const byte NV2BACKKEY1_INIT @0x00010401 = ; */ #define _NV2BACKKEY1 (*(const NV2BACKKEY1STR *)0x00010401) #define NV2BACKKEY1 _NV2BACKKEY1.Byte #define NV2BACKKEY1_KEY0 _NV2BACKKEY1.Bits.KEY0 #define NV2BACKKEY1_KEY1 _NV2BACKKEY1.Bits.KEY1 #define NV2BACKKEY1_KEY2 _NV2BACKKEY1.Bits.KEY2 #define NV2BACKKEY1_KEY3 _NV2BACKKEY1.Bits.KEY3 #define NV2BACKKEY1_KEY4 _NV2BACKKEY1.Bits.KEY4 #define NV2BACKKEY1_KEY5 _NV2BACKKEY1.Bits.KEY5 #define NV2BACKKEY1_KEY6 _NV2BACKKEY1.Bits.KEY6 #define NV2BACKKEY1_KEY7 _NV2BACKKEY1.Bits.KEY7 #define NV2BACKKEY1_KEY0_MASK 1 #define NV2BACKKEY1_KEY1_MASK 2 #define NV2BACKKEY1_KEY2_MASK 4 #define NV2BACKKEY1_KEY3_MASK 8 #define NV2BACKKEY1_KEY4_MASK 16 #define NV2BACKKEY1_KEY5_MASK 32 #define NV2BACKKEY1_KEY6_MASK 64 #define NV2BACKKEY1_KEY7_MASK 128 /*** NV2BACKKEY2 - Backdoor Comparison Key 2; 0x00010402 ***/ typedef union { byte Byte; struct { byte KEY0 :1; /* Backdoor Comparison Key 2 Bits, bit 0 */ byte KEY1 :1; /* Backdoor Comparison Key 2 Bits, bit 1 */ byte KEY2 :1; /* Backdoor Comparison Key 2 Bits, bit 2 */ byte KEY3 :1; /* Backdoor Comparison Key 2 Bits, bit 3 */ byte KEY4 :1; /* Backdoor Comparison Key 2 Bits, bit 4 */ byte KEY5 :1; /* Backdoor Comparison Key 2 Bits, bit 5 */ byte KEY6 :1; /* Backdoor Comparison Key 2 Bits, bit 6 */ byte KEY7 :1; /* Backdoor Comparison Key 2 Bits, bit 7 */ } Bits; } NV2BACKKEY2STR; /* Tip for register initialization in the user code: const byte NV2BACKKEY2_INIT @0x00010402 = ; */ #define _NV2BACKKEY2 (*(const NV2BACKKEY2STR *)0x00010402) #define NV2BACKKEY2 _NV2BACKKEY2.Byte #define NV2BACKKEY2_KEY0 _NV2BACKKEY2.Bits.KEY0 #define NV2BACKKEY2_KEY1 _NV2BACKKEY2.Bits.KEY1 #define NV2BACKKEY2_KEY2 _NV2BACKKEY2.Bits.KEY2 #define NV2BACKKEY2_KEY3 _NV2BACKKEY2.Bits.KEY3 #define NV2BACKKEY2_KEY4 _NV2BACKKEY2.Bits.KEY4 #define NV2BACKKEY2_KEY5 _NV2BACKKEY2.Bits.KEY5 #define NV2BACKKEY2_KEY6 _NV2BACKKEY2.Bits.KEY6 #define NV2BACKKEY2_KEY7 _NV2BACKKEY2.Bits.KEY7 #define NV2BACKKEY2_KEY0_MASK 1 #define NV2BACKKEY2_KEY1_MASK 2 #define NV2BACKKEY2_KEY2_MASK 4 #define NV2BACKKEY2_KEY3_MASK 8 #define NV2BACKKEY2_KEY4_MASK 16 #define NV2BACKKEY2_KEY5_MASK 32 #define NV2BACKKEY2_KEY6_MASK 64 #define NV2BACKKEY2_KEY7_MASK 128 /*** NV2BACKKEY3 - Backdoor Comparison Key 3; 0x00010403 ***/ typedef union { byte Byte; struct { byte KEY0 :1; /* Backdoor Comparison Key 3 Bits, bit 0 */ byte KEY1 :1; /* Backdoor Comparison Key 3 Bits, bit 1 */ byte KEY2 :1; /* Backdoor Comparison Key 3 Bits, bit 2 */ byte KEY3 :1; /* Backdoor Comparison Key 3 Bits, bit 3 */ byte KEY4 :1; /* Backdoor Comparison Key 3 Bits, bit 4 */ byte KEY5 :1; /* Backdoor Comparison Key 3 Bits, bit 5 */ byte KEY6 :1; /* Backdoor Comparison Key 3 Bits, bit 6 */ byte KEY7 :1; /* Backdoor Comparison Key 3 Bits, bit 7 */ } Bits; } NV2BACKKEY3STR; /* Tip for register initialization in the user code: const byte NV2BACKKEY3_INIT @0x00010403 = ; */ #define _NV2BACKKEY3 (*(const NV2BACKKEY3STR *)0x00010403) #define NV2BACKKEY3 _NV2BACKKEY3.Byte #define NV2BACKKEY3_KEY0 _NV2BACKKEY3.Bits.KEY0 #define NV2BACKKEY3_KEY1 _NV2BACKKEY3.Bits.KEY1 #define NV2BACKKEY3_KEY2 _NV2BACKKEY3.Bits.KEY2 #define NV2BACKKEY3_KEY3 _NV2BACKKEY3.Bits.KEY3 #define NV2BACKKEY3_KEY4 _NV2BACKKEY3.Bits.KEY4 #define NV2BACKKEY3_KEY5 _NV2BACKKEY3.Bits.KEY5 #define NV2BACKKEY3_KEY6 _NV2BACKKEY3.Bits.KEY6 #define NV2BACKKEY3_KEY7 _NV2BACKKEY3.Bits.KEY7 #define NV2BACKKEY3_KEY0_MASK 1 #define NV2BACKKEY3_KEY1_MASK 2 #define NV2BACKKEY3_KEY2_MASK 4 #define NV2BACKKEY3_KEY3_MASK 8 #define NV2BACKKEY3_KEY4_MASK 16 #define NV2BACKKEY3_KEY5_MASK 32 #define NV2BACKKEY3_KEY6_MASK 64 #define NV2BACKKEY3_KEY7_MASK 128 /*** NV2BACKKEY4 - Backdoor Comparison Key 4; 0x00010404 ***/ typedef union { byte Byte; struct { byte KEY0 :1; /* Backdoor Comparison Key 4 Bits, bit 0 */ byte KEY1 :1; /* Backdoor Comparison Key 4 Bits, bit 1 */ byte KEY2 :1; /* Backdoor Comparison Key 4 Bits, bit 2 */ byte KEY3 :1; /* Backdoor Comparison Key 4 Bits, bit 3 */ byte KEY4 :1; /* Backdoor Comparison Key 4 Bits, bit 4 */ byte KEY5 :1; /* Backdoor Comparison Key 4 Bits, bit 5 */ byte KEY6 :1; /* Backdoor Comparison Key 4 Bits, bit 6 */ byte KEY7 :1; /* Backdoor Comparison Key 4 Bits, bit 7 */ } Bits; } NV2BACKKEY4STR; /* Tip for register initialization in the user code: const byte NV2BACKKEY4_INIT @0x00010404 = ; */ #define _NV2BACKKEY4 (*(const NV2BACKKEY4STR *)0x00010404) #define NV2BACKKEY4 _NV2BACKKEY4.Byte #define NV2BACKKEY4_KEY0 _NV2BACKKEY4.Bits.KEY0 #define NV2BACKKEY4_KEY1 _NV2BACKKEY4.Bits.KEY1 #define NV2BACKKEY4_KEY2 _NV2BACKKEY4.Bits.KEY2 #define NV2BACKKEY4_KEY3 _NV2BACKKEY4.Bits.KEY3 #define NV2BACKKEY4_KEY4 _NV2BACKKEY4.Bits.KEY4 #define NV2BACKKEY4_KEY5 _NV2BACKKEY4.Bits.KEY5 #define NV2BACKKEY4_KEY6 _NV2BACKKEY4.Bits.KEY6 #define NV2BACKKEY4_KEY7 _NV2BACKKEY4.Bits.KEY7 #define NV2BACKKEY4_KEY0_MASK 1 #define NV2BACKKEY4_KEY1_MASK 2 #define NV2BACKKEY4_KEY2_MASK 4 #define NV2BACKKEY4_KEY3_MASK 8 #define NV2BACKKEY4_KEY4_MASK 16 #define NV2BACKKEY4_KEY5_MASK 32 #define NV2BACKKEY4_KEY6_MASK 64 #define NV2BACKKEY4_KEY7_MASK 128 /*** NV2BACKKEY5 - Backdoor Comparison Key 5; 0x00010405 ***/ typedef union { byte Byte; struct { byte KEY0 :1; /* Backdoor Comparison Key 5 Bits, bit 0 */ byte KEY1 :1; /* Backdoor Comparison Key 5 Bits, bit 1 */ byte KEY2 :1; /* Backdoor Comparison Key 5 Bits, bit 2 */ byte KEY3 :1; /* Backdoor Comparison Key 5 Bits, bit 3 */ byte KEY4 :1; /* Backdoor Comparison Key 5 Bits, bit 4 */ byte KEY5 :1; /* Backdoor Comparison Key 5 Bits, bit 5 */ byte KEY6 :1; /* Backdoor Comparison Key 5 Bits, bit 6 */ byte KEY7 :1; /* Backdoor Comparison Key 5 Bits, bit 7 */ } Bits; } NV2BACKKEY5STR; /* Tip for register initialization in the user code: const byte NV2BACKKEY5_INIT @0x00010405 = ; */ #define _NV2BACKKEY5 (*(const NV2BACKKEY5STR *)0x00010405) #define NV2BACKKEY5 _NV2BACKKEY5.Byte #define NV2BACKKEY5_KEY0 _NV2BACKKEY5.Bits.KEY0 #define NV2BACKKEY5_KEY1 _NV2BACKKEY5.Bits.KEY1 #define NV2BACKKEY5_KEY2 _NV2BACKKEY5.Bits.KEY2 #define NV2BACKKEY5_KEY3 _NV2BACKKEY5.Bits.KEY3 #define NV2BACKKEY5_KEY4 _NV2BACKKEY5.Bits.KEY4 #define NV2BACKKEY5_KEY5 _NV2BACKKEY5.Bits.KEY5 #define NV2BACKKEY5_KEY6 _NV2BACKKEY5.Bits.KEY6 #define NV2BACKKEY5_KEY7 _NV2BACKKEY5.Bits.KEY7 #define NV2BACKKEY5_KEY0_MASK 1 #define NV2BACKKEY5_KEY1_MASK 2 #define NV2BACKKEY5_KEY2_MASK 4 #define NV2BACKKEY5_KEY3_MASK 8 #define NV2BACKKEY5_KEY4_MASK 16 #define NV2BACKKEY5_KEY5_MASK 32 #define NV2BACKKEY5_KEY6_MASK 64 #define NV2BACKKEY5_KEY7_MASK 128 /*** NV2BACKKEY6 - Backdoor Comparison Key 6; 0x00010406 ***/ typedef union { byte Byte; struct { byte KEY0 :1; /* Backdoor Comparison Key 6 Bits, bit 0 */ byte KEY1 :1; /* Backdoor Comparison Key 6 Bits, bit 1 */ byte KEY2 :1; /* Backdoor Comparison Key 6 Bits, bit 2 */ byte KEY3 :1; /* Backdoor Comparison Key 6 Bits, bit 3 */ byte KEY4 :1; /* Backdoor Comparison Key 6 Bits, bit 4 */ byte KEY5 :1; /* Backdoor Comparison Key 6 Bits, bit 5 */ byte KEY6 :1; /* Backdoor Comparison Key 6 Bits, bit 6 */ byte KEY7 :1; /* Backdoor Comparison Key 6 Bits, bit 7 */ } Bits; } NV2BACKKEY6STR; /* Tip for register initialization in the user code: const byte NV2BACKKEY6_INIT @0x00010406 = ; */ #define _NV2BACKKEY6 (*(const NV2BACKKEY6STR *)0x00010406) #define NV2BACKKEY6 _NV2BACKKEY6.Byte #define NV2BACKKEY6_KEY0 _NV2BACKKEY6.Bits.KEY0 #define NV2BACKKEY6_KEY1 _NV2BACKKEY6.Bits.KEY1 #define NV2BACKKEY6_KEY2 _NV2BACKKEY6.Bits.KEY2 #define NV2BACKKEY6_KEY3 _NV2BACKKEY6.Bits.KEY3 #define NV2BACKKEY6_KEY4 _NV2BACKKEY6.Bits.KEY4 #define NV2BACKKEY6_KEY5 _NV2BACKKEY6.Bits.KEY5 #define NV2BACKKEY6_KEY6 _NV2BACKKEY6.Bits.KEY6 #define NV2BACKKEY6_KEY7 _NV2BACKKEY6.Bits.KEY7 #define NV2BACKKEY6_KEY0_MASK 1 #define NV2BACKKEY6_KEY1_MASK 2 #define NV2BACKKEY6_KEY2_MASK 4 #define NV2BACKKEY6_KEY3_MASK 8 #define NV2BACKKEY6_KEY4_MASK 16 #define NV2BACKKEY6_KEY5_MASK 32 #define NV2BACKKEY6_KEY6_MASK 64 #define NV2BACKKEY6_KEY7_MASK 128 /*** NV2BACKKEY7 - Backdoor Comparison Key 7; 0x00010407 ***/ typedef union { byte Byte; struct { byte KEY0 :1; /* Backdoor Comparison Key 7 Bits, bit 0 */ byte KEY1 :1; /* Backdoor Comparison Key 7 Bits, bit 1 */ byte KEY2 :1; /* Backdoor Comparison Key 7 Bits, bit 2 */ byte KEY3 :1; /* Backdoor Comparison Key 7 Bits, bit 3 */ byte KEY4 :1; /* Backdoor Comparison Key 7 Bits, bit 4 */ byte KEY5 :1; /* Backdoor Comparison Key 7 Bits, bit 5 */ byte KEY6 :1; /* Backdoor Comparison Key 7 Bits, bit 6 */ byte KEY7 :1; /* Backdoor Comparison Key 7 Bits, bit 7 */ } Bits; } NV2BACKKEY7STR; /* Tip for register initialization in the user code: const byte NV2BACKKEY7_INIT @0x00010407 = ; */ #define _NV2BACKKEY7 (*(const NV2BACKKEY7STR *)0x00010407) #define NV2BACKKEY7 _NV2BACKKEY7.Byte #define NV2BACKKEY7_KEY0 _NV2BACKKEY7.Bits.KEY0 #define NV2BACKKEY7_KEY1 _NV2BACKKEY7.Bits.KEY1 #define NV2BACKKEY7_KEY2 _NV2BACKKEY7.Bits.KEY2 #define NV2BACKKEY7_KEY3 _NV2BACKKEY7.Bits.KEY3 #define NV2BACKKEY7_KEY4 _NV2BACKKEY7.Bits.KEY4 #define NV2BACKKEY7_KEY5 _NV2BACKKEY7.Bits.KEY5 #define NV2BACKKEY7_KEY6 _NV2BACKKEY7.Bits.KEY6 #define NV2BACKKEY7_KEY7 _NV2BACKKEY7.Bits.KEY7 #define NV2BACKKEY7_KEY0_MASK 1 #define NV2BACKKEY7_KEY1_MASK 2 #define NV2BACKKEY7_KEY2_MASK 4 #define NV2BACKKEY7_KEY3_MASK 8 #define NV2BACKKEY7_KEY4_MASK 16 #define NV2BACKKEY7_KEY5_MASK 32 #define NV2BACKKEY7_KEY6_MASK 64 #define NV2BACKKEY7_KEY7_MASK 128 /*** NV2PROT - Nonvolatile Flash Protection Register; 0x0001040D ***/ typedef union { byte Byte; struct { byte FPOPEN :1; /* Flash Protection Open */ byte FPS0 :1; /* Flash Protection Size, bit 0 */ byte FPS1 :1; /* Flash Protection Size, bit 1 */ byte FPS2 :1; /* Flash Protection Size, bit 2 */ byte FPS3 :1; /* Flash Protection Size, bit 3 */ byte FPS4 :1; /* Flash Protection Size, bit 4 */ byte FPS5 :1; /* Flash Protection Size, bit 5 */ byte FPS6 :1; /* Flash Protection Size, bit 6 */ } Bits; struct { byte :1; byte grpFPS :7; } MergedBits; } NV2PROTSTR; /* Tip for register initialization in the user code: const byte NV2PROT_INIT @0x0001040D = ; */ #define _NV2PROT (*(const NV2PROTSTR *)0x0001040D) #define NV2PROT _NV2PROT.Byte #define NV2PROT_FPOPEN _NV2PROT.Bits.FPOPEN #define NV2PROT_FPS0 _NV2PROT.Bits.FPS0 #define NV2PROT_FPS1 _NV2PROT.Bits.FPS1 #define NV2PROT_FPS2 _NV2PROT.Bits.FPS2 #define NV2PROT_FPS3 _NV2PROT.Bits.FPS3 #define NV2PROT_FPS4 _NV2PROT.Bits.FPS4 #define NV2PROT_FPS5 _NV2PROT.Bits.FPS5 #define NV2PROT_FPS6 _NV2PROT.Bits.FPS6 #define NV2PROT_FPS _NV2PROT.MergedBits.grpFPS #define NV2PROT_FPOPEN_MASK 1 #define NV2PROT_FPS0_MASK 2 #define NV2PROT_FPS1_MASK 4 #define NV2PROT_FPS2_MASK 8 #define NV2PROT_FPS3_MASK 16 #define NV2PROT_FPS4_MASK 32 #define NV2PROT_FPS5_MASK 64 #define NV2PROT_FPS6_MASK 128 #define NV2PROT_FPS_MASK 254 #define NV2PROT_FPS_BITNUM 1 /*** NV2OPT - Nonvolatile Flash Options Register; 0x0001040F ***/ typedef union { byte Byte; struct { byte SEC0 :1; /* Flash Security Bit 0 */ byte SEC1 :1; /* Flash Security Bit 1 */ byte :1; byte :1; byte :1; byte :1; byte KEYEN0 :1; /* Backdoor Key Security Enable Bit 0 */ byte KEYEN1 :1; /* Backdoor Key Security Enable Bit 1 */ } Bits; struct { byte grpSEC :2; byte :1; byte :1; byte :1; byte :1; byte grpKEYEN :2; } MergedBits; } NV2OPTSTR; /* Tip for register initialization in the user code: const byte NV2OPT_INIT @0x0001040F = ; */ #define _NV2OPT (*(const NV2OPTSTR *)0x0001040F) #define NV2OPT _NV2OPT.Byte #define NV2OPT_SEC0 _NV2OPT.Bits.SEC0 #define NV2OPT_SEC1 _NV2OPT.Bits.SEC1 #define NV2OPT_KEYEN0 _NV2OPT.Bits.KEYEN0 #define NV2OPT_KEYEN1 _NV2OPT.Bits.KEYEN1 #define NV2OPT_SEC _NV2OPT.MergedBits.grpSEC #define NV2OPT_KEYEN _NV2OPT.MergedBits.grpKEYEN #define NV2OPT_SEC0_MASK 1 #define NV2OPT_SEC1_MASK 2 #define NV2OPT_KEYEN0_MASK 64 #define NV2OPT_KEYEN1_MASK 128 #define NV2OPT_SEC_MASK 3 #define NV2OPT_SEC_BITNUM 0 #define NV2OPT_KEYEN_MASK 192 #define NV2OPT_KEYEN_BITNUM 6 /*** RGPIO_DIR - RGPIO Data Direction Register; 0x00C00000 ***/ typedef union { word Word; struct { word DIR0 :1; /* RGPIO data direction bit 0 */ word DIR1 :1; /* RGPIO data direction bit 1 */ word DIR2 :1; /* RGPIO data direction bit 2 */ word DIR3 :1; /* RGPIO data direction bit 3 */ word DIR4 :1; /* RGPIO data direction bit 4 */ word DIR5 :1; /* RGPIO data direction bit 5 */ word DIR6 :1; /* RGPIO data direction bit 6 */ word DIR7 :1; /* RGPIO data direction bit 7 */ word DIR8 :1; /* RGPIO data direction bit 8 */ word DIR9 :1; /* RGPIO data direction bit 9 */ word DIR10 :1; /* RGPIO data direction bit 10 */ word DIR11 :1; /* RGPIO data direction bit 11 */ word DIR12 :1; /* RGPIO data direction bit 12 */ word DIR13 :1; /* RGPIO data direction bit 13 */ word DIR14 :1; /* RGPIO data direction bit 14 */ word DIR15 :1; /* RGPIO data direction bit 15 */ } Bits; } RGPIO_DIRSTR; extern volatile RGPIO_DIRSTR _RGPIO_DIR @0x00C00000; #define RGPIO_DIR _RGPIO_DIR.Word #define RGPIO_DIR_DIR0 _RGPIO_DIR.Bits.DIR0 #define RGPIO_DIR_DIR1 _RGPIO_DIR.Bits.DIR1 #define RGPIO_DIR_DIR2 _RGPIO_DIR.Bits.DIR2 #define RGPIO_DIR_DIR3 _RGPIO_DIR.Bits.DIR3 #define RGPIO_DIR_DIR4 _RGPIO_DIR.Bits.DIR4 #define RGPIO_DIR_DIR5 _RGPIO_DIR.Bits.DIR5 #define RGPIO_DIR_DIR6 _RGPIO_DIR.Bits.DIR6 #define RGPIO_DIR_DIR7 _RGPIO_DIR.Bits.DIR7 #define RGPIO_DIR_DIR8 _RGPIO_DIR.Bits.DIR8 #define RGPIO_DIR_DIR9 _RGPIO_DIR.Bits.DIR9 #define RGPIO_DIR_DIR10 _RGPIO_DIR.Bits.DIR10 #define RGPIO_DIR_DIR11 _RGPIO_DIR.Bits.DIR11 #define RGPIO_DIR_DIR12 _RGPIO_DIR.Bits.DIR12 #define RGPIO_DIR_DIR13 _RGPIO_DIR.Bits.DIR13 #define RGPIO_DIR_DIR14 _RGPIO_DIR.Bits.DIR14 #define RGPIO_DIR_DIR15 _RGPIO_DIR.Bits.DIR15 #define RGPIO_DIR_DIR0_MASK 1 #define RGPIO_DIR_DIR1_MASK 2 #define RGPIO_DIR_DIR2_MASK 4 #define RGPIO_DIR_DIR3_MASK 8 #define RGPIO_DIR_DIR4_MASK 16 #define RGPIO_DIR_DIR5_MASK 32 #define RGPIO_DIR_DIR6_MASK 64 #define RGPIO_DIR_DIR7_MASK 128 #define RGPIO_DIR_DIR8_MASK 256 #define RGPIO_DIR_DIR9_MASK 512 #define RGPIO_DIR_DIR10_MASK 1024 #define RGPIO_DIR_DIR11_MASK 2048 #define RGPIO_DIR_DIR12_MASK 4096 #define RGPIO_DIR_DIR13_MASK 8192 #define RGPIO_DIR_DIR14_MASK 16384 #define RGPIO_DIR_DIR15_MASK 32768 /*** RGPIO_DATA - RGPIO Data Register; 0x00C00002 ***/ typedef union { word Word; struct { word DATA0 :1; /* RGPIO data bit 0 */ word DATA1 :1; /* RGPIO data bit 1 */ word DATA2 :1; /* RGPIO data bit 2 */ word DATA3 :1; /* RGPIO data bit 3 */ word DATA4 :1; /* RGPIO data bit 4 */ word DATA5 :1; /* RGPIO data bit 5 */ word DATA6 :1; /* RGPIO data bit 6 */ word DATA7 :1; /* RGPIO data bit 7 */ word DATA8 :1; /* RGPIO data bit 8 */ word DATA9 :1; /* RGPIO data bit 9 */ word DATA10 :1; /* RGPIO data bit 10 */ word DATA11 :1; /* RGPIO data bit 11 */ word DATA12 :1; /* RGPIO data bit 12 */ word DATA13 :1; /* RGPIO data bit 13 */ word DATA14 :1; /* RGPIO data bit 14 */ word DATA15 :1; /* RGPIO data bit 15 */ } Bits; } RGPIO_DATASTR; extern volatile RGPIO_DATASTR _RGPIO_DATA @0x00C00002; #define RGPIO_DATA _RGPIO_DATA.Word #define RGPIO_DATA_DATA0 _RGPIO_DATA.Bits.DATA0 #define RGPIO_DATA_DATA1 _RGPIO_DATA.Bits.DATA1 #define RGPIO_DATA_DATA2 _RGPIO_DATA.Bits.DATA2 #define RGPIO_DATA_DATA3 _RGPIO_DATA.Bits.DATA3 #define RGPIO_DATA_DATA4 _RGPIO_DATA.Bits.DATA4 #define RGPIO_DATA_DATA5 _RGPIO_DATA.Bits.DATA5 #define RGPIO_DATA_DATA6 _RGPIO_DATA.Bits.DATA6 #define RGPIO_DATA_DATA7 _RGPIO_DATA.Bits.DATA7 #define RGPIO_DATA_DATA8 _RGPIO_DATA.Bits.DATA8 #define RGPIO_DATA_DATA9 _RGPIO_DATA.Bits.DATA9 #define RGPIO_DATA_DATA10 _RGPIO_DATA.Bits.DATA10 #define RGPIO_DATA_DATA11 _RGPIO_DATA.Bits.DATA11 #define RGPIO_DATA_DATA12 _RGPIO_DATA.Bits.DATA12 #define RGPIO_DATA_DATA13 _RGPIO_DATA.Bits.DATA13 #define RGPIO_DATA_DATA14 _RGPIO_DATA.Bits.DATA14 #define RGPIO_DATA_DATA15 _RGPIO_DATA.Bits.DATA15 #define RGPIO_DATA_DATA0_MASK 1 #define RGPIO_DATA_DATA1_MASK 2 #define RGPIO_DATA_DATA2_MASK 4 #define RGPIO_DATA_DATA3_MASK 8 #define RGPIO_DATA_DATA4_MASK 16 #define RGPIO_DATA_DATA5_MASK 32 #define RGPIO_DATA_DATA6_MASK 64 #define RGPIO_DATA_DATA7_MASK 128 #define RGPIO_DATA_DATA8_MASK 256 #define RGPIO_DATA_DATA9_MASK 512 #define RGPIO_DATA_DATA10_MASK 1024 #define RGPIO_DATA_DATA11_MASK 2048 #define RGPIO_DATA_DATA12_MASK 4096 #define RGPIO_DATA_DATA13_MASK 8192 #define RGPIO_DATA_DATA14_MASK 16384 #define RGPIO_DATA_DATA15_MASK 32768 /*** RGPIO_ENB - RGPIO Pin Enable Register; 0x00C00004 ***/ typedef union { word Word; struct { word ENB0 :1; /* RGPIO enable bit 0 */ word ENB1 :1; /* RGPIO enable bit 1 */ word ENB2 :1; /* RGPIO enable bit 2 */ word ENB3 :1; /* RGPIO enable bit 3 */ word ENB4 :1; /* RGPIO enable bit 4 */ word ENB5 :1; /* RGPIO enable bit 5 */ word ENB6 :1; /* RGPIO enable bit 6 */ word ENB7 :1; /* RGPIO enable bit 7 */ word ENB8 :1; /* RGPIO enable bit 8 */ word ENB9 :1; /* RGPIO enable bit 9 */ word ENB10 :1; /* RGPIO enable bit 10 */ word ENB11 :1; /* RGPIO enable bit 11 */ word ENB12 :1; /* RGPIO enable bit 12 */ word ENB13 :1; /* RGPIO enable bit 13 */ word ENB14 :1; /* RGPIO enable bit 14 */ word ENB15 :1; /* RGPIO enable bit 15 */ } Bits; } RGPIO_ENBSTR; extern volatile RGPIO_ENBSTR _RGPIO_ENB @0x00C00004; #define RGPIO_ENB _RGPIO_ENB.Word #define RGPIO_ENB_ENB0 _RGPIO_ENB.Bits.ENB0 #define RGPIO_ENB_ENB1 _RGPIO_ENB.Bits.ENB1 #define RGPIO_ENB_ENB2 _RGPIO_ENB.Bits.ENB2 #define RGPIO_ENB_ENB3 _RGPIO_ENB.Bits.ENB3 #define RGPIO_ENB_ENB4 _RGPIO_ENB.Bits.ENB4 #define RGPIO_ENB_ENB5 _RGPIO_ENB.Bits.ENB5 #define RGPIO_ENB_ENB6 _RGPIO_ENB.Bits.ENB6 #define RGPIO_ENB_ENB7 _RGPIO_ENB.Bits.ENB7 #define RGPIO_ENB_ENB8 _RGPIO_ENB.Bits.ENB8 #define RGPIO_ENB_ENB9 _RGPIO_ENB.Bits.ENB9 #define RGPIO_ENB_ENB10 _RGPIO_ENB.Bits.ENB10 #define RGPIO_ENB_ENB11 _RGPIO_ENB.Bits.ENB11 #define RGPIO_ENB_ENB12 _RGPIO_ENB.Bits.ENB12 #define RGPIO_ENB_ENB13 _RGPIO_ENB.Bits.ENB13 #define RGPIO_ENB_ENB14 _RGPIO_ENB.Bits.ENB14 #define RGPIO_ENB_ENB15 _RGPIO_ENB.Bits.ENB15 #define RGPIO_ENB_ENB0_MASK 1 #define RGPIO_ENB_ENB1_MASK 2 #define RGPIO_ENB_ENB2_MASK 4 #define RGPIO_ENB_ENB3_MASK 8 #define RGPIO_ENB_ENB4_MASK 16 #define RGPIO_ENB_ENB5_MASK 32 #define RGPIO_ENB_ENB6_MASK 64 #define RGPIO_ENB_ENB7_MASK 128 #define RGPIO_ENB_ENB8_MASK 256 #define RGPIO_ENB_ENB9_MASK 512 #define RGPIO_ENB_ENB10_MASK 1024 #define RGPIO_ENB_ENB11_MASK 2048 #define RGPIO_ENB_ENB12_MASK 4096 #define RGPIO_ENB_ENB13_MASK 8192 #define RGPIO_ENB_ENB14_MASK 16384 #define RGPIO_ENB_ENB15_MASK 32768 /*** RGPIO_CLR - RGPIO Clear Data Register; 0x00C00006 ***/ typedef union { word Word; struct { word CLR0 :1; /* RGPIO clear data bit 0 */ word CLR1 :1; /* RGPIO clear data bit 1 */ word CLR2 :1; /* RGPIO clear data bit 2 */ word CLR3 :1; /* RGPIO clear data bit 3 */ word CLR4 :1; /* RGPIO clear data bit 4 */ word CLR5 :1; /* RGPIO clear data bit 5 */ word CLR6 :1; /* RGPIO clear data bit 6 */ word CLR7 :1; /* RGPIO clear data bit 7 */ word CLR8 :1; /* RGPIO clear data bit 8 */ word CLR9 :1; /* RGPIO clear data bit 9 */ word CLR10 :1; /* RGPIO clear data bit 10 */ word CLR11 :1; /* RGPIO clear data bit 11 */ word CLR12 :1; /* RGPIO clear data bit 12 */ word CLR13 :1; /* RGPIO clear data bit 13 */ word CLR14 :1; /* RGPIO clear data bit 14 */ word CLR15 :1; /* RGPIO clear data bit 15 */ } Bits; } RGPIO_CLRSTR; extern volatile RGPIO_CLRSTR _RGPIO_CLR @0x00C00006; #define RGPIO_CLR _RGPIO_CLR.Word #define RGPIO_CLR_CLR0 _RGPIO_CLR.Bits.CLR0 #define RGPIO_CLR_CLR1 _RGPIO_CLR.Bits.CLR1 #define RGPIO_CLR_CLR2 _RGPIO_CLR.Bits.CLR2 #define RGPIO_CLR_CLR3 _RGPIO_CLR.Bits.CLR3 #define RGPIO_CLR_CLR4 _RGPIO_CLR.Bits.CLR4 #define RGPIO_CLR_CLR5 _RGPIO_CLR.Bits.CLR5 #define RGPIO_CLR_CLR6 _RGPIO_CLR.Bits.CLR6 #define RGPIO_CLR_CLR7 _RGPIO_CLR.Bits.CLR7 #define RGPIO_CLR_CLR8 _RGPIO_CLR.Bits.CLR8 #define RGPIO_CLR_CLR9 _RGPIO_CLR.Bits.CLR9 #define RGPIO_CLR_CLR10 _RGPIO_CLR.Bits.CLR10 #define RGPIO_CLR_CLR11 _RGPIO_CLR.Bits.CLR11 #define RGPIO_CLR_CLR12 _RGPIO_CLR.Bits.CLR12 #define RGPIO_CLR_CLR13 _RGPIO_CLR.Bits.CLR13 #define RGPIO_CLR_CLR14 _RGPIO_CLR.Bits.CLR14 #define RGPIO_CLR_CLR15 _RGPIO_CLR.Bits.CLR15 #define RGPIO_CLR_CLR0_MASK 1 #define RGPIO_CLR_CLR1_MASK 2 #define RGPIO_CLR_CLR2_MASK 4 #define RGPIO_CLR_CLR3_MASK 8 #define RGPIO_CLR_CLR4_MASK 16 #define RGPIO_CLR_CLR5_MASK 32 #define RGPIO_CLR_CLR6_MASK 64 #define RGPIO_CLR_CLR7_MASK 128 #define RGPIO_CLR_CLR8_MASK 256 #define RGPIO_CLR_CLR9_MASK 512 #define RGPIO_CLR_CLR10_MASK 1024 #define RGPIO_CLR_CLR11_MASK 2048 #define RGPIO_CLR_CLR12_MASK 4096 #define RGPIO_CLR_CLR13_MASK 8192 #define RGPIO_CLR_CLR14_MASK 16384 #define RGPIO_CLR_CLR15_MASK 32768 /*** RGPIO_SET - RGPIO Set Data Register; 0x00C0000A ***/ typedef union { word Word; struct { word SET0 :1; /* RGPIO set data bit 0 */ word SET1 :1; /* RGPIO set data bit 1 */ word SET2 :1; /* RGPIO set data bit 2 */ word SET3 :1; /* RGPIO set data bit 3 */ word SET4 :1; /* RGPIO set data bit 4 */ word SET5 :1; /* RGPIO set data bit 5 */ word SET6 :1; /* RGPIO set data bit 6 */ word SET7 :1; /* RGPIO set data bit 7 */ word SET8 :1; /* RGPIO set data bit 8 */ word SET9 :1; /* RGPIO set data bit 9 */ word SET10 :1; /* RGPIO set data bit 10 */ word SET11 :1; /* RGPIO set data bit 11 */ word SET12 :1; /* RGPIO set data bit 12 */ word SET13 :1; /* RGPIO set data bit 13 */ word SET14 :1; /* RGPIO set data bit 14 */ word SET15 :1; /* RGPIO set data bit 15 */ } Bits; } RGPIO_SETSTR; extern volatile RGPIO_SETSTR _RGPIO_SET @0x00C0000A; #define RGPIO_SET _RGPIO_SET.Word #define RGPIO_SET_SET0 _RGPIO_SET.Bits.SET0 #define RGPIO_SET_SET1 _RGPIO_SET.Bits.SET1 #define RGPIO_SET_SET2 _RGPIO_SET.Bits.SET2 #define RGPIO_SET_SET3 _RGPIO_SET.Bits.SET3 #define RGPIO_SET_SET4 _RGPIO_SET.Bits.SET4 #define RGPIO_SET_SET5 _RGPIO_SET.Bits.SET5 #define RGPIO_SET_SET6 _RGPIO_SET.Bits.SET6 #define RGPIO_SET_SET7 _RGPIO_SET.Bits.SET7 #define RGPIO_SET_SET8 _RGPIO_SET.Bits.SET8 #define RGPIO_SET_SET9 _RGPIO_SET.Bits.SET9 #define RGPIO_SET_SET10 _RGPIO_SET.Bits.SET10 #define RGPIO_SET_SET11 _RGPIO_SET.Bits.SET11 #define RGPIO_SET_SET12 _RGPIO_SET.Bits.SET12 #define RGPIO_SET_SET13 _RGPIO_SET.Bits.SET13 #define RGPIO_SET_SET14 _RGPIO_SET.Bits.SET14 #define RGPIO_SET_SET15 _RGPIO_SET.Bits.SET15 #define RGPIO_SET_SET0_MASK 1 #define RGPIO_SET_SET1_MASK 2 #define RGPIO_SET_SET2_MASK 4 #define RGPIO_SET_SET3_MASK 8 #define RGPIO_SET_SET4_MASK 16 #define RGPIO_SET_SET5_MASK 32 #define RGPIO_SET_SET6_MASK 64 #define RGPIO_SET_SET7_MASK 128 #define RGPIO_SET_SET8_MASK 256 #define RGPIO_SET_SET9_MASK 512 #define RGPIO_SET_SET10_MASK 1024 #define RGPIO_SET_SET11_MASK 2048 #define RGPIO_SET_SET12_MASK 4096 #define RGPIO_SET_SET13_MASK 8192 #define RGPIO_SET_SET14_MASK 16384 #define RGPIO_SET_SET15_MASK 32768 /*** RGPIO_TOG - RGPIO Toggle Data Register; 0x00C0000E ***/ typedef union { word Word; struct { word TOG0 :1; /* RGPIO toggle data bit 0 */ word TOG1 :1; /* RGPIO toggle data bit 1 */ word TOG2 :1; /* RGPIO toggle data bit 2 */ word TOG3 :1; /* RGPIO toggle data bit 3 */ word TOG4 :1; /* RGPIO toggle data bit 4 */ word TOG5 :1; /* RGPIO toggle data bit 5 */ word TOG6 :1; /* RGPIO toggle data bit 6 */ word TOG7 :1; /* RGPIO toggle data bit 7 */ word TOG8 :1; /* RGPIO toggle data bit 8 */ word TOG9 :1; /* RGPIO toggle data bit 9 */ word TOG10 :1; /* RGPIO toggle data bit 10 */ word TOG11 :1; /* RGPIO toggle data bit 11 */ word TOG12 :1; /* RGPIO toggle data bit 12 */ word TOG13 :1; /* RGPIO toggle data bit 13 */ word TOG14 :1; /* RGPIO toggle data bit 14 */ word TOG15 :1; /* RGPIO toggle data bit 15 */ } Bits; } RGPIO_TOGSTR; extern volatile RGPIO_TOGSTR _RGPIO_TOG @0x00C0000E; #define RGPIO_TOG _RGPIO_TOG.Word #define RGPIO_TOG_TOG0 _RGPIO_TOG.Bits.TOG0 #define RGPIO_TOG_TOG1 _RGPIO_TOG.Bits.TOG1 #define RGPIO_TOG_TOG2 _RGPIO_TOG.Bits.TOG2 #define RGPIO_TOG_TOG3 _RGPIO_TOG.Bits.TOG3 #define RGPIO_TOG_TOG4 _RGPIO_TOG.Bits.TOG4 #define RGPIO_TOG_TOG5 _RGPIO_TOG.Bits.TOG5 #define RGPIO_TOG_TOG6 _RGPIO_TOG.Bits.TOG6 #define RGPIO_TOG_TOG7 _RGPIO_TOG.Bits.TOG7 #define RGPIO_TOG_TOG8 _RGPIO_TOG.Bits.TOG8 #define RGPIO_TOG_TOG9 _RGPIO_TOG.Bits.TOG9 #define RGPIO_TOG_TOG10 _RGPIO_TOG.Bits.TOG10 #define RGPIO_TOG_TOG11 _RGPIO_TOG.Bits.TOG11 #define RGPIO_TOG_TOG12 _RGPIO_TOG.Bits.TOG12 #define RGPIO_TOG_TOG13 _RGPIO_TOG.Bits.TOG13 #define RGPIO_TOG_TOG14 _RGPIO_TOG.Bits.TOG14 #define RGPIO_TOG_TOG15 _RGPIO_TOG.Bits.TOG15 #define RGPIO_TOG_TOG0_MASK 1 #define RGPIO_TOG_TOG1_MASK 2 #define RGPIO_TOG_TOG2_MASK 4 #define RGPIO_TOG_TOG3_MASK 8 #define RGPIO_TOG_TOG4_MASK 16 #define RGPIO_TOG_TOG5_MASK 32 #define RGPIO_TOG_TOG6_MASK 64 #define RGPIO_TOG_TOG7_MASK 128 #define RGPIO_TOG_TOG8_MASK 256 #define RGPIO_TOG_TOG9_MASK 512 #define RGPIO_TOG_TOG10_MASK 1024 #define RGPIO_TOG_TOG11_MASK 2048 #define RGPIO_TOG_TOG12_MASK 4096 #define RGPIO_TOG_TOG13_MASK 8192 #define RGPIO_TOG_TOG14_MASK 16384 #define RGPIO_TOG_TOG15_MASK 32768 /*** PTAD - Port A Data Register; 0xFFFF8000 ***/ typedef union { byte Byte; struct { byte PTAD0 :1; /* Port A Data Register Bit 0 */ byte PTAD1 :1; /* Port A Data Register Bit 1 */ byte PTAD2 :1; /* Port A Data Register Bit 2 */ byte PTAD3 :1; /* Port A Data Register Bit 3 */ byte PTAD4 :1; /* Port A Data Register Bit 4 */ byte PTAD5 :1; /* Port A Data Register Bit 5 */ byte PTAD6 :1; /* Port A Data Register Bit 6 */ byte PTAD7 :1; /* Port A Data Register Bit 7 */ } Bits; } PTADSTR; extern volatile PTADSTR _PTAD @0xFFFF8000; #define PTAD _PTAD.Byte #define PTAD_PTAD0 _PTAD.Bits.PTAD0 #define PTAD_PTAD1 _PTAD.Bits.PTAD1 #define PTAD_PTAD2 _PTAD.Bits.PTAD2 #define PTAD_PTAD3 _PTAD.Bits.PTAD3 #define PTAD_PTAD4 _PTAD.Bits.PTAD4 #define PTAD_PTAD5 _PTAD.Bits.PTAD5 #define PTAD_PTAD6 _PTAD.Bits.PTAD6 #define PTAD_PTAD7 _PTAD.Bits.PTAD7 #define PTAD_PTAD0_MASK 1 #define PTAD_PTAD1_MASK 2 #define PTAD_PTAD2_MASK 4 #define PTAD_PTAD3_MASK 8 #define PTAD_PTAD4_MASK 16 #define PTAD_PTAD5_MASK 32 #define PTAD_PTAD6_MASK 64 #define PTAD_PTAD7_MASK 128 /*** PTADD - Port A Data Direction Register; 0xFFFF8001 ***/ typedef union { byte Byte; struct { byte PTADD0 :1; /* Data Direction for Port A Bit 0 */ byte PTADD1 :1; /* Data Direction for Port A Bit 1 */ byte PTADD2 :1; /* Data Direction for Port A Bit 2 */ byte PTADD3 :1; /* Data Direction for Port A Bit 3 */ byte PTADD4 :1; /* Data Direction for Port A Bit 4 */ byte PTADD5 :1; /* Data Direction for Port A Bit 5 */ byte PTADD6 :1; /* Data Direction for Port A Bit 6 */ byte PTADD7 :1; /* Data Direction for Port A Bit 7 */ } Bits; } PTADDSTR; extern volatile PTADDSTR _PTADD @0xFFFF8001; #define PTADD _PTADD.Byte #define PTADD_PTADD0 _PTADD.Bits.PTADD0 #define PTADD_PTADD1 _PTADD.Bits.PTADD1 #define PTADD_PTADD2 _PTADD.Bits.PTADD2 #define PTADD_PTADD3 _PTADD.Bits.PTADD3 #define PTADD_PTADD4 _PTADD.Bits.PTADD4 #define PTADD_PTADD5 _PTADD.Bits.PTADD5 #define PTADD_PTADD6 _PTADD.Bits.PTADD6 #define PTADD_PTADD7 _PTADD.Bits.PTADD7 #define PTADD_PTADD0_MASK 1 #define PTADD_PTADD1_MASK 2 #define PTADD_PTADD2_MASK 4 #define PTADD_PTADD3_MASK 8 #define PTADD_PTADD4_MASK 16 #define PTADD_PTADD5_MASK 32 #define PTADD_PTADD6_MASK 64 #define PTADD_PTADD7_MASK 128 /*** PTASET - Port A Data Set Register; 0xFFFF8002 ***/ typedef union { byte Byte; struct { byte PTASET0 :1; /* Data Set for Port A Bit 0 */ byte PTASET1 :1; /* Data Set for Port A Bit 1 */ byte PTASET2 :1; /* Data Set for Port A Bit 2 */ byte PTASET3 :1; /* Data Set for Port A Bit 3 */ byte PTASET4 :1; /* Data Set for Port A Bit 4 */ byte PTASET5 :1; /* Data Set for Port A Bit 5 */ byte PTASET6 :1; /* Data Set for Port A Bit 6 */ byte PTASET7 :1; /* Data Set for Port A Bit 7 */ } Bits; } PTASETSTR; extern volatile PTASETSTR _PTASET @0xFFFF8002; #define PTASET _PTASET.Byte #define PTASET_PTASET0 _PTASET.Bits.PTASET0 #define PTASET_PTASET1 _PTASET.Bits.PTASET1 #define PTASET_PTASET2 _PTASET.Bits.PTASET2 #define PTASET_PTASET3 _PTASET.Bits.PTASET3 #define PTASET_PTASET4 _PTASET.Bits.PTASET4 #define PTASET_PTASET5 _PTASET.Bits.PTASET5 #define PTASET_PTASET6 _PTASET.Bits.PTASET6 #define PTASET_PTASET7 _PTASET.Bits.PTASET7 #define PTASET_PTASET0_MASK 1 #define PTASET_PTASET1_MASK 2 #define PTASET_PTASET2_MASK 4 #define PTASET_PTASET3_MASK 8 #define PTASET_PTASET4_MASK 16 #define PTASET_PTASET5_MASK 32 #define PTASET_PTASET6_MASK 64 #define PTASET_PTASET7_MASK 128 /*** PTACLR - Port A Data Clear Register; 0xFFFF8003 ***/ typedef union { byte Byte; struct { byte PTACLR0 :1; /* Data Clear for Port A Bit 0 */ byte PTACLR1 :1; /* Data Clear for Port A Bit 1 */ byte PTACLR2 :1; /* Data Clear for Port A Bit 2 */ byte PTACLR3 :1; /* Data Clear for Port A Bit 3 */ byte PTACLR4 :1; /* Data Clear for Port A Bit 4 */ byte PTACLR5 :1; /* Data Clear for Port A Bit 5 */ byte PTACLR6 :1; /* Data Clear for Port A Bit 6 */ byte PTACLR7 :1; /* Data Clear for Port A Bit 7 */ } Bits; } PTACLRSTR; extern volatile PTACLRSTR _PTACLR @0xFFFF8003; #define PTACLR _PTACLR.Byte #define PTACLR_PTACLR0 _PTACLR.Bits.PTACLR0 #define PTACLR_PTACLR1 _PTACLR.Bits.PTACLR1 #define PTACLR_PTACLR2 _PTACLR.Bits.PTACLR2 #define PTACLR_PTACLR3 _PTACLR.Bits.PTACLR3 #define PTACLR_PTACLR4 _PTACLR.Bits.PTACLR4 #define PTACLR_PTACLR5 _PTACLR.Bits.PTACLR5 #define PTACLR_PTACLR6 _PTACLR.Bits.PTACLR6 #define PTACLR_PTACLR7 _PTACLR.Bits.PTACLR7 #define PTACLR_PTACLR0_MASK 1 #define PTACLR_PTACLR1_MASK 2 #define PTACLR_PTACLR2_MASK 4 #define PTACLR_PTACLR3_MASK 8 #define PTACLR_PTACLR4_MASK 16 #define PTACLR_PTACLR5_MASK 32 #define PTACLR_PTACLR6_MASK 64 #define PTACLR_PTACLR7_MASK 128 /*** PTATOG - Port A Toggle Register; 0xFFFF8004 ***/ typedef union { byte Byte; struct { byte PTATOG0 :1; /* Toggle Enable for Port A Bit 0 */ byte PTATOG1 :1; /* Toggle Enable for Port A Bit 1 */ byte PTATOG2 :1; /* Toggle Enable for Port A Bit 2 */ byte PTATOG3 :1; /* Toggle Enable for Port A Bit 3 */ byte PTATOG4 :1; /* Toggle Enable for Port A Bit 4 */ byte PTATOG5 :1; /* Toggle Enable for Port A Bit 5 */ byte PTATOG6 :1; /* Toggle Enable for Port A Bit 6 */ byte PTATOG7 :1; /* Toggle Enable for Port A Bit 7 */ } Bits; } PTATOGSTR; extern volatile PTATOGSTR _PTATOG @0xFFFF8004; #define PTATOG _PTATOG.Byte #define PTATOG_PTATOG0 _PTATOG.Bits.PTATOG0 #define PTATOG_PTATOG1 _PTATOG.Bits.PTATOG1 #define PTATOG_PTATOG2 _PTATOG.Bits.PTATOG2 #define PTATOG_PTATOG3 _PTATOG.Bits.PTATOG3 #define PTATOG_PTATOG4 _PTATOG.Bits.PTATOG4 #define PTATOG_PTATOG5 _PTATOG.Bits.PTATOG5 #define PTATOG_PTATOG6 _PTATOG.Bits.PTATOG6 #define PTATOG_PTATOG7 _PTATOG.Bits.PTATOG7 #define PTATOG_PTATOG0_MASK 1 #define PTATOG_PTATOG1_MASK 2 #define PTATOG_PTATOG2_MASK 4 #define PTATOG_PTATOG3_MASK 8 #define PTATOG_PTATOG4_MASK 16 #define PTATOG_PTATOG5_MASK 32 #define PTATOG_PTATOG6_MASK 64 #define PTATOG_PTATOG7_MASK 128 /*** PTAPE - Port A Pull Enable Register; 0xFFFF8008 ***/ typedef union { byte Byte; struct { byte PTAPE0 :1; /* Internal Pull Enable for Port A Bit 0 */ byte PTAPE1 :1; /* Internal Pull Enable for Port A Bit 1 */ byte PTAPE2 :1; /* Internal Pull Enable for Port A Bit 2 */ byte PTAPE3 :1; /* Internal Pull Enable for Port A Bit 3 */ byte PTAPE4 :1; /* Internal Pull Enable for Port A Bit 4 */ byte PTAPE5 :1; /* Internal Pull Enable for Port A Bit 5 */ byte PTAPE6 :1; /* Internal Pull Enable for Port A Bit 6 */ byte PTAPE7 :1; /* Internal Pull Enable for Port A Bit 7 */ } Bits; } PTAPESTR; extern volatile PTAPESTR _PTAPE @0xFFFF8008; #define PTAPE _PTAPE.Byte #define PTAPE_PTAPE0 _PTAPE.Bits.PTAPE0 #define PTAPE_PTAPE1 _PTAPE.Bits.PTAPE1 #define PTAPE_PTAPE2 _PTAPE.Bits.PTAPE2 #define PTAPE_PTAPE3 _PTAPE.Bits.PTAPE3 #define PTAPE_PTAPE4 _PTAPE.Bits.PTAPE4 #define PTAPE_PTAPE5 _PTAPE.Bits.PTAPE5 #define PTAPE_PTAPE6 _PTAPE.Bits.PTAPE6 #define PTAPE_PTAPE7 _PTAPE.Bits.PTAPE7 #define PTAPE_PTAPE0_MASK 1 #define PTAPE_PTAPE1_MASK 2 #define PTAPE_PTAPE2_MASK 4 #define PTAPE_PTAPE3_MASK 8 #define PTAPE_PTAPE4_MASK 16 #define PTAPE_PTAPE5_MASK 32 #define PTAPE_PTAPE6_MASK 64 #define PTAPE_PTAPE7_MASK 128 /*** PTASE - Port A Slew Rate Enable Register; 0xFFFF8009 ***/ typedef union { byte Byte; struct { byte PTASE0 :1; /* Output Slew Rate Enable for Port A Bit 0 */ byte PTASE1 :1; /* Output Slew Rate Enable for Port A Bit 1 */ byte PTASE2 :1; /* Output Slew Rate Enable for Port A Bit 2 */ byte PTASE3 :1; /* Output Slew Rate Enable for Port A Bit 3 */ byte PTASE4 :1; /* Output Slew Rate Enable for Port A Bit 4 */ byte PTASE5 :1; /* Output Slew Rate Enable for Port A Bit 5 */ byte PTASE6 :1; /* Output Slew Rate Enable for Port A Bit 6 */ byte PTASE7 :1; /* Output Slew Rate Enable for Port A Bit 7 */ } Bits; } PTASESTR; extern volatile PTASESTR _PTASE @0xFFFF8009; #define PTASE _PTASE.Byte #define PTASE_PTASE0 _PTASE.Bits.PTASE0 #define PTASE_PTASE1 _PTASE.Bits.PTASE1 #define PTASE_PTASE2 _PTASE.Bits.PTASE2 #define PTASE_PTASE3 _PTASE.Bits.PTASE3 #define PTASE_PTASE4 _PTASE.Bits.PTASE4 #define PTASE_PTASE5 _PTASE.Bits.PTASE5 #define PTASE_PTASE6 _PTASE.Bits.PTASE6 #define PTASE_PTASE7 _PTASE.Bits.PTASE7 #define PTASE_PTASE0_MASK 1 #define PTASE_PTASE1_MASK 2 #define PTASE_PTASE2_MASK 4 #define PTASE_PTASE3_MASK 8 #define PTASE_PTASE4_MASK 16 #define PTASE_PTASE5_MASK 32 #define PTASE_PTASE6_MASK 64 #define PTASE_PTASE7_MASK 128 /*** PTADS - Port A Drive Strength Selection Register; 0xFFFF800A ***/ typedef union { byte Byte; struct { byte PTADS0 :1; /* Output Drive Strength Selection for Port A Bit 0 */ byte PTADS1 :1; /* Output Drive Strength Selection for Port A Bit 1 */ byte PTADS2 :1; /* Output Drive Strength Selection for Port A Bit 2 */ byte PTADS3 :1; /* Output Drive Strength Selection for Port A Bit 3 */ byte PTADS4 :1; /* Output Drive Strength Selection for Port A Bit 4 */ byte PTADS5 :1; /* Output Drive Strength Selection for Port A Bit 5 */ byte PTADS6 :1; /* Output Drive Strength Selection for Port A Bit 6 */ byte PTADS7 :1; /* Output Drive Strength Selection for Port A Bit 7 */ } Bits; } PTADSSTR; extern volatile PTADSSTR _PTADS @0xFFFF800A; #define PTADS _PTADS.Byte #define PTADS_PTADS0 _PTADS.Bits.PTADS0 #define PTADS_PTADS1 _PTADS.Bits.PTADS1 #define PTADS_PTADS2 _PTADS.Bits.PTADS2 #define PTADS_PTADS3 _PTADS.Bits.PTADS3 #define PTADS_PTADS4 _PTADS.Bits.PTADS4 #define PTADS_PTADS5 _PTADS.Bits.PTADS5 #define PTADS_PTADS6 _PTADS.Bits.PTADS6 #define PTADS_PTADS7 _PTADS.Bits.PTADS7 #define PTADS_PTADS0_MASK 1 #define PTADS_PTADS1_MASK 2 #define PTADS_PTADS2_MASK 4 #define PTADS_PTADS3_MASK 8 #define PTADS_PTADS4_MASK 16 #define PTADS_PTADS5_MASK 32 #define PTADS_PTADS6_MASK 64 #define PTADS_PTADS7_MASK 128 /*** PTAIFE - Port A Input Filter Enable Register; 0xFFFF800B ***/ typedef union { byte Byte; struct { byte PTAIFE0 :1; /* Port A Input Filter Enable Bit 0 */ byte PTAIFE1 :1; /* Port A Input Filter Enable Bit 1 */ byte PTAIFE2 :1; /* Port A Input Filter Enable Bit 2 */ byte PTAIFE3 :1; /* Port A Input Filter Enable Bit 3 */ byte PTAIFE4 :1; /* Port A Input Filter Enable Bit 4 */ byte PTAIFE5 :1; /* Port A Input Filter Enable Bit 5 */ byte PTAIFE6 :1; /* Port A Input Filter Enable Bit 6 */ byte PTAIFE7 :1; /* Port A Input Filter Enable Bit 7 */ } Bits; } PTAIFESTR; extern volatile PTAIFESTR _PTAIFE @0xFFFF800B; #define PTAIFE _PTAIFE.Byte #define PTAIFE_PTAIFE0 _PTAIFE.Bits.PTAIFE0 #define PTAIFE_PTAIFE1 _PTAIFE.Bits.PTAIFE1 #define PTAIFE_PTAIFE2 _PTAIFE.Bits.PTAIFE2 #define PTAIFE_PTAIFE3 _PTAIFE.Bits.PTAIFE3 #define PTAIFE_PTAIFE4 _PTAIFE.Bits.PTAIFE4 #define PTAIFE_PTAIFE5 _PTAIFE.Bits.PTAIFE5 #define PTAIFE_PTAIFE6 _PTAIFE.Bits.PTAIFE6 #define PTAIFE_PTAIFE7 _PTAIFE.Bits.PTAIFE7 #define PTAIFE_PTAIFE0_MASK 1 #define PTAIFE_PTAIFE1_MASK 2 #define PTAIFE_PTAIFE2_MASK 4 #define PTAIFE_PTAIFE3_MASK 8 #define PTAIFE_PTAIFE4_MASK 16 #define PTAIFE_PTAIFE5_MASK 32 #define PTAIFE_PTAIFE6_MASK 64 #define PTAIFE_PTAIFE7_MASK 128 /*** PTBD - Port B Data Register; 0xFFFF8040 ***/ typedef union { byte Byte; struct { byte PTBD0 :1; /* Port B Data Register Bit 0 */ byte PTBD1 :1; /* Port B Data Register Bit 1 */ byte PTBD2 :1; /* Port B Data Register Bit 2 */ byte PTBD3 :1; /* Port B Data Register Bit 3 */ byte PTBD4 :1; /* Port B Data Register Bit 4 */ byte PTBD5 :1; /* Port B Data Register Bit 5 */ byte PTBD6 :1; /* Port B Data Register Bit 6 */ byte PTBD7 :1; /* Port B Data Register Bit 7 */ } Bits; } PTBDSTR; extern volatile PTBDSTR _PTBD @0xFFFF8040; #define PTBD _PTBD.Byte #define PTBD_PTBD0 _PTBD.Bits.PTBD0 #define PTBD_PTBD1 _PTBD.Bits.PTBD1 #define PTBD_PTBD2 _PTBD.Bits.PTBD2 #define PTBD_PTBD3 _PTBD.Bits.PTBD3 #define PTBD_PTBD4 _PTBD.Bits.PTBD4 #define PTBD_PTBD5 _PTBD.Bits.PTBD5 #define PTBD_PTBD6 _PTBD.Bits.PTBD6 #define PTBD_PTBD7 _PTBD.Bits.PTBD7 #define PTBD_PTBD0_MASK 1 #define PTBD_PTBD1_MASK 2 #define PTBD_PTBD2_MASK 4 #define PTBD_PTBD3_MASK 8 #define PTBD_PTBD4_MASK 16 #define PTBD_PTBD5_MASK 32 #define PTBD_PTBD6_MASK 64 #define PTBD_PTBD7_MASK 128 /*** PTBDD - Port B Data Direction Register; 0xFFFF8041 ***/ typedef union { byte Byte; struct { byte PTBDD0 :1; /* Data Direction for Port B Bit 0 */ byte PTBDD1 :1; /* Data Direction for Port B Bit 1 */ byte PTBDD2 :1; /* Data Direction for Port B Bit 2 */ byte PTBDD3 :1; /* Data Direction for Port B Bit 3 */ byte PTBDD4 :1; /* Data Direction for Port B Bit 4 */ byte PTBDD5 :1; /* Data Direction for Port B Bit 5 */ byte PTBDD6 :1; /* Data Direction for Port B Bit 6 */ byte PTBDD7 :1; /* Data Direction for Port B Bit 7 */ } Bits; } PTBDDSTR; extern volatile PTBDDSTR _PTBDD @0xFFFF8041; #define PTBDD _PTBDD.Byte #define PTBDD_PTBDD0 _PTBDD.Bits.PTBDD0 #define PTBDD_PTBDD1 _PTBDD.Bits.PTBDD1 #define PTBDD_PTBDD2 _PTBDD.Bits.PTBDD2 #define PTBDD_PTBDD3 _PTBDD.Bits.PTBDD3 #define PTBDD_PTBDD4 _PTBDD.Bits.PTBDD4 #define PTBDD_PTBDD5 _PTBDD.Bits.PTBDD5 #define PTBDD_PTBDD6 _PTBDD.Bits.PTBDD6 #define PTBDD_PTBDD7 _PTBDD.Bits.PTBDD7 #define PTBDD_PTBDD0_MASK 1 #define PTBDD_PTBDD1_MASK 2 #define PTBDD_PTBDD2_MASK 4 #define PTBDD_PTBDD3_MASK 8 #define PTBDD_PTBDD4_MASK 16 #define PTBDD_PTBDD5_MASK 32 #define PTBDD_PTBDD6_MASK 64 #define PTBDD_PTBDD7_MASK 128 /*** PTBSET - Port B Data Set Register; 0xFFFF8042 ***/ typedef union { byte Byte; struct { byte PTBSET0 :1; /* Data Set for Port B Bit 0 */ byte PTBSET1 :1; /* Data Set for Port B Bit 1 */ byte PTBSET2 :1; /* Data Set for Port B Bit 2 */ byte PTBSET3 :1; /* Data Set for Port B Bit 3 */ byte PTBSET4 :1; /* Data Set for Port B Bit 4 */ byte PTBSET5 :1; /* Data Set for Port B Bit 5 */ byte PTBSET6 :1; /* Data Set for Port B Bit 6 */ byte PTBSET7 :1; /* Data Set for Port B Bit 7 */ } Bits; } PTBSETSTR; extern volatile PTBSETSTR _PTBSET @0xFFFF8042; #define PTBSET _PTBSET.Byte #define PTBSET_PTBSET0 _PTBSET.Bits.PTBSET0 #define PTBSET_PTBSET1 _PTBSET.Bits.PTBSET1 #define PTBSET_PTBSET2 _PTBSET.Bits.PTBSET2 #define PTBSET_PTBSET3 _PTBSET.Bits.PTBSET3 #define PTBSET_PTBSET4 _PTBSET.Bits.PTBSET4 #define PTBSET_PTBSET5 _PTBSET.Bits.PTBSET5 #define PTBSET_PTBSET6 _PTBSET.Bits.PTBSET6 #define PTBSET_PTBSET7 _PTBSET.Bits.PTBSET7 #define PTBSET_PTBSET0_MASK 1 #define PTBSET_PTBSET1_MASK 2 #define PTBSET_PTBSET2_MASK 4 #define PTBSET_PTBSET3_MASK 8 #define PTBSET_PTBSET4_MASK 16 #define PTBSET_PTBSET5_MASK 32 #define PTBSET_PTBSET6_MASK 64 #define PTBSET_PTBSET7_MASK 128 /*** PTBCLR - Port B Data Clear Register; 0xFFFF8043 ***/ typedef union { byte Byte; struct { byte PTBCLR0 :1; /* Data Clear for Port B Bit 0 */ byte PTBCLR1 :1; /* Data Clear for Port B Bit 1 */ byte PTBCLR2 :1; /* Data Clear for Port B Bit 2 */ byte PTBCLR3 :1; /* Data Clear for Port B Bit 3 */ byte PTBCLR4 :1; /* Data Clear for Port B Bit 4 */ byte PTBCLR5 :1; /* Data Clear for Port B Bit 5 */ byte PTBCLR6 :1; /* Data Clear for Port B Bit 6 */ byte PTBCLR7 :1; /* Data Clear for Port B Bit 7 */ } Bits; } PTBCLRSTR; extern volatile PTBCLRSTR _PTBCLR @0xFFFF8043; #define PTBCLR _PTBCLR.Byte #define PTBCLR_PTBCLR0 _PTBCLR.Bits.PTBCLR0 #define PTBCLR_PTBCLR1 _PTBCLR.Bits.PTBCLR1 #define PTBCLR_PTBCLR2 _PTBCLR.Bits.PTBCLR2 #define PTBCLR_PTBCLR3 _PTBCLR.Bits.PTBCLR3 #define PTBCLR_PTBCLR4 _PTBCLR.Bits.PTBCLR4 #define PTBCLR_PTBCLR5 _PTBCLR.Bits.PTBCLR5 #define PTBCLR_PTBCLR6 _PTBCLR.Bits.PTBCLR6 #define PTBCLR_PTBCLR7 _PTBCLR.Bits.PTBCLR7 #define PTBCLR_PTBCLR0_MASK 1 #define PTBCLR_PTBCLR1_MASK 2 #define PTBCLR_PTBCLR2_MASK 4 #define PTBCLR_PTBCLR3_MASK 8 #define PTBCLR_PTBCLR4_MASK 16 #define PTBCLR_PTBCLR5_MASK 32 #define PTBCLR_PTBCLR6_MASK 64 #define PTBCLR_PTBCLR7_MASK 128 /*** PTBTOG - Port B Toggle Register; 0xFFFF8044 ***/ typedef union { byte Byte; struct { byte PTBTOG0 :1; /* Toggle Enable for Port B Bit 0 */ byte PTBTOG1 :1; /* Toggle Enable for Port B Bit 1 */ byte PTBTOG2 :1; /* Toggle Enable for Port B Bit 2 */ byte PTBTOG3 :1; /* Toggle Enable for Port B Bit 3 */ byte PTBTOG4 :1; /* Toggle Enable for Port B Bit 4 */ byte PTBTOG5 :1; /* Toggle Enable for Port B Bit 5 */ byte PTBTOG6 :1; /* Toggle Enable for Port B Bit 6 */ byte PTBTOG7 :1; /* Toggle Enable for Port B Bit 7 */ } Bits; } PTBTOGSTR; extern volatile PTBTOGSTR _PTBTOG @0xFFFF8044; #define PTBTOG _PTBTOG.Byte #define PTBTOG_PTBTOG0 _PTBTOG.Bits.PTBTOG0 #define PTBTOG_PTBTOG1 _PTBTOG.Bits.PTBTOG1 #define PTBTOG_PTBTOG2 _PTBTOG.Bits.PTBTOG2 #define PTBTOG_PTBTOG3 _PTBTOG.Bits.PTBTOG3 #define PTBTOG_PTBTOG4 _PTBTOG.Bits.PTBTOG4 #define PTBTOG_PTBTOG5 _PTBTOG.Bits.PTBTOG5 #define PTBTOG_PTBTOG6 _PTBTOG.Bits.PTBTOG6 #define PTBTOG_PTBTOG7 _PTBTOG.Bits.PTBTOG7 #define PTBTOG_PTBTOG0_MASK 1 #define PTBTOG_PTBTOG1_MASK 2 #define PTBTOG_PTBTOG2_MASK 4 #define PTBTOG_PTBTOG3_MASK 8 #define PTBTOG_PTBTOG4_MASK 16 #define PTBTOG_PTBTOG5_MASK 32 #define PTBTOG_PTBTOG6_MASK 64 #define PTBTOG_PTBTOG7_MASK 128 /*** PTBPE - Port B Pull Enable Register; 0xFFFF8048 ***/ typedef union { byte Byte; struct { byte PTBPE0 :1; /* Internal Pull Enable for Port B Bit 0 */ byte PTBPE1 :1; /* Internal Pull Enable for Port B Bit 1 */ byte PTBPE2 :1; /* Internal Pull Enable for Port B Bit 2 */ byte PTBPE3 :1; /* Internal Pull Enable for Port B Bit 3 */ byte PTBPE4 :1; /* Internal Pull Enable for Port B Bit 4 */ byte PTBPE5 :1; /* Internal Pull Enable for Port B Bit 5 */ byte PTBPE6 :1; /* Internal Pull Enable for Port B Bit 6 */ byte PTBPE7 :1; /* Internal Pull Enable for Port B Bit 7 */ } Bits; } PTBPESTR; extern volatile PTBPESTR _PTBPE @0xFFFF8048; #define PTBPE _PTBPE.Byte #define PTBPE_PTBPE0 _PTBPE.Bits.PTBPE0 #define PTBPE_PTBPE1 _PTBPE.Bits.PTBPE1 #define PTBPE_PTBPE2 _PTBPE.Bits.PTBPE2 #define PTBPE_PTBPE3 _PTBPE.Bits.PTBPE3 #define PTBPE_PTBPE4 _PTBPE.Bits.PTBPE4 #define PTBPE_PTBPE5 _PTBPE.Bits.PTBPE5 #define PTBPE_PTBPE6 _PTBPE.Bits.PTBPE6 #define PTBPE_PTBPE7 _PTBPE.Bits.PTBPE7 #define PTBPE_PTBPE0_MASK 1 #define PTBPE_PTBPE1_MASK 2 #define PTBPE_PTBPE2_MASK 4 #define PTBPE_PTBPE3_MASK 8 #define PTBPE_PTBPE4_MASK 16 #define PTBPE_PTBPE5_MASK 32 #define PTBPE_PTBPE6_MASK 64 #define PTBPE_PTBPE7_MASK 128 /*** PTBSE - Port B Slew Rate Enable Register; 0xFFFF8049 ***/ typedef union { byte Byte; struct { byte PTBSE0 :1; /* Output Slew Rate Enable for Port B Bit 0 */ byte PTBSE1 :1; /* Output Slew Rate Enable for Port B Bit 1 */ byte PTBSE2 :1; /* Output Slew Rate Enable for Port B Bit 2 */ byte PTBSE3 :1; /* Output Slew Rate Enable for Port B Bit 3 */ byte PTBSE4 :1; /* Output Slew Rate Enable for Port B Bit 4 */ byte PTBSE5 :1; /* Output Slew Rate Enable for Port B Bit 5 */ byte PTBSE6 :1; /* Output Slew Rate Enable for Port B Bit 6 */ byte PTBSE7 :1; /* Output Slew Rate Enable for Port B Bit 7 */ } Bits; } PTBSESTR; extern volatile PTBSESTR _PTBSE @0xFFFF8049; #define PTBSE _PTBSE.Byte #define PTBSE_PTBSE0 _PTBSE.Bits.PTBSE0 #define PTBSE_PTBSE1 _PTBSE.Bits.PTBSE1 #define PTBSE_PTBSE2 _PTBSE.Bits.PTBSE2 #define PTBSE_PTBSE3 _PTBSE.Bits.PTBSE3 #define PTBSE_PTBSE4 _PTBSE.Bits.PTBSE4 #define PTBSE_PTBSE5 _PTBSE.Bits.PTBSE5 #define PTBSE_PTBSE6 _PTBSE.Bits.PTBSE6 #define PTBSE_PTBSE7 _PTBSE.Bits.PTBSE7 #define PTBSE_PTBSE0_MASK 1 #define PTBSE_PTBSE1_MASK 2 #define PTBSE_PTBSE2_MASK 4 #define PTBSE_PTBSE3_MASK 8 #define PTBSE_PTBSE4_MASK 16 #define PTBSE_PTBSE5_MASK 32 #define PTBSE_PTBSE6_MASK 64 #define PTBSE_PTBSE7_MASK 128 /*** PTBDS - Port B Drive Strength Selection Register; 0xFFFF804A ***/ typedef union { byte Byte; struct { byte PTBDS0 :1; /* Output Drive Strength Selection for Port B Bit 0 */ byte PTBDS1 :1; /* Output Drive Strength Selection for Port B Bit 1 */ byte PTBDS2 :1; /* Output Drive Strength Selection for Port B Bit 2 */ byte PTBDS3 :1; /* Output Drive Strength Selection for Port B Bit 3 */ byte PTBDS4 :1; /* Output Drive Strength Selection for Port B Bit 4 */ byte PTBDS5 :1; /* Output Drive Strength Selection for Port B Bit 5 */ byte PTBDS6 :1; /* Output Drive Strength Selection for Port B Bit 6 */ byte PTBDS7 :1; /* Output Drive Strength Selection for Port B Bit 7 */ } Bits; } PTBDSSTR; extern volatile PTBDSSTR _PTBDS @0xFFFF804A; #define PTBDS _PTBDS.Byte #define PTBDS_PTBDS0 _PTBDS.Bits.PTBDS0 #define PTBDS_PTBDS1 _PTBDS.Bits.PTBDS1 #define PTBDS_PTBDS2 _PTBDS.Bits.PTBDS2 #define PTBDS_PTBDS3 _PTBDS.Bits.PTBDS3 #define PTBDS_PTBDS4 _PTBDS.Bits.PTBDS4 #define PTBDS_PTBDS5 _PTBDS.Bits.PTBDS5 #define PTBDS_PTBDS6 _PTBDS.Bits.PTBDS6 #define PTBDS_PTBDS7 _PTBDS.Bits.PTBDS7 #define PTBDS_PTBDS0_MASK 1 #define PTBDS_PTBDS1_MASK 2 #define PTBDS_PTBDS2_MASK 4 #define PTBDS_PTBDS3_MASK 8 #define PTBDS_PTBDS4_MASK 16 #define PTBDS_PTBDS5_MASK 32 #define PTBDS_PTBDS6_MASK 64 #define PTBDS_PTBDS7_MASK 128 /*** PTBIFE - Port B Input Filter Enable Register; 0xFFFF804B ***/ typedef union { byte Byte; struct { byte PTBIFE0 :1; /* Port B Input Filter Enable Bit 0 */ byte PTBIFE1 :1; /* Port B Input Filter Enable Bit 1 */ byte PTBIFE2 :1; /* Port B Input Filter Enable Bit 2 */ byte PTBIFE3 :1; /* Port B Input Filter Enable Bit 3 */ byte PTBIFE4 :1; /* Port B Input Filter Enable Bit 4 */ byte PTBIFE5 :1; /* Port B Input Filter Enable Bit 5 */ byte PTBIFE6 :1; /* Port B Input Filter Enable Bit 6 */ byte PTBIFE7 :1; /* Port B Input Filter Enable Bit 7 */ } Bits; } PTBIFESTR; extern volatile PTBIFESTR _PTBIFE @0xFFFF804B; #define PTBIFE _PTBIFE.Byte #define PTBIFE_PTBIFE0 _PTBIFE.Bits.PTBIFE0 #define PTBIFE_PTBIFE1 _PTBIFE.Bits.PTBIFE1 #define PTBIFE_PTBIFE2 _PTBIFE.Bits.PTBIFE2 #define PTBIFE_PTBIFE3 _PTBIFE.Bits.PTBIFE3 #define PTBIFE_PTBIFE4 _PTBIFE.Bits.PTBIFE4 #define PTBIFE_PTBIFE5 _PTBIFE.Bits.PTBIFE5 #define PTBIFE_PTBIFE6 _PTBIFE.Bits.PTBIFE6 #define PTBIFE_PTBIFE7 _PTBIFE.Bits.PTBIFE7 #define PTBIFE_PTBIFE0_MASK 1 #define PTBIFE_PTBIFE1_MASK 2 #define PTBIFE_PTBIFE2_MASK 4 #define PTBIFE_PTBIFE3_MASK 8 #define PTBIFE_PTBIFE4_MASK 16 #define PTBIFE_PTBIFE5_MASK 32 #define PTBIFE_PTBIFE6_MASK 64 #define PTBIFE_PTBIFE7_MASK 128 /*** PTCD - Port C Data Register; 0xFFFF8080 ***/ typedef union { byte Byte; struct { byte PTCD0 :1; /* Port C Data Register Bit 0 */ byte PTCD1 :1; /* Port C Data Register Bit 1 */ byte PTCD2 :1; /* Port C Data Register Bit 2 */ byte PTCD3 :1; /* Port C Data Register Bit 3 */ byte PTCD4 :1; /* Port C Data Register Bit 4 */ byte PTCD5 :1; /* Port C Data Register Bit 5 */ byte PTCD6 :1; /* Port C Data Register Bit 6 */ byte PTCD7 :1; /* Port C Data Register Bit 7 */ } Bits; } PTCDSTR; extern volatile PTCDSTR _PTCD @0xFFFF8080; #define PTCD _PTCD.Byte #define PTCD_PTCD0 _PTCD.Bits.PTCD0 #define PTCD_PTCD1 _PTCD.Bits.PTCD1 #define PTCD_PTCD2 _PTCD.Bits.PTCD2 #define PTCD_PTCD3 _PTCD.Bits.PTCD3 #define PTCD_PTCD4 _PTCD.Bits.PTCD4 #define PTCD_PTCD5 _PTCD.Bits.PTCD5 #define PTCD_PTCD6 _PTCD.Bits.PTCD6 #define PTCD_PTCD7 _PTCD.Bits.PTCD7 #define PTCD_PTCD0_MASK 1 #define PTCD_PTCD1_MASK 2 #define PTCD_PTCD2_MASK 4 #define PTCD_PTCD3_MASK 8 #define PTCD_PTCD4_MASK 16 #define PTCD_PTCD5_MASK 32 #define PTCD_PTCD6_MASK 64 #define PTCD_PTCD7_MASK 128 /*** PTCDD - Port C Data Direction Register; 0xFFFF8081 ***/ typedef union { byte Byte; struct { byte PTCDD0 :1; /* Data Direction for Port C Bit 0 */ byte PTCDD1 :1; /* Data Direction for Port C Bit 1 */ byte PTCDD2 :1; /* Data Direction for Port C Bit 2 */ byte PTCDD3 :1; /* Data Direction for Port C Bit 3 */ byte PTCDD4 :1; /* Data Direction for Port C Bit 4 */ byte PTCDD5 :1; /* Data Direction for Port C Bit 5 */ byte PTCDD6 :1; /* Data Direction for Port C Bit 6 */ byte PTCDD7 :1; /* Data Direction for Port C Bit 7 */ } Bits; } PTCDDSTR; extern volatile PTCDDSTR _PTCDD @0xFFFF8081; #define PTCDD _PTCDD.Byte #define PTCDD_PTCDD0 _PTCDD.Bits.PTCDD0 #define PTCDD_PTCDD1 _PTCDD.Bits.PTCDD1 #define PTCDD_PTCDD2 _PTCDD.Bits.PTCDD2 #define PTCDD_PTCDD3 _PTCDD.Bits.PTCDD3 #define PTCDD_PTCDD4 _PTCDD.Bits.PTCDD4 #define PTCDD_PTCDD5 _PTCDD.Bits.PTCDD5 #define PTCDD_PTCDD6 _PTCDD.Bits.PTCDD6 #define PTCDD_PTCDD7 _PTCDD.Bits.PTCDD7 #define PTCDD_PTCDD0_MASK 1 #define PTCDD_PTCDD1_MASK 2 #define PTCDD_PTCDD2_MASK 4 #define PTCDD_PTCDD3_MASK 8 #define PTCDD_PTCDD4_MASK 16 #define PTCDD_PTCDD5_MASK 32 #define PTCDD_PTCDD6_MASK 64 #define PTCDD_PTCDD7_MASK 128 /*** PTCSET - Port C Data Set Register; 0xFFFF8082 ***/ typedef union { byte Byte; struct { byte PTCSET0 :1; /* Data Set for Port C Bit 0 */ byte PTCSET1 :1; /* Data Set for Port C Bit 1 */ byte PTCSET2 :1; /* Data Set for Port C Bit 2 */ byte PTCSET3 :1; /* Data Set for Port C Bit 3 */ byte PTCSET4 :1; /* Data Set for Port C Bit 4 */ byte PTCSET5 :1; /* Data Set for Port C Bit 5 */ byte PTCSET6 :1; /* Data Set for Port C Bit 6 */ byte PTCSET7 :1; /* Data Set for Port C Bit 7 */ } Bits; } PTCSETSTR; extern volatile PTCSETSTR _PTCSET @0xFFFF8082; #define PTCSET _PTCSET.Byte #define PTCSET_PTCSET0 _PTCSET.Bits.PTCSET0 #define PTCSET_PTCSET1 _PTCSET.Bits.PTCSET1 #define PTCSET_PTCSET2 _PTCSET.Bits.PTCSET2 #define PTCSET_PTCSET3 _PTCSET.Bits.PTCSET3 #define PTCSET_PTCSET4 _PTCSET.Bits.PTCSET4 #define PTCSET_PTCSET5 _PTCSET.Bits.PTCSET5 #define PTCSET_PTCSET6 _PTCSET.Bits.PTCSET6 #define PTCSET_PTCSET7 _PTCSET.Bits.PTCSET7 #define PTCSET_PTCSET0_MASK 1 #define PTCSET_PTCSET1_MASK 2 #define PTCSET_PTCSET2_MASK 4 #define PTCSET_PTCSET3_MASK 8 #define PTCSET_PTCSET4_MASK 16 #define PTCSET_PTCSET5_MASK 32 #define PTCSET_PTCSET6_MASK 64 #define PTCSET_PTCSET7_MASK 128 /*** PTCCLR - Port C Data Clear Register; 0xFFFF8083 ***/ typedef union { byte Byte; struct { byte PTCCLR0 :1; /* Data Clear for Port C Bit 0 */ byte PTCCLR1 :1; /* Data Clear for Port C Bit 1 */ byte PTCCLR2 :1; /* Data Clear for Port C Bit 2 */ byte PTCCLR3 :1; /* Data Clear for Port C Bit 3 */ byte PTCCLR4 :1; /* Data Clear for Port C Bit 4 */ byte PTCCLR5 :1; /* Data Clear for Port C Bit 5 */ byte PTCCLR6 :1; /* Data Clear for Port C Bit 6 */ byte PTCCLR7 :1; /* Data Clear for Port C Bit 7 */ } Bits; } PTCCLRSTR; extern volatile PTCCLRSTR _PTCCLR @0xFFFF8083; #define PTCCLR _PTCCLR.Byte #define PTCCLR_PTCCLR0 _PTCCLR.Bits.PTCCLR0 #define PTCCLR_PTCCLR1 _PTCCLR.Bits.PTCCLR1 #define PTCCLR_PTCCLR2 _PTCCLR.Bits.PTCCLR2 #define PTCCLR_PTCCLR3 _PTCCLR.Bits.PTCCLR3 #define PTCCLR_PTCCLR4 _PTCCLR.Bits.PTCCLR4 #define PTCCLR_PTCCLR5 _PTCCLR.Bits.PTCCLR5 #define PTCCLR_PTCCLR6 _PTCCLR.Bits.PTCCLR6 #define PTCCLR_PTCCLR7 _PTCCLR.Bits.PTCCLR7 #define PTCCLR_PTCCLR0_MASK 1 #define PTCCLR_PTCCLR1_MASK 2 #define PTCCLR_PTCCLR2_MASK 4 #define PTCCLR_PTCCLR3_MASK 8 #define PTCCLR_PTCCLR4_MASK 16 #define PTCCLR_PTCCLR5_MASK 32 #define PTCCLR_PTCCLR6_MASK 64 #define PTCCLR_PTCCLR7_MASK 128 /*** PTCTOG - Port C Toggle Register; 0xFFFF8084 ***/ typedef union { byte Byte; struct { byte PTCTOG0 :1; /* Toggle Enable for Port C Bit 0 */ byte PTCTOG1 :1; /* Toggle Enable for Port C Bit 1 */ byte PTCTOG2 :1; /* Toggle Enable for Port C Bit 2 */ byte PTCTOG3 :1; /* Toggle Enable for Port C Bit 3 */ byte PTCTOG4 :1; /* Toggle Enable for Port C Bit 4 */ byte PTCTOG5 :1; /* Toggle Enable for Port C Bit 5 */ byte PTCTOG6 :1; /* Toggle Enable for Port C Bit 6 */ byte PTCTOG7 :1; /* Toggle Enable for Port C Bit 7 */ } Bits; } PTCTOGSTR; extern volatile PTCTOGSTR _PTCTOG @0xFFFF8084; #define PTCTOG _PTCTOG.Byte #define PTCTOG_PTCTOG0 _PTCTOG.Bits.PTCTOG0 #define PTCTOG_PTCTOG1 _PTCTOG.Bits.PTCTOG1 #define PTCTOG_PTCTOG2 _PTCTOG.Bits.PTCTOG2 #define PTCTOG_PTCTOG3 _PTCTOG.Bits.PTCTOG3 #define PTCTOG_PTCTOG4 _PTCTOG.Bits.PTCTOG4 #define PTCTOG_PTCTOG5 _PTCTOG.Bits.PTCTOG5 #define PTCTOG_PTCTOG6 _PTCTOG.Bits.PTCTOG6 #define PTCTOG_PTCTOG7 _PTCTOG.Bits.PTCTOG7 #define PTCTOG_PTCTOG0_MASK 1 #define PTCTOG_PTCTOG1_MASK 2 #define PTCTOG_PTCTOG2_MASK 4 #define PTCTOG_PTCTOG3_MASK 8 #define PTCTOG_PTCTOG4_MASK 16 #define PTCTOG_PTCTOG5_MASK 32 #define PTCTOG_PTCTOG6_MASK 64 #define PTCTOG_PTCTOG7_MASK 128 /*** PTCPE - Port C Pull Enable Register; 0xFFFF8088 ***/ typedef union { byte Byte; struct { byte PTCPE0 :1; /* Internal Pull Enable for Port C Bit 0 */ byte PTCPE1 :1; /* Internal Pull Enable for Port C Bit 1 */ byte PTCPE2 :1; /* Internal Pull Enable for Port C Bit 2 */ byte PTCPE3 :1; /* Internal Pull Enable for Port C Bit 3 */ byte PTCPE4 :1; /* Internal Pull Enable for Port C Bit 4 */ byte PTCPE5 :1; /* Internal Pull Enable for Port C Bit 5 */ byte PTCPE6 :1; /* Internal Pull Enable for Port C Bit 6 */ byte PTCPE7 :1; /* Internal Pull Enable for Port C Bit 7 */ } Bits; } PTCPESTR; extern volatile PTCPESTR _PTCPE @0xFFFF8088; #define PTCPE _PTCPE.Byte #define PTCPE_PTCPE0 _PTCPE.Bits.PTCPE0 #define PTCPE_PTCPE1 _PTCPE.Bits.PTCPE1 #define PTCPE_PTCPE2 _PTCPE.Bits.PTCPE2 #define PTCPE_PTCPE3 _PTCPE.Bits.PTCPE3 #define PTCPE_PTCPE4 _PTCPE.Bits.PTCPE4 #define PTCPE_PTCPE5 _PTCPE.Bits.PTCPE5 #define PTCPE_PTCPE6 _PTCPE.Bits.PTCPE6 #define PTCPE_PTCPE7 _PTCPE.Bits.PTCPE7 #define PTCPE_PTCPE0_MASK 1 #define PTCPE_PTCPE1_MASK 2 #define PTCPE_PTCPE2_MASK 4 #define PTCPE_PTCPE3_MASK 8 #define PTCPE_PTCPE4_MASK 16 #define PTCPE_PTCPE5_MASK 32 #define PTCPE_PTCPE6_MASK 64 #define PTCPE_PTCPE7_MASK 128 /*** PTCSE - Port C Slew Rate Enable Register; 0xFFFF8089 ***/ typedef union { byte Byte; struct { byte PTCSE0 :1; /* Output Slew Rate Enable for Port C Bit 0 */ byte PTCSE1 :1; /* Output Slew Rate Enable for Port C Bit 1 */ byte PTCSE2 :1; /* Output Slew Rate Enable for Port C Bit 2 */ byte PTCSE3 :1; /* Output Slew Rate Enable for Port C Bit 3 */ byte PTCSE4 :1; /* Output Slew Rate Enable for Port C Bit 4 */ byte PTCSE5 :1; /* Output Slew Rate Enable for Port C Bit 5 */ byte PTCSE6 :1; /* Output Slew Rate Enable for Port C Bit 6 */ byte PTCSE7 :1; /* Output Slew Rate Enable for Port C Bit 7 */ } Bits; } PTCSESTR; extern volatile PTCSESTR _PTCSE @0xFFFF8089; #define PTCSE _PTCSE.Byte #define PTCSE_PTCSE0 _PTCSE.Bits.PTCSE0 #define PTCSE_PTCSE1 _PTCSE.Bits.PTCSE1 #define PTCSE_PTCSE2 _PTCSE.Bits.PTCSE2 #define PTCSE_PTCSE3 _PTCSE.Bits.PTCSE3 #define PTCSE_PTCSE4 _PTCSE.Bits.PTCSE4 #define PTCSE_PTCSE5 _PTCSE.Bits.PTCSE5 #define PTCSE_PTCSE6 _PTCSE.Bits.PTCSE6 #define PTCSE_PTCSE7 _PTCSE.Bits.PTCSE7 #define PTCSE_PTCSE0_MASK 1 #define PTCSE_PTCSE1_MASK 2 #define PTCSE_PTCSE2_MASK 4 #define PTCSE_PTCSE3_MASK 8 #define PTCSE_PTCSE4_MASK 16 #define PTCSE_PTCSE5_MASK 32 #define PTCSE_PTCSE6_MASK 64 #define PTCSE_PTCSE7_MASK 128 /*** PTCDS - Port C Drive Strength Selection Register; 0xFFFF808A ***/ typedef union { byte Byte; struct { byte PTCDS0 :1; /* Output Drive Strength Selection for Port C Bit 0 */ byte PTCDS1 :1; /* Output Drive Strength Selection for Port C Bit 1 */ byte PTCDS2 :1; /* Output Drive Strength Selection for Port C Bit 2 */ byte PTCDS3 :1; /* Output Drive Strength Selection for Port C Bit 3 */ byte PTCDS4 :1; /* Output Drive Strength Selection for Port C Bit 4 */ byte PTCDS5 :1; /* Output Drive Strength Selection for Port C Bit 5 */ byte PTCDS6 :1; /* Output Drive Strength Selection for Port C Bit 6 */ byte PTCDS7 :1; /* Output Drive Strength Selection for Port C Bit 7 */ } Bits; } PTCDSSTR; extern volatile PTCDSSTR _PTCDS @0xFFFF808A; #define PTCDS _PTCDS.Byte #define PTCDS_PTCDS0 _PTCDS.Bits.PTCDS0 #define PTCDS_PTCDS1 _PTCDS.Bits.PTCDS1 #define PTCDS_PTCDS2 _PTCDS.Bits.PTCDS2 #define PTCDS_PTCDS3 _PTCDS.Bits.PTCDS3 #define PTCDS_PTCDS4 _PTCDS.Bits.PTCDS4 #define PTCDS_PTCDS5 _PTCDS.Bits.PTCDS5 #define PTCDS_PTCDS6 _PTCDS.Bits.PTCDS6 #define PTCDS_PTCDS7 _PTCDS.Bits.PTCDS7 #define PTCDS_PTCDS0_MASK 1 #define PTCDS_PTCDS1_MASK 2 #define PTCDS_PTCDS2_MASK 4 #define PTCDS_PTCDS3_MASK 8 #define PTCDS_PTCDS4_MASK 16 #define PTCDS_PTCDS5_MASK 32 #define PTCDS_PTCDS6_MASK 64 #define PTCDS_PTCDS7_MASK 128 /*** PTCIFE - Port C Input Filter Enable Register; 0xFFFF808B ***/ typedef union { byte Byte; struct { byte PTCIFE0 :1; /* Port C Input Filter Enable Bit 0 */ byte PTCIFE1 :1; /* Port C Input Filter Enable Bit 1 */ byte PTCIFE2 :1; /* Port C Input Filter Enable Bit 2 */ byte PTCIFE3 :1; /* Port C Input Filter Enable Bit 3 */ byte PTCIFE4 :1; /* Port C Input Filter Enable Bit 4 */ byte PTCIFE5 :1; /* Port C Input Filter Enable Bit 5 */ byte PTCIFE6 :1; /* Port C Input Filter Enable Bit 6 */ byte PTCIFE7 :1; /* Port C Input Filter Enable Bit 7 */ } Bits; } PTCIFESTR; extern volatile PTCIFESTR _PTCIFE @0xFFFF808B; #define PTCIFE _PTCIFE.Byte #define PTCIFE_PTCIFE0 _PTCIFE.Bits.PTCIFE0 #define PTCIFE_PTCIFE1 _PTCIFE.Bits.PTCIFE1 #define PTCIFE_PTCIFE2 _PTCIFE.Bits.PTCIFE2 #define PTCIFE_PTCIFE3 _PTCIFE.Bits.PTCIFE3 #define PTCIFE_PTCIFE4 _PTCIFE.Bits.PTCIFE4 #define PTCIFE_PTCIFE5 _PTCIFE.Bits.PTCIFE5 #define PTCIFE_PTCIFE6 _PTCIFE.Bits.PTCIFE6 #define PTCIFE_PTCIFE7 _PTCIFE.Bits.PTCIFE7 #define PTCIFE_PTCIFE0_MASK 1 #define PTCIFE_PTCIFE1_MASK 2 #define PTCIFE_PTCIFE2_MASK 4 #define PTCIFE_PTCIFE3_MASK 8 #define PTCIFE_PTCIFE4_MASK 16 #define PTCIFE_PTCIFE5_MASK 32 #define PTCIFE_PTCIFE6_MASK 64 #define PTCIFE_PTCIFE7_MASK 128 /*** PTDD - Port D Data Register; 0xFFFF80C0 ***/ typedef union { byte Byte; struct { byte PTDD0 :1; /* Port D Data Register Bit 0 */ byte PTDD1 :1; /* Port D Data Register Bit 1 */ byte PTDD2 :1; /* Port D Data Register Bit 2 */ byte PTDD3 :1; /* Port D Data Register Bit 3 */ byte PTDD4 :1; /* Port D Data Register Bit 4 */ byte PTDD5 :1; /* Port D Data Register Bit 5 */ byte PTDD6 :1; /* Port D Data Register Bit 6 */ byte PTDD7 :1; /* Port D Data Register Bit 7 */ } Bits; } PTDDSTR; extern volatile PTDDSTR _PTDD @0xFFFF80C0; #define PTDD _PTDD.Byte #define PTDD_PTDD0 _PTDD.Bits.PTDD0 #define PTDD_PTDD1 _PTDD.Bits.PTDD1 #define PTDD_PTDD2 _PTDD.Bits.PTDD2 #define PTDD_PTDD3 _PTDD.Bits.PTDD3 #define PTDD_PTDD4 _PTDD.Bits.PTDD4 #define PTDD_PTDD5 _PTDD.Bits.PTDD5 #define PTDD_PTDD6 _PTDD.Bits.PTDD6 #define PTDD_PTDD7 _PTDD.Bits.PTDD7 #define PTDD_PTDD0_MASK 1 #define PTDD_PTDD1_MASK 2 #define PTDD_PTDD2_MASK 4 #define PTDD_PTDD3_MASK 8 #define PTDD_PTDD4_MASK 16 #define PTDD_PTDD5_MASK 32 #define PTDD_PTDD6_MASK 64 #define PTDD_PTDD7_MASK 128 /*** PTDDD - Port D Data Direction Register; 0xFFFF80C1 ***/ typedef union { byte Byte; struct { byte PTDDD0 :1; /* Data Direction for Port D Bit 0 */ byte PTDDD1 :1; /* Data Direction for Port D Bit 1 */ byte PTDDD2 :1; /* Data Direction for Port D Bit 2 */ byte PTDDD3 :1; /* Data Direction for Port D Bit 3 */ byte PTDDD4 :1; /* Data Direction for Port D Bit 4 */ byte PTDDD5 :1; /* Data Direction for Port D Bit 5 */ byte PTDDD6 :1; /* Data Direction for Port D Bit 6 */ byte PTDDD7 :1; /* Data Direction for Port D Bit 7 */ } Bits; } PTDDDSTR; extern volatile PTDDDSTR _PTDDD @0xFFFF80C1; #define PTDDD _PTDDD.Byte #define PTDDD_PTDDD0 _PTDDD.Bits.PTDDD0 #define PTDDD_PTDDD1 _PTDDD.Bits.PTDDD1 #define PTDDD_PTDDD2 _PTDDD.Bits.PTDDD2 #define PTDDD_PTDDD3 _PTDDD.Bits.PTDDD3 #define PTDDD_PTDDD4 _PTDDD.Bits.PTDDD4 #define PTDDD_PTDDD5 _PTDDD.Bits.PTDDD5 #define PTDDD_PTDDD6 _PTDDD.Bits.PTDDD6 #define PTDDD_PTDDD7 _PTDDD.Bits.PTDDD7 #define PTDDD_PTDDD0_MASK 1 #define PTDDD_PTDDD1_MASK 2 #define PTDDD_PTDDD2_MASK 4 #define PTDDD_PTDDD3_MASK 8 #define PTDDD_PTDDD4_MASK 16 #define PTDDD_PTDDD5_MASK 32 #define PTDDD_PTDDD6_MASK 64 #define PTDDD_PTDDD7_MASK 128 /*** PTDSET - Port D Data Set Register; 0xFFFF80C2 ***/ typedef union { byte Byte; struct { byte PTDSET0 :1; /* Data Set for Port D Bit 0 */ byte PTDSET1 :1; /* Data Set for Port D Bit 1 */ byte PTDSET2 :1; /* Data Set for Port D Bit 2 */ byte PTDSET3 :1; /* Data Set for Port D Bit 3 */ byte PTDSET4 :1; /* Data Set for Port D Bit 4 */ byte PTDSET5 :1; /* Data Set for Port D Bit 5 */ byte PTDSET6 :1; /* Data Set for Port D Bit 6 */ byte PTDSET7 :1; /* Data Set for Port D Bit 7 */ } Bits; } PTDSETSTR; extern volatile PTDSETSTR _PTDSET @0xFFFF80C2; #define PTDSET _PTDSET.Byte #define PTDSET_PTDSET0 _PTDSET.Bits.PTDSET0 #define PTDSET_PTDSET1 _PTDSET.Bits.PTDSET1 #define PTDSET_PTDSET2 _PTDSET.Bits.PTDSET2 #define PTDSET_PTDSET3 _PTDSET.Bits.PTDSET3 #define PTDSET_PTDSET4 _PTDSET.Bits.PTDSET4 #define PTDSET_PTDSET5 _PTDSET.Bits.PTDSET5 #define PTDSET_PTDSET6 _PTDSET.Bits.PTDSET6 #define PTDSET_PTDSET7 _PTDSET.Bits.PTDSET7 #define PTDSET_PTDSET0_MASK 1 #define PTDSET_PTDSET1_MASK 2 #define PTDSET_PTDSET2_MASK 4 #define PTDSET_PTDSET3_MASK 8 #define PTDSET_PTDSET4_MASK 16 #define PTDSET_PTDSET5_MASK 32 #define PTDSET_PTDSET6_MASK 64 #define PTDSET_PTDSET7_MASK 128 /*** PTDCLR - Port D Data Clear Register; 0xFFFF80C3 ***/ typedef union { byte Byte; struct { byte PTDCLR0 :1; /* Data Clear for Port D Bit 0 */ byte PTDCLR1 :1; /* Data Clear for Port D Bit 1 */ byte PTDCLR2 :1; /* Data Clear for Port D Bit 2 */ byte PTDCLR3 :1; /* Data Clear for Port D Bit 3 */ byte PTDCLR4 :1; /* Data Clear for Port D Bit 4 */ byte PTDCLR5 :1; /* Data Clear for Port D Bit 5 */ byte PTDCLR6 :1; /* Data Clear for Port D Bit 6 */ byte PTDCLR7 :1; /* Data Clear for Port D Bit 7 */ } Bits; } PTDCLRSTR; extern volatile PTDCLRSTR _PTDCLR @0xFFFF80C3; #define PTDCLR _PTDCLR.Byte #define PTDCLR_PTDCLR0 _PTDCLR.Bits.PTDCLR0 #define PTDCLR_PTDCLR1 _PTDCLR.Bits.PTDCLR1 #define PTDCLR_PTDCLR2 _PTDCLR.Bits.PTDCLR2 #define PTDCLR_PTDCLR3 _PTDCLR.Bits.PTDCLR3 #define PTDCLR_PTDCLR4 _PTDCLR.Bits.PTDCLR4 #define PTDCLR_PTDCLR5 _PTDCLR.Bits.PTDCLR5 #define PTDCLR_PTDCLR6 _PTDCLR.Bits.PTDCLR6 #define PTDCLR_PTDCLR7 _PTDCLR.Bits.PTDCLR7 #define PTDCLR_PTDCLR0_MASK 1 #define PTDCLR_PTDCLR1_MASK 2 #define PTDCLR_PTDCLR2_MASK 4 #define PTDCLR_PTDCLR3_MASK 8 #define PTDCLR_PTDCLR4_MASK 16 #define PTDCLR_PTDCLR5_MASK 32 #define PTDCLR_PTDCLR6_MASK 64 #define PTDCLR_PTDCLR7_MASK 128 /*** PTDTOG - Port D Toggle Register; 0xFFFF80C4 ***/ typedef union { byte Byte; struct { byte PTDTOG0 :1; /* Toggle Enable for Port D Bit 0 */ byte PTDTOG1 :1; /* Toggle Enable for Port D Bit 1 */ byte PTDTOG2 :1; /* Toggle Enable for Port D Bit 2 */ byte PTDTOG3 :1; /* Toggle Enable for Port D Bit 3 */ byte PTDTOG4 :1; /* Toggle Enable for Port D Bit 4 */ byte PTDTOG5 :1; /* Toggle Enable for Port D Bit 5 */ byte PTDTOG6 :1; /* Toggle Enable for Port D Bit 6 */ byte PTDTOG7 :1; /* Toggle Enable for Port D Bit 7 */ } Bits; } PTDTOGSTR; extern volatile PTDTOGSTR _PTDTOG @0xFFFF80C4; #define PTDTOG _PTDTOG.Byte #define PTDTOG_PTDTOG0 _PTDTOG.Bits.PTDTOG0 #define PTDTOG_PTDTOG1 _PTDTOG.Bits.PTDTOG1 #define PTDTOG_PTDTOG2 _PTDTOG.Bits.PTDTOG2 #define PTDTOG_PTDTOG3 _PTDTOG.Bits.PTDTOG3 #define PTDTOG_PTDTOG4 _PTDTOG.Bits.PTDTOG4 #define PTDTOG_PTDTOG5 _PTDTOG.Bits.PTDTOG5 #define PTDTOG_PTDTOG6 _PTDTOG.Bits.PTDTOG6 #define PTDTOG_PTDTOG7 _PTDTOG.Bits.PTDTOG7 #define PTDTOG_PTDTOG0_MASK 1 #define PTDTOG_PTDTOG1_MASK 2 #define PTDTOG_PTDTOG2_MASK 4 #define PTDTOG_PTDTOG3_MASK 8 #define PTDTOG_PTDTOG4_MASK 16 #define PTDTOG_PTDTOG5_MASK 32 #define PTDTOG_PTDTOG6_MASK 64 #define PTDTOG_PTDTOG7_MASK 128 /*** PTDPE - Port D Pull Enable Register; 0xFFFF80C8 ***/ typedef union { byte Byte; struct { byte PTDPE0 :1; /* Internal Pull Enable for Port D Bit 0 */ byte PTDPE1 :1; /* Internal Pull Enable for Port D Bit 1 */ byte PTDPE2 :1; /* Internal Pull Enable for Port D Bit 2 */ byte PTDPE3 :1; /* Internal Pull Enable for Port D Bit 3 */ byte PTDPE4 :1; /* Internal Pull Enable for Port D Bit 4 */ byte PTDPE5 :1; /* Internal Pull Enable for Port D Bit 5 */ byte PTDPE6 :1; /* Internal Pull Enable for Port D Bit 6 */ byte PTDPE7 :1; /* Internal Pull Enable for Port D Bit 7 */ } Bits; } PTDPESTR; extern volatile PTDPESTR _PTDPE @0xFFFF80C8; #define PTDPE _PTDPE.Byte #define PTDPE_PTDPE0 _PTDPE.Bits.PTDPE0 #define PTDPE_PTDPE1 _PTDPE.Bits.PTDPE1 #define PTDPE_PTDPE2 _PTDPE.Bits.PTDPE2 #define PTDPE_PTDPE3 _PTDPE.Bits.PTDPE3 #define PTDPE_PTDPE4 _PTDPE.Bits.PTDPE4 #define PTDPE_PTDPE5 _PTDPE.Bits.PTDPE5 #define PTDPE_PTDPE6 _PTDPE.Bits.PTDPE6 #define PTDPE_PTDPE7 _PTDPE.Bits.PTDPE7 #define PTDPE_PTDPE0_MASK 1 #define PTDPE_PTDPE1_MASK 2 #define PTDPE_PTDPE2_MASK 4 #define PTDPE_PTDPE3_MASK 8 #define PTDPE_PTDPE4_MASK 16 #define PTDPE_PTDPE5_MASK 32 #define PTDPE_PTDPE6_MASK 64 #define PTDPE_PTDPE7_MASK 128 /*** PTDSE - Port D Slew Rate Enable Register; 0xFFFF80C9 ***/ typedef union { byte Byte; struct { byte PTDSE0 :1; /* Output Slew Rate Enable for Port D Bit 0 */ byte PTDSE1 :1; /* Output Slew Rate Enable for Port D Bit 1 */ byte PTDSE2 :1; /* Output Slew Rate Enable for Port D Bit 2 */ byte PTDSE3 :1; /* Output Slew Rate Enable for Port D Bit 3 */ byte PTDSE4 :1; /* Output Slew Rate Enable for Port D Bit 4 */ byte PTDSE5 :1; /* Output Slew Rate Enable for Port D Bit 5 */ byte PTDSE6 :1; /* Output Slew Rate Enable for Port D Bit 6 */ byte PTDSE7 :1; /* Output Slew Rate Enable for Port D Bit 7 */ } Bits; } PTDSESTR; extern volatile PTDSESTR _PTDSE @0xFFFF80C9; #define PTDSE _PTDSE.Byte #define PTDSE_PTDSE0 _PTDSE.Bits.PTDSE0 #define PTDSE_PTDSE1 _PTDSE.Bits.PTDSE1 #define PTDSE_PTDSE2 _PTDSE.Bits.PTDSE2 #define PTDSE_PTDSE3 _PTDSE.Bits.PTDSE3 #define PTDSE_PTDSE4 _PTDSE.Bits.PTDSE4 #define PTDSE_PTDSE5 _PTDSE.Bits.PTDSE5 #define PTDSE_PTDSE6 _PTDSE.Bits.PTDSE6 #define PTDSE_PTDSE7 _PTDSE.Bits.PTDSE7 #define PTDSE_PTDSE0_MASK 1 #define PTDSE_PTDSE1_MASK 2 #define PTDSE_PTDSE2_MASK 4 #define PTDSE_PTDSE3_MASK 8 #define PTDSE_PTDSE4_MASK 16 #define PTDSE_PTDSE5_MASK 32 #define PTDSE_PTDSE6_MASK 64 #define PTDSE_PTDSE7_MASK 128 /*** PTDDS - Port D Drive Strength Selection Register; 0xFFFF80CA ***/ typedef union { byte Byte; struct { byte PTDDS0 :1; /* Output Drive Strength Selection for Port D Bit 0 */ byte PTDDS1 :1; /* Output Drive Strength Selection for Port D Bit 1 */ byte PTDDS2 :1; /* Output Drive Strength Selection for Port D Bit 2 */ byte PTDDS3 :1; /* Output Drive Strength Selection for Port D Bit 3 */ byte PTDDS4 :1; /* Output Drive Strength Selection for Port D Bit 4 */ byte PTDDS5 :1; /* Output Drive Strength Selection for Port D Bit 5 */ byte PTDDS6 :1; /* Output Drive Strength Selection for Port D Bit 6 */ byte PTDDS7 :1; /* Output Drive Strength Selection for Port D Bit 7 */ } Bits; } PTDDSSTR; extern volatile PTDDSSTR _PTDDS @0xFFFF80CA; #define PTDDS _PTDDS.Byte #define PTDDS_PTDDS0 _PTDDS.Bits.PTDDS0 #define PTDDS_PTDDS1 _PTDDS.Bits.PTDDS1 #define PTDDS_PTDDS2 _PTDDS.Bits.PTDDS2 #define PTDDS_PTDDS3 _PTDDS.Bits.PTDDS3 #define PTDDS_PTDDS4 _PTDDS.Bits.PTDDS4 #define PTDDS_PTDDS5 _PTDDS.Bits.PTDDS5 #define PTDDS_PTDDS6 _PTDDS.Bits.PTDDS6 #define PTDDS_PTDDS7 _PTDDS.Bits.PTDDS7 #define PTDDS_PTDDS0_MASK 1 #define PTDDS_PTDDS1_MASK 2 #define PTDDS_PTDDS2_MASK 4 #define PTDDS_PTDDS3_MASK 8 #define PTDDS_PTDDS4_MASK 16 #define PTDDS_PTDDS5_MASK 32 #define PTDDS_PTDDS6_MASK 64 #define PTDDS_PTDDS7_MASK 128 /*** PTDIFE - Port D Input Filter Enable Register; 0xFFFF80CB ***/ typedef union { byte Byte; struct { byte PTDIFE0 :1; /* Port D Input Filter Enable Bit 0 */ byte PTDIFE1 :1; /* Port D Input Filter Enable Bit 1 */ byte PTDIFE2 :1; /* Port D Input Filter Enable Bit 2 */ byte PTDIFE3 :1; /* Port D Input Filter Enable Bit 3 */ byte PTDIFE4 :1; /* Port D Input Filter Enable Bit 4 */ byte PTDIFE5 :1; /* Port D Input Filter Enable Bit 5 */ byte PTDIFE6 :1; /* Port D Input Filter Enable Bit 6 */ byte PTDIFE7 :1; /* Port D Input Filter Enable Bit 7 */ } Bits; } PTDIFESTR; extern volatile PTDIFESTR _PTDIFE @0xFFFF80CB; #define PTDIFE _PTDIFE.Byte #define PTDIFE_PTDIFE0 _PTDIFE.Bits.PTDIFE0 #define PTDIFE_PTDIFE1 _PTDIFE.Bits.PTDIFE1 #define PTDIFE_PTDIFE2 _PTDIFE.Bits.PTDIFE2 #define PTDIFE_PTDIFE3 _PTDIFE.Bits.PTDIFE3 #define PTDIFE_PTDIFE4 _PTDIFE.Bits.PTDIFE4 #define PTDIFE_PTDIFE5 _PTDIFE.Bits.PTDIFE5 #define PTDIFE_PTDIFE6 _PTDIFE.Bits.PTDIFE6 #define PTDIFE_PTDIFE7 _PTDIFE.Bits.PTDIFE7 #define PTDIFE_PTDIFE0_MASK 1 #define PTDIFE_PTDIFE1_MASK 2 #define PTDIFE_PTDIFE2_MASK 4 #define PTDIFE_PTDIFE3_MASK 8 #define PTDIFE_PTDIFE4_MASK 16 #define PTDIFE_PTDIFE5_MASK 32 #define PTDIFE_PTDIFE6_MASK 64 #define PTDIFE_PTDIFE7_MASK 128 /*** PTED - Port E Data Register; 0xFFFF8100 ***/ typedef union { byte Byte; struct { byte PTED0 :1; /* Port E Data Register Bit 0 */ byte PTED1 :1; /* Port E Data Register Bit 1 */ byte PTED2 :1; /* Port E Data Register Bit 2 */ byte PTED3 :1; /* Port E Data Register Bit 3 */ byte PTED4 :1; /* Port E Data Register Bit 4 */ byte PTED5 :1; /* Port E Data Register Bit 5 */ byte PTED6 :1; /* Port E Data Register Bit 6 */ byte PTED7 :1; /* Port E Data Register Bit 7 */ } Bits; } PTEDSTR; extern volatile PTEDSTR _PTED @0xFFFF8100; #define PTED _PTED.Byte #define PTED_PTED0 _PTED.Bits.PTED0 #define PTED_PTED1 _PTED.Bits.PTED1 #define PTED_PTED2 _PTED.Bits.PTED2 #define PTED_PTED3 _PTED.Bits.PTED3 #define PTED_PTED4 _PTED.Bits.PTED4 #define PTED_PTED5 _PTED.Bits.PTED5 #define PTED_PTED6 _PTED.Bits.PTED6 #define PTED_PTED7 _PTED.Bits.PTED7 #define PTED_PTED0_MASK 1 #define PTED_PTED1_MASK 2 #define PTED_PTED2_MASK 4 #define PTED_PTED3_MASK 8 #define PTED_PTED4_MASK 16 #define PTED_PTED5_MASK 32 #define PTED_PTED6_MASK 64 #define PTED_PTED7_MASK 128 /*** PTEDD - Port E Data Direction Register; 0xFFFF8101 ***/ typedef union { byte Byte; struct { byte PTEDD0 :1; /* Data Direction for Port E Bit 0 */ byte PTEDD1 :1; /* Data Direction for Port E Bit 1 */ byte PTEDD2 :1; /* Data Direction for Port E Bit 2 */ byte PTEDD3 :1; /* Data Direction for Port E Bit 3 */ byte PTEDD4 :1; /* Data Direction for Port E Bit 4 */ byte PTEDD5 :1; /* Data Direction for Port E Bit 5 */ byte PTEDD6 :1; /* Data Direction for Port E Bit 6 */ byte PTEDD7 :1; /* Data Direction for Port E Bit 7 */ } Bits; } PTEDDSTR; extern volatile PTEDDSTR _PTEDD @0xFFFF8101; #define PTEDD _PTEDD.Byte #define PTEDD_PTEDD0 _PTEDD.Bits.PTEDD0 #define PTEDD_PTEDD1 _PTEDD.Bits.PTEDD1 #define PTEDD_PTEDD2 _PTEDD.Bits.PTEDD2 #define PTEDD_PTEDD3 _PTEDD.Bits.PTEDD3 #define PTEDD_PTEDD4 _PTEDD.Bits.PTEDD4 #define PTEDD_PTEDD5 _PTEDD.Bits.PTEDD5 #define PTEDD_PTEDD6 _PTEDD.Bits.PTEDD6 #define PTEDD_PTEDD7 _PTEDD.Bits.PTEDD7 #define PTEDD_PTEDD0_MASK 1 #define PTEDD_PTEDD1_MASK 2 #define PTEDD_PTEDD2_MASK 4 #define PTEDD_PTEDD3_MASK 8 #define PTEDD_PTEDD4_MASK 16 #define PTEDD_PTEDD5_MASK 32 #define PTEDD_PTEDD6_MASK 64 #define PTEDD_PTEDD7_MASK 128 /*** PTESET - Port E Data Set Register; 0xFFFF8102 ***/ typedef union { byte Byte; struct { byte PTESET0 :1; /* Data Set for Port E Bit 0 */ byte PTESET1 :1; /* Data Set for Port E Bit 1 */ byte PTESET2 :1; /* Data Set for Port E Bit 2 */ byte PTESET3 :1; /* Data Set for Port E Bit 3 */ byte PTESET4 :1; /* Data Set for Port E Bit 4 */ byte PTESET5 :1; /* Data Set for Port E Bit 5 */ byte PTESET6 :1; /* Data Set for Port E Bit 6 */ byte PTESET7 :1; /* Data Set for Port E Bit 7 */ } Bits; } PTESETSTR; extern volatile PTESETSTR _PTESET @0xFFFF8102; #define PTESET _PTESET.Byte #define PTESET_PTESET0 _PTESET.Bits.PTESET0 #define PTESET_PTESET1 _PTESET.Bits.PTESET1 #define PTESET_PTESET2 _PTESET.Bits.PTESET2 #define PTESET_PTESET3 _PTESET.Bits.PTESET3 #define PTESET_PTESET4 _PTESET.Bits.PTESET4 #define PTESET_PTESET5 _PTESET.Bits.PTESET5 #define PTESET_PTESET6 _PTESET.Bits.PTESET6 #define PTESET_PTESET7 _PTESET.Bits.PTESET7 #define PTESET_PTESET0_MASK 1 #define PTESET_PTESET1_MASK 2 #define PTESET_PTESET2_MASK 4 #define PTESET_PTESET3_MASK 8 #define PTESET_PTESET4_MASK 16 #define PTESET_PTESET5_MASK 32 #define PTESET_PTESET6_MASK 64 #define PTESET_PTESET7_MASK 128 /*** PTECLR - Port E Data Clear Register; 0xFFFF8103 ***/ typedef union { byte Byte; struct { byte PTECLR0 :1; /* Data Clear for Port E Bit 0 */ byte PTECLR1 :1; /* Data Clear for Port E Bit 1 */ byte PTECLR2 :1; /* Data Clear for Port E Bit 2 */ byte PTECLR3 :1; /* Data Clear for Port E Bit 3 */ byte PTECLR4 :1; /* Data Clear for Port E Bit 4 */ byte PTECLR5 :1; /* Data Clear for Port E Bit 5 */ byte PTECLR6 :1; /* Data Clear for Port E Bit 6 */ byte PTECLR7 :1; /* Data Clear for Port E Bit 7 */ } Bits; } PTECLRSTR; extern volatile PTECLRSTR _PTECLR @0xFFFF8103; #define PTECLR _PTECLR.Byte #define PTECLR_PTECLR0 _PTECLR.Bits.PTECLR0 #define PTECLR_PTECLR1 _PTECLR.Bits.PTECLR1 #define PTECLR_PTECLR2 _PTECLR.Bits.PTECLR2 #define PTECLR_PTECLR3 _PTECLR.Bits.PTECLR3 #define PTECLR_PTECLR4 _PTECLR.Bits.PTECLR4 #define PTECLR_PTECLR5 _PTECLR.Bits.PTECLR5 #define PTECLR_PTECLR6 _PTECLR.Bits.PTECLR6 #define PTECLR_PTECLR7 _PTECLR.Bits.PTECLR7 #define PTECLR_PTECLR0_MASK 1 #define PTECLR_PTECLR1_MASK 2 #define PTECLR_PTECLR2_MASK 4 #define PTECLR_PTECLR3_MASK 8 #define PTECLR_PTECLR4_MASK 16 #define PTECLR_PTECLR5_MASK 32 #define PTECLR_PTECLR6_MASK 64 #define PTECLR_PTECLR7_MASK 128 /*** PTETOG - Port E Toggle Register; 0xFFFF8104 ***/ typedef union { byte Byte; struct { byte PTETOG0 :1; /* Toggle Enable for Port E Bit 0 */ byte PTETOG1 :1; /* Toggle Enable for Port E Bit 1 */ byte PTETOG2 :1; /* Toggle Enable for Port E Bit 2 */ byte PTETOG3 :1; /* Toggle Enable for Port E Bit 3 */ byte PTETOG4 :1; /* Toggle Enable for Port E Bit 4 */ byte PTETOG5 :1; /* Toggle Enable for Port E Bit 5 */ byte PTETOG6 :1; /* Toggle Enable for Port E Bit 6 */ byte PTETOG7 :1; /* Toggle Enable for Port E Bit 7 */ } Bits; } PTETOGSTR; extern volatile PTETOGSTR _PTETOG @0xFFFF8104; #define PTETOG _PTETOG.Byte #define PTETOG_PTETOG0 _PTETOG.Bits.PTETOG0 #define PTETOG_PTETOG1 _PTETOG.Bits.PTETOG1 #define PTETOG_PTETOG2 _PTETOG.Bits.PTETOG2 #define PTETOG_PTETOG3 _PTETOG.Bits.PTETOG3 #define PTETOG_PTETOG4 _PTETOG.Bits.PTETOG4 #define PTETOG_PTETOG5 _PTETOG.Bits.PTETOG5 #define PTETOG_PTETOG6 _PTETOG.Bits.PTETOG6 #define PTETOG_PTETOG7 _PTETOG.Bits.PTETOG7 #define PTETOG_PTETOG0_MASK 1 #define PTETOG_PTETOG1_MASK 2 #define PTETOG_PTETOG2_MASK 4 #define PTETOG_PTETOG3_MASK 8 #define PTETOG_PTETOG4_MASK 16 #define PTETOG_PTETOG5_MASK 32 #define PTETOG_PTETOG6_MASK 64 #define PTETOG_PTETOG7_MASK 128 /*** PTEPE - Port E Pull Enable Register; 0xFFFF8108 ***/ typedef union { byte Byte; struct { byte PTEPE0 :1; /* Internal Pull Enable for Port E Bit 0 */ byte PTEPE1 :1; /* Internal Pull Enable for Port E Bit 1 */ byte PTEPE2 :1; /* Internal Pull Enable for Port E Bit 2 */ byte PTEPE3 :1; /* Internal Pull Enable for Port E Bit 3 */ byte PTEPE4 :1; /* Internal Pull Enable for Port E Bit 4 */ byte PTEPE5 :1; /* Internal Pull Enable for Port E Bit 5 */ byte PTEPE6 :1; /* Internal Pull Enable for Port E Bit 6 */ byte PTEPE7 :1; /* Internal Pull Enable for Port E Bit 7 */ } Bits; } PTEPESTR; extern volatile PTEPESTR _PTEPE @0xFFFF8108; #define PTEPE _PTEPE.Byte #define PTEPE_PTEPE0 _PTEPE.Bits.PTEPE0 #define PTEPE_PTEPE1 _PTEPE.Bits.PTEPE1 #define PTEPE_PTEPE2 _PTEPE.Bits.PTEPE2 #define PTEPE_PTEPE3 _PTEPE.Bits.PTEPE3 #define PTEPE_PTEPE4 _PTEPE.Bits.PTEPE4 #define PTEPE_PTEPE5 _PTEPE.Bits.PTEPE5 #define PTEPE_PTEPE6 _PTEPE.Bits.PTEPE6 #define PTEPE_PTEPE7 _PTEPE.Bits.PTEPE7 #define PTEPE_PTEPE0_MASK 1 #define PTEPE_PTEPE1_MASK 2 #define PTEPE_PTEPE2_MASK 4 #define PTEPE_PTEPE3_MASK 8 #define PTEPE_PTEPE4_MASK 16 #define PTEPE_PTEPE5_MASK 32 #define PTEPE_PTEPE6_MASK 64 #define PTEPE_PTEPE7_MASK 128 /*** PTESE - Port E Slew Rate Enable Register; 0xFFFF8109 ***/ typedef union { byte Byte; struct { byte PTESE0 :1; /* Output Slew Rate Enable for Port E Bit 0 */ byte PTESE1 :1; /* Output Slew Rate Enable for Port E Bit 1 */ byte PTESE2 :1; /* Output Slew Rate Enable for Port E Bit 2 */ byte PTESE3 :1; /* Output Slew Rate Enable for Port E Bit 3 */ byte PTESE4 :1; /* Output Slew Rate Enable for Port E Bit 4 */ byte PTESE5 :1; /* Output Slew Rate Enable for Port E Bit 5 */ byte PTESE6 :1; /* Output Slew Rate Enable for Port E Bit 6 */ byte PTESE7 :1; /* Output Slew Rate Enable for Port E Bit 7 */ } Bits; } PTESESTR; extern volatile PTESESTR _PTESE @0xFFFF8109; #define PTESE _PTESE.Byte #define PTESE_PTESE0 _PTESE.Bits.PTESE0 #define PTESE_PTESE1 _PTESE.Bits.PTESE1 #define PTESE_PTESE2 _PTESE.Bits.PTESE2 #define PTESE_PTESE3 _PTESE.Bits.PTESE3 #define PTESE_PTESE4 _PTESE.Bits.PTESE4 #define PTESE_PTESE5 _PTESE.Bits.PTESE5 #define PTESE_PTESE6 _PTESE.Bits.PTESE6 #define PTESE_PTESE7 _PTESE.Bits.PTESE7 #define PTESE_PTESE0_MASK 1 #define PTESE_PTESE1_MASK 2 #define PTESE_PTESE2_MASK 4 #define PTESE_PTESE3_MASK 8 #define PTESE_PTESE4_MASK 16 #define PTESE_PTESE5_MASK 32 #define PTESE_PTESE6_MASK 64 #define PTESE_PTESE7_MASK 128 /*** PTEDS - Port E Drive Strength Selection Register; 0xFFFF810A ***/ typedef union { byte Byte; struct { byte PTEDS0 :1; /* Output Drive Strength Selection for Port E Bit 0 */ byte PTEDS1 :1; /* Output Drive Strength Selection for Port E Bit 1 */ byte PTEDS2 :1; /* Output Drive Strength Selection for Port E Bit 2 */ byte PTEDS3 :1; /* Output Drive Strength Selection for Port E Bit 3 */ byte PTEDS4 :1; /* Output Drive Strength Selection for Port E Bit 4 */ byte PTEDS5 :1; /* Output Drive Strength Selection for Port E Bit 5 */ byte PTEDS6 :1; /* Output Drive Strength Selection for Port E Bit 6 */ byte PTEDS7 :1; /* Output Drive Strength Selection for Port E Bit 7 */ } Bits; } PTEDSSTR; extern volatile PTEDSSTR _PTEDS @0xFFFF810A; #define PTEDS _PTEDS.Byte #define PTEDS_PTEDS0 _PTEDS.Bits.PTEDS0 #define PTEDS_PTEDS1 _PTEDS.Bits.PTEDS1 #define PTEDS_PTEDS2 _PTEDS.Bits.PTEDS2 #define PTEDS_PTEDS3 _PTEDS.Bits.PTEDS3 #define PTEDS_PTEDS4 _PTEDS.Bits.PTEDS4 #define PTEDS_PTEDS5 _PTEDS.Bits.PTEDS5 #define PTEDS_PTEDS6 _PTEDS.Bits.PTEDS6 #define PTEDS_PTEDS7 _PTEDS.Bits.PTEDS7 #define PTEDS_PTEDS0_MASK 1 #define PTEDS_PTEDS1_MASK 2 #define PTEDS_PTEDS2_MASK 4 #define PTEDS_PTEDS3_MASK 8 #define PTEDS_PTEDS4_MASK 16 #define PTEDS_PTEDS5_MASK 32 #define PTEDS_PTEDS6_MASK 64 #define PTEDS_PTEDS7_MASK 128 /*** PTEIFE - Port E Input Filter Enable Register; 0xFFFF810B ***/ typedef union { byte Byte; struct { byte PTEIFE0 :1; /* Port E Input Filter Enable Bit 0 */ byte PTEIFE1 :1; /* Port E Input Filter Enable Bit 1 */ byte PTEIFE2 :1; /* Port E Input Filter Enable Bit 2 */ byte PTEIFE3 :1; /* Port E Input Filter Enable Bit 3 */ byte PTEIFE4 :1; /* Port E Input Filter Enable Bit 4 */ byte PTEIFE5 :1; /* Port E Input Filter Enable Bit 5 */ byte PTEIFE6 :1; /* Port E Input Filter Enable Bit 6 */ byte PTEIFE7 :1; /* Port E Input Filter Enable Bit 7 */ } Bits; } PTEIFESTR; extern volatile PTEIFESTR _PTEIFE @0xFFFF810B; #define PTEIFE _PTEIFE.Byte #define PTEIFE_PTEIFE0 _PTEIFE.Bits.PTEIFE0 #define PTEIFE_PTEIFE1 _PTEIFE.Bits.PTEIFE1 #define PTEIFE_PTEIFE2 _PTEIFE.Bits.PTEIFE2 #define PTEIFE_PTEIFE3 _PTEIFE.Bits.PTEIFE3 #define PTEIFE_PTEIFE4 _PTEIFE.Bits.PTEIFE4 #define PTEIFE_PTEIFE5 _PTEIFE.Bits.PTEIFE5 #define PTEIFE_PTEIFE6 _PTEIFE.Bits.PTEIFE6 #define PTEIFE_PTEIFE7 _PTEIFE.Bits.PTEIFE7 #define PTEIFE_PTEIFE0_MASK 1 #define PTEIFE_PTEIFE1_MASK 2 #define PTEIFE_PTEIFE2_MASK 4 #define PTEIFE_PTEIFE3_MASK 8 #define PTEIFE_PTEIFE4_MASK 16 #define PTEIFE_PTEIFE5_MASK 32 #define PTEIFE_PTEIFE6_MASK 64 #define PTEIFE_PTEIFE7_MASK 128 /*** PTFD - Port F Data Register; 0xFFFF8140 ***/ typedef union { byte Byte; struct { byte PTFD0 :1; /* Port F Data Register Bit 0 */ byte PTFD1 :1; /* Port F Data Register Bit 1 */ byte PTFD2 :1; /* Port F Data Register Bit 2 */ byte PTFD3 :1; /* Port F Data Register Bit 3 */ byte PTFD4 :1; /* Port F Data Register Bit 4 */ byte PTFD5 :1; /* Port F Data Register Bit 5 */ byte PTFD6 :1; /* Port F Data Register Bit 6 */ byte PTFD7 :1; /* Port F Data Register Bit 7 */ } Bits; } PTFDSTR; extern volatile PTFDSTR _PTFD @0xFFFF8140; #define PTFD _PTFD.Byte #define PTFD_PTFD0 _PTFD.Bits.PTFD0 #define PTFD_PTFD1 _PTFD.Bits.PTFD1 #define PTFD_PTFD2 _PTFD.Bits.PTFD2 #define PTFD_PTFD3 _PTFD.Bits.PTFD3 #define PTFD_PTFD4 _PTFD.Bits.PTFD4 #define PTFD_PTFD5 _PTFD.Bits.PTFD5 #define PTFD_PTFD6 _PTFD.Bits.PTFD6 #define PTFD_PTFD7 _PTFD.Bits.PTFD7 #define PTFD_PTFD0_MASK 1 #define PTFD_PTFD1_MASK 2 #define PTFD_PTFD2_MASK 4 #define PTFD_PTFD3_MASK 8 #define PTFD_PTFD4_MASK 16 #define PTFD_PTFD5_MASK 32 #define PTFD_PTFD6_MASK 64 #define PTFD_PTFD7_MASK 128 /*** PTFDD - Port F Data Direction Register; 0xFFFF8141 ***/ typedef union { byte Byte; struct { byte PTFDD0 :1; /* Data Direction for Port F Bit 0 */ byte PTFDD1 :1; /* Data Direction for Port F Bit 1 */ byte PTFDD2 :1; /* Data Direction for Port F Bit 2 */ byte PTFDD3 :1; /* Data Direction for Port F Bit 3 */ byte PTFDD4 :1; /* Data Direction for Port F Bit 4 */ byte PTFDD5 :1; /* Data Direction for Port F Bit 5 */ byte PTFDD6 :1; /* Data Direction for Port F Bit 6 */ byte PTFDD7 :1; /* Data Direction for Port F Bit 7 */ } Bits; } PTFDDSTR; extern volatile PTFDDSTR _PTFDD @0xFFFF8141; #define PTFDD _PTFDD.Byte #define PTFDD_PTFDD0 _PTFDD.Bits.PTFDD0 #define PTFDD_PTFDD1 _PTFDD.Bits.PTFDD1 #define PTFDD_PTFDD2 _PTFDD.Bits.PTFDD2 #define PTFDD_PTFDD3 _PTFDD.Bits.PTFDD3 #define PTFDD_PTFDD4 _PTFDD.Bits.PTFDD4 #define PTFDD_PTFDD5 _PTFDD.Bits.PTFDD5 #define PTFDD_PTFDD6 _PTFDD.Bits.PTFDD6 #define PTFDD_PTFDD7 _PTFDD.Bits.PTFDD7 #define PTFDD_PTFDD0_MASK 1 #define PTFDD_PTFDD1_MASK 2 #define PTFDD_PTFDD2_MASK 4 #define PTFDD_PTFDD3_MASK 8 #define PTFDD_PTFDD4_MASK 16 #define PTFDD_PTFDD5_MASK 32 #define PTFDD_PTFDD6_MASK 64 #define PTFDD_PTFDD7_MASK 128 /*** PTFSET - Port F Data Set Register; 0xFFFF8142 ***/ typedef union { byte Byte; struct { byte PTFSET0 :1; /* Data Set for Port F Bit 0 */ byte PTFSET1 :1; /* Data Set for Port F Bit 1 */ byte PTFSET2 :1; /* Data Set for Port F Bit 2 */ byte PTFSET3 :1; /* Data Set for Port F Bit 3 */ byte PTFSET4 :1; /* Data Set for Port F Bit 4 */ byte PTFSET5 :1; /* Data Set for Port F Bit 5 */ byte PTFSET6 :1; /* Data Set for Port F Bit 6 */ byte PTFSET7 :1; /* Data Set for Port F Bit 7 */ } Bits; } PTFSETSTR; extern volatile PTFSETSTR _PTFSET @0xFFFF8142; #define PTFSET _PTFSET.Byte #define PTFSET_PTFSET0 _PTFSET.Bits.PTFSET0 #define PTFSET_PTFSET1 _PTFSET.Bits.PTFSET1 #define PTFSET_PTFSET2 _PTFSET.Bits.PTFSET2 #define PTFSET_PTFSET3 _PTFSET.Bits.PTFSET3 #define PTFSET_PTFSET4 _PTFSET.Bits.PTFSET4 #define PTFSET_PTFSET5 _PTFSET.Bits.PTFSET5 #define PTFSET_PTFSET6 _PTFSET.Bits.PTFSET6 #define PTFSET_PTFSET7 _PTFSET.Bits.PTFSET7 #define PTFSET_PTFSET0_MASK 1 #define PTFSET_PTFSET1_MASK 2 #define PTFSET_PTFSET2_MASK 4 #define PTFSET_PTFSET3_MASK 8 #define PTFSET_PTFSET4_MASK 16 #define PTFSET_PTFSET5_MASK 32 #define PTFSET_PTFSET6_MASK 64 #define PTFSET_PTFSET7_MASK 128 /*** PTFCLR - Port F Data Clear Register; 0xFFFF8143 ***/ typedef union { byte Byte; struct { byte PTFCLR0 :1; /* Data Clear for Port F Bit 0 */ byte PTFCLR1 :1; /* Data Clear for Port F Bit 1 */ byte PTFCLR2 :1; /* Data Clear for Port F Bit 2 */ byte PTFCLR3 :1; /* Data Clear for Port F Bit 3 */ byte PTFCLR4 :1; /* Data Clear for Port F Bit 4 */ byte PTFCLR5 :1; /* Data Clear for Port F Bit 5 */ byte PTFCLR6 :1; /* Data Clear for Port F Bit 6 */ byte PTFCLR7 :1; /* Data Clear for Port F Bit 7 */ } Bits; } PTFCLRSTR; extern volatile PTFCLRSTR _PTFCLR @0xFFFF8143; #define PTFCLR _PTFCLR.Byte #define PTFCLR_PTFCLR0 _PTFCLR.Bits.PTFCLR0 #define PTFCLR_PTFCLR1 _PTFCLR.Bits.PTFCLR1 #define PTFCLR_PTFCLR2 _PTFCLR.Bits.PTFCLR2 #define PTFCLR_PTFCLR3 _PTFCLR.Bits.PTFCLR3 #define PTFCLR_PTFCLR4 _PTFCLR.Bits.PTFCLR4 #define PTFCLR_PTFCLR5 _PTFCLR.Bits.PTFCLR5 #define PTFCLR_PTFCLR6 _PTFCLR.Bits.PTFCLR6 #define PTFCLR_PTFCLR7 _PTFCLR.Bits.PTFCLR7 #define PTFCLR_PTFCLR0_MASK 1 #define PTFCLR_PTFCLR1_MASK 2 #define PTFCLR_PTFCLR2_MASK 4 #define PTFCLR_PTFCLR3_MASK 8 #define PTFCLR_PTFCLR4_MASK 16 #define PTFCLR_PTFCLR5_MASK 32 #define PTFCLR_PTFCLR6_MASK 64 #define PTFCLR_PTFCLR7_MASK 128 /*** PTFTOG - Port F Toggle Register; 0xFFFF8144 ***/ typedef union { byte Byte; struct { byte PTFTOG0 :1; /* Toggle Enable for Port F Bit 0 */ byte PTFTOG1 :1; /* Toggle Enable for Port F Bit 1 */ byte PTFTOG2 :1; /* Toggle Enable for Port F Bit 2 */ byte PTFTOG3 :1; /* Toggle Enable for Port F Bit 3 */ byte PTFTOG4 :1; /* Toggle Enable for Port F Bit 4 */ byte PTFTOG5 :1; /* Toggle Enable for Port F Bit 5 */ byte PTFTOG6 :1; /* Toggle Enable for Port F Bit 6 */ byte PTFTOG7 :1; /* Toggle Enable for Port F Bit 7 */ } Bits; } PTFTOGSTR; extern volatile PTFTOGSTR _PTFTOG @0xFFFF8144; #define PTFTOG _PTFTOG.Byte #define PTFTOG_PTFTOG0 _PTFTOG.Bits.PTFTOG0 #define PTFTOG_PTFTOG1 _PTFTOG.Bits.PTFTOG1 #define PTFTOG_PTFTOG2 _PTFTOG.Bits.PTFTOG2 #define PTFTOG_PTFTOG3 _PTFTOG.Bits.PTFTOG3 #define PTFTOG_PTFTOG4 _PTFTOG.Bits.PTFTOG4 #define PTFTOG_PTFTOG5 _PTFTOG.Bits.PTFTOG5 #define PTFTOG_PTFTOG6 _PTFTOG.Bits.PTFTOG6 #define PTFTOG_PTFTOG7 _PTFTOG.Bits.PTFTOG7 #define PTFTOG_PTFTOG0_MASK 1 #define PTFTOG_PTFTOG1_MASK 2 #define PTFTOG_PTFTOG2_MASK 4 #define PTFTOG_PTFTOG3_MASK 8 #define PTFTOG_PTFTOG4_MASK 16 #define PTFTOG_PTFTOG5_MASK 32 #define PTFTOG_PTFTOG6_MASK 64 #define PTFTOG_PTFTOG7_MASK 128 /*** PTFPE - Port F Pull Enable Register; 0xFFFF8148 ***/ typedef union { byte Byte; struct { byte PTFPE0 :1; /* Internal Pull Enable for Port F Bit 0 */ byte PTFPE1 :1; /* Internal Pull Enable for Port F Bit 1 */ byte PTFPE2 :1; /* Internal Pull Enable for Port F Bit 2 */ byte PTFPE3 :1; /* Internal Pull Enable for Port F Bit 3 */ byte PTFPE4 :1; /* Internal Pull Enable for Port F Bit 4 */ byte PTFPE5 :1; /* Internal Pull Enable for Port F Bit 5 */ byte PTFPE6 :1; /* Internal Pull Enable for Port F Bit 6 */ byte PTFPE7 :1; /* Internal Pull Enable for Port F Bit 7 */ } Bits; } PTFPESTR; extern volatile PTFPESTR _PTFPE @0xFFFF8148; #define PTFPE _PTFPE.Byte #define PTFPE_PTFPE0 _PTFPE.Bits.PTFPE0 #define PTFPE_PTFPE1 _PTFPE.Bits.PTFPE1 #define PTFPE_PTFPE2 _PTFPE.Bits.PTFPE2 #define PTFPE_PTFPE3 _PTFPE.Bits.PTFPE3 #define PTFPE_PTFPE4 _PTFPE.Bits.PTFPE4 #define PTFPE_PTFPE5 _PTFPE.Bits.PTFPE5 #define PTFPE_PTFPE6 _PTFPE.Bits.PTFPE6 #define PTFPE_PTFPE7 _PTFPE.Bits.PTFPE7 #define PTFPE_PTFPE0_MASK 1 #define PTFPE_PTFPE1_MASK 2 #define PTFPE_PTFPE2_MASK 4 #define PTFPE_PTFPE3_MASK 8 #define PTFPE_PTFPE4_MASK 16 #define PTFPE_PTFPE5_MASK 32 #define PTFPE_PTFPE6_MASK 64 #define PTFPE_PTFPE7_MASK 128 /*** PTFSE - Port F Slew Rate Enable Register; 0xFFFF8149 ***/ typedef union { byte Byte; struct { byte PTFSE0 :1; /* Output Slew Rate Enable for Port F Bit 0 */ byte PTFSE1 :1; /* Output Slew Rate Enable for Port F Bit 1 */ byte PTFSE2 :1; /* Output Slew Rate Enable for Port F Bit 2 */ byte PTFSE3 :1; /* Output Slew Rate Enable for Port F Bit 3 */ byte PTFSE4 :1; /* Output Slew Rate Enable for Port F Bit 4 */ byte PTFSE5 :1; /* Output Slew Rate Enable for Port F Bit 5 */ byte PTFSE6 :1; /* Output Slew Rate Enable for Port F Bit 6 */ byte PTFSE7 :1; /* Output Slew Rate Enable for Port F Bit 7 */ } Bits; } PTFSESTR; extern volatile PTFSESTR _PTFSE @0xFFFF8149; #define PTFSE _PTFSE.Byte #define PTFSE_PTFSE0 _PTFSE.Bits.PTFSE0 #define PTFSE_PTFSE1 _PTFSE.Bits.PTFSE1 #define PTFSE_PTFSE2 _PTFSE.Bits.PTFSE2 #define PTFSE_PTFSE3 _PTFSE.Bits.PTFSE3 #define PTFSE_PTFSE4 _PTFSE.Bits.PTFSE4 #define PTFSE_PTFSE5 _PTFSE.Bits.PTFSE5 #define PTFSE_PTFSE6 _PTFSE.Bits.PTFSE6 #define PTFSE_PTFSE7 _PTFSE.Bits.PTFSE7 #define PTFSE_PTFSE0_MASK 1 #define PTFSE_PTFSE1_MASK 2 #define PTFSE_PTFSE2_MASK 4 #define PTFSE_PTFSE3_MASK 8 #define PTFSE_PTFSE4_MASK 16 #define PTFSE_PTFSE5_MASK 32 #define PTFSE_PTFSE6_MASK 64 #define PTFSE_PTFSE7_MASK 128 /*** PTFDS - Port F Drive Strength Selection Register; 0xFFFF814A ***/ typedef union { byte Byte; struct { byte PTFDS0 :1; /* Output Drive Strength Selection for Port F Bit 0 */ byte PTFDS1 :1; /* Output Drive Strength Selection for Port F Bit 1 */ byte PTFDS2 :1; /* Output Drive Strength Selection for Port F Bit 2 */ byte PTFDS3 :1; /* Output Drive Strength Selection for Port F Bit 3 */ byte PTFDS4 :1; /* Output Drive Strength Selection for Port F Bit 4 */ byte PTFDS5 :1; /* Output Drive Strength Selection for Port F Bit 5 */ byte PTFDS6 :1; /* Output Drive Strength Selection for Port F Bit 6 */ byte PTFDS7 :1; /* Output Drive Strength Selection for Port F Bit 7 */ } Bits; } PTFDSSTR; extern volatile PTFDSSTR _PTFDS @0xFFFF814A; #define PTFDS _PTFDS.Byte #define PTFDS_PTFDS0 _PTFDS.Bits.PTFDS0 #define PTFDS_PTFDS1 _PTFDS.Bits.PTFDS1 #define PTFDS_PTFDS2 _PTFDS.Bits.PTFDS2 #define PTFDS_PTFDS3 _PTFDS.Bits.PTFDS3 #define PTFDS_PTFDS4 _PTFDS.Bits.PTFDS4 #define PTFDS_PTFDS5 _PTFDS.Bits.PTFDS5 #define PTFDS_PTFDS6 _PTFDS.Bits.PTFDS6 #define PTFDS_PTFDS7 _PTFDS.Bits.PTFDS7 #define PTFDS_PTFDS0_MASK 1 #define PTFDS_PTFDS1_MASK 2 #define PTFDS_PTFDS2_MASK 4 #define PTFDS_PTFDS3_MASK 8 #define PTFDS_PTFDS4_MASK 16 #define PTFDS_PTFDS5_MASK 32 #define PTFDS_PTFDS6_MASK 64 #define PTFDS_PTFDS7_MASK 128 /*** PTFIFE - Port F Input Filter Enable Register; 0xFFFF814B ***/ typedef union { byte Byte; struct { byte PTFIFE0 :1; /* Port F Input Filter Enable Bit 0 */ byte PTFIFE1 :1; /* Port F Input Filter Enable Bit 1 */ byte PTFIFE2 :1; /* Port F Input Filter Enable Bit 2 */ byte PTFIFE3 :1; /* Port F Input Filter Enable Bit 3 */ byte PTFIFE4 :1; /* Port F Input Filter Enable Bit 4 */ byte PTFIFE5 :1; /* Port F Input Filter Enable Bit 5 */ byte PTFIFE6 :1; /* Port F Input Filter Enable Bit 6 */ byte PTFIFE7 :1; /* Port F Input Filter Enable Bit 7 */ } Bits; } PTFIFESTR; extern volatile PTFIFESTR _PTFIFE @0xFFFF814B; #define PTFIFE _PTFIFE.Byte #define PTFIFE_PTFIFE0 _PTFIFE.Bits.PTFIFE0 #define PTFIFE_PTFIFE1 _PTFIFE.Bits.PTFIFE1 #define PTFIFE_PTFIFE2 _PTFIFE.Bits.PTFIFE2 #define PTFIFE_PTFIFE3 _PTFIFE.Bits.PTFIFE3 #define PTFIFE_PTFIFE4 _PTFIFE.Bits.PTFIFE4 #define PTFIFE_PTFIFE5 _PTFIFE.Bits.PTFIFE5 #define PTFIFE_PTFIFE6 _PTFIFE.Bits.PTFIFE6 #define PTFIFE_PTFIFE7 _PTFIFE.Bits.PTFIFE7 #define PTFIFE_PTFIFE0_MASK 1 #define PTFIFE_PTFIFE1_MASK 2 #define PTFIFE_PTFIFE2_MASK 4 #define PTFIFE_PTFIFE3_MASK 8 #define PTFIFE_PTFIFE4_MASK 16 #define PTFIFE_PTFIFE5_MASK 32 #define PTFIFE_PTFIFE6_MASK 64 #define PTFIFE_PTFIFE7_MASK 128 /*** KBI1SC - KBI1 Status and Control Register; 0xFFFF8180 ***/ typedef union { byte Byte; struct { byte KBIMOD :1; /* Keyboard Detection Mode */ byte KBIE :1; /* Keyboard Interrupt Enable */ byte KBACK :1; /* Keyboard Interrupt Acknowledge */ byte KBF :1; /* Keyboard Interrupt Flag */ byte :1; byte :1; byte :1; byte :1; } Bits; } KBI1SCSTR; extern volatile KBI1SCSTR _KBI1SC @0xFFFF8180; #define KBI1SC _KBI1SC.Byte #define KBI1SC_KBIMOD _KBI1SC.Bits.KBIMOD #define KBI1SC_KBIE _KBI1SC.Bits.KBIE #define KBI1SC_KBACK _KBI1SC.Bits.KBACK #define KBI1SC_KBF _KBI1SC.Bits.KBF #define KBI1SC_KBIMOD_MASK 1 #define KBI1SC_KBIE_MASK 2 #define KBI1SC_KBACK_MASK 4 #define KBI1SC_KBF_MASK 8 /*** KBI1PE - KBI1 Pin Enable Register; 0xFFFF8181 ***/ typedef union { byte Byte; struct { byte KBIPE0 :1; /* Keyboard Pin Enable for KBI Port Bit 0 */ byte KBIPE1 :1; /* Keyboard Pin Enable for KBI Port Bit 1 */ byte KBIPE2 :1; /* Keyboard Pin Enable for KBI Port Bit 2 */ byte KBIPE3 :1; /* Keyboard Pin Enable for KBI Port Bit 3 */ byte KBIPE4 :1; /* Keyboard Pin Enable for KBI Port Bit 4 */ byte KBIPE5 :1; /* Keyboard Pin Enable for KBI Port Bit 5 */ byte KBIPE6 :1; /* Keyboard Pin Enable for KBI Port Bit 6 */ byte KBIPE7 :1; /* Keyboard Pin Enable for KBI Port Bit 7 */ } Bits; } KBI1PESTR; extern volatile KBI1PESTR _KBI1PE @0xFFFF8181; #define KBI1PE _KBI1PE.Byte #define KBI1PE_KBIPE0 _KBI1PE.Bits.KBIPE0 #define KBI1PE_KBIPE1 _KBI1PE.Bits.KBIPE1 #define KBI1PE_KBIPE2 _KBI1PE.Bits.KBIPE2 #define KBI1PE_KBIPE3 _KBI1PE.Bits.KBIPE3 #define KBI1PE_KBIPE4 _KBI1PE.Bits.KBIPE4 #define KBI1PE_KBIPE5 _KBI1PE.Bits.KBIPE5 #define KBI1PE_KBIPE6 _KBI1PE.Bits.KBIPE6 #define KBI1PE_KBIPE7 _KBI1PE.Bits.KBIPE7 #define KBI1PE_KBIPE0_MASK 1 #define KBI1PE_KBIPE1_MASK 2 #define KBI1PE_KBIPE2_MASK 4 #define KBI1PE_KBIPE3_MASK 8 #define KBI1PE_KBIPE4_MASK 16 #define KBI1PE_KBIPE5_MASK 32 #define KBI1PE_KBIPE6_MASK 64 #define KBI1PE_KBIPE7_MASK 128 /*** KBI1ES - KBI1 Edge Select Register; 0xFFFF8182 ***/ typedef union { byte Byte; struct { byte KBEDG0 :1; /* Keyboard Edge Select Bit 0 */ byte KBEDG1 :1; /* Keyboard Edge Select Bit 1 */ byte KBEDG2 :1; /* Keyboard Edge Select Bit 2 */ byte KBEDG3 :1; /* Keyboard Edge Select Bit 3 */ byte KBEDG4 :1; /* Keyboard Edge Select Bit 4 */ byte KBEDG5 :1; /* Keyboard Edge Select Bit 5 */ byte KBEDG6 :1; /* Keyboard Edge Select Bit 6 */ byte KBEDG7 :1; /* Keyboard Edge Select Bit 7 */ } Bits; } KBI1ESSTR; extern volatile KBI1ESSTR _KBI1ES @0xFFFF8182; #define KBI1ES _KBI1ES.Byte #define KBI1ES_KBEDG0 _KBI1ES.Bits.KBEDG0 #define KBI1ES_KBEDG1 _KBI1ES.Bits.KBEDG1 #define KBI1ES_KBEDG2 _KBI1ES.Bits.KBEDG2 #define KBI1ES_KBEDG3 _KBI1ES.Bits.KBEDG3 #define KBI1ES_KBEDG4 _KBI1ES.Bits.KBEDG4 #define KBI1ES_KBEDG5 _KBI1ES.Bits.KBEDG5 #define KBI1ES_KBEDG6 _KBI1ES.Bits.KBEDG6 #define KBI1ES_KBEDG7 _KBI1ES.Bits.KBEDG7 #define KBI1ES_KBEDG0_MASK 1 #define KBI1ES_KBEDG1_MASK 2 #define KBI1ES_KBEDG2_MASK 4 #define KBI1ES_KBEDG3_MASK 8 #define KBI1ES_KBEDG4_MASK 16 #define KBI1ES_KBEDG5_MASK 32 #define KBI1ES_KBEDG6_MASK 64 #define KBI1ES_KBEDG7_MASK 128 /*** KBI2SC - KBI2 Status and Control Register; 0xFFFF81A0 ***/ typedef union { byte Byte; struct { byte KBIMOD :1; /* Keyboard Detection Mode */ byte KBIE :1; /* Keyboard Interrupt Enable */ byte KBACK :1; /* Keyboard Interrupt Acknowledge */ byte KBF :1; /* Keyboard Interrupt Flag */ byte :1; byte :1; byte :1; byte :1; } Bits; } KBI2SCSTR; extern volatile KBI2SCSTR _KBI2SC @0xFFFF81A0; #define KBI2SC _KBI2SC.Byte #define KBI2SC_KBIMOD _KBI2SC.Bits.KBIMOD #define KBI2SC_KBIE _KBI2SC.Bits.KBIE #define KBI2SC_KBACK _KBI2SC.Bits.KBACK #define KBI2SC_KBF _KBI2SC.Bits.KBF #define KBI2SC_KBIMOD_MASK 1 #define KBI2SC_KBIE_MASK 2 #define KBI2SC_KBACK_MASK 4 #define KBI2SC_KBF_MASK 8 /*** KBI2PE - KBI2 Pin Enable Register; 0xFFFF81A1 ***/ typedef union { byte Byte; struct { byte KBIPE0 :1; /* Keyboard Pin Enable for KBI Port Bit 0 */ byte KBIPE1 :1; /* Keyboard Pin Enable for KBI Port Bit 1 */ byte KBIPE2 :1; /* Keyboard Pin Enable for KBI Port Bit 2 */ byte KBIPE3 :1; /* Keyboard Pin Enable for KBI Port Bit 3 */ byte KBIPE4 :1; /* Keyboard Pin Enable for KBI Port Bit 4 */ byte KBIPE5 :1; /* Keyboard Pin Enable for KBI Port Bit 5 */ byte KBIPE6 :1; /* Keyboard Pin Enable for KBI Port Bit 6 */ byte KBIPE7 :1; /* Keyboard Pin Enable for KBI Port Bit 7 */ } Bits; } KBI2PESTR; extern volatile KBI2PESTR _KBI2PE @0xFFFF81A1; #define KBI2PE _KBI2PE.Byte #define KBI2PE_KBIPE0 _KBI2PE.Bits.KBIPE0 #define KBI2PE_KBIPE1 _KBI2PE.Bits.KBIPE1 #define KBI2PE_KBIPE2 _KBI2PE.Bits.KBIPE2 #define KBI2PE_KBIPE3 _KBI2PE.Bits.KBIPE3 #define KBI2PE_KBIPE4 _KBI2PE.Bits.KBIPE4 #define KBI2PE_KBIPE5 _KBI2PE.Bits.KBIPE5 #define KBI2PE_KBIPE6 _KBI2PE.Bits.KBIPE6 #define KBI2PE_KBIPE7 _KBI2PE.Bits.KBIPE7 #define KBI2PE_KBIPE0_MASK 1 #define KBI2PE_KBIPE1_MASK 2 #define KBI2PE_KBIPE2_MASK 4 #define KBI2PE_KBIPE3_MASK 8 #define KBI2PE_KBIPE4_MASK 16 #define KBI2PE_KBIPE5_MASK 32 #define KBI2PE_KBIPE6_MASK 64 #define KBI2PE_KBIPE7_MASK 128 /*** KBI2ES - KBI2 Edge Select Register; 0xFFFF81A2 ***/ typedef union { byte Byte; struct { byte KBEDG0 :1; /* Keyboard Edge Select Bit 0 */ byte KBEDG1 :1; /* Keyboard Edge Select Bit 1 */ byte KBEDG2 :1; /* Keyboard Edge Select Bit 2 */ byte KBEDG3 :1; /* Keyboard Edge Select Bit 3 */ byte KBEDG4 :1; /* Keyboard Edge Select Bit 4 */ byte KBEDG5 :1; /* Keyboard Edge Select Bit 5 */ byte KBEDG6 :1; /* Keyboard Edge Select Bit 6 */ byte KBEDG7 :1; /* Keyboard Edge Select Bit 7 */ } Bits; } KBI2ESSTR; extern volatile KBI2ESSTR _KBI2ES @0xFFFF81A2; #define KBI2ES _KBI2ES.Byte #define KBI2ES_KBEDG0 _KBI2ES.Bits.KBEDG0 #define KBI2ES_KBEDG1 _KBI2ES.Bits.KBEDG1 #define KBI2ES_KBEDG2 _KBI2ES.Bits.KBEDG2 #define KBI2ES_KBEDG3 _KBI2ES.Bits.KBEDG3 #define KBI2ES_KBEDG4 _KBI2ES.Bits.KBEDG4 #define KBI2ES_KBEDG5 _KBI2ES.Bits.KBEDG5 #define KBI2ES_KBEDG6 _KBI2ES.Bits.KBEDG6 #define KBI2ES_KBEDG7 _KBI2ES.Bits.KBEDG7 #define KBI2ES_KBEDG0_MASK 1 #define KBI2ES_KBEDG1_MASK 2 #define KBI2ES_KBEDG2_MASK 4 #define KBI2ES_KBEDG3_MASK 8 #define KBI2ES_KBEDG4_MASK 16 #define KBI2ES_KBEDG5_MASK 32 #define KBI2ES_KBEDG6_MASK 64 #define KBI2ES_KBEDG7_MASK 128 /*** IRQSC - Interrupt request status and control register; 0xFFFF81C0 ***/ typedef union { byte Byte; struct { byte IRQMOD :1; /* IRQ Detection Mode */ byte IRQIE :1; /* IRQ Interrupt Enable */ byte IRQACK :1; /* IRQ Acknowledge */ byte IRQF :1; /* IRQ Flag */ byte IRQPE :1; /* IRQ Pin Enable */ byte IRQEDG :1; /* IRQ Edge Select */ byte IRQPDD :1; /* IRQ Pull Device Disable */ byte :1; } Bits; } IRQSCSTR; extern volatile IRQSCSTR _IRQSC @0xFFFF81C0; #define IRQSC _IRQSC.Byte #define IRQSC_IRQMOD _IRQSC.Bits.IRQMOD #define IRQSC_IRQIE _IRQSC.Bits.IRQIE #define IRQSC_IRQACK _IRQSC.Bits.IRQACK #define IRQSC_IRQF _IRQSC.Bits.IRQF #define IRQSC_IRQPE _IRQSC.Bits.IRQPE #define IRQSC_IRQEDG _IRQSC.Bits.IRQEDG #define IRQSC_IRQPDD _IRQSC.Bits.IRQPDD #define IRQSC_IRQMOD_MASK 1 #define IRQSC_IRQIE_MASK 2 #define IRQSC_IRQACK_MASK 4 #define IRQSC_IRQF_MASK 8 #define IRQSC_IRQPE_MASK 16 #define IRQSC_IRQEDG_MASK 32 #define IRQSC_IRQPDD_MASK 64 /*** PTAPF1 - Port A Routing Register 1; 0xFFFF8200 ***/ typedef union { byte Byte; struct { byte A40 :1; /* Port PTA4 Pin Mux Controls, bit 0 */ byte A41 :1; /* Port PTA4 Pin Mux Controls, bit 1 */ byte A50 :1; /* Port PTA5 Pin Mux Controls, bit 0 */ byte A51 :1; /* Port PTA5 Pin Mux Controls, bit 1 */ byte A60 :1; /* Port PTA6 Pin Mux Controls, bit 0 */ byte A61 :1; /* Port PTA6 Pin Mux Controls, bit 1 */ byte A70 :1; /* Port PTA7 Pin Mux Controls, bit 0 */ byte A71 :1; /* Port PTA7 Pin Mux Controls, bit 1 */ } Bits; struct { byte grpA4 :2; byte grpA5 :2; byte grpA6 :2; byte grpA7 :2; } MergedBits; } PTAPF1STR; extern volatile PTAPF1STR _PTAPF1 @0xFFFF8200; #define PTAPF1 _PTAPF1.Byte #define PTAPF1_A40 _PTAPF1.Bits.A40 #define PTAPF1_A41 _PTAPF1.Bits.A41 #define PTAPF1_A50 _PTAPF1.Bits.A50 #define PTAPF1_A51 _PTAPF1.Bits.A51 #define PTAPF1_A60 _PTAPF1.Bits.A60 #define PTAPF1_A61 _PTAPF1.Bits.A61 #define PTAPF1_A70 _PTAPF1.Bits.A70 #define PTAPF1_A71 _PTAPF1.Bits.A71 #define PTAPF1_A4 _PTAPF1.MergedBits.grpA4 #define PTAPF1_A5 _PTAPF1.MergedBits.grpA5 #define PTAPF1_A6 _PTAPF1.MergedBits.grpA6 #define PTAPF1_A7 _PTAPF1.MergedBits.grpA7 #define PTAPF1_A40_MASK 1 #define PTAPF1_A41_MASK 2 #define PTAPF1_A50_MASK 4 #define PTAPF1_A51_MASK 8 #define PTAPF1_A60_MASK 16 #define PTAPF1_A61_MASK 32 #define PTAPF1_A70_MASK 64 #define PTAPF1_A71_MASK 128 #define PTAPF1_A4_MASK 3 #define PTAPF1_A4_BITNUM 0 #define PTAPF1_A5_MASK 12 #define PTAPF1_A5_BITNUM 2 #define PTAPF1_A6_MASK 48 #define PTAPF1_A6_BITNUM 4 #define PTAPF1_A7_MASK 192 #define PTAPF1_A7_BITNUM 6 /*** PTAPF2 - Port A Routing Register 2; 0xFFFF8201 ***/ typedef union { byte Byte; struct { byte A00 :1; /* Port PTA0 Pin Mux Controls, bit 0 */ byte A01 :1; /* Port PTA0 Pin Mux Controls, bit 1 */ byte A10 :1; /* Port PTA1 Pin Mux Controls, bit 0 */ byte A11 :1; /* Port PTA1 Pin Mux Controls, bit 1 */ byte A20 :1; /* Port PTA2 Pin Mux Controls, bit 0 */ byte A21 :1; /* Port PTA2 Pin Mux Controls, bit 1 */ byte A30 :1; /* Port PTA3 Pin Mux Controls, bit 0 */ byte A31 :1; /* Port PTA3 Pin Mux Controls, bit 1 */ } Bits; struct { byte grpA0 :2; byte grpA1 :2; byte grpA2 :2; byte grpA3 :2; } MergedBits; } PTAPF2STR; extern volatile PTAPF2STR _PTAPF2 @0xFFFF8201; #define PTAPF2 _PTAPF2.Byte #define PTAPF2_A00 _PTAPF2.Bits.A00 #define PTAPF2_A01 _PTAPF2.Bits.A01 #define PTAPF2_A10 _PTAPF2.Bits.A10 #define PTAPF2_A11 _PTAPF2.Bits.A11 #define PTAPF2_A20 _PTAPF2.Bits.A20 #define PTAPF2_A21 _PTAPF2.Bits.A21 #define PTAPF2_A30 _PTAPF2.Bits.A30 #define PTAPF2_A31 _PTAPF2.Bits.A31 #define PTAPF2_A0 _PTAPF2.MergedBits.grpA0 #define PTAPF2_A1 _PTAPF2.MergedBits.grpA1 #define PTAPF2_A2 _PTAPF2.MergedBits.grpA2 #define PTAPF2_A3 _PTAPF2.MergedBits.grpA3 #define PTAPF2_A00_MASK 1 #define PTAPF2_A01_MASK 2 #define PTAPF2_A10_MASK 4 #define PTAPF2_A11_MASK 8 #define PTAPF2_A20_MASK 16 #define PTAPF2_A21_MASK 32 #define PTAPF2_A30_MASK 64 #define PTAPF2_A31_MASK 128 #define PTAPF2_A0_MASK 3 #define PTAPF2_A0_BITNUM 0 #define PTAPF2_A1_MASK 12 #define PTAPF2_A1_BITNUM 2 #define PTAPF2_A2_MASK 48 #define PTAPF2_A2_BITNUM 4 #define PTAPF2_A3_MASK 192 #define PTAPF2_A3_BITNUM 6 /*** PTBPF1 - Port B Routing Register 1; 0xFFFF8202 ***/ typedef union { byte Byte; struct { byte B40 :1; /* Port PTB4 Pin Mux Controls, bit 0 */ byte B41 :1; /* Port PTB4 Pin Mux Controls, bit 1 */ byte B50 :1; /* Port PTB5 Pin Mux Controls, bit 0 */ byte B51 :1; /* Port PTB5 Pin Mux Controls, bit 1 */ byte B60 :1; /* Port PTB6 Pin Mux Controls, bit 0 */ byte B61 :1; /* Port PTB6 Pin Mux Controls, bit 1 */ byte B70 :1; /* Port PTB7 Pin Mux Controls, bit 0 */ byte B71 :1; /* Port PTB7 Pin Mux Controls, bit 1 */ } Bits; struct { byte grpB4 :2; byte grpB5 :2; byte grpB6 :2; byte grpB7 :2; } MergedBits; } PTBPF1STR; extern volatile PTBPF1STR _PTBPF1 @0xFFFF8202; #define PTBPF1 _PTBPF1.Byte #define PTBPF1_B40 _PTBPF1.Bits.B40 #define PTBPF1_B41 _PTBPF1.Bits.B41 #define PTBPF1_B50 _PTBPF1.Bits.B50 #define PTBPF1_B51 _PTBPF1.Bits.B51 #define PTBPF1_B60 _PTBPF1.Bits.B60 #define PTBPF1_B61 _PTBPF1.Bits.B61 #define PTBPF1_B70 _PTBPF1.Bits.B70 #define PTBPF1_B71 _PTBPF1.Bits.B71 #define PTBPF1_B4 _PTBPF1.MergedBits.grpB4 #define PTBPF1_B5 _PTBPF1.MergedBits.grpB5 #define PTBPF1_B6 _PTBPF1.MergedBits.grpB6 #define PTBPF1_B7 _PTBPF1.MergedBits.grpB7 #define PTBPF1_B40_MASK 1 #define PTBPF1_B41_MASK 2 #define PTBPF1_B50_MASK 4 #define PTBPF1_B51_MASK 8 #define PTBPF1_B60_MASK 16 #define PTBPF1_B61_MASK 32 #define PTBPF1_B70_MASK 64 #define PTBPF1_B71_MASK 128 #define PTBPF1_B4_MASK 3 #define PTBPF1_B4_BITNUM 0 #define PTBPF1_B5_MASK 12 #define PTBPF1_B5_BITNUM 2 #define PTBPF1_B6_MASK 48 #define PTBPF1_B6_BITNUM 4 #define PTBPF1_B7_MASK 192 #define PTBPF1_B7_BITNUM 6 /*** PTBPF2 - Port B Routing Register 2; 0xFFFF8203 ***/ typedef union { byte Byte; struct { byte B00 :1; /* Port PTB0 Pin Mux Controls, bit 0 */ byte B01 :1; /* Port PTB0 Pin Mux Controls, bit 1 */ byte B10 :1; /* Port PTB1 Pin Mux Controls, bit 0 */ byte B11 :1; /* Port PTB1 Pin Mux Controls, bit 1 */ byte B20 :1; /* Port PTB2 Pin Mux Controls, bit 0 */ byte B21 :1; /* Port PTB2 Pin Mux Controls, bit 1 */ byte B30 :1; /* Port PTB3 Pin Mux Controls, bit 0 */ byte B31 :1; /* Port PTB3 Pin Mux Controls, bit 1 */ } Bits; struct { byte grpB0 :2; byte grpB1 :2; byte grpB2 :2; byte grpB3 :2; } MergedBits; } PTBPF2STR; extern volatile PTBPF2STR _PTBPF2 @0xFFFF8203; #define PTBPF2 _PTBPF2.Byte #define PTBPF2_B00 _PTBPF2.Bits.B00 #define PTBPF2_B01 _PTBPF2.Bits.B01 #define PTBPF2_B10 _PTBPF2.Bits.B10 #define PTBPF2_B11 _PTBPF2.Bits.B11 #define PTBPF2_B20 _PTBPF2.Bits.B20 #define PTBPF2_B21 _PTBPF2.Bits.B21 #define PTBPF2_B30 _PTBPF2.Bits.B30 #define PTBPF2_B31 _PTBPF2.Bits.B31 #define PTBPF2_B0 _PTBPF2.MergedBits.grpB0 #define PTBPF2_B1 _PTBPF2.MergedBits.grpB1 #define PTBPF2_B2 _PTBPF2.MergedBits.grpB2 #define PTBPF2_B3 _PTBPF2.MergedBits.grpB3 #define PTBPF2_B00_MASK 1 #define PTBPF2_B01_MASK 2 #define PTBPF2_B10_MASK 4 #define PTBPF2_B11_MASK 8 #define PTBPF2_B20_MASK 16 #define PTBPF2_B21_MASK 32 #define PTBPF2_B30_MASK 64 #define PTBPF2_B31_MASK 128 #define PTBPF2_B0_MASK 3 #define PTBPF2_B0_BITNUM 0 #define PTBPF2_B1_MASK 12 #define PTBPF2_B1_BITNUM 2 #define PTBPF2_B2_MASK 48 #define PTBPF2_B2_BITNUM 4 #define PTBPF2_B3_MASK 192 #define PTBPF2_B3_BITNUM 6 /*** PTCPF1 - Port C Routing Register 1; 0xFFFF8204 ***/ typedef union { byte Byte; struct { byte C40 :1; /* Port PTC4 Pin Mux Controls, bit 0 */ byte C41 :1; /* Port PTC4 Pin Mux Controls, bit 1 */ byte C50 :1; /* Port PTC5 Pin Mux Controls, bit 0 */ byte C51 :1; /* Port PTC5 Pin Mux Controls, bit 1 */ byte C60 :1; /* Port PTC6 Pin Mux Controls, bit 0 */ byte C61 :1; /* Port PTC6 Pin Mux Controls, bit 1 */ byte C70 :1; /* Port PTC7 Pin Mux Controls, bit 0 */ byte C71 :1; /* Port PTC7 Pin Mux Controls, bit 1 */ } Bits; struct { byte grpC4 :2; byte grpC5 :2; byte grpC6 :2; byte grpC7 :2; } MergedBits; } PTCPF1STR; extern volatile PTCPF1STR _PTCPF1 @0xFFFF8204; #define PTCPF1 _PTCPF1.Byte #define PTCPF1_C40 _PTCPF1.Bits.C40 #define PTCPF1_C41 _PTCPF1.Bits.C41 #define PTCPF1_C50 _PTCPF1.Bits.C50 #define PTCPF1_C51 _PTCPF1.Bits.C51 #define PTCPF1_C60 _PTCPF1.Bits.C60 #define PTCPF1_C61 _PTCPF1.Bits.C61 #define PTCPF1_C70 _PTCPF1.Bits.C70 #define PTCPF1_C71 _PTCPF1.Bits.C71 #define PTCPF1_C4 _PTCPF1.MergedBits.grpC4 #define PTCPF1_C5 _PTCPF1.MergedBits.grpC5 #define PTCPF1_C6 _PTCPF1.MergedBits.grpC6 #define PTCPF1_C7 _PTCPF1.MergedBits.grpC7 #define PTCPF1_C40_MASK 1 #define PTCPF1_C41_MASK 2 #define PTCPF1_C50_MASK 4 #define PTCPF1_C51_MASK 8 #define PTCPF1_C60_MASK 16 #define PTCPF1_C61_MASK 32 #define PTCPF1_C70_MASK 64 #define PTCPF1_C71_MASK 128 #define PTCPF1_C4_MASK 3 #define PTCPF1_C4_BITNUM 0 #define PTCPF1_C5_MASK 12 #define PTCPF1_C5_BITNUM 2 #define PTCPF1_C6_MASK 48 #define PTCPF1_C6_BITNUM 4 #define PTCPF1_C7_MASK 192 #define PTCPF1_C7_BITNUM 6 /*** PTCPF2 - Port C Routing Register 2; 0xFFFF8205 ***/ typedef union { byte Byte; struct { byte C00 :1; /* Port PTC0 Pin Mux Controls, bit 0 */ byte C01 :1; /* Port PTC0 Pin Mux Controls, bit 1 */ byte C10 :1; /* Port PTC1 Pin Mux Controls, bit 0 */ byte C11 :1; /* Port PTC1 Pin Mux Controls, bit 1 */ byte C20 :1; /* Port PTC2 Pin Mux Controls, bit 0 */ byte C21 :1; /* Port PTC2 Pin Mux Controls, bit 1 */ byte C30 :1; /* Port PTC3 Pin Mux Controls, bit 0 */ byte C31 :1; /* Port PTC3 Pin Mux Controls, bit 1 */ } Bits; struct { byte grpC0 :2; byte grpC1 :2; byte grpC2 :2; byte grpC3 :2; } MergedBits; } PTCPF2STR; extern volatile PTCPF2STR _PTCPF2 @0xFFFF8205; #define PTCPF2 _PTCPF2.Byte #define PTCPF2_C00 _PTCPF2.Bits.C00 #define PTCPF2_C01 _PTCPF2.Bits.C01 #define PTCPF2_C10 _PTCPF2.Bits.C10 #define PTCPF2_C11 _PTCPF2.Bits.C11 #define PTCPF2_C20 _PTCPF2.Bits.C20 #define PTCPF2_C21 _PTCPF2.Bits.C21 #define PTCPF2_C30 _PTCPF2.Bits.C30 #define PTCPF2_C31 _PTCPF2.Bits.C31 #define PTCPF2_C0 _PTCPF2.MergedBits.grpC0 #define PTCPF2_C1 _PTCPF2.MergedBits.grpC1 #define PTCPF2_C2 _PTCPF2.MergedBits.grpC2 #define PTCPF2_C3 _PTCPF2.MergedBits.grpC3 #define PTCPF2_C00_MASK 1 #define PTCPF2_C01_MASK 2 #define PTCPF2_C10_MASK 4 #define PTCPF2_C11_MASK 8 #define PTCPF2_C20_MASK 16 #define PTCPF2_C21_MASK 32 #define PTCPF2_C30_MASK 64 #define PTCPF2_C31_MASK 128 #define PTCPF2_C0_MASK 3 #define PTCPF2_C0_BITNUM 0 #define PTCPF2_C1_MASK 12 #define PTCPF2_C1_BITNUM 2 #define PTCPF2_C2_MASK 48 #define PTCPF2_C2_BITNUM 4 #define PTCPF2_C3_MASK 192 #define PTCPF2_C3_BITNUM 6 /*** PTDPF1 - Port D Routing Register 1; 0xFFFF8206 ***/ typedef union { byte Byte; struct { byte D40 :1; /* Port PTD4 Pin Mux Controls, bit 0 */ byte D41 :1; /* Port PTD4 Pin Mux Controls, bit 1 */ byte D50 :1; /* Port PTD5 Pin Mux Controls, bit 0 */ byte D51 :1; /* Port PTD5 Pin Mux Controls, bit 1 */ byte D60 :1; /* Port PTD6 Pin Mux Controls, bit 0 */ byte D61 :1; /* Port PTD6 Pin Mux Controls, bit 1 */ byte D70 :1; /* Port PTD7 Pin Mux Controls, bit 0 */ byte D71 :1; /* Port PTD7 Pin Mux Controls, bit 1 */ } Bits; struct { byte grpD4 :2; byte grpD5 :2; byte grpD6 :2; byte grpD7 :2; } MergedBits; } PTDPF1STR; extern volatile PTDPF1STR _PTDPF1 @0xFFFF8206; #define PTDPF1 _PTDPF1.Byte #define PTDPF1_D40 _PTDPF1.Bits.D40 #define PTDPF1_D41 _PTDPF1.Bits.D41 #define PTDPF1_D50 _PTDPF1.Bits.D50 #define PTDPF1_D51 _PTDPF1.Bits.D51 #define PTDPF1_D60 _PTDPF1.Bits.D60 #define PTDPF1_D61 _PTDPF1.Bits.D61 #define PTDPF1_D70 _PTDPF1.Bits.D70 #define PTDPF1_D71 _PTDPF1.Bits.D71 #define PTDPF1_D4 _PTDPF1.MergedBits.grpD4 #define PTDPF1_D5 _PTDPF1.MergedBits.grpD5 #define PTDPF1_D6 _PTDPF1.MergedBits.grpD6 #define PTDPF1_D7 _PTDPF1.MergedBits.grpD7 #define PTDPF1_D40_MASK 1 #define PTDPF1_D41_MASK 2 #define PTDPF1_D50_MASK 4 #define PTDPF1_D51_MASK 8 #define PTDPF1_D60_MASK 16 #define PTDPF1_D61_MASK 32 #define PTDPF1_D70_MASK 64 #define PTDPF1_D71_MASK 128 #define PTDPF1_D4_MASK 3 #define PTDPF1_D4_BITNUM 0 #define PTDPF1_D5_MASK 12 #define PTDPF1_D5_BITNUM 2 #define PTDPF1_D6_MASK 48 #define PTDPF1_D6_BITNUM 4 #define PTDPF1_D7_MASK 192 #define PTDPF1_D7_BITNUM 6 /*** PTDPF2 - Port D Routing Register 2; 0xFFFF8207 ***/ typedef union { byte Byte; struct { byte D00 :1; /* Port PTD0 Pin Mux Controls, bit 0 */ byte D01 :1; /* Port PTD0 Pin Mux Controls, bit 1 */ byte D10 :1; /* Port PTD1 Pin Mux Controls, bit 0 */ byte D11 :1; /* Port PTD1 Pin Mux Controls, bit 1 */ byte D20 :1; /* Port PTD2 Pin Mux Controls, bit 0 */ byte D21 :1; /* Port PTD2 Pin Mux Controls, bit 1 */ byte D30 :1; /* Port PTD3 Pin Mux Controls, bit 0 */ byte D31 :1; /* Port PTD3 Pin Mux Controls, bit 1 */ } Bits; struct { byte grpD0 :2; byte grpD1 :2; byte grpD2 :2; byte grpD3 :2; } MergedBits; } PTDPF2STR; extern volatile PTDPF2STR _PTDPF2 @0xFFFF8207; #define PTDPF2 _PTDPF2.Byte #define PTDPF2_D00 _PTDPF2.Bits.D00 #define PTDPF2_D01 _PTDPF2.Bits.D01 #define PTDPF2_D10 _PTDPF2.Bits.D10 #define PTDPF2_D11 _PTDPF2.Bits.D11 #define PTDPF2_D20 _PTDPF2.Bits.D20 #define PTDPF2_D21 _PTDPF2.Bits.D21 #define PTDPF2_D30 _PTDPF2.Bits.D30 #define PTDPF2_D31 _PTDPF2.Bits.D31 #define PTDPF2_D0 _PTDPF2.MergedBits.grpD0 #define PTDPF2_D1 _PTDPF2.MergedBits.grpD1 #define PTDPF2_D2 _PTDPF2.MergedBits.grpD2 #define PTDPF2_D3 _PTDPF2.MergedBits.grpD3 #define PTDPF2_D00_MASK 1 #define PTDPF2_D01_MASK 2 #define PTDPF2_D10_MASK 4 #define PTDPF2_D11_MASK 8 #define PTDPF2_D20_MASK 16 #define PTDPF2_D21_MASK 32 #define PTDPF2_D30_MASK 64 #define PTDPF2_D31_MASK 128 #define PTDPF2_D0_MASK 3 #define PTDPF2_D0_BITNUM 0 #define PTDPF2_D1_MASK 12 #define PTDPF2_D1_BITNUM 2 #define PTDPF2_D2_MASK 48 #define PTDPF2_D2_BITNUM 4 #define PTDPF2_D3_MASK 192 #define PTDPF2_D3_BITNUM 6 /*** PTEPF1 - Port E Routing Register 1; 0xFFFF8208 ***/ typedef union { byte Byte; struct { byte E40 :1; /* Port PTE4 Pin Mux Controls, bit 0 */ byte E41 :1; /* Port PTE4 Pin Mux Controls, bit 1 */ byte E50 :1; /* Port PTE5 Pin Mux Controls, bit 0 */ byte E51 :1; /* Port PTE5 Pin Mux Controls, bit 1 */ byte E60 :1; /* Port PTE6 Pin Mux Controls, bit 0 */ byte E61 :1; /* Port PTE6 Pin Mux Controls, bit 1 */ byte E70 :1; /* Port PTE7 Pin Mux Controls, bit 0 */ byte E71 :1; /* Port PTE7 Pin Mux Controls, bit 1 */ } Bits; struct { byte grpE4 :2; byte grpE5 :2; byte grpE6 :2; byte grpE7 :2; } MergedBits; } PTEPF1STR; extern volatile PTEPF1STR _PTEPF1 @0xFFFF8208; #define PTEPF1 _PTEPF1.Byte #define PTEPF1_E40 _PTEPF1.Bits.E40 #define PTEPF1_E41 _PTEPF1.Bits.E41 #define PTEPF1_E50 _PTEPF1.Bits.E50 #define PTEPF1_E51 _PTEPF1.Bits.E51 #define PTEPF1_E60 _PTEPF1.Bits.E60 #define PTEPF1_E61 _PTEPF1.Bits.E61 #define PTEPF1_E70 _PTEPF1.Bits.E70 #define PTEPF1_E71 _PTEPF1.Bits.E71 #define PTEPF1_E4 _PTEPF1.MergedBits.grpE4 #define PTEPF1_E5 _PTEPF1.MergedBits.grpE5 #define PTEPF1_E6 _PTEPF1.MergedBits.grpE6 #define PTEPF1_E7 _PTEPF1.MergedBits.grpE7 #define PTEPF1_E40_MASK 1 #define PTEPF1_E41_MASK 2 #define PTEPF1_E50_MASK 4 #define PTEPF1_E51_MASK 8 #define PTEPF1_E60_MASK 16 #define PTEPF1_E61_MASK 32 #define PTEPF1_E70_MASK 64 #define PTEPF1_E71_MASK 128 #define PTEPF1_E4_MASK 3 #define PTEPF1_E4_BITNUM 0 #define PTEPF1_E5_MASK 12 #define PTEPF1_E5_BITNUM 2 #define PTEPF1_E6_MASK 48 #define PTEPF1_E6_BITNUM 4 #define PTEPF1_E7_MASK 192 #define PTEPF1_E7_BITNUM 6 /*** PTEPF2 - Port E Routing Register 2; 0xFFFF8209 ***/ typedef union { byte Byte; struct { byte E00 :1; /* Port PTE0 Pin Mux Controls, bit 0 */ byte E01 :1; /* Port PTE0 Pin Mux Controls, bit 1 */ byte E10 :1; /* Port PTE1 Pin Mux Controls, bit 0 */ byte E11 :1; /* Port PTE1 Pin Mux Controls, bit 1 */ byte E20 :1; /* Port PTE2 Pin Mux Controls, bit 0 */ byte E21 :1; /* Port PTE2 Pin Mux Controls, bit 1 */ byte E30 :1; /* Port PTE3 Pin Mux Controls, bit 0 */ byte E31 :1; /* Port PTE3 Pin Mux Controls, bit 1 */ } Bits; struct { byte grpE0 :2; byte grpE1 :2; byte grpE2 :2; byte grpE3 :2; } MergedBits; } PTEPF2STR; extern volatile PTEPF2STR _PTEPF2 @0xFFFF8209; #define PTEPF2 _PTEPF2.Byte #define PTEPF2_E00 _PTEPF2.Bits.E00 #define PTEPF2_E01 _PTEPF2.Bits.E01 #define PTEPF2_E10 _PTEPF2.Bits.E10 #define PTEPF2_E11 _PTEPF2.Bits.E11 #define PTEPF2_E20 _PTEPF2.Bits.E20 #define PTEPF2_E21 _PTEPF2.Bits.E21 #define PTEPF2_E30 _PTEPF2.Bits.E30 #define PTEPF2_E31 _PTEPF2.Bits.E31 #define PTEPF2_E0 _PTEPF2.MergedBits.grpE0 #define PTEPF2_E1 _PTEPF2.MergedBits.grpE1 #define PTEPF2_E2 _PTEPF2.MergedBits.grpE2 #define PTEPF2_E3 _PTEPF2.MergedBits.grpE3 #define PTEPF2_E00_MASK 1 #define PTEPF2_E01_MASK 2 #define PTEPF2_E10_MASK 4 #define PTEPF2_E11_MASK 8 #define PTEPF2_E20_MASK 16 #define PTEPF2_E21_MASK 32 #define PTEPF2_E30_MASK 64 #define PTEPF2_E31_MASK 128 #define PTEPF2_E0_MASK 3 #define PTEPF2_E0_BITNUM 0 #define PTEPF2_E1_MASK 12 #define PTEPF2_E1_BITNUM 2 #define PTEPF2_E2_MASK 48 #define PTEPF2_E2_BITNUM 4 #define PTEPF2_E3_MASK 192 #define PTEPF2_E3_BITNUM 6 /*** PTFPF1 - Port F Routing Register 1; 0xFFFF820A ***/ typedef union { byte Byte; struct { byte F40 :1; /* Port PTF4 Pin Mux Controls, bit 0 */ byte F41 :1; /* Port PTF4 Pin Mux Controls, bit 1 */ byte F50 :1; /* Port PTF5 Pin Mux Controls, bit 0 */ byte F51 :1; /* Port PTF5 Pin Mux Controls, bit 1 */ byte F60 :1; /* Port PTF6 Pin Mux Controls, bit 0 */ byte F61 :1; /* Port PTF6 Pin Mux Controls, bit 1 */ byte F70 :1; /* Port PTF7 Pin Mux Controls, bit 0 */ byte F71 :1; /* Port PTF7 Pin Mux Controls, bit 1 */ } Bits; struct { byte grpF4 :2; byte grpF5 :2; byte grpF6 :2; byte grpF7 :2; } MergedBits; } PTFPF1STR; extern volatile PTFPF1STR _PTFPF1 @0xFFFF820A; #define PTFPF1 _PTFPF1.Byte #define PTFPF1_F40 _PTFPF1.Bits.F40 #define PTFPF1_F41 _PTFPF1.Bits.F41 #define PTFPF1_F50 _PTFPF1.Bits.F50 #define PTFPF1_F51 _PTFPF1.Bits.F51 #define PTFPF1_F60 _PTFPF1.Bits.F60 #define PTFPF1_F61 _PTFPF1.Bits.F61 #define PTFPF1_F70 _PTFPF1.Bits.F70 #define PTFPF1_F71 _PTFPF1.Bits.F71 #define PTFPF1_F4 _PTFPF1.MergedBits.grpF4 #define PTFPF1_F5 _PTFPF1.MergedBits.grpF5 #define PTFPF1_F6 _PTFPF1.MergedBits.grpF6 #define PTFPF1_F7 _PTFPF1.MergedBits.grpF7 #define PTFPF1_F40_MASK 1 #define PTFPF1_F41_MASK 2 #define PTFPF1_F50_MASK 4 #define PTFPF1_F51_MASK 8 #define PTFPF1_F60_MASK 16 #define PTFPF1_F61_MASK 32 #define PTFPF1_F70_MASK 64 #define PTFPF1_F71_MASK 128 #define PTFPF1_F4_MASK 3 #define PTFPF1_F4_BITNUM 0 #define PTFPF1_F5_MASK 12 #define PTFPF1_F5_BITNUM 2 #define PTFPF1_F6_MASK 48 #define PTFPF1_F6_BITNUM 4 #define PTFPF1_F7_MASK 192 #define PTFPF1_F7_BITNUM 6 /*** PTFPF2 - Port F Routing Register 2; 0xFFFF820B ***/ typedef union { byte Byte; struct { byte F00 :1; /* Port PTF0 Pin Mux Controls, bit 0 */ byte F01 :1; /* Port PTF0 Pin Mux Controls, bit 1 */ byte F10 :1; /* Port PTF1 Pin Mux Controls, bit 0 */ byte F11 :1; /* Port PTF1 Pin Mux Controls, bit 1 */ byte F20 :1; /* Port PTF2 Pin Mux Controls, bit 0 */ byte F21 :1; /* Port PTF2 Pin Mux Controls, bit 1 */ byte F30 :1; /* Port PTF3 Pin Mux Controls, bit 0 */ byte F31 :1; /* Port PTF3 Pin Mux Controls, bit 1 */ } Bits; struct { byte grpF0 :2; byte grpF1 :2; byte grpF2 :2; byte grpF3 :2; } MergedBits; } PTFPF2STR; extern volatile PTFPF2STR _PTFPF2 @0xFFFF820B; #define PTFPF2 _PTFPF2.Byte #define PTFPF2_F00 _PTFPF2.Bits.F00 #define PTFPF2_F01 _PTFPF2.Bits.F01 #define PTFPF2_F10 _PTFPF2.Bits.F10 #define PTFPF2_F11 _PTFPF2.Bits.F11 #define PTFPF2_F20 _PTFPF2.Bits.F20 #define PTFPF2_F21 _PTFPF2.Bits.F21 #define PTFPF2_F30 _PTFPF2.Bits.F30 #define PTFPF2_F31 _PTFPF2.Bits.F31 #define PTFPF2_F0 _PTFPF2.MergedBits.grpF0 #define PTFPF2_F1 _PTFPF2.MergedBits.grpF1 #define PTFPF2_F2 _PTFPF2.MergedBits.grpF2 #define PTFPF2_F3 _PTFPF2.MergedBits.grpF3 #define PTFPF2_F00_MASK 1 #define PTFPF2_F01_MASK 2 #define PTFPF2_F10_MASK 4 #define PTFPF2_F11_MASK 8 #define PTFPF2_F20_MASK 16 #define PTFPF2_F21_MASK 32 #define PTFPF2_F30_MASK 64 #define PTFPF2_F31_MASK 128 #define PTFPF2_F0_MASK 3 #define PTFPF2_F0_BITNUM 0 #define PTFPF2_F1_MASK 12 #define PTFPF2_F1_BITNUM 2 #define PTFPF2_F2_MASK 48 #define PTFPF2_F2_BITNUM 4 #define PTFPF2_F3_MASK 192 #define PTFPF2_F3_BITNUM 6 /*** LCDPF1 - LCD Pin Mux Control Register 1; 0xFFFF820C ***/ typedef union { byte Byte; struct { byte LCD60 :1; /* LCD6 mux control bit 0 */ byte LCD61 :1; /* LCD6 mux control bit 1 */ byte LCD70 :1; /* LCD7 mux control bit 0 */ byte LCD71 :1; /* LCD7 mux control bit 1 */ byte LCD80 :1; /* LCD8 mux control bit 0 */ byte LCD81 :1; /* LCD8 mux control bit 1 */ byte LCD90 :1; /* LCD9 mux control bit 0 */ byte LCD91 :1; /* LCD9 mux control bit 1 */ } Bits; struct { byte grpLCD_60 :2; byte grpLCD_70 :2; byte grpLCD_80 :2; byte grpLCD_90 :2; } MergedBits; } LCDPF1STR; extern volatile LCDPF1STR _LCDPF1 @0xFFFF820C; #define LCDPF1 _LCDPF1.Byte #define LCDPF1_LCD60 _LCDPF1.Bits.LCD60 #define LCDPF1_LCD61 _LCDPF1.Bits.LCD61 #define LCDPF1_LCD70 _LCDPF1.Bits.LCD70 #define LCDPF1_LCD71 _LCDPF1.Bits.LCD71 #define LCDPF1_LCD80 _LCDPF1.Bits.LCD80 #define LCDPF1_LCD81 _LCDPF1.Bits.LCD81 #define LCDPF1_LCD90 _LCDPF1.Bits.LCD90 #define LCDPF1_LCD91 _LCDPF1.Bits.LCD91 #define LCDPF1_LCD_60 _LCDPF1.MergedBits.grpLCD_60 #define LCDPF1_LCD_70 _LCDPF1.MergedBits.grpLCD_70 #define LCDPF1_LCD_80 _LCDPF1.MergedBits.grpLCD_80 #define LCDPF1_LCD_90 _LCDPF1.MergedBits.grpLCD_90 #define LCDPF1_LCD LCDPF1_LCD_60 #define LCDPF1_LCD60_MASK 1 #define LCDPF1_LCD61_MASK 2 #define LCDPF1_LCD70_MASK 4 #define LCDPF1_LCD71_MASK 8 #define LCDPF1_LCD80_MASK 16 #define LCDPF1_LCD81_MASK 32 #define LCDPF1_LCD90_MASK 64 #define LCDPF1_LCD91_MASK 128 #define LCDPF1_LCD_60_MASK 3 #define LCDPF1_LCD_60_BITNUM 0 #define LCDPF1_LCD_70_MASK 12 #define LCDPF1_LCD_70_BITNUM 2 #define LCDPF1_LCD_80_MASK 48 #define LCDPF1_LCD_80_BITNUM 4 #define LCDPF1_LCD_90_MASK 192 #define LCDPF1_LCD_90_BITNUM 6 /*** LCDPF2 - LCD Pin Mux Control Register 1; 0xFFFF820D ***/ typedef union { byte Byte; struct { byte LCD350 :1; /* LCD35 mux control bit 0 */ byte LCD351 :1; /* LCD35 mux control bit 1 */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpLCD3_50 :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } LCDPF2STR; extern volatile LCDPF2STR _LCDPF2 @0xFFFF820D; #define LCDPF2 _LCDPF2.Byte #define LCDPF2_LCD350 _LCDPF2.Bits.LCD350 #define LCDPF2_LCD351 _LCDPF2.Bits.LCD351 #define LCDPF2_LCD3_50 _LCDPF2.MergedBits.grpLCD3_50 #define LCDPF2_LCD3 LCDPF2_LCD3_50 #define LCDPF2_LCD350_MASK 1 #define LCDPF2_LCD351_MASK 2 #define LCDPF2_LCD3_50_MASK 3 #define LCDPF2_LCD3_50_BITNUM 0 /*** ICSC1 - ICS Control Register 1; 0xFFFF8220 ***/ typedef union { byte Byte; struct { byte IREFSTEN :1; /* Internal Reference Stop Enable */ byte IRCLKEN :1; /* Internal Reference Clock Enable */ byte IREFS :1; /* Internal Reference Select */ byte RDIV0 :1; /* Reference Divider, bit 0 */ byte RDIV1 :1; /* Reference Divider, bit 1 */ byte RDIV2 :1; /* Reference Divider, bit 2 */ byte CLKS0 :1; /* Clock Source Select, bit 0 */ byte CLKS1 :1; /* Clock Source Select, bit 1 */ } Bits; struct { byte :1; byte :1; byte :1; byte grpRDIV :3; byte grpCLKS :2; } MergedBits; } ICSC1STR; extern volatile ICSC1STR _ICSC1 @0xFFFF8220; #define ICSC1 _ICSC1.Byte #define ICSC1_IREFSTEN _ICSC1.Bits.IREFSTEN #define ICSC1_IRCLKEN _ICSC1.Bits.IRCLKEN #define ICSC1_IREFS _ICSC1.Bits.IREFS #define ICSC1_RDIV0 _ICSC1.Bits.RDIV0 #define ICSC1_RDIV1 _ICSC1.Bits.RDIV1 #define ICSC1_RDIV2 _ICSC1.Bits.RDIV2 #define ICSC1_CLKS0 _ICSC1.Bits.CLKS0 #define ICSC1_CLKS1 _ICSC1.Bits.CLKS1 #define ICSC1_RDIV _ICSC1.MergedBits.grpRDIV #define ICSC1_CLKS _ICSC1.MergedBits.grpCLKS #define ICSC1_IREFSTEN_MASK 1 #define ICSC1_IRCLKEN_MASK 2 #define ICSC1_IREFS_MASK 4 #define ICSC1_RDIV0_MASK 8 #define ICSC1_RDIV1_MASK 16 #define ICSC1_RDIV2_MASK 32 #define ICSC1_CLKS0_MASK 64 #define ICSC1_CLKS1_MASK 128 #define ICSC1_RDIV_MASK 56 #define ICSC1_RDIV_BITNUM 3 #define ICSC1_CLKS_MASK 192 #define ICSC1_CLKS_BITNUM 6 /*** ICSC2 - ICS Control Register 2; 0xFFFF8221 ***/ typedef union { byte Byte; struct { byte EREFSTEN :1; /* External Reference Stop Enable */ byte ERCLKEN :1; /* External Reference Enable */ byte EREFS :1; /* External Reference Select */ byte LP :1; /* Low Power Select */ byte HGO :1; /* High Gain Oscillator Select */ byte RANGE :1; /* Frequency Range Select */ byte BDIV0 :1; /* Bus Frequency Divider, bit 0 */ byte BDIV1 :1; /* Bus Frequency Divider, bit 1 */ } Bits; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte grpBDIV :2; } MergedBits; } ICSC2STR; extern volatile ICSC2STR _ICSC2 @0xFFFF8221; #define ICSC2 _ICSC2.Byte #define ICSC2_EREFSTEN _ICSC2.Bits.EREFSTEN #define ICSC2_ERCLKEN _ICSC2.Bits.ERCLKEN #define ICSC2_EREFS _ICSC2.Bits.EREFS #define ICSC2_LP _ICSC2.Bits.LP #define ICSC2_HGO _ICSC2.Bits.HGO #define ICSC2_RANGE _ICSC2.Bits.RANGE #define ICSC2_BDIV0 _ICSC2.Bits.BDIV0 #define ICSC2_BDIV1 _ICSC2.Bits.BDIV1 #define ICSC2_BDIV _ICSC2.MergedBits.grpBDIV #define ICSC2_EREFSTEN_MASK 1 #define ICSC2_ERCLKEN_MASK 2 #define ICSC2_EREFS_MASK 4 #define ICSC2_LP_MASK 8 #define ICSC2_HGO_MASK 16 #define ICSC2_RANGE_MASK 32 #define ICSC2_BDIV0_MASK 64 #define ICSC2_BDIV1_MASK 128 #define ICSC2_BDIV_MASK 192 #define ICSC2_BDIV_BITNUM 6 /*** ICSTRM - ICS Trim Register; 0xFFFF8222 ***/ typedef union { byte Byte; struct { byte TRIM0 :1; /* ICS Trim Setting, bit 0 */ byte TRIM1 :1; /* ICS Trim Setting, bit 1 */ byte TRIM2 :1; /* ICS Trim Setting, bit 2 */ byte TRIM3 :1; /* ICS Trim Setting, bit 3 */ byte TRIM4 :1; /* ICS Trim Setting, bit 4 */ byte TRIM5 :1; /* ICS Trim Setting, bit 5 */ byte TRIM6 :1; /* ICS Trim Setting, bit 6 */ byte TRIM7 :1; /* ICS Trim Setting, bit 7 */ } Bits; } ICSTRMSTR; extern volatile ICSTRMSTR _ICSTRM @0xFFFF8222; #define ICSTRM _ICSTRM.Byte #define ICSTRM_TRIM0 _ICSTRM.Bits.TRIM0 #define ICSTRM_TRIM1 _ICSTRM.Bits.TRIM1 #define ICSTRM_TRIM2 _ICSTRM.Bits.TRIM2 #define ICSTRM_TRIM3 _ICSTRM.Bits.TRIM3 #define ICSTRM_TRIM4 _ICSTRM.Bits.TRIM4 #define ICSTRM_TRIM5 _ICSTRM.Bits.TRIM5 #define ICSTRM_TRIM6 _ICSTRM.Bits.TRIM6 #define ICSTRM_TRIM7 _ICSTRM.Bits.TRIM7 #define ICSTRM_TRIM0_MASK 1 #define ICSTRM_TRIM1_MASK 2 #define ICSTRM_TRIM2_MASK 4 #define ICSTRM_TRIM3_MASK 8 #define ICSTRM_TRIM4_MASK 16 #define ICSTRM_TRIM5_MASK 32 #define ICSTRM_TRIM6_MASK 64 #define ICSTRM_TRIM7_MASK 128 /*** ICSSC - ICS Status and Control Register; 0xFFFF8223 ***/ typedef union { byte Byte; struct { byte FTRIM :1; /* ICS Fine Trim */ byte OSCINIT :1; /* OSC Initialization */ byte CLKST0 :1; /* Clock Mode Status, bit 0 */ byte CLKST1 :1; /* Clock Mode Status, bit 1 */ byte IREFST :1; /* Internal Reference Status */ byte DMX32 :1; /* DCO Maximum frequency with 32.768 kHz reference */ byte DRST_DRS0 :1; /* DCO Range Status/Range Select, bit 0 */ byte DRST_DRS1 :1; /* DCO Range Status/Range Select, bit 1 */ } Bits; struct { byte :1; byte :1; byte grpCLKST :2; byte :1; byte grpDMX_32 :1; byte grpDRST_DRS :2; } MergedBits; } ICSSCSTR; extern volatile ICSSCSTR _ICSSC @0xFFFF8223; #define ICSSC _ICSSC.Byte #define ICSSC_FTRIM _ICSSC.Bits.FTRIM #define ICSSC_OSCINIT _ICSSC.Bits.OSCINIT #define ICSSC_CLKST0 _ICSSC.Bits.CLKST0 #define ICSSC_CLKST1 _ICSSC.Bits.CLKST1 #define ICSSC_IREFST _ICSSC.Bits.IREFST #define ICSSC_DMX32 _ICSSC.Bits.DMX32 #define ICSSC_DRST_DRS0 _ICSSC.Bits.DRST_DRS0 #define ICSSC_DRST_DRS1 _ICSSC.Bits.DRST_DRS1 #define ICSSC_CLKST _ICSSC.MergedBits.grpCLKST #define ICSSC_DRST_DRS _ICSSC.MergedBits.grpDRST_DRS #define ICSSC_FTRIM_MASK 1 #define ICSSC_OSCINIT_MASK 2 #define ICSSC_CLKST0_MASK 4 #define ICSSC_CLKST1_MASK 8 #define ICSSC_IREFST_MASK 16 #define ICSSC_DMX32_MASK 32 #define ICSSC_DRST_DRS0_MASK 64 #define ICSSC_DRST_DRS1_MASK 128 #define ICSSC_CLKST_MASK 12 #define ICSSC_CLKST_BITNUM 2 #define ICSSC_DRST_DRS_MASK 192 #define ICSSC_DRST_DRS_BITNUM 6 /*** CCSCTRL - Clock Check & Select Control; 0xFFFF8240 ***/ typedef union { byte Byte; struct { byte SEL :1; /* External Clock Select */ byte TEST :1; /* TEST */ byte EN :1; /* Enable clock for CCS */ byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } CCSCTRLSTR; extern volatile CCSCTRLSTR _CCSCTRL @0xFFFF8240; #define CCSCTRL _CCSCTRL.Byte #define CCSCTRL_SEL _CCSCTRL.Bits.SEL #define CCSCTRL_TEST _CCSCTRL.Bits.TEST #define CCSCTRL_EN _CCSCTRL.Bits.EN #define CCSCTRL_SEL_MASK 1 #define CCSCTRL_TEST_MASK 2 #define CCSCTRL_EN_MASK 4 /*** CCSTMR1 - CCS XOSC1 Timer Register; 0xFFFF8241 ***/ typedef union { byte Byte; struct { byte CNT10 :1; /* CNT1, bit 0 */ byte CNT11 :1; /* CNT1, bit 1 */ byte CNT12 :1; /* CNT1, bit 2 */ byte CNT13 :1; /* CNT1, bit 3 */ byte CNT14 :1; /* CNT1, bit 4 */ byte CNT15 :1; /* CNT1, bit 5 */ byte CNT16 :1; /* CNT1, bit 6 */ byte CNT17 :1; /* CNT1, bit 7 */ } Bits; } CCSTMR1STR; extern volatile CCSTMR1STR _CCSTMR1 @0xFFFF8241; #define CCSTMR1 _CCSTMR1.Byte #define CCSTMR1_CNT10 _CCSTMR1.Bits.CNT10 #define CCSTMR1_CNT11 _CCSTMR1.Bits.CNT11 #define CCSTMR1_CNT12 _CCSTMR1.Bits.CNT12 #define CCSTMR1_CNT13 _CCSTMR1.Bits.CNT13 #define CCSTMR1_CNT14 _CCSTMR1.Bits.CNT14 #define CCSTMR1_CNT15 _CCSTMR1.Bits.CNT15 #define CCSTMR1_CNT16 _CCSTMR1.Bits.CNT16 #define CCSTMR1_CNT17 _CCSTMR1.Bits.CNT17 #define CCSTMR1_CNT10_MASK 1 #define CCSTMR1_CNT11_MASK 2 #define CCSTMR1_CNT12_MASK 4 #define CCSTMR1_CNT13_MASK 8 #define CCSTMR1_CNT14_MASK 16 #define CCSTMR1_CNT15_MASK 32 #define CCSTMR1_CNT16_MASK 64 #define CCSTMR1_CNT17_MASK 128 /*** CCSTMR2 - CCS XOSC2 Timer Register; 0xFFFF8242 ***/ typedef union { byte Byte; struct { byte CNT20 :1; /* CNT2, bit 0 */ byte CNT21 :1; /* CNT2, bit 1 */ byte CNT22 :1; /* CNT2, bit 2 */ byte CNT23 :1; /* CNT2, bit 3 */ byte CNT24 :1; /* CNT2, bit 4 */ byte CNT25 :1; /* CNT2, bit 5 */ byte CNT26 :1; /* CNT2, bit 6 */ byte CNT27 :1; /* CNT2, bit 7 */ } Bits; } CCSTMR2STR; extern volatile CCSTMR2STR _CCSTMR2 @0xFFFF8242; #define CCSTMR2 _CCSTMR2.Byte #define CCSTMR2_CNT20 _CCSTMR2.Bits.CNT20 #define CCSTMR2_CNT21 _CCSTMR2.Bits.CNT21 #define CCSTMR2_CNT22 _CCSTMR2.Bits.CNT22 #define CCSTMR2_CNT23 _CCSTMR2.Bits.CNT23 #define CCSTMR2_CNT24 _CCSTMR2.Bits.CNT24 #define CCSTMR2_CNT25 _CCSTMR2.Bits.CNT25 #define CCSTMR2_CNT26 _CCSTMR2.Bits.CNT26 #define CCSTMR2_CNT27 _CCSTMR2.Bits.CNT27 #define CCSTMR2_CNT20_MASK 1 #define CCSTMR2_CNT21_MASK 2 #define CCSTMR2_CNT22_MASK 4 #define CCSTMR2_CNT23_MASK 8 #define CCSTMR2_CNT24_MASK 16 #define CCSTMR2_CNT25_MASK 32 #define CCSTMR2_CNT26_MASK 64 #define CCSTMR2_CNT27_MASK 128 /*** CCSTMRIR - CCS Internal Reference Clock Timer Register; 0xFFFF8243 ***/ typedef union { byte Byte; struct { byte CNTIR0 :1; /* CNTIR, bit 0 */ byte CNTIR1 :1; /* CNTIR, bit 1 */ byte CNTIR2 :1; /* CNTIR, bit 2 */ byte CNTIR3 :1; /* CNTIR, bit 3 */ byte CNTIR4 :1; /* CNTIR, bit 4 */ byte CNTIR5 :1; /* CNTIR, bit 5 */ byte CNTIR6 :1; /* CNTIR, bit 6 */ byte CNTIR7 :1; /* CNTIR, bit 7 */ } Bits; } CCSTMRIRSTR; extern volatile CCSTMRIRSTR _CCSTMRIR @0xFFFF8243; #define CCSTMRIR _CCSTMRIR.Byte #define CCSTMRIR_CNTIR0 _CCSTMRIR.Bits.CNTIR0 #define CCSTMRIR_CNTIR1 _CCSTMRIR.Bits.CNTIR1 #define CCSTMRIR_CNTIR2 _CCSTMRIR.Bits.CNTIR2 #define CCSTMRIR_CNTIR3 _CCSTMRIR.Bits.CNTIR3 #define CCSTMRIR_CNTIR4 _CCSTMRIR.Bits.CNTIR4 #define CCSTMRIR_CNTIR5 _CCSTMRIR.Bits.CNTIR5 #define CCSTMRIR_CNTIR6 _CCSTMRIR.Bits.CNTIR6 #define CCSTMRIR_CNTIR7 _CCSTMRIR.Bits.CNTIR7 #define CCSTMRIR_CNTIR0_MASK 1 #define CCSTMRIR_CNTIR1_MASK 2 #define CCSTMRIR_CNTIR2_MASK 4 #define CCSTMRIR_CNTIR3_MASK 8 #define CCSTMRIR_CNTIR4_MASK 16 #define CCSTMRIR_CNTIR5_MASK 32 #define CCSTMRIR_CNTIR6_MASK 64 #define CCSTMRIR_CNTIR7_MASK 128 /*** SRS - System Reset Status Register; 0xFFFF8280 ***/ typedef union { byte Byte; struct { byte :1; byte LVD :1; /* Low Voltage Detect */ byte :1; byte ILAD :1; /* Illegal Address */ byte ILOP :1; /* Illegal Opcode */ byte COP :1; /* Computer Operating Properly (COP) Watchdog */ byte PIN :1; /* External Reset Pin */ byte POR :1; /* Power-On Reset */ } Bits; } SRSSTR; extern volatile SRSSTR _SRS @0xFFFF8280; #define SRS _SRS.Byte #define SRS_LVD _SRS.Bits.LVD #define SRS_ILAD _SRS.Bits.ILAD #define SRS_ILOP _SRS.Bits.ILOP #define SRS_COP _SRS.Bits.COP #define SRS_PIN _SRS.Bits.PIN #define SRS_POR _SRS.Bits.POR #define SRS_LVD_MASK 2 #define SRS_ILAD_MASK 8 #define SRS_ILOP_MASK 16 #define SRS_COP_MASK 32 #define SRS_PIN_MASK 64 #define SRS_POR_MASK 128 /*** SOPT1 - System Options Register 1; 0xFFFF8281 ***/ typedef union { byte Byte; struct { byte COPW :1; /* COP Window Mode */ byte COPCLKS :1; /* COP Watchdog Clock Select */ byte COPT0 :1; /* COP Watchdog Timeout, bit 0 */ byte COPT1 :1; /* COP Watchdog Timeout, bit 1 */ byte WAITE :1; /* WAIT Mode Enable */ byte STOPE :1; /* Stop Mode Enable */ byte :1; byte :1; } Bits; struct { byte :1; byte :1; byte grpCOPT :2; byte :1; byte :1; byte :1; byte :1; } MergedBits; } SOPT1STR; extern volatile SOPT1STR _SOPT1 @0xFFFF8281; #define SOPT1 _SOPT1.Byte #define SOPT1_COPW _SOPT1.Bits.COPW #define SOPT1_COPCLKS _SOPT1.Bits.COPCLKS #define SOPT1_COPT0 _SOPT1.Bits.COPT0 #define SOPT1_COPT1 _SOPT1.Bits.COPT1 #define SOPT1_WAITE _SOPT1.Bits.WAITE #define SOPT1_STOPE _SOPT1.Bits.STOPE #define SOPT1_COPT _SOPT1.MergedBits.grpCOPT #define SOPT1_COPW_MASK 1 #define SOPT1_COPCLKS_MASK 2 #define SOPT1_COPT0_MASK 4 #define SOPT1_COPT1_MASK 8 #define SOPT1_WAITE_MASK 16 #define SOPT1_STOPE_MASK 32 #define SOPT1_COPT_MASK 12 #define SOPT1_COPT_BITNUM 2 /*** SOPT2 - System Options Register 2; 0xFFFF8282 ***/ typedef union { byte Byte; struct { byte PMC_LVD_TRIM0 :1; /* PMC LVD TRIM, bit 0 */ byte PMC_LVD_TRIM1 :1; /* PMC LVD TRIM, bit 1 */ byte PMC_LVD_TRIM2 :1; /* PMC LVD TRIM, bit 2 */ byte PMC_LVD_TRIM3 :1; /* PMC LVD TRIM, bit 3 */ byte PMC_LVD_TRIM4 :1; /* PMC LVD TRIM, bit 4 */ byte :1; byte :1; byte :1; } Bits; struct { byte grpPMC_LVD_TRIM :5; byte :1; byte :1; byte :1; } MergedBits; } SOPT2STR; extern volatile SOPT2STR _SOPT2 @0xFFFF8282; #define SOPT2 _SOPT2.Byte #define SOPT2_PMC_LVD_TRIM0 _SOPT2.Bits.PMC_LVD_TRIM0 #define SOPT2_PMC_LVD_TRIM1 _SOPT2.Bits.PMC_LVD_TRIM1 #define SOPT2_PMC_LVD_TRIM2 _SOPT2.Bits.PMC_LVD_TRIM2 #define SOPT2_PMC_LVD_TRIM3 _SOPT2.Bits.PMC_LVD_TRIM3 #define SOPT2_PMC_LVD_TRIM4 _SOPT2.Bits.PMC_LVD_TRIM4 #define SOPT2_PMC_LVD_TRIM _SOPT2.MergedBits.grpPMC_LVD_TRIM #define SOPT2_PMC_LVD_TRIM0_MASK 1 #define SOPT2_PMC_LVD_TRIM1_MASK 2 #define SOPT2_PMC_LVD_TRIM2_MASK 4 #define SOPT2_PMC_LVD_TRIM3_MASK 8 #define SOPT2_PMC_LVD_TRIM4_MASK 16 #define SOPT2_PMC_LVD_TRIM_MASK 31 #define SOPT2_PMC_LVD_TRIM_BITNUM 0 /*** SDID - System Device Identification Register; 0xFFFF8284 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** SDIDH - System Device Identification Register High; 0xFFFF8284 ***/ union { byte Byte; struct { byte ID8 :1; /* Part Identification Number, bit 8 */ byte ID9 :1; /* Part Identification Number, bit 9 */ byte ID10 :1; /* Part Identification Number, bit 10 */ byte ID11 :1; /* Part Identification Number, bit 11 */ byte REV0 :1; /* Revision Number, bit 0 */ byte REV1 :1; /* Revision Number, bit 1 */ byte REV2 :1; /* Revision Number, bit 2 */ byte REV3 :1; /* Revision Number, bit 3 */ } Bits; struct { byte grpID_8 :4; byte grpREV :4; } MergedBits; } SDIDHSTR; #define SDIDH _SDID.Overlap_STR.SDIDHSTR.Byte #define SDIDH_ID8 _SDID.Overlap_STR.SDIDHSTR.Bits.ID8 #define SDIDH_ID9 _SDID.Overlap_STR.SDIDHSTR.Bits.ID9 #define SDIDH_ID10 _SDID.Overlap_STR.SDIDHSTR.Bits.ID10 #define SDIDH_ID11 _SDID.Overlap_STR.SDIDHSTR.Bits.ID11 #define SDIDH_REV0 _SDID.Overlap_STR.SDIDHSTR.Bits.REV0 #define SDIDH_REV1 _SDID.Overlap_STR.SDIDHSTR.Bits.REV1 #define SDIDH_REV2 _SDID.Overlap_STR.SDIDHSTR.Bits.REV2 #define SDIDH_REV3 _SDID.Overlap_STR.SDIDHSTR.Bits.REV3 #define SDIDH_ID_8 _SDID.Overlap_STR.SDIDHSTR.MergedBits.grpID_8 #define SDIDH_REV _SDID.Overlap_STR.SDIDHSTR.MergedBits.grpREV #define SDIDH_ID SDIDH_ID_8 #define SDIDH_ID8_MASK 1 #define SDIDH_ID9_MASK 2 #define SDIDH_ID10_MASK 4 #define SDIDH_ID11_MASK 8 #define SDIDH_REV0_MASK 16 #define SDIDH_REV1_MASK 32 #define SDIDH_REV2_MASK 64 #define SDIDH_REV3_MASK 128 #define SDIDH_ID_8_MASK 15 #define SDIDH_ID_8_BITNUM 0 #define SDIDH_REV_MASK 240 #define SDIDH_REV_BITNUM 4 /*** SDIDL - System Device Identification Register Low; 0xFFFF8285 ***/ union { byte Byte; struct { byte ID0 :1; /* Part Identification Number, bit 0 */ byte ID1 :1; /* Part Identification Number, bit 1 */ byte ID2 :1; /* Part Identification Number, bit 2 */ byte ID3 :1; /* Part Identification Number, bit 3 */ byte ID4 :1; /* Part Identification Number, bit 4 */ byte ID5 :1; /* Part Identification Number, bit 5 */ byte ID6 :1; /* Part Identification Number, bit 6 */ byte ID7 :1; /* Part Identification Number, bit 7 */ } Bits; } SDIDLSTR; #define SDIDL _SDID.Overlap_STR.SDIDLSTR.Byte #define SDIDL_ID0 _SDID.Overlap_STR.SDIDLSTR.Bits.ID0 #define SDIDL_ID1 _SDID.Overlap_STR.SDIDLSTR.Bits.ID1 #define SDIDL_ID2 _SDID.Overlap_STR.SDIDLSTR.Bits.ID2 #define SDIDL_ID3 _SDID.Overlap_STR.SDIDLSTR.Bits.ID3 #define SDIDL_ID4 _SDID.Overlap_STR.SDIDLSTR.Bits.ID4 #define SDIDL_ID5 _SDID.Overlap_STR.SDIDLSTR.Bits.ID5 #define SDIDL_ID6 _SDID.Overlap_STR.SDIDLSTR.Bits.ID6 #define SDIDL_ID7 _SDID.Overlap_STR.SDIDLSTR.Bits.ID7 #define SDIDL_ID0_MASK 1 #define SDIDL_ID1_MASK 2 #define SDIDL_ID2_MASK 4 #define SDIDL_ID3_MASK 8 #define SDIDL_ID4_MASK 16 #define SDIDL_ID5_MASK 32 #define SDIDL_ID6_MASK 64 #define SDIDL_ID7_MASK 128 } Overlap_STR; struct { word ID0 :1; /* Part Identification Number, bit 0 */ word ID1 :1; /* Part Identification Number, bit 1 */ word ID2 :1; /* Part Identification Number, bit 2 */ word ID3 :1; /* Part Identification Number, bit 3 */ word ID4 :1; /* Part Identification Number, bit 4 */ word ID5 :1; /* Part Identification Number, bit 5 */ word ID6 :1; /* Part Identification Number, bit 6 */ word ID7 :1; /* Part Identification Number, bit 7 */ word ID8 :1; /* Part Identification Number, bit 8 */ word ID9 :1; /* Part Identification Number, bit 9 */ word ID10 :1; /* Part Identification Number, bit 10 */ word ID11 :1; /* Part Identification Number, bit 11 */ word REV0 :1; /* Revision Number */ word REV1 :1; /* Revision Number, bit 1 */ word REV2 :1; /* Revision Number, bit 2 */ word REV3 :1; /* Revision Number, bit 3 */ } Bits; struct { word grpID :12; word grpREV :4; } MergedBits; } SDIDSTR; extern volatile SDIDSTR _SDID @0xFFFF8284; #define SDID _SDID.Word #define SDID_ID0 _SDID.Bits.ID0 #define SDID_ID1 _SDID.Bits.ID1 #define SDID_ID2 _SDID.Bits.ID2 #define SDID_ID3 _SDID.Bits.ID3 #define SDID_ID4 _SDID.Bits.ID4 #define SDID_ID5 _SDID.Bits.ID5 #define SDID_ID6 _SDID.Bits.ID6 #define SDID_ID7 _SDID.Bits.ID7 #define SDID_ID8 _SDID.Bits.ID8 #define SDID_ID9 _SDID.Bits.ID9 #define SDID_ID10 _SDID.Bits.ID10 #define SDID_ID11 _SDID.Bits.ID11 #define SDID_REV0 _SDID.Bits.REV0 #define SDID_REV1 _SDID.Bits.REV1 #define SDID_REV2 _SDID.Bits.REV2 #define SDID_REV3 _SDID.Bits.REV3 #define SDID_ID _SDID.MergedBits.grpID #define SDID_REV _SDID.MergedBits.grpREV #define SDID_ID0_MASK 1 #define SDID_ID1_MASK 2 #define SDID_ID2_MASK 4 #define SDID_ID3_MASK 8 #define SDID_ID4_MASK 16 #define SDID_ID5_MASK 32 #define SDID_ID6_MASK 64 #define SDID_ID7_MASK 128 #define SDID_ID8_MASK 256 #define SDID_ID9_MASK 512 #define SDID_ID10_MASK 1024 #define SDID_ID11_MASK 2048 #define SDID_REV0_MASK 4096 #define SDID_REV1_MASK 8192 #define SDID_REV2_MASK 16384 #define SDID_REV3_MASK 32768 #define SDID_ID_MASK 4095 #define SDID_ID_BITNUM 0 #define SDID_REV_MASK 61440 #define SDID_REV_BITNUM 12 /*** SCGC1 - System Clock Gating Control 1 Register; 0xFFFF8286 ***/ typedef union { byte Byte; struct { byte SCI1 :1; /* SCI1 Clock Gate Control */ byte SCI2 :1; /* SCI2 Clock Gate Control */ byte SCI3 :1; /* SCI3 Clock Gate Control */ byte IIC :1; /* IIC Clock Gate Control */ byte ADC1 :1; /* ADC 1 Clock Gate Control */ byte ADC2 :1; /* ADC 2 Clock Gate Control */ byte ADC3 :1; /* ADC 3 Clock Gate Control */ byte ADC4 :1; /* ADC 4 Clock Gate Control */ } Bits; struct { byte grpSCI_1 :3; byte :1; byte grpADC_1 :4; } MergedBits; } SCGC1STR; extern volatile SCGC1STR _SCGC1 @0xFFFF8286; #define SCGC1 _SCGC1.Byte #define SCGC1_SCI1 _SCGC1.Bits.SCI1 #define SCGC1_SCI2 _SCGC1.Bits.SCI2 #define SCGC1_SCI3 _SCGC1.Bits.SCI3 #define SCGC1_IIC _SCGC1.Bits.IIC #define SCGC1_ADC1 _SCGC1.Bits.ADC1 #define SCGC1_ADC2 _SCGC1.Bits.ADC2 #define SCGC1_ADC3 _SCGC1.Bits.ADC3 #define SCGC1_ADC4 _SCGC1.Bits.ADC4 #define SCGC1_SCI_1 _SCGC1.MergedBits.grpSCI_1 #define SCGC1_ADC_1 _SCGC1.MergedBits.grpADC_1 #define SCGC1_SCI SCGC1_SCI_1 #define SCGC1_ADC SCGC1_ADC_1 #define SCGC1_SCI1_MASK 1 #define SCGC1_SCI2_MASK 2 #define SCGC1_SCI3_MASK 4 #define SCGC1_IIC_MASK 8 #define SCGC1_ADC1_MASK 16 #define SCGC1_ADC2_MASK 32 #define SCGC1_ADC3_MASK 64 #define SCGC1_ADC4_MASK 128 #define SCGC1_SCI_1_MASK 7 #define SCGC1_SCI_1_BITNUM 0 #define SCGC1_ADC_1_MASK 240 #define SCGC1_ADC_1_BITNUM 4 /*** SCGC2 - System Clock Gating Control 2 Register; 0xFFFF8287 ***/ typedef union { byte Byte; struct { byte SPI1 :1; /* SPI1 Clock Gate Control */ byte SPI2 :1; /* SPI2 Clock Gate Control */ byte SPI3 :1; /* SPI3 Clock Gate Control */ byte LCD :1; /* LCD Clock Gate Control */ byte IRQ :1; /* IRQ Clock Gate Control */ byte VREF :1; /* VREF Clock Gate Control */ byte CMP1 :1; /* CMP1 Clock Gate Control */ byte CMP2 :1; /* CMP2 Clock Gate Control */ } Bits; struct { byte grpSPI_1 :3; byte :1; byte :1; byte :1; byte grpCMP_1 :2; } MergedBits; } SCGC2STR; extern volatile SCGC2STR _SCGC2 @0xFFFF8287; #define SCGC2 _SCGC2.Byte #define SCGC2_SPI1 _SCGC2.Bits.SPI1 #define SCGC2_SPI2 _SCGC2.Bits.SPI2 #define SCGC2_SPI3 _SCGC2.Bits.SPI3 #define SCGC2_LCD _SCGC2.Bits.LCD #define SCGC2_IRQ _SCGC2.Bits.IRQ #define SCGC2_VREF _SCGC2.Bits.VREF #define SCGC2_CMP1 _SCGC2.Bits.CMP1 #define SCGC2_CMP2 _SCGC2.Bits.CMP2 #define SCGC2_SPI_1 _SCGC2.MergedBits.grpSPI_1 #define SCGC2_CMP_1 _SCGC2.MergedBits.grpCMP_1 #define SCGC2_SPI SCGC2_SPI_1 #define SCGC2_CMP SCGC2_CMP_1 #define SCGC2_SPI1_MASK 1 #define SCGC2_SPI2_MASK 2 #define SCGC2_SPI3_MASK 4 #define SCGC2_LCD_MASK 8 #define SCGC2_IRQ_MASK 16 #define SCGC2_VREF_MASK 32 #define SCGC2_CMP1_MASK 64 #define SCGC2_CMP2_MASK 128 #define SCGC2_SPI_1_MASK 7 #define SCGC2_SPI_1_BITNUM 0 #define SCGC2_CMP_1_MASK 192 #define SCGC2_CMP_1_BITNUM 6 /*** SCGC3 - System Clock Gating Control 3 Register; 0xFFFF8288 ***/ typedef union { byte Byte; struct { byte PTA :1; /* PTA Clock Gate Control */ byte PTB :1; /* PTB Clock Gate Control */ byte PTC :1; /* PTC Clock Gate Control */ byte PTD :1; /* PTD Clock Gate Control */ byte PTE :1; /* PTE Clock Gate Control */ byte PTF :1; /* PTF Clock Gate Control */ byte KBI1 :1; /* KBI1 Clock Gate Control */ byte KBI2 :1; /* KBI2 Clock Gate Control */ } Bits; struct { byte grpPTx :6; byte grpKBI_1 :2; } MergedBits; } SCGC3STR; extern volatile SCGC3STR _SCGC3 @0xFFFF8288; #define SCGC3 _SCGC3.Byte #define SCGC3_PTA _SCGC3.Bits.PTA #define SCGC3_PTB _SCGC3.Bits.PTB #define SCGC3_PTC _SCGC3.Bits.PTC #define SCGC3_PTD _SCGC3.Bits.PTD #define SCGC3_PTE _SCGC3.Bits.PTE #define SCGC3_PTF _SCGC3.Bits.PTF #define SCGC3_KBI1 _SCGC3.Bits.KBI1 #define SCGC3_KBI2 _SCGC3.Bits.KBI2 #define SCGC3_PTx _SCGC3.MergedBits.grpPTx #define SCGC3_KBI_1 _SCGC3.MergedBits.grpKBI_1 #define SCGC3_KBI SCGC3_KBI_1 #define SCGC3_PTA_MASK 1 #define SCGC3_PTB_MASK 2 #define SCGC3_PTC_MASK 4 #define SCGC3_PTD_MASK 8 #define SCGC3_PTE_MASK 16 #define SCGC3_PTF_MASK 32 #define SCGC3_KBI1_MASK 64 #define SCGC3_KBI2_MASK 128 #define SCGC3_PTx_MASK 63 #define SCGC3_PTx_BITNUM 0 #define SCGC3_KBI_1_MASK 192 #define SCGC3_KBI_1_BITNUM 6 /*** SCGC4 - System Clock Gating Control 4 Register; 0xFFFF8289 ***/ typedef union { byte Byte; struct { byte MTIM1 :1; /* MTIM1 Clock Gate Control */ byte MTIM2 :1; /* MTIM2 Clock Gate Control */ byte MTIM3 :1; /* MTIM3 Clock Gate Control */ byte PDB :1; /* PDB Clock Gate Control */ byte TPM :1; /* TPM Clock Gate Control */ byte CRC :1; /* CRC Clock Gate Control */ byte PM :1; /* Port Mux Control */ byte :1; } Bits; struct { byte grpMTIM_1 :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } SCGC4STR; extern volatile SCGC4STR _SCGC4 @0xFFFF8289; #define SCGC4 _SCGC4.Byte #define SCGC4_MTIM1 _SCGC4.Bits.MTIM1 #define SCGC4_MTIM2 _SCGC4.Bits.MTIM2 #define SCGC4_MTIM3 _SCGC4.Bits.MTIM3 #define SCGC4_PDB _SCGC4.Bits.PDB #define SCGC4_TPM _SCGC4.Bits.TPM #define SCGC4_CRC _SCGC4.Bits.CRC #define SCGC4_PM _SCGC4.Bits.PM #define SCGC4_MTIM_1 _SCGC4.MergedBits.grpMTIM_1 #define SCGC4_MTIM SCGC4_MTIM_1 #define SCGC4_MTIM1_MASK 1 #define SCGC4_MTIM2_MASK 2 #define SCGC4_MTIM3_MASK 4 #define SCGC4_PDB_MASK 8 #define SCGC4_TPM_MASK 16 #define SCGC4_CRC_MASK 32 #define SCGC4_PM_MASK 64 #define SCGC4_MTIM_1_MASK 7 #define SCGC4_MTIM_1_BITNUM 0 /*** SCGC5 - System Clock Gating Control 5 Register; 0xFFFF828A ***/ typedef union { byte Byte; struct { byte FTSR1 :1; /* FTSR1 Clock Gate Control */ byte FTSR2 :1; /* FTSR2 Clock Gate Control */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpFTSR_1 :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } SCGC5STR; extern volatile SCGC5STR _SCGC5 @0xFFFF828A; #define SCGC5 _SCGC5.Byte #define SCGC5_FTSR1 _SCGC5.Bits.FTSR1 #define SCGC5_FTSR2 _SCGC5.Bits.FTSR2 #define SCGC5_FTSR_1 _SCGC5.MergedBits.grpFTSR_1 #define SCGC5_FTSR SCGC5_FTSR_1 #define SCGC5_FTSR1_MASK 1 #define SCGC5_FTSR2_MASK 2 #define SCGC5_FTSR_1_MASK 3 #define SCGC5_FTSR_1_BITNUM 0 /*** SIMCO - SIM Clock Options Register; 0xFFFF828B ***/ typedef union { byte Byte; struct { byte CS0 :1; /* CLKOUT Select, bit 0 */ byte CS1 :1; /* CLKOUT Select, bit 1 */ byte CS2 :1; /* CLKOUT Select, bit 2 */ byte CS3 :1; /* CLKOUT Select, bit 3 */ byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpCS :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } SIMCOSTR; extern volatile SIMCOSTR _SIMCO @0xFFFF828B; #define SIMCO _SIMCO.Byte #define SIMCO_CS0 _SIMCO.Bits.CS0 #define SIMCO_CS1 _SIMCO.Bits.CS1 #define SIMCO_CS2 _SIMCO.Bits.CS2 #define SIMCO_CS3 _SIMCO.Bits.CS3 #define SIMCO_CS _SIMCO.MergedBits.grpCS #define SIMCO_CS0_MASK 1 #define SIMCO_CS1_MASK 2 #define SIMCO_CS2_MASK 4 #define SIMCO_CS3_MASK 8 #define SIMCO_CS_MASK 15 #define SIMCO_CS_BITNUM 0 /*** SIMIPS1 - Internal Peripheral Select Register 1; 0xFFFF828D ***/ typedef union { byte Byte; struct { byte MTIM1 :1; /* MTIM1 External Clock Pin Selec */ byte MTIM20 :1; /* MTIM2 External Clock Pin Select, bit 0 */ byte MTIM21 :1; /* MTIM2 External Clock Pin Select, bit 1 */ byte :1; byte MTIM30 :1; /* MTIM3 External Clock Pin Selec, bit 0 */ byte MTIM31 :1; /* MTIM3 External Clock Pin Selec, bit 1 */ byte :1; byte TPM :1; /* TPM External Clock Select Pin */ } Bits; struct { byte grpMTIM_1 :1; byte grpMTIM2 :2; byte :1; byte grpMTIM3 :2; byte :1; byte :1; } MergedBits; } SIMIPS1STR; extern volatile SIMIPS1STR _SIMIPS1 @0xFFFF828D; #define SIMIPS1 _SIMIPS1.Byte #define SIMIPS1_MTIM1 _SIMIPS1.Bits.MTIM1 #define SIMIPS1_MTIM20 _SIMIPS1.Bits.MTIM20 #define SIMIPS1_MTIM21 _SIMIPS1.Bits.MTIM21 #define SIMIPS1_MTIM30 _SIMIPS1.Bits.MTIM30 #define SIMIPS1_MTIM31 _SIMIPS1.Bits.MTIM31 #define SIMIPS1_TPM _SIMIPS1.Bits.TPM #define SIMIPS1_MTIM2 _SIMIPS1.MergedBits.grpMTIM2 #define SIMIPS1_MTIM3 _SIMIPS1.MergedBits.grpMTIM3 #define SIMIPS1_MTIM1_MASK 1 #define SIMIPS1_MTIM20_MASK 2 #define SIMIPS1_MTIM21_MASK 4 #define SIMIPS1_MTIM30_MASK 16 #define SIMIPS1_MTIM31_MASK 32 #define SIMIPS1_TPM_MASK 128 #define SIMIPS1_MTIM2_MASK 6 #define SIMIPS1_MTIM2_BITNUM 1 #define SIMIPS1_MTIM3_MASK 48 #define SIMIPS1_MTIM3_BITNUM 4 /*** SIMIPS2 - Internal Peripheral Select Register 1; 0xFFFF828E ***/ typedef union { byte Byte; struct { byte MODTX1 :1; /* Modulate TX1 */ byte MODTX2 :1; /* Modulate TX2 */ byte MTBASE10 :1; /* SCI1 TX Modulation Time Base Select, bit 0 */ byte MTBASE11 :1; /* SCI1 TX Modulation Time Base Select, bit 1 */ byte MTBASE20 :1; /* SCI2 TX Modulation Time Base Select, bit 0 */ byte MTBASE21 :1; /* SCI2 TX Modulation Time Base Select, bit 1 */ byte RX1IN :1; /* SCI1 RX Input Pin Select */ byte RX2IN :1; /* SCI2 RX Input Pin Select */ } Bits; struct { byte grpMODTX_1 :2; byte grpMTBASE1 :2; byte grpMTBASE2 :2; byte :1; byte :1; } MergedBits; } SIMIPS2STR; extern volatile SIMIPS2STR _SIMIPS2 @0xFFFF828E; #define SIMIPS2 _SIMIPS2.Byte #define SIMIPS2_MODTX1 _SIMIPS2.Bits.MODTX1 #define SIMIPS2_MODTX2 _SIMIPS2.Bits.MODTX2 #define SIMIPS2_MTBASE10 _SIMIPS2.Bits.MTBASE10 #define SIMIPS2_MTBASE11 _SIMIPS2.Bits.MTBASE11 #define SIMIPS2_MTBASE20 _SIMIPS2.Bits.MTBASE20 #define SIMIPS2_MTBASE21 _SIMIPS2.Bits.MTBASE21 #define SIMIPS2_RX1IN _SIMIPS2.Bits.RX1IN #define SIMIPS2_RX2IN _SIMIPS2.Bits.RX2IN #define SIMIPS2_MODTX_1 _SIMIPS2.MergedBits.grpMODTX_1 #define SIMIPS2_MTBASE1 _SIMIPS2.MergedBits.grpMTBASE1 #define SIMIPS2_MTBASE2 _SIMIPS2.MergedBits.grpMTBASE2 #define SIMIPS2_MODTX SIMIPS2_MODTX_1 #define SIMIPS2_MODTX1_MASK 1 #define SIMIPS2_MODTX2_MASK 2 #define SIMIPS2_MTBASE10_MASK 4 #define SIMIPS2_MTBASE11_MASK 8 #define SIMIPS2_MTBASE20_MASK 16 #define SIMIPS2_MTBASE21_MASK 32 #define SIMIPS2_RX1IN_MASK 64 #define SIMIPS2_RX2IN_MASK 128 #define SIMIPS2_MODTX_1_MASK 3 #define SIMIPS2_MODTX_1_BITNUM 0 #define SIMIPS2_MTBASE1_MASK 12 #define SIMIPS2_MTBASE1_BITNUM 2 #define SIMIPS2_MTBASE2_MASK 48 #define SIMIPS2_MTBASE2_BITNUM 4 /*** SPMSC1 - System Power Management Status and Control 1 Register; 0xFFFF82A0 ***/ typedef union { byte Byte; struct { byte BGBE :1; /* Bandgap Buffer Enable */ byte BGBDS :1; /* Bandgap Buffer Drive Select */ byte LVDE :1; /* Low-Voltage Detect Enable */ byte LVDSE :1; /* Low-Voltage Detect Stop Enable */ byte LVDRE :1; /* Low-Voltage Detect Reset Enable */ byte LVDIE :1; /* Low-Voltage Detect Interrupt Enable */ byte LVDACK :1; /* Low-Voltage Detect Acknowledge */ byte LVDF :1; /* Low-Voltage Detect Flag */ } Bits; } SPMSC1STR; extern volatile SPMSC1STR _SPMSC1 @0xFFFF82A0; #define SPMSC1 _SPMSC1.Byte #define SPMSC1_BGBE _SPMSC1.Bits.BGBE #define SPMSC1_BGBDS _SPMSC1.Bits.BGBDS #define SPMSC1_LVDE _SPMSC1.Bits.LVDE #define SPMSC1_LVDSE _SPMSC1.Bits.LVDSE #define SPMSC1_LVDRE _SPMSC1.Bits.LVDRE #define SPMSC1_LVDIE _SPMSC1.Bits.LVDIE #define SPMSC1_LVDACK _SPMSC1.Bits.LVDACK #define SPMSC1_LVDF _SPMSC1.Bits.LVDF #define SPMSC1_BGBE_MASK 1 #define SPMSC1_BGBDS_MASK 2 #define SPMSC1_LVDE_MASK 4 #define SPMSC1_LVDSE_MASK 8 #define SPMSC1_LVDRE_MASK 16 #define SPMSC1_LVDIE_MASK 32 #define SPMSC1_LVDACK_MASK 64 #define SPMSC1_LVDF_MASK 128 /*** SPMSC2 - System Power Management Status and Control 2 Register; 0xFFFF82A1 ***/ typedef union { byte Byte; struct { byte PPDC :1; /* Partial Power Down Control */ byte PPDE :1; /* Partial Power-Down Enable */ byte PPDACK :1; /* Partial Power Down Acknowledge */ byte PPDF :1; /* Partial Power Down Flag */ byte :1; byte LPWUI :1; /* Low Power Wake Up on Interrupt */ byte LPRS :1; /* Low Power Regulator Status */ byte LPR :1; /* Low Power Regulator Control */ } Bits; } SPMSC2STR; extern volatile SPMSC2STR _SPMSC2 @0xFFFF82A1; #define SPMSC2 _SPMSC2.Byte #define SPMSC2_PPDC _SPMSC2.Bits.PPDC #define SPMSC2_PPDE _SPMSC2.Bits.PPDE #define SPMSC2_PPDACK _SPMSC2.Bits.PPDACK #define SPMSC2_PPDF _SPMSC2.Bits.PPDF #define SPMSC2_LPWUI _SPMSC2.Bits.LPWUI #define SPMSC2_LPRS _SPMSC2.Bits.LPRS #define SPMSC2_LPR _SPMSC2.Bits.LPR #define SPMSC2_PPDC_MASK 1 #define SPMSC2_PPDE_MASK 2 #define SPMSC2_PPDACK_MASK 4 #define SPMSC2_PPDF_MASK 8 #define SPMSC2_LPWUI_MASK 32 #define SPMSC2_LPRS_MASK 64 #define SPMSC2_LPR_MASK 128 /*** SPMSC3 - System Power Management Status and Control 3 Register; 0xFFFF82A3 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte LVWIE :1; /* Low-Voltage Warning Interrupt Enable */ byte LVWV :1; /* Low-Voltage Warning Voltage Select */ byte LVDV :1; /* Low-Voltage Detect Voltage Select */ byte LVWACK :1; /* Low-Voltage Warning Acknowledge */ byte LVWF :1; /* Low-Voltage Warning Flag */ } Bits; } SPMSC3STR; extern volatile SPMSC3STR _SPMSC3 @0xFFFF82A3; #define SPMSC3 _SPMSC3.Byte #define SPMSC3_LVWIE _SPMSC3.Bits.LVWIE #define SPMSC3_LVWV _SPMSC3.Bits.LVWV #define SPMSC3_LVDV _SPMSC3.Bits.LVDV #define SPMSC3_LVWACK _SPMSC3.Bits.LVWACK #define SPMSC3_LVWF _SPMSC3.Bits.LVWF #define SPMSC3_LVWIE_MASK 8 #define SPMSC3_LVWV_MASK 16 #define SPMSC3_LVDV_MASK 32 #define SPMSC3_LVWACK_MASK 64 #define SPMSC3_LVWF_MASK 128 /*** SCI1BD - SCI1 Baud Rate Register; 0xFFFF82C0 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** SCI1BDH - SCI1 Baud Rate Register High; 0xFFFF82C0 ***/ union { byte Byte; struct { byte SBR8 :1; /* Baud Rate Modulo Divisor Bit 8 */ byte SBR9 :1; /* Baud Rate Modulo Divisor Bit 9 */ byte SBR10 :1; /* Baud Rate Modulo Divisor Bit 10 */ byte SBR11 :1; /* Baud Rate Modulo Divisor Bit 11 */ byte SBR12 :1; /* Baud Rate Modulo Divisor Bit 12 */ byte :1; byte RXEDGIE :1; /* RxD Input Active Edge Interrupt Enable (for RXEDGIF) */ byte LBKDIE :1; /* LIN Break Detect Interrupt Enable (for LBKDIF) */ } Bits; struct { byte grpSBR_8 :5; byte :1; byte :1; byte :1; } MergedBits; } SCI1BDHSTR; #define SCI1BDH _SCI1BD.Overlap_STR.SCI1BDHSTR.Byte #define SCI1BDH_SBR8 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR8 #define SCI1BDH_SBR9 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR9 #define SCI1BDH_SBR10 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR10 #define SCI1BDH_SBR11 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR11 #define SCI1BDH_SBR12 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR12 #define SCI1BDH_RXEDGIE _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.RXEDGIE #define SCI1BDH_LBKDIE _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.LBKDIE #define SCI1BDH_SBR_8 _SCI1BD.Overlap_STR.SCI1BDHSTR.MergedBits.grpSBR_8 #define SCI1BDH_SBR SCI1BDH_SBR_8 #define SCI1BDH_SBR8_MASK 1 #define SCI1BDH_SBR9_MASK 2 #define SCI1BDH_SBR10_MASK 4 #define SCI1BDH_SBR11_MASK 8 #define SCI1BDH_SBR12_MASK 16 #define SCI1BDH_RXEDGIE_MASK 64 #define SCI1BDH_LBKDIE_MASK 128 #define SCI1BDH_SBR_8_MASK 31 #define SCI1BDH_SBR_8_BITNUM 0 /*** SCI1BDL - SCI1 Baud Rate Register Low; 0xFFFF82C1 ***/ union { byte Byte; struct { byte SBR0 :1; /* Baud Rate Modulo Divisor Bit 0 */ byte SBR1 :1; /* Baud Rate Modulo Divisor Bit 1 */ byte SBR2 :1; /* Baud Rate Modulo Divisor Bit 2 */ byte SBR3 :1; /* Baud Rate Modulo Divisor Bit 3 */ byte SBR4 :1; /* Baud Rate Modulo Divisor Bit 4 */ byte SBR5 :1; /* Baud Rate Modulo Divisor Bit 5 */ byte SBR6 :1; /* Baud Rate Modulo Divisor Bit 6 */ byte SBR7 :1; /* Baud Rate Modulo Divisor Bit 7 */ } Bits; } SCI1BDLSTR; #define SCI1BDL _SCI1BD.Overlap_STR.SCI1BDLSTR.Byte #define SCI1BDL_SBR0 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR0 #define SCI1BDL_SBR1 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR1 #define SCI1BDL_SBR2 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR2 #define SCI1BDL_SBR3 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR3 #define SCI1BDL_SBR4 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR4 #define SCI1BDL_SBR5 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR5 #define SCI1BDL_SBR6 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR6 #define SCI1BDL_SBR7 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR7 #define SCI1BDL_SBR0_MASK 1 #define SCI1BDL_SBR1_MASK 2 #define SCI1BDL_SBR2_MASK 4 #define SCI1BDL_SBR3_MASK 8 #define SCI1BDL_SBR4_MASK 16 #define SCI1BDL_SBR5_MASK 32 #define SCI1BDL_SBR6_MASK 64 #define SCI1BDL_SBR7_MASK 128 } Overlap_STR; struct { word SBR0 :1; /* Baud Rate Modulo Divisor Bit 0 */ word SBR1 :1; /* Baud Rate Modulo Divisor Bit 1 */ word SBR2 :1; /* Baud Rate Modulo Divisor Bit 2 */ word SBR3 :1; /* Baud Rate Modulo Divisor Bit 3 */ word SBR4 :1; /* Baud Rate Modulo Divisor Bit 4 */ word SBR5 :1; /* Baud Rate Modulo Divisor Bit 5 */ word SBR6 :1; /* Baud Rate Modulo Divisor Bit 6 */ word SBR7 :1; /* Baud Rate Modulo Divisor Bit 7 */ word SBR8 :1; /* Baud Rate Modulo Divisor Bit 8 */ word SBR9 :1; /* Baud Rate Modulo Divisor Bit 9 */ word SBR10 :1; /* Baud Rate Modulo Divisor Bit 10 */ word SBR11 :1; /* Baud Rate Modulo Divisor Bit 11 */ word SBR12 :1; /* Baud Rate Modulo Divisor Bit 12 */ word :1; word RXEDGIE :1; /* RxD Input Active Edge Interrupt Enable (for RXEDGIF) */ word LBKDIE :1; /* LIN Break Detect Interrupt Enable (for LBKDIF) */ } Bits; struct { word grpSBR :13; word :1; word :1; word :1; } MergedBits; } SCI1BDSTR; extern volatile SCI1BDSTR _SCI1BD @0xFFFF82C0; #define SCI1BD _SCI1BD.Word #define SCI1BD_SBR0 _SCI1BD.Bits.SBR0 #define SCI1BD_SBR1 _SCI1BD.Bits.SBR1 #define SCI1BD_SBR2 _SCI1BD.Bits.SBR2 #define SCI1BD_SBR3 _SCI1BD.Bits.SBR3 #define SCI1BD_SBR4 _SCI1BD.Bits.SBR4 #define SCI1BD_SBR5 _SCI1BD.Bits.SBR5 #define SCI1BD_SBR6 _SCI1BD.Bits.SBR6 #define SCI1BD_SBR7 _SCI1BD.Bits.SBR7 #define SCI1BD_SBR8 _SCI1BD.Bits.SBR8 #define SCI1BD_SBR9 _SCI1BD.Bits.SBR9 #define SCI1BD_SBR10 _SCI1BD.Bits.SBR10 #define SCI1BD_SBR11 _SCI1BD.Bits.SBR11 #define SCI1BD_SBR12 _SCI1BD.Bits.SBR12 #define SCI1BD_RXEDGIE _SCI1BD.Bits.RXEDGIE #define SCI1BD_LBKDIE _SCI1BD.Bits.LBKDIE #define SCI1BD_SBR _SCI1BD.MergedBits.grpSBR #define SCI1BD_SBR0_MASK 1 #define SCI1BD_SBR1_MASK 2 #define SCI1BD_SBR2_MASK 4 #define SCI1BD_SBR3_MASK 8 #define SCI1BD_SBR4_MASK 16 #define SCI1BD_SBR5_MASK 32 #define SCI1BD_SBR6_MASK 64 #define SCI1BD_SBR7_MASK 128 #define SCI1BD_SBR8_MASK 256 #define SCI1BD_SBR9_MASK 512 #define SCI1BD_SBR10_MASK 1024 #define SCI1BD_SBR11_MASK 2048 #define SCI1BD_SBR12_MASK 4096 #define SCI1BD_RXEDGIE_MASK 16384 #define SCI1BD_LBKDIE_MASK 32768 #define SCI1BD_SBR_MASK 8191 #define SCI1BD_SBR_BITNUM 0 /*** SCI1C1 - SCI1 Control Register 1; 0xFFFF82C2 ***/ typedef union { byte Byte; struct { byte PT :1; /* Parity Type */ byte PE :1; /* Parity Enable */ byte ILT :1; /* Idle Line Type Select */ byte WAKE :1; /* Receiver Wakeup Method Select */ byte M :1; /* 9-Bit or 8-Bit Mode Select */ byte RSRC :1; /* Receiver Source Select */ byte SCISWAI :1; /* SCI Stops in Wait Mode */ byte LOOPS :1; /* Loop Mode Select */ } Bits; } SCI1C1STR; extern volatile SCI1C1STR _SCI1C1 @0xFFFF82C2; #define SCI1C1 _SCI1C1.Byte #define SCI1C1_PT _SCI1C1.Bits.PT #define SCI1C1_PE _SCI1C1.Bits.PE #define SCI1C1_ILT _SCI1C1.Bits.ILT #define SCI1C1_WAKE _SCI1C1.Bits.WAKE #define SCI1C1_M _SCI1C1.Bits.M #define SCI1C1_RSRC _SCI1C1.Bits.RSRC #define SCI1C1_SCISWAI _SCI1C1.Bits.SCISWAI #define SCI1C1_LOOPS _SCI1C1.Bits.LOOPS #define SCI1C1_PT_MASK 1 #define SCI1C1_PE_MASK 2 #define SCI1C1_ILT_MASK 4 #define SCI1C1_WAKE_MASK 8 #define SCI1C1_M_MASK 16 #define SCI1C1_RSRC_MASK 32 #define SCI1C1_SCISWAI_MASK 64 #define SCI1C1_LOOPS_MASK 128 /*** SCI1C2 - SCI1 Control Register 2; 0xFFFF82C3 ***/ typedef union { byte Byte; struct { byte SBK :1; /* Send Break */ byte RWU :1; /* Receiver Wakeup Control */ byte RE :1; /* Receiver Enable */ byte TE :1; /* Transmitter Enable */ byte ILIE :1; /* Idle Line Interrupt Enable (for IDLE) */ byte RIE :1; /* Receiver Interrupt Enable (for RDRF) */ byte TCIE :1; /* Transmission Complete Interrupt Enable (for TC) */ byte TIE :1; /* Transmit Interrupt Enable (for TDRE) */ } Bits; } SCI1C2STR; extern volatile SCI1C2STR _SCI1C2 @0xFFFF82C3; #define SCI1C2 _SCI1C2.Byte #define SCI1C2_SBK _SCI1C2.Bits.SBK #define SCI1C2_RWU _SCI1C2.Bits.RWU #define SCI1C2_RE _SCI1C2.Bits.RE #define SCI1C2_TE _SCI1C2.Bits.TE #define SCI1C2_ILIE _SCI1C2.Bits.ILIE #define SCI1C2_RIE _SCI1C2.Bits.RIE #define SCI1C2_TCIE _SCI1C2.Bits.TCIE #define SCI1C2_TIE _SCI1C2.Bits.TIE #define SCI1C2_SBK_MASK 1 #define SCI1C2_RWU_MASK 2 #define SCI1C2_RE_MASK 4 #define SCI1C2_TE_MASK 8 #define SCI1C2_ILIE_MASK 16 #define SCI1C2_RIE_MASK 32 #define SCI1C2_TCIE_MASK 64 #define SCI1C2_TIE_MASK 128 /*** SCI1S1 - SCI1 Status Register 1; 0xFFFF82C4 ***/ typedef union { byte Byte; struct { byte PF :1; /* Parity Error Flag */ byte FE :1; /* Framing Error Flag */ byte NF :1; /* Noise Flag */ byte OR :1; /* Receiver Overrun Flag */ byte IDLE :1; /* Idle Line Flag */ byte RDRF :1; /* Receive Data Register Full Flag */ byte TC :1; /* Transmission Complete Flag */ byte TDRE :1; /* Transmit Data Register Empty Flag */ } Bits; } SCI1S1STR; extern volatile SCI1S1STR _SCI1S1 @0xFFFF82C4; #define SCI1S1 _SCI1S1.Byte #define SCI1S1_PF _SCI1S1.Bits.PF #define SCI1S1_FE _SCI1S1.Bits.FE #define SCI1S1_NF _SCI1S1.Bits.NF #define SCI1S1_OR _SCI1S1.Bits.OR #define SCI1S1_IDLE _SCI1S1.Bits.IDLE #define SCI1S1_RDRF _SCI1S1.Bits.RDRF #define SCI1S1_TC _SCI1S1.Bits.TC #define SCI1S1_TDRE _SCI1S1.Bits.TDRE #define SCI1S1_PF_MASK 1 #define SCI1S1_FE_MASK 2 #define SCI1S1_NF_MASK 4 #define SCI1S1_OR_MASK 8 #define SCI1S1_IDLE_MASK 16 #define SCI1S1_RDRF_MASK 32 #define SCI1S1_TC_MASK 64 #define SCI1S1_TDRE_MASK 128 /*** SCI1S2 - SCI1 Status Register 2; 0xFFFF82C5 ***/ typedef union { byte Byte; struct { byte RAF :1; /* Receiver Active Flag */ byte LBKDE :1; /* LIN Break Detection Enable */ byte BRK13 :1; /* Break Character Generation Length */ byte RWUID :1; /* Receive Wake Up Idle Detect */ byte RXINV :1; /* Receive Data Inversion */ byte :1; byte RXEDGIF :1; /* RxD Pin Active Edge Interrupt Flag */ byte LBKDIF :1; /* LIN Break Detect Interrupt Flag */ } Bits; } SCI1S2STR; extern volatile SCI1S2STR _SCI1S2 @0xFFFF82C5; #define SCI1S2 _SCI1S2.Byte #define SCI1S2_RAF _SCI1S2.Bits.RAF #define SCI1S2_LBKDE _SCI1S2.Bits.LBKDE #define SCI1S2_BRK13 _SCI1S2.Bits.BRK13 #define SCI1S2_RWUID _SCI1S2.Bits.RWUID #define SCI1S2_RXINV _SCI1S2.Bits.RXINV #define SCI1S2_RXEDGIF _SCI1S2.Bits.RXEDGIF #define SCI1S2_LBKDIF _SCI1S2.Bits.LBKDIF #define SCI1S2_RAF_MASK 1 #define SCI1S2_LBKDE_MASK 2 #define SCI1S2_BRK13_MASK 4 #define SCI1S2_RWUID_MASK 8 #define SCI1S2_RXINV_MASK 16 #define SCI1S2_RXEDGIF_MASK 64 #define SCI1S2_LBKDIF_MASK 128 /*** SCI1C3 - SCI1 Control Register 3; 0xFFFF82C6 ***/ typedef union { byte Byte; struct { byte PEIE :1; /* Parity Error Interrupt Enable */ byte FEIE :1; /* Framing Error Interrupt Enable */ byte NEIE :1; /* Noise Error Interrupt Enable */ byte ORIE :1; /* Overrun Interrupt Enable */ byte TXINV :1; /* Transmit Data Inversion */ byte TXDIR :1; /* TxD Pin Direction in Single-Wire Mode */ byte T8 :1; /* Ninth Data Bit for Transmitter */ byte R8 :1; /* Ninth Data Bit for Receiver */ } Bits; } SCI1C3STR; extern volatile SCI1C3STR _SCI1C3 @0xFFFF82C6; #define SCI1C3 _SCI1C3.Byte #define SCI1C3_PEIE _SCI1C3.Bits.PEIE #define SCI1C3_FEIE _SCI1C3.Bits.FEIE #define SCI1C3_NEIE _SCI1C3.Bits.NEIE #define SCI1C3_ORIE _SCI1C3.Bits.ORIE #define SCI1C3_TXINV _SCI1C3.Bits.TXINV #define SCI1C3_TXDIR _SCI1C3.Bits.TXDIR #define SCI1C3_T8 _SCI1C3.Bits.T8 #define SCI1C3_R8 _SCI1C3.Bits.R8 #define SCI1C3_PEIE_MASK 1 #define SCI1C3_FEIE_MASK 2 #define SCI1C3_NEIE_MASK 4 #define SCI1C3_ORIE_MASK 8 #define SCI1C3_TXINV_MASK 16 #define SCI1C3_TXDIR_MASK 32 #define SCI1C3_T8_MASK 64 #define SCI1C3_R8_MASK 128 /*** SCI1D - SCI1 Data Register; 0xFFFF82C7 ***/ typedef union { byte Byte; struct { byte R0_T0 :1; /* Receive/Transmit Data Bit 0 */ byte R1_T1 :1; /* Receive/Transmit Data Bit 1 */ byte R2_T2 :1; /* Receive/Transmit Data Bit 2 */ byte R3_T3 :1; /* Receive/Transmit Data Bit 3 */ byte R4_T4 :1; /* Receive/Transmit Data Bit 4 */ byte R5_T5 :1; /* Receive/Transmit Data Bit 5 */ byte R6_T6 :1; /* Receive/Transmit Data Bit 6 */ byte R7_T7 :1; /* Receive/Transmit Data Bit 7 */ } Bits; } SCI1DSTR; extern volatile SCI1DSTR _SCI1D @0xFFFF82C7; #define SCI1D _SCI1D.Byte #define SCI1D_R0_T0 _SCI1D.Bits.R0_T0 #define SCI1D_R1_T1 _SCI1D.Bits.R1_T1 #define SCI1D_R2_T2 _SCI1D.Bits.R2_T2 #define SCI1D_R3_T3 _SCI1D.Bits.R3_T3 #define SCI1D_R4_T4 _SCI1D.Bits.R4_T4 #define SCI1D_R5_T5 _SCI1D.Bits.R5_T5 #define SCI1D_R6_T6 _SCI1D.Bits.R6_T6 #define SCI1D_R7_T7 _SCI1D.Bits.R7_T7 #define SCI1D_R0_T0_MASK 1 #define SCI1D_R1_T1_MASK 2 #define SCI1D_R2_T2_MASK 4 #define SCI1D_R3_T3_MASK 8 #define SCI1D_R4_T4_MASK 16 #define SCI1D_R5_T5_MASK 32 #define SCI1D_R6_T6_MASK 64 #define SCI1D_R7_T7_MASK 128 /*** SCI2BD - SCI2 Baud Rate Register; 0xFFFF82E0 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** SCI2BDH - SCI2 Baud Rate Register High; 0xFFFF82E0 ***/ union { byte Byte; struct { byte SBR8 :1; /* Baud Rate Modulo Divisor Bit 8 */ byte SBR9 :1; /* Baud Rate Modulo Divisor Bit 9 */ byte SBR10 :1; /* Baud Rate Modulo Divisor Bit 10 */ byte SBR11 :1; /* Baud Rate Modulo Divisor Bit 11 */ byte SBR12 :1; /* Baud Rate Modulo Divisor Bit 12 */ byte :1; byte RXEDGIE :1; /* RxD Input Active Edge Interrupt Enable (for RXEDGIF) */ byte LBKDIE :1; /* LIN Break Detect Interrupt Enable (for LBKDIF) */ } Bits; struct { byte grpSBR_8 :5; byte :1; byte :1; byte :1; } MergedBits; } SCI2BDHSTR; #define SCI2BDH _SCI2BD.Overlap_STR.SCI2BDHSTR.Byte #define SCI2BDH_SBR8 _SCI2BD.Overlap_STR.SCI2BDHSTR.Bits.SBR8 #define SCI2BDH_SBR9 _SCI2BD.Overlap_STR.SCI2BDHSTR.Bits.SBR9 #define SCI2BDH_SBR10 _SCI2BD.Overlap_STR.SCI2BDHSTR.Bits.SBR10 #define SCI2BDH_SBR11 _SCI2BD.Overlap_STR.SCI2BDHSTR.Bits.SBR11 #define SCI2BDH_SBR12 _SCI2BD.Overlap_STR.SCI2BDHSTR.Bits.SBR12 #define SCI2BDH_RXEDGIE _SCI2BD.Overlap_STR.SCI2BDHSTR.Bits.RXEDGIE #define SCI2BDH_LBKDIE _SCI2BD.Overlap_STR.SCI2BDHSTR.Bits.LBKDIE #define SCI2BDH_SBR_8 _SCI2BD.Overlap_STR.SCI2BDHSTR.MergedBits.grpSBR_8 #define SCI2BDH_SBR SCI2BDH_SBR_8 #define SCI2BDH_SBR8_MASK 1 #define SCI2BDH_SBR9_MASK 2 #define SCI2BDH_SBR10_MASK 4 #define SCI2BDH_SBR11_MASK 8 #define SCI2BDH_SBR12_MASK 16 #define SCI2BDH_RXEDGIE_MASK 64 #define SCI2BDH_LBKDIE_MASK 128 #define SCI2BDH_SBR_8_MASK 31 #define SCI2BDH_SBR_8_BITNUM 0 /*** SCI2BDL - SCI2 Baud Rate Register Low; 0xFFFF82E1 ***/ union { byte Byte; struct { byte SBR0 :1; /* Baud Rate Modulo Divisor Bit 0 */ byte SBR1 :1; /* Baud Rate Modulo Divisor Bit 1 */ byte SBR2 :1; /* Baud Rate Modulo Divisor Bit 2 */ byte SBR3 :1; /* Baud Rate Modulo Divisor Bit 3 */ byte SBR4 :1; /* Baud Rate Modulo Divisor Bit 4 */ byte SBR5 :1; /* Baud Rate Modulo Divisor Bit 5 */ byte SBR6 :1; /* Baud Rate Modulo Divisor Bit 6 */ byte SBR7 :1; /* Baud Rate Modulo Divisor Bit 7 */ } Bits; } SCI2BDLSTR; #define SCI2BDL _SCI2BD.Overlap_STR.SCI2BDLSTR.Byte #define SCI2BDL_SBR0 _SCI2BD.Overlap_STR.SCI2BDLSTR.Bits.SBR0 #define SCI2BDL_SBR1 _SCI2BD.Overlap_STR.SCI2BDLSTR.Bits.SBR1 #define SCI2BDL_SBR2 _SCI2BD.Overlap_STR.SCI2BDLSTR.Bits.SBR2 #define SCI2BDL_SBR3 _SCI2BD.Overlap_STR.SCI2BDLSTR.Bits.SBR3 #define SCI2BDL_SBR4 _SCI2BD.Overlap_STR.SCI2BDLSTR.Bits.SBR4 #define SCI2BDL_SBR5 _SCI2BD.Overlap_STR.SCI2BDLSTR.Bits.SBR5 #define SCI2BDL_SBR6 _SCI2BD.Overlap_STR.SCI2BDLSTR.Bits.SBR6 #define SCI2BDL_SBR7 _SCI2BD.Overlap_STR.SCI2BDLSTR.Bits.SBR7 #define SCI2BDL_SBR0_MASK 1 #define SCI2BDL_SBR1_MASK 2 #define SCI2BDL_SBR2_MASK 4 #define SCI2BDL_SBR3_MASK 8 #define SCI2BDL_SBR4_MASK 16 #define SCI2BDL_SBR5_MASK 32 #define SCI2BDL_SBR6_MASK 64 #define SCI2BDL_SBR7_MASK 128 } Overlap_STR; struct { word SBR0 :1; /* Baud Rate Modulo Divisor Bit 0 */ word SBR1 :1; /* Baud Rate Modulo Divisor Bit 1 */ word SBR2 :1; /* Baud Rate Modulo Divisor Bit 2 */ word SBR3 :1; /* Baud Rate Modulo Divisor Bit 3 */ word SBR4 :1; /* Baud Rate Modulo Divisor Bit 4 */ word SBR5 :1; /* Baud Rate Modulo Divisor Bit 5 */ word SBR6 :1; /* Baud Rate Modulo Divisor Bit 6 */ word SBR7 :1; /* Baud Rate Modulo Divisor Bit 7 */ word SBR8 :1; /* Baud Rate Modulo Divisor Bit 8 */ word SBR9 :1; /* Baud Rate Modulo Divisor Bit 9 */ word SBR10 :1; /* Baud Rate Modulo Divisor Bit 10 */ word SBR11 :1; /* Baud Rate Modulo Divisor Bit 11 */ word SBR12 :1; /* Baud Rate Modulo Divisor Bit 12 */ word :1; word RXEDGIE :1; /* RxD Input Active Edge Interrupt Enable (for RXEDGIF) */ word LBKDIE :1; /* LIN Break Detect Interrupt Enable (for LBKDIF) */ } Bits; struct { word grpSBR :13; word :1; word :1; word :1; } MergedBits; } SCI2BDSTR; extern volatile SCI2BDSTR _SCI2BD @0xFFFF82E0; #define SCI2BD _SCI2BD.Word #define SCI2BD_SBR0 _SCI2BD.Bits.SBR0 #define SCI2BD_SBR1 _SCI2BD.Bits.SBR1 #define SCI2BD_SBR2 _SCI2BD.Bits.SBR2 #define SCI2BD_SBR3 _SCI2BD.Bits.SBR3 #define SCI2BD_SBR4 _SCI2BD.Bits.SBR4 #define SCI2BD_SBR5 _SCI2BD.Bits.SBR5 #define SCI2BD_SBR6 _SCI2BD.Bits.SBR6 #define SCI2BD_SBR7 _SCI2BD.Bits.SBR7 #define SCI2BD_SBR8 _SCI2BD.Bits.SBR8 #define SCI2BD_SBR9 _SCI2BD.Bits.SBR9 #define SCI2BD_SBR10 _SCI2BD.Bits.SBR10 #define SCI2BD_SBR11 _SCI2BD.Bits.SBR11 #define SCI2BD_SBR12 _SCI2BD.Bits.SBR12 #define SCI2BD_RXEDGIE _SCI2BD.Bits.RXEDGIE #define SCI2BD_LBKDIE _SCI2BD.Bits.LBKDIE #define SCI2BD_SBR _SCI2BD.MergedBits.grpSBR #define SCI2BD_SBR0_MASK 1 #define SCI2BD_SBR1_MASK 2 #define SCI2BD_SBR2_MASK 4 #define SCI2BD_SBR3_MASK 8 #define SCI2BD_SBR4_MASK 16 #define SCI2BD_SBR5_MASK 32 #define SCI2BD_SBR6_MASK 64 #define SCI2BD_SBR7_MASK 128 #define SCI2BD_SBR8_MASK 256 #define SCI2BD_SBR9_MASK 512 #define SCI2BD_SBR10_MASK 1024 #define SCI2BD_SBR11_MASK 2048 #define SCI2BD_SBR12_MASK 4096 #define SCI2BD_RXEDGIE_MASK 16384 #define SCI2BD_LBKDIE_MASK 32768 #define SCI2BD_SBR_MASK 8191 #define SCI2BD_SBR_BITNUM 0 /*** SCI2C1 - SCI2 Control Register 1; 0xFFFF82E2 ***/ typedef union { byte Byte; struct { byte PT :1; /* Parity Type */ byte PE :1; /* Parity Enable */ byte ILT :1; /* Idle Line Type Select */ byte WAKE :1; /* Receiver Wakeup Method Select */ byte M :1; /* 9-Bit or 8-Bit Mode Select */ byte RSRC :1; /* Receiver Source Select */ byte SCISWAI :1; /* SCI Stops in Wait Mode */ byte LOOPS :1; /* Loop Mode Select */ } Bits; } SCI2C1STR; extern volatile SCI2C1STR _SCI2C1 @0xFFFF82E2; #define SCI2C1 _SCI2C1.Byte #define SCI2C1_PT _SCI2C1.Bits.PT #define SCI2C1_PE _SCI2C1.Bits.PE #define SCI2C1_ILT _SCI2C1.Bits.ILT #define SCI2C1_WAKE _SCI2C1.Bits.WAKE #define SCI2C1_M _SCI2C1.Bits.M #define SCI2C1_RSRC _SCI2C1.Bits.RSRC #define SCI2C1_SCISWAI _SCI2C1.Bits.SCISWAI #define SCI2C1_LOOPS _SCI2C1.Bits.LOOPS #define SCI2C1_PT_MASK 1 #define SCI2C1_PE_MASK 2 #define SCI2C1_ILT_MASK 4 #define SCI2C1_WAKE_MASK 8 #define SCI2C1_M_MASK 16 #define SCI2C1_RSRC_MASK 32 #define SCI2C1_SCISWAI_MASK 64 #define SCI2C1_LOOPS_MASK 128 /*** SCI2C2 - SCI2 Control Register 2; 0xFFFF82E3 ***/ typedef union { byte Byte; struct { byte SBK :1; /* Send Break */ byte RWU :1; /* Receiver Wakeup Control */ byte RE :1; /* Receiver Enable */ byte TE :1; /* Transmitter Enable */ byte ILIE :1; /* Idle Line Interrupt Enable (for IDLE) */ byte RIE :1; /* Receiver Interrupt Enable (for RDRF) */ byte TCIE :1; /* Transmission Complete Interrupt Enable (for TC) */ byte TIE :1; /* Transmit Interrupt Enable (for TDRE) */ } Bits; } SCI2C2STR; extern volatile SCI2C2STR _SCI2C2 @0xFFFF82E3; #define SCI2C2 _SCI2C2.Byte #define SCI2C2_SBK _SCI2C2.Bits.SBK #define SCI2C2_RWU _SCI2C2.Bits.RWU #define SCI2C2_RE _SCI2C2.Bits.RE #define SCI2C2_TE _SCI2C2.Bits.TE #define SCI2C2_ILIE _SCI2C2.Bits.ILIE #define SCI2C2_RIE _SCI2C2.Bits.RIE #define SCI2C2_TCIE _SCI2C2.Bits.TCIE #define SCI2C2_TIE _SCI2C2.Bits.TIE #define SCI2C2_SBK_MASK 1 #define SCI2C2_RWU_MASK 2 #define SCI2C2_RE_MASK 4 #define SCI2C2_TE_MASK 8 #define SCI2C2_ILIE_MASK 16 #define SCI2C2_RIE_MASK 32 #define SCI2C2_TCIE_MASK 64 #define SCI2C2_TIE_MASK 128 /*** SCI2S1 - SCI2 Status Register 1; 0xFFFF82E4 ***/ typedef union { byte Byte; struct { byte PF :1; /* Parity Error Flag */ byte FE :1; /* Framing Error Flag */ byte NF :1; /* Noise Flag */ byte OR :1; /* Receiver Overrun Flag */ byte IDLE :1; /* Idle Line Flag */ byte RDRF :1; /* Receive Data Register Full Flag */ byte TC :1; /* Transmission Complete Flag */ byte TDRE :1; /* Transmit Data Register Empty Flag */ } Bits; } SCI2S1STR; extern volatile SCI2S1STR _SCI2S1 @0xFFFF82E4; #define SCI2S1 _SCI2S1.Byte #define SCI2S1_PF _SCI2S1.Bits.PF #define SCI2S1_FE _SCI2S1.Bits.FE #define SCI2S1_NF _SCI2S1.Bits.NF #define SCI2S1_OR _SCI2S1.Bits.OR #define SCI2S1_IDLE _SCI2S1.Bits.IDLE #define SCI2S1_RDRF _SCI2S1.Bits.RDRF #define SCI2S1_TC _SCI2S1.Bits.TC #define SCI2S1_TDRE _SCI2S1.Bits.TDRE #define SCI2S1_PF_MASK 1 #define SCI2S1_FE_MASK 2 #define SCI2S1_NF_MASK 4 #define SCI2S1_OR_MASK 8 #define SCI2S1_IDLE_MASK 16 #define SCI2S1_RDRF_MASK 32 #define SCI2S1_TC_MASK 64 #define SCI2S1_TDRE_MASK 128 /*** SCI2S2 - SCI2 Status Register 2; 0xFFFF82E5 ***/ typedef union { byte Byte; struct { byte RAF :1; /* Receiver Active Flag */ byte LBKDE :1; /* LIN Break Detection Enable */ byte BRK13 :1; /* Break Character Generation Length */ byte RWUID :1; /* Receive Wake Up Idle Detect */ byte RXINV :1; /* Receive Data Inversion */ byte :1; byte RXEDGIF :1; /* RxD Pin Active Edge Interrupt Flag */ byte LBKDIF :1; /* LIN Break Detect Interrupt Flag */ } Bits; } SCI2S2STR; extern volatile SCI2S2STR _SCI2S2 @0xFFFF82E5; #define SCI2S2 _SCI2S2.Byte #define SCI2S2_RAF _SCI2S2.Bits.RAF #define SCI2S2_LBKDE _SCI2S2.Bits.LBKDE #define SCI2S2_BRK13 _SCI2S2.Bits.BRK13 #define SCI2S2_RWUID _SCI2S2.Bits.RWUID #define SCI2S2_RXINV _SCI2S2.Bits.RXINV #define SCI2S2_RXEDGIF _SCI2S2.Bits.RXEDGIF #define SCI2S2_LBKDIF _SCI2S2.Bits.LBKDIF #define SCI2S2_RAF_MASK 1 #define SCI2S2_LBKDE_MASK 2 #define SCI2S2_BRK13_MASK 4 #define SCI2S2_RWUID_MASK 8 #define SCI2S2_RXINV_MASK 16 #define SCI2S2_RXEDGIF_MASK 64 #define SCI2S2_LBKDIF_MASK 128 /*** SCI2C3 - SCI2 Control Register 3; 0xFFFF82E6 ***/ typedef union { byte Byte; struct { byte PEIE :1; /* Parity Error Interrupt Enable */ byte FEIE :1; /* Framing Error Interrupt Enable */ byte NEIE :1; /* Noise Error Interrupt Enable */ byte ORIE :1; /* Overrun Interrupt Enable */ byte TXINV :1; /* Transmit Data Inversion */ byte TXDIR :1; /* TxD Pin Direction in Single-Wire Mode */ byte T8 :1; /* Ninth Data Bit for Transmitter */ byte R8 :1; /* Ninth Data Bit for Receiver */ } Bits; } SCI2C3STR; extern volatile SCI2C3STR _SCI2C3 @0xFFFF82E6; #define SCI2C3 _SCI2C3.Byte #define SCI2C3_PEIE _SCI2C3.Bits.PEIE #define SCI2C3_FEIE _SCI2C3.Bits.FEIE #define SCI2C3_NEIE _SCI2C3.Bits.NEIE #define SCI2C3_ORIE _SCI2C3.Bits.ORIE #define SCI2C3_TXINV _SCI2C3.Bits.TXINV #define SCI2C3_TXDIR _SCI2C3.Bits.TXDIR #define SCI2C3_T8 _SCI2C3.Bits.T8 #define SCI2C3_R8 _SCI2C3.Bits.R8 #define SCI2C3_PEIE_MASK 1 #define SCI2C3_FEIE_MASK 2 #define SCI2C3_NEIE_MASK 4 #define SCI2C3_ORIE_MASK 8 #define SCI2C3_TXINV_MASK 16 #define SCI2C3_TXDIR_MASK 32 #define SCI2C3_T8_MASK 64 #define SCI2C3_R8_MASK 128 /*** SCI2D - SCI2 Data Register; 0xFFFF82E7 ***/ typedef union { byte Byte; struct { byte R0_T0 :1; /* Receive/Transmit Data Bit 0 */ byte R1_T1 :1; /* Receive/Transmit Data Bit 1 */ byte R2_T2 :1; /* Receive/Transmit Data Bit 2 */ byte R3_T3 :1; /* Receive/Transmit Data Bit 3 */ byte R4_T4 :1; /* Receive/Transmit Data Bit 4 */ byte R5_T5 :1; /* Receive/Transmit Data Bit 5 */ byte R6_T6 :1; /* Receive/Transmit Data Bit 6 */ byte R7_T7 :1; /* Receive/Transmit Data Bit 7 */ } Bits; } SCI2DSTR; extern volatile SCI2DSTR _SCI2D @0xFFFF82E7; #define SCI2D _SCI2D.Byte #define SCI2D_R0_T0 _SCI2D.Bits.R0_T0 #define SCI2D_R1_T1 _SCI2D.Bits.R1_T1 #define SCI2D_R2_T2 _SCI2D.Bits.R2_T2 #define SCI2D_R3_T3 _SCI2D.Bits.R3_T3 #define SCI2D_R4_T4 _SCI2D.Bits.R4_T4 #define SCI2D_R5_T5 _SCI2D.Bits.R5_T5 #define SCI2D_R6_T6 _SCI2D.Bits.R6_T6 #define SCI2D_R7_T7 _SCI2D.Bits.R7_T7 #define SCI2D_R0_T0_MASK 1 #define SCI2D_R1_T1_MASK 2 #define SCI2D_R2_T2_MASK 4 #define SCI2D_R3_T3_MASK 8 #define SCI2D_R4_T4_MASK 16 #define SCI2D_R5_T5_MASK 32 #define SCI2D_R6_T6_MASK 64 #define SCI2D_R7_T7_MASK 128 /*** SCI3BD - SCI3 Baud Rate Register; 0xFFFF8300 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** SCI3BDH - SCI3 Baud Rate Register High; 0xFFFF8300 ***/ union { byte Byte; struct { byte SBR8 :1; /* Baud Rate Modulo Divisor Bit 8 */ byte SBR9 :1; /* Baud Rate Modulo Divisor Bit 9 */ byte SBR10 :1; /* Baud Rate Modulo Divisor Bit 10 */ byte SBR11 :1; /* Baud Rate Modulo Divisor Bit 11 */ byte SBR12 :1; /* Baud Rate Modulo Divisor Bit 12 */ byte :1; byte RXEDGIE :1; /* RxD Input Active Edge Interrupt Enable (for RXEDGIF) */ byte LBKDIE :1; /* LIN Break Detect Interrupt Enable (for LBKDIF) */ } Bits; struct { byte grpSBR_8 :5; byte :1; byte :1; byte :1; } MergedBits; } SCI3BDHSTR; #define SCI3BDH _SCI3BD.Overlap_STR.SCI3BDHSTR.Byte #define SCI3BDH_SBR8 _SCI3BD.Overlap_STR.SCI3BDHSTR.Bits.SBR8 #define SCI3BDH_SBR9 _SCI3BD.Overlap_STR.SCI3BDHSTR.Bits.SBR9 #define SCI3BDH_SBR10 _SCI3BD.Overlap_STR.SCI3BDHSTR.Bits.SBR10 #define SCI3BDH_SBR11 _SCI3BD.Overlap_STR.SCI3BDHSTR.Bits.SBR11 #define SCI3BDH_SBR12 _SCI3BD.Overlap_STR.SCI3BDHSTR.Bits.SBR12 #define SCI3BDH_RXEDGIE _SCI3BD.Overlap_STR.SCI3BDHSTR.Bits.RXEDGIE #define SCI3BDH_LBKDIE _SCI3BD.Overlap_STR.SCI3BDHSTR.Bits.LBKDIE #define SCI3BDH_SBR_8 _SCI3BD.Overlap_STR.SCI3BDHSTR.MergedBits.grpSBR_8 #define SCI3BDH_SBR SCI3BDH_SBR_8 #define SCI3BDH_SBR8_MASK 1 #define SCI3BDH_SBR9_MASK 2 #define SCI3BDH_SBR10_MASK 4 #define SCI3BDH_SBR11_MASK 8 #define SCI3BDH_SBR12_MASK 16 #define SCI3BDH_RXEDGIE_MASK 64 #define SCI3BDH_LBKDIE_MASK 128 #define SCI3BDH_SBR_8_MASK 31 #define SCI3BDH_SBR_8_BITNUM 0 /*** SCI3BDL - SCI3 Baud Rate Register Low; 0xFFFF8301 ***/ union { byte Byte; struct { byte SBR0 :1; /* Baud Rate Modulo Divisor Bit 0 */ byte SBR1 :1; /* Baud Rate Modulo Divisor Bit 1 */ byte SBR2 :1; /* Baud Rate Modulo Divisor Bit 2 */ byte SBR3 :1; /* Baud Rate Modulo Divisor Bit 3 */ byte SBR4 :1; /* Baud Rate Modulo Divisor Bit 4 */ byte SBR5 :1; /* Baud Rate Modulo Divisor Bit 5 */ byte SBR6 :1; /* Baud Rate Modulo Divisor Bit 6 */ byte SBR7 :1; /* Baud Rate Modulo Divisor Bit 7 */ } Bits; } SCI3BDLSTR; #define SCI3BDL _SCI3BD.Overlap_STR.SCI3BDLSTR.Byte #define SCI3BDL_SBR0 _SCI3BD.Overlap_STR.SCI3BDLSTR.Bits.SBR0 #define SCI3BDL_SBR1 _SCI3BD.Overlap_STR.SCI3BDLSTR.Bits.SBR1 #define SCI3BDL_SBR2 _SCI3BD.Overlap_STR.SCI3BDLSTR.Bits.SBR2 #define SCI3BDL_SBR3 _SCI3BD.Overlap_STR.SCI3BDLSTR.Bits.SBR3 #define SCI3BDL_SBR4 _SCI3BD.Overlap_STR.SCI3BDLSTR.Bits.SBR4 #define SCI3BDL_SBR5 _SCI3BD.Overlap_STR.SCI3BDLSTR.Bits.SBR5 #define SCI3BDL_SBR6 _SCI3BD.Overlap_STR.SCI3BDLSTR.Bits.SBR6 #define SCI3BDL_SBR7 _SCI3BD.Overlap_STR.SCI3BDLSTR.Bits.SBR7 #define SCI3BDL_SBR0_MASK 1 #define SCI3BDL_SBR1_MASK 2 #define SCI3BDL_SBR2_MASK 4 #define SCI3BDL_SBR3_MASK 8 #define SCI3BDL_SBR4_MASK 16 #define SCI3BDL_SBR5_MASK 32 #define SCI3BDL_SBR6_MASK 64 #define SCI3BDL_SBR7_MASK 128 } Overlap_STR; struct { word SBR0 :1; /* Baud Rate Modulo Divisor Bit 0 */ word SBR1 :1; /* Baud Rate Modulo Divisor Bit 1 */ word SBR2 :1; /* Baud Rate Modulo Divisor Bit 2 */ word SBR3 :1; /* Baud Rate Modulo Divisor Bit 3 */ word SBR4 :1; /* Baud Rate Modulo Divisor Bit 4 */ word SBR5 :1; /* Baud Rate Modulo Divisor Bit 5 */ word SBR6 :1; /* Baud Rate Modulo Divisor Bit 6 */ word SBR7 :1; /* Baud Rate Modulo Divisor Bit 7 */ word SBR8 :1; /* Baud Rate Modulo Divisor Bit 8 */ word SBR9 :1; /* Baud Rate Modulo Divisor Bit 9 */ word SBR10 :1; /* Baud Rate Modulo Divisor Bit 10 */ word SBR11 :1; /* Baud Rate Modulo Divisor Bit 11 */ word SBR12 :1; /* Baud Rate Modulo Divisor Bit 12 */ word :1; word RXEDGIE :1; /* RxD Input Active Edge Interrupt Enable (for RXEDGIF) */ word LBKDIE :1; /* LIN Break Detect Interrupt Enable (for LBKDIF) */ } Bits; struct { word grpSBR :13; word :1; word :1; word :1; } MergedBits; } SCI3BDSTR; extern volatile SCI3BDSTR _SCI3BD @0xFFFF8300; #define SCI3BD _SCI3BD.Word #define SCI3BD_SBR0 _SCI3BD.Bits.SBR0 #define SCI3BD_SBR1 _SCI3BD.Bits.SBR1 #define SCI3BD_SBR2 _SCI3BD.Bits.SBR2 #define SCI3BD_SBR3 _SCI3BD.Bits.SBR3 #define SCI3BD_SBR4 _SCI3BD.Bits.SBR4 #define SCI3BD_SBR5 _SCI3BD.Bits.SBR5 #define SCI3BD_SBR6 _SCI3BD.Bits.SBR6 #define SCI3BD_SBR7 _SCI3BD.Bits.SBR7 #define SCI3BD_SBR8 _SCI3BD.Bits.SBR8 #define SCI3BD_SBR9 _SCI3BD.Bits.SBR9 #define SCI3BD_SBR10 _SCI3BD.Bits.SBR10 #define SCI3BD_SBR11 _SCI3BD.Bits.SBR11 #define SCI3BD_SBR12 _SCI3BD.Bits.SBR12 #define SCI3BD_RXEDGIE _SCI3BD.Bits.RXEDGIE #define SCI3BD_LBKDIE _SCI3BD.Bits.LBKDIE #define SCI3BD_SBR _SCI3BD.MergedBits.grpSBR #define SCI3BD_SBR0_MASK 1 #define SCI3BD_SBR1_MASK 2 #define SCI3BD_SBR2_MASK 4 #define SCI3BD_SBR3_MASK 8 #define SCI3BD_SBR4_MASK 16 #define SCI3BD_SBR5_MASK 32 #define SCI3BD_SBR6_MASK 64 #define SCI3BD_SBR7_MASK 128 #define SCI3BD_SBR8_MASK 256 #define SCI3BD_SBR9_MASK 512 #define SCI3BD_SBR10_MASK 1024 #define SCI3BD_SBR11_MASK 2048 #define SCI3BD_SBR12_MASK 4096 #define SCI3BD_RXEDGIE_MASK 16384 #define SCI3BD_LBKDIE_MASK 32768 #define SCI3BD_SBR_MASK 8191 #define SCI3BD_SBR_BITNUM 0 /*** SCI3C1 - SCI3 Control Register 1; 0xFFFF8302 ***/ typedef union { byte Byte; struct { byte PT :1; /* Parity Type */ byte PE :1; /* Parity Enable */ byte ILT :1; /* Idle Line Type Select */ byte WAKE :1; /* Receiver Wakeup Method Select */ byte M :1; /* 9-Bit or 8-Bit Mode Select */ byte RSRC :1; /* Receiver Source Select */ byte SCISWAI :1; /* SCI Stops in Wait Mode */ byte LOOPS :1; /* Loop Mode Select */ } Bits; } SCI3C1STR; extern volatile SCI3C1STR _SCI3C1 @0xFFFF8302; #define SCI3C1 _SCI3C1.Byte #define SCI3C1_PT _SCI3C1.Bits.PT #define SCI3C1_PE _SCI3C1.Bits.PE #define SCI3C1_ILT _SCI3C1.Bits.ILT #define SCI3C1_WAKE _SCI3C1.Bits.WAKE #define SCI3C1_M _SCI3C1.Bits.M #define SCI3C1_RSRC _SCI3C1.Bits.RSRC #define SCI3C1_SCISWAI _SCI3C1.Bits.SCISWAI #define SCI3C1_LOOPS _SCI3C1.Bits.LOOPS #define SCI3C1_PT_MASK 1 #define SCI3C1_PE_MASK 2 #define SCI3C1_ILT_MASK 4 #define SCI3C1_WAKE_MASK 8 #define SCI3C1_M_MASK 16 #define SCI3C1_RSRC_MASK 32 #define SCI3C1_SCISWAI_MASK 64 #define SCI3C1_LOOPS_MASK 128 /*** SCI3C2 - SCI3 Control Register 2; 0xFFFF8303 ***/ typedef union { byte Byte; struct { byte SBK :1; /* Send Break */ byte RWU :1; /* Receiver Wakeup Control */ byte RE :1; /* Receiver Enable */ byte TE :1; /* Transmitter Enable */ byte ILIE :1; /* Idle Line Interrupt Enable (for IDLE) */ byte RIE :1; /* Receiver Interrupt Enable (for RDRF) */ byte TCIE :1; /* Transmission Complete Interrupt Enable (for TC) */ byte TIE :1; /* Transmit Interrupt Enable (for TDRE) */ } Bits; } SCI3C2STR; extern volatile SCI3C2STR _SCI3C2 @0xFFFF8303; #define SCI3C2 _SCI3C2.Byte #define SCI3C2_SBK _SCI3C2.Bits.SBK #define SCI3C2_RWU _SCI3C2.Bits.RWU #define SCI3C2_RE _SCI3C2.Bits.RE #define SCI3C2_TE _SCI3C2.Bits.TE #define SCI3C2_ILIE _SCI3C2.Bits.ILIE #define SCI3C2_RIE _SCI3C2.Bits.RIE #define SCI3C2_TCIE _SCI3C2.Bits.TCIE #define SCI3C2_TIE _SCI3C2.Bits.TIE #define SCI3C2_SBK_MASK 1 #define SCI3C2_RWU_MASK 2 #define SCI3C2_RE_MASK 4 #define SCI3C2_TE_MASK 8 #define SCI3C2_ILIE_MASK 16 #define SCI3C2_RIE_MASK 32 #define SCI3C2_TCIE_MASK 64 #define SCI3C2_TIE_MASK 128 /*** SCI3S1 - SCI3 Status Register 1; 0xFFFF8304 ***/ typedef union { byte Byte; struct { byte PF :1; /* Parity Error Flag */ byte FE :1; /* Framing Error Flag */ byte NF :1; /* Noise Flag */ byte OR :1; /* Receiver Overrun Flag */ byte IDLE :1; /* Idle Line Flag */ byte RDRF :1; /* Receive Data Register Full Flag */ byte TC :1; /* Transmission Complete Flag */ byte TDRE :1; /* Transmit Data Register Empty Flag */ } Bits; } SCI3S1STR; extern volatile SCI3S1STR _SCI3S1 @0xFFFF8304; #define SCI3S1 _SCI3S1.Byte #define SCI3S1_PF _SCI3S1.Bits.PF #define SCI3S1_FE _SCI3S1.Bits.FE #define SCI3S1_NF _SCI3S1.Bits.NF #define SCI3S1_OR _SCI3S1.Bits.OR #define SCI3S1_IDLE _SCI3S1.Bits.IDLE #define SCI3S1_RDRF _SCI3S1.Bits.RDRF #define SCI3S1_TC _SCI3S1.Bits.TC #define SCI3S1_TDRE _SCI3S1.Bits.TDRE #define SCI3S1_PF_MASK 1 #define SCI3S1_FE_MASK 2 #define SCI3S1_NF_MASK 4 #define SCI3S1_OR_MASK 8 #define SCI3S1_IDLE_MASK 16 #define SCI3S1_RDRF_MASK 32 #define SCI3S1_TC_MASK 64 #define SCI3S1_TDRE_MASK 128 /*** SCI3S2 - SCI3 Status Register 2; 0xFFFF8305 ***/ typedef union { byte Byte; struct { byte RAF :1; /* Receiver Active Flag */ byte LBKDE :1; /* LIN Break Detection Enable */ byte BRK13 :1; /* Break Character Generation Length */ byte RWUID :1; /* Receive Wake Up Idle Detect */ byte RXINV :1; /* Receive Data Inversion */ byte :1; byte RXEDGIF :1; /* RxD Pin Active Edge Interrupt Flag */ byte LBKDIF :1; /* LIN Break Detect Interrupt Flag */ } Bits; } SCI3S2STR; extern volatile SCI3S2STR _SCI3S2 @0xFFFF8305; #define SCI3S2 _SCI3S2.Byte #define SCI3S2_RAF _SCI3S2.Bits.RAF #define SCI3S2_LBKDE _SCI3S2.Bits.LBKDE #define SCI3S2_BRK13 _SCI3S2.Bits.BRK13 #define SCI3S2_RWUID _SCI3S2.Bits.RWUID #define SCI3S2_RXINV _SCI3S2.Bits.RXINV #define SCI3S2_RXEDGIF _SCI3S2.Bits.RXEDGIF #define SCI3S2_LBKDIF _SCI3S2.Bits.LBKDIF #define SCI3S2_RAF_MASK 1 #define SCI3S2_LBKDE_MASK 2 #define SCI3S2_BRK13_MASK 4 #define SCI3S2_RWUID_MASK 8 #define SCI3S2_RXINV_MASK 16 #define SCI3S2_RXEDGIF_MASK 64 #define SCI3S2_LBKDIF_MASK 128 /*** SCI3C3 - SCI3 Control Register 3; 0xFFFF8306 ***/ typedef union { byte Byte; struct { byte PEIE :1; /* Parity Error Interrupt Enable */ byte FEIE :1; /* Framing Error Interrupt Enable */ byte NEIE :1; /* Noise Error Interrupt Enable */ byte ORIE :1; /* Overrun Interrupt Enable */ byte TXINV :1; /* Transmit Data Inversion */ byte TXDIR :1; /* TxD Pin Direction in Single-Wire Mode */ byte T8 :1; /* Ninth Data Bit for Transmitter */ byte R8 :1; /* Ninth Data Bit for Receiver */ } Bits; } SCI3C3STR; extern volatile SCI3C3STR _SCI3C3 @0xFFFF8306; #define SCI3C3 _SCI3C3.Byte #define SCI3C3_PEIE _SCI3C3.Bits.PEIE #define SCI3C3_FEIE _SCI3C3.Bits.FEIE #define SCI3C3_NEIE _SCI3C3.Bits.NEIE #define SCI3C3_ORIE _SCI3C3.Bits.ORIE #define SCI3C3_TXINV _SCI3C3.Bits.TXINV #define SCI3C3_TXDIR _SCI3C3.Bits.TXDIR #define SCI3C3_T8 _SCI3C3.Bits.T8 #define SCI3C3_R8 _SCI3C3.Bits.R8 #define SCI3C3_PEIE_MASK 1 #define SCI3C3_FEIE_MASK 2 #define SCI3C3_NEIE_MASK 4 #define SCI3C3_ORIE_MASK 8 #define SCI3C3_TXINV_MASK 16 #define SCI3C3_TXDIR_MASK 32 #define SCI3C3_T8_MASK 64 #define SCI3C3_R8_MASK 128 /*** SCI3D - SCI3 Data Register; 0xFFFF8307 ***/ typedef union { byte Byte; struct { byte R0_T0 :1; /* Receive/Transmit Data Bit 0 */ byte R1_T1 :1; /* Receive/Transmit Data Bit 1 */ byte R2_T2 :1; /* Receive/Transmit Data Bit 2 */ byte R3_T3 :1; /* Receive/Transmit Data Bit 3 */ byte R4_T4 :1; /* Receive/Transmit Data Bit 4 */ byte R5_T5 :1; /* Receive/Transmit Data Bit 5 */ byte R6_T6 :1; /* Receive/Transmit Data Bit 6 */ byte R7_T7 :1; /* Receive/Transmit Data Bit 7 */ } Bits; } SCI3DSTR; extern volatile SCI3DSTR _SCI3D @0xFFFF8307; #define SCI3D _SCI3D.Byte #define SCI3D_R0_T0 _SCI3D.Bits.R0_T0 #define SCI3D_R1_T1 _SCI3D.Bits.R1_T1 #define SCI3D_R2_T2 _SCI3D.Bits.R2_T2 #define SCI3D_R3_T3 _SCI3D.Bits.R3_T3 #define SCI3D_R4_T4 _SCI3D.Bits.R4_T4 #define SCI3D_R5_T5 _SCI3D.Bits.R5_T5 #define SCI3D_R6_T6 _SCI3D.Bits.R6_T6 #define SCI3D_R7_T7 _SCI3D.Bits.R7_T7 #define SCI3D_R0_T0_MASK 1 #define SCI3D_R1_T1_MASK 2 #define SCI3D_R2_T2_MASK 4 #define SCI3D_R3_T3_MASK 8 #define SCI3D_R4_T4_MASK 16 #define SCI3D_R5_T5_MASK 32 #define SCI3D_R6_T6_MASK 64 #define SCI3D_R7_T7_MASK 128 /*** SPI1C1 - SPI1 Control Register 1; 0xFFFF8320 ***/ typedef union { byte Byte; struct { byte LSBFE :1; /* LSB First (Shifter Direction) */ byte SSOE :1; /* Slave Select Output Enable */ byte CPHA :1; /* Clock Phase */ byte CPOL :1; /* Clock Polarity */ byte MSTR :1; /* Master/Slave Mode Select */ byte SPTIE :1; /* SPI Transmit Interrupt Enable */ byte SPE :1; /* SPI System Enable */ byte SPIE :1; /* SPI Interrupt Enable (for SPRF and MODF) */ } Bits; } SPI1C1STR; extern volatile SPI1C1STR _SPI1C1 @0xFFFF8320; #define SPI1C1 _SPI1C1.Byte #define SPI1C1_LSBFE _SPI1C1.Bits.LSBFE #define SPI1C1_SSOE _SPI1C1.Bits.SSOE #define SPI1C1_CPHA _SPI1C1.Bits.CPHA #define SPI1C1_CPOL _SPI1C1.Bits.CPOL #define SPI1C1_MSTR _SPI1C1.Bits.MSTR #define SPI1C1_SPTIE _SPI1C1.Bits.SPTIE #define SPI1C1_SPE _SPI1C1.Bits.SPE #define SPI1C1_SPIE _SPI1C1.Bits.SPIE #define SPI1C1_LSBFE_MASK 1 #define SPI1C1_SSOE_MASK 2 #define SPI1C1_CPHA_MASK 4 #define SPI1C1_CPOL_MASK 8 #define SPI1C1_MSTR_MASK 16 #define SPI1C1_SPTIE_MASK 32 #define SPI1C1_SPE_MASK 64 #define SPI1C1_SPIE_MASK 128 /*** SPI1C2 - SPI1 Control Register 2; 0xFFFF8321 ***/ typedef union { byte Byte; struct { byte SPC0 :1; /* SPI Pin Control 0 */ byte SPISWAI :1; /* SPI Stop in Wait Mode */ byte :1; byte BIDIROE :1; /* Bidirectional Mode Output Enable */ byte MODFEN :1; /* Master Mode-Fault Function Enable */ byte :1; byte SPIMODE :1; /* SPI 8- or 16-bit Mode Select */ byte SPMIE :1; /* SPI Match Interrupt Enable */ } Bits; } SPI1C2STR; extern volatile SPI1C2STR _SPI1C2 @0xFFFF8321; #define SPI1C2 _SPI1C2.Byte #define SPI1C2_SPC0 _SPI1C2.Bits.SPC0 #define SPI1C2_SPISWAI _SPI1C2.Bits.SPISWAI #define SPI1C2_BIDIROE _SPI1C2.Bits.BIDIROE #define SPI1C2_MODFEN _SPI1C2.Bits.MODFEN #define SPI1C2_SPIMODE _SPI1C2.Bits.SPIMODE #define SPI1C2_SPMIE _SPI1C2.Bits.SPMIE #define SPI1C2_SPC0_MASK 1 #define SPI1C2_SPISWAI_MASK 2 #define SPI1C2_BIDIROE_MASK 8 #define SPI1C2_MODFEN_MASK 16 #define SPI1C2_SPIMODE_MASK 64 #define SPI1C2_SPMIE_MASK 128 /*** SPI1BR - SPI1 Baud Rate Register; 0xFFFF8322 ***/ typedef union { byte Byte; struct { byte SPR0 :1; /* SPI Baud Rate Divisor Bit 0 */ byte SPR1 :1; /* SPI Baud Rate Divisor Bit 1 */ byte SPR2 :1; /* SPI Baud Rate Divisor Bit 2 */ byte SPR3 :1; /* SPI Baud Rate Divisor Bit 3 */ byte SPPR0 :1; /* SPI Baud Rate Prescale Divisor Bit 0 */ byte SPPR1 :1; /* SPI Baud Rate Prescale Divisor Bit 1 */ byte SPPR2 :1; /* SPI Baud Rate Prescale Divisor Bit 2 */ byte :1; } Bits; struct { byte grpSPR :4; byte grpSPPR :3; byte :1; } MergedBits; } SPI1BRSTR; extern volatile SPI1BRSTR _SPI1BR @0xFFFF8322; #define SPI1BR _SPI1BR.Byte #define SPI1BR_SPR0 _SPI1BR.Bits.SPR0 #define SPI1BR_SPR1 _SPI1BR.Bits.SPR1 #define SPI1BR_SPR2 _SPI1BR.Bits.SPR2 #define SPI1BR_SPR3 _SPI1BR.Bits.SPR3 #define SPI1BR_SPPR0 _SPI1BR.Bits.SPPR0 #define SPI1BR_SPPR1 _SPI1BR.Bits.SPPR1 #define SPI1BR_SPPR2 _SPI1BR.Bits.SPPR2 #define SPI1BR_SPR _SPI1BR.MergedBits.grpSPR #define SPI1BR_SPPR _SPI1BR.MergedBits.grpSPPR #define SPI1BR_SPR0_MASK 1 #define SPI1BR_SPR1_MASK 2 #define SPI1BR_SPR2_MASK 4 #define SPI1BR_SPR3_MASK 8 #define SPI1BR_SPPR0_MASK 16 #define SPI1BR_SPPR1_MASK 32 #define SPI1BR_SPPR2_MASK 64 #define SPI1BR_SPR_MASK 15 #define SPI1BR_SPR_BITNUM 0 #define SPI1BR_SPPR_MASK 112 #define SPI1BR_SPPR_BITNUM 4 /*** SPI1S - SPI1 Status Register; 0xFFFF8323 ***/ typedef union { byte Byte; struct { byte RFIFOEF :1; /* SPI Read FIFO Empty Flag */ byte TXFULLF :1; /* SPI Transmit FIFO Full Flag */ byte TNEAREF :1; /* SPI Transmit FIFO Nearly Empty Flag */ byte RNFULLF :1; /* SPI Receive FIFO Nearly Full Flag */ byte MODF :1; /* Master Mode Fault Flag */ byte SPTEF :1; /* SPI Transmit Buffer Empty Flag */ byte SPMF :1; /* SPI Match Flag */ byte SPRF :1; /* SPI Read Buffer Full Flag */ } Bits; } SPI1SSTR; extern volatile SPI1SSTR _SPI1S @0xFFFF8323; #define SPI1S _SPI1S.Byte #define SPI1S_RFIFOEF _SPI1S.Bits.RFIFOEF #define SPI1S_TXFULLF _SPI1S.Bits.TXFULLF #define SPI1S_TNEAREF _SPI1S.Bits.TNEAREF #define SPI1S_RNFULLF _SPI1S.Bits.RNFULLF #define SPI1S_MODF _SPI1S.Bits.MODF #define SPI1S_SPTEF _SPI1S.Bits.SPTEF #define SPI1S_SPMF _SPI1S.Bits.SPMF #define SPI1S_SPRF _SPI1S.Bits.SPRF #define SPI1S_RFIFOEF_MASK 1 #define SPI1S_TXFULLF_MASK 2 #define SPI1S_TNEAREF_MASK 4 #define SPI1S_RNFULLF_MASK 8 #define SPI1S_MODF_MASK 16 #define SPI1S_SPTEF_MASK 32 #define SPI1S_SPMF_MASK 64 #define SPI1S_SPRF_MASK 128 /*** SPI1D16 - SPI1 Data Register; 0xFFFF8324 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** SPI1DH - SPI1 Data Register High; 0xFFFF8324 ***/ union { byte Byte; } SPI1DHSTR; #define SPI1DH _SPI1D16.Overlap_STR.SPI1DHSTR.Byte /*** SPI1DL - SPI1 Data Register Low; 0xFFFF8325 ***/ union { byte Byte; union { /* Several registers at the same address */ /*** SPI1DL - SPI1 Data Register Low; Several registers at the same address ***/ #define SPI1DL _SPI1D16.Overlap_STR.SPI1DLSTR.Byte /*** SPI1D - SPI1 Data Register Low; Several registers at the same address ***/ union { struct { byte Bit0 :1; /* SPI Data Bit 0 */ byte Bit1 :1; /* SPI Data Bit 1 */ byte Bit2 :1; /* SPI Data Bit 2 */ byte Bit3 :1; /* SPI Data Bit 3 */ byte Bit4 :1; /* SPI Data Bit 4 */ byte Bit5 :1; /* SPI Data Bit 5 */ byte Bit6 :1; /* SPI Data Bit 6 */ byte Bit7 :1; /* SPI Data Bit 7 */ } Bits; } SPI1DSTR; #define SPI1D _SPI1D16.Overlap_STR.SPI1DLSTR.Byte #define SPI1D_Bit0 _SPI1D16.Overlap_STR.SPI1DLSTR.SameAddr_STR.SPI1DSTR.Bits.Bit0 #define SPI1D_Bit1 _SPI1D16.Overlap_STR.SPI1DLSTR.SameAddr_STR.SPI1DSTR.Bits.Bit1 #define SPI1D_Bit2 _SPI1D16.Overlap_STR.SPI1DLSTR.SameAddr_STR.SPI1DSTR.Bits.Bit2 #define SPI1D_Bit3 _SPI1D16.Overlap_STR.SPI1DLSTR.SameAddr_STR.SPI1DSTR.Bits.Bit3 #define SPI1D_Bit4 _SPI1D16.Overlap_STR.SPI1DLSTR.SameAddr_STR.SPI1DSTR.Bits.Bit4 #define SPI1D_Bit5 _SPI1D16.Overlap_STR.SPI1DLSTR.SameAddr_STR.SPI1DSTR.Bits.Bit5 #define SPI1D_Bit6 _SPI1D16.Overlap_STR.SPI1DLSTR.SameAddr_STR.SPI1DSTR.Bits.Bit6 #define SPI1D_Bit7 _SPI1D16.Overlap_STR.SPI1DLSTR.SameAddr_STR.SPI1DSTR.Bits.Bit7 #define SPI1D_Bit0_MASK 1 #define SPI1D_Bit1_MASK 2 #define SPI1D_Bit2_MASK 4 #define SPI1D_Bit3_MASK 8 #define SPI1D_Bit4_MASK 16 #define SPI1D_Bit5_MASK 32 #define SPI1D_Bit6_MASK 64 #define SPI1D_Bit7_MASK 128 } SameAddr_STR; /*Several registers at the same address */ } SPI1DLSTR; } Overlap_STR; } SPI1D16STR; extern volatile SPI1D16STR _SPI1D16 @0xFFFF8324; #define SPI1D16 _SPI1D16.Word /*** SPI1M - SPI1 Match Register; 0xFFFF8326 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** SPI1MH - SPI1 Match Register High; 0xFFFF8326 ***/ union { byte Byte; struct { byte Bit8 :1; /* SPI Match Value Bit 8 */ byte Bit9 :1; /* SPI Match Value Bit 9 */ byte Bit10 :1; /* SPI Match Value Bit 10 */ byte Bit11 :1; /* SPI Match Value Bit 11 */ byte Bit12 :1; /* SPI Match Value Bit 12 */ byte Bit13 :1; /* SPI Match Value Bit 13 */ byte Bit14 :1; /* SPI Match Value Bit 14 */ byte Bit15 :1; /* SPI Match Value Bit 15 */ } Bits; } SPI1MHSTR; #define SPI1MH _SPI1M.Overlap_STR.SPI1MHSTR.Byte #define SPI1MH_Bit8 _SPI1M.Overlap_STR.SPI1MHSTR.Bits.Bit8 #define SPI1MH_Bit9 _SPI1M.Overlap_STR.SPI1MHSTR.Bits.Bit9 #define SPI1MH_Bit10 _SPI1M.Overlap_STR.SPI1MHSTR.Bits.Bit10 #define SPI1MH_Bit11 _SPI1M.Overlap_STR.SPI1MHSTR.Bits.Bit11 #define SPI1MH_Bit12 _SPI1M.Overlap_STR.SPI1MHSTR.Bits.Bit12 #define SPI1MH_Bit13 _SPI1M.Overlap_STR.SPI1MHSTR.Bits.Bit13 #define SPI1MH_Bit14 _SPI1M.Overlap_STR.SPI1MHSTR.Bits.Bit14 #define SPI1MH_Bit15 _SPI1M.Overlap_STR.SPI1MHSTR.Bits.Bit15 #define SPI1MH_Bit8_MASK 1 #define SPI1MH_Bit9_MASK 2 #define SPI1MH_Bit10_MASK 4 #define SPI1MH_Bit11_MASK 8 #define SPI1MH_Bit12_MASK 16 #define SPI1MH_Bit13_MASK 32 #define SPI1MH_Bit14_MASK 64 #define SPI1MH_Bit15_MASK 128 /*** SPI1ML - SPI1 Match Register Low; 0xFFFF8327 ***/ union { byte Byte; struct { byte Bit0 :1; /* SPI Match Value Bit 0 */ byte Bit1 :1; /* SPI Match Value Bit 1 */ byte Bit2 :1; /* SPI Match Value Bit 2 */ byte Bit3 :1; /* SPI Match Value Bit 3 */ byte Bit4 :1; /* SPI Match Value Bit 4 */ byte Bit5 :1; /* SPI Match Value Bit 5 */ byte Bit6 :1; /* SPI Match Value Bit 6 */ byte Bit7 :1; /* SPI Match Value Bit 7 */ } Bits; } SPI1MLSTR; #define SPI1ML _SPI1M.Overlap_STR.SPI1MLSTR.Byte #define SPI1ML_Bit0 _SPI1M.Overlap_STR.SPI1MLSTR.Bits.Bit0 #define SPI1ML_Bit1 _SPI1M.Overlap_STR.SPI1MLSTR.Bits.Bit1 #define SPI1ML_Bit2 _SPI1M.Overlap_STR.SPI1MLSTR.Bits.Bit2 #define SPI1ML_Bit3 _SPI1M.Overlap_STR.SPI1MLSTR.Bits.Bit3 #define SPI1ML_Bit4 _SPI1M.Overlap_STR.SPI1MLSTR.Bits.Bit4 #define SPI1ML_Bit5 _SPI1M.Overlap_STR.SPI1MLSTR.Bits.Bit5 #define SPI1ML_Bit6 _SPI1M.Overlap_STR.SPI1MLSTR.Bits.Bit6 #define SPI1ML_Bit7 _SPI1M.Overlap_STR.SPI1MLSTR.Bits.Bit7 #define SPI1ML_Bit0_MASK 1 #define SPI1ML_Bit1_MASK 2 #define SPI1ML_Bit2_MASK 4 #define SPI1ML_Bit3_MASK 8 #define SPI1ML_Bit4_MASK 16 #define SPI1ML_Bit5_MASK 32 #define SPI1ML_Bit6_MASK 64 #define SPI1ML_Bit7_MASK 128 } Overlap_STR; struct { word Bit0 :1; /* SPI Match Value Bit 0 */ word Bit1 :1; /* SPI Match Value Bit 1 */ word Bit2 :1; /* SPI Match Value Bit 2 */ word Bit3 :1; /* SPI Match Value Bit 3 */ word Bit4 :1; /* SPI Match Value Bit 4 */ word Bit5 :1; /* SPI Match Value Bit 5 */ word Bit6 :1; /* SPI Match Value Bit 6 */ word Bit7 :1; /* SPI Match Value Bit 7 */ word Bit8 :1; /* SPI Match Value Bit 8 */ word Bit9 :1; /* SPI Match Value Bit 9 */ word Bit10 :1; /* SPI Match Value Bit 10 */ word Bit11 :1; /* SPI Match Value Bit 11 */ word Bit12 :1; /* SPI Match Value Bit 12 */ word Bit13 :1; /* SPI Match Value Bit 13 */ word Bit14 :1; /* SPI Match Value Bit 14 */ word Bit15 :1; /* SPI Match Value Bit 15 */ } Bits; } SPI1MSTR; extern volatile SPI1MSTR _SPI1M @0xFFFF8326; #define SPI1M _SPI1M.Word #define SPI1M_Bit0 _SPI1M.Bits.Bit0 #define SPI1M_Bit1 _SPI1M.Bits.Bit1 #define SPI1M_Bit2 _SPI1M.Bits.Bit2 #define SPI1M_Bit3 _SPI1M.Bits.Bit3 #define SPI1M_Bit4 _SPI1M.Bits.Bit4 #define SPI1M_Bit5 _SPI1M.Bits.Bit5 #define SPI1M_Bit6 _SPI1M.Bits.Bit6 #define SPI1M_Bit7 _SPI1M.Bits.Bit7 #define SPI1M_Bit8 _SPI1M.Bits.Bit8 #define SPI1M_Bit9 _SPI1M.Bits.Bit9 #define SPI1M_Bit10 _SPI1M.Bits.Bit10 #define SPI1M_Bit11 _SPI1M.Bits.Bit11 #define SPI1M_Bit12 _SPI1M.Bits.Bit12 #define SPI1M_Bit13 _SPI1M.Bits.Bit13 #define SPI1M_Bit14 _SPI1M.Bits.Bit14 #define SPI1M_Bit15 _SPI1M.Bits.Bit15 #define SPI1M_Bit0_MASK 1 #define SPI1M_Bit1_MASK 2 #define SPI1M_Bit2_MASK 4 #define SPI1M_Bit3_MASK 8 #define SPI1M_Bit4_MASK 16 #define SPI1M_Bit5_MASK 32 #define SPI1M_Bit6_MASK 64 #define SPI1M_Bit7_MASK 128 #define SPI1M_Bit8_MASK 256 #define SPI1M_Bit9_MASK 512 #define SPI1M_Bit10_MASK 1024 #define SPI1M_Bit11_MASK 2048 #define SPI1M_Bit12_MASK 4096 #define SPI1M_Bit13_MASK 8192 #define SPI1M_Bit14_MASK 16384 #define SPI1M_Bit15_MASK 32768 /*** SPI1C3 - SPI1 Control Register 3; 0xFFFF8328 ***/ typedef union { byte Byte; struct { byte FIFOMODE :1; /* SPI FIFO Mode Enable */ byte RNFULLIEN :1; /* Receive FIFO Nearly Full Interrupt Enable. This is an additional interrupt on the SPI and will only interrupt the CPU if SPIE in the SPIxC1 register is also set. This bit is ignored and has no function if FIFOMODE=0 */ byte TNEARIEN :1; /* Transmit FIFO Nearly Empty Interrupt Enable. This is an additional interrupt on the SPI and will only interrupt the CPU if SPTIE in the
SPIxC1 register is also set. This bit is ignored and has no function if FIFOMODE=0 */ byte INTCLR :1; /* Interrupt Clearing Mechanism Select - This bit selects the mechanism by which SPRF, SPTEF, TNEAREF, RNFULLF interrupts gets cleared */ byte RNFULLF_MARK :1; /* Receive FIFO Nearly Full Water Mark - This bit selects the mark for which RNFULLF flag is asserted */ byte TNEAREF_MARK :1; /* Transmit FIFO Nearly Empty Water Mark - This bit selects the mark after which TNEAREF flag is asserted */ byte :1; byte :1; } Bits; } SPI1C3STR; extern volatile SPI1C3STR _SPI1C3 @0xFFFF8328; #define SPI1C3 _SPI1C3.Byte #define SPI1C3_FIFOMODE _SPI1C3.Bits.FIFOMODE #define SPI1C3_RNFULLIEN _SPI1C3.Bits.RNFULLIEN #define SPI1C3_TNEARIEN _SPI1C3.Bits.TNEARIEN #define SPI1C3_INTCLR _SPI1C3.Bits.INTCLR #define SPI1C3_RNFULLF_MARK _SPI1C3.Bits.RNFULLF_MARK #define SPI1C3_TNEAREF_MARK _SPI1C3.Bits.TNEAREF_MARK #define SPI1C3_FIFOMODE_MASK 1 #define SPI1C3_RNFULLIEN_MASK 2 #define SPI1C3_TNEARIEN_MASK 4 #define SPI1C3_INTCLR_MASK 8 #define SPI1C3_RNFULLF_MARK_MASK 16 #define SPI1C3_TNEAREF_MARK_MASK 32 /*** SPI1CI - SPI1 Clear Interrupt Register; 0xFFFF8329 ***/ typedef union { byte Byte; struct { byte SPRFCI :1; /* Receive FIFO Full Flag Clear Interrupt Bit - Write of 1 clears the TNEAREF interrupt provided SPIxC3[3] is set */ byte SPTEFCI :1; /* Transmit FIFO Empty Flag Clear Interrupt Bit - Write of 1 clears the SPTEF interrupt provided SPIxC3[3] SPTEFCI is set */ byte RNFULLFCI :1; /* Receive FIFO Nearly Full Flag Clear Interrupt - Write of 1 clears the RNFULLF interrupt provided SPIxC3[3] is set */ byte TNEAREFCI :1; /* Transmit FIFO Nearly Empty Flag Clear Interrupt Bit - Write of 1 clears the TNEAREF interrupt provided SPIxC3[3] is set */ byte RXFOF :1; /* RX FIFO Overflow Flag - This Flag indicates that RX FIFO overflow condition has occured */ byte TXFOF :1; /* TX FIFO Overflow Flag - This Flag indicates that TX FIFO overflow condition has occured */ byte RXFERR :1; /* Receive FIFO Error Flag - This flag indicates that RX FIFO error occured because entries in fifo goes above 8 */ byte TXFERR :1; /* Transmit FIFO ErrorFlag - This flag indicates that TX FIFO error occured because entries in fifo goes above 8 */ } Bits; } SPI1CISTR; extern volatile SPI1CISTR _SPI1CI @0xFFFF8329; #define SPI1CI _SPI1CI.Byte #define SPI1CI_SPRFCI _SPI1CI.Bits.SPRFCI #define SPI1CI_SPTEFCI _SPI1CI.Bits.SPTEFCI #define SPI1CI_RNFULLFCI _SPI1CI.Bits.RNFULLFCI #define SPI1CI_TNEAREFCI _SPI1CI.Bits.TNEAREFCI #define SPI1CI_RXFOF _SPI1CI.Bits.RXFOF #define SPI1CI_TXFOF _SPI1CI.Bits.TXFOF #define SPI1CI_RXFERR _SPI1CI.Bits.RXFERR #define SPI1CI_TXFERR _SPI1CI.Bits.TXFERR #define SPI1CI_SPRFCI_MASK 1 #define SPI1CI_SPTEFCI_MASK 2 #define SPI1CI_RNFULLFCI_MASK 4 #define SPI1CI_TNEAREFCI_MASK 8 #define SPI1CI_RXFOF_MASK 16 #define SPI1CI_TXFOF_MASK 32 #define SPI1CI_RXFERR_MASK 64 #define SPI1CI_TXFERR_MASK 128 /*** SPI2C1 - SPI2 Control Register 1; 0xFFFF8340 ***/ typedef union { byte Byte; struct { byte LSBFE :1; /* LSB First (Shifter Direction) */ byte SSOE :1; /* Slave Select Output Enable */ byte CPHA :1; /* Clock Phase */ byte CPOL :1; /* Clock Polarity */ byte MSTR :1; /* Master/Slave Mode Select */ byte SPTIE :1; /* SPI Transmit Interrupt Enable */ byte SPE :1; /* SPI System Enable */ byte SPIE :1; /* SPI Interrupt Enable (for SPRF and MODF) */ } Bits; } SPI2C1STR; extern volatile SPI2C1STR _SPI2C1 @0xFFFF8340; #define SPI2C1 _SPI2C1.Byte #define SPI2C1_LSBFE _SPI2C1.Bits.LSBFE #define SPI2C1_SSOE _SPI2C1.Bits.SSOE #define SPI2C1_CPHA _SPI2C1.Bits.CPHA #define SPI2C1_CPOL _SPI2C1.Bits.CPOL #define SPI2C1_MSTR _SPI2C1.Bits.MSTR #define SPI2C1_SPTIE _SPI2C1.Bits.SPTIE #define SPI2C1_SPE _SPI2C1.Bits.SPE #define SPI2C1_SPIE _SPI2C1.Bits.SPIE #define SPI2C1_LSBFE_MASK 1 #define SPI2C1_SSOE_MASK 2 #define SPI2C1_CPHA_MASK 4 #define SPI2C1_CPOL_MASK 8 #define SPI2C1_MSTR_MASK 16 #define SPI2C1_SPTIE_MASK 32 #define SPI2C1_SPE_MASK 64 #define SPI2C1_SPIE_MASK 128 /*** SPI2C2 - SPI2 Control Register 2; 0xFFFF8341 ***/ typedef union { byte Byte; struct { byte SPC0 :1; /* SPI Pin Control 0 */ byte SPISWAI :1; /* SPI Stop in Wait Mode */ byte :1; byte BIDIROE :1; /* Bidirectional Mode Output Enable */ byte MODFEN :1; /* Master Mode-Fault Function Enable */ byte :1; byte :1; byte :1; } Bits; } SPI2C2STR; extern volatile SPI2C2STR _SPI2C2 @0xFFFF8341; #define SPI2C2 _SPI2C2.Byte #define SPI2C2_SPC0 _SPI2C2.Bits.SPC0 #define SPI2C2_SPISWAI _SPI2C2.Bits.SPISWAI #define SPI2C2_BIDIROE _SPI2C2.Bits.BIDIROE #define SPI2C2_MODFEN _SPI2C2.Bits.MODFEN #define SPI2C2_SPC0_MASK 1 #define SPI2C2_SPISWAI_MASK 2 #define SPI2C2_BIDIROE_MASK 8 #define SPI2C2_MODFEN_MASK 16 /*** SPI2BR - SPI2 Baud Rate Register; 0xFFFF8342 ***/ typedef union { byte Byte; struct { byte SPR0 :1; /* SPI Baud Rate Divisor Bit 0 */ byte SPR1 :1; /* SPI Baud Rate Divisor Bit 1 */ byte SPR2 :1; /* SPI Baud Rate Divisor Bit 2 */ byte SPR3 :1; /* SPI Baud Rate Divisor Bit 3 */ byte SPPR0 :1; /* SPI Baud Rate Prescale Divisor Bit 0 */ byte SPPR1 :1; /* SPI Baud Rate Prescale Divisor Bit 1 */ byte SPPR2 :1; /* SPI Baud Rate Prescale Divisor Bit 2 */ byte :1; } Bits; struct { byte grpSPR :4; byte grpSPPR :3; byte :1; } MergedBits; } SPI2BRSTR; extern volatile SPI2BRSTR _SPI2BR @0xFFFF8342; #define SPI2BR _SPI2BR.Byte #define SPI2BR_SPR0 _SPI2BR.Bits.SPR0 #define SPI2BR_SPR1 _SPI2BR.Bits.SPR1 #define SPI2BR_SPR2 _SPI2BR.Bits.SPR2 #define SPI2BR_SPR3 _SPI2BR.Bits.SPR3 #define SPI2BR_SPPR0 _SPI2BR.Bits.SPPR0 #define SPI2BR_SPPR1 _SPI2BR.Bits.SPPR1 #define SPI2BR_SPPR2 _SPI2BR.Bits.SPPR2 #define SPI2BR_SPR _SPI2BR.MergedBits.grpSPR #define SPI2BR_SPPR _SPI2BR.MergedBits.grpSPPR #define SPI2BR_SPR0_MASK 1 #define SPI2BR_SPR1_MASK 2 #define SPI2BR_SPR2_MASK 4 #define SPI2BR_SPR3_MASK 8 #define SPI2BR_SPPR0_MASK 16 #define SPI2BR_SPPR1_MASK 32 #define SPI2BR_SPPR2_MASK 64 #define SPI2BR_SPR_MASK 15 #define SPI2BR_SPR_BITNUM 0 #define SPI2BR_SPPR_MASK 112 #define SPI2BR_SPPR_BITNUM 4 /*** SPI2S - SPI2 Status Register; 0xFFFF8343 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte MODF :1; /* Master Mode Fault Flag */ byte SPTEF :1; /* SPI Transmit Buffer Empty Flag */ byte :1; byte SPRF :1; /* SPI Read Buffer Full Flag */ } Bits; } SPI2SSTR; extern volatile SPI2SSTR _SPI2S @0xFFFF8343; #define SPI2S _SPI2S.Byte #define SPI2S_MODF _SPI2S.Bits.MODF #define SPI2S_SPTEF _SPI2S.Bits.SPTEF #define SPI2S_SPRF _SPI2S.Bits.SPRF #define SPI2S_MODF_MASK 16 #define SPI2S_SPTEF_MASK 32 #define SPI2S_SPRF_MASK 128 /*** SPI2D - SPI2 Data Register; 0xFFFF8345 ***/ typedef union { byte Byte; } SPI2DSTR; extern volatile SPI2DSTR _SPI2D @0xFFFF8345; #define SPI2D _SPI2D.Byte /*** SPI3C1 - SPI3 Control Register 1; 0xFFFF8360 ***/ typedef union { byte Byte; struct { byte LSBFE :1; /* LSB First (Shifter Direction) */ byte SSOE :1; /* Slave Select Output Enable */ byte CPHA :1; /* Clock Phase */ byte CPOL :1; /* Clock Polarity */ byte MSTR :1; /* Master/Slave Mode Select */ byte SPTIE :1; /* SPI Transmit Interrupt Enable */ byte SPE :1; /* SPI System Enable */ byte SPIE :1; /* SPI Interrupt Enable (for SPRF and MODF) */ } Bits; } SPI3C1STR; extern volatile SPI3C1STR _SPI3C1 @0xFFFF8360; #define SPI3C1 _SPI3C1.Byte #define SPI3C1_LSBFE _SPI3C1.Bits.LSBFE #define SPI3C1_SSOE _SPI3C1.Bits.SSOE #define SPI3C1_CPHA _SPI3C1.Bits.CPHA #define SPI3C1_CPOL _SPI3C1.Bits.CPOL #define SPI3C1_MSTR _SPI3C1.Bits.MSTR #define SPI3C1_SPTIE _SPI3C1.Bits.SPTIE #define SPI3C1_SPE _SPI3C1.Bits.SPE #define SPI3C1_SPIE _SPI3C1.Bits.SPIE #define SPI3C1_LSBFE_MASK 1 #define SPI3C1_SSOE_MASK 2 #define SPI3C1_CPHA_MASK 4 #define SPI3C1_CPOL_MASK 8 #define SPI3C1_MSTR_MASK 16 #define SPI3C1_SPTIE_MASK 32 #define SPI3C1_SPE_MASK 64 #define SPI3C1_SPIE_MASK 128 /*** SPI3C2 - SPI3 Control Register 2; 0xFFFF8361 ***/ typedef union { byte Byte; struct { byte SPC0 :1; /* SPI Pin Control 0 */ byte SPISWAI :1; /* SPI Stop in Wait Mode */ byte :1; byte BIDIROE :1; /* Bidirectional Mode Output Enable */ byte MODFEN :1; /* Master Mode-Fault Function Enable */ byte :1; byte :1; byte :1; } Bits; } SPI3C2STR; extern volatile SPI3C2STR _SPI3C2 @0xFFFF8361; #define SPI3C2 _SPI3C2.Byte #define SPI3C2_SPC0 _SPI3C2.Bits.SPC0 #define SPI3C2_SPISWAI _SPI3C2.Bits.SPISWAI #define SPI3C2_BIDIROE _SPI3C2.Bits.BIDIROE #define SPI3C2_MODFEN _SPI3C2.Bits.MODFEN #define SPI3C2_SPC0_MASK 1 #define SPI3C2_SPISWAI_MASK 2 #define SPI3C2_BIDIROE_MASK 8 #define SPI3C2_MODFEN_MASK 16 /*** SPI3BR - SPI3 Baud Rate Register; 0xFFFF8362 ***/ typedef union { byte Byte; struct { byte SPR0 :1; /* SPI Baud Rate Divisor Bit 0 */ byte SPR1 :1; /* SPI Baud Rate Divisor Bit 1 */ byte SPR2 :1; /* SPI Baud Rate Divisor Bit 2 */ byte SPR3 :1; /* SPI Baud Rate Divisor Bit 3 */ byte SPPR0 :1; /* SPI Baud Rate Prescale Divisor Bit 0 */ byte SPPR1 :1; /* SPI Baud Rate Prescale Divisor Bit 1 */ byte SPPR2 :1; /* SPI Baud Rate Prescale Divisor Bit 2 */ byte :1; } Bits; struct { byte grpSPR :4; byte grpSPPR :3; byte :1; } MergedBits; } SPI3BRSTR; extern volatile SPI3BRSTR _SPI3BR @0xFFFF8362; #define SPI3BR _SPI3BR.Byte #define SPI3BR_SPR0 _SPI3BR.Bits.SPR0 #define SPI3BR_SPR1 _SPI3BR.Bits.SPR1 #define SPI3BR_SPR2 _SPI3BR.Bits.SPR2 #define SPI3BR_SPR3 _SPI3BR.Bits.SPR3 #define SPI3BR_SPPR0 _SPI3BR.Bits.SPPR0 #define SPI3BR_SPPR1 _SPI3BR.Bits.SPPR1 #define SPI3BR_SPPR2 _SPI3BR.Bits.SPPR2 #define SPI3BR_SPR _SPI3BR.MergedBits.grpSPR #define SPI3BR_SPPR _SPI3BR.MergedBits.grpSPPR #define SPI3BR_SPR0_MASK 1 #define SPI3BR_SPR1_MASK 2 #define SPI3BR_SPR2_MASK 4 #define SPI3BR_SPR3_MASK 8 #define SPI3BR_SPPR0_MASK 16 #define SPI3BR_SPPR1_MASK 32 #define SPI3BR_SPPR2_MASK 64 #define SPI3BR_SPR_MASK 15 #define SPI3BR_SPR_BITNUM 0 #define SPI3BR_SPPR_MASK 112 #define SPI3BR_SPPR_BITNUM 4 /*** SPI3S - SPI3 Status Register; 0xFFFF8363 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte MODF :1; /* Master Mode Fault Flag */ byte SPTEF :1; /* SPI Transmit Buffer Empty Flag */ byte :1; byte SPRF :1; /* SPI Read Buffer Full Flag */ } Bits; } SPI3SSTR; extern volatile SPI3SSTR _SPI3S @0xFFFF8363; #define SPI3S _SPI3S.Byte #define SPI3S_MODF _SPI3S.Bits.MODF #define SPI3S_SPTEF _SPI3S.Bits.SPTEF #define SPI3S_SPRF _SPI3S.Bits.SPRF #define SPI3S_MODF_MASK 16 #define SPI3S_SPTEF_MASK 32 #define SPI3S_SPRF_MASK 128 /*** SPI3D - SPI3 Data Register; 0xFFFF8365 ***/ typedef union { byte Byte; } SPI3DSTR; extern volatile SPI3DSTR _SPI3D @0xFFFF8365; #define SPI3D _SPI3D.Byte /*** IICA1 - IIC Address Register; 0xFFFF8380 ***/ typedef union { byte Byte; union { /* Several registers at the same address */ /*** IICA1 - IIC Address Register; Several registers at the same address ***/ union { struct { byte :1; byte AD1 :1; /* Slave Address Bit 1 */ byte AD2 :1; /* Slave Address Bit 2 */ byte AD3 :1; /* Slave Address Bit 3 */ byte AD4 :1; /* Slave Address Bit 4 */ byte AD5 :1; /* Slave Address Bit 5 */ byte AD6 :1; /* Slave Address Bit 6 */ byte AD7 :1; /* Slave Address Bit 7 */ } Bits; struct { byte :1; byte grpAD_1 :7; } MergedBits; } IICA1STR; #define IICA1 _IICA1.Byte #define IICA1_AD1 _IICA1.SameAddr_STR.IICA1STR.Bits.AD1 #define IICA1_AD2 _IICA1.SameAddr_STR.IICA1STR.Bits.AD2 #define IICA1_AD3 _IICA1.SameAddr_STR.IICA1STR.Bits.AD3 #define IICA1_AD4 _IICA1.SameAddr_STR.IICA1STR.Bits.AD4 #define IICA1_AD5 _IICA1.SameAddr_STR.IICA1STR.Bits.AD5 #define IICA1_AD6 _IICA1.SameAddr_STR.IICA1STR.Bits.AD6 #define IICA1_AD7 _IICA1.SameAddr_STR.IICA1STR.Bits.AD7 #define IICA1_AD_1 _IICA1.SameAddr_STR.IICA1STR.MergedBits.grpAD_1 #define IICA1_AD IICA1_AD_1 #define IICA1_AD1_MASK 2 #define IICA1_AD2_MASK 4 #define IICA1_AD3_MASK 8 #define IICA1_AD4_MASK 16 #define IICA1_AD5_MASK 32 #define IICA1_AD6_MASK 64 #define IICA1_AD7_MASK 128 #define IICA1_AD_1_MASK 254 #define IICA1_AD_1_BITNUM 1 /*** IICA - IIC Address Register; Several registers at the same address ***/ union { struct { byte :1; byte AD1 :1; /* Slave Address Bit 1 */ byte AD2 :1; /* Slave Address Bit 2 */ byte AD3 :1; /* Slave Address Bit 3 */ byte AD4 :1; /* Slave Address Bit 4 */ byte AD5 :1; /* Slave Address Bit 5 */ byte AD6 :1; /* Slave Address Bit 6 */ byte AD7 :1; /* Slave Address Bit 7 */ } Bits; struct { byte :1; byte grpAD_1 :7; } MergedBits; } IICASTR; #define IICA _IICA1.Byte #define IICA_AD1 _IICA1.SameAddr_STR.IICASTR.Bits.AD1 #define IICA_AD2 _IICA1.SameAddr_STR.IICASTR.Bits.AD2 #define IICA_AD3 _IICA1.SameAddr_STR.IICASTR.Bits.AD3 #define IICA_AD4 _IICA1.SameAddr_STR.IICASTR.Bits.AD4 #define IICA_AD5 _IICA1.SameAddr_STR.IICASTR.Bits.AD5 #define IICA_AD6 _IICA1.SameAddr_STR.IICASTR.Bits.AD6 #define IICA_AD7 _IICA1.SameAddr_STR.IICASTR.Bits.AD7 #define IICA_AD_1 _IICA1.SameAddr_STR.IICASTR.MergedBits.grpAD_1 #define IICA_AD IICA_AD_1 #define IICA_AD1_MASK 2 #define IICA_AD2_MASK 4 #define IICA_AD3_MASK 8 #define IICA_AD4_MASK 16 #define IICA_AD5_MASK 32 #define IICA_AD6_MASK 64 #define IICA_AD7_MASK 128 #define IICA_AD_1_MASK 254 #define IICA_AD_1_BITNUM 1 } SameAddr_STR; /*Several registers at the same address */ } IICA1STR; extern volatile IICA1STR _IICA1 @0xFFFF8380; /*** IICF - IIC Frequency Divider Register; 0xFFFF8381 ***/ typedef union { byte Byte; struct { byte ICR0 :1; /* IIC Clock Rate Bit 0 */ byte ICR1 :1; /* IIC Clock Rate Bit 1 */ byte ICR2 :1; /* IIC Clock Rate Bit 2 */ byte ICR3 :1; /* IIC Clock Rate Bit 3 */ byte ICR4 :1; /* IIC Clock Rate Bit 4 */ byte ICR5 :1; /* IIC Clock Rate Bit 5 */ byte MULT0 :1; /* Multiplier Factor Bit 0 */ byte MULT1 :1; /* Multiplier Factor Bit 1 */ } Bits; struct { byte grpICR :6; byte grpMULT :2; } MergedBits; } IICFSTR; extern volatile IICFSTR _IICF @0xFFFF8381; #define IICF _IICF.Byte #define IICF_ICR0 _IICF.Bits.ICR0 #define IICF_ICR1 _IICF.Bits.ICR1 #define IICF_ICR2 _IICF.Bits.ICR2 #define IICF_ICR3 _IICF.Bits.ICR3 #define IICF_ICR4 _IICF.Bits.ICR4 #define IICF_ICR5 _IICF.Bits.ICR5 #define IICF_MULT0 _IICF.Bits.MULT0 #define IICF_MULT1 _IICF.Bits.MULT1 #define IICF_ICR _IICF.MergedBits.grpICR #define IICF_MULT _IICF.MergedBits.grpMULT #define IICF_ICR0_MASK 1 #define IICF_ICR1_MASK 2 #define IICF_ICR2_MASK 4 #define IICF_ICR3_MASK 8 #define IICF_ICR4_MASK 16 #define IICF_ICR5_MASK 32 #define IICF_MULT0_MASK 64 #define IICF_MULT1_MASK 128 #define IICF_ICR_MASK 63 #define IICF_ICR_BITNUM 0 #define IICF_MULT_MASK 192 #define IICF_MULT_BITNUM 6 /*** IICC1 - IIC Control Register 1; 0xFFFF8382 ***/ typedef union { byte Byte; union { /* Several registers at the same address */ /*** IICC1 - IIC Control Register 1; Several registers at the same address ***/ union { struct { byte :1; byte :1; byte RSTA :1; /* Repeat START */ byte TXAK :1; /* Transmit Acknowledge Enable */ byte TX :1; /* Transmit Mode Select */ byte MST :1; /* Master Mode Select */ byte IICIE :1; /* IIC Interrupt Enable */ byte IICEN :1; /* IIC Enable */ } Bits; } IICC1STR; #define IICC1 _IICC1.Byte #define IICC1_RSTA _IICC1.SameAddr_STR.IICC1STR.Bits.RSTA #define IICC1_TXAK _IICC1.SameAddr_STR.IICC1STR.Bits.TXAK #define IICC1_TX _IICC1.SameAddr_STR.IICC1STR.Bits.TX #define IICC1_MST _IICC1.SameAddr_STR.IICC1STR.Bits.MST #define IICC1_IICIE _IICC1.SameAddr_STR.IICC1STR.Bits.IICIE #define IICC1_IICEN _IICC1.SameAddr_STR.IICC1STR.Bits.IICEN #define IICC1_RSTA_MASK 4 #define IICC1_TXAK_MASK 8 #define IICC1_TX_MASK 16 #define IICC1_MST_MASK 32 #define IICC1_IICIE_MASK 64 #define IICC1_IICEN_MASK 128 /*** IICC - IIC Control Register; Several registers at the same address ***/ union { struct { byte :1; byte :1; byte RSTA :1; /* Repeat START */ byte TXAK :1; /* Transmit Acknowledge Enable */ byte TX :1; /* Transmit Mode Select */ byte MST :1; /* Master Mode Select */ byte IICIE :1; /* IIC Interrupt Enable */ byte IICEN :1; /* IIC Enable */ } Bits; } IICCSTR; #define IICC _IICC1.Byte #define IICC_RSTA _IICC1.SameAddr_STR.IICCSTR.Bits.RSTA #define IICC_TXAK _IICC1.SameAddr_STR.IICCSTR.Bits.TXAK #define IICC_TX _IICC1.SameAddr_STR.IICCSTR.Bits.TX #define IICC_MST _IICC1.SameAddr_STR.IICCSTR.Bits.MST #define IICC_IICIE _IICC1.SameAddr_STR.IICCSTR.Bits.IICIE #define IICC_IICEN _IICC1.SameAddr_STR.IICCSTR.Bits.IICEN #define IICC_RSTA_MASK 4 #define IICC_TXAK_MASK 8 #define IICC_TX_MASK 16 #define IICC_MST_MASK 32 #define IICC_IICIE_MASK 64 #define IICC_IICEN_MASK 128 } SameAddr_STR; /*Several registers at the same address */ } IICC1STR; extern volatile IICC1STR _IICC1 @0xFFFF8382; /*** IICS - IIC Status Register; 0xFFFF8383 ***/ typedef union { byte Byte; struct { byte RXAK :1; /* Receive Acknowledge */ byte IICIF :1; /* IIC Interrupt Flag */ byte SRW :1; /* Slave Read/Write */ byte :1; byte ARBL :1; /* Arbitration Lost */ byte BUSY :1; /* Bus Busy */ byte IAAS :1; /* Addressed as a Slave */ byte TCF :1; /* Transfer Complete Flag */ } Bits; } IICSSTR; extern volatile IICSSTR _IICS @0xFFFF8383; #define IICS _IICS.Byte #define IICS_RXAK _IICS.Bits.RXAK #define IICS_IICIF _IICS.Bits.IICIF #define IICS_SRW _IICS.Bits.SRW #define IICS_ARBL _IICS.Bits.ARBL #define IICS_BUSY _IICS.Bits.BUSY #define IICS_IAAS _IICS.Bits.IAAS #define IICS_TCF _IICS.Bits.TCF #define IICS_RXAK_MASK 1 #define IICS_IICIF_MASK 2 #define IICS_SRW_MASK 4 #define IICS_ARBL_MASK 16 #define IICS_BUSY_MASK 32 #define IICS_IAAS_MASK 64 #define IICS_TCF_MASK 128 /*** IICD - IIC Data I/O Register; 0xFFFF8384 ***/ typedef union { byte Byte; struct { byte DATA0 :1; /* IIC Data Bit 0 */ byte DATA1 :1; /* IIC Data Bit 1 */ byte DATA2 :1; /* IIC Data Bit 2 */ byte DATA3 :1; /* IIC Data Bit 3 */ byte DATA4 :1; /* IIC Data Bit 4 */ byte DATA5 :1; /* IIC Data Bit 5 */ byte DATA6 :1; /* IIC Data Bit 6 */ byte DATA7 :1; /* IIC Data Bit 7 */ } Bits; } IICDSTR; extern volatile IICDSTR _IICD @0xFFFF8384; #define IICD _IICD.Byte #define IICD_DATA0 _IICD.Bits.DATA0 #define IICD_DATA1 _IICD.Bits.DATA1 #define IICD_DATA2 _IICD.Bits.DATA2 #define IICD_DATA3 _IICD.Bits.DATA3 #define IICD_DATA4 _IICD.Bits.DATA4 #define IICD_DATA5 _IICD.Bits.DATA5 #define IICD_DATA6 _IICD.Bits.DATA6 #define IICD_DATA7 _IICD.Bits.DATA7 #define IICD_DATA0_MASK 1 #define IICD_DATA1_MASK 2 #define IICD_DATA2_MASK 4 #define IICD_DATA3_MASK 8 #define IICD_DATA4_MASK 16 #define IICD_DATA5_MASK 32 #define IICD_DATA6_MASK 64 #define IICD_DATA7_MASK 128 /*** IICC2 - IIC Control Register 2; 0xFFFF8385 ***/ typedef union { byte Byte; struct { byte AD8 :1; /* Slave Address Bit 8 */ byte AD9 :1; /* Slave Address Bit 9 */ byte AD10 :1; /* Slave Address Bit 10 */ byte :1; byte :1; byte :1; byte ADEXT :1; /* Address Extension */ byte GCAEN :1; /* General Call Address Enable */ } Bits; struct { byte grpAD_8 :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } IICC2STR; extern volatile IICC2STR _IICC2 @0xFFFF8385; #define IICC2 _IICC2.Byte #define IICC2_AD8 _IICC2.Bits.AD8 #define IICC2_AD9 _IICC2.Bits.AD9 #define IICC2_AD10 _IICC2.Bits.AD10 #define IICC2_ADEXT _IICC2.Bits.ADEXT #define IICC2_GCAEN _IICC2.Bits.GCAEN #define IICC2_AD_8 _IICC2.MergedBits.grpAD_8 #define IICC2_AD IICC2_AD_8 #define IICC2_AD8_MASK 1 #define IICC2_AD9_MASK 2 #define IICC2_AD10_MASK 4 #define IICC2_ADEXT_MASK 64 #define IICC2_GCAEN_MASK 128 #define IICC2_AD_8_MASK 7 #define IICC2_AD_8_BITNUM 0 /*** IICSMB - SMBus Control and Status Register; 0xFFFF8386 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte SHTF :1; /* SCL High Timeout Flag */ byte SLTF :1; /* SCL Low Timeout Flag */ byte TCKSEL :1; /* Time Out Counter Clock Select */ byte SIICAEN :1; /* Second IIC Address Enable */ byte ALERTEN :1; /* SMBus Alert Response Address Enable */ byte FACK :1; /* Fast NACK/ACK enable */ } Bits; } IICSMBSTR; extern volatile IICSMBSTR _IICSMB @0xFFFF8386; #define IICSMB _IICSMB.Byte #define IICSMB_SHTF _IICSMB.Bits.SHTF #define IICSMB_SLTF _IICSMB.Bits.SLTF #define IICSMB_TCKSEL _IICSMB.Bits.TCKSEL #define IICSMB_SIICAEN _IICSMB.Bits.SIICAEN #define IICSMB_ALERTEN _IICSMB.Bits.ALERTEN #define IICSMB_FACK _IICSMB.Bits.FACK #define IICSMB_SHTF_MASK 4 #define IICSMB_SLTF_MASK 8 #define IICSMB_TCKSEL_MASK 16 #define IICSMB_SIICAEN_MASK 32 #define IICSMB_ALERTEN_MASK 64 #define IICSMB_FACK_MASK 128 /*** IICA2 - IIC Address Register 2; 0xFFFF8387 ***/ typedef union { byte Byte; struct { byte :1; byte SAD1 :1; /* SMBus Address Bit 1 */ byte SAD2 :1; /* SMBus Address Bit 2 */ byte SAD3 :1; /* SMBus Address Bit 3 */ byte SAD4 :1; /* SMBus Address Bit 4 */ byte SAD5 :1; /* SMBus Address Bit 5 */ byte SAD6 :1; /* SMBus Address Bit 6 */ byte SAD7 :1; /* SMBus Address Bit 7 */ } Bits; struct { byte :1; byte grpSAD_1 :7; } MergedBits; } IICA2STR; extern volatile IICA2STR _IICA2 @0xFFFF8387; #define IICA2 _IICA2.Byte #define IICA2_SAD1 _IICA2.Bits.SAD1 #define IICA2_SAD2 _IICA2.Bits.SAD2 #define IICA2_SAD3 _IICA2.Bits.SAD3 #define IICA2_SAD4 _IICA2.Bits.SAD4 #define IICA2_SAD5 _IICA2.Bits.SAD5 #define IICA2_SAD6 _IICA2.Bits.SAD6 #define IICA2_SAD7 _IICA2.Bits.SAD7 #define IICA2_SAD_1 _IICA2.MergedBits.grpSAD_1 #define IICA2_SAD IICA2_SAD_1 #define IICA2_SAD1_MASK 2 #define IICA2_SAD2_MASK 4 #define IICA2_SAD3_MASK 8 #define IICA2_SAD4_MASK 16 #define IICA2_SAD5_MASK 32 #define IICA2_SAD6_MASK 64 #define IICA2_SAD7_MASK 128 #define IICA2_SAD_1_MASK 254 #define IICA2_SAD_1_BITNUM 1 /*** IICSLT - IIC SCL Low Time Out register; 0xFFFF8388 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** IICSLTH - IIC SCL Low Time Out register - High byte; 0xFFFF8388 ***/ union { byte Byte; struct { byte SSLT8 :1; /* SCL Low Time Out Bit 8 */ byte SSLT9 :1; /* SCL Low Time Out Bit 9 */ byte SSLT10 :1; /* SCL Low Time Out Bit 10 */ byte SSLT11 :1; /* SCL Low Time Out Bit 11 */ byte SSLT12 :1; /* SCL Low Time Out Bit 12 */ byte SSLT13 :1; /* SCL Low Time Out Bit 13 */ byte SSLT14 :1; /* SCL Low Time Out Bit 14 */ byte SSLT15 :1; /* SCL Low Time Out Bit 15 */ } Bits; } IICSLTHSTR; #define IICSLTH _IICSLT.Overlap_STR.IICSLTHSTR.Byte #define IICSLTH_SSLT8 _IICSLT.Overlap_STR.IICSLTHSTR.Bits.SSLT8 #define IICSLTH_SSLT9 _IICSLT.Overlap_STR.IICSLTHSTR.Bits.SSLT9 #define IICSLTH_SSLT10 _IICSLT.Overlap_STR.IICSLTHSTR.Bits.SSLT10 #define IICSLTH_SSLT11 _IICSLT.Overlap_STR.IICSLTHSTR.Bits.SSLT11 #define IICSLTH_SSLT12 _IICSLT.Overlap_STR.IICSLTHSTR.Bits.SSLT12 #define IICSLTH_SSLT13 _IICSLT.Overlap_STR.IICSLTHSTR.Bits.SSLT13 #define IICSLTH_SSLT14 _IICSLT.Overlap_STR.IICSLTHSTR.Bits.SSLT14 #define IICSLTH_SSLT15 _IICSLT.Overlap_STR.IICSLTHSTR.Bits.SSLT15 #define IICSLTH_SSLT8_MASK 1 #define IICSLTH_SSLT9_MASK 2 #define IICSLTH_SSLT10_MASK 4 #define IICSLTH_SSLT11_MASK 8 #define IICSLTH_SSLT12_MASK 16 #define IICSLTH_SSLT13_MASK 32 #define IICSLTH_SSLT14_MASK 64 #define IICSLTH_SSLT15_MASK 128 /*** IICSLTL - IIC SCL Low Time Out register - Low byte; 0xFFFF8389 ***/ union { byte Byte; struct { byte SSLT0 :1; /* SCL Low Time Out Bits, bit 0 */ byte SSLT1 :1; /* SCL Low Time Out Bits, bit 1 */ byte SSLT2 :1; /* SCL Low Time Out Bits, bit 2 */ byte SSLT3 :1; /* SCL Low Time Out Bits, bit 3 */ byte SSLT4 :1; /* SCL Low Time Out Bits, bit 4 */ byte SSLT5 :1; /* SCL Low Time Out Bits, bit 5 */ byte SSLT6 :1; /* SCL Low Time Out Bits, bit 6 */ byte SSLT7 :1; /* SCL Low Time Out Bits, bit 7 */ } Bits; } IICSLTLSTR; #define IICSLTL _IICSLT.Overlap_STR.IICSLTLSTR.Byte #define IICSLTL_SSLT0 _IICSLT.Overlap_STR.IICSLTLSTR.Bits.SSLT0 #define IICSLTL_SSLT1 _IICSLT.Overlap_STR.IICSLTLSTR.Bits.SSLT1 #define IICSLTL_SSLT2 _IICSLT.Overlap_STR.IICSLTLSTR.Bits.SSLT2 #define IICSLTL_SSLT3 _IICSLT.Overlap_STR.IICSLTLSTR.Bits.SSLT3 #define IICSLTL_SSLT4 _IICSLT.Overlap_STR.IICSLTLSTR.Bits.SSLT4 #define IICSLTL_SSLT5 _IICSLT.Overlap_STR.IICSLTLSTR.Bits.SSLT5 #define IICSLTL_SSLT6 _IICSLT.Overlap_STR.IICSLTLSTR.Bits.SSLT6 #define IICSLTL_SSLT7 _IICSLT.Overlap_STR.IICSLTLSTR.Bits.SSLT7 #define IICSLTL_SSLT0_MASK 1 #define IICSLTL_SSLT1_MASK 2 #define IICSLTL_SSLT2_MASK 4 #define IICSLTL_SSLT3_MASK 8 #define IICSLTL_SSLT4_MASK 16 #define IICSLTL_SSLT5_MASK 32 #define IICSLTL_SSLT6_MASK 64 #define IICSLTL_SSLT7_MASK 128 } Overlap_STR; struct { word SSLT0 :1; /* SCL Low Time Out Bits, bit 0 */ word SSLT1 :1; /* SCL Low Time Out Bits, bit 1 */ word SSLT2 :1; /* SCL Low Time Out Bits, bit 2 */ word SSLT3 :1; /* SCL Low Time Out Bits, bit 3 */ word SSLT4 :1; /* SCL Low Time Out Bits, bit 4 */ word SSLT5 :1; /* SCL Low Time Out Bits, bit 5 */ word SSLT6 :1; /* SCL Low Time Out Bits, bit 6 */ word SSLT7 :1; /* SCL Low Time Out Bits, bit 7 */ word SSLT8 :1; /* SCL Low Time Out Bits, bit 8 */ word SSLT9 :1; /* SCL Low Time Out Bits, bit 9 */ word SSLT10 :1; /* SCL Low Time Out Bits, bit 10 */ word SSLT11 :1; /* SCL Low Time Out Bits, bit 11 */ word SSLT12 :1; /* SCL Low Time Out Bits, bit 12 */ word SSLT13 :1; /* SCL Low Time Out Bits, bit 13 */ word SSLT14 :1; /* SCL Low Time Out Bits, bit 14 */ word SSLT15 :1; /* SCL Low Time Out Bits, bit 15 */ } Bits; } IICSLTSTR; extern volatile IICSLTSTR _IICSLT @0xFFFF8388; #define IICSLT _IICSLT.Word #define IICSLT_SSLT0 _IICSLT.Bits.SSLT0 #define IICSLT_SSLT1 _IICSLT.Bits.SSLT1 #define IICSLT_SSLT2 _IICSLT.Bits.SSLT2 #define IICSLT_SSLT3 _IICSLT.Bits.SSLT3 #define IICSLT_SSLT4 _IICSLT.Bits.SSLT4 #define IICSLT_SSLT5 _IICSLT.Bits.SSLT5 #define IICSLT_SSLT6 _IICSLT.Bits.SSLT6 #define IICSLT_SSLT7 _IICSLT.Bits.SSLT7 #define IICSLT_SSLT8 _IICSLT.Bits.SSLT8 #define IICSLT_SSLT9 _IICSLT.Bits.SSLT9 #define IICSLT_SSLT10 _IICSLT.Bits.SSLT10 #define IICSLT_SSLT11 _IICSLT.Bits.SSLT11 #define IICSLT_SSLT12 _IICSLT.Bits.SSLT12 #define IICSLT_SSLT13 _IICSLT.Bits.SSLT13 #define IICSLT_SSLT14 _IICSLT.Bits.SSLT14 #define IICSLT_SSLT15 _IICSLT.Bits.SSLT15 #define IICSLT_SSLT0_MASK 1 #define IICSLT_SSLT1_MASK 2 #define IICSLT_SSLT2_MASK 4 #define IICSLT_SSLT3_MASK 8 #define IICSLT_SSLT4_MASK 16 #define IICSLT_SSLT5_MASK 32 #define IICSLT_SSLT6_MASK 64 #define IICSLT_SSLT7_MASK 128 #define IICSLT_SSLT8_MASK 256 #define IICSLT_SSLT9_MASK 512 #define IICSLT_SSLT10_MASK 1024 #define IICSLT_SSLT11_MASK 2048 #define IICSLT_SSLT12_MASK 4096 #define IICSLT_SSLT13_MASK 8192 #define IICSLT_SSLT14_MASK 16384 #define IICSLT_SSLT15_MASK 32768 /*** IICFLT - IIC Filter register; 0xFFFF838A ***/ typedef union { byte Byte; struct { byte FLT0 :1; /* Filter value bit 0 */ byte FLT1 :1; /* Filter value bit 1 */ byte FLT2 :1; /* Filter value bit 2 */ byte FLT3 :1; /* Filter value bit 3 */ byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpFLT :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } IICFLTSTR; extern volatile IICFLTSTR _IICFLT @0xFFFF838A; #define IICFLT _IICFLT.Byte #define IICFLT_FLT0 _IICFLT.Bits.FLT0 #define IICFLT_FLT1 _IICFLT.Bits.FLT1 #define IICFLT_FLT2 _IICFLT.Bits.FLT2 #define IICFLT_FLT3 _IICFLT.Bits.FLT3 #define IICFLT_FLT _IICFLT.MergedBits.grpFLT #define IICFLT_FLT0_MASK 1 #define IICFLT_FLT1_MASK 2 #define IICFLT_FLT2_MASK 4 #define IICFLT_FLT3_MASK 8 #define IICFLT_FLT_MASK 15 #define IICFLT_FLT_BITNUM 0 /*** VREFTRM - VREF Trim Register; 0xFFFF83C0 ***/ typedef union { byte Byte; struct { byte TRM0 :1; /* Trim Bits, bit 0 */ byte TRM1 :1; /* Trim Bits, bit 1 */ byte TRM2 :1; /* Trim Bits, bit 2 */ byte TRM3 :1; /* Trim Bits, bit 3 */ byte TRM4 :1; /* Trim Bits, bit 4 */ byte TRM5 :1; /* Trim Bits, bit 5 */ byte TRM6 :1; /* Trim Bits, bit 6 */ byte TRM7 :1; /* Trim Bits, bit 7 */ } Bits; } VREFTRMSTR; extern volatile VREFTRMSTR _VREFTRM @0xFFFF83C0; #define VREFTRM _VREFTRM.Byte #define VREFTRM_TRM0 _VREFTRM.Bits.TRM0 #define VREFTRM_TRM1 _VREFTRM.Bits.TRM1 #define VREFTRM_TRM2 _VREFTRM.Bits.TRM2 #define VREFTRM_TRM3 _VREFTRM.Bits.TRM3 #define VREFTRM_TRM4 _VREFTRM.Bits.TRM4 #define VREFTRM_TRM5 _VREFTRM.Bits.TRM5 #define VREFTRM_TRM6 _VREFTRM.Bits.TRM6 #define VREFTRM_TRM7 _VREFTRM.Bits.TRM7 #define VREFTRM_TRM0_MASK 1 #define VREFTRM_TRM1_MASK 2 #define VREFTRM_TRM2_MASK 4 #define VREFTRM_TRM3_MASK 8 #define VREFTRM_TRM4_MASK 16 #define VREFTRM_TRM5_MASK 32 #define VREFTRM_TRM6_MASK 64 #define VREFTRM_TRM7_MASK 128 /*** VREFSC - VREF Control Register; 0xFFFF83C1 ***/ typedef union { byte Byte; struct { byte MODE0 :1; /* Mode selection, bit 0 */ byte MODE1 :1; /* Mode selection, bit 1 */ byte VREFST :1; /* Internal Voltage Reference Stable */ byte :1; byte :1; byte :1; byte :1; byte VREFEN :1; /* Internal Voltage Reference Enable */ } Bits; struct { byte grpMODE :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } VREFSCSTR; extern volatile VREFSCSTR _VREFSC @0xFFFF83C1; #define VREFSC _VREFSC.Byte #define VREFSC_MODE0 _VREFSC.Bits.MODE0 #define VREFSC_MODE1 _VREFSC.Bits.MODE1 #define VREFSC_VREFST _VREFSC.Bits.VREFST #define VREFSC_VREFEN _VREFSC.Bits.VREFEN #define VREFSC_MODE _VREFSC.MergedBits.grpMODE #define VREFSC_MODE0_MASK 1 #define VREFSC_MODE1_MASK 2 #define VREFSC_VREFST_MASK 4 #define VREFSC_VREFEN_MASK 128 #define VREFSC_MODE_MASK 3 #define VREFSC_MODE_BITNUM 0 /*** ADC1SC1A - Status and Control Register 1A; 0xFFFF8400 ***/ typedef union { byte Byte; struct { byte ADCHA0 :1; /* Input Channel Select Bit 0 */ byte ADCHA1 :1; /* Input Channel Select Bit 1 */ byte ADCHA2 :1; /* Input Channel Select Bit 2 */ byte ADCHA3 :1; /* Input Channel Select Bit 3 */ byte ADCHA4 :1; /* Input Channel Select Bit 4 */ byte DIFFA :1; /* Differential Mode Enable - DIFFA configures the ADC to operate in differential mode */ byte AIENA :1; /* Interrupt Enable - AIENA enables conversion complete interrupts. When COCOA becomes set while the respective AIENA is high, an interrupt is asserted */ byte COCOA :1; /* Conversion Complete Flag */ } Bits; struct { byte grpADCHA :5; byte grpDIFFx :1; byte grpAIENx :1; byte grpCOCOx :1; } MergedBits; } ADC1SC1ASTR; extern volatile ADC1SC1ASTR _ADC1SC1A @0xFFFF8400; #define ADC1SC1A _ADC1SC1A.Byte #define ADC1SC1A_ADCHA0 _ADC1SC1A.Bits.ADCHA0 #define ADC1SC1A_ADCHA1 _ADC1SC1A.Bits.ADCHA1 #define ADC1SC1A_ADCHA2 _ADC1SC1A.Bits.ADCHA2 #define ADC1SC1A_ADCHA3 _ADC1SC1A.Bits.ADCHA3 #define ADC1SC1A_ADCHA4 _ADC1SC1A.Bits.ADCHA4 #define ADC1SC1A_DIFFA _ADC1SC1A.Bits.DIFFA #define ADC1SC1A_AIENA _ADC1SC1A.Bits.AIENA #define ADC1SC1A_COCOA _ADC1SC1A.Bits.COCOA #define ADC1SC1A_ADCHA _ADC1SC1A.MergedBits.grpADCHA #define ADC1SC1A_ADCHA0_MASK 1 #define ADC1SC1A_ADCHA1_MASK 2 #define ADC1SC1A_ADCHA2_MASK 4 #define ADC1SC1A_ADCHA3_MASK 8 #define ADC1SC1A_ADCHA4_MASK 16 #define ADC1SC1A_DIFFA_MASK 32 #define ADC1SC1A_AIENA_MASK 64 #define ADC1SC1A_COCOA_MASK 128 #define ADC1SC1A_ADCHA_MASK 31 #define ADC1SC1A_ADCHA_BITNUM 0 /*** ADC1SC1B - Status and Control Register 1B; 0xFFFF8401 ***/ typedef union { byte Byte; struct { byte ADCHB0 :1; /* Input Channel Select Bit 0 */ byte ADCHB1 :1; /* Input Channel Select Bit 1 */ byte ADCHB2 :1; /* Input Channel Select Bit 2 */ byte ADCHB3 :1; /* Input Channel Select Bit 3 */ byte ADCHB4 :1; /* Input Channel Select Bit 4 */ byte DIFFB :1; /* Differential Mode Enable - DIFFB configures the ADC to operate in differential mode */ byte AIENB :1; /* Interrupt Enable - AIENB enables conversion complete interrupts. When COCOB becomes set while the respective AIENB is high, an interrupt is asserted */ byte COCOB :1; /* Conversion Complete Flag */ } Bits; struct { byte grpADCHB :5; byte :1; byte :1; byte :1; } MergedBits; } ADC1SC1BSTR; extern volatile ADC1SC1BSTR _ADC1SC1B @0xFFFF8401; #define ADC1SC1B _ADC1SC1B.Byte #define ADC1SC1B_ADCHB0 _ADC1SC1B.Bits.ADCHB0 #define ADC1SC1B_ADCHB1 _ADC1SC1B.Bits.ADCHB1 #define ADC1SC1B_ADCHB2 _ADC1SC1B.Bits.ADCHB2 #define ADC1SC1B_ADCHB3 _ADC1SC1B.Bits.ADCHB3 #define ADC1SC1B_ADCHB4 _ADC1SC1B.Bits.ADCHB4 #define ADC1SC1B_DIFFB _ADC1SC1B.Bits.DIFFB #define ADC1SC1B_AIENB _ADC1SC1B.Bits.AIENB #define ADC1SC1B_COCOB _ADC1SC1B.Bits.COCOB #define ADC1SC1B_ADCHB _ADC1SC1B.MergedBits.grpADCHB #define ADC1SC1B_ADCHB0_MASK 1 #define ADC1SC1B_ADCHB1_MASK 2 #define ADC1SC1B_ADCHB2_MASK 4 #define ADC1SC1B_ADCHB3_MASK 8 #define ADC1SC1B_ADCHB4_MASK 16 #define ADC1SC1B_DIFFB_MASK 32 #define ADC1SC1B_AIENB_MASK 64 #define ADC1SC1B_COCOB_MASK 128 #define ADC1SC1B_ADCHB_MASK 31 #define ADC1SC1B_ADCHB_BITNUM 0 /*** ADC1CFG1 - Configuration Register 1; 0xFFFF8402 ***/ typedef union { byte Byte; struct { byte ADICLK0 :1; /* Input Clock Select Bit 0 */ byte ADICLK1 :1; /* Input Clock Select Bit 1 */ byte MODE0 :1; /* Conversion Mode Selection Bit 0 */ byte MODE1 :1; /* Conversion Mode Selection Bit 1 */ byte ADLSMP :1; /* Long Sample Time Configuration */ byte ADIV0 :1; /* Clock Divide Select Bit 0 */ byte ADIV1 :1; /* Clock Divide Select Bit 1 */ byte ADLPC :1; /* Low Power Configuration */ } Bits; struct { byte grpADICLK :2; byte grpMODE :2; byte :1; byte grpADIV :2; byte :1; } MergedBits; } ADC1CFG1STR; extern volatile ADC1CFG1STR _ADC1CFG1 @0xFFFF8402; #define ADC1CFG1 _ADC1CFG1.Byte #define ADC1CFG1_ADICLK0 _ADC1CFG1.Bits.ADICLK0 #define ADC1CFG1_ADICLK1 _ADC1CFG1.Bits.ADICLK1 #define ADC1CFG1_MODE0 _ADC1CFG1.Bits.MODE0 #define ADC1CFG1_MODE1 _ADC1CFG1.Bits.MODE1 #define ADC1CFG1_ADLSMP _ADC1CFG1.Bits.ADLSMP #define ADC1CFG1_ADIV0 _ADC1CFG1.Bits.ADIV0 #define ADC1CFG1_ADIV1 _ADC1CFG1.Bits.ADIV1 #define ADC1CFG1_ADLPC _ADC1CFG1.Bits.ADLPC #define ADC1CFG1_ADICLK _ADC1CFG1.MergedBits.grpADICLK #define ADC1CFG1_MODE _ADC1CFG1.MergedBits.grpMODE #define ADC1CFG1_ADIV _ADC1CFG1.MergedBits.grpADIV #define ADC1CFG1_ADICLK0_MASK 1 #define ADC1CFG1_ADICLK1_MASK 2 #define ADC1CFG1_MODE0_MASK 4 #define ADC1CFG1_MODE1_MASK 8 #define ADC1CFG1_ADLSMP_MASK 16 #define ADC1CFG1_ADIV0_MASK 32 #define ADC1CFG1_ADIV1_MASK 64 #define ADC1CFG1_ADLPC_MASK 128 #define ADC1CFG1_ADICLK_MASK 3 #define ADC1CFG1_ADICLK_BITNUM 0 #define ADC1CFG1_MODE_MASK 12 #define ADC1CFG1_MODE_BITNUM 2 #define ADC1CFG1_ADIV_MASK 96 #define ADC1CFG1_ADIV_BITNUM 5 /*** ADC1CFG2 - Configuration Register 2; 0xFFFF8403 ***/ typedef union { byte Byte; struct { byte ADLSTS0 :1; /* Long Sample Time Select Bit 0 */ byte ADLSTS1 :1; /* Long Sample Time Select Bit 1 */ byte ADHSC :1; /* High Speed Configuration */ byte ADACKEN :1; /* Asynchronous Clock Output Enable */ byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpADLSTS :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ADC1CFG2STR; extern volatile ADC1CFG2STR _ADC1CFG2 @0xFFFF8403; #define ADC1CFG2 _ADC1CFG2.Byte #define ADC1CFG2_ADLSTS0 _ADC1CFG2.Bits.ADLSTS0 #define ADC1CFG2_ADLSTS1 _ADC1CFG2.Bits.ADLSTS1 #define ADC1CFG2_ADHSC _ADC1CFG2.Bits.ADHSC #define ADC1CFG2_ADACKEN _ADC1CFG2.Bits.ADACKEN #define ADC1CFG2_ADLSTS _ADC1CFG2.MergedBits.grpADLSTS #define ADC1CFG2_ADLSTS0_MASK 1 #define ADC1CFG2_ADLSTS1_MASK 2 #define ADC1CFG2_ADHSC_MASK 4 #define ADC1CFG2_ADACKEN_MASK 8 #define ADC1CFG2_ADLSTS_MASK 3 #define ADC1CFG2_ADLSTS_BITNUM 0 /*** ADC1RA - Data Result Register A; 0xFFFF8404 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC1RHA - Data Result High Register A; 0xFFFF8404 ***/ union { byte Byte; struct { byte D8 :1; /* ADC Result Data Bit 8 */ byte D9 :1; /* ADC Result Data Bit 9 */ byte D10 :1; /* ADC Result Data Bit 10 */ byte D11 :1; /* ADC Result Data Bit 11 */ byte D12 :1; /* ADC Result Data Bit 12 */ byte D13 :1; /* ADC Result Data Bit 13 */ byte D14 :1; /* ADC Result Data Bit 14 */ byte D15 :1; /* ADC Result Data Bit 15 */ } Bits; } ADC1RHASTR; #define ADC1RHA _ADC1RA.Overlap_STR.ADC1RHASTR.Byte #define ADC1RHA_D8 _ADC1RA.Overlap_STR.ADC1RHASTR.Bits.D8 #define ADC1RHA_D9 _ADC1RA.Overlap_STR.ADC1RHASTR.Bits.D9 #define ADC1RHA_D10 _ADC1RA.Overlap_STR.ADC1RHASTR.Bits.D10 #define ADC1RHA_D11 _ADC1RA.Overlap_STR.ADC1RHASTR.Bits.D11 #define ADC1RHA_D12 _ADC1RA.Overlap_STR.ADC1RHASTR.Bits.D12 #define ADC1RHA_D13 _ADC1RA.Overlap_STR.ADC1RHASTR.Bits.D13 #define ADC1RHA_D14 _ADC1RA.Overlap_STR.ADC1RHASTR.Bits.D14 #define ADC1RHA_D15 _ADC1RA.Overlap_STR.ADC1RHASTR.Bits.D15 #define ADC1RHA_D8_MASK 1 #define ADC1RHA_D9_MASK 2 #define ADC1RHA_D10_MASK 4 #define ADC1RHA_D11_MASK 8 #define ADC1RHA_D12_MASK 16 #define ADC1RHA_D13_MASK 32 #define ADC1RHA_D14_MASK 64 #define ADC1RHA_D15_MASK 128 /*** ADC1RLA - Data Result Low Register A; 0xFFFF8405 ***/ union { byte Byte; struct { byte D0 :1; /* ADC Result Data Bit 0 */ byte D1 :1; /* ADC Result Data Bit 1 */ byte D2 :1; /* ADC Result Data Bit 2 */ byte D3 :1; /* ADC Result Data Bit 3 */ byte D4 :1; /* ADC Result Data Bit 4 */ byte D5 :1; /* ADC Result Data Bit 5 */ byte D6 :1; /* ADC Result Data Bit 6 */ byte D7 :1; /* ADC Result Data Bit 7 */ } Bits; } ADC1RLASTR; #define ADC1RLA _ADC1RA.Overlap_STR.ADC1RLASTR.Byte #define ADC1RLA_D0 _ADC1RA.Overlap_STR.ADC1RLASTR.Bits.D0 #define ADC1RLA_D1 _ADC1RA.Overlap_STR.ADC1RLASTR.Bits.D1 #define ADC1RLA_D2 _ADC1RA.Overlap_STR.ADC1RLASTR.Bits.D2 #define ADC1RLA_D3 _ADC1RA.Overlap_STR.ADC1RLASTR.Bits.D3 #define ADC1RLA_D4 _ADC1RA.Overlap_STR.ADC1RLASTR.Bits.D4 #define ADC1RLA_D5 _ADC1RA.Overlap_STR.ADC1RLASTR.Bits.D5 #define ADC1RLA_D6 _ADC1RA.Overlap_STR.ADC1RLASTR.Bits.D6 #define ADC1RLA_D7 _ADC1RA.Overlap_STR.ADC1RLASTR.Bits.D7 #define ADC1RLA_D0_MASK 1 #define ADC1RLA_D1_MASK 2 #define ADC1RLA_D2_MASK 4 #define ADC1RLA_D3_MASK 8 #define ADC1RLA_D4_MASK 16 #define ADC1RLA_D5_MASK 32 #define ADC1RLA_D6_MASK 64 #define ADC1RLA_D7_MASK 128 } Overlap_STR; struct { word D0 :1; /* ADC Result Data Bit 0 */ word D1 :1; /* ADC Result Data Bit 1 */ word D2 :1; /* ADC Result Data Bit 2 */ word D3 :1; /* ADC Result Data Bit 3 */ word D4 :1; /* ADC Result Data Bit 4 */ word D5 :1; /* ADC Result Data Bit 5 */ word D6 :1; /* ADC Result Data Bit 6 */ word D7 :1; /* ADC Result Data Bit 7 */ word D8 :1; /* ADC Result Data Bit 8 */ word D9 :1; /* ADC Result Data Bit 9 */ word D10 :1; /* ADC Result Data Bit 10 */ word D11 :1; /* ADC Result Data Bit 11 */ word D12 :1; /* ADC Result Data Bit 12 */ word D13 :1; /* ADC Result Data Bit 13 */ word D14 :1; /* ADC Result Data Bit 14 */ word D15 :1; /* ADC Result Data Bit 15 */ } Bits; } ADC1RASTR; extern volatile ADC1RASTR _ADC1RA @0xFFFF8404; #define ADC1RA _ADC1RA.Word #define ADC1RA_D0 _ADC1RA.Bits.D0 #define ADC1RA_D1 _ADC1RA.Bits.D1 #define ADC1RA_D2 _ADC1RA.Bits.D2 #define ADC1RA_D3 _ADC1RA.Bits.D3 #define ADC1RA_D4 _ADC1RA.Bits.D4 #define ADC1RA_D5 _ADC1RA.Bits.D5 #define ADC1RA_D6 _ADC1RA.Bits.D6 #define ADC1RA_D7 _ADC1RA.Bits.D7 #define ADC1RA_D8 _ADC1RA.Bits.D8 #define ADC1RA_D9 _ADC1RA.Bits.D9 #define ADC1RA_D10 _ADC1RA.Bits.D10 #define ADC1RA_D11 _ADC1RA.Bits.D11 #define ADC1RA_D12 _ADC1RA.Bits.D12 #define ADC1RA_D13 _ADC1RA.Bits.D13 #define ADC1RA_D14 _ADC1RA.Bits.D14 #define ADC1RA_D15 _ADC1RA.Bits.D15 #define ADC1RA_D0_MASK 1 #define ADC1RA_D1_MASK 2 #define ADC1RA_D2_MASK 4 #define ADC1RA_D3_MASK 8 #define ADC1RA_D4_MASK 16 #define ADC1RA_D5_MASK 32 #define ADC1RA_D6_MASK 64 #define ADC1RA_D7_MASK 128 #define ADC1RA_D8_MASK 256 #define ADC1RA_D9_MASK 512 #define ADC1RA_D10_MASK 1024 #define ADC1RA_D11_MASK 2048 #define ADC1RA_D12_MASK 4096 #define ADC1RA_D13_MASK 8192 #define ADC1RA_D14_MASK 16384 #define ADC1RA_D15_MASK 32768 /*** ADC1RB - Data Result Register B; 0xFFFF8406 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC1RHB - Data Result High Register B; 0xFFFF8406 ***/ union { byte Byte; struct { byte D8 :1; /* ADC Result Data Bit 8 */ byte D9 :1; /* ADC Result Data Bit 9 */ byte D10 :1; /* ADC Result Data Bit 10 */ byte D11 :1; /* ADC Result Data Bit 11 */ byte D12 :1; /* ADC Result Data Bit 12 */ byte D13 :1; /* ADC Result Data Bit 13 */ byte D14 :1; /* ADC Result Data Bit 14 */ byte D15 :1; /* ADC Result Data Bit 15 */ } Bits; } ADC1RHBSTR; #define ADC1RHB _ADC1RB.Overlap_STR.ADC1RHBSTR.Byte #define ADC1RHB_D8 _ADC1RB.Overlap_STR.ADC1RHBSTR.Bits.D8 #define ADC1RHB_D9 _ADC1RB.Overlap_STR.ADC1RHBSTR.Bits.D9 #define ADC1RHB_D10 _ADC1RB.Overlap_STR.ADC1RHBSTR.Bits.D10 #define ADC1RHB_D11 _ADC1RB.Overlap_STR.ADC1RHBSTR.Bits.D11 #define ADC1RHB_D12 _ADC1RB.Overlap_STR.ADC1RHBSTR.Bits.D12 #define ADC1RHB_D13 _ADC1RB.Overlap_STR.ADC1RHBSTR.Bits.D13 #define ADC1RHB_D14 _ADC1RB.Overlap_STR.ADC1RHBSTR.Bits.D14 #define ADC1RHB_D15 _ADC1RB.Overlap_STR.ADC1RHBSTR.Bits.D15 #define ADC1RHB_D8_MASK 1 #define ADC1RHB_D9_MASK 2 #define ADC1RHB_D10_MASK 4 #define ADC1RHB_D11_MASK 8 #define ADC1RHB_D12_MASK 16 #define ADC1RHB_D13_MASK 32 #define ADC1RHB_D14_MASK 64 #define ADC1RHB_D15_MASK 128 /*** ADC1RLB - Data Result Low Register B; 0xFFFF8407 ***/ union { byte Byte; struct { byte D0 :1; /* ADC Result Data Bit 0 */ byte D1 :1; /* ADC Result Data Bit 1 */ byte D2 :1; /* ADC Result Data Bit 2 */ byte D3 :1; /* ADC Result Data Bit 3 */ byte D4 :1; /* ADC Result Data Bit 4 */ byte D5 :1; /* ADC Result Data Bit 5 */ byte D6 :1; /* ADC Result Data Bit 6 */ byte D7 :1; /* ADC Result Data Bit 7 */ } Bits; } ADC1RLBSTR; #define ADC1RLB _ADC1RB.Overlap_STR.ADC1RLBSTR.Byte #define ADC1RLB_D0 _ADC1RB.Overlap_STR.ADC1RLBSTR.Bits.D0 #define ADC1RLB_D1 _ADC1RB.Overlap_STR.ADC1RLBSTR.Bits.D1 #define ADC1RLB_D2 _ADC1RB.Overlap_STR.ADC1RLBSTR.Bits.D2 #define ADC1RLB_D3 _ADC1RB.Overlap_STR.ADC1RLBSTR.Bits.D3 #define ADC1RLB_D4 _ADC1RB.Overlap_STR.ADC1RLBSTR.Bits.D4 #define ADC1RLB_D5 _ADC1RB.Overlap_STR.ADC1RLBSTR.Bits.D5 #define ADC1RLB_D6 _ADC1RB.Overlap_STR.ADC1RLBSTR.Bits.D6 #define ADC1RLB_D7 _ADC1RB.Overlap_STR.ADC1RLBSTR.Bits.D7 #define ADC1RLB_D0_MASK 1 #define ADC1RLB_D1_MASK 2 #define ADC1RLB_D2_MASK 4 #define ADC1RLB_D3_MASK 8 #define ADC1RLB_D4_MASK 16 #define ADC1RLB_D5_MASK 32 #define ADC1RLB_D6_MASK 64 #define ADC1RLB_D7_MASK 128 } Overlap_STR; struct { word D0 :1; /* ADC Result Data Bit 0 */ word D1 :1; /* ADC Result Data Bit 1 */ word D2 :1; /* ADC Result Data Bit 2 */ word D3 :1; /* ADC Result Data Bit 3 */ word D4 :1; /* ADC Result Data Bit 4 */ word D5 :1; /* ADC Result Data Bit 5 */ word D6 :1; /* ADC Result Data Bit 6 */ word D7 :1; /* ADC Result Data Bit 7 */ word D8 :1; /* ADC Result Data Bit 8 */ word D9 :1; /* ADC Result Data Bit 9 */ word D10 :1; /* ADC Result Data Bit 10 */ word D11 :1; /* ADC Result Data Bit 11 */ word D12 :1; /* ADC Result Data Bit 12 */ word D13 :1; /* ADC Result Data Bit 13 */ word D14 :1; /* ADC Result Data Bit 14 */ word D15 :1; /* ADC Result Data Bit 15 */ } Bits; } ADC1RBSTR; extern volatile ADC1RBSTR _ADC1RB @0xFFFF8406; #define ADC1RB _ADC1RB.Word #define ADC1RB_D0 _ADC1RB.Bits.D0 #define ADC1RB_D1 _ADC1RB.Bits.D1 #define ADC1RB_D2 _ADC1RB.Bits.D2 #define ADC1RB_D3 _ADC1RB.Bits.D3 #define ADC1RB_D4 _ADC1RB.Bits.D4 #define ADC1RB_D5 _ADC1RB.Bits.D5 #define ADC1RB_D6 _ADC1RB.Bits.D6 #define ADC1RB_D7 _ADC1RB.Bits.D7 #define ADC1RB_D8 _ADC1RB.Bits.D8 #define ADC1RB_D9 _ADC1RB.Bits.D9 #define ADC1RB_D10 _ADC1RB.Bits.D10 #define ADC1RB_D11 _ADC1RB.Bits.D11 #define ADC1RB_D12 _ADC1RB.Bits.D12 #define ADC1RB_D13 _ADC1RB.Bits.D13 #define ADC1RB_D14 _ADC1RB.Bits.D14 #define ADC1RB_D15 _ADC1RB.Bits.D15 #define ADC1RB_D0_MASK 1 #define ADC1RB_D1_MASK 2 #define ADC1RB_D2_MASK 4 #define ADC1RB_D3_MASK 8 #define ADC1RB_D4_MASK 16 #define ADC1RB_D5_MASK 32 #define ADC1RB_D6_MASK 64 #define ADC1RB_D7_MASK 128 #define ADC1RB_D8_MASK 256 #define ADC1RB_D9_MASK 512 #define ADC1RB_D10_MASK 1024 #define ADC1RB_D11_MASK 2048 #define ADC1RB_D12_MASK 4096 #define ADC1RB_D13_MASK 8192 #define ADC1RB_D14_MASK 16384 #define ADC1RB_D15_MASK 32768 /*** ADC1CV1 - Compare Value 1 Register; 0xFFFF8408 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC1CV1H - Compare Value 1 High Register; 0xFFFF8408 ***/ union { byte Byte; struct { byte CV18 :1; /* Compare Function Value 8 */ byte CV19 :1; /* Compare Function Value 9 */ byte CV110 :1; /* Compare Function Value 10 */ byte CV111 :1; /* Compare Function Value 11 */ byte CV112 :1; /* Compare Function Value 12 */ byte CV113 :1; /* Compare Function Value 13 */ byte CV114 :1; /* Compare Function Value 14 */ byte CV115 :1; /* Compare Function Value 15 */ } Bits; struct { byte grpCV_18 :2; byte grpCV1_10 :6; } MergedBits; } ADC1CV1HSTR; #define ADC1CV1H _ADC1CV1.Overlap_STR.ADC1CV1HSTR.Byte #define ADC1CV1H_CV18 _ADC1CV1.Overlap_STR.ADC1CV1HSTR.Bits.CV18 #define ADC1CV1H_CV19 _ADC1CV1.Overlap_STR.ADC1CV1HSTR.Bits.CV19 #define ADC1CV1H_CV110 _ADC1CV1.Overlap_STR.ADC1CV1HSTR.Bits.CV110 #define ADC1CV1H_CV111 _ADC1CV1.Overlap_STR.ADC1CV1HSTR.Bits.CV111 #define ADC1CV1H_CV112 _ADC1CV1.Overlap_STR.ADC1CV1HSTR.Bits.CV112 #define ADC1CV1H_CV113 _ADC1CV1.Overlap_STR.ADC1CV1HSTR.Bits.CV113 #define ADC1CV1H_CV114 _ADC1CV1.Overlap_STR.ADC1CV1HSTR.Bits.CV114 #define ADC1CV1H_CV115 _ADC1CV1.Overlap_STR.ADC1CV1HSTR.Bits.CV115 #define ADC1CV1H_CV_18 _ADC1CV1.Overlap_STR.ADC1CV1HSTR.MergedBits.grpCV_18 #define ADC1CV1H_CV1_10 _ADC1CV1.Overlap_STR.ADC1CV1HSTR.MergedBits.grpCV1_10 #define ADC1CV1H_CV ADC1CV1H_CV_18 #define ADC1CV1H_CV1 ADC1CV1H_CV1_10 #define ADC1CV1H_CV18_MASK 1 #define ADC1CV1H_CV19_MASK 2 #define ADC1CV1H_CV110_MASK 4 #define ADC1CV1H_CV111_MASK 8 #define ADC1CV1H_CV112_MASK 16 #define ADC1CV1H_CV113_MASK 32 #define ADC1CV1H_CV114_MASK 64 #define ADC1CV1H_CV115_MASK 128 #define ADC1CV1H_CV_18_MASK 3 #define ADC1CV1H_CV_18_BITNUM 0 #define ADC1CV1H_CV1_10_MASK 252 #define ADC1CV1H_CV1_10_BITNUM 2 /*** ADC1CV1L - Compare Value 1 Low Register; 0xFFFF8409 ***/ union { byte Byte; struct { byte CV10 :1; /* Compare Function Value 0 */ byte CV11 :1; /* Compare Function Value 1 */ byte CV12 :1; /* Compare Function Value 2 */ byte CV13 :1; /* Compare Function Value 3 */ byte CV14 :1; /* Compare Function Value 4 */ byte CV15 :1; /* Compare Function Value 5 */ byte CV16 :1; /* Compare Function Value 6 */ byte CV17 :1; /* Compare Function Value 7 */ } Bits; } ADC1CV1LSTR; #define ADC1CV1L _ADC1CV1.Overlap_STR.ADC1CV1LSTR.Byte #define ADC1CV1L_CV10 _ADC1CV1.Overlap_STR.ADC1CV1LSTR.Bits.CV10 #define ADC1CV1L_CV11 _ADC1CV1.Overlap_STR.ADC1CV1LSTR.Bits.CV11 #define ADC1CV1L_CV12 _ADC1CV1.Overlap_STR.ADC1CV1LSTR.Bits.CV12 #define ADC1CV1L_CV13 _ADC1CV1.Overlap_STR.ADC1CV1LSTR.Bits.CV13 #define ADC1CV1L_CV14 _ADC1CV1.Overlap_STR.ADC1CV1LSTR.Bits.CV14 #define ADC1CV1L_CV15 _ADC1CV1.Overlap_STR.ADC1CV1LSTR.Bits.CV15 #define ADC1CV1L_CV16 _ADC1CV1.Overlap_STR.ADC1CV1LSTR.Bits.CV16 #define ADC1CV1L_CV17 _ADC1CV1.Overlap_STR.ADC1CV1LSTR.Bits.CV17 #define ADC1CV1L_CV10_MASK 1 #define ADC1CV1L_CV11_MASK 2 #define ADC1CV1L_CV12_MASK 4 #define ADC1CV1L_CV13_MASK 8 #define ADC1CV1L_CV14_MASK 16 #define ADC1CV1L_CV15_MASK 32 #define ADC1CV1L_CV16_MASK 64 #define ADC1CV1L_CV17_MASK 128 } Overlap_STR; struct { word CV10 :1; /* Compare Function Value 0 */ word CV11 :1; /* Compare Function Value 1 */ word CV12 :1; /* Compare Function Value 2 */ word CV13 :1; /* Compare Function Value 3 */ word CV14 :1; /* Compare Function Value 4 */ word CV15 :1; /* Compare Function Value 5 */ word CV16 :1; /* Compare Function Value 6 */ word CV17 :1; /* Compare Function Value 7 */ word CV18 :1; /* Compare Function Value 8 */ word CV19 :1; /* Compare Function Value 9 */ word CV110 :1; /* Compare Function Value 10 */ word CV111 :1; /* Compare Function Value 11 */ word CV112 :1; /* Compare Function Value 12 */ word CV113 :1; /* Compare Function Value 13 */ word CV114 :1; /* Compare Function Value 14 */ word CV115 :1; /* Compare Function Value 15 */ } Bits; struct { word grpCV_10 :10; word grpCV1_10 :6; } MergedBits; } ADC1CV1STR; extern volatile ADC1CV1STR _ADC1CV1 @0xFFFF8408; #define ADC1CV1 _ADC1CV1.Word #define ADC1CV1_CV10 _ADC1CV1.Bits.CV10 #define ADC1CV1_CV11 _ADC1CV1.Bits.CV11 #define ADC1CV1_CV12 _ADC1CV1.Bits.CV12 #define ADC1CV1_CV13 _ADC1CV1.Bits.CV13 #define ADC1CV1_CV14 _ADC1CV1.Bits.CV14 #define ADC1CV1_CV15 _ADC1CV1.Bits.CV15 #define ADC1CV1_CV16 _ADC1CV1.Bits.CV16 #define ADC1CV1_CV17 _ADC1CV1.Bits.CV17 #define ADC1CV1_CV18 _ADC1CV1.Bits.CV18 #define ADC1CV1_CV19 _ADC1CV1.Bits.CV19 #define ADC1CV1_CV110 _ADC1CV1.Bits.CV110 #define ADC1CV1_CV111 _ADC1CV1.Bits.CV111 #define ADC1CV1_CV112 _ADC1CV1.Bits.CV112 #define ADC1CV1_CV113 _ADC1CV1.Bits.CV113 #define ADC1CV1_CV114 _ADC1CV1.Bits.CV114 #define ADC1CV1_CV115 _ADC1CV1.Bits.CV115 #define ADC1CV1_CV_10 _ADC1CV1.MergedBits.grpCV_10 #define ADC1CV1_CV1_10 _ADC1CV1.MergedBits.grpCV1_10 #define ADC1CV1_CV ADC1CV1_CV_10 #define ADC1CV1_CV1 ADC1CV1_CV1_10 #define ADC1CV1_CV10_MASK 1 #define ADC1CV1_CV11_MASK 2 #define ADC1CV1_CV12_MASK 4 #define ADC1CV1_CV13_MASK 8 #define ADC1CV1_CV14_MASK 16 #define ADC1CV1_CV15_MASK 32 #define ADC1CV1_CV16_MASK 64 #define ADC1CV1_CV17_MASK 128 #define ADC1CV1_CV18_MASK 256 #define ADC1CV1_CV19_MASK 512 #define ADC1CV1_CV110_MASK 1024 #define ADC1CV1_CV111_MASK 2048 #define ADC1CV1_CV112_MASK 4096 #define ADC1CV1_CV113_MASK 8192 #define ADC1CV1_CV114_MASK 16384 #define ADC1CV1_CV115_MASK 32768 #define ADC1CV1_CV_10_MASK 1023 #define ADC1CV1_CV_10_BITNUM 0 #define ADC1CV1_CV1_10_MASK 64512 #define ADC1CV1_CV1_10_BITNUM 10 /*** ADC1CV2 - Compare Value 2 Register; 0xFFFF840A ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC1CV2H - Compare Value 2 High Register; 0xFFFF840A ***/ union { byte Byte; struct { byte CV28 :1; /* Compare Function Value 8 */ byte CV29 :1; /* Compare Function Value 9 */ byte CV210 :1; /* Compare Function Value 10 */ byte CV211 :1; /* Compare Function Value 11 */ byte CV212 :1; /* Compare Function Value 12 */ byte CV213 :1; /* Compare Function Value 13 */ byte CV214 :1; /* Compare Function Value 14 */ byte CV215 :1; /* Compare Function Value 15 */ } Bits; struct { byte grpCV_28 :2; byte grpCV2_10 :6; } MergedBits; } ADC1CV2HSTR; #define ADC1CV2H _ADC1CV2.Overlap_STR.ADC1CV2HSTR.Byte #define ADC1CV2H_CV28 _ADC1CV2.Overlap_STR.ADC1CV2HSTR.Bits.CV28 #define ADC1CV2H_CV29 _ADC1CV2.Overlap_STR.ADC1CV2HSTR.Bits.CV29 #define ADC1CV2H_CV210 _ADC1CV2.Overlap_STR.ADC1CV2HSTR.Bits.CV210 #define ADC1CV2H_CV211 _ADC1CV2.Overlap_STR.ADC1CV2HSTR.Bits.CV211 #define ADC1CV2H_CV212 _ADC1CV2.Overlap_STR.ADC1CV2HSTR.Bits.CV212 #define ADC1CV2H_CV213 _ADC1CV2.Overlap_STR.ADC1CV2HSTR.Bits.CV213 #define ADC1CV2H_CV214 _ADC1CV2.Overlap_STR.ADC1CV2HSTR.Bits.CV214 #define ADC1CV2H_CV215 _ADC1CV2.Overlap_STR.ADC1CV2HSTR.Bits.CV215 #define ADC1CV2H_CV_28 _ADC1CV2.Overlap_STR.ADC1CV2HSTR.MergedBits.grpCV_28 #define ADC1CV2H_CV2_10 _ADC1CV2.Overlap_STR.ADC1CV2HSTR.MergedBits.grpCV2_10 #define ADC1CV2H_CV ADC1CV2H_CV_28 #define ADC1CV2H_CV2 ADC1CV2H_CV2_10 #define ADC1CV2H_CV28_MASK 1 #define ADC1CV2H_CV29_MASK 2 #define ADC1CV2H_CV210_MASK 4 #define ADC1CV2H_CV211_MASK 8 #define ADC1CV2H_CV212_MASK 16 #define ADC1CV2H_CV213_MASK 32 #define ADC1CV2H_CV214_MASK 64 #define ADC1CV2H_CV215_MASK 128 #define ADC1CV2H_CV_28_MASK 3 #define ADC1CV2H_CV_28_BITNUM 0 #define ADC1CV2H_CV2_10_MASK 252 #define ADC1CV2H_CV2_10_BITNUM 2 /*** ADC1CV2L - Compare Value 2 Low Register; 0xFFFF840B ***/ union { byte Byte; struct { byte CV20 :1; /* Compare Function Value 0 */ byte CV21 :1; /* Compare Function Value 1 */ byte CV22 :1; /* Compare Function Value 2 */ byte CV23 :1; /* Compare Function Value 3 */ byte CV24 :1; /* Compare Function Value 4 */ byte CV25 :1; /* Compare Function Value 5 */ byte CV26 :1; /* Compare Function Value 6 */ byte CV27 :1; /* Compare Function Value 7 */ } Bits; } ADC1CV2LSTR; #define ADC1CV2L _ADC1CV2.Overlap_STR.ADC1CV2LSTR.Byte #define ADC1CV2L_CV20 _ADC1CV2.Overlap_STR.ADC1CV2LSTR.Bits.CV20 #define ADC1CV2L_CV21 _ADC1CV2.Overlap_STR.ADC1CV2LSTR.Bits.CV21 #define ADC1CV2L_CV22 _ADC1CV2.Overlap_STR.ADC1CV2LSTR.Bits.CV22 #define ADC1CV2L_CV23 _ADC1CV2.Overlap_STR.ADC1CV2LSTR.Bits.CV23 #define ADC1CV2L_CV24 _ADC1CV2.Overlap_STR.ADC1CV2LSTR.Bits.CV24 #define ADC1CV2L_CV25 _ADC1CV2.Overlap_STR.ADC1CV2LSTR.Bits.CV25 #define ADC1CV2L_CV26 _ADC1CV2.Overlap_STR.ADC1CV2LSTR.Bits.CV26 #define ADC1CV2L_CV27 _ADC1CV2.Overlap_STR.ADC1CV2LSTR.Bits.CV27 #define ADC1CV2L_CV20_MASK 1 #define ADC1CV2L_CV21_MASK 2 #define ADC1CV2L_CV22_MASK 4 #define ADC1CV2L_CV23_MASK 8 #define ADC1CV2L_CV24_MASK 16 #define ADC1CV2L_CV25_MASK 32 #define ADC1CV2L_CV26_MASK 64 #define ADC1CV2L_CV27_MASK 128 } Overlap_STR; struct { word CV20 :1; /* Compare Function Value 0 */ word CV21 :1; /* Compare Function Value 1 */ word CV22 :1; /* Compare Function Value 2 */ word CV23 :1; /* Compare Function Value 3 */ word CV24 :1; /* Compare Function Value 4 */ word CV25 :1; /* Compare Function Value 5 */ word CV26 :1; /* Compare Function Value 6 */ word CV27 :1; /* Compare Function Value 7 */ word CV28 :1; /* Compare Function Value 8 */ word CV29 :1; /* Compare Function Value 9 */ word CV210 :1; /* Compare Function Value 10 */ word CV211 :1; /* Compare Function Value 11 */ word CV212 :1; /* Compare Function Value 12 */ word CV213 :1; /* Compare Function Value 13 */ word CV214 :1; /* Compare Function Value 14 */ word CV215 :1; /* Compare Function Value 15 */ } Bits; struct { word grpCV_20 :10; word grpCV2_10 :6; } MergedBits; } ADC1CV2STR; extern volatile ADC1CV2STR _ADC1CV2 @0xFFFF840A; #define ADC1CV2 _ADC1CV2.Word #define ADC1CV2_CV20 _ADC1CV2.Bits.CV20 #define ADC1CV2_CV21 _ADC1CV2.Bits.CV21 #define ADC1CV2_CV22 _ADC1CV2.Bits.CV22 #define ADC1CV2_CV23 _ADC1CV2.Bits.CV23 #define ADC1CV2_CV24 _ADC1CV2.Bits.CV24 #define ADC1CV2_CV25 _ADC1CV2.Bits.CV25 #define ADC1CV2_CV26 _ADC1CV2.Bits.CV26 #define ADC1CV2_CV27 _ADC1CV2.Bits.CV27 #define ADC1CV2_CV28 _ADC1CV2.Bits.CV28 #define ADC1CV2_CV29 _ADC1CV2.Bits.CV29 #define ADC1CV2_CV210 _ADC1CV2.Bits.CV210 #define ADC1CV2_CV211 _ADC1CV2.Bits.CV211 #define ADC1CV2_CV212 _ADC1CV2.Bits.CV212 #define ADC1CV2_CV213 _ADC1CV2.Bits.CV213 #define ADC1CV2_CV214 _ADC1CV2.Bits.CV214 #define ADC1CV2_CV215 _ADC1CV2.Bits.CV215 #define ADC1CV2_CV_20 _ADC1CV2.MergedBits.grpCV_20 #define ADC1CV2_CV2_10 _ADC1CV2.MergedBits.grpCV2_10 #define ADC1CV2_CV ADC1CV2_CV_20 #define ADC1CV2_CV2 ADC1CV2_CV2_10 #define ADC1CV2_CV20_MASK 1 #define ADC1CV2_CV21_MASK 2 #define ADC1CV2_CV22_MASK 4 #define ADC1CV2_CV23_MASK 8 #define ADC1CV2_CV24_MASK 16 #define ADC1CV2_CV25_MASK 32 #define ADC1CV2_CV26_MASK 64 #define ADC1CV2_CV27_MASK 128 #define ADC1CV2_CV28_MASK 256 #define ADC1CV2_CV29_MASK 512 #define ADC1CV2_CV210_MASK 1024 #define ADC1CV2_CV211_MASK 2048 #define ADC1CV2_CV212_MASK 4096 #define ADC1CV2_CV213_MASK 8192 #define ADC1CV2_CV214_MASK 16384 #define ADC1CV2_CV215_MASK 32768 #define ADC1CV2_CV_20_MASK 1023 #define ADC1CV2_CV_20_BITNUM 0 #define ADC1CV2_CV2_10_MASK 64512 #define ADC1CV2_CV2_10_BITNUM 10 /*** ADC1SC2 - Status and Control Register 2; 0xFFFF840C ***/ typedef union { byte Byte; struct { byte REFSEL0 :1; /* Voltage Reference Selection, bit 0 */ byte REFSEL1 :1; /* Voltage Reference Selection, bit 1 */ byte :1; byte ACREN :1; /* Compare Function Range Enable */ byte ACFGT :1; /* Compare Function Greater Than Enable */ byte ACFE :1; /* Compare Function Enable - ACFE is used to enable the compare function */ byte ADTRG :1; /* Conversion Trigger Select-ADTRG is used to select the type of trigger to be used for initiating a conversion */ byte ADACT :1; /* Conversion Active - ADACT indicates that a conversion is in progress. ADACT is set when a conversion is initiated and cleared when a conversion is completed or aborted */ } Bits; struct { byte grpREFSEL :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ADC1SC2STR; extern volatile ADC1SC2STR _ADC1SC2 @0xFFFF840C; #define ADC1SC2 _ADC1SC2.Byte #define ADC1SC2_REFSEL0 _ADC1SC2.Bits.REFSEL0 #define ADC1SC2_REFSEL1 _ADC1SC2.Bits.REFSEL1 #define ADC1SC2_ACREN _ADC1SC2.Bits.ACREN #define ADC1SC2_ACFGT _ADC1SC2.Bits.ACFGT #define ADC1SC2_ACFE _ADC1SC2.Bits.ACFE #define ADC1SC2_ADTRG _ADC1SC2.Bits.ADTRG #define ADC1SC2_ADACT _ADC1SC2.Bits.ADACT #define ADC1SC2_REFSEL _ADC1SC2.MergedBits.grpREFSEL #define ADC1SC2_REFSEL0_MASK 1 #define ADC1SC2_REFSEL1_MASK 2 #define ADC1SC2_ACREN_MASK 8 #define ADC1SC2_ACFGT_MASK 16 #define ADC1SC2_ACFE_MASK 32 #define ADC1SC2_ADTRG_MASK 64 #define ADC1SC2_ADACT_MASK 128 #define ADC1SC2_REFSEL_MASK 3 #define ADC1SC2_REFSEL_BITNUM 0 /*** ADC1SC3 - Status and Control Register 3; 0xFFFF840D ***/ typedef union { byte Byte; struct { byte AVGS0 :1; /* Hardware Average select, bit 0 */ byte AVGS1 :1; /* Hardware Average select, bit 1 */ byte AVGE :1; /* Hardware average enable - AVGE enables the hardware average function of the ADC */ byte ADCO :1; /* Continuous Conversion Enable - ADCO enables continuous conversions */ byte :1; byte :1; byte CALF :1; /* Calibration Failed Flag - CALF displays the result of the calibration sequence */ byte CAL :1; /* Calibration - CAL begins the calibration sequence when set */ } Bits; struct { byte grpAVGS :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ADC1SC3STR; extern volatile ADC1SC3STR _ADC1SC3 @0xFFFF840D; #define ADC1SC3 _ADC1SC3.Byte #define ADC1SC3_AVGS0 _ADC1SC3.Bits.AVGS0 #define ADC1SC3_AVGS1 _ADC1SC3.Bits.AVGS1 #define ADC1SC3_AVGE _ADC1SC3.Bits.AVGE #define ADC1SC3_ADCO _ADC1SC3.Bits.ADCO #define ADC1SC3_CALF _ADC1SC3.Bits.CALF #define ADC1SC3_CAL _ADC1SC3.Bits.CAL #define ADC1SC3_AVGS _ADC1SC3.MergedBits.grpAVGS #define ADC1SC3_AVGS0_MASK 1 #define ADC1SC3_AVGS1_MASK 2 #define ADC1SC3_AVGE_MASK 4 #define ADC1SC3_ADCO_MASK 8 #define ADC1SC3_CALF_MASK 64 #define ADC1SC3_CAL_MASK 128 #define ADC1SC3_AVGS_MASK 3 #define ADC1SC3_AVGS_BITNUM 0 /*** ADC1OFS - Offset Correction Register; 0xFFFF840E ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC1OFSH - Offset Correction High Register; 0xFFFF840E ***/ union { byte Byte; struct { byte OFS8 :1; /* Offset error correction value bit 8 */ byte OFS9 :1; /* Offset error correction value bit 9 */ byte OFS10 :1; /* Offset error correction value bit 10 */ byte OFS11 :1; /* Offset error correction value bit 11 */ byte OFS12 :1; /* Offset error correction value bit 12 */ byte OFS13 :1; /* Offset error correction value bit 13 */ byte OFS14 :1; /* Offset error correction value bit 14 */ byte OFS15 :1; /* Offset error correction value bit 15 */ } Bits; } ADC1OFSHSTR; #define ADC1OFSH _ADC1OFS.Overlap_STR.ADC1OFSHSTR.Byte #define ADC1OFSH_OFS8 _ADC1OFS.Overlap_STR.ADC1OFSHSTR.Bits.OFS8 #define ADC1OFSH_OFS9 _ADC1OFS.Overlap_STR.ADC1OFSHSTR.Bits.OFS9 #define ADC1OFSH_OFS10 _ADC1OFS.Overlap_STR.ADC1OFSHSTR.Bits.OFS10 #define ADC1OFSH_OFS11 _ADC1OFS.Overlap_STR.ADC1OFSHSTR.Bits.OFS11 #define ADC1OFSH_OFS12 _ADC1OFS.Overlap_STR.ADC1OFSHSTR.Bits.OFS12 #define ADC1OFSH_OFS13 _ADC1OFS.Overlap_STR.ADC1OFSHSTR.Bits.OFS13 #define ADC1OFSH_OFS14 _ADC1OFS.Overlap_STR.ADC1OFSHSTR.Bits.OFS14 #define ADC1OFSH_OFS15 _ADC1OFS.Overlap_STR.ADC1OFSHSTR.Bits.OFS15 #define ADC1OFSH_OFS8_MASK 1 #define ADC1OFSH_OFS9_MASK 2 #define ADC1OFSH_OFS10_MASK 4 #define ADC1OFSH_OFS11_MASK 8 #define ADC1OFSH_OFS12_MASK 16 #define ADC1OFSH_OFS13_MASK 32 #define ADC1OFSH_OFS14_MASK 64 #define ADC1OFSH_OFS15_MASK 128 /*** ADC1OFSL - Offset Correction Low Register; 0xFFFF840F ***/ union { byte Byte; struct { byte OFS0 :1; /* Offset error correction value bit 0 */ byte OFS1 :1; /* Offset error correction value bit 1 */ byte OFS2 :1; /* Offset error correction value bit 2 */ byte OFS3 :1; /* Offset error correction value bit 3 */ byte OFS4 :1; /* Offset error correction value bit 4 */ byte OFS5 :1; /* Offset error correction value bit 5 */ byte OFS6 :1; /* Offset error correction value bit 6 */ byte OFS7 :1; /* Offset error correction value bit 7 */ } Bits; } ADC1OFSLSTR; #define ADC1OFSL _ADC1OFS.Overlap_STR.ADC1OFSLSTR.Byte #define ADC1OFSL_OFS0 _ADC1OFS.Overlap_STR.ADC1OFSLSTR.Bits.OFS0 #define ADC1OFSL_OFS1 _ADC1OFS.Overlap_STR.ADC1OFSLSTR.Bits.OFS1 #define ADC1OFSL_OFS2 _ADC1OFS.Overlap_STR.ADC1OFSLSTR.Bits.OFS2 #define ADC1OFSL_OFS3 _ADC1OFS.Overlap_STR.ADC1OFSLSTR.Bits.OFS3 #define ADC1OFSL_OFS4 _ADC1OFS.Overlap_STR.ADC1OFSLSTR.Bits.OFS4 #define ADC1OFSL_OFS5 _ADC1OFS.Overlap_STR.ADC1OFSLSTR.Bits.OFS5 #define ADC1OFSL_OFS6 _ADC1OFS.Overlap_STR.ADC1OFSLSTR.Bits.OFS6 #define ADC1OFSL_OFS7 _ADC1OFS.Overlap_STR.ADC1OFSLSTR.Bits.OFS7 #define ADC1OFSL_OFS0_MASK 1 #define ADC1OFSL_OFS1_MASK 2 #define ADC1OFSL_OFS2_MASK 4 #define ADC1OFSL_OFS3_MASK 8 #define ADC1OFSL_OFS4_MASK 16 #define ADC1OFSL_OFS5_MASK 32 #define ADC1OFSL_OFS6_MASK 64 #define ADC1OFSL_OFS7_MASK 128 } Overlap_STR; struct { word OFS0 :1; /* Offset error correction value bit 0 */ word OFS1 :1; /* Offset error correction value bit 1 */ word OFS2 :1; /* Offset error correction value bit 2 */ word OFS3 :1; /* Offset error correction value bit 3 */ word OFS4 :1; /* Offset error correction value bit 4 */ word OFS5 :1; /* Offset error correction value bit 5 */ word OFS6 :1; /* Offset error correction value bit 6 */ word OFS7 :1; /* Offset error correction value bit 7 */ word OFS8 :1; /* Offset error correction value bit 8 */ word OFS9 :1; /* Offset error correction value bit 9 */ word OFS10 :1; /* Offset error correction value bit 10 */ word OFS11 :1; /* Offset error correction value bit 11 */ word OFS12 :1; /* Offset error correction value bit 12 */ word OFS13 :1; /* Offset error correction value bit 13 */ word OFS14 :1; /* Offset error correction value bit 14 */ word OFS15 :1; /* Offset error correction value bit 15 */ } Bits; } ADC1OFSSTR; extern volatile ADC1OFSSTR _ADC1OFS @0xFFFF840E; #define ADC1OFS _ADC1OFS.Word #define ADC1OFS_OFS0 _ADC1OFS.Bits.OFS0 #define ADC1OFS_OFS1 _ADC1OFS.Bits.OFS1 #define ADC1OFS_OFS2 _ADC1OFS.Bits.OFS2 #define ADC1OFS_OFS3 _ADC1OFS.Bits.OFS3 #define ADC1OFS_OFS4 _ADC1OFS.Bits.OFS4 #define ADC1OFS_OFS5 _ADC1OFS.Bits.OFS5 #define ADC1OFS_OFS6 _ADC1OFS.Bits.OFS6 #define ADC1OFS_OFS7 _ADC1OFS.Bits.OFS7 #define ADC1OFS_OFS8 _ADC1OFS.Bits.OFS8 #define ADC1OFS_OFS9 _ADC1OFS.Bits.OFS9 #define ADC1OFS_OFS10 _ADC1OFS.Bits.OFS10 #define ADC1OFS_OFS11 _ADC1OFS.Bits.OFS11 #define ADC1OFS_OFS12 _ADC1OFS.Bits.OFS12 #define ADC1OFS_OFS13 _ADC1OFS.Bits.OFS13 #define ADC1OFS_OFS14 _ADC1OFS.Bits.OFS14 #define ADC1OFS_OFS15 _ADC1OFS.Bits.OFS15 #define ADC1OFS_OFS0_MASK 1 #define ADC1OFS_OFS1_MASK 2 #define ADC1OFS_OFS2_MASK 4 #define ADC1OFS_OFS3_MASK 8 #define ADC1OFS_OFS4_MASK 16 #define ADC1OFS_OFS5_MASK 32 #define ADC1OFS_OFS6_MASK 64 #define ADC1OFS_OFS7_MASK 128 #define ADC1OFS_OFS8_MASK 256 #define ADC1OFS_OFS9_MASK 512 #define ADC1OFS_OFS10_MASK 1024 #define ADC1OFS_OFS11_MASK 2048 #define ADC1OFS_OFS12_MASK 4096 #define ADC1OFS_OFS13_MASK 8192 #define ADC1OFS_OFS14_MASK 16384 #define ADC1OFS_OFS15_MASK 32768 /*** ADC1PG - Plus-Side Gain Register; 0xFFFF8410 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC1PGH - Plus-Side Gain High Register; 0xFFFF8410 ***/ union { byte Byte; struct { byte PG8 :1; /* Gain error correction for the plus-side input value bit 8 */ byte PG9 :1; /* Gain error correction for the plus-side input value bit 9 */ byte PG10 :1; /* Gain error correction for the plus-side input value bit 10 */ byte PG11 :1; /* Gain error correction for the plus-side input value bit 11 */ byte PG12 :1; /* Gain error correction for the plus-side input value bit 12 */ byte PG13 :1; /* Gain error correction for the plus-side input value bit 13 */ byte PG14 :1; /* Gain error correction for the plus-side input value bit 14 */ byte PG15 :1; /* Gain error correction for the plus-side input value bit 15 */ } Bits; } ADC1PGHSTR; #define ADC1PGH _ADC1PG.Overlap_STR.ADC1PGHSTR.Byte #define ADC1PGH_PG8 _ADC1PG.Overlap_STR.ADC1PGHSTR.Bits.PG8 #define ADC1PGH_PG9 _ADC1PG.Overlap_STR.ADC1PGHSTR.Bits.PG9 #define ADC1PGH_PG10 _ADC1PG.Overlap_STR.ADC1PGHSTR.Bits.PG10 #define ADC1PGH_PG11 _ADC1PG.Overlap_STR.ADC1PGHSTR.Bits.PG11 #define ADC1PGH_PG12 _ADC1PG.Overlap_STR.ADC1PGHSTR.Bits.PG12 #define ADC1PGH_PG13 _ADC1PG.Overlap_STR.ADC1PGHSTR.Bits.PG13 #define ADC1PGH_PG14 _ADC1PG.Overlap_STR.ADC1PGHSTR.Bits.PG14 #define ADC1PGH_PG15 _ADC1PG.Overlap_STR.ADC1PGHSTR.Bits.PG15 #define ADC1PGH_PG8_MASK 1 #define ADC1PGH_PG9_MASK 2 #define ADC1PGH_PG10_MASK 4 #define ADC1PGH_PG11_MASK 8 #define ADC1PGH_PG12_MASK 16 #define ADC1PGH_PG13_MASK 32 #define ADC1PGH_PG14_MASK 64 #define ADC1PGH_PG15_MASK 128 /*** ADC1PGL - Plus-Side Gain Low Register; 0xFFFF8411 ***/ union { byte Byte; struct { byte PG0 :1; /* Gain error correction for the plus-side input value bit 0 */ byte PG1 :1; /* Gain error correction for the plus-side input value bit 1 */ byte PG2 :1; /* Gain error correction for the plus-side input value bit 2 */ byte PG3 :1; /* Gain error correction for the plus-side input value bit 3 */ byte PG4 :1; /* Gain error correction for the plus-side input value bit 4 */ byte PG5 :1; /* Gain error correction for the plus-side input value bit 5 */ byte PG6 :1; /* Gain error correction for the plus-side input value bit 6 */ byte PG7 :1; /* Gain error correction for the plus-side input value bit 7 */ } Bits; } ADC1PGLSTR; #define ADC1PGL _ADC1PG.Overlap_STR.ADC1PGLSTR.Byte #define ADC1PGL_PG0 _ADC1PG.Overlap_STR.ADC1PGLSTR.Bits.PG0 #define ADC1PGL_PG1 _ADC1PG.Overlap_STR.ADC1PGLSTR.Bits.PG1 #define ADC1PGL_PG2 _ADC1PG.Overlap_STR.ADC1PGLSTR.Bits.PG2 #define ADC1PGL_PG3 _ADC1PG.Overlap_STR.ADC1PGLSTR.Bits.PG3 #define ADC1PGL_PG4 _ADC1PG.Overlap_STR.ADC1PGLSTR.Bits.PG4 #define ADC1PGL_PG5 _ADC1PG.Overlap_STR.ADC1PGLSTR.Bits.PG5 #define ADC1PGL_PG6 _ADC1PG.Overlap_STR.ADC1PGLSTR.Bits.PG6 #define ADC1PGL_PG7 _ADC1PG.Overlap_STR.ADC1PGLSTR.Bits.PG7 #define ADC1PGL_PG0_MASK 1 #define ADC1PGL_PG1_MASK 2 #define ADC1PGL_PG2_MASK 4 #define ADC1PGL_PG3_MASK 8 #define ADC1PGL_PG4_MASK 16 #define ADC1PGL_PG5_MASK 32 #define ADC1PGL_PG6_MASK 64 #define ADC1PGL_PG7_MASK 128 } Overlap_STR; struct { word PG0 :1; /* Gain error correction for the plus-side input value bit 0 */ word PG1 :1; /* Gain error correction for the plus-side input value bit 1 */ word PG2 :1; /* Gain error correction for the plus-side input value bit 2 */ word PG3 :1; /* Gain error correction for the plus-side input value bit 3 */ word PG4 :1; /* Gain error correction for the plus-side input value bit 4 */ word PG5 :1; /* Gain error correction for the plus-side input value bit 5 */ word PG6 :1; /* Gain error correction for the plus-side input value bit 6 */ word PG7 :1; /* Gain error correction for the plus-side input value bit 7 */ word PG8 :1; /* Gain error correction for the plus-side input value bit 8 */ word PG9 :1; /* Gain error correction for the plus-side input value bit 9 */ word PG10 :1; /* Gain error correction for the plus-side input value bit 10 */ word PG11 :1; /* Gain error correction for the plus-side input value bit 11 */ word PG12 :1; /* Gain error correction for the plus-side input value bit 12 */ word PG13 :1; /* Gain error correction for the plus-side input value bit 13 */ word PG14 :1; /* Gain error correction for the plus-side input value bit 14 */ word PG15 :1; /* Gain error correction for the plus-side input value bit 15 */ } Bits; } ADC1PGSTR; extern volatile ADC1PGSTR _ADC1PG @0xFFFF8410; #define ADC1PG _ADC1PG.Word #define ADC1PG_PG0 _ADC1PG.Bits.PG0 #define ADC1PG_PG1 _ADC1PG.Bits.PG1 #define ADC1PG_PG2 _ADC1PG.Bits.PG2 #define ADC1PG_PG3 _ADC1PG.Bits.PG3 #define ADC1PG_PG4 _ADC1PG.Bits.PG4 #define ADC1PG_PG5 _ADC1PG.Bits.PG5 #define ADC1PG_PG6 _ADC1PG.Bits.PG6 #define ADC1PG_PG7 _ADC1PG.Bits.PG7 #define ADC1PG_PG8 _ADC1PG.Bits.PG8 #define ADC1PG_PG9 _ADC1PG.Bits.PG9 #define ADC1PG_PG10 _ADC1PG.Bits.PG10 #define ADC1PG_PG11 _ADC1PG.Bits.PG11 #define ADC1PG_PG12 _ADC1PG.Bits.PG12 #define ADC1PG_PG13 _ADC1PG.Bits.PG13 #define ADC1PG_PG14 _ADC1PG.Bits.PG14 #define ADC1PG_PG15 _ADC1PG.Bits.PG15 #define ADC1PG_PG0_MASK 1 #define ADC1PG_PG1_MASK 2 #define ADC1PG_PG2_MASK 4 #define ADC1PG_PG3_MASK 8 #define ADC1PG_PG4_MASK 16 #define ADC1PG_PG5_MASK 32 #define ADC1PG_PG6_MASK 64 #define ADC1PG_PG7_MASK 128 #define ADC1PG_PG8_MASK 256 #define ADC1PG_PG9_MASK 512 #define ADC1PG_PG10_MASK 1024 #define ADC1PG_PG11_MASK 2048 #define ADC1PG_PG12_MASK 4096 #define ADC1PG_PG13_MASK 8192 #define ADC1PG_PG14_MASK 16384 #define ADC1PG_PG15_MASK 32768 /*** ADC1MG - Minus-Side Gain Register; 0xFFFF8412 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC1MGH - Minus-Side Gain High Register; 0xFFFF8412 ***/ union { byte Byte; struct { byte MG8 :1; /* Gain error correction for the minus-side input value bit 8 */ byte MG9 :1; /* Gain error correction for the minus-side input value bit 9 */ byte MG10 :1; /* Gain error correction for the minus-side input value bit 10 */ byte MG11 :1; /* Gain error correction for the minus-side input value bit 11 */ byte MG12 :1; /* Gain error correction for the minus-side input value bit 12 */ byte MG13 :1; /* Gain error correction for the minus-side input value bit 13 */ byte MG14 :1; /* Gain error correction for the minus-side input value bit 14 */ byte MG15 :1; /* Gain error correction for the minus-side input value bit 15 */ } Bits; } ADC1MGHSTR; #define ADC1MGH _ADC1MG.Overlap_STR.ADC1MGHSTR.Byte #define ADC1MGH_MG8 _ADC1MG.Overlap_STR.ADC1MGHSTR.Bits.MG8 #define ADC1MGH_MG9 _ADC1MG.Overlap_STR.ADC1MGHSTR.Bits.MG9 #define ADC1MGH_MG10 _ADC1MG.Overlap_STR.ADC1MGHSTR.Bits.MG10 #define ADC1MGH_MG11 _ADC1MG.Overlap_STR.ADC1MGHSTR.Bits.MG11 #define ADC1MGH_MG12 _ADC1MG.Overlap_STR.ADC1MGHSTR.Bits.MG12 #define ADC1MGH_MG13 _ADC1MG.Overlap_STR.ADC1MGHSTR.Bits.MG13 #define ADC1MGH_MG14 _ADC1MG.Overlap_STR.ADC1MGHSTR.Bits.MG14 #define ADC1MGH_MG15 _ADC1MG.Overlap_STR.ADC1MGHSTR.Bits.MG15 #define ADC1MGH_MG8_MASK 1 #define ADC1MGH_MG9_MASK 2 #define ADC1MGH_MG10_MASK 4 #define ADC1MGH_MG11_MASK 8 #define ADC1MGH_MG12_MASK 16 #define ADC1MGH_MG13_MASK 32 #define ADC1MGH_MG14_MASK 64 #define ADC1MGH_MG15_MASK 128 /*** ADC1MGL - Minus-Side Gain Low Register; 0xFFFF8413 ***/ union { byte Byte; struct { byte MG0 :1; /* Gain error correction for the minus-side input value bit 0 */ byte MG1 :1; /* Gain error correction for the minus-side input value bit 1 */ byte MG2 :1; /* Gain error correction for the minus-side input value bit 2 */ byte MG3 :1; /* Gain error correction for the minus-side input value bit 3 */ byte MG4 :1; /* Gain error correction for the minus-side input value bit 4 */ byte MG5 :1; /* Gain error correction for the minus-side input value bit 5 */ byte MG6 :1; /* Gain error correction for the minus-side input value bit 6 */ byte MG7 :1; /* Gain error correction for the minus-side input value bit 7 */ } Bits; } ADC1MGLSTR; #define ADC1MGL _ADC1MG.Overlap_STR.ADC1MGLSTR.Byte #define ADC1MGL_MG0 _ADC1MG.Overlap_STR.ADC1MGLSTR.Bits.MG0 #define ADC1MGL_MG1 _ADC1MG.Overlap_STR.ADC1MGLSTR.Bits.MG1 #define ADC1MGL_MG2 _ADC1MG.Overlap_STR.ADC1MGLSTR.Bits.MG2 #define ADC1MGL_MG3 _ADC1MG.Overlap_STR.ADC1MGLSTR.Bits.MG3 #define ADC1MGL_MG4 _ADC1MG.Overlap_STR.ADC1MGLSTR.Bits.MG4 #define ADC1MGL_MG5 _ADC1MG.Overlap_STR.ADC1MGLSTR.Bits.MG5 #define ADC1MGL_MG6 _ADC1MG.Overlap_STR.ADC1MGLSTR.Bits.MG6 #define ADC1MGL_MG7 _ADC1MG.Overlap_STR.ADC1MGLSTR.Bits.MG7 #define ADC1MGL_MG0_MASK 1 #define ADC1MGL_MG1_MASK 2 #define ADC1MGL_MG2_MASK 4 #define ADC1MGL_MG3_MASK 8 #define ADC1MGL_MG4_MASK 16 #define ADC1MGL_MG5_MASK 32 #define ADC1MGL_MG6_MASK 64 #define ADC1MGL_MG7_MASK 128 } Overlap_STR; struct { word MG0 :1; /* Gain error correction for the minus-side input value bit 0 */ word MG1 :1; /* Gain error correction for the minus-side input value bit 1 */ word MG2 :1; /* Gain error correction for the minus-side input value bit 2 */ word MG3 :1; /* Gain error correction for the minus-side input value bit 3 */ word MG4 :1; /* Gain error correction for the minus-side input value bit 4 */ word MG5 :1; /* Gain error correction for the minus-side input value bit 5 */ word MG6 :1; /* Gain error correction for the minus-side input value bit 6 */ word MG7 :1; /* Gain error correction for the minus-side input value bit 7 */ word MG8 :1; /* Gain error correction for the minus-side input value bit 8 */ word MG9 :1; /* Gain error correction for the minus-side input value bit 9 */ word MG10 :1; /* Gain error correction for the minus-side input value bit 10 */ word MG11 :1; /* Gain error correction for the minus-side input value bit 11 */ word MG12 :1; /* Gain error correction for the minus-side input value bit 12 */ word MG13 :1; /* Gain error correction for the minus-side input value bit 13 */ word MG14 :1; /* Gain error correction for the minus-side input value bit 14 */ word MG15 :1; /* Gain error correction for the minus-side input value bit 15 */ } Bits; } ADC1MGSTR; extern volatile ADC1MGSTR _ADC1MG @0xFFFF8412; #define ADC1MG _ADC1MG.Word #define ADC1MG_MG0 _ADC1MG.Bits.MG0 #define ADC1MG_MG1 _ADC1MG.Bits.MG1 #define ADC1MG_MG2 _ADC1MG.Bits.MG2 #define ADC1MG_MG3 _ADC1MG.Bits.MG3 #define ADC1MG_MG4 _ADC1MG.Bits.MG4 #define ADC1MG_MG5 _ADC1MG.Bits.MG5 #define ADC1MG_MG6 _ADC1MG.Bits.MG6 #define ADC1MG_MG7 _ADC1MG.Bits.MG7 #define ADC1MG_MG8 _ADC1MG.Bits.MG8 #define ADC1MG_MG9 _ADC1MG.Bits.MG9 #define ADC1MG_MG10 _ADC1MG.Bits.MG10 #define ADC1MG_MG11 _ADC1MG.Bits.MG11 #define ADC1MG_MG12 _ADC1MG.Bits.MG12 #define ADC1MG_MG13 _ADC1MG.Bits.MG13 #define ADC1MG_MG14 _ADC1MG.Bits.MG14 #define ADC1MG_MG15 _ADC1MG.Bits.MG15 #define ADC1MG_MG0_MASK 1 #define ADC1MG_MG1_MASK 2 #define ADC1MG_MG2_MASK 4 #define ADC1MG_MG3_MASK 8 #define ADC1MG_MG4_MASK 16 #define ADC1MG_MG5_MASK 32 #define ADC1MG_MG6_MASK 64 #define ADC1MG_MG7_MASK 128 #define ADC1MG_MG8_MASK 256 #define ADC1MG_MG9_MASK 512 #define ADC1MG_MG10_MASK 1024 #define ADC1MG_MG11_MASK 2048 #define ADC1MG_MG12_MASK 4096 #define ADC1MG_MG13_MASK 8192 #define ADC1MG_MG14_MASK 16384 #define ADC1MG_MG15_MASK 32768 /*** ADC1CLPD - Plus-Side General Calibration Value D Register; 0xFFFF8414 ***/ typedef union { byte Byte; struct { byte CLPD0 :1; /* Plus-Side General Calibration Value D bit 0 */ byte CLPD1 :1; /* Plus-Side General Calibration Value D bit 1 */ byte CLPD2 :1; /* Plus-Side General Calibration Value D bit 2 */ byte CLPD3 :1; /* Plus-Side General Calibration Value D bit 3 */ byte CLPD4 :1; /* Plus-Side General Calibration Value D bit 4 */ byte CLPD5 :1; /* Plus-Side General Calibration Value D bit 5 */ byte :1; byte :1; } Bits; struct { byte grpCLPD :6; byte :1; byte :1; } MergedBits; } ADC1CLPDSTR; extern volatile ADC1CLPDSTR _ADC1CLPD @0xFFFF8414; #define ADC1CLPD _ADC1CLPD.Byte #define ADC1CLPD_CLPD0 _ADC1CLPD.Bits.CLPD0 #define ADC1CLPD_CLPD1 _ADC1CLPD.Bits.CLPD1 #define ADC1CLPD_CLPD2 _ADC1CLPD.Bits.CLPD2 #define ADC1CLPD_CLPD3 _ADC1CLPD.Bits.CLPD3 #define ADC1CLPD_CLPD4 _ADC1CLPD.Bits.CLPD4 #define ADC1CLPD_CLPD5 _ADC1CLPD.Bits.CLPD5 #define ADC1CLPD_CLPD _ADC1CLPD.MergedBits.grpCLPD #define ADC1CLPD_CLPD0_MASK 1 #define ADC1CLPD_CLPD1_MASK 2 #define ADC1CLPD_CLPD2_MASK 4 #define ADC1CLPD_CLPD3_MASK 8 #define ADC1CLPD_CLPD4_MASK 16 #define ADC1CLPD_CLPD5_MASK 32 #define ADC1CLPD_CLPD_MASK 63 #define ADC1CLPD_CLPD_BITNUM 0 /*** ADC1CLPS - Plus-Side General Calibration Value S Register; 0xFFFF8415 ***/ typedef union { byte Byte; struct { byte CLPS0 :1; /* Plus-Side General Calibration Value S bit 0 */ byte CLPS1 :1; /* Plus-Side General Calibration Value S bit 1 */ byte CLPS2 :1; /* Plus-Side General Calibration Value S bit 2 */ byte CLPS3 :1; /* Plus-Side General Calibration Value S bit 3 */ byte CLPS4 :1; /* Plus-Side General Calibration Value S bit 4 */ byte CLPS5 :1; /* Plus-Side General Calibration Value S bit 5 */ byte :1; byte :1; } Bits; struct { byte grpCLPS :6; byte :1; byte :1; } MergedBits; } ADC1CLPSSTR; extern volatile ADC1CLPSSTR _ADC1CLPS @0xFFFF8415; #define ADC1CLPS _ADC1CLPS.Byte #define ADC1CLPS_CLPS0 _ADC1CLPS.Bits.CLPS0 #define ADC1CLPS_CLPS1 _ADC1CLPS.Bits.CLPS1 #define ADC1CLPS_CLPS2 _ADC1CLPS.Bits.CLPS2 #define ADC1CLPS_CLPS3 _ADC1CLPS.Bits.CLPS3 #define ADC1CLPS_CLPS4 _ADC1CLPS.Bits.CLPS4 #define ADC1CLPS_CLPS5 _ADC1CLPS.Bits.CLPS5 #define ADC1CLPS_CLPS _ADC1CLPS.MergedBits.grpCLPS #define ADC1CLPS_CLPS0_MASK 1 #define ADC1CLPS_CLPS1_MASK 2 #define ADC1CLPS_CLPS2_MASK 4 #define ADC1CLPS_CLPS3_MASK 8 #define ADC1CLPS_CLPS4_MASK 16 #define ADC1CLPS_CLPS5_MASK 32 #define ADC1CLPS_CLPS_MASK 63 #define ADC1CLPS_CLPS_BITNUM 0 /*** ADC1CLP4 - Plus-Side General Calibration Value 4 Register; 0xFFFF8416 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC1CLP4H - Plus-Side General Calibration Value 4 High Register; 0xFFFF8416 ***/ union { byte Byte; struct { byte CLP48 :1; /* Plus-Side General Calibration Value 4 bit 8 */ byte CLP49 :1; /* Plus-Side General Calibration Value 4 bit 9 */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpCLP_48 :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ADC1CLP4HSTR; #define ADC1CLP4H _ADC1CLP4.Overlap_STR.ADC1CLP4HSTR.Byte #define ADC1CLP4H_CLP48 _ADC1CLP4.Overlap_STR.ADC1CLP4HSTR.Bits.CLP48 #define ADC1CLP4H_CLP49 _ADC1CLP4.Overlap_STR.ADC1CLP4HSTR.Bits.CLP49 #define ADC1CLP4H_CLP_48 _ADC1CLP4.Overlap_STR.ADC1CLP4HSTR.MergedBits.grpCLP_48 #define ADC1CLP4H_CLP ADC1CLP4H_CLP_48 #define ADC1CLP4H_CLP48_MASK 1 #define ADC1CLP4H_CLP49_MASK 2 #define ADC1CLP4H_CLP_48_MASK 3 #define ADC1CLP4H_CLP_48_BITNUM 0 /*** ADC1CLP4L - Plus-Side General Calibration Value 4 Low Register; 0xFFFF8417 ***/ union { byte Byte; struct { byte CLP40 :1; /* Plus-Side General Calibration Value 4 bit 0 */ byte CLP41 :1; /* Plus-Side General Calibration Value 4 bit 1 */ byte CLP42 :1; /* Plus-Side General Calibration Value 4 bit 2 */ byte CLP43 :1; /* Plus-Side General Calibration Value 4 bit 3 */ byte CLP44 :1; /* Plus-Side General Calibration Value 4 bit 4 */ byte CLP45 :1; /* Plus-Side General Calibration Value 4 bit 5 */ byte CLP46 :1; /* Plus-Side General Calibration Value 4 bit 6 */ byte CLP47 :1; /* Plus-Side General Calibration Value 4 bit 7 */ } Bits; } ADC1CLP4LSTR; #define ADC1CLP4L _ADC1CLP4.Overlap_STR.ADC1CLP4LSTR.Byte #define ADC1CLP4L_CLP40 _ADC1CLP4.Overlap_STR.ADC1CLP4LSTR.Bits.CLP40 #define ADC1CLP4L_CLP41 _ADC1CLP4.Overlap_STR.ADC1CLP4LSTR.Bits.CLP41 #define ADC1CLP4L_CLP42 _ADC1CLP4.Overlap_STR.ADC1CLP4LSTR.Bits.CLP42 #define ADC1CLP4L_CLP43 _ADC1CLP4.Overlap_STR.ADC1CLP4LSTR.Bits.CLP43 #define ADC1CLP4L_CLP44 _ADC1CLP4.Overlap_STR.ADC1CLP4LSTR.Bits.CLP44 #define ADC1CLP4L_CLP45 _ADC1CLP4.Overlap_STR.ADC1CLP4LSTR.Bits.CLP45 #define ADC1CLP4L_CLP46 _ADC1CLP4.Overlap_STR.ADC1CLP4LSTR.Bits.CLP46 #define ADC1CLP4L_CLP47 _ADC1CLP4.Overlap_STR.ADC1CLP4LSTR.Bits.CLP47 #define ADC1CLP4L_CLP40_MASK 1 #define ADC1CLP4L_CLP41_MASK 2 #define ADC1CLP4L_CLP42_MASK 4 #define ADC1CLP4L_CLP43_MASK 8 #define ADC1CLP4L_CLP44_MASK 16 #define ADC1CLP4L_CLP45_MASK 32 #define ADC1CLP4L_CLP46_MASK 64 #define ADC1CLP4L_CLP47_MASK 128 } Overlap_STR; struct { word CLP40 :1; /* Plus-Side General Calibration Value 4 bit 0 */ word CLP41 :1; /* Plus-Side General Calibration Value 4 bit 1 */ word CLP42 :1; /* Plus-Side General Calibration Value 4 bit 2 */ word CLP43 :1; /* Plus-Side General Calibration Value 4 bit 3 */ word CLP44 :1; /* Plus-Side General Calibration Value 4 bit 4 */ word CLP45 :1; /* Plus-Side General Calibration Value 4 bit 5 */ word CLP46 :1; /* Plus-Side General Calibration Value 4 bit 6 */ word CLP47 :1; /* Plus-Side General Calibration Value 4 bit 7 */ word CLP48 :1; /* Plus-Side General Calibration Value 4 bit 8 */ word CLP49 :1; /* Plus-Side General Calibration Value 4 bit 9 */ word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpCLP_40 :10; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } ADC1CLP4STR; extern volatile ADC1CLP4STR _ADC1CLP4 @0xFFFF8416; #define ADC1CLP4 _ADC1CLP4.Word #define ADC1CLP4_CLP40 _ADC1CLP4.Bits.CLP40 #define ADC1CLP4_CLP41 _ADC1CLP4.Bits.CLP41 #define ADC1CLP4_CLP42 _ADC1CLP4.Bits.CLP42 #define ADC1CLP4_CLP43 _ADC1CLP4.Bits.CLP43 #define ADC1CLP4_CLP44 _ADC1CLP4.Bits.CLP44 #define ADC1CLP4_CLP45 _ADC1CLP4.Bits.CLP45 #define ADC1CLP4_CLP46 _ADC1CLP4.Bits.CLP46 #define ADC1CLP4_CLP47 _ADC1CLP4.Bits.CLP47 #define ADC1CLP4_CLP48 _ADC1CLP4.Bits.CLP48 #define ADC1CLP4_CLP49 _ADC1CLP4.Bits.CLP49 #define ADC1CLP4_CLP_40 _ADC1CLP4.MergedBits.grpCLP_40 #define ADC1CLP4_CLP ADC1CLP4_CLP_40 #define ADC1CLP4_CLP40_MASK 1 #define ADC1CLP4_CLP41_MASK 2 #define ADC1CLP4_CLP42_MASK 4 #define ADC1CLP4_CLP43_MASK 8 #define ADC1CLP4_CLP44_MASK 16 #define ADC1CLP4_CLP45_MASK 32 #define ADC1CLP4_CLP46_MASK 64 #define ADC1CLP4_CLP47_MASK 128 #define ADC1CLP4_CLP48_MASK 256 #define ADC1CLP4_CLP49_MASK 512 #define ADC1CLP4_CLP_40_MASK 1023 #define ADC1CLP4_CLP_40_BITNUM 0 /*** ADC1CLP3 - Plus-Side General Calibration Value 3 Register; 0xFFFF8418 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC1CLP3H - Plus-Side General Calibration Value 3 High Register; 0xFFFF8418 ***/ union { byte Byte; struct { byte CLP38 :1; /* Plus-Side General Calibration Value 3 bits */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } ADC1CLP3HSTR; #define ADC1CLP3H _ADC1CLP3.Overlap_STR.ADC1CLP3HSTR.Byte #define ADC1CLP3H_CLP38 _ADC1CLP3.Overlap_STR.ADC1CLP3HSTR.Bits.CLP38 #define ADC1CLP3H_CLP38_MASK 1 /*** ADC1CLP3L - Plus-Side General Calibration Value 3 Low Register; 0xFFFF8419 ***/ union { byte Byte; struct { byte CLP30 :1; /* Plus-Side General Calibration Value 3 bit 0 */ byte CLP31 :1; /* Plus-Side General Calibration Value 3 bit 1 */ byte CLP32 :1; /* Plus-Side General Calibration Value 3 bit 2 */ byte CLP33 :1; /* Plus-Side General Calibration Value 3 bit 3 */ byte CLP34 :1; /* Plus-Side General Calibration Value 3 bit 4 */ byte CLP35 :1; /* Plus-Side General Calibration Value 3 bit 5 */ byte CLP36 :1; /* Plus-Side General Calibration Value 3 bit 6 */ byte CLP37 :1; /* Plus-Side General Calibration Value 3 bit 7 */ } Bits; } ADC1CLP3LSTR; #define ADC1CLP3L _ADC1CLP3.Overlap_STR.ADC1CLP3LSTR.Byte #define ADC1CLP3L_CLP30 _ADC1CLP3.Overlap_STR.ADC1CLP3LSTR.Bits.CLP30 #define ADC1CLP3L_CLP31 _ADC1CLP3.Overlap_STR.ADC1CLP3LSTR.Bits.CLP31 #define ADC1CLP3L_CLP32 _ADC1CLP3.Overlap_STR.ADC1CLP3LSTR.Bits.CLP32 #define ADC1CLP3L_CLP33 _ADC1CLP3.Overlap_STR.ADC1CLP3LSTR.Bits.CLP33 #define ADC1CLP3L_CLP34 _ADC1CLP3.Overlap_STR.ADC1CLP3LSTR.Bits.CLP34 #define ADC1CLP3L_CLP35 _ADC1CLP3.Overlap_STR.ADC1CLP3LSTR.Bits.CLP35 #define ADC1CLP3L_CLP36 _ADC1CLP3.Overlap_STR.ADC1CLP3LSTR.Bits.CLP36 #define ADC1CLP3L_CLP37 _ADC1CLP3.Overlap_STR.ADC1CLP3LSTR.Bits.CLP37 #define ADC1CLP3L_CLP30_MASK 1 #define ADC1CLP3L_CLP31_MASK 2 #define ADC1CLP3L_CLP32_MASK 4 #define ADC1CLP3L_CLP33_MASK 8 #define ADC1CLP3L_CLP34_MASK 16 #define ADC1CLP3L_CLP35_MASK 32 #define ADC1CLP3L_CLP36_MASK 64 #define ADC1CLP3L_CLP37_MASK 128 } Overlap_STR; struct { word CLP30 :1; /* Plus-Side General Calibration Value 3 bit 0 */ word CLP31 :1; /* Plus-Side General Calibration Value 3 bit 1 */ word CLP32 :1; /* Plus-Side General Calibration Value 3 bit 2 */ word CLP33 :1; /* Plus-Side General Calibration Value 3 bit 3 */ word CLP34 :1; /* Plus-Side General Calibration Value 3 bit 4 */ word CLP35 :1; /* Plus-Side General Calibration Value 3 bit 5 */ word CLP36 :1; /* Plus-Side General Calibration Value 3 bit 6 */ word CLP37 :1; /* Plus-Side General Calibration Value 3 bit 7 */ word CLP38 :1; /* Plus-Side General Calibration Value 3 bit 8 */ word :1; word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpCLP_30 :9; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } ADC1CLP3STR; extern volatile ADC1CLP3STR _ADC1CLP3 @0xFFFF8418; #define ADC1CLP3 _ADC1CLP3.Word #define ADC1CLP3_CLP30 _ADC1CLP3.Bits.CLP30 #define ADC1CLP3_CLP31 _ADC1CLP3.Bits.CLP31 #define ADC1CLP3_CLP32 _ADC1CLP3.Bits.CLP32 #define ADC1CLP3_CLP33 _ADC1CLP3.Bits.CLP33 #define ADC1CLP3_CLP34 _ADC1CLP3.Bits.CLP34 #define ADC1CLP3_CLP35 _ADC1CLP3.Bits.CLP35 #define ADC1CLP3_CLP36 _ADC1CLP3.Bits.CLP36 #define ADC1CLP3_CLP37 _ADC1CLP3.Bits.CLP37 #define ADC1CLP3_CLP38 _ADC1CLP3.Bits.CLP38 #define ADC1CLP3_CLP_30 _ADC1CLP3.MergedBits.grpCLP_30 #define ADC1CLP3_CLP ADC1CLP3_CLP_30 #define ADC1CLP3_CLP30_MASK 1 #define ADC1CLP3_CLP31_MASK 2 #define ADC1CLP3_CLP32_MASK 4 #define ADC1CLP3_CLP33_MASK 8 #define ADC1CLP3_CLP34_MASK 16 #define ADC1CLP3_CLP35_MASK 32 #define ADC1CLP3_CLP36_MASK 64 #define ADC1CLP3_CLP37_MASK 128 #define ADC1CLP3_CLP38_MASK 256 #define ADC1CLP3_CLP_30_MASK 511 #define ADC1CLP3_CLP_30_BITNUM 0 /*** ADC1CLP2 - Plus-Side General Calibration Value 2 Register; 0xFFFF841A ***/ typedef union { byte Byte; struct { byte CLP20 :1; /* Plus-Side General Calibration Value 2 bit 0 */ byte CLP21 :1; /* Plus-Side General Calibration Value 2 bit 1 */ byte CLP22 :1; /* Plus-Side General Calibration Value 2 bit 2 */ byte CLP23 :1; /* Plus-Side General Calibration Value 2 bit 3 */ byte CLP24 :1; /* Plus-Side General Calibration Value 2 bit 4 */ byte CLP25 :1; /* Plus-Side General Calibration Value 2 bit 5 */ byte CLP26 :1; /* Plus-Side General Calibration Value 2 bit 6 */ byte CLP27 :1; /* Plus-Side General Calibration Value 2 bit 7 */ } Bits; } ADC1CLP2STR; extern volatile ADC1CLP2STR _ADC1CLP2 @0xFFFF841A; #define ADC1CLP2 _ADC1CLP2.Byte #define ADC1CLP2_CLP20 _ADC1CLP2.Bits.CLP20 #define ADC1CLP2_CLP21 _ADC1CLP2.Bits.CLP21 #define ADC1CLP2_CLP22 _ADC1CLP2.Bits.CLP22 #define ADC1CLP2_CLP23 _ADC1CLP2.Bits.CLP23 #define ADC1CLP2_CLP24 _ADC1CLP2.Bits.CLP24 #define ADC1CLP2_CLP25 _ADC1CLP2.Bits.CLP25 #define ADC1CLP2_CLP26 _ADC1CLP2.Bits.CLP26 #define ADC1CLP2_CLP27 _ADC1CLP2.Bits.CLP27 #define ADC1CLP2_CLP20_MASK 1 #define ADC1CLP2_CLP21_MASK 2 #define ADC1CLP2_CLP22_MASK 4 #define ADC1CLP2_CLP23_MASK 8 #define ADC1CLP2_CLP24_MASK 16 #define ADC1CLP2_CLP25_MASK 32 #define ADC1CLP2_CLP26_MASK 64 #define ADC1CLP2_CLP27_MASK 128 /*** ADC1CLP1 - Plus-Side General Calibration Value 1 Register; 0xFFFF841B ***/ typedef union { byte Byte; struct { byte CLP10 :1; /* Plus-Side General Calibration Value 1 bit 0 */ byte CLP11 :1; /* Plus-Side General Calibration Value 1 bit 1 */ byte CLP12 :1; /* Plus-Side General Calibration Value 1 bit 2 */ byte CLP13 :1; /* Plus-Side General Calibration Value 1 bit 3 */ byte CLP14 :1; /* Plus-Side General Calibration Value 1 bit 4 */ byte CLP15 :1; /* Plus-Side General Calibration Value 1 bit 5 */ byte CLP16 :1; /* Plus-Side General Calibration Value 1 bit 6 */ byte :1; } Bits; struct { byte grpCLP_10 :7; byte :1; } MergedBits; } ADC1CLP1STR; extern volatile ADC1CLP1STR _ADC1CLP1 @0xFFFF841B; #define ADC1CLP1 _ADC1CLP1.Byte #define ADC1CLP1_CLP10 _ADC1CLP1.Bits.CLP10 #define ADC1CLP1_CLP11 _ADC1CLP1.Bits.CLP11 #define ADC1CLP1_CLP12 _ADC1CLP1.Bits.CLP12 #define ADC1CLP1_CLP13 _ADC1CLP1.Bits.CLP13 #define ADC1CLP1_CLP14 _ADC1CLP1.Bits.CLP14 #define ADC1CLP1_CLP15 _ADC1CLP1.Bits.CLP15 #define ADC1CLP1_CLP16 _ADC1CLP1.Bits.CLP16 #define ADC1CLP1_CLP_10 _ADC1CLP1.MergedBits.grpCLP_10 #define ADC1CLP1_CLP ADC1CLP1_CLP_10 #define ADC1CLP1_CLP10_MASK 1 #define ADC1CLP1_CLP11_MASK 2 #define ADC1CLP1_CLP12_MASK 4 #define ADC1CLP1_CLP13_MASK 8 #define ADC1CLP1_CLP14_MASK 16 #define ADC1CLP1_CLP15_MASK 32 #define ADC1CLP1_CLP16_MASK 64 #define ADC1CLP1_CLP_10_MASK 127 #define ADC1CLP1_CLP_10_BITNUM 0 /*** ADC1CLP0 - Plus-Side General Calibration Value 0 Register; 0xFFFF841C ***/ typedef union { byte Byte; struct { byte CLP00 :1; /* Plus-Side General Calibration Value 0 bit 0 */ byte CLP01 :1; /* Plus-Side General Calibration Value 0 bit 1 */ byte CLP02 :1; /* Plus-Side General Calibration Value 0 bit 2 */ byte CLP03 :1; /* Plus-Side General Calibration Value 0 bit 3 */ byte CLP04 :1; /* Plus-Side General Calibration Value 0 bit 4 */ byte CLP05 :1; /* Plus-Side General Calibration Value 0 bit 5 */ byte :1; byte :1; } Bits; struct { byte grpCLP0 :6; byte :1; byte :1; } MergedBits; } ADC1CLP0STR; extern volatile ADC1CLP0STR _ADC1CLP0 @0xFFFF841C; #define ADC1CLP0 _ADC1CLP0.Byte #define ADC1CLP0_CLP00 _ADC1CLP0.Bits.CLP00 #define ADC1CLP0_CLP01 _ADC1CLP0.Bits.CLP01 #define ADC1CLP0_CLP02 _ADC1CLP0.Bits.CLP02 #define ADC1CLP0_CLP03 _ADC1CLP0.Bits.CLP03 #define ADC1CLP0_CLP04 _ADC1CLP0.Bits.CLP04 #define ADC1CLP0_CLP05 _ADC1CLP0.Bits.CLP05 #define ADC1CLP0_CLP0 _ADC1CLP0.MergedBits.grpCLP0 #define ADC1CLP0_CLP00_MASK 1 #define ADC1CLP0_CLP01_MASK 2 #define ADC1CLP0_CLP02_MASK 4 #define ADC1CLP0_CLP03_MASK 8 #define ADC1CLP0_CLP04_MASK 16 #define ADC1CLP0_CLP05_MASK 32 #define ADC1CLP0_CLP0_MASK 63 #define ADC1CLP0_CLP0_BITNUM 0 /*** ADC1CLMD - Minus-Side General Calibration Value D Register; 0xFFFF841E ***/ typedef union { byte Byte; struct { byte CLMD0 :1; /* Minus-Side General Calibration Value D bit 0 */ byte CLMD1 :1; /* Minus-Side General Calibration Value D bit 1 */ byte CLMD2 :1; /* Minus-Side General Calibration Value D bit 2 */ byte CLMD3 :1; /* Minus-Side General Calibration Value D bit 3 */ byte CLMD4 :1; /* Minus-Side General Calibration Value D bit 4 */ byte CLMD5 :1; /* Minus-Side General Calibration Value D bit 5 */ byte :1; byte :1; } Bits; struct { byte grpCLMD :6; byte :1; byte :1; } MergedBits; } ADC1CLMDSTR; extern volatile ADC1CLMDSTR _ADC1CLMD @0xFFFF841E; #define ADC1CLMD _ADC1CLMD.Byte #define ADC1CLMD_CLMD0 _ADC1CLMD.Bits.CLMD0 #define ADC1CLMD_CLMD1 _ADC1CLMD.Bits.CLMD1 #define ADC1CLMD_CLMD2 _ADC1CLMD.Bits.CLMD2 #define ADC1CLMD_CLMD3 _ADC1CLMD.Bits.CLMD3 #define ADC1CLMD_CLMD4 _ADC1CLMD.Bits.CLMD4 #define ADC1CLMD_CLMD5 _ADC1CLMD.Bits.CLMD5 #define ADC1CLMD_CLMD _ADC1CLMD.MergedBits.grpCLMD #define ADC1CLMD_CLMD0_MASK 1 #define ADC1CLMD_CLMD1_MASK 2 #define ADC1CLMD_CLMD2_MASK 4 #define ADC1CLMD_CLMD3_MASK 8 #define ADC1CLMD_CLMD4_MASK 16 #define ADC1CLMD_CLMD5_MASK 32 #define ADC1CLMD_CLMD_MASK 63 #define ADC1CLMD_CLMD_BITNUM 0 /*** ADC1CLMS - Minus-Side General Calibration Value S Register; 0xFFFF841F ***/ typedef union { byte Byte; struct { byte CLMS0 :1; /* Minus-Side General Calibration Value S bit 0 */ byte CLMS1 :1; /* Minus-Side General Calibration Value S bit 1 */ byte CLMS2 :1; /* Minus-Side General Calibration Value S bit 2 */ byte CLMS3 :1; /* Minus-Side General Calibration Value S bit 3 */ byte CLMS4 :1; /* Minus-Side General Calibration Value S bit 4 */ byte CLMS5 :1; /* Minus-Side General Calibration Value S bit 5 */ byte :1; byte :1; } Bits; struct { byte grpCLMS :6; byte :1; byte :1; } MergedBits; } ADC1CLMSSTR; extern volatile ADC1CLMSSTR _ADC1CLMS @0xFFFF841F; #define ADC1CLMS _ADC1CLMS.Byte #define ADC1CLMS_CLMS0 _ADC1CLMS.Bits.CLMS0 #define ADC1CLMS_CLMS1 _ADC1CLMS.Bits.CLMS1 #define ADC1CLMS_CLMS2 _ADC1CLMS.Bits.CLMS2 #define ADC1CLMS_CLMS3 _ADC1CLMS.Bits.CLMS3 #define ADC1CLMS_CLMS4 _ADC1CLMS.Bits.CLMS4 #define ADC1CLMS_CLMS5 _ADC1CLMS.Bits.CLMS5 #define ADC1CLMS_CLMS _ADC1CLMS.MergedBits.grpCLMS #define ADC1CLMS_CLMS0_MASK 1 #define ADC1CLMS_CLMS1_MASK 2 #define ADC1CLMS_CLMS2_MASK 4 #define ADC1CLMS_CLMS3_MASK 8 #define ADC1CLMS_CLMS4_MASK 16 #define ADC1CLMS_CLMS5_MASK 32 #define ADC1CLMS_CLMS_MASK 63 #define ADC1CLMS_CLMS_BITNUM 0 /*** ADC1CLM4 - Minus-Side General Calibration Value 4 Register; 0xFFFF8420 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC1CLM4H - Minus-Side General Calibration Value 4 High Register; 0xFFFF8420 ***/ union { byte Byte; struct { byte CLM48 :1; /* Minus-Side General Calibration Value 4 bit 8 */ byte CLM49 :1; /* Minus-Side General Calibration Value 4 bit 9 */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpCLM_48 :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ADC1CLM4HSTR; #define ADC1CLM4H _ADC1CLM4.Overlap_STR.ADC1CLM4HSTR.Byte #define ADC1CLM4H_CLM48 _ADC1CLM4.Overlap_STR.ADC1CLM4HSTR.Bits.CLM48 #define ADC1CLM4H_CLM49 _ADC1CLM4.Overlap_STR.ADC1CLM4HSTR.Bits.CLM49 #define ADC1CLM4H_CLM_48 _ADC1CLM4.Overlap_STR.ADC1CLM4HSTR.MergedBits.grpCLM_48 #define ADC1CLM4H_CLM ADC1CLM4H_CLM_48 #define ADC1CLM4H_CLM48_MASK 1 #define ADC1CLM4H_CLM49_MASK 2 #define ADC1CLM4H_CLM_48_MASK 3 #define ADC1CLM4H_CLM_48_BITNUM 0 /*** ADC1CLM4L - Minus-Side General Calibration Value 4 Low Register; 0xFFFF8421 ***/ union { byte Byte; struct { byte CLM40 :1; /* Minus-Side General Calibration Value 4 bit 0 */ byte CLM41 :1; /* Minus-Side General Calibration Value 4 bit 1 */ byte CLM42 :1; /* Minus-Side General Calibration Value 4 bit 2 */ byte CLM43 :1; /* Minus-Side General Calibration Value 4 bit 3 */ byte CLM44 :1; /* Minus-Side General Calibration Value 4 bit 4 */ byte CLM45 :1; /* Minus-Side General Calibration Value 4 bit 5 */ byte CLM46 :1; /* Minus-Side General Calibration Value 4 bit 6 */ byte CLM47 :1; /* Minus-Side General Calibration Value 4 bit 7 */ } Bits; } ADC1CLM4LSTR; #define ADC1CLM4L _ADC1CLM4.Overlap_STR.ADC1CLM4LSTR.Byte #define ADC1CLM4L_CLM40 _ADC1CLM4.Overlap_STR.ADC1CLM4LSTR.Bits.CLM40 #define ADC1CLM4L_CLM41 _ADC1CLM4.Overlap_STR.ADC1CLM4LSTR.Bits.CLM41 #define ADC1CLM4L_CLM42 _ADC1CLM4.Overlap_STR.ADC1CLM4LSTR.Bits.CLM42 #define ADC1CLM4L_CLM43 _ADC1CLM4.Overlap_STR.ADC1CLM4LSTR.Bits.CLM43 #define ADC1CLM4L_CLM44 _ADC1CLM4.Overlap_STR.ADC1CLM4LSTR.Bits.CLM44 #define ADC1CLM4L_CLM45 _ADC1CLM4.Overlap_STR.ADC1CLM4LSTR.Bits.CLM45 #define ADC1CLM4L_CLM46 _ADC1CLM4.Overlap_STR.ADC1CLM4LSTR.Bits.CLM46 #define ADC1CLM4L_CLM47 _ADC1CLM4.Overlap_STR.ADC1CLM4LSTR.Bits.CLM47 #define ADC1CLM4L_CLM40_MASK 1 #define ADC1CLM4L_CLM41_MASK 2 #define ADC1CLM4L_CLM42_MASK 4 #define ADC1CLM4L_CLM43_MASK 8 #define ADC1CLM4L_CLM44_MASK 16 #define ADC1CLM4L_CLM45_MASK 32 #define ADC1CLM4L_CLM46_MASK 64 #define ADC1CLM4L_CLM47_MASK 128 } Overlap_STR; struct { word CLM40 :1; /* Minus-Side General Calibration Value 4 bit 0 */ word CLM41 :1; /* Minus-Side General Calibration Value 4 bit 1 */ word CLM42 :1; /* Minus-Side General Calibration Value 4 bit 2 */ word CLM43 :1; /* Minus-Side General Calibration Value 4 bit 3 */ word CLM44 :1; /* Minus-Side General Calibration Value 4 bit 4 */ word CLM45 :1; /* Minus-Side General Calibration Value 4 bit 5 */ word CLM46 :1; /* Minus-Side General Calibration Value 4 bit 6 */ word CLM47 :1; /* Minus-Side General Calibration Value 4 bit 7 */ word CLM48 :1; /* Minus-Side General Calibration Value 4 bit 8 */ word CLM49 :1; /* Minus-Side General Calibration Value 4 bit 9 */ word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpCLM_40 :10; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } ADC1CLM4STR; extern volatile ADC1CLM4STR _ADC1CLM4 @0xFFFF8420; #define ADC1CLM4 _ADC1CLM4.Word #define ADC1CLM4_CLM40 _ADC1CLM4.Bits.CLM40 #define ADC1CLM4_CLM41 _ADC1CLM4.Bits.CLM41 #define ADC1CLM4_CLM42 _ADC1CLM4.Bits.CLM42 #define ADC1CLM4_CLM43 _ADC1CLM4.Bits.CLM43 #define ADC1CLM4_CLM44 _ADC1CLM4.Bits.CLM44 #define ADC1CLM4_CLM45 _ADC1CLM4.Bits.CLM45 #define ADC1CLM4_CLM46 _ADC1CLM4.Bits.CLM46 #define ADC1CLM4_CLM47 _ADC1CLM4.Bits.CLM47 #define ADC1CLM4_CLM48 _ADC1CLM4.Bits.CLM48 #define ADC1CLM4_CLM49 _ADC1CLM4.Bits.CLM49 #define ADC1CLM4_CLM_40 _ADC1CLM4.MergedBits.grpCLM_40 #define ADC1CLM4_CLM ADC1CLM4_CLM_40 #define ADC1CLM4_CLM40_MASK 1 #define ADC1CLM4_CLM41_MASK 2 #define ADC1CLM4_CLM42_MASK 4 #define ADC1CLM4_CLM43_MASK 8 #define ADC1CLM4_CLM44_MASK 16 #define ADC1CLM4_CLM45_MASK 32 #define ADC1CLM4_CLM46_MASK 64 #define ADC1CLM4_CLM47_MASK 128 #define ADC1CLM4_CLM48_MASK 256 #define ADC1CLM4_CLM49_MASK 512 #define ADC1CLM4_CLM_40_MASK 1023 #define ADC1CLM4_CLM_40_BITNUM 0 /*** ADC1CLM3 - Minus-Side General Calibration Value 3 Register; 0xFFFF8422 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC1CLM3H - Minus-Side General Calibration Value 3 High Register; 0xFFFF8422 ***/ union { byte Byte; struct { byte CLM38 :1; /* Minus-Side General Calibration Value 3 bits */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } ADC1CLM3HSTR; #define ADC1CLM3H _ADC1CLM3.Overlap_STR.ADC1CLM3HSTR.Byte #define ADC1CLM3H_CLM38 _ADC1CLM3.Overlap_STR.ADC1CLM3HSTR.Bits.CLM38 #define ADC1CLM3H_CLM38_MASK 1 /*** ADC1CLM3L - Minus-Side General Calibration Value 3 Low Register; 0xFFFF8423 ***/ union { byte Byte; struct { byte CLM30 :1; /* Minus-Side General Calibration Value 3 bit 0 */ byte CLM31 :1; /* Minus-Side General Calibration Value 3 bit 1 */ byte CLM32 :1; /* Minus-Side General Calibration Value 3 bit 2 */ byte CLM33 :1; /* Minus-Side General Calibration Value 3 bit 3 */ byte CLM34 :1; /* Minus-Side General Calibration Value 3 bit 4 */ byte CLM35 :1; /* Minus-Side General Calibration Value 3 bit 5 */ byte CLM36 :1; /* Minus-Side General Calibration Value 3 bit 6 */ byte CLM37 :1; /* Minus-Side General Calibration Value 3 bit 7 */ } Bits; } ADC1CLM3LSTR; #define ADC1CLM3L _ADC1CLM3.Overlap_STR.ADC1CLM3LSTR.Byte #define ADC1CLM3L_CLM30 _ADC1CLM3.Overlap_STR.ADC1CLM3LSTR.Bits.CLM30 #define ADC1CLM3L_CLM31 _ADC1CLM3.Overlap_STR.ADC1CLM3LSTR.Bits.CLM31 #define ADC1CLM3L_CLM32 _ADC1CLM3.Overlap_STR.ADC1CLM3LSTR.Bits.CLM32 #define ADC1CLM3L_CLM33 _ADC1CLM3.Overlap_STR.ADC1CLM3LSTR.Bits.CLM33 #define ADC1CLM3L_CLM34 _ADC1CLM3.Overlap_STR.ADC1CLM3LSTR.Bits.CLM34 #define ADC1CLM3L_CLM35 _ADC1CLM3.Overlap_STR.ADC1CLM3LSTR.Bits.CLM35 #define ADC1CLM3L_CLM36 _ADC1CLM3.Overlap_STR.ADC1CLM3LSTR.Bits.CLM36 #define ADC1CLM3L_CLM37 _ADC1CLM3.Overlap_STR.ADC1CLM3LSTR.Bits.CLM37 #define ADC1CLM3L_CLM30_MASK 1 #define ADC1CLM3L_CLM31_MASK 2 #define ADC1CLM3L_CLM32_MASK 4 #define ADC1CLM3L_CLM33_MASK 8 #define ADC1CLM3L_CLM34_MASK 16 #define ADC1CLM3L_CLM35_MASK 32 #define ADC1CLM3L_CLM36_MASK 64 #define ADC1CLM3L_CLM37_MASK 128 } Overlap_STR; struct { word CLM30 :1; /* Minus-Side General Calibration Value 3 bit 0 */ word CLM31 :1; /* Minus-Side General Calibration Value 3 bit 1 */ word CLM32 :1; /* Minus-Side General Calibration Value 3 bit 2 */ word CLM33 :1; /* Minus-Side General Calibration Value 3 bit 3 */ word CLM34 :1; /* Minus-Side General Calibration Value 3 bit 4 */ word CLM35 :1; /* Minus-Side General Calibration Value 3 bit 5 */ word CLM36 :1; /* Minus-Side General Calibration Value 3 bit 6 */ word CLM37 :1; /* Minus-Side General Calibration Value 3 bit 7 */ word CLM38 :1; /* Minus-Side General Calibration Value 3 bit 8 */ word :1; word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpCLM_30 :9; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } ADC1CLM3STR; extern volatile ADC1CLM3STR _ADC1CLM3 @0xFFFF8422; #define ADC1CLM3 _ADC1CLM3.Word #define ADC1CLM3_CLM30 _ADC1CLM3.Bits.CLM30 #define ADC1CLM3_CLM31 _ADC1CLM3.Bits.CLM31 #define ADC1CLM3_CLM32 _ADC1CLM3.Bits.CLM32 #define ADC1CLM3_CLM33 _ADC1CLM3.Bits.CLM33 #define ADC1CLM3_CLM34 _ADC1CLM3.Bits.CLM34 #define ADC1CLM3_CLM35 _ADC1CLM3.Bits.CLM35 #define ADC1CLM3_CLM36 _ADC1CLM3.Bits.CLM36 #define ADC1CLM3_CLM37 _ADC1CLM3.Bits.CLM37 #define ADC1CLM3_CLM38 _ADC1CLM3.Bits.CLM38 #define ADC1CLM3_CLM_30 _ADC1CLM3.MergedBits.grpCLM_30 #define ADC1CLM3_CLM ADC1CLM3_CLM_30 #define ADC1CLM3_CLM30_MASK 1 #define ADC1CLM3_CLM31_MASK 2 #define ADC1CLM3_CLM32_MASK 4 #define ADC1CLM3_CLM33_MASK 8 #define ADC1CLM3_CLM34_MASK 16 #define ADC1CLM3_CLM35_MASK 32 #define ADC1CLM3_CLM36_MASK 64 #define ADC1CLM3_CLM37_MASK 128 #define ADC1CLM3_CLM38_MASK 256 #define ADC1CLM3_CLM_30_MASK 511 #define ADC1CLM3_CLM_30_BITNUM 0 /*** ADC1CLM2 - Minus-Side General Calibration Value 2 Register; 0xFFFF8424 ***/ typedef union { byte Byte; struct { byte CLM20 :1; /* Minus-Side General Calibration Value 2 bit 0 */ byte CLM21 :1; /* Minus-Side General Calibration Value 2 bit 1 */ byte CLM22 :1; /* Minus-Side General Calibration Value 2 bit 2 */ byte CLM23 :1; /* Minus-Side General Calibration Value 2 bit 3 */ byte CLM24 :1; /* Minus-Side General Calibration Value 2 bit 4 */ byte CLM25 :1; /* Minus-Side General Calibration Value 2 bit 5 */ byte CLM26 :1; /* Minus-Side General Calibration Value 2 bit 6 */ byte CLM27 :1; /* Minus-Side General Calibration Value 2 bit 7 */ } Bits; } ADC1CLM2STR; extern volatile ADC1CLM2STR _ADC1CLM2 @0xFFFF8424; #define ADC1CLM2 _ADC1CLM2.Byte #define ADC1CLM2_CLM20 _ADC1CLM2.Bits.CLM20 #define ADC1CLM2_CLM21 _ADC1CLM2.Bits.CLM21 #define ADC1CLM2_CLM22 _ADC1CLM2.Bits.CLM22 #define ADC1CLM2_CLM23 _ADC1CLM2.Bits.CLM23 #define ADC1CLM2_CLM24 _ADC1CLM2.Bits.CLM24 #define ADC1CLM2_CLM25 _ADC1CLM2.Bits.CLM25 #define ADC1CLM2_CLM26 _ADC1CLM2.Bits.CLM26 #define ADC1CLM2_CLM27 _ADC1CLM2.Bits.CLM27 #define ADC1CLM2_CLM20_MASK 1 #define ADC1CLM2_CLM21_MASK 2 #define ADC1CLM2_CLM22_MASK 4 #define ADC1CLM2_CLM23_MASK 8 #define ADC1CLM2_CLM24_MASK 16 #define ADC1CLM2_CLM25_MASK 32 #define ADC1CLM2_CLM26_MASK 64 #define ADC1CLM2_CLM27_MASK 128 /*** ADC1CLM1 - Minus-Side General Calibration Value 1 Register; 0xFFFF8425 ***/ typedef union { byte Byte; struct { byte CLM10 :1; /* Minus-Side General Calibration Value 1 bit 0 */ byte CLM11 :1; /* Minus-Side General Calibration Value 1 bit 1 */ byte CLM12 :1; /* Minus-Side General Calibration Value 1 bit 2 */ byte CLM13 :1; /* Minus-Side General Calibration Value 1 bit 3 */ byte CLM14 :1; /* Minus-Side General Calibration Value 1 bit 4 */ byte CLM15 :1; /* Minus-Side General Calibration Value 1 bit 5 */ byte CLM16 :1; /* Minus-Side General Calibration Value 1 bit 6 */ byte :1; } Bits; struct { byte grpCLM_10 :7; byte :1; } MergedBits; } ADC1CLM1STR; extern volatile ADC1CLM1STR _ADC1CLM1 @0xFFFF8425; #define ADC1CLM1 _ADC1CLM1.Byte #define ADC1CLM1_CLM10 _ADC1CLM1.Bits.CLM10 #define ADC1CLM1_CLM11 _ADC1CLM1.Bits.CLM11 #define ADC1CLM1_CLM12 _ADC1CLM1.Bits.CLM12 #define ADC1CLM1_CLM13 _ADC1CLM1.Bits.CLM13 #define ADC1CLM1_CLM14 _ADC1CLM1.Bits.CLM14 #define ADC1CLM1_CLM15 _ADC1CLM1.Bits.CLM15 #define ADC1CLM1_CLM16 _ADC1CLM1.Bits.CLM16 #define ADC1CLM1_CLM_10 _ADC1CLM1.MergedBits.grpCLM_10 #define ADC1CLM1_CLM ADC1CLM1_CLM_10 #define ADC1CLM1_CLM10_MASK 1 #define ADC1CLM1_CLM11_MASK 2 #define ADC1CLM1_CLM12_MASK 4 #define ADC1CLM1_CLM13_MASK 8 #define ADC1CLM1_CLM14_MASK 16 #define ADC1CLM1_CLM15_MASK 32 #define ADC1CLM1_CLM16_MASK 64 #define ADC1CLM1_CLM_10_MASK 127 #define ADC1CLM1_CLM_10_BITNUM 0 /*** ADC1CLM0 - Minus-Side General Calibration Value 0 Register; 0xFFFF8426 ***/ typedef union { byte Byte; struct { byte CLM00 :1; /* Minus-Side General Calibration Value 0 bit 0 */ byte CLM01 :1; /* Minus-Side General Calibration Value 0 bit 1 */ byte CLM02 :1; /* Minus-Side General Calibration Value 0 bit 2 */ byte CLM03 :1; /* Minus-Side General Calibration Value 0 bit 3 */ byte CLM04 :1; /* Minus-Side General Calibration Value 0 bit 4 */ byte CLM05 :1; /* Minus-Side General Calibration Value 0 bit 5 */ byte :1; byte :1; } Bits; struct { byte grpCLM0 :6; byte :1; byte :1; } MergedBits; } ADC1CLM0STR; extern volatile ADC1CLM0STR _ADC1CLM0 @0xFFFF8426; #define ADC1CLM0 _ADC1CLM0.Byte #define ADC1CLM0_CLM00 _ADC1CLM0.Bits.CLM00 #define ADC1CLM0_CLM01 _ADC1CLM0.Bits.CLM01 #define ADC1CLM0_CLM02 _ADC1CLM0.Bits.CLM02 #define ADC1CLM0_CLM03 _ADC1CLM0.Bits.CLM03 #define ADC1CLM0_CLM04 _ADC1CLM0.Bits.CLM04 #define ADC1CLM0_CLM05 _ADC1CLM0.Bits.CLM05 #define ADC1CLM0_CLM0 _ADC1CLM0.MergedBits.grpCLM0 #define ADC1CLM0_CLM00_MASK 1 #define ADC1CLM0_CLM01_MASK 2 #define ADC1CLM0_CLM02_MASK 4 #define ADC1CLM0_CLM03_MASK 8 #define ADC1CLM0_CLM04_MASK 16 #define ADC1CLM0_CLM05_MASK 32 #define ADC1CLM0_CLM0_MASK 63 #define ADC1CLM0_CLM0_BITNUM 0 /*** ADC2SC1A - Status and Control Register 1A; 0xFFFF8440 ***/ typedef union { byte Byte; struct { byte ADCHA0 :1; /* Input Channel Select Bit 0 */ byte ADCHA1 :1; /* Input Channel Select Bit 1 */ byte ADCHA2 :1; /* Input Channel Select Bit 2 */ byte ADCHA3 :1; /* Input Channel Select Bit 3 */ byte ADCHA4 :1; /* Input Channel Select Bit 4 */ byte DIFFA :1; /* Differential Mode Enable - DIFFA configures the ADC to operate in differential mode */ byte AIENA :1; /* Interrupt Enable - AIENA enables conversion complete interrupts. When COCOA becomes set while the respective AIENA is high, an interrupt is asserted */ byte COCOA :1; /* Conversion Complete Flag */ } Bits; struct { byte grpADCHA :5; byte grpDIFFx :1; byte grpAIENx :1; byte grpCOCOx :1; } MergedBits; } ADC2SC1ASTR; extern volatile ADC2SC1ASTR _ADC2SC1A @0xFFFF8440; #define ADC2SC1A _ADC2SC1A.Byte #define ADC2SC1A_ADCHA0 _ADC2SC1A.Bits.ADCHA0 #define ADC2SC1A_ADCHA1 _ADC2SC1A.Bits.ADCHA1 #define ADC2SC1A_ADCHA2 _ADC2SC1A.Bits.ADCHA2 #define ADC2SC1A_ADCHA3 _ADC2SC1A.Bits.ADCHA3 #define ADC2SC1A_ADCHA4 _ADC2SC1A.Bits.ADCHA4 #define ADC2SC1A_DIFFA _ADC2SC1A.Bits.DIFFA #define ADC2SC1A_AIENA _ADC2SC1A.Bits.AIENA #define ADC2SC1A_COCOA _ADC2SC1A.Bits.COCOA #define ADC2SC1A_ADCHA _ADC2SC1A.MergedBits.grpADCHA #define ADC2SC1A_ADCHA0_MASK 1 #define ADC2SC1A_ADCHA1_MASK 2 #define ADC2SC1A_ADCHA2_MASK 4 #define ADC2SC1A_ADCHA3_MASK 8 #define ADC2SC1A_ADCHA4_MASK 16 #define ADC2SC1A_DIFFA_MASK 32 #define ADC2SC1A_AIENA_MASK 64 #define ADC2SC1A_COCOA_MASK 128 #define ADC2SC1A_ADCHA_MASK 31 #define ADC2SC1A_ADCHA_BITNUM 0 /*** ADC2SC1B - Status and Control Register 1B; 0xFFFF8441 ***/ typedef union { byte Byte; struct { byte ADCHB0 :1; /* Input Channel Select Bit 0 */ byte ADCHB1 :1; /* Input Channel Select Bit 1 */ byte ADCHB2 :1; /* Input Channel Select Bit 2 */ byte ADCHB3 :1; /* Input Channel Select Bit 3 */ byte ADCHB4 :1; /* Input Channel Select Bit 4 */ byte DIFFB :1; /* Differential Mode Enable - DIFFB configures the ADC to operate in differential mode */ byte AIENB :1; /* Interrupt Enable - AIENB enables conversion complete interrupts. When COCOB becomes set while the respective AIENB is high, an interrupt is asserted */ byte COCOB :1; /* Conversion Complete Flag */ } Bits; struct { byte grpADCHB :5; byte :1; byte :1; byte :1; } MergedBits; } ADC2SC1BSTR; extern volatile ADC2SC1BSTR _ADC2SC1B @0xFFFF8441; #define ADC2SC1B _ADC2SC1B.Byte #define ADC2SC1B_ADCHB0 _ADC2SC1B.Bits.ADCHB0 #define ADC2SC1B_ADCHB1 _ADC2SC1B.Bits.ADCHB1 #define ADC2SC1B_ADCHB2 _ADC2SC1B.Bits.ADCHB2 #define ADC2SC1B_ADCHB3 _ADC2SC1B.Bits.ADCHB3 #define ADC2SC1B_ADCHB4 _ADC2SC1B.Bits.ADCHB4 #define ADC2SC1B_DIFFB _ADC2SC1B.Bits.DIFFB #define ADC2SC1B_AIENB _ADC2SC1B.Bits.AIENB #define ADC2SC1B_COCOB _ADC2SC1B.Bits.COCOB #define ADC2SC1B_ADCHB _ADC2SC1B.MergedBits.grpADCHB #define ADC2SC1B_ADCHB0_MASK 1 #define ADC2SC1B_ADCHB1_MASK 2 #define ADC2SC1B_ADCHB2_MASK 4 #define ADC2SC1B_ADCHB3_MASK 8 #define ADC2SC1B_ADCHB4_MASK 16 #define ADC2SC1B_DIFFB_MASK 32 #define ADC2SC1B_AIENB_MASK 64 #define ADC2SC1B_COCOB_MASK 128 #define ADC2SC1B_ADCHB_MASK 31 #define ADC2SC1B_ADCHB_BITNUM 0 /*** ADC2CFG1 - Configuration Register 1; 0xFFFF8442 ***/ typedef union { byte Byte; struct { byte ADICLK0 :1; /* Input Clock Select Bit 0 */ byte ADICLK1 :1; /* Input Clock Select Bit 1 */ byte MODE0 :1; /* Conversion Mode Selection Bit 0 */ byte MODE1 :1; /* Conversion Mode Selection Bit 1 */ byte ADLSMP :1; /* Long Sample Time Configuration */ byte ADIV0 :1; /* Clock Divide Select Bit 0 */ byte ADIV1 :1; /* Clock Divide Select Bit 1 */ byte ADLPC :1; /* Low Power Configuration */ } Bits; struct { byte grpADICLK :2; byte grpMODE :2; byte :1; byte grpADIV :2; byte :1; } MergedBits; } ADC2CFG1STR; extern volatile ADC2CFG1STR _ADC2CFG1 @0xFFFF8442; #define ADC2CFG1 _ADC2CFG1.Byte #define ADC2CFG1_ADICLK0 _ADC2CFG1.Bits.ADICLK0 #define ADC2CFG1_ADICLK1 _ADC2CFG1.Bits.ADICLK1 #define ADC2CFG1_MODE0 _ADC2CFG1.Bits.MODE0 #define ADC2CFG1_MODE1 _ADC2CFG1.Bits.MODE1 #define ADC2CFG1_ADLSMP _ADC2CFG1.Bits.ADLSMP #define ADC2CFG1_ADIV0 _ADC2CFG1.Bits.ADIV0 #define ADC2CFG1_ADIV1 _ADC2CFG1.Bits.ADIV1 #define ADC2CFG1_ADLPC _ADC2CFG1.Bits.ADLPC #define ADC2CFG1_ADICLK _ADC2CFG1.MergedBits.grpADICLK #define ADC2CFG1_MODE _ADC2CFG1.MergedBits.grpMODE #define ADC2CFG1_ADIV _ADC2CFG1.MergedBits.grpADIV #define ADC2CFG1_ADICLK0_MASK 1 #define ADC2CFG1_ADICLK1_MASK 2 #define ADC2CFG1_MODE0_MASK 4 #define ADC2CFG1_MODE1_MASK 8 #define ADC2CFG1_ADLSMP_MASK 16 #define ADC2CFG1_ADIV0_MASK 32 #define ADC2CFG1_ADIV1_MASK 64 #define ADC2CFG1_ADLPC_MASK 128 #define ADC2CFG1_ADICLK_MASK 3 #define ADC2CFG1_ADICLK_BITNUM 0 #define ADC2CFG1_MODE_MASK 12 #define ADC2CFG1_MODE_BITNUM 2 #define ADC2CFG1_ADIV_MASK 96 #define ADC2CFG1_ADIV_BITNUM 5 /*** ADC2CFG2 - Configuration Register 2; 0xFFFF8443 ***/ typedef union { byte Byte; struct { byte ADLSTS0 :1; /* Long Sample Time Select Bit 0 */ byte ADLSTS1 :1; /* Long Sample Time Select Bit 1 */ byte ADHSC :1; /* High Speed Configuration */ byte ADACKEN :1; /* Asynchronous Clock Output Enable */ byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpADLSTS :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ADC2CFG2STR; extern volatile ADC2CFG2STR _ADC2CFG2 @0xFFFF8443; #define ADC2CFG2 _ADC2CFG2.Byte #define ADC2CFG2_ADLSTS0 _ADC2CFG2.Bits.ADLSTS0 #define ADC2CFG2_ADLSTS1 _ADC2CFG2.Bits.ADLSTS1 #define ADC2CFG2_ADHSC _ADC2CFG2.Bits.ADHSC #define ADC2CFG2_ADACKEN _ADC2CFG2.Bits.ADACKEN #define ADC2CFG2_ADLSTS _ADC2CFG2.MergedBits.grpADLSTS #define ADC2CFG2_ADLSTS0_MASK 1 #define ADC2CFG2_ADLSTS1_MASK 2 #define ADC2CFG2_ADHSC_MASK 4 #define ADC2CFG2_ADACKEN_MASK 8 #define ADC2CFG2_ADLSTS_MASK 3 #define ADC2CFG2_ADLSTS_BITNUM 0 /*** ADC2RA - Data Result Register A; 0xFFFF8444 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC2RHA - Data Result High Register A; 0xFFFF8444 ***/ union { byte Byte; struct { byte D8 :1; /* ADC Result Data Bit 8 */ byte D9 :1; /* ADC Result Data Bit 9 */ byte D10 :1; /* ADC Result Data Bit 10 */ byte D11 :1; /* ADC Result Data Bit 11 */ byte D12 :1; /* ADC Result Data Bit 12 */ byte D13 :1; /* ADC Result Data Bit 13 */ byte D14 :1; /* ADC Result Data Bit 14 */ byte D15 :1; /* ADC Result Data Bit 15 */ } Bits; } ADC2RHASTR; #define ADC2RHA _ADC2RA.Overlap_STR.ADC2RHASTR.Byte #define ADC2RHA_D8 _ADC2RA.Overlap_STR.ADC2RHASTR.Bits.D8 #define ADC2RHA_D9 _ADC2RA.Overlap_STR.ADC2RHASTR.Bits.D9 #define ADC2RHA_D10 _ADC2RA.Overlap_STR.ADC2RHASTR.Bits.D10 #define ADC2RHA_D11 _ADC2RA.Overlap_STR.ADC2RHASTR.Bits.D11 #define ADC2RHA_D12 _ADC2RA.Overlap_STR.ADC2RHASTR.Bits.D12 #define ADC2RHA_D13 _ADC2RA.Overlap_STR.ADC2RHASTR.Bits.D13 #define ADC2RHA_D14 _ADC2RA.Overlap_STR.ADC2RHASTR.Bits.D14 #define ADC2RHA_D15 _ADC2RA.Overlap_STR.ADC2RHASTR.Bits.D15 #define ADC2RHA_D8_MASK 1 #define ADC2RHA_D9_MASK 2 #define ADC2RHA_D10_MASK 4 #define ADC2RHA_D11_MASK 8 #define ADC2RHA_D12_MASK 16 #define ADC2RHA_D13_MASK 32 #define ADC2RHA_D14_MASK 64 #define ADC2RHA_D15_MASK 128 /*** ADC2RLA - Data Result Low Register A; 0xFFFF8445 ***/ union { byte Byte; struct { byte D0 :1; /* ADC Result Data Bit 0 */ byte D1 :1; /* ADC Result Data Bit 1 */ byte D2 :1; /* ADC Result Data Bit 2 */ byte D3 :1; /* ADC Result Data Bit 3 */ byte D4 :1; /* ADC Result Data Bit 4 */ byte D5 :1; /* ADC Result Data Bit 5 */ byte D6 :1; /* ADC Result Data Bit 6 */ byte D7 :1; /* ADC Result Data Bit 7 */ } Bits; } ADC2RLASTR; #define ADC2RLA _ADC2RA.Overlap_STR.ADC2RLASTR.Byte #define ADC2RLA_D0 _ADC2RA.Overlap_STR.ADC2RLASTR.Bits.D0 #define ADC2RLA_D1 _ADC2RA.Overlap_STR.ADC2RLASTR.Bits.D1 #define ADC2RLA_D2 _ADC2RA.Overlap_STR.ADC2RLASTR.Bits.D2 #define ADC2RLA_D3 _ADC2RA.Overlap_STR.ADC2RLASTR.Bits.D3 #define ADC2RLA_D4 _ADC2RA.Overlap_STR.ADC2RLASTR.Bits.D4 #define ADC2RLA_D5 _ADC2RA.Overlap_STR.ADC2RLASTR.Bits.D5 #define ADC2RLA_D6 _ADC2RA.Overlap_STR.ADC2RLASTR.Bits.D6 #define ADC2RLA_D7 _ADC2RA.Overlap_STR.ADC2RLASTR.Bits.D7 #define ADC2RLA_D0_MASK 1 #define ADC2RLA_D1_MASK 2 #define ADC2RLA_D2_MASK 4 #define ADC2RLA_D3_MASK 8 #define ADC2RLA_D4_MASK 16 #define ADC2RLA_D5_MASK 32 #define ADC2RLA_D6_MASK 64 #define ADC2RLA_D7_MASK 128 } Overlap_STR; struct { word D0 :1; /* ADC Result Data Bit 0 */ word D1 :1; /* ADC Result Data Bit 1 */ word D2 :1; /* ADC Result Data Bit 2 */ word D3 :1; /* ADC Result Data Bit 3 */ word D4 :1; /* ADC Result Data Bit 4 */ word D5 :1; /* ADC Result Data Bit 5 */ word D6 :1; /* ADC Result Data Bit 6 */ word D7 :1; /* ADC Result Data Bit 7 */ word D8 :1; /* ADC Result Data Bit 8 */ word D9 :1; /* ADC Result Data Bit 9 */ word D10 :1; /* ADC Result Data Bit 10 */ word D11 :1; /* ADC Result Data Bit 11 */ word D12 :1; /* ADC Result Data Bit 12 */ word D13 :1; /* ADC Result Data Bit 13 */ word D14 :1; /* ADC Result Data Bit 14 */ word D15 :1; /* ADC Result Data Bit 15 */ } Bits; } ADC2RASTR; extern volatile ADC2RASTR _ADC2RA @0xFFFF8444; #define ADC2RA _ADC2RA.Word #define ADC2RA_D0 _ADC2RA.Bits.D0 #define ADC2RA_D1 _ADC2RA.Bits.D1 #define ADC2RA_D2 _ADC2RA.Bits.D2 #define ADC2RA_D3 _ADC2RA.Bits.D3 #define ADC2RA_D4 _ADC2RA.Bits.D4 #define ADC2RA_D5 _ADC2RA.Bits.D5 #define ADC2RA_D6 _ADC2RA.Bits.D6 #define ADC2RA_D7 _ADC2RA.Bits.D7 #define ADC2RA_D8 _ADC2RA.Bits.D8 #define ADC2RA_D9 _ADC2RA.Bits.D9 #define ADC2RA_D10 _ADC2RA.Bits.D10 #define ADC2RA_D11 _ADC2RA.Bits.D11 #define ADC2RA_D12 _ADC2RA.Bits.D12 #define ADC2RA_D13 _ADC2RA.Bits.D13 #define ADC2RA_D14 _ADC2RA.Bits.D14 #define ADC2RA_D15 _ADC2RA.Bits.D15 #define ADC2RA_D0_MASK 1 #define ADC2RA_D1_MASK 2 #define ADC2RA_D2_MASK 4 #define ADC2RA_D3_MASK 8 #define ADC2RA_D4_MASK 16 #define ADC2RA_D5_MASK 32 #define ADC2RA_D6_MASK 64 #define ADC2RA_D7_MASK 128 #define ADC2RA_D8_MASK 256 #define ADC2RA_D9_MASK 512 #define ADC2RA_D10_MASK 1024 #define ADC2RA_D11_MASK 2048 #define ADC2RA_D12_MASK 4096 #define ADC2RA_D13_MASK 8192 #define ADC2RA_D14_MASK 16384 #define ADC2RA_D15_MASK 32768 /*** ADC2RB - Data Result Register B; 0xFFFF8446 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC2RHB - Data Result High Register B; 0xFFFF8446 ***/ union { byte Byte; struct { byte D8 :1; /* ADC Result Data Bit 8 */ byte D9 :1; /* ADC Result Data Bit 9 */ byte D10 :1; /* ADC Result Data Bit 10 */ byte D11 :1; /* ADC Result Data Bit 11 */ byte D12 :1; /* ADC Result Data Bit 12 */ byte D13 :1; /* ADC Result Data Bit 13 */ byte D14 :1; /* ADC Result Data Bit 14 */ byte D15 :1; /* ADC Result Data Bit 15 */ } Bits; } ADC2RHBSTR; #define ADC2RHB _ADC2RB.Overlap_STR.ADC2RHBSTR.Byte #define ADC2RHB_D8 _ADC2RB.Overlap_STR.ADC2RHBSTR.Bits.D8 #define ADC2RHB_D9 _ADC2RB.Overlap_STR.ADC2RHBSTR.Bits.D9 #define ADC2RHB_D10 _ADC2RB.Overlap_STR.ADC2RHBSTR.Bits.D10 #define ADC2RHB_D11 _ADC2RB.Overlap_STR.ADC2RHBSTR.Bits.D11 #define ADC2RHB_D12 _ADC2RB.Overlap_STR.ADC2RHBSTR.Bits.D12 #define ADC2RHB_D13 _ADC2RB.Overlap_STR.ADC2RHBSTR.Bits.D13 #define ADC2RHB_D14 _ADC2RB.Overlap_STR.ADC2RHBSTR.Bits.D14 #define ADC2RHB_D15 _ADC2RB.Overlap_STR.ADC2RHBSTR.Bits.D15 #define ADC2RHB_D8_MASK 1 #define ADC2RHB_D9_MASK 2 #define ADC2RHB_D10_MASK 4 #define ADC2RHB_D11_MASK 8 #define ADC2RHB_D12_MASK 16 #define ADC2RHB_D13_MASK 32 #define ADC2RHB_D14_MASK 64 #define ADC2RHB_D15_MASK 128 /*** ADC2RLB - Data Result Low Register B; 0xFFFF8447 ***/ union { byte Byte; struct { byte D0 :1; /* ADC Result Data Bit 0 */ byte D1 :1; /* ADC Result Data Bit 1 */ byte D2 :1; /* ADC Result Data Bit 2 */ byte D3 :1; /* ADC Result Data Bit 3 */ byte D4 :1; /* ADC Result Data Bit 4 */ byte D5 :1; /* ADC Result Data Bit 5 */ byte D6 :1; /* ADC Result Data Bit 6 */ byte D7 :1; /* ADC Result Data Bit 7 */ } Bits; } ADC2RLBSTR; #define ADC2RLB _ADC2RB.Overlap_STR.ADC2RLBSTR.Byte #define ADC2RLB_D0 _ADC2RB.Overlap_STR.ADC2RLBSTR.Bits.D0 #define ADC2RLB_D1 _ADC2RB.Overlap_STR.ADC2RLBSTR.Bits.D1 #define ADC2RLB_D2 _ADC2RB.Overlap_STR.ADC2RLBSTR.Bits.D2 #define ADC2RLB_D3 _ADC2RB.Overlap_STR.ADC2RLBSTR.Bits.D3 #define ADC2RLB_D4 _ADC2RB.Overlap_STR.ADC2RLBSTR.Bits.D4 #define ADC2RLB_D5 _ADC2RB.Overlap_STR.ADC2RLBSTR.Bits.D5 #define ADC2RLB_D6 _ADC2RB.Overlap_STR.ADC2RLBSTR.Bits.D6 #define ADC2RLB_D7 _ADC2RB.Overlap_STR.ADC2RLBSTR.Bits.D7 #define ADC2RLB_D0_MASK 1 #define ADC2RLB_D1_MASK 2 #define ADC2RLB_D2_MASK 4 #define ADC2RLB_D3_MASK 8 #define ADC2RLB_D4_MASK 16 #define ADC2RLB_D5_MASK 32 #define ADC2RLB_D6_MASK 64 #define ADC2RLB_D7_MASK 128 } Overlap_STR; struct { word D0 :1; /* ADC Result Data Bit 0 */ word D1 :1; /* ADC Result Data Bit 1 */ word D2 :1; /* ADC Result Data Bit 2 */ word D3 :1; /* ADC Result Data Bit 3 */ word D4 :1; /* ADC Result Data Bit 4 */ word D5 :1; /* ADC Result Data Bit 5 */ word D6 :1; /* ADC Result Data Bit 6 */ word D7 :1; /* ADC Result Data Bit 7 */ word D8 :1; /* ADC Result Data Bit 8 */ word D9 :1; /* ADC Result Data Bit 9 */ word D10 :1; /* ADC Result Data Bit 10 */ word D11 :1; /* ADC Result Data Bit 11 */ word D12 :1; /* ADC Result Data Bit 12 */ word D13 :1; /* ADC Result Data Bit 13 */ word D14 :1; /* ADC Result Data Bit 14 */ word D15 :1; /* ADC Result Data Bit 15 */ } Bits; } ADC2RBSTR; extern volatile ADC2RBSTR _ADC2RB @0xFFFF8446; #define ADC2RB _ADC2RB.Word #define ADC2RB_D0 _ADC2RB.Bits.D0 #define ADC2RB_D1 _ADC2RB.Bits.D1 #define ADC2RB_D2 _ADC2RB.Bits.D2 #define ADC2RB_D3 _ADC2RB.Bits.D3 #define ADC2RB_D4 _ADC2RB.Bits.D4 #define ADC2RB_D5 _ADC2RB.Bits.D5 #define ADC2RB_D6 _ADC2RB.Bits.D6 #define ADC2RB_D7 _ADC2RB.Bits.D7 #define ADC2RB_D8 _ADC2RB.Bits.D8 #define ADC2RB_D9 _ADC2RB.Bits.D9 #define ADC2RB_D10 _ADC2RB.Bits.D10 #define ADC2RB_D11 _ADC2RB.Bits.D11 #define ADC2RB_D12 _ADC2RB.Bits.D12 #define ADC2RB_D13 _ADC2RB.Bits.D13 #define ADC2RB_D14 _ADC2RB.Bits.D14 #define ADC2RB_D15 _ADC2RB.Bits.D15 #define ADC2RB_D0_MASK 1 #define ADC2RB_D1_MASK 2 #define ADC2RB_D2_MASK 4 #define ADC2RB_D3_MASK 8 #define ADC2RB_D4_MASK 16 #define ADC2RB_D5_MASK 32 #define ADC2RB_D6_MASK 64 #define ADC2RB_D7_MASK 128 #define ADC2RB_D8_MASK 256 #define ADC2RB_D9_MASK 512 #define ADC2RB_D10_MASK 1024 #define ADC2RB_D11_MASK 2048 #define ADC2RB_D12_MASK 4096 #define ADC2RB_D13_MASK 8192 #define ADC2RB_D14_MASK 16384 #define ADC2RB_D15_MASK 32768 /*** ADC2CV1 - Compare Value 1 Register; 0xFFFF8448 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC2CV1H - Compare Value 1 High Register; 0xFFFF8448 ***/ union { byte Byte; struct { byte CV18 :1; /* Compare Function Value 8 */ byte CV19 :1; /* Compare Function Value 9 */ byte CV110 :1; /* Compare Function Value 10 */ byte CV111 :1; /* Compare Function Value 11 */ byte CV112 :1; /* Compare Function Value 12 */ byte CV113 :1; /* Compare Function Value 13 */ byte CV114 :1; /* Compare Function Value 14 */ byte CV115 :1; /* Compare Function Value 15 */ } Bits; struct { byte grpCV_18 :2; byte grpCV1_10 :6; } MergedBits; } ADC2CV1HSTR; #define ADC2CV1H _ADC2CV1.Overlap_STR.ADC2CV1HSTR.Byte #define ADC2CV1H_CV18 _ADC2CV1.Overlap_STR.ADC2CV1HSTR.Bits.CV18 #define ADC2CV1H_CV19 _ADC2CV1.Overlap_STR.ADC2CV1HSTR.Bits.CV19 #define ADC2CV1H_CV110 _ADC2CV1.Overlap_STR.ADC2CV1HSTR.Bits.CV110 #define ADC2CV1H_CV111 _ADC2CV1.Overlap_STR.ADC2CV1HSTR.Bits.CV111 #define ADC2CV1H_CV112 _ADC2CV1.Overlap_STR.ADC2CV1HSTR.Bits.CV112 #define ADC2CV1H_CV113 _ADC2CV1.Overlap_STR.ADC2CV1HSTR.Bits.CV113 #define ADC2CV1H_CV114 _ADC2CV1.Overlap_STR.ADC2CV1HSTR.Bits.CV114 #define ADC2CV1H_CV115 _ADC2CV1.Overlap_STR.ADC2CV1HSTR.Bits.CV115 #define ADC2CV1H_CV_18 _ADC2CV1.Overlap_STR.ADC2CV1HSTR.MergedBits.grpCV_18 #define ADC2CV1H_CV1_10 _ADC2CV1.Overlap_STR.ADC2CV1HSTR.MergedBits.grpCV1_10 #define ADC2CV1H_CV ADC2CV1H_CV_18 #define ADC2CV1H_CV1 ADC2CV1H_CV1_10 #define ADC2CV1H_CV18_MASK 1 #define ADC2CV1H_CV19_MASK 2 #define ADC2CV1H_CV110_MASK 4 #define ADC2CV1H_CV111_MASK 8 #define ADC2CV1H_CV112_MASK 16 #define ADC2CV1H_CV113_MASK 32 #define ADC2CV1H_CV114_MASK 64 #define ADC2CV1H_CV115_MASK 128 #define ADC2CV1H_CV_18_MASK 3 #define ADC2CV1H_CV_18_BITNUM 0 #define ADC2CV1H_CV1_10_MASK 252 #define ADC2CV1H_CV1_10_BITNUM 2 /*** ADC2CV1L - Compare Value 1 Low Register; 0xFFFF8449 ***/ union { byte Byte; struct { byte CV10 :1; /* Compare Function Value 0 */ byte CV11 :1; /* Compare Function Value 1 */ byte CV12 :1; /* Compare Function Value 2 */ byte CV13 :1; /* Compare Function Value 3 */ byte CV14 :1; /* Compare Function Value 4 */ byte CV15 :1; /* Compare Function Value 5 */ byte CV16 :1; /* Compare Function Value 6 */ byte CV17 :1; /* Compare Function Value 7 */ } Bits; } ADC2CV1LSTR; #define ADC2CV1L _ADC2CV1.Overlap_STR.ADC2CV1LSTR.Byte #define ADC2CV1L_CV10 _ADC2CV1.Overlap_STR.ADC2CV1LSTR.Bits.CV10 #define ADC2CV1L_CV11 _ADC2CV1.Overlap_STR.ADC2CV1LSTR.Bits.CV11 #define ADC2CV1L_CV12 _ADC2CV1.Overlap_STR.ADC2CV1LSTR.Bits.CV12 #define ADC2CV1L_CV13 _ADC2CV1.Overlap_STR.ADC2CV1LSTR.Bits.CV13 #define ADC2CV1L_CV14 _ADC2CV1.Overlap_STR.ADC2CV1LSTR.Bits.CV14 #define ADC2CV1L_CV15 _ADC2CV1.Overlap_STR.ADC2CV1LSTR.Bits.CV15 #define ADC2CV1L_CV16 _ADC2CV1.Overlap_STR.ADC2CV1LSTR.Bits.CV16 #define ADC2CV1L_CV17 _ADC2CV1.Overlap_STR.ADC2CV1LSTR.Bits.CV17 #define ADC2CV1L_CV10_MASK 1 #define ADC2CV1L_CV11_MASK 2 #define ADC2CV1L_CV12_MASK 4 #define ADC2CV1L_CV13_MASK 8 #define ADC2CV1L_CV14_MASK 16 #define ADC2CV1L_CV15_MASK 32 #define ADC2CV1L_CV16_MASK 64 #define ADC2CV1L_CV17_MASK 128 } Overlap_STR; struct { word CV10 :1; /* Compare Function Value 0 */ word CV11 :1; /* Compare Function Value 1 */ word CV12 :1; /* Compare Function Value 2 */ word CV13 :1; /* Compare Function Value 3 */ word CV14 :1; /* Compare Function Value 4 */ word CV15 :1; /* Compare Function Value 5 */ word CV16 :1; /* Compare Function Value 6 */ word CV17 :1; /* Compare Function Value 7 */ word CV18 :1; /* Compare Function Value 8 */ word CV19 :1; /* Compare Function Value 9 */ word CV110 :1; /* Compare Function Value 10 */ word CV111 :1; /* Compare Function Value 11 */ word CV112 :1; /* Compare Function Value 12 */ word CV113 :1; /* Compare Function Value 13 */ word CV114 :1; /* Compare Function Value 14 */ word CV115 :1; /* Compare Function Value 15 */ } Bits; struct { word grpCV_10 :10; word grpCV1_10 :6; } MergedBits; } ADC2CV1STR; extern volatile ADC2CV1STR _ADC2CV1 @0xFFFF8448; #define ADC2CV1 _ADC2CV1.Word #define ADC2CV1_CV10 _ADC2CV1.Bits.CV10 #define ADC2CV1_CV11 _ADC2CV1.Bits.CV11 #define ADC2CV1_CV12 _ADC2CV1.Bits.CV12 #define ADC2CV1_CV13 _ADC2CV1.Bits.CV13 #define ADC2CV1_CV14 _ADC2CV1.Bits.CV14 #define ADC2CV1_CV15 _ADC2CV1.Bits.CV15 #define ADC2CV1_CV16 _ADC2CV1.Bits.CV16 #define ADC2CV1_CV17 _ADC2CV1.Bits.CV17 #define ADC2CV1_CV18 _ADC2CV1.Bits.CV18 #define ADC2CV1_CV19 _ADC2CV1.Bits.CV19 #define ADC2CV1_CV110 _ADC2CV1.Bits.CV110 #define ADC2CV1_CV111 _ADC2CV1.Bits.CV111 #define ADC2CV1_CV112 _ADC2CV1.Bits.CV112 #define ADC2CV1_CV113 _ADC2CV1.Bits.CV113 #define ADC2CV1_CV114 _ADC2CV1.Bits.CV114 #define ADC2CV1_CV115 _ADC2CV1.Bits.CV115 #define ADC2CV1_CV_10 _ADC2CV1.MergedBits.grpCV_10 #define ADC2CV1_CV1_10 _ADC2CV1.MergedBits.grpCV1_10 #define ADC2CV1_CV ADC2CV1_CV_10 #define ADC2CV1_CV1 ADC2CV1_CV1_10 #define ADC2CV1_CV10_MASK 1 #define ADC2CV1_CV11_MASK 2 #define ADC2CV1_CV12_MASK 4 #define ADC2CV1_CV13_MASK 8 #define ADC2CV1_CV14_MASK 16 #define ADC2CV1_CV15_MASK 32 #define ADC2CV1_CV16_MASK 64 #define ADC2CV1_CV17_MASK 128 #define ADC2CV1_CV18_MASK 256 #define ADC2CV1_CV19_MASK 512 #define ADC2CV1_CV110_MASK 1024 #define ADC2CV1_CV111_MASK 2048 #define ADC2CV1_CV112_MASK 4096 #define ADC2CV1_CV113_MASK 8192 #define ADC2CV1_CV114_MASK 16384 #define ADC2CV1_CV115_MASK 32768 #define ADC2CV1_CV_10_MASK 1023 #define ADC2CV1_CV_10_BITNUM 0 #define ADC2CV1_CV1_10_MASK 64512 #define ADC2CV1_CV1_10_BITNUM 10 /*** ADC2CV2 - Compare Value 2 Register; 0xFFFF844A ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC2CV2H - Compare Value 2 High Register; 0xFFFF844A ***/ union { byte Byte; struct { byte CV28 :1; /* Compare Function Value 8 */ byte CV29 :1; /* Compare Function Value 9 */ byte CV210 :1; /* Compare Function Value 10 */ byte CV211 :1; /* Compare Function Value 11 */ byte CV212 :1; /* Compare Function Value 12 */ byte CV213 :1; /* Compare Function Value 13 */ byte CV214 :1; /* Compare Function Value 14 */ byte CV215 :1; /* Compare Function Value 15 */ } Bits; struct { byte grpCV_28 :2; byte grpCV2_10 :6; } MergedBits; } ADC2CV2HSTR; #define ADC2CV2H _ADC2CV2.Overlap_STR.ADC2CV2HSTR.Byte #define ADC2CV2H_CV28 _ADC2CV2.Overlap_STR.ADC2CV2HSTR.Bits.CV28 #define ADC2CV2H_CV29 _ADC2CV2.Overlap_STR.ADC2CV2HSTR.Bits.CV29 #define ADC2CV2H_CV210 _ADC2CV2.Overlap_STR.ADC2CV2HSTR.Bits.CV210 #define ADC2CV2H_CV211 _ADC2CV2.Overlap_STR.ADC2CV2HSTR.Bits.CV211 #define ADC2CV2H_CV212 _ADC2CV2.Overlap_STR.ADC2CV2HSTR.Bits.CV212 #define ADC2CV2H_CV213 _ADC2CV2.Overlap_STR.ADC2CV2HSTR.Bits.CV213 #define ADC2CV2H_CV214 _ADC2CV2.Overlap_STR.ADC2CV2HSTR.Bits.CV214 #define ADC2CV2H_CV215 _ADC2CV2.Overlap_STR.ADC2CV2HSTR.Bits.CV215 #define ADC2CV2H_CV_28 _ADC2CV2.Overlap_STR.ADC2CV2HSTR.MergedBits.grpCV_28 #define ADC2CV2H_CV2_10 _ADC2CV2.Overlap_STR.ADC2CV2HSTR.MergedBits.grpCV2_10 #define ADC2CV2H_CV ADC2CV2H_CV_28 #define ADC2CV2H_CV2 ADC2CV2H_CV2_10 #define ADC2CV2H_CV28_MASK 1 #define ADC2CV2H_CV29_MASK 2 #define ADC2CV2H_CV210_MASK 4 #define ADC2CV2H_CV211_MASK 8 #define ADC2CV2H_CV212_MASK 16 #define ADC2CV2H_CV213_MASK 32 #define ADC2CV2H_CV214_MASK 64 #define ADC2CV2H_CV215_MASK 128 #define ADC2CV2H_CV_28_MASK 3 #define ADC2CV2H_CV_28_BITNUM 0 #define ADC2CV2H_CV2_10_MASK 252 #define ADC2CV2H_CV2_10_BITNUM 2 /*** ADC2CV2L - Compare Value 2 Low Register; 0xFFFF844B ***/ union { byte Byte; struct { byte CV20 :1; /* Compare Function Value 0 */ byte CV21 :1; /* Compare Function Value 1 */ byte CV22 :1; /* Compare Function Value 2 */ byte CV23 :1; /* Compare Function Value 3 */ byte CV24 :1; /* Compare Function Value 4 */ byte CV25 :1; /* Compare Function Value 5 */ byte CV26 :1; /* Compare Function Value 6 */ byte CV27 :1; /* Compare Function Value 7 */ } Bits; } ADC2CV2LSTR; #define ADC2CV2L _ADC2CV2.Overlap_STR.ADC2CV2LSTR.Byte #define ADC2CV2L_CV20 _ADC2CV2.Overlap_STR.ADC2CV2LSTR.Bits.CV20 #define ADC2CV2L_CV21 _ADC2CV2.Overlap_STR.ADC2CV2LSTR.Bits.CV21 #define ADC2CV2L_CV22 _ADC2CV2.Overlap_STR.ADC2CV2LSTR.Bits.CV22 #define ADC2CV2L_CV23 _ADC2CV2.Overlap_STR.ADC2CV2LSTR.Bits.CV23 #define ADC2CV2L_CV24 _ADC2CV2.Overlap_STR.ADC2CV2LSTR.Bits.CV24 #define ADC2CV2L_CV25 _ADC2CV2.Overlap_STR.ADC2CV2LSTR.Bits.CV25 #define ADC2CV2L_CV26 _ADC2CV2.Overlap_STR.ADC2CV2LSTR.Bits.CV26 #define ADC2CV2L_CV27 _ADC2CV2.Overlap_STR.ADC2CV2LSTR.Bits.CV27 #define ADC2CV2L_CV20_MASK 1 #define ADC2CV2L_CV21_MASK 2 #define ADC2CV2L_CV22_MASK 4 #define ADC2CV2L_CV23_MASK 8 #define ADC2CV2L_CV24_MASK 16 #define ADC2CV2L_CV25_MASK 32 #define ADC2CV2L_CV26_MASK 64 #define ADC2CV2L_CV27_MASK 128 } Overlap_STR; struct { word CV20 :1; /* Compare Function Value 0 */ word CV21 :1; /* Compare Function Value 1 */ word CV22 :1; /* Compare Function Value 2 */ word CV23 :1; /* Compare Function Value 3 */ word CV24 :1; /* Compare Function Value 4 */ word CV25 :1; /* Compare Function Value 5 */ word CV26 :1; /* Compare Function Value 6 */ word CV27 :1; /* Compare Function Value 7 */ word CV28 :1; /* Compare Function Value 8 */ word CV29 :1; /* Compare Function Value 9 */ word CV210 :1; /* Compare Function Value 10 */ word CV211 :1; /* Compare Function Value 11 */ word CV212 :1; /* Compare Function Value 12 */ word CV213 :1; /* Compare Function Value 13 */ word CV214 :1; /* Compare Function Value 14 */ word CV215 :1; /* Compare Function Value 15 */ } Bits; struct { word grpCV_20 :10; word grpCV2_10 :6; } MergedBits; } ADC2CV2STR; extern volatile ADC2CV2STR _ADC2CV2 @0xFFFF844A; #define ADC2CV2 _ADC2CV2.Word #define ADC2CV2_CV20 _ADC2CV2.Bits.CV20 #define ADC2CV2_CV21 _ADC2CV2.Bits.CV21 #define ADC2CV2_CV22 _ADC2CV2.Bits.CV22 #define ADC2CV2_CV23 _ADC2CV2.Bits.CV23 #define ADC2CV2_CV24 _ADC2CV2.Bits.CV24 #define ADC2CV2_CV25 _ADC2CV2.Bits.CV25 #define ADC2CV2_CV26 _ADC2CV2.Bits.CV26 #define ADC2CV2_CV27 _ADC2CV2.Bits.CV27 #define ADC2CV2_CV28 _ADC2CV2.Bits.CV28 #define ADC2CV2_CV29 _ADC2CV2.Bits.CV29 #define ADC2CV2_CV210 _ADC2CV2.Bits.CV210 #define ADC2CV2_CV211 _ADC2CV2.Bits.CV211 #define ADC2CV2_CV212 _ADC2CV2.Bits.CV212 #define ADC2CV2_CV213 _ADC2CV2.Bits.CV213 #define ADC2CV2_CV214 _ADC2CV2.Bits.CV214 #define ADC2CV2_CV215 _ADC2CV2.Bits.CV215 #define ADC2CV2_CV_20 _ADC2CV2.MergedBits.grpCV_20 #define ADC2CV2_CV2_10 _ADC2CV2.MergedBits.grpCV2_10 #define ADC2CV2_CV ADC2CV2_CV_20 #define ADC2CV2_CV2 ADC2CV2_CV2_10 #define ADC2CV2_CV20_MASK 1 #define ADC2CV2_CV21_MASK 2 #define ADC2CV2_CV22_MASK 4 #define ADC2CV2_CV23_MASK 8 #define ADC2CV2_CV24_MASK 16 #define ADC2CV2_CV25_MASK 32 #define ADC2CV2_CV26_MASK 64 #define ADC2CV2_CV27_MASK 128 #define ADC2CV2_CV28_MASK 256 #define ADC2CV2_CV29_MASK 512 #define ADC2CV2_CV210_MASK 1024 #define ADC2CV2_CV211_MASK 2048 #define ADC2CV2_CV212_MASK 4096 #define ADC2CV2_CV213_MASK 8192 #define ADC2CV2_CV214_MASK 16384 #define ADC2CV2_CV215_MASK 32768 #define ADC2CV2_CV_20_MASK 1023 #define ADC2CV2_CV_20_BITNUM 0 #define ADC2CV2_CV2_10_MASK 64512 #define ADC2CV2_CV2_10_BITNUM 10 /*** ADC2SC2 - Status and Control Register 2; 0xFFFF844C ***/ typedef union { byte Byte; struct { byte REFSEL0 :1; /* Voltage Reference Selection, bit 0 */ byte REFSEL1 :1; /* Voltage Reference Selection, bit 1 */ byte :1; byte ACREN :1; /* Compare Function Range Enable */ byte ACFGT :1; /* Compare Function Greater Than Enable */ byte ACFE :1; /* Compare Function Enable - ACFE is used to enable the compare function */ byte ADTRG :1; /* Conversion Trigger Select-ADTRG is used to select the type of trigger to be used for initiating a conversion */ byte ADACT :1; /* Conversion Active - ADACT indicates that a conversion is in progress. ADACT is set when a conversion is initiated and cleared when a conversion is completed or aborted */ } Bits; struct { byte grpREFSEL :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ADC2SC2STR; extern volatile ADC2SC2STR _ADC2SC2 @0xFFFF844C; #define ADC2SC2 _ADC2SC2.Byte #define ADC2SC2_REFSEL0 _ADC2SC2.Bits.REFSEL0 #define ADC2SC2_REFSEL1 _ADC2SC2.Bits.REFSEL1 #define ADC2SC2_ACREN _ADC2SC2.Bits.ACREN #define ADC2SC2_ACFGT _ADC2SC2.Bits.ACFGT #define ADC2SC2_ACFE _ADC2SC2.Bits.ACFE #define ADC2SC2_ADTRG _ADC2SC2.Bits.ADTRG #define ADC2SC2_ADACT _ADC2SC2.Bits.ADACT #define ADC2SC2_REFSEL _ADC2SC2.MergedBits.grpREFSEL #define ADC2SC2_REFSEL0_MASK 1 #define ADC2SC2_REFSEL1_MASK 2 #define ADC2SC2_ACREN_MASK 8 #define ADC2SC2_ACFGT_MASK 16 #define ADC2SC2_ACFE_MASK 32 #define ADC2SC2_ADTRG_MASK 64 #define ADC2SC2_ADACT_MASK 128 #define ADC2SC2_REFSEL_MASK 3 #define ADC2SC2_REFSEL_BITNUM 0 /*** ADC2SC3 - Status and Control Register 3; 0xFFFF844D ***/ typedef union { byte Byte; struct { byte AVGS0 :1; /* Hardware Average select, bit 0 */ byte AVGS1 :1; /* Hardware Average select, bit 1 */ byte AVGE :1; /* Hardware average enable - AVGE enables the hardware average function of the ADC */ byte ADCO :1; /* Continuous Conversion Enable - ADCO enables continuous conversions */ byte :1; byte :1; byte CALF :1; /* Calibration Failed Flag - CALF displays the result of the calibration sequence */ byte CAL :1; /* Calibration - CAL begins the calibration sequence when set */ } Bits; struct { byte grpAVGS :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ADC2SC3STR; extern volatile ADC2SC3STR _ADC2SC3 @0xFFFF844D; #define ADC2SC3 _ADC2SC3.Byte #define ADC2SC3_AVGS0 _ADC2SC3.Bits.AVGS0 #define ADC2SC3_AVGS1 _ADC2SC3.Bits.AVGS1 #define ADC2SC3_AVGE _ADC2SC3.Bits.AVGE #define ADC2SC3_ADCO _ADC2SC3.Bits.ADCO #define ADC2SC3_CALF _ADC2SC3.Bits.CALF #define ADC2SC3_CAL _ADC2SC3.Bits.CAL #define ADC2SC3_AVGS _ADC2SC3.MergedBits.grpAVGS #define ADC2SC3_AVGS0_MASK 1 #define ADC2SC3_AVGS1_MASK 2 #define ADC2SC3_AVGE_MASK 4 #define ADC2SC3_ADCO_MASK 8 #define ADC2SC3_CALF_MASK 64 #define ADC2SC3_CAL_MASK 128 #define ADC2SC3_AVGS_MASK 3 #define ADC2SC3_AVGS_BITNUM 0 /*** ADC2OFS - Offset Correction Register; 0xFFFF844E ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC2OFSH - Offset Correction High Register; 0xFFFF844E ***/ union { byte Byte; struct { byte OFS8 :1; /* Offset error correction value bit 8 */ byte OFS9 :1; /* Offset error correction value bit 9 */ byte OFS10 :1; /* Offset error correction value bit 10 */ byte OFS11 :1; /* Offset error correction value bit 11 */ byte OFS12 :1; /* Offset error correction value bit 12 */ byte OFS13 :1; /* Offset error correction value bit 13 */ byte OFS14 :1; /* Offset error correction value bit 14 */ byte OFS15 :1; /* Offset error correction value bit 15 */ } Bits; } ADC2OFSHSTR; #define ADC2OFSH _ADC2OFS.Overlap_STR.ADC2OFSHSTR.Byte #define ADC2OFSH_OFS8 _ADC2OFS.Overlap_STR.ADC2OFSHSTR.Bits.OFS8 #define ADC2OFSH_OFS9 _ADC2OFS.Overlap_STR.ADC2OFSHSTR.Bits.OFS9 #define ADC2OFSH_OFS10 _ADC2OFS.Overlap_STR.ADC2OFSHSTR.Bits.OFS10 #define ADC2OFSH_OFS11 _ADC2OFS.Overlap_STR.ADC2OFSHSTR.Bits.OFS11 #define ADC2OFSH_OFS12 _ADC2OFS.Overlap_STR.ADC2OFSHSTR.Bits.OFS12 #define ADC2OFSH_OFS13 _ADC2OFS.Overlap_STR.ADC2OFSHSTR.Bits.OFS13 #define ADC2OFSH_OFS14 _ADC2OFS.Overlap_STR.ADC2OFSHSTR.Bits.OFS14 #define ADC2OFSH_OFS15 _ADC2OFS.Overlap_STR.ADC2OFSHSTR.Bits.OFS15 #define ADC2OFSH_OFS8_MASK 1 #define ADC2OFSH_OFS9_MASK 2 #define ADC2OFSH_OFS10_MASK 4 #define ADC2OFSH_OFS11_MASK 8 #define ADC2OFSH_OFS12_MASK 16 #define ADC2OFSH_OFS13_MASK 32 #define ADC2OFSH_OFS14_MASK 64 #define ADC2OFSH_OFS15_MASK 128 /*** ADC2OFSL - Offset Correction Low Register; 0xFFFF844F ***/ union { byte Byte; struct { byte OFS0 :1; /* Offset error correction value bit 0 */ byte OFS1 :1; /* Offset error correction value bit 1 */ byte OFS2 :1; /* Offset error correction value bit 2 */ byte OFS3 :1; /* Offset error correction value bit 3 */ byte OFS4 :1; /* Offset error correction value bit 4 */ byte OFS5 :1; /* Offset error correction value bit 5 */ byte OFS6 :1; /* Offset error correction value bit 6 */ byte OFS7 :1; /* Offset error correction value bit 7 */ } Bits; } ADC2OFSLSTR; #define ADC2OFSL _ADC2OFS.Overlap_STR.ADC2OFSLSTR.Byte #define ADC2OFSL_OFS0 _ADC2OFS.Overlap_STR.ADC2OFSLSTR.Bits.OFS0 #define ADC2OFSL_OFS1 _ADC2OFS.Overlap_STR.ADC2OFSLSTR.Bits.OFS1 #define ADC2OFSL_OFS2 _ADC2OFS.Overlap_STR.ADC2OFSLSTR.Bits.OFS2 #define ADC2OFSL_OFS3 _ADC2OFS.Overlap_STR.ADC2OFSLSTR.Bits.OFS3 #define ADC2OFSL_OFS4 _ADC2OFS.Overlap_STR.ADC2OFSLSTR.Bits.OFS4 #define ADC2OFSL_OFS5 _ADC2OFS.Overlap_STR.ADC2OFSLSTR.Bits.OFS5 #define ADC2OFSL_OFS6 _ADC2OFS.Overlap_STR.ADC2OFSLSTR.Bits.OFS6 #define ADC2OFSL_OFS7 _ADC2OFS.Overlap_STR.ADC2OFSLSTR.Bits.OFS7 #define ADC2OFSL_OFS0_MASK 1 #define ADC2OFSL_OFS1_MASK 2 #define ADC2OFSL_OFS2_MASK 4 #define ADC2OFSL_OFS3_MASK 8 #define ADC2OFSL_OFS4_MASK 16 #define ADC2OFSL_OFS5_MASK 32 #define ADC2OFSL_OFS6_MASK 64 #define ADC2OFSL_OFS7_MASK 128 } Overlap_STR; struct { word OFS0 :1; /* Offset error correction value bit 0 */ word OFS1 :1; /* Offset error correction value bit 1 */ word OFS2 :1; /* Offset error correction value bit 2 */ word OFS3 :1; /* Offset error correction value bit 3 */ word OFS4 :1; /* Offset error correction value bit 4 */ word OFS5 :1; /* Offset error correction value bit 5 */ word OFS6 :1; /* Offset error correction value bit 6 */ word OFS7 :1; /* Offset error correction value bit 7 */ word OFS8 :1; /* Offset error correction value bit 8 */ word OFS9 :1; /* Offset error correction value bit 9 */ word OFS10 :1; /* Offset error correction value bit 10 */ word OFS11 :1; /* Offset error correction value bit 11 */ word OFS12 :1; /* Offset error correction value bit 12 */ word OFS13 :1; /* Offset error correction value bit 13 */ word OFS14 :1; /* Offset error correction value bit 14 */ word OFS15 :1; /* Offset error correction value bit 15 */ } Bits; } ADC2OFSSTR; extern volatile ADC2OFSSTR _ADC2OFS @0xFFFF844E; #define ADC2OFS _ADC2OFS.Word #define ADC2OFS_OFS0 _ADC2OFS.Bits.OFS0 #define ADC2OFS_OFS1 _ADC2OFS.Bits.OFS1 #define ADC2OFS_OFS2 _ADC2OFS.Bits.OFS2 #define ADC2OFS_OFS3 _ADC2OFS.Bits.OFS3 #define ADC2OFS_OFS4 _ADC2OFS.Bits.OFS4 #define ADC2OFS_OFS5 _ADC2OFS.Bits.OFS5 #define ADC2OFS_OFS6 _ADC2OFS.Bits.OFS6 #define ADC2OFS_OFS7 _ADC2OFS.Bits.OFS7 #define ADC2OFS_OFS8 _ADC2OFS.Bits.OFS8 #define ADC2OFS_OFS9 _ADC2OFS.Bits.OFS9 #define ADC2OFS_OFS10 _ADC2OFS.Bits.OFS10 #define ADC2OFS_OFS11 _ADC2OFS.Bits.OFS11 #define ADC2OFS_OFS12 _ADC2OFS.Bits.OFS12 #define ADC2OFS_OFS13 _ADC2OFS.Bits.OFS13 #define ADC2OFS_OFS14 _ADC2OFS.Bits.OFS14 #define ADC2OFS_OFS15 _ADC2OFS.Bits.OFS15 #define ADC2OFS_OFS0_MASK 1 #define ADC2OFS_OFS1_MASK 2 #define ADC2OFS_OFS2_MASK 4 #define ADC2OFS_OFS3_MASK 8 #define ADC2OFS_OFS4_MASK 16 #define ADC2OFS_OFS5_MASK 32 #define ADC2OFS_OFS6_MASK 64 #define ADC2OFS_OFS7_MASK 128 #define ADC2OFS_OFS8_MASK 256 #define ADC2OFS_OFS9_MASK 512 #define ADC2OFS_OFS10_MASK 1024 #define ADC2OFS_OFS11_MASK 2048 #define ADC2OFS_OFS12_MASK 4096 #define ADC2OFS_OFS13_MASK 8192 #define ADC2OFS_OFS14_MASK 16384 #define ADC2OFS_OFS15_MASK 32768 /*** ADC2PG - Plus-Side Gain Register; 0xFFFF8450 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC2PGH - Plus-Side Gain High Register; 0xFFFF8450 ***/ union { byte Byte; struct { byte PG8 :1; /* Gain error correction for the plus-side input value bit 8 */ byte PG9 :1; /* Gain error correction for the plus-side input value bit 9 */ byte PG10 :1; /* Gain error correction for the plus-side input value bit 10 */ byte PG11 :1; /* Gain error correction for the plus-side input value bit 11 */ byte PG12 :1; /* Gain error correction for the plus-side input value bit 12 */ byte PG13 :1; /* Gain error correction for the plus-side input value bit 13 */ byte PG14 :1; /* Gain error correction for the plus-side input value bit 14 */ byte PG15 :1; /* Gain error correction for the plus-side input value bit 15 */ } Bits; } ADC2PGHSTR; #define ADC2PGH _ADC2PG.Overlap_STR.ADC2PGHSTR.Byte #define ADC2PGH_PG8 _ADC2PG.Overlap_STR.ADC2PGHSTR.Bits.PG8 #define ADC2PGH_PG9 _ADC2PG.Overlap_STR.ADC2PGHSTR.Bits.PG9 #define ADC2PGH_PG10 _ADC2PG.Overlap_STR.ADC2PGHSTR.Bits.PG10 #define ADC2PGH_PG11 _ADC2PG.Overlap_STR.ADC2PGHSTR.Bits.PG11 #define ADC2PGH_PG12 _ADC2PG.Overlap_STR.ADC2PGHSTR.Bits.PG12 #define ADC2PGH_PG13 _ADC2PG.Overlap_STR.ADC2PGHSTR.Bits.PG13 #define ADC2PGH_PG14 _ADC2PG.Overlap_STR.ADC2PGHSTR.Bits.PG14 #define ADC2PGH_PG15 _ADC2PG.Overlap_STR.ADC2PGHSTR.Bits.PG15 #define ADC2PGH_PG8_MASK 1 #define ADC2PGH_PG9_MASK 2 #define ADC2PGH_PG10_MASK 4 #define ADC2PGH_PG11_MASK 8 #define ADC2PGH_PG12_MASK 16 #define ADC2PGH_PG13_MASK 32 #define ADC2PGH_PG14_MASK 64 #define ADC2PGH_PG15_MASK 128 /*** ADC2PGL - Plus-Side Gain Low Register; 0xFFFF8451 ***/ union { byte Byte; struct { byte PG0 :1; /* Gain error correction for the plus-side input value bit 0 */ byte PG1 :1; /* Gain error correction for the plus-side input value bit 1 */ byte PG2 :1; /* Gain error correction for the plus-side input value bit 2 */ byte PG3 :1; /* Gain error correction for the plus-side input value bit 3 */ byte PG4 :1; /* Gain error correction for the plus-side input value bit 4 */ byte PG5 :1; /* Gain error correction for the plus-side input value bit 5 */ byte PG6 :1; /* Gain error correction for the plus-side input value bit 6 */ byte PG7 :1; /* Gain error correction for the plus-side input value bit 7 */ } Bits; } ADC2PGLSTR; #define ADC2PGL _ADC2PG.Overlap_STR.ADC2PGLSTR.Byte #define ADC2PGL_PG0 _ADC2PG.Overlap_STR.ADC2PGLSTR.Bits.PG0 #define ADC2PGL_PG1 _ADC2PG.Overlap_STR.ADC2PGLSTR.Bits.PG1 #define ADC2PGL_PG2 _ADC2PG.Overlap_STR.ADC2PGLSTR.Bits.PG2 #define ADC2PGL_PG3 _ADC2PG.Overlap_STR.ADC2PGLSTR.Bits.PG3 #define ADC2PGL_PG4 _ADC2PG.Overlap_STR.ADC2PGLSTR.Bits.PG4 #define ADC2PGL_PG5 _ADC2PG.Overlap_STR.ADC2PGLSTR.Bits.PG5 #define ADC2PGL_PG6 _ADC2PG.Overlap_STR.ADC2PGLSTR.Bits.PG6 #define ADC2PGL_PG7 _ADC2PG.Overlap_STR.ADC2PGLSTR.Bits.PG7 #define ADC2PGL_PG0_MASK 1 #define ADC2PGL_PG1_MASK 2 #define ADC2PGL_PG2_MASK 4 #define ADC2PGL_PG3_MASK 8 #define ADC2PGL_PG4_MASK 16 #define ADC2PGL_PG5_MASK 32 #define ADC2PGL_PG6_MASK 64 #define ADC2PGL_PG7_MASK 128 } Overlap_STR; struct { word PG0 :1; /* Gain error correction for the plus-side input value bit 0 */ word PG1 :1; /* Gain error correction for the plus-side input value bit 1 */ word PG2 :1; /* Gain error correction for the plus-side input value bit 2 */ word PG3 :1; /* Gain error correction for the plus-side input value bit 3 */ word PG4 :1; /* Gain error correction for the plus-side input value bit 4 */ word PG5 :1; /* Gain error correction for the plus-side input value bit 5 */ word PG6 :1; /* Gain error correction for the plus-side input value bit 6 */ word PG7 :1; /* Gain error correction for the plus-side input value bit 7 */ word PG8 :1; /* Gain error correction for the plus-side input value bit 8 */ word PG9 :1; /* Gain error correction for the plus-side input value bit 9 */ word PG10 :1; /* Gain error correction for the plus-side input value bit 10 */ word PG11 :1; /* Gain error correction for the plus-side input value bit 11 */ word PG12 :1; /* Gain error correction for the plus-side input value bit 12 */ word PG13 :1; /* Gain error correction for the plus-side input value bit 13 */ word PG14 :1; /* Gain error correction for the plus-side input value bit 14 */ word PG15 :1; /* Gain error correction for the plus-side input value bit 15 */ } Bits; } ADC2PGSTR; extern volatile ADC2PGSTR _ADC2PG @0xFFFF8450; #define ADC2PG _ADC2PG.Word #define ADC2PG_PG0 _ADC2PG.Bits.PG0 #define ADC2PG_PG1 _ADC2PG.Bits.PG1 #define ADC2PG_PG2 _ADC2PG.Bits.PG2 #define ADC2PG_PG3 _ADC2PG.Bits.PG3 #define ADC2PG_PG4 _ADC2PG.Bits.PG4 #define ADC2PG_PG5 _ADC2PG.Bits.PG5 #define ADC2PG_PG6 _ADC2PG.Bits.PG6 #define ADC2PG_PG7 _ADC2PG.Bits.PG7 #define ADC2PG_PG8 _ADC2PG.Bits.PG8 #define ADC2PG_PG9 _ADC2PG.Bits.PG9 #define ADC2PG_PG10 _ADC2PG.Bits.PG10 #define ADC2PG_PG11 _ADC2PG.Bits.PG11 #define ADC2PG_PG12 _ADC2PG.Bits.PG12 #define ADC2PG_PG13 _ADC2PG.Bits.PG13 #define ADC2PG_PG14 _ADC2PG.Bits.PG14 #define ADC2PG_PG15 _ADC2PG.Bits.PG15 #define ADC2PG_PG0_MASK 1 #define ADC2PG_PG1_MASK 2 #define ADC2PG_PG2_MASK 4 #define ADC2PG_PG3_MASK 8 #define ADC2PG_PG4_MASK 16 #define ADC2PG_PG5_MASK 32 #define ADC2PG_PG6_MASK 64 #define ADC2PG_PG7_MASK 128 #define ADC2PG_PG8_MASK 256 #define ADC2PG_PG9_MASK 512 #define ADC2PG_PG10_MASK 1024 #define ADC2PG_PG11_MASK 2048 #define ADC2PG_PG12_MASK 4096 #define ADC2PG_PG13_MASK 8192 #define ADC2PG_PG14_MASK 16384 #define ADC2PG_PG15_MASK 32768 /*** ADC2MG - Minus-Side Gain Register; 0xFFFF8452 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC2MGH - Minus-Side Gain High Register; 0xFFFF8452 ***/ union { byte Byte; struct { byte MG8 :1; /* Gain error correction for the minus-side input value bit 8 */ byte MG9 :1; /* Gain error correction for the minus-side input value bit 9 */ byte MG10 :1; /* Gain error correction for the minus-side input value bit 10 */ byte MG11 :1; /* Gain error correction for the minus-side input value bit 11 */ byte MG12 :1; /* Gain error correction for the minus-side input value bit 12 */ byte MG13 :1; /* Gain error correction for the minus-side input value bit 13 */ byte MG14 :1; /* Gain error correction for the minus-side input value bit 14 */ byte MG15 :1; /* Gain error correction for the minus-side input value bit 15 */ } Bits; } ADC2MGHSTR; #define ADC2MGH _ADC2MG.Overlap_STR.ADC2MGHSTR.Byte #define ADC2MGH_MG8 _ADC2MG.Overlap_STR.ADC2MGHSTR.Bits.MG8 #define ADC2MGH_MG9 _ADC2MG.Overlap_STR.ADC2MGHSTR.Bits.MG9 #define ADC2MGH_MG10 _ADC2MG.Overlap_STR.ADC2MGHSTR.Bits.MG10 #define ADC2MGH_MG11 _ADC2MG.Overlap_STR.ADC2MGHSTR.Bits.MG11 #define ADC2MGH_MG12 _ADC2MG.Overlap_STR.ADC2MGHSTR.Bits.MG12 #define ADC2MGH_MG13 _ADC2MG.Overlap_STR.ADC2MGHSTR.Bits.MG13 #define ADC2MGH_MG14 _ADC2MG.Overlap_STR.ADC2MGHSTR.Bits.MG14 #define ADC2MGH_MG15 _ADC2MG.Overlap_STR.ADC2MGHSTR.Bits.MG15 #define ADC2MGH_MG8_MASK 1 #define ADC2MGH_MG9_MASK 2 #define ADC2MGH_MG10_MASK 4 #define ADC2MGH_MG11_MASK 8 #define ADC2MGH_MG12_MASK 16 #define ADC2MGH_MG13_MASK 32 #define ADC2MGH_MG14_MASK 64 #define ADC2MGH_MG15_MASK 128 /*** ADC2MGL - Minus-Side Gain Low Register; 0xFFFF8453 ***/ union { byte Byte; struct { byte MG0 :1; /* Gain error correction for the minus-side input value bit 0 */ byte MG1 :1; /* Gain error correction for the minus-side input value bit 1 */ byte MG2 :1; /* Gain error correction for the minus-side input value bit 2 */ byte MG3 :1; /* Gain error correction for the minus-side input value bit 3 */ byte MG4 :1; /* Gain error correction for the minus-side input value bit 4 */ byte MG5 :1; /* Gain error correction for the minus-side input value bit 5 */ byte MG6 :1; /* Gain error correction for the minus-side input value bit 6 */ byte MG7 :1; /* Gain error correction for the minus-side input value bit 7 */ } Bits; } ADC2MGLSTR; #define ADC2MGL _ADC2MG.Overlap_STR.ADC2MGLSTR.Byte #define ADC2MGL_MG0 _ADC2MG.Overlap_STR.ADC2MGLSTR.Bits.MG0 #define ADC2MGL_MG1 _ADC2MG.Overlap_STR.ADC2MGLSTR.Bits.MG1 #define ADC2MGL_MG2 _ADC2MG.Overlap_STR.ADC2MGLSTR.Bits.MG2 #define ADC2MGL_MG3 _ADC2MG.Overlap_STR.ADC2MGLSTR.Bits.MG3 #define ADC2MGL_MG4 _ADC2MG.Overlap_STR.ADC2MGLSTR.Bits.MG4 #define ADC2MGL_MG5 _ADC2MG.Overlap_STR.ADC2MGLSTR.Bits.MG5 #define ADC2MGL_MG6 _ADC2MG.Overlap_STR.ADC2MGLSTR.Bits.MG6 #define ADC2MGL_MG7 _ADC2MG.Overlap_STR.ADC2MGLSTR.Bits.MG7 #define ADC2MGL_MG0_MASK 1 #define ADC2MGL_MG1_MASK 2 #define ADC2MGL_MG2_MASK 4 #define ADC2MGL_MG3_MASK 8 #define ADC2MGL_MG4_MASK 16 #define ADC2MGL_MG5_MASK 32 #define ADC2MGL_MG6_MASK 64 #define ADC2MGL_MG7_MASK 128 } Overlap_STR; struct { word MG0 :1; /* Gain error correction for the minus-side input value bit 0 */ word MG1 :1; /* Gain error correction for the minus-side input value bit 1 */ word MG2 :1; /* Gain error correction for the minus-side input value bit 2 */ word MG3 :1; /* Gain error correction for the minus-side input value bit 3 */ word MG4 :1; /* Gain error correction for the minus-side input value bit 4 */ word MG5 :1; /* Gain error correction for the minus-side input value bit 5 */ word MG6 :1; /* Gain error correction for the minus-side input value bit 6 */ word MG7 :1; /* Gain error correction for the minus-side input value bit 7 */ word MG8 :1; /* Gain error correction for the minus-side input value bit 8 */ word MG9 :1; /* Gain error correction for the minus-side input value bit 9 */ word MG10 :1; /* Gain error correction for the minus-side input value bit 10 */ word MG11 :1; /* Gain error correction for the minus-side input value bit 11 */ word MG12 :1; /* Gain error correction for the minus-side input value bit 12 */ word MG13 :1; /* Gain error correction for the minus-side input value bit 13 */ word MG14 :1; /* Gain error correction for the minus-side input value bit 14 */ word MG15 :1; /* Gain error correction for the minus-side input value bit 15 */ } Bits; } ADC2MGSTR; extern volatile ADC2MGSTR _ADC2MG @0xFFFF8452; #define ADC2MG _ADC2MG.Word #define ADC2MG_MG0 _ADC2MG.Bits.MG0 #define ADC2MG_MG1 _ADC2MG.Bits.MG1 #define ADC2MG_MG2 _ADC2MG.Bits.MG2 #define ADC2MG_MG3 _ADC2MG.Bits.MG3 #define ADC2MG_MG4 _ADC2MG.Bits.MG4 #define ADC2MG_MG5 _ADC2MG.Bits.MG5 #define ADC2MG_MG6 _ADC2MG.Bits.MG6 #define ADC2MG_MG7 _ADC2MG.Bits.MG7 #define ADC2MG_MG8 _ADC2MG.Bits.MG8 #define ADC2MG_MG9 _ADC2MG.Bits.MG9 #define ADC2MG_MG10 _ADC2MG.Bits.MG10 #define ADC2MG_MG11 _ADC2MG.Bits.MG11 #define ADC2MG_MG12 _ADC2MG.Bits.MG12 #define ADC2MG_MG13 _ADC2MG.Bits.MG13 #define ADC2MG_MG14 _ADC2MG.Bits.MG14 #define ADC2MG_MG15 _ADC2MG.Bits.MG15 #define ADC2MG_MG0_MASK 1 #define ADC2MG_MG1_MASK 2 #define ADC2MG_MG2_MASK 4 #define ADC2MG_MG3_MASK 8 #define ADC2MG_MG4_MASK 16 #define ADC2MG_MG5_MASK 32 #define ADC2MG_MG6_MASK 64 #define ADC2MG_MG7_MASK 128 #define ADC2MG_MG8_MASK 256 #define ADC2MG_MG9_MASK 512 #define ADC2MG_MG10_MASK 1024 #define ADC2MG_MG11_MASK 2048 #define ADC2MG_MG12_MASK 4096 #define ADC2MG_MG13_MASK 8192 #define ADC2MG_MG14_MASK 16384 #define ADC2MG_MG15_MASK 32768 /*** ADC2CLPD - Plus-Side General Calibration Value D Register; 0xFFFF8454 ***/ typedef union { byte Byte; struct { byte CLPD0 :1; /* Plus-Side General Calibration Value D bit 0 */ byte CLPD1 :1; /* Plus-Side General Calibration Value D bit 1 */ byte CLPD2 :1; /* Plus-Side General Calibration Value D bit 2 */ byte CLPD3 :1; /* Plus-Side General Calibration Value D bit 3 */ byte CLPD4 :1; /* Plus-Side General Calibration Value D bit 4 */ byte CLPD5 :1; /* Plus-Side General Calibration Value D bit 5 */ byte :1; byte :1; } Bits; struct { byte grpCLPD :6; byte :1; byte :1; } MergedBits; } ADC2CLPDSTR; extern volatile ADC2CLPDSTR _ADC2CLPD @0xFFFF8454; #define ADC2CLPD _ADC2CLPD.Byte #define ADC2CLPD_CLPD0 _ADC2CLPD.Bits.CLPD0 #define ADC2CLPD_CLPD1 _ADC2CLPD.Bits.CLPD1 #define ADC2CLPD_CLPD2 _ADC2CLPD.Bits.CLPD2 #define ADC2CLPD_CLPD3 _ADC2CLPD.Bits.CLPD3 #define ADC2CLPD_CLPD4 _ADC2CLPD.Bits.CLPD4 #define ADC2CLPD_CLPD5 _ADC2CLPD.Bits.CLPD5 #define ADC2CLPD_CLPD _ADC2CLPD.MergedBits.grpCLPD #define ADC2CLPD_CLPD0_MASK 1 #define ADC2CLPD_CLPD1_MASK 2 #define ADC2CLPD_CLPD2_MASK 4 #define ADC2CLPD_CLPD3_MASK 8 #define ADC2CLPD_CLPD4_MASK 16 #define ADC2CLPD_CLPD5_MASK 32 #define ADC2CLPD_CLPD_MASK 63 #define ADC2CLPD_CLPD_BITNUM 0 /*** ADC2CLPS - Plus-Side General Calibration Value S Register; 0xFFFF8455 ***/ typedef union { byte Byte; struct { byte CLPS0 :1; /* Plus-Side General Calibration Value S bit 0 */ byte CLPS1 :1; /* Plus-Side General Calibration Value S bit 1 */ byte CLPS2 :1; /* Plus-Side General Calibration Value S bit 2 */ byte CLPS3 :1; /* Plus-Side General Calibration Value S bit 3 */ byte CLPS4 :1; /* Plus-Side General Calibration Value S bit 4 */ byte CLPS5 :1; /* Plus-Side General Calibration Value S bit 5 */ byte :1; byte :1; } Bits; struct { byte grpCLPS :6; byte :1; byte :1; } MergedBits; } ADC2CLPSSTR; extern volatile ADC2CLPSSTR _ADC2CLPS @0xFFFF8455; #define ADC2CLPS _ADC2CLPS.Byte #define ADC2CLPS_CLPS0 _ADC2CLPS.Bits.CLPS0 #define ADC2CLPS_CLPS1 _ADC2CLPS.Bits.CLPS1 #define ADC2CLPS_CLPS2 _ADC2CLPS.Bits.CLPS2 #define ADC2CLPS_CLPS3 _ADC2CLPS.Bits.CLPS3 #define ADC2CLPS_CLPS4 _ADC2CLPS.Bits.CLPS4 #define ADC2CLPS_CLPS5 _ADC2CLPS.Bits.CLPS5 #define ADC2CLPS_CLPS _ADC2CLPS.MergedBits.grpCLPS #define ADC2CLPS_CLPS0_MASK 1 #define ADC2CLPS_CLPS1_MASK 2 #define ADC2CLPS_CLPS2_MASK 4 #define ADC2CLPS_CLPS3_MASK 8 #define ADC2CLPS_CLPS4_MASK 16 #define ADC2CLPS_CLPS5_MASK 32 #define ADC2CLPS_CLPS_MASK 63 #define ADC2CLPS_CLPS_BITNUM 0 /*** ADC2CLP4 - Plus-Side General Calibration Value 4 Register; 0xFFFF8456 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC2CLP4H - Plus-Side General Calibration Value 4 High Register; 0xFFFF8456 ***/ union { byte Byte; struct { byte CLP48 :1; /* Plus-Side General Calibration Value 4 bit 8 */ byte CLP49 :1; /* Plus-Side General Calibration Value 4 bit 9 */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpCLP_48 :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ADC2CLP4HSTR; #define ADC2CLP4H _ADC2CLP4.Overlap_STR.ADC2CLP4HSTR.Byte #define ADC2CLP4H_CLP48 _ADC2CLP4.Overlap_STR.ADC2CLP4HSTR.Bits.CLP48 #define ADC2CLP4H_CLP49 _ADC2CLP4.Overlap_STR.ADC2CLP4HSTR.Bits.CLP49 #define ADC2CLP4H_CLP_48 _ADC2CLP4.Overlap_STR.ADC2CLP4HSTR.MergedBits.grpCLP_48 #define ADC2CLP4H_CLP ADC2CLP4H_CLP_48 #define ADC2CLP4H_CLP48_MASK 1 #define ADC2CLP4H_CLP49_MASK 2 #define ADC2CLP4H_CLP_48_MASK 3 #define ADC2CLP4H_CLP_48_BITNUM 0 /*** ADC2CLP4L - Plus-Side General Calibration Value 4 Low Register; 0xFFFF8457 ***/ union { byte Byte; struct { byte CLP40 :1; /* Plus-Side General Calibration Value 4 bit 0 */ byte CLP41 :1; /* Plus-Side General Calibration Value 4 bit 1 */ byte CLP42 :1; /* Plus-Side General Calibration Value 4 bit 2 */ byte CLP43 :1; /* Plus-Side General Calibration Value 4 bit 3 */ byte CLP44 :1; /* Plus-Side General Calibration Value 4 bit 4 */ byte CLP45 :1; /* Plus-Side General Calibration Value 4 bit 5 */ byte CLP46 :1; /* Plus-Side General Calibration Value 4 bit 6 */ byte CLP47 :1; /* Plus-Side General Calibration Value 4 bit 7 */ } Bits; } ADC2CLP4LSTR; #define ADC2CLP4L _ADC2CLP4.Overlap_STR.ADC2CLP4LSTR.Byte #define ADC2CLP4L_CLP40 _ADC2CLP4.Overlap_STR.ADC2CLP4LSTR.Bits.CLP40 #define ADC2CLP4L_CLP41 _ADC2CLP4.Overlap_STR.ADC2CLP4LSTR.Bits.CLP41 #define ADC2CLP4L_CLP42 _ADC2CLP4.Overlap_STR.ADC2CLP4LSTR.Bits.CLP42 #define ADC2CLP4L_CLP43 _ADC2CLP4.Overlap_STR.ADC2CLP4LSTR.Bits.CLP43 #define ADC2CLP4L_CLP44 _ADC2CLP4.Overlap_STR.ADC2CLP4LSTR.Bits.CLP44 #define ADC2CLP4L_CLP45 _ADC2CLP4.Overlap_STR.ADC2CLP4LSTR.Bits.CLP45 #define ADC2CLP4L_CLP46 _ADC2CLP4.Overlap_STR.ADC2CLP4LSTR.Bits.CLP46 #define ADC2CLP4L_CLP47 _ADC2CLP4.Overlap_STR.ADC2CLP4LSTR.Bits.CLP47 #define ADC2CLP4L_CLP40_MASK 1 #define ADC2CLP4L_CLP41_MASK 2 #define ADC2CLP4L_CLP42_MASK 4 #define ADC2CLP4L_CLP43_MASK 8 #define ADC2CLP4L_CLP44_MASK 16 #define ADC2CLP4L_CLP45_MASK 32 #define ADC2CLP4L_CLP46_MASK 64 #define ADC2CLP4L_CLP47_MASK 128 } Overlap_STR; struct { word CLP40 :1; /* Plus-Side General Calibration Value 4 bit 0 */ word CLP41 :1; /* Plus-Side General Calibration Value 4 bit 1 */ word CLP42 :1; /* Plus-Side General Calibration Value 4 bit 2 */ word CLP43 :1; /* Plus-Side General Calibration Value 4 bit 3 */ word CLP44 :1; /* Plus-Side General Calibration Value 4 bit 4 */ word CLP45 :1; /* Plus-Side General Calibration Value 4 bit 5 */ word CLP46 :1; /* Plus-Side General Calibration Value 4 bit 6 */ word CLP47 :1; /* Plus-Side General Calibration Value 4 bit 7 */ word CLP48 :1; /* Plus-Side General Calibration Value 4 bit 8 */ word CLP49 :1; /* Plus-Side General Calibration Value 4 bit 9 */ word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpCLP_40 :10; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } ADC2CLP4STR; extern volatile ADC2CLP4STR _ADC2CLP4 @0xFFFF8456; #define ADC2CLP4 _ADC2CLP4.Word #define ADC2CLP4_CLP40 _ADC2CLP4.Bits.CLP40 #define ADC2CLP4_CLP41 _ADC2CLP4.Bits.CLP41 #define ADC2CLP4_CLP42 _ADC2CLP4.Bits.CLP42 #define ADC2CLP4_CLP43 _ADC2CLP4.Bits.CLP43 #define ADC2CLP4_CLP44 _ADC2CLP4.Bits.CLP44 #define ADC2CLP4_CLP45 _ADC2CLP4.Bits.CLP45 #define ADC2CLP4_CLP46 _ADC2CLP4.Bits.CLP46 #define ADC2CLP4_CLP47 _ADC2CLP4.Bits.CLP47 #define ADC2CLP4_CLP48 _ADC2CLP4.Bits.CLP48 #define ADC2CLP4_CLP49 _ADC2CLP4.Bits.CLP49 #define ADC2CLP4_CLP_40 _ADC2CLP4.MergedBits.grpCLP_40 #define ADC2CLP4_CLP ADC2CLP4_CLP_40 #define ADC2CLP4_CLP40_MASK 1 #define ADC2CLP4_CLP41_MASK 2 #define ADC2CLP4_CLP42_MASK 4 #define ADC2CLP4_CLP43_MASK 8 #define ADC2CLP4_CLP44_MASK 16 #define ADC2CLP4_CLP45_MASK 32 #define ADC2CLP4_CLP46_MASK 64 #define ADC2CLP4_CLP47_MASK 128 #define ADC2CLP4_CLP48_MASK 256 #define ADC2CLP4_CLP49_MASK 512 #define ADC2CLP4_CLP_40_MASK 1023 #define ADC2CLP4_CLP_40_BITNUM 0 /*** ADC2CLP3 - Plus-Side General Calibration Value 3 Register; 0xFFFF8458 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC2CLP3H - Plus-Side General Calibration Value 3 High Register; 0xFFFF8458 ***/ union { byte Byte; struct { byte CLP38 :1; /* Plus-Side General Calibration Value 3 bits */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } ADC2CLP3HSTR; #define ADC2CLP3H _ADC2CLP3.Overlap_STR.ADC2CLP3HSTR.Byte #define ADC2CLP3H_CLP38 _ADC2CLP3.Overlap_STR.ADC2CLP3HSTR.Bits.CLP38 #define ADC2CLP3H_CLP38_MASK 1 /*** ADC2CLP3L - Plus-Side General Calibration Value 3 Low Register; 0xFFFF8459 ***/ union { byte Byte; struct { byte CLP30 :1; /* Plus-Side General Calibration Value 3 bit 0 */ byte CLP31 :1; /* Plus-Side General Calibration Value 3 bit 1 */ byte CLP32 :1; /* Plus-Side General Calibration Value 3 bit 2 */ byte CLP33 :1; /* Plus-Side General Calibration Value 3 bit 3 */ byte CLP34 :1; /* Plus-Side General Calibration Value 3 bit 4 */ byte CLP35 :1; /* Plus-Side General Calibration Value 3 bit 5 */ byte CLP36 :1; /* Plus-Side General Calibration Value 3 bit 6 */ byte CLP37 :1; /* Plus-Side General Calibration Value 3 bit 7 */ } Bits; } ADC2CLP3LSTR; #define ADC2CLP3L _ADC2CLP3.Overlap_STR.ADC2CLP3LSTR.Byte #define ADC2CLP3L_CLP30 _ADC2CLP3.Overlap_STR.ADC2CLP3LSTR.Bits.CLP30 #define ADC2CLP3L_CLP31 _ADC2CLP3.Overlap_STR.ADC2CLP3LSTR.Bits.CLP31 #define ADC2CLP3L_CLP32 _ADC2CLP3.Overlap_STR.ADC2CLP3LSTR.Bits.CLP32 #define ADC2CLP3L_CLP33 _ADC2CLP3.Overlap_STR.ADC2CLP3LSTR.Bits.CLP33 #define ADC2CLP3L_CLP34 _ADC2CLP3.Overlap_STR.ADC2CLP3LSTR.Bits.CLP34 #define ADC2CLP3L_CLP35 _ADC2CLP3.Overlap_STR.ADC2CLP3LSTR.Bits.CLP35 #define ADC2CLP3L_CLP36 _ADC2CLP3.Overlap_STR.ADC2CLP3LSTR.Bits.CLP36 #define ADC2CLP3L_CLP37 _ADC2CLP3.Overlap_STR.ADC2CLP3LSTR.Bits.CLP37 #define ADC2CLP3L_CLP30_MASK 1 #define ADC2CLP3L_CLP31_MASK 2 #define ADC2CLP3L_CLP32_MASK 4 #define ADC2CLP3L_CLP33_MASK 8 #define ADC2CLP3L_CLP34_MASK 16 #define ADC2CLP3L_CLP35_MASK 32 #define ADC2CLP3L_CLP36_MASK 64 #define ADC2CLP3L_CLP37_MASK 128 } Overlap_STR; struct { word CLP30 :1; /* Plus-Side General Calibration Value 3 bit 0 */ word CLP31 :1; /* Plus-Side General Calibration Value 3 bit 1 */ word CLP32 :1; /* Plus-Side General Calibration Value 3 bit 2 */ word CLP33 :1; /* Plus-Side General Calibration Value 3 bit 3 */ word CLP34 :1; /* Plus-Side General Calibration Value 3 bit 4 */ word CLP35 :1; /* Plus-Side General Calibration Value 3 bit 5 */ word CLP36 :1; /* Plus-Side General Calibration Value 3 bit 6 */ word CLP37 :1; /* Plus-Side General Calibration Value 3 bit 7 */ word CLP38 :1; /* Plus-Side General Calibration Value 3 bit 8 */ word :1; word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpCLP_30 :9; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } ADC2CLP3STR; extern volatile ADC2CLP3STR _ADC2CLP3 @0xFFFF8458; #define ADC2CLP3 _ADC2CLP3.Word #define ADC2CLP3_CLP30 _ADC2CLP3.Bits.CLP30 #define ADC2CLP3_CLP31 _ADC2CLP3.Bits.CLP31 #define ADC2CLP3_CLP32 _ADC2CLP3.Bits.CLP32 #define ADC2CLP3_CLP33 _ADC2CLP3.Bits.CLP33 #define ADC2CLP3_CLP34 _ADC2CLP3.Bits.CLP34 #define ADC2CLP3_CLP35 _ADC2CLP3.Bits.CLP35 #define ADC2CLP3_CLP36 _ADC2CLP3.Bits.CLP36 #define ADC2CLP3_CLP37 _ADC2CLP3.Bits.CLP37 #define ADC2CLP3_CLP38 _ADC2CLP3.Bits.CLP38 #define ADC2CLP3_CLP_30 _ADC2CLP3.MergedBits.grpCLP_30 #define ADC2CLP3_CLP ADC2CLP3_CLP_30 #define ADC2CLP3_CLP30_MASK 1 #define ADC2CLP3_CLP31_MASK 2 #define ADC2CLP3_CLP32_MASK 4 #define ADC2CLP3_CLP33_MASK 8 #define ADC2CLP3_CLP34_MASK 16 #define ADC2CLP3_CLP35_MASK 32 #define ADC2CLP3_CLP36_MASK 64 #define ADC2CLP3_CLP37_MASK 128 #define ADC2CLP3_CLP38_MASK 256 #define ADC2CLP3_CLP_30_MASK 511 #define ADC2CLP3_CLP_30_BITNUM 0 /*** ADC2CLP2 - Plus-Side General Calibration Value 2 Register; 0xFFFF845A ***/ typedef union { byte Byte; struct { byte CLP20 :1; /* Plus-Side General Calibration Value 2 bit 0 */ byte CLP21 :1; /* Plus-Side General Calibration Value 2 bit 1 */ byte CLP22 :1; /* Plus-Side General Calibration Value 2 bit 2 */ byte CLP23 :1; /* Plus-Side General Calibration Value 2 bit 3 */ byte CLP24 :1; /* Plus-Side General Calibration Value 2 bit 4 */ byte CLP25 :1; /* Plus-Side General Calibration Value 2 bit 5 */ byte CLP26 :1; /* Plus-Side General Calibration Value 2 bit 6 */ byte CLP27 :1; /* Plus-Side General Calibration Value 2 bit 7 */ } Bits; } ADC2CLP2STR; extern volatile ADC2CLP2STR _ADC2CLP2 @0xFFFF845A; #define ADC2CLP2 _ADC2CLP2.Byte #define ADC2CLP2_CLP20 _ADC2CLP2.Bits.CLP20 #define ADC2CLP2_CLP21 _ADC2CLP2.Bits.CLP21 #define ADC2CLP2_CLP22 _ADC2CLP2.Bits.CLP22 #define ADC2CLP2_CLP23 _ADC2CLP2.Bits.CLP23 #define ADC2CLP2_CLP24 _ADC2CLP2.Bits.CLP24 #define ADC2CLP2_CLP25 _ADC2CLP2.Bits.CLP25 #define ADC2CLP2_CLP26 _ADC2CLP2.Bits.CLP26 #define ADC2CLP2_CLP27 _ADC2CLP2.Bits.CLP27 #define ADC2CLP2_CLP20_MASK 1 #define ADC2CLP2_CLP21_MASK 2 #define ADC2CLP2_CLP22_MASK 4 #define ADC2CLP2_CLP23_MASK 8 #define ADC2CLP2_CLP24_MASK 16 #define ADC2CLP2_CLP25_MASK 32 #define ADC2CLP2_CLP26_MASK 64 #define ADC2CLP2_CLP27_MASK 128 /*** ADC2CLP1 - Plus-Side General Calibration Value 1 Register; 0xFFFF845B ***/ typedef union { byte Byte; struct { byte CLP10 :1; /* Plus-Side General Calibration Value 1 bit 0 */ byte CLP11 :1; /* Plus-Side General Calibration Value 1 bit 1 */ byte CLP12 :1; /* Plus-Side General Calibration Value 1 bit 2 */ byte CLP13 :1; /* Plus-Side General Calibration Value 1 bit 3 */ byte CLP14 :1; /* Plus-Side General Calibration Value 1 bit 4 */ byte CLP15 :1; /* Plus-Side General Calibration Value 1 bit 5 */ byte CLP16 :1; /* Plus-Side General Calibration Value 1 bit 6 */ byte :1; } Bits; struct { byte grpCLP_10 :7; byte :1; } MergedBits; } ADC2CLP1STR; extern volatile ADC2CLP1STR _ADC2CLP1 @0xFFFF845B; #define ADC2CLP1 _ADC2CLP1.Byte #define ADC2CLP1_CLP10 _ADC2CLP1.Bits.CLP10 #define ADC2CLP1_CLP11 _ADC2CLP1.Bits.CLP11 #define ADC2CLP1_CLP12 _ADC2CLP1.Bits.CLP12 #define ADC2CLP1_CLP13 _ADC2CLP1.Bits.CLP13 #define ADC2CLP1_CLP14 _ADC2CLP1.Bits.CLP14 #define ADC2CLP1_CLP15 _ADC2CLP1.Bits.CLP15 #define ADC2CLP1_CLP16 _ADC2CLP1.Bits.CLP16 #define ADC2CLP1_CLP_10 _ADC2CLP1.MergedBits.grpCLP_10 #define ADC2CLP1_CLP ADC2CLP1_CLP_10 #define ADC2CLP1_CLP10_MASK 1 #define ADC2CLP1_CLP11_MASK 2 #define ADC2CLP1_CLP12_MASK 4 #define ADC2CLP1_CLP13_MASK 8 #define ADC2CLP1_CLP14_MASK 16 #define ADC2CLP1_CLP15_MASK 32 #define ADC2CLP1_CLP16_MASK 64 #define ADC2CLP1_CLP_10_MASK 127 #define ADC2CLP1_CLP_10_BITNUM 0 /*** ADC2CLP0 - Plus-Side General Calibration Value 0 Register; 0xFFFF845C ***/ typedef union { byte Byte; struct { byte CLP00 :1; /* Plus-Side General Calibration Value 0 bit 0 */ byte CLP01 :1; /* Plus-Side General Calibration Value 0 bit 1 */ byte CLP02 :1; /* Plus-Side General Calibration Value 0 bit 2 */ byte CLP03 :1; /* Plus-Side General Calibration Value 0 bit 3 */ byte CLP04 :1; /* Plus-Side General Calibration Value 0 bit 4 */ byte CLP05 :1; /* Plus-Side General Calibration Value 0 bit 5 */ byte :1; byte :1; } Bits; struct { byte grpCLP0 :6; byte :1; byte :1; } MergedBits; } ADC2CLP0STR; extern volatile ADC2CLP0STR _ADC2CLP0 @0xFFFF845C; #define ADC2CLP0 _ADC2CLP0.Byte #define ADC2CLP0_CLP00 _ADC2CLP0.Bits.CLP00 #define ADC2CLP0_CLP01 _ADC2CLP0.Bits.CLP01 #define ADC2CLP0_CLP02 _ADC2CLP0.Bits.CLP02 #define ADC2CLP0_CLP03 _ADC2CLP0.Bits.CLP03 #define ADC2CLP0_CLP04 _ADC2CLP0.Bits.CLP04 #define ADC2CLP0_CLP05 _ADC2CLP0.Bits.CLP05 #define ADC2CLP0_CLP0 _ADC2CLP0.MergedBits.grpCLP0 #define ADC2CLP0_CLP00_MASK 1 #define ADC2CLP0_CLP01_MASK 2 #define ADC2CLP0_CLP02_MASK 4 #define ADC2CLP0_CLP03_MASK 8 #define ADC2CLP0_CLP04_MASK 16 #define ADC2CLP0_CLP05_MASK 32 #define ADC2CLP0_CLP0_MASK 63 #define ADC2CLP0_CLP0_BITNUM 0 /*** ADC2CLMD - Minus-Side General Calibration Value D Register; 0xFFFF845E ***/ typedef union { byte Byte; struct { byte CLMD0 :1; /* Minus-Side General Calibration Value D bit 0 */ byte CLMD1 :1; /* Minus-Side General Calibration Value D bit 1 */ byte CLMD2 :1; /* Minus-Side General Calibration Value D bit 2 */ byte CLMD3 :1; /* Minus-Side General Calibration Value D bit 3 */ byte CLMD4 :1; /* Minus-Side General Calibration Value D bit 4 */ byte CLMD5 :1; /* Minus-Side General Calibration Value D bit 5 */ byte :1; byte :1; } Bits; struct { byte grpCLMD :6; byte :1; byte :1; } MergedBits; } ADC2CLMDSTR; extern volatile ADC2CLMDSTR _ADC2CLMD @0xFFFF845E; #define ADC2CLMD _ADC2CLMD.Byte #define ADC2CLMD_CLMD0 _ADC2CLMD.Bits.CLMD0 #define ADC2CLMD_CLMD1 _ADC2CLMD.Bits.CLMD1 #define ADC2CLMD_CLMD2 _ADC2CLMD.Bits.CLMD2 #define ADC2CLMD_CLMD3 _ADC2CLMD.Bits.CLMD3 #define ADC2CLMD_CLMD4 _ADC2CLMD.Bits.CLMD4 #define ADC2CLMD_CLMD5 _ADC2CLMD.Bits.CLMD5 #define ADC2CLMD_CLMD _ADC2CLMD.MergedBits.grpCLMD #define ADC2CLMD_CLMD0_MASK 1 #define ADC2CLMD_CLMD1_MASK 2 #define ADC2CLMD_CLMD2_MASK 4 #define ADC2CLMD_CLMD3_MASK 8 #define ADC2CLMD_CLMD4_MASK 16 #define ADC2CLMD_CLMD5_MASK 32 #define ADC2CLMD_CLMD_MASK 63 #define ADC2CLMD_CLMD_BITNUM 0 /*** ADC2CLMS - Minus-Side General Calibration Value S Register; 0xFFFF845F ***/ typedef union { byte Byte; struct { byte CLMS0 :1; /* Minus-Side General Calibration Value S bit 0 */ byte CLMS1 :1; /* Minus-Side General Calibration Value S bit 1 */ byte CLMS2 :1; /* Minus-Side General Calibration Value S bit 2 */ byte CLMS3 :1; /* Minus-Side General Calibration Value S bit 3 */ byte CLMS4 :1; /* Minus-Side General Calibration Value S bit 4 */ byte CLMS5 :1; /* Minus-Side General Calibration Value S bit 5 */ byte :1; byte :1; } Bits; struct { byte grpCLMS :6; byte :1; byte :1; } MergedBits; } ADC2CLMSSTR; extern volatile ADC2CLMSSTR _ADC2CLMS @0xFFFF845F; #define ADC2CLMS _ADC2CLMS.Byte #define ADC2CLMS_CLMS0 _ADC2CLMS.Bits.CLMS0 #define ADC2CLMS_CLMS1 _ADC2CLMS.Bits.CLMS1 #define ADC2CLMS_CLMS2 _ADC2CLMS.Bits.CLMS2 #define ADC2CLMS_CLMS3 _ADC2CLMS.Bits.CLMS3 #define ADC2CLMS_CLMS4 _ADC2CLMS.Bits.CLMS4 #define ADC2CLMS_CLMS5 _ADC2CLMS.Bits.CLMS5 #define ADC2CLMS_CLMS _ADC2CLMS.MergedBits.grpCLMS #define ADC2CLMS_CLMS0_MASK 1 #define ADC2CLMS_CLMS1_MASK 2 #define ADC2CLMS_CLMS2_MASK 4 #define ADC2CLMS_CLMS3_MASK 8 #define ADC2CLMS_CLMS4_MASK 16 #define ADC2CLMS_CLMS5_MASK 32 #define ADC2CLMS_CLMS_MASK 63 #define ADC2CLMS_CLMS_BITNUM 0 /*** ADC2CLM4 - Minus-Side General Calibration Value 4 Register; 0xFFFF8460 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC2CLM4H - Minus-Side General Calibration Value 4 High Register; 0xFFFF8460 ***/ union { byte Byte; struct { byte CLM48 :1; /* Minus-Side General Calibration Value 4 bit 8 */ byte CLM49 :1; /* Minus-Side General Calibration Value 4 bit 9 */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpCLM_48 :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ADC2CLM4HSTR; #define ADC2CLM4H _ADC2CLM4.Overlap_STR.ADC2CLM4HSTR.Byte #define ADC2CLM4H_CLM48 _ADC2CLM4.Overlap_STR.ADC2CLM4HSTR.Bits.CLM48 #define ADC2CLM4H_CLM49 _ADC2CLM4.Overlap_STR.ADC2CLM4HSTR.Bits.CLM49 #define ADC2CLM4H_CLM_48 _ADC2CLM4.Overlap_STR.ADC2CLM4HSTR.MergedBits.grpCLM_48 #define ADC2CLM4H_CLM ADC2CLM4H_CLM_48 #define ADC2CLM4H_CLM48_MASK 1 #define ADC2CLM4H_CLM49_MASK 2 #define ADC2CLM4H_CLM_48_MASK 3 #define ADC2CLM4H_CLM_48_BITNUM 0 /*** ADC2CLM4L - Minus-Side General Calibration Value 4 Low Register; 0xFFFF8461 ***/ union { byte Byte; struct { byte CLM40 :1; /* Minus-Side General Calibration Value 4 bit 0 */ byte CLM41 :1; /* Minus-Side General Calibration Value 4 bit 1 */ byte CLM42 :1; /* Minus-Side General Calibration Value 4 bit 2 */ byte CLM43 :1; /* Minus-Side General Calibration Value 4 bit 3 */ byte CLM44 :1; /* Minus-Side General Calibration Value 4 bit 4 */ byte CLM45 :1; /* Minus-Side General Calibration Value 4 bit 5 */ byte CLM46 :1; /* Minus-Side General Calibration Value 4 bit 6 */ byte CLM47 :1; /* Minus-Side General Calibration Value 4 bit 7 */ } Bits; } ADC2CLM4LSTR; #define ADC2CLM4L _ADC2CLM4.Overlap_STR.ADC2CLM4LSTR.Byte #define ADC2CLM4L_CLM40 _ADC2CLM4.Overlap_STR.ADC2CLM4LSTR.Bits.CLM40 #define ADC2CLM4L_CLM41 _ADC2CLM4.Overlap_STR.ADC2CLM4LSTR.Bits.CLM41 #define ADC2CLM4L_CLM42 _ADC2CLM4.Overlap_STR.ADC2CLM4LSTR.Bits.CLM42 #define ADC2CLM4L_CLM43 _ADC2CLM4.Overlap_STR.ADC2CLM4LSTR.Bits.CLM43 #define ADC2CLM4L_CLM44 _ADC2CLM4.Overlap_STR.ADC2CLM4LSTR.Bits.CLM44 #define ADC2CLM4L_CLM45 _ADC2CLM4.Overlap_STR.ADC2CLM4LSTR.Bits.CLM45 #define ADC2CLM4L_CLM46 _ADC2CLM4.Overlap_STR.ADC2CLM4LSTR.Bits.CLM46 #define ADC2CLM4L_CLM47 _ADC2CLM4.Overlap_STR.ADC2CLM4LSTR.Bits.CLM47 #define ADC2CLM4L_CLM40_MASK 1 #define ADC2CLM4L_CLM41_MASK 2 #define ADC2CLM4L_CLM42_MASK 4 #define ADC2CLM4L_CLM43_MASK 8 #define ADC2CLM4L_CLM44_MASK 16 #define ADC2CLM4L_CLM45_MASK 32 #define ADC2CLM4L_CLM46_MASK 64 #define ADC2CLM4L_CLM47_MASK 128 } Overlap_STR; struct { word CLM40 :1; /* Minus-Side General Calibration Value 4 bit 0 */ word CLM41 :1; /* Minus-Side General Calibration Value 4 bit 1 */ word CLM42 :1; /* Minus-Side General Calibration Value 4 bit 2 */ word CLM43 :1; /* Minus-Side General Calibration Value 4 bit 3 */ word CLM44 :1; /* Minus-Side General Calibration Value 4 bit 4 */ word CLM45 :1; /* Minus-Side General Calibration Value 4 bit 5 */ word CLM46 :1; /* Minus-Side General Calibration Value 4 bit 6 */ word CLM47 :1; /* Minus-Side General Calibration Value 4 bit 7 */ word CLM48 :1; /* Minus-Side General Calibration Value 4 bit 8 */ word CLM49 :1; /* Minus-Side General Calibration Value 4 bit 9 */ word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpCLM_40 :10; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } ADC2CLM4STR; extern volatile ADC2CLM4STR _ADC2CLM4 @0xFFFF8460; #define ADC2CLM4 _ADC2CLM4.Word #define ADC2CLM4_CLM40 _ADC2CLM4.Bits.CLM40 #define ADC2CLM4_CLM41 _ADC2CLM4.Bits.CLM41 #define ADC2CLM4_CLM42 _ADC2CLM4.Bits.CLM42 #define ADC2CLM4_CLM43 _ADC2CLM4.Bits.CLM43 #define ADC2CLM4_CLM44 _ADC2CLM4.Bits.CLM44 #define ADC2CLM4_CLM45 _ADC2CLM4.Bits.CLM45 #define ADC2CLM4_CLM46 _ADC2CLM4.Bits.CLM46 #define ADC2CLM4_CLM47 _ADC2CLM4.Bits.CLM47 #define ADC2CLM4_CLM48 _ADC2CLM4.Bits.CLM48 #define ADC2CLM4_CLM49 _ADC2CLM4.Bits.CLM49 #define ADC2CLM4_CLM_40 _ADC2CLM4.MergedBits.grpCLM_40 #define ADC2CLM4_CLM ADC2CLM4_CLM_40 #define ADC2CLM4_CLM40_MASK 1 #define ADC2CLM4_CLM41_MASK 2 #define ADC2CLM4_CLM42_MASK 4 #define ADC2CLM4_CLM43_MASK 8 #define ADC2CLM4_CLM44_MASK 16 #define ADC2CLM4_CLM45_MASK 32 #define ADC2CLM4_CLM46_MASK 64 #define ADC2CLM4_CLM47_MASK 128 #define ADC2CLM4_CLM48_MASK 256 #define ADC2CLM4_CLM49_MASK 512 #define ADC2CLM4_CLM_40_MASK 1023 #define ADC2CLM4_CLM_40_BITNUM 0 /*** ADC2CLM3 - Minus-Side General Calibration Value 3 Register; 0xFFFF8462 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC2CLM3H - Minus-Side General Calibration Value 3 High Register; 0xFFFF8462 ***/ union { byte Byte; struct { byte CLM38 :1; /* Minus-Side General Calibration Value 3 bits */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } ADC2CLM3HSTR; #define ADC2CLM3H _ADC2CLM3.Overlap_STR.ADC2CLM3HSTR.Byte #define ADC2CLM3H_CLM38 _ADC2CLM3.Overlap_STR.ADC2CLM3HSTR.Bits.CLM38 #define ADC2CLM3H_CLM38_MASK 1 /*** ADC2CLM3L - Minus-Side General Calibration Value 3 Low Register; 0xFFFF8463 ***/ union { byte Byte; struct { byte CLM30 :1; /* Minus-Side General Calibration Value 3 bit 0 */ byte CLM31 :1; /* Minus-Side General Calibration Value 3 bit 1 */ byte CLM32 :1; /* Minus-Side General Calibration Value 3 bit 2 */ byte CLM33 :1; /* Minus-Side General Calibration Value 3 bit 3 */ byte CLM34 :1; /* Minus-Side General Calibration Value 3 bit 4 */ byte CLM35 :1; /* Minus-Side General Calibration Value 3 bit 5 */ byte CLM36 :1; /* Minus-Side General Calibration Value 3 bit 6 */ byte CLM37 :1; /* Minus-Side General Calibration Value 3 bit 7 */ } Bits; } ADC2CLM3LSTR; #define ADC2CLM3L _ADC2CLM3.Overlap_STR.ADC2CLM3LSTR.Byte #define ADC2CLM3L_CLM30 _ADC2CLM3.Overlap_STR.ADC2CLM3LSTR.Bits.CLM30 #define ADC2CLM3L_CLM31 _ADC2CLM3.Overlap_STR.ADC2CLM3LSTR.Bits.CLM31 #define ADC2CLM3L_CLM32 _ADC2CLM3.Overlap_STR.ADC2CLM3LSTR.Bits.CLM32 #define ADC2CLM3L_CLM33 _ADC2CLM3.Overlap_STR.ADC2CLM3LSTR.Bits.CLM33 #define ADC2CLM3L_CLM34 _ADC2CLM3.Overlap_STR.ADC2CLM3LSTR.Bits.CLM34 #define ADC2CLM3L_CLM35 _ADC2CLM3.Overlap_STR.ADC2CLM3LSTR.Bits.CLM35 #define ADC2CLM3L_CLM36 _ADC2CLM3.Overlap_STR.ADC2CLM3LSTR.Bits.CLM36 #define ADC2CLM3L_CLM37 _ADC2CLM3.Overlap_STR.ADC2CLM3LSTR.Bits.CLM37 #define ADC2CLM3L_CLM30_MASK 1 #define ADC2CLM3L_CLM31_MASK 2 #define ADC2CLM3L_CLM32_MASK 4 #define ADC2CLM3L_CLM33_MASK 8 #define ADC2CLM3L_CLM34_MASK 16 #define ADC2CLM3L_CLM35_MASK 32 #define ADC2CLM3L_CLM36_MASK 64 #define ADC2CLM3L_CLM37_MASK 128 } Overlap_STR; struct { word CLM30 :1; /* Minus-Side General Calibration Value 3 bit 0 */ word CLM31 :1; /* Minus-Side General Calibration Value 3 bit 1 */ word CLM32 :1; /* Minus-Side General Calibration Value 3 bit 2 */ word CLM33 :1; /* Minus-Side General Calibration Value 3 bit 3 */ word CLM34 :1; /* Minus-Side General Calibration Value 3 bit 4 */ word CLM35 :1; /* Minus-Side General Calibration Value 3 bit 5 */ word CLM36 :1; /* Minus-Side General Calibration Value 3 bit 6 */ word CLM37 :1; /* Minus-Side General Calibration Value 3 bit 7 */ word CLM38 :1; /* Minus-Side General Calibration Value 3 bit 8 */ word :1; word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpCLM_30 :9; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } ADC2CLM3STR; extern volatile ADC2CLM3STR _ADC2CLM3 @0xFFFF8462; #define ADC2CLM3 _ADC2CLM3.Word #define ADC2CLM3_CLM30 _ADC2CLM3.Bits.CLM30 #define ADC2CLM3_CLM31 _ADC2CLM3.Bits.CLM31 #define ADC2CLM3_CLM32 _ADC2CLM3.Bits.CLM32 #define ADC2CLM3_CLM33 _ADC2CLM3.Bits.CLM33 #define ADC2CLM3_CLM34 _ADC2CLM3.Bits.CLM34 #define ADC2CLM3_CLM35 _ADC2CLM3.Bits.CLM35 #define ADC2CLM3_CLM36 _ADC2CLM3.Bits.CLM36 #define ADC2CLM3_CLM37 _ADC2CLM3.Bits.CLM37 #define ADC2CLM3_CLM38 _ADC2CLM3.Bits.CLM38 #define ADC2CLM3_CLM_30 _ADC2CLM3.MergedBits.grpCLM_30 #define ADC2CLM3_CLM ADC2CLM3_CLM_30 #define ADC2CLM3_CLM30_MASK 1 #define ADC2CLM3_CLM31_MASK 2 #define ADC2CLM3_CLM32_MASK 4 #define ADC2CLM3_CLM33_MASK 8 #define ADC2CLM3_CLM34_MASK 16 #define ADC2CLM3_CLM35_MASK 32 #define ADC2CLM3_CLM36_MASK 64 #define ADC2CLM3_CLM37_MASK 128 #define ADC2CLM3_CLM38_MASK 256 #define ADC2CLM3_CLM_30_MASK 511 #define ADC2CLM3_CLM_30_BITNUM 0 /*** ADC2CLM2 - Minus-Side General Calibration Value 2 Register; 0xFFFF8464 ***/ typedef union { byte Byte; struct { byte CLM20 :1; /* Minus-Side General Calibration Value 2 bit 0 */ byte CLM21 :1; /* Minus-Side General Calibration Value 2 bit 1 */ byte CLM22 :1; /* Minus-Side General Calibration Value 2 bit 2 */ byte CLM23 :1; /* Minus-Side General Calibration Value 2 bit 3 */ byte CLM24 :1; /* Minus-Side General Calibration Value 2 bit 4 */ byte CLM25 :1; /* Minus-Side General Calibration Value 2 bit 5 */ byte CLM26 :1; /* Minus-Side General Calibration Value 2 bit 6 */ byte CLM27 :1; /* Minus-Side General Calibration Value 2 bit 7 */ } Bits; } ADC2CLM2STR; extern volatile ADC2CLM2STR _ADC2CLM2 @0xFFFF8464; #define ADC2CLM2 _ADC2CLM2.Byte #define ADC2CLM2_CLM20 _ADC2CLM2.Bits.CLM20 #define ADC2CLM2_CLM21 _ADC2CLM2.Bits.CLM21 #define ADC2CLM2_CLM22 _ADC2CLM2.Bits.CLM22 #define ADC2CLM2_CLM23 _ADC2CLM2.Bits.CLM23 #define ADC2CLM2_CLM24 _ADC2CLM2.Bits.CLM24 #define ADC2CLM2_CLM25 _ADC2CLM2.Bits.CLM25 #define ADC2CLM2_CLM26 _ADC2CLM2.Bits.CLM26 #define ADC2CLM2_CLM27 _ADC2CLM2.Bits.CLM27 #define ADC2CLM2_CLM20_MASK 1 #define ADC2CLM2_CLM21_MASK 2 #define ADC2CLM2_CLM22_MASK 4 #define ADC2CLM2_CLM23_MASK 8 #define ADC2CLM2_CLM24_MASK 16 #define ADC2CLM2_CLM25_MASK 32 #define ADC2CLM2_CLM26_MASK 64 #define ADC2CLM2_CLM27_MASK 128 /*** ADC2CLM1 - Minus-Side General Calibration Value 1 Register; 0xFFFF8465 ***/ typedef union { byte Byte; struct { byte CLM10 :1; /* Minus-Side General Calibration Value 1 bit 0 */ byte CLM11 :1; /* Minus-Side General Calibration Value 1 bit 1 */ byte CLM12 :1; /* Minus-Side General Calibration Value 1 bit 2 */ byte CLM13 :1; /* Minus-Side General Calibration Value 1 bit 3 */ byte CLM14 :1; /* Minus-Side General Calibration Value 1 bit 4 */ byte CLM15 :1; /* Minus-Side General Calibration Value 1 bit 5 */ byte CLM16 :1; /* Minus-Side General Calibration Value 1 bit 6 */ byte :1; } Bits; struct { byte grpCLM_10 :7; byte :1; } MergedBits; } ADC2CLM1STR; extern volatile ADC2CLM1STR _ADC2CLM1 @0xFFFF8465; #define ADC2CLM1 _ADC2CLM1.Byte #define ADC2CLM1_CLM10 _ADC2CLM1.Bits.CLM10 #define ADC2CLM1_CLM11 _ADC2CLM1.Bits.CLM11 #define ADC2CLM1_CLM12 _ADC2CLM1.Bits.CLM12 #define ADC2CLM1_CLM13 _ADC2CLM1.Bits.CLM13 #define ADC2CLM1_CLM14 _ADC2CLM1.Bits.CLM14 #define ADC2CLM1_CLM15 _ADC2CLM1.Bits.CLM15 #define ADC2CLM1_CLM16 _ADC2CLM1.Bits.CLM16 #define ADC2CLM1_CLM_10 _ADC2CLM1.MergedBits.grpCLM_10 #define ADC2CLM1_CLM ADC2CLM1_CLM_10 #define ADC2CLM1_CLM10_MASK 1 #define ADC2CLM1_CLM11_MASK 2 #define ADC2CLM1_CLM12_MASK 4 #define ADC2CLM1_CLM13_MASK 8 #define ADC2CLM1_CLM14_MASK 16 #define ADC2CLM1_CLM15_MASK 32 #define ADC2CLM1_CLM16_MASK 64 #define ADC2CLM1_CLM_10_MASK 127 #define ADC2CLM1_CLM_10_BITNUM 0 /*** ADC2CLM0 - Minus-Side General Calibration Value 0 Register; 0xFFFF8466 ***/ typedef union { byte Byte; struct { byte CLM00 :1; /* Minus-Side General Calibration Value 0 bit 0 */ byte CLM01 :1; /* Minus-Side General Calibration Value 0 bit 1 */ byte CLM02 :1; /* Minus-Side General Calibration Value 0 bit 2 */ byte CLM03 :1; /* Minus-Side General Calibration Value 0 bit 3 */ byte CLM04 :1; /* Minus-Side General Calibration Value 0 bit 4 */ byte CLM05 :1; /* Minus-Side General Calibration Value 0 bit 5 */ byte :1; byte :1; } Bits; struct { byte grpCLM0 :6; byte :1; byte :1; } MergedBits; } ADC2CLM0STR; extern volatile ADC2CLM0STR _ADC2CLM0 @0xFFFF8466; #define ADC2CLM0 _ADC2CLM0.Byte #define ADC2CLM0_CLM00 _ADC2CLM0.Bits.CLM00 #define ADC2CLM0_CLM01 _ADC2CLM0.Bits.CLM01 #define ADC2CLM0_CLM02 _ADC2CLM0.Bits.CLM02 #define ADC2CLM0_CLM03 _ADC2CLM0.Bits.CLM03 #define ADC2CLM0_CLM04 _ADC2CLM0.Bits.CLM04 #define ADC2CLM0_CLM05 _ADC2CLM0.Bits.CLM05 #define ADC2CLM0_CLM0 _ADC2CLM0.MergedBits.grpCLM0 #define ADC2CLM0_CLM00_MASK 1 #define ADC2CLM0_CLM01_MASK 2 #define ADC2CLM0_CLM02_MASK 4 #define ADC2CLM0_CLM03_MASK 8 #define ADC2CLM0_CLM04_MASK 16 #define ADC2CLM0_CLM05_MASK 32 #define ADC2CLM0_CLM0_MASK 63 #define ADC2CLM0_CLM0_BITNUM 0 /*** ADC3SC1A - Status and Control Register 1A; 0xFFFF8480 ***/ typedef union { byte Byte; struct { byte ADCHA0 :1; /* Input Channel Select Bit 0 */ byte ADCHA1 :1; /* Input Channel Select Bit 1 */ byte ADCHA2 :1; /* Input Channel Select Bit 2 */ byte ADCHA3 :1; /* Input Channel Select Bit 3 */ byte ADCHA4 :1; /* Input Channel Select Bit 4 */ byte DIFFA :1; /* Differential Mode Enable - DIFFA configures the ADC to operate in differential mode */ byte AIENA :1; /* Interrupt Enable - AIENA enables conversion complete interrupts. When COCOA becomes set while the respective AIENA is high, an interrupt is asserted */ byte COCOA :1; /* Conversion Complete Flag */ } Bits; struct { byte grpADCHA :5; byte grpDIFFx :1; byte grpAIENx :1; byte grpCOCOx :1; } MergedBits; } ADC3SC1ASTR; extern volatile ADC3SC1ASTR _ADC3SC1A @0xFFFF8480; #define ADC3SC1A _ADC3SC1A.Byte #define ADC3SC1A_ADCHA0 _ADC3SC1A.Bits.ADCHA0 #define ADC3SC1A_ADCHA1 _ADC3SC1A.Bits.ADCHA1 #define ADC3SC1A_ADCHA2 _ADC3SC1A.Bits.ADCHA2 #define ADC3SC1A_ADCHA3 _ADC3SC1A.Bits.ADCHA3 #define ADC3SC1A_ADCHA4 _ADC3SC1A.Bits.ADCHA4 #define ADC3SC1A_DIFFA _ADC3SC1A.Bits.DIFFA #define ADC3SC1A_AIENA _ADC3SC1A.Bits.AIENA #define ADC3SC1A_COCOA _ADC3SC1A.Bits.COCOA #define ADC3SC1A_ADCHA _ADC3SC1A.MergedBits.grpADCHA #define ADC3SC1A_ADCHA0_MASK 1 #define ADC3SC1A_ADCHA1_MASK 2 #define ADC3SC1A_ADCHA2_MASK 4 #define ADC3SC1A_ADCHA3_MASK 8 #define ADC3SC1A_ADCHA4_MASK 16 #define ADC3SC1A_DIFFA_MASK 32 #define ADC3SC1A_AIENA_MASK 64 #define ADC3SC1A_COCOA_MASK 128 #define ADC3SC1A_ADCHA_MASK 31 #define ADC3SC1A_ADCHA_BITNUM 0 /*** ADC3SC1B - Status and Control Register 1B; 0xFFFF8481 ***/ typedef union { byte Byte; struct { byte ADCHB0 :1; /* Input Channel Select Bit 0 */ byte ADCHB1 :1; /* Input Channel Select Bit 1 */ byte ADCHB2 :1; /* Input Channel Select Bit 2 */ byte ADCHB3 :1; /* Input Channel Select Bit 3 */ byte ADCHB4 :1; /* Input Channel Select Bit 4 */ byte DIFFB :1; /* Differential Mode Enable - DIFFB configures the ADC to operate in differential mode */ byte AIENB :1; /* Interrupt Enable - AIENB enables conversion complete interrupts. When COCOB becomes set while the respective AIENB is high, an interrupt is asserted */ byte COCOB :1; /* Conversion Complete Flag */ } Bits; struct { byte grpADCHB :5; byte :1; byte :1; byte :1; } MergedBits; } ADC3SC1BSTR; extern volatile ADC3SC1BSTR _ADC3SC1B @0xFFFF8481; #define ADC3SC1B _ADC3SC1B.Byte #define ADC3SC1B_ADCHB0 _ADC3SC1B.Bits.ADCHB0 #define ADC3SC1B_ADCHB1 _ADC3SC1B.Bits.ADCHB1 #define ADC3SC1B_ADCHB2 _ADC3SC1B.Bits.ADCHB2 #define ADC3SC1B_ADCHB3 _ADC3SC1B.Bits.ADCHB3 #define ADC3SC1B_ADCHB4 _ADC3SC1B.Bits.ADCHB4 #define ADC3SC1B_DIFFB _ADC3SC1B.Bits.DIFFB #define ADC3SC1B_AIENB _ADC3SC1B.Bits.AIENB #define ADC3SC1B_COCOB _ADC3SC1B.Bits.COCOB #define ADC3SC1B_ADCHB _ADC3SC1B.MergedBits.grpADCHB #define ADC3SC1B_ADCHB0_MASK 1 #define ADC3SC1B_ADCHB1_MASK 2 #define ADC3SC1B_ADCHB2_MASK 4 #define ADC3SC1B_ADCHB3_MASK 8 #define ADC3SC1B_ADCHB4_MASK 16 #define ADC3SC1B_DIFFB_MASK 32 #define ADC3SC1B_AIENB_MASK 64 #define ADC3SC1B_COCOB_MASK 128 #define ADC3SC1B_ADCHB_MASK 31 #define ADC3SC1B_ADCHB_BITNUM 0 /*** ADC3CFG1 - Configuration Register 1; 0xFFFF8482 ***/ typedef union { byte Byte; struct { byte ADICLK0 :1; /* Input Clock Select Bit 0 */ byte ADICLK1 :1; /* Input Clock Select Bit 1 */ byte MODE0 :1; /* Conversion Mode Selection Bit 0 */ byte MODE1 :1; /* Conversion Mode Selection Bit 1 */ byte ADLSMP :1; /* Long Sample Time Configuration */ byte ADIV0 :1; /* Clock Divide Select Bit 0 */ byte ADIV1 :1; /* Clock Divide Select Bit 1 */ byte ADLPC :1; /* Low Power Configuration */ } Bits; struct { byte grpADICLK :2; byte grpMODE :2; byte :1; byte grpADIV :2; byte :1; } MergedBits; } ADC3CFG1STR; extern volatile ADC3CFG1STR _ADC3CFG1 @0xFFFF8482; #define ADC3CFG1 _ADC3CFG1.Byte #define ADC3CFG1_ADICLK0 _ADC3CFG1.Bits.ADICLK0 #define ADC3CFG1_ADICLK1 _ADC3CFG1.Bits.ADICLK1 #define ADC3CFG1_MODE0 _ADC3CFG1.Bits.MODE0 #define ADC3CFG1_MODE1 _ADC3CFG1.Bits.MODE1 #define ADC3CFG1_ADLSMP _ADC3CFG1.Bits.ADLSMP #define ADC3CFG1_ADIV0 _ADC3CFG1.Bits.ADIV0 #define ADC3CFG1_ADIV1 _ADC3CFG1.Bits.ADIV1 #define ADC3CFG1_ADLPC _ADC3CFG1.Bits.ADLPC #define ADC3CFG1_ADICLK _ADC3CFG1.MergedBits.grpADICLK #define ADC3CFG1_MODE _ADC3CFG1.MergedBits.grpMODE #define ADC3CFG1_ADIV _ADC3CFG1.MergedBits.grpADIV #define ADC3CFG1_ADICLK0_MASK 1 #define ADC3CFG1_ADICLK1_MASK 2 #define ADC3CFG1_MODE0_MASK 4 #define ADC3CFG1_MODE1_MASK 8 #define ADC3CFG1_ADLSMP_MASK 16 #define ADC3CFG1_ADIV0_MASK 32 #define ADC3CFG1_ADIV1_MASK 64 #define ADC3CFG1_ADLPC_MASK 128 #define ADC3CFG1_ADICLK_MASK 3 #define ADC3CFG1_ADICLK_BITNUM 0 #define ADC3CFG1_MODE_MASK 12 #define ADC3CFG1_MODE_BITNUM 2 #define ADC3CFG1_ADIV_MASK 96 #define ADC3CFG1_ADIV_BITNUM 5 /*** ADC3CFG2 - Configuration Register 2; 0xFFFF8483 ***/ typedef union { byte Byte; struct { byte ADLSTS0 :1; /* Long Sample Time Select Bit 0 */ byte ADLSTS1 :1; /* Long Sample Time Select Bit 1 */ byte ADHSC :1; /* High Speed Configuration */ byte ADACKEN :1; /* Asynchronous Clock Output Enable */ byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpADLSTS :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ADC3CFG2STR; extern volatile ADC3CFG2STR _ADC3CFG2 @0xFFFF8483; #define ADC3CFG2 _ADC3CFG2.Byte #define ADC3CFG2_ADLSTS0 _ADC3CFG2.Bits.ADLSTS0 #define ADC3CFG2_ADLSTS1 _ADC3CFG2.Bits.ADLSTS1 #define ADC3CFG2_ADHSC _ADC3CFG2.Bits.ADHSC #define ADC3CFG2_ADACKEN _ADC3CFG2.Bits.ADACKEN #define ADC3CFG2_ADLSTS _ADC3CFG2.MergedBits.grpADLSTS #define ADC3CFG2_ADLSTS0_MASK 1 #define ADC3CFG2_ADLSTS1_MASK 2 #define ADC3CFG2_ADHSC_MASK 4 #define ADC3CFG2_ADACKEN_MASK 8 #define ADC3CFG2_ADLSTS_MASK 3 #define ADC3CFG2_ADLSTS_BITNUM 0 /*** ADC3RA - Data Result Register A; 0xFFFF8484 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC3RHA - Data Result High Register A; 0xFFFF8484 ***/ union { byte Byte; struct { byte D8 :1; /* ADC Result Data Bit 8 */ byte D9 :1; /* ADC Result Data Bit 9 */ byte D10 :1; /* ADC Result Data Bit 10 */ byte D11 :1; /* ADC Result Data Bit 11 */ byte D12 :1; /* ADC Result Data Bit 12 */ byte D13 :1; /* ADC Result Data Bit 13 */ byte D14 :1; /* ADC Result Data Bit 14 */ byte D15 :1; /* ADC Result Data Bit 15 */ } Bits; } ADC3RHASTR; #define ADC3RHA _ADC3RA.Overlap_STR.ADC3RHASTR.Byte #define ADC3RHA_D8 _ADC3RA.Overlap_STR.ADC3RHASTR.Bits.D8 #define ADC3RHA_D9 _ADC3RA.Overlap_STR.ADC3RHASTR.Bits.D9 #define ADC3RHA_D10 _ADC3RA.Overlap_STR.ADC3RHASTR.Bits.D10 #define ADC3RHA_D11 _ADC3RA.Overlap_STR.ADC3RHASTR.Bits.D11 #define ADC3RHA_D12 _ADC3RA.Overlap_STR.ADC3RHASTR.Bits.D12 #define ADC3RHA_D13 _ADC3RA.Overlap_STR.ADC3RHASTR.Bits.D13 #define ADC3RHA_D14 _ADC3RA.Overlap_STR.ADC3RHASTR.Bits.D14 #define ADC3RHA_D15 _ADC3RA.Overlap_STR.ADC3RHASTR.Bits.D15 #define ADC3RHA_D8_MASK 1 #define ADC3RHA_D9_MASK 2 #define ADC3RHA_D10_MASK 4 #define ADC3RHA_D11_MASK 8 #define ADC3RHA_D12_MASK 16 #define ADC3RHA_D13_MASK 32 #define ADC3RHA_D14_MASK 64 #define ADC3RHA_D15_MASK 128 /*** ADC3RLA - Data Result Low Register A; 0xFFFF8485 ***/ union { byte Byte; struct { byte D0 :1; /* ADC Result Data Bit 0 */ byte D1 :1; /* ADC Result Data Bit 1 */ byte D2 :1; /* ADC Result Data Bit 2 */ byte D3 :1; /* ADC Result Data Bit 3 */ byte D4 :1; /* ADC Result Data Bit 4 */ byte D5 :1; /* ADC Result Data Bit 5 */ byte D6 :1; /* ADC Result Data Bit 6 */ byte D7 :1; /* ADC Result Data Bit 7 */ } Bits; } ADC3RLASTR; #define ADC3RLA _ADC3RA.Overlap_STR.ADC3RLASTR.Byte #define ADC3RLA_D0 _ADC3RA.Overlap_STR.ADC3RLASTR.Bits.D0 #define ADC3RLA_D1 _ADC3RA.Overlap_STR.ADC3RLASTR.Bits.D1 #define ADC3RLA_D2 _ADC3RA.Overlap_STR.ADC3RLASTR.Bits.D2 #define ADC3RLA_D3 _ADC3RA.Overlap_STR.ADC3RLASTR.Bits.D3 #define ADC3RLA_D4 _ADC3RA.Overlap_STR.ADC3RLASTR.Bits.D4 #define ADC3RLA_D5 _ADC3RA.Overlap_STR.ADC3RLASTR.Bits.D5 #define ADC3RLA_D6 _ADC3RA.Overlap_STR.ADC3RLASTR.Bits.D6 #define ADC3RLA_D7 _ADC3RA.Overlap_STR.ADC3RLASTR.Bits.D7 #define ADC3RLA_D0_MASK 1 #define ADC3RLA_D1_MASK 2 #define ADC3RLA_D2_MASK 4 #define ADC3RLA_D3_MASK 8 #define ADC3RLA_D4_MASK 16 #define ADC3RLA_D5_MASK 32 #define ADC3RLA_D6_MASK 64 #define ADC3RLA_D7_MASK 128 } Overlap_STR; struct { word D0 :1; /* ADC Result Data Bit 0 */ word D1 :1; /* ADC Result Data Bit 1 */ word D2 :1; /* ADC Result Data Bit 2 */ word D3 :1; /* ADC Result Data Bit 3 */ word D4 :1; /* ADC Result Data Bit 4 */ word D5 :1; /* ADC Result Data Bit 5 */ word D6 :1; /* ADC Result Data Bit 6 */ word D7 :1; /* ADC Result Data Bit 7 */ word D8 :1; /* ADC Result Data Bit 8 */ word D9 :1; /* ADC Result Data Bit 9 */ word D10 :1; /* ADC Result Data Bit 10 */ word D11 :1; /* ADC Result Data Bit 11 */ word D12 :1; /* ADC Result Data Bit 12 */ word D13 :1; /* ADC Result Data Bit 13 */ word D14 :1; /* ADC Result Data Bit 14 */ word D15 :1; /* ADC Result Data Bit 15 */ } Bits; } ADC3RASTR; extern volatile ADC3RASTR _ADC3RA @0xFFFF8484; #define ADC3RA _ADC3RA.Word #define ADC3RA_D0 _ADC3RA.Bits.D0 #define ADC3RA_D1 _ADC3RA.Bits.D1 #define ADC3RA_D2 _ADC3RA.Bits.D2 #define ADC3RA_D3 _ADC3RA.Bits.D3 #define ADC3RA_D4 _ADC3RA.Bits.D4 #define ADC3RA_D5 _ADC3RA.Bits.D5 #define ADC3RA_D6 _ADC3RA.Bits.D6 #define ADC3RA_D7 _ADC3RA.Bits.D7 #define ADC3RA_D8 _ADC3RA.Bits.D8 #define ADC3RA_D9 _ADC3RA.Bits.D9 #define ADC3RA_D10 _ADC3RA.Bits.D10 #define ADC3RA_D11 _ADC3RA.Bits.D11 #define ADC3RA_D12 _ADC3RA.Bits.D12 #define ADC3RA_D13 _ADC3RA.Bits.D13 #define ADC3RA_D14 _ADC3RA.Bits.D14 #define ADC3RA_D15 _ADC3RA.Bits.D15 #define ADC3RA_D0_MASK 1 #define ADC3RA_D1_MASK 2 #define ADC3RA_D2_MASK 4 #define ADC3RA_D3_MASK 8 #define ADC3RA_D4_MASK 16 #define ADC3RA_D5_MASK 32 #define ADC3RA_D6_MASK 64 #define ADC3RA_D7_MASK 128 #define ADC3RA_D8_MASK 256 #define ADC3RA_D9_MASK 512 #define ADC3RA_D10_MASK 1024 #define ADC3RA_D11_MASK 2048 #define ADC3RA_D12_MASK 4096 #define ADC3RA_D13_MASK 8192 #define ADC3RA_D14_MASK 16384 #define ADC3RA_D15_MASK 32768 /*** ADC3RB - Data Result Register B; 0xFFFF8486 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC3RHB - Data Result High Register B; 0xFFFF8486 ***/ union { byte Byte; struct { byte D8 :1; /* ADC Result Data Bit 8 */ byte D9 :1; /* ADC Result Data Bit 9 */ byte D10 :1; /* ADC Result Data Bit 10 */ byte D11 :1; /* ADC Result Data Bit 11 */ byte D12 :1; /* ADC Result Data Bit 12 */ byte D13 :1; /* ADC Result Data Bit 13 */ byte D14 :1; /* ADC Result Data Bit 14 */ byte D15 :1; /* ADC Result Data Bit 15 */ } Bits; } ADC3RHBSTR; #define ADC3RHB _ADC3RB.Overlap_STR.ADC3RHBSTR.Byte #define ADC3RHB_D8 _ADC3RB.Overlap_STR.ADC3RHBSTR.Bits.D8 #define ADC3RHB_D9 _ADC3RB.Overlap_STR.ADC3RHBSTR.Bits.D9 #define ADC3RHB_D10 _ADC3RB.Overlap_STR.ADC3RHBSTR.Bits.D10 #define ADC3RHB_D11 _ADC3RB.Overlap_STR.ADC3RHBSTR.Bits.D11 #define ADC3RHB_D12 _ADC3RB.Overlap_STR.ADC3RHBSTR.Bits.D12 #define ADC3RHB_D13 _ADC3RB.Overlap_STR.ADC3RHBSTR.Bits.D13 #define ADC3RHB_D14 _ADC3RB.Overlap_STR.ADC3RHBSTR.Bits.D14 #define ADC3RHB_D15 _ADC3RB.Overlap_STR.ADC3RHBSTR.Bits.D15 #define ADC3RHB_D8_MASK 1 #define ADC3RHB_D9_MASK 2 #define ADC3RHB_D10_MASK 4 #define ADC3RHB_D11_MASK 8 #define ADC3RHB_D12_MASK 16 #define ADC3RHB_D13_MASK 32 #define ADC3RHB_D14_MASK 64 #define ADC3RHB_D15_MASK 128 /*** ADC3RLB - Data Result Low Register B; 0xFFFF8487 ***/ union { byte Byte; struct { byte D0 :1; /* ADC Result Data Bit 0 */ byte D1 :1; /* ADC Result Data Bit 1 */ byte D2 :1; /* ADC Result Data Bit 2 */ byte D3 :1; /* ADC Result Data Bit 3 */ byte D4 :1; /* ADC Result Data Bit 4 */ byte D5 :1; /* ADC Result Data Bit 5 */ byte D6 :1; /* ADC Result Data Bit 6 */ byte D7 :1; /* ADC Result Data Bit 7 */ } Bits; } ADC3RLBSTR; #define ADC3RLB _ADC3RB.Overlap_STR.ADC3RLBSTR.Byte #define ADC3RLB_D0 _ADC3RB.Overlap_STR.ADC3RLBSTR.Bits.D0 #define ADC3RLB_D1 _ADC3RB.Overlap_STR.ADC3RLBSTR.Bits.D1 #define ADC3RLB_D2 _ADC3RB.Overlap_STR.ADC3RLBSTR.Bits.D2 #define ADC3RLB_D3 _ADC3RB.Overlap_STR.ADC3RLBSTR.Bits.D3 #define ADC3RLB_D4 _ADC3RB.Overlap_STR.ADC3RLBSTR.Bits.D4 #define ADC3RLB_D5 _ADC3RB.Overlap_STR.ADC3RLBSTR.Bits.D5 #define ADC3RLB_D6 _ADC3RB.Overlap_STR.ADC3RLBSTR.Bits.D6 #define ADC3RLB_D7 _ADC3RB.Overlap_STR.ADC3RLBSTR.Bits.D7 #define ADC3RLB_D0_MASK 1 #define ADC3RLB_D1_MASK 2 #define ADC3RLB_D2_MASK 4 #define ADC3RLB_D3_MASK 8 #define ADC3RLB_D4_MASK 16 #define ADC3RLB_D5_MASK 32 #define ADC3RLB_D6_MASK 64 #define ADC3RLB_D7_MASK 128 } Overlap_STR; struct { word D0 :1; /* ADC Result Data Bit 0 */ word D1 :1; /* ADC Result Data Bit 1 */ word D2 :1; /* ADC Result Data Bit 2 */ word D3 :1; /* ADC Result Data Bit 3 */ word D4 :1; /* ADC Result Data Bit 4 */ word D5 :1; /* ADC Result Data Bit 5 */ word D6 :1; /* ADC Result Data Bit 6 */ word D7 :1; /* ADC Result Data Bit 7 */ word D8 :1; /* ADC Result Data Bit 8 */ word D9 :1; /* ADC Result Data Bit 9 */ word D10 :1; /* ADC Result Data Bit 10 */ word D11 :1; /* ADC Result Data Bit 11 */ word D12 :1; /* ADC Result Data Bit 12 */ word D13 :1; /* ADC Result Data Bit 13 */ word D14 :1; /* ADC Result Data Bit 14 */ word D15 :1; /* ADC Result Data Bit 15 */ } Bits; } ADC3RBSTR; extern volatile ADC3RBSTR _ADC3RB @0xFFFF8486; #define ADC3RB _ADC3RB.Word #define ADC3RB_D0 _ADC3RB.Bits.D0 #define ADC3RB_D1 _ADC3RB.Bits.D1 #define ADC3RB_D2 _ADC3RB.Bits.D2 #define ADC3RB_D3 _ADC3RB.Bits.D3 #define ADC3RB_D4 _ADC3RB.Bits.D4 #define ADC3RB_D5 _ADC3RB.Bits.D5 #define ADC3RB_D6 _ADC3RB.Bits.D6 #define ADC3RB_D7 _ADC3RB.Bits.D7 #define ADC3RB_D8 _ADC3RB.Bits.D8 #define ADC3RB_D9 _ADC3RB.Bits.D9 #define ADC3RB_D10 _ADC3RB.Bits.D10 #define ADC3RB_D11 _ADC3RB.Bits.D11 #define ADC3RB_D12 _ADC3RB.Bits.D12 #define ADC3RB_D13 _ADC3RB.Bits.D13 #define ADC3RB_D14 _ADC3RB.Bits.D14 #define ADC3RB_D15 _ADC3RB.Bits.D15 #define ADC3RB_D0_MASK 1 #define ADC3RB_D1_MASK 2 #define ADC3RB_D2_MASK 4 #define ADC3RB_D3_MASK 8 #define ADC3RB_D4_MASK 16 #define ADC3RB_D5_MASK 32 #define ADC3RB_D6_MASK 64 #define ADC3RB_D7_MASK 128 #define ADC3RB_D8_MASK 256 #define ADC3RB_D9_MASK 512 #define ADC3RB_D10_MASK 1024 #define ADC3RB_D11_MASK 2048 #define ADC3RB_D12_MASK 4096 #define ADC3RB_D13_MASK 8192 #define ADC3RB_D14_MASK 16384 #define ADC3RB_D15_MASK 32768 /*** ADC3CV1 - Compare Value 1 Register; 0xFFFF8488 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC3CV1H - Compare Value 1 High Register; 0xFFFF8488 ***/ union { byte Byte; struct { byte CV18 :1; /* Compare Function Value 8 */ byte CV19 :1; /* Compare Function Value 9 */ byte CV110 :1; /* Compare Function Value 10 */ byte CV111 :1; /* Compare Function Value 11 */ byte CV112 :1; /* Compare Function Value 12 */ byte CV113 :1; /* Compare Function Value 13 */ byte CV114 :1; /* Compare Function Value 14 */ byte CV115 :1; /* Compare Function Value 15 */ } Bits; struct { byte grpCV_18 :2; byte grpCV1_10 :6; } MergedBits; } ADC3CV1HSTR; #define ADC3CV1H _ADC3CV1.Overlap_STR.ADC3CV1HSTR.Byte #define ADC3CV1H_CV18 _ADC3CV1.Overlap_STR.ADC3CV1HSTR.Bits.CV18 #define ADC3CV1H_CV19 _ADC3CV1.Overlap_STR.ADC3CV1HSTR.Bits.CV19 #define ADC3CV1H_CV110 _ADC3CV1.Overlap_STR.ADC3CV1HSTR.Bits.CV110 #define ADC3CV1H_CV111 _ADC3CV1.Overlap_STR.ADC3CV1HSTR.Bits.CV111 #define ADC3CV1H_CV112 _ADC3CV1.Overlap_STR.ADC3CV1HSTR.Bits.CV112 #define ADC3CV1H_CV113 _ADC3CV1.Overlap_STR.ADC3CV1HSTR.Bits.CV113 #define ADC3CV1H_CV114 _ADC3CV1.Overlap_STR.ADC3CV1HSTR.Bits.CV114 #define ADC3CV1H_CV115 _ADC3CV1.Overlap_STR.ADC3CV1HSTR.Bits.CV115 #define ADC3CV1H_CV_18 _ADC3CV1.Overlap_STR.ADC3CV1HSTR.MergedBits.grpCV_18 #define ADC3CV1H_CV1_10 _ADC3CV1.Overlap_STR.ADC3CV1HSTR.MergedBits.grpCV1_10 #define ADC3CV1H_CV ADC3CV1H_CV_18 #define ADC3CV1H_CV1 ADC3CV1H_CV1_10 #define ADC3CV1H_CV18_MASK 1 #define ADC3CV1H_CV19_MASK 2 #define ADC3CV1H_CV110_MASK 4 #define ADC3CV1H_CV111_MASK 8 #define ADC3CV1H_CV112_MASK 16 #define ADC3CV1H_CV113_MASK 32 #define ADC3CV1H_CV114_MASK 64 #define ADC3CV1H_CV115_MASK 128 #define ADC3CV1H_CV_18_MASK 3 #define ADC3CV1H_CV_18_BITNUM 0 #define ADC3CV1H_CV1_10_MASK 252 #define ADC3CV1H_CV1_10_BITNUM 2 /*** ADC3CV1L - Compare Value 1 Low Register; 0xFFFF8489 ***/ union { byte Byte; struct { byte CV10 :1; /* Compare Function Value 0 */ byte CV11 :1; /* Compare Function Value 1 */ byte CV12 :1; /* Compare Function Value 2 */ byte CV13 :1; /* Compare Function Value 3 */ byte CV14 :1; /* Compare Function Value 4 */ byte CV15 :1; /* Compare Function Value 5 */ byte CV16 :1; /* Compare Function Value 6 */ byte CV17 :1; /* Compare Function Value 7 */ } Bits; } ADC3CV1LSTR; #define ADC3CV1L _ADC3CV1.Overlap_STR.ADC3CV1LSTR.Byte #define ADC3CV1L_CV10 _ADC3CV1.Overlap_STR.ADC3CV1LSTR.Bits.CV10 #define ADC3CV1L_CV11 _ADC3CV1.Overlap_STR.ADC3CV1LSTR.Bits.CV11 #define ADC3CV1L_CV12 _ADC3CV1.Overlap_STR.ADC3CV1LSTR.Bits.CV12 #define ADC3CV1L_CV13 _ADC3CV1.Overlap_STR.ADC3CV1LSTR.Bits.CV13 #define ADC3CV1L_CV14 _ADC3CV1.Overlap_STR.ADC3CV1LSTR.Bits.CV14 #define ADC3CV1L_CV15 _ADC3CV1.Overlap_STR.ADC3CV1LSTR.Bits.CV15 #define ADC3CV1L_CV16 _ADC3CV1.Overlap_STR.ADC3CV1LSTR.Bits.CV16 #define ADC3CV1L_CV17 _ADC3CV1.Overlap_STR.ADC3CV1LSTR.Bits.CV17 #define ADC3CV1L_CV10_MASK 1 #define ADC3CV1L_CV11_MASK 2 #define ADC3CV1L_CV12_MASK 4 #define ADC3CV1L_CV13_MASK 8 #define ADC3CV1L_CV14_MASK 16 #define ADC3CV1L_CV15_MASK 32 #define ADC3CV1L_CV16_MASK 64 #define ADC3CV1L_CV17_MASK 128 } Overlap_STR; struct { word CV10 :1; /* Compare Function Value 0 */ word CV11 :1; /* Compare Function Value 1 */ word CV12 :1; /* Compare Function Value 2 */ word CV13 :1; /* Compare Function Value 3 */ word CV14 :1; /* Compare Function Value 4 */ word CV15 :1; /* Compare Function Value 5 */ word CV16 :1; /* Compare Function Value 6 */ word CV17 :1; /* Compare Function Value 7 */ word CV18 :1; /* Compare Function Value 8 */ word CV19 :1; /* Compare Function Value 9 */ word CV110 :1; /* Compare Function Value 10 */ word CV111 :1; /* Compare Function Value 11 */ word CV112 :1; /* Compare Function Value 12 */ word CV113 :1; /* Compare Function Value 13 */ word CV114 :1; /* Compare Function Value 14 */ word CV115 :1; /* Compare Function Value 15 */ } Bits; struct { word grpCV_10 :10; word grpCV1_10 :6; } MergedBits; } ADC3CV1STR; extern volatile ADC3CV1STR _ADC3CV1 @0xFFFF8488; #define ADC3CV1 _ADC3CV1.Word #define ADC3CV1_CV10 _ADC3CV1.Bits.CV10 #define ADC3CV1_CV11 _ADC3CV1.Bits.CV11 #define ADC3CV1_CV12 _ADC3CV1.Bits.CV12 #define ADC3CV1_CV13 _ADC3CV1.Bits.CV13 #define ADC3CV1_CV14 _ADC3CV1.Bits.CV14 #define ADC3CV1_CV15 _ADC3CV1.Bits.CV15 #define ADC3CV1_CV16 _ADC3CV1.Bits.CV16 #define ADC3CV1_CV17 _ADC3CV1.Bits.CV17 #define ADC3CV1_CV18 _ADC3CV1.Bits.CV18 #define ADC3CV1_CV19 _ADC3CV1.Bits.CV19 #define ADC3CV1_CV110 _ADC3CV1.Bits.CV110 #define ADC3CV1_CV111 _ADC3CV1.Bits.CV111 #define ADC3CV1_CV112 _ADC3CV1.Bits.CV112 #define ADC3CV1_CV113 _ADC3CV1.Bits.CV113 #define ADC3CV1_CV114 _ADC3CV1.Bits.CV114 #define ADC3CV1_CV115 _ADC3CV1.Bits.CV115 #define ADC3CV1_CV_10 _ADC3CV1.MergedBits.grpCV_10 #define ADC3CV1_CV1_10 _ADC3CV1.MergedBits.grpCV1_10 #define ADC3CV1_CV ADC3CV1_CV_10 #define ADC3CV1_CV1 ADC3CV1_CV1_10 #define ADC3CV1_CV10_MASK 1 #define ADC3CV1_CV11_MASK 2 #define ADC3CV1_CV12_MASK 4 #define ADC3CV1_CV13_MASK 8 #define ADC3CV1_CV14_MASK 16 #define ADC3CV1_CV15_MASK 32 #define ADC3CV1_CV16_MASK 64 #define ADC3CV1_CV17_MASK 128 #define ADC3CV1_CV18_MASK 256 #define ADC3CV1_CV19_MASK 512 #define ADC3CV1_CV110_MASK 1024 #define ADC3CV1_CV111_MASK 2048 #define ADC3CV1_CV112_MASK 4096 #define ADC3CV1_CV113_MASK 8192 #define ADC3CV1_CV114_MASK 16384 #define ADC3CV1_CV115_MASK 32768 #define ADC3CV1_CV_10_MASK 1023 #define ADC3CV1_CV_10_BITNUM 0 #define ADC3CV1_CV1_10_MASK 64512 #define ADC3CV1_CV1_10_BITNUM 10 /*** ADC3CV2 - Compare Value 2 Register; 0xFFFF848A ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC3CV2H - Compare Value 2 High Register; 0xFFFF848A ***/ union { byte Byte; struct { byte CV28 :1; /* Compare Function Value 8 */ byte CV29 :1; /* Compare Function Value 9 */ byte CV210 :1; /* Compare Function Value 10 */ byte CV211 :1; /* Compare Function Value 11 */ byte CV212 :1; /* Compare Function Value 12 */ byte CV213 :1; /* Compare Function Value 13 */ byte CV214 :1; /* Compare Function Value 14 */ byte CV215 :1; /* Compare Function Value 15 */ } Bits; struct { byte grpCV_28 :2; byte grpCV2_10 :6; } MergedBits; } ADC3CV2HSTR; #define ADC3CV2H _ADC3CV2.Overlap_STR.ADC3CV2HSTR.Byte #define ADC3CV2H_CV28 _ADC3CV2.Overlap_STR.ADC3CV2HSTR.Bits.CV28 #define ADC3CV2H_CV29 _ADC3CV2.Overlap_STR.ADC3CV2HSTR.Bits.CV29 #define ADC3CV2H_CV210 _ADC3CV2.Overlap_STR.ADC3CV2HSTR.Bits.CV210 #define ADC3CV2H_CV211 _ADC3CV2.Overlap_STR.ADC3CV2HSTR.Bits.CV211 #define ADC3CV2H_CV212 _ADC3CV2.Overlap_STR.ADC3CV2HSTR.Bits.CV212 #define ADC3CV2H_CV213 _ADC3CV2.Overlap_STR.ADC3CV2HSTR.Bits.CV213 #define ADC3CV2H_CV214 _ADC3CV2.Overlap_STR.ADC3CV2HSTR.Bits.CV214 #define ADC3CV2H_CV215 _ADC3CV2.Overlap_STR.ADC3CV2HSTR.Bits.CV215 #define ADC3CV2H_CV_28 _ADC3CV2.Overlap_STR.ADC3CV2HSTR.MergedBits.grpCV_28 #define ADC3CV2H_CV2_10 _ADC3CV2.Overlap_STR.ADC3CV2HSTR.MergedBits.grpCV2_10 #define ADC3CV2H_CV ADC3CV2H_CV_28 #define ADC3CV2H_CV2 ADC3CV2H_CV2_10 #define ADC3CV2H_CV28_MASK 1 #define ADC3CV2H_CV29_MASK 2 #define ADC3CV2H_CV210_MASK 4 #define ADC3CV2H_CV211_MASK 8 #define ADC3CV2H_CV212_MASK 16 #define ADC3CV2H_CV213_MASK 32 #define ADC3CV2H_CV214_MASK 64 #define ADC3CV2H_CV215_MASK 128 #define ADC3CV2H_CV_28_MASK 3 #define ADC3CV2H_CV_28_BITNUM 0 #define ADC3CV2H_CV2_10_MASK 252 #define ADC3CV2H_CV2_10_BITNUM 2 /*** ADC3CV2L - Compare Value 2 Low Register; 0xFFFF848B ***/ union { byte Byte; struct { byte CV20 :1; /* Compare Function Value 0 */ byte CV21 :1; /* Compare Function Value 1 */ byte CV22 :1; /* Compare Function Value 2 */ byte CV23 :1; /* Compare Function Value 3 */ byte CV24 :1; /* Compare Function Value 4 */ byte CV25 :1; /* Compare Function Value 5 */ byte CV26 :1; /* Compare Function Value 6 */ byte CV27 :1; /* Compare Function Value 7 */ } Bits; } ADC3CV2LSTR; #define ADC3CV2L _ADC3CV2.Overlap_STR.ADC3CV2LSTR.Byte #define ADC3CV2L_CV20 _ADC3CV2.Overlap_STR.ADC3CV2LSTR.Bits.CV20 #define ADC3CV2L_CV21 _ADC3CV2.Overlap_STR.ADC3CV2LSTR.Bits.CV21 #define ADC3CV2L_CV22 _ADC3CV2.Overlap_STR.ADC3CV2LSTR.Bits.CV22 #define ADC3CV2L_CV23 _ADC3CV2.Overlap_STR.ADC3CV2LSTR.Bits.CV23 #define ADC3CV2L_CV24 _ADC3CV2.Overlap_STR.ADC3CV2LSTR.Bits.CV24 #define ADC3CV2L_CV25 _ADC3CV2.Overlap_STR.ADC3CV2LSTR.Bits.CV25 #define ADC3CV2L_CV26 _ADC3CV2.Overlap_STR.ADC3CV2LSTR.Bits.CV26 #define ADC3CV2L_CV27 _ADC3CV2.Overlap_STR.ADC3CV2LSTR.Bits.CV27 #define ADC3CV2L_CV20_MASK 1 #define ADC3CV2L_CV21_MASK 2 #define ADC3CV2L_CV22_MASK 4 #define ADC3CV2L_CV23_MASK 8 #define ADC3CV2L_CV24_MASK 16 #define ADC3CV2L_CV25_MASK 32 #define ADC3CV2L_CV26_MASK 64 #define ADC3CV2L_CV27_MASK 128 } Overlap_STR; struct { word CV20 :1; /* Compare Function Value 0 */ word CV21 :1; /* Compare Function Value 1 */ word CV22 :1; /* Compare Function Value 2 */ word CV23 :1; /* Compare Function Value 3 */ word CV24 :1; /* Compare Function Value 4 */ word CV25 :1; /* Compare Function Value 5 */ word CV26 :1; /* Compare Function Value 6 */ word CV27 :1; /* Compare Function Value 7 */ word CV28 :1; /* Compare Function Value 8 */ word CV29 :1; /* Compare Function Value 9 */ word CV210 :1; /* Compare Function Value 10 */ word CV211 :1; /* Compare Function Value 11 */ word CV212 :1; /* Compare Function Value 12 */ word CV213 :1; /* Compare Function Value 13 */ word CV214 :1; /* Compare Function Value 14 */ word CV215 :1; /* Compare Function Value 15 */ } Bits; struct { word grpCV_20 :10; word grpCV2_10 :6; } MergedBits; } ADC3CV2STR; extern volatile ADC3CV2STR _ADC3CV2 @0xFFFF848A; #define ADC3CV2 _ADC3CV2.Word #define ADC3CV2_CV20 _ADC3CV2.Bits.CV20 #define ADC3CV2_CV21 _ADC3CV2.Bits.CV21 #define ADC3CV2_CV22 _ADC3CV2.Bits.CV22 #define ADC3CV2_CV23 _ADC3CV2.Bits.CV23 #define ADC3CV2_CV24 _ADC3CV2.Bits.CV24 #define ADC3CV2_CV25 _ADC3CV2.Bits.CV25 #define ADC3CV2_CV26 _ADC3CV2.Bits.CV26 #define ADC3CV2_CV27 _ADC3CV2.Bits.CV27 #define ADC3CV2_CV28 _ADC3CV2.Bits.CV28 #define ADC3CV2_CV29 _ADC3CV2.Bits.CV29 #define ADC3CV2_CV210 _ADC3CV2.Bits.CV210 #define ADC3CV2_CV211 _ADC3CV2.Bits.CV211 #define ADC3CV2_CV212 _ADC3CV2.Bits.CV212 #define ADC3CV2_CV213 _ADC3CV2.Bits.CV213 #define ADC3CV2_CV214 _ADC3CV2.Bits.CV214 #define ADC3CV2_CV215 _ADC3CV2.Bits.CV215 #define ADC3CV2_CV_20 _ADC3CV2.MergedBits.grpCV_20 #define ADC3CV2_CV2_10 _ADC3CV2.MergedBits.grpCV2_10 #define ADC3CV2_CV ADC3CV2_CV_20 #define ADC3CV2_CV2 ADC3CV2_CV2_10 #define ADC3CV2_CV20_MASK 1 #define ADC3CV2_CV21_MASK 2 #define ADC3CV2_CV22_MASK 4 #define ADC3CV2_CV23_MASK 8 #define ADC3CV2_CV24_MASK 16 #define ADC3CV2_CV25_MASK 32 #define ADC3CV2_CV26_MASK 64 #define ADC3CV2_CV27_MASK 128 #define ADC3CV2_CV28_MASK 256 #define ADC3CV2_CV29_MASK 512 #define ADC3CV2_CV210_MASK 1024 #define ADC3CV2_CV211_MASK 2048 #define ADC3CV2_CV212_MASK 4096 #define ADC3CV2_CV213_MASK 8192 #define ADC3CV2_CV214_MASK 16384 #define ADC3CV2_CV215_MASK 32768 #define ADC3CV2_CV_20_MASK 1023 #define ADC3CV2_CV_20_BITNUM 0 #define ADC3CV2_CV2_10_MASK 64512 #define ADC3CV2_CV2_10_BITNUM 10 /*** ADC3SC2 - Status and Control Register 2; 0xFFFF848C ***/ typedef union { byte Byte; struct { byte REFSEL0 :1; /* Voltage Reference Selection, bit 0 */ byte REFSEL1 :1; /* Voltage Reference Selection, bit 1 */ byte :1; byte ACREN :1; /* Compare Function Range Enable */ byte ACFGT :1; /* Compare Function Greater Than Enable */ byte ACFE :1; /* Compare Function Enable - ACFE is used to enable the compare function */ byte ADTRG :1; /* Conversion Trigger Select-ADTRG is used to select the type of trigger to be used for initiating a conversion */ byte ADACT :1; /* Conversion Active - ADACT indicates that a conversion is in progress. ADACT is set when a conversion is initiated and cleared when a conversion is completed or aborted */ } Bits; struct { byte grpREFSEL :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ADC3SC2STR; extern volatile ADC3SC2STR _ADC3SC2 @0xFFFF848C; #define ADC3SC2 _ADC3SC2.Byte #define ADC3SC2_REFSEL0 _ADC3SC2.Bits.REFSEL0 #define ADC3SC2_REFSEL1 _ADC3SC2.Bits.REFSEL1 #define ADC3SC2_ACREN _ADC3SC2.Bits.ACREN #define ADC3SC2_ACFGT _ADC3SC2.Bits.ACFGT #define ADC3SC2_ACFE _ADC3SC2.Bits.ACFE #define ADC3SC2_ADTRG _ADC3SC2.Bits.ADTRG #define ADC3SC2_ADACT _ADC3SC2.Bits.ADACT #define ADC3SC2_REFSEL _ADC3SC2.MergedBits.grpREFSEL #define ADC3SC2_REFSEL0_MASK 1 #define ADC3SC2_REFSEL1_MASK 2 #define ADC3SC2_ACREN_MASK 8 #define ADC3SC2_ACFGT_MASK 16 #define ADC3SC2_ACFE_MASK 32 #define ADC3SC2_ADTRG_MASK 64 #define ADC3SC2_ADACT_MASK 128 #define ADC3SC2_REFSEL_MASK 3 #define ADC3SC2_REFSEL_BITNUM 0 /*** ADC3SC3 - Status and Control Register 3; 0xFFFF848D ***/ typedef union { byte Byte; struct { byte AVGS0 :1; /* Hardware Average select, bit 0 */ byte AVGS1 :1; /* Hardware Average select, bit 1 */ byte AVGE :1; /* Hardware average enable - AVGE enables the hardware average function of the ADC */ byte ADCO :1; /* Continuous Conversion Enable - ADCO enables continuous conversions */ byte :1; byte :1; byte CALF :1; /* Calibration Failed Flag - CALF displays the result of the calibration sequence */ byte CAL :1; /* Calibration - CAL begins the calibration sequence when set */ } Bits; struct { byte grpAVGS :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ADC3SC3STR; extern volatile ADC3SC3STR _ADC3SC3 @0xFFFF848D; #define ADC3SC3 _ADC3SC3.Byte #define ADC3SC3_AVGS0 _ADC3SC3.Bits.AVGS0 #define ADC3SC3_AVGS1 _ADC3SC3.Bits.AVGS1 #define ADC3SC3_AVGE _ADC3SC3.Bits.AVGE #define ADC3SC3_ADCO _ADC3SC3.Bits.ADCO #define ADC3SC3_CALF _ADC3SC3.Bits.CALF #define ADC3SC3_CAL _ADC3SC3.Bits.CAL #define ADC3SC3_AVGS _ADC3SC3.MergedBits.grpAVGS #define ADC3SC3_AVGS0_MASK 1 #define ADC3SC3_AVGS1_MASK 2 #define ADC3SC3_AVGE_MASK 4 #define ADC3SC3_ADCO_MASK 8 #define ADC3SC3_CALF_MASK 64 #define ADC3SC3_CAL_MASK 128 #define ADC3SC3_AVGS_MASK 3 #define ADC3SC3_AVGS_BITNUM 0 /*** ADC3OFS - Offset Correction Register; 0xFFFF848E ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC3OFSH - Offset Correction High Register; 0xFFFF848E ***/ union { byte Byte; struct { byte OFS8 :1; /* Offset error correction value bit 8 */ byte OFS9 :1; /* Offset error correction value bit 9 */ byte OFS10 :1; /* Offset error correction value bit 10 */ byte OFS11 :1; /* Offset error correction value bit 11 */ byte OFS12 :1; /* Offset error correction value bit 12 */ byte OFS13 :1; /* Offset error correction value bit 13 */ byte OFS14 :1; /* Offset error correction value bit 14 */ byte OFS15 :1; /* Offset error correction value bit 15 */ } Bits; } ADC3OFSHSTR; #define ADC3OFSH _ADC3OFS.Overlap_STR.ADC3OFSHSTR.Byte #define ADC3OFSH_OFS8 _ADC3OFS.Overlap_STR.ADC3OFSHSTR.Bits.OFS8 #define ADC3OFSH_OFS9 _ADC3OFS.Overlap_STR.ADC3OFSHSTR.Bits.OFS9 #define ADC3OFSH_OFS10 _ADC3OFS.Overlap_STR.ADC3OFSHSTR.Bits.OFS10 #define ADC3OFSH_OFS11 _ADC3OFS.Overlap_STR.ADC3OFSHSTR.Bits.OFS11 #define ADC3OFSH_OFS12 _ADC3OFS.Overlap_STR.ADC3OFSHSTR.Bits.OFS12 #define ADC3OFSH_OFS13 _ADC3OFS.Overlap_STR.ADC3OFSHSTR.Bits.OFS13 #define ADC3OFSH_OFS14 _ADC3OFS.Overlap_STR.ADC3OFSHSTR.Bits.OFS14 #define ADC3OFSH_OFS15 _ADC3OFS.Overlap_STR.ADC3OFSHSTR.Bits.OFS15 #define ADC3OFSH_OFS8_MASK 1 #define ADC3OFSH_OFS9_MASK 2 #define ADC3OFSH_OFS10_MASK 4 #define ADC3OFSH_OFS11_MASK 8 #define ADC3OFSH_OFS12_MASK 16 #define ADC3OFSH_OFS13_MASK 32 #define ADC3OFSH_OFS14_MASK 64 #define ADC3OFSH_OFS15_MASK 128 /*** ADC3OFSL - Offset Correction Low Register; 0xFFFF848F ***/ union { byte Byte; struct { byte OFS0 :1; /* Offset error correction value bit 0 */ byte OFS1 :1; /* Offset error correction value bit 1 */ byte OFS2 :1; /* Offset error correction value bit 2 */ byte OFS3 :1; /* Offset error correction value bit 3 */ byte OFS4 :1; /* Offset error correction value bit 4 */ byte OFS5 :1; /* Offset error correction value bit 5 */ byte OFS6 :1; /* Offset error correction value bit 6 */ byte OFS7 :1; /* Offset error correction value bit 7 */ } Bits; } ADC3OFSLSTR; #define ADC3OFSL _ADC3OFS.Overlap_STR.ADC3OFSLSTR.Byte #define ADC3OFSL_OFS0 _ADC3OFS.Overlap_STR.ADC3OFSLSTR.Bits.OFS0 #define ADC3OFSL_OFS1 _ADC3OFS.Overlap_STR.ADC3OFSLSTR.Bits.OFS1 #define ADC3OFSL_OFS2 _ADC3OFS.Overlap_STR.ADC3OFSLSTR.Bits.OFS2 #define ADC3OFSL_OFS3 _ADC3OFS.Overlap_STR.ADC3OFSLSTR.Bits.OFS3 #define ADC3OFSL_OFS4 _ADC3OFS.Overlap_STR.ADC3OFSLSTR.Bits.OFS4 #define ADC3OFSL_OFS5 _ADC3OFS.Overlap_STR.ADC3OFSLSTR.Bits.OFS5 #define ADC3OFSL_OFS6 _ADC3OFS.Overlap_STR.ADC3OFSLSTR.Bits.OFS6 #define ADC3OFSL_OFS7 _ADC3OFS.Overlap_STR.ADC3OFSLSTR.Bits.OFS7 #define ADC3OFSL_OFS0_MASK 1 #define ADC3OFSL_OFS1_MASK 2 #define ADC3OFSL_OFS2_MASK 4 #define ADC3OFSL_OFS3_MASK 8 #define ADC3OFSL_OFS4_MASK 16 #define ADC3OFSL_OFS5_MASK 32 #define ADC3OFSL_OFS6_MASK 64 #define ADC3OFSL_OFS7_MASK 128 } Overlap_STR; struct { word OFS0 :1; /* Offset error correction value bit 0 */ word OFS1 :1; /* Offset error correction value bit 1 */ word OFS2 :1; /* Offset error correction value bit 2 */ word OFS3 :1; /* Offset error correction value bit 3 */ word OFS4 :1; /* Offset error correction value bit 4 */ word OFS5 :1; /* Offset error correction value bit 5 */ word OFS6 :1; /* Offset error correction value bit 6 */ word OFS7 :1; /* Offset error correction value bit 7 */ word OFS8 :1; /* Offset error correction value bit 8 */ word OFS9 :1; /* Offset error correction value bit 9 */ word OFS10 :1; /* Offset error correction value bit 10 */ word OFS11 :1; /* Offset error correction value bit 11 */ word OFS12 :1; /* Offset error correction value bit 12 */ word OFS13 :1; /* Offset error correction value bit 13 */ word OFS14 :1; /* Offset error correction value bit 14 */ word OFS15 :1; /* Offset error correction value bit 15 */ } Bits; } ADC3OFSSTR; extern volatile ADC3OFSSTR _ADC3OFS @0xFFFF848E; #define ADC3OFS _ADC3OFS.Word #define ADC3OFS_OFS0 _ADC3OFS.Bits.OFS0 #define ADC3OFS_OFS1 _ADC3OFS.Bits.OFS1 #define ADC3OFS_OFS2 _ADC3OFS.Bits.OFS2 #define ADC3OFS_OFS3 _ADC3OFS.Bits.OFS3 #define ADC3OFS_OFS4 _ADC3OFS.Bits.OFS4 #define ADC3OFS_OFS5 _ADC3OFS.Bits.OFS5 #define ADC3OFS_OFS6 _ADC3OFS.Bits.OFS6 #define ADC3OFS_OFS7 _ADC3OFS.Bits.OFS7 #define ADC3OFS_OFS8 _ADC3OFS.Bits.OFS8 #define ADC3OFS_OFS9 _ADC3OFS.Bits.OFS9 #define ADC3OFS_OFS10 _ADC3OFS.Bits.OFS10 #define ADC3OFS_OFS11 _ADC3OFS.Bits.OFS11 #define ADC3OFS_OFS12 _ADC3OFS.Bits.OFS12 #define ADC3OFS_OFS13 _ADC3OFS.Bits.OFS13 #define ADC3OFS_OFS14 _ADC3OFS.Bits.OFS14 #define ADC3OFS_OFS15 _ADC3OFS.Bits.OFS15 #define ADC3OFS_OFS0_MASK 1 #define ADC3OFS_OFS1_MASK 2 #define ADC3OFS_OFS2_MASK 4 #define ADC3OFS_OFS3_MASK 8 #define ADC3OFS_OFS4_MASK 16 #define ADC3OFS_OFS5_MASK 32 #define ADC3OFS_OFS6_MASK 64 #define ADC3OFS_OFS7_MASK 128 #define ADC3OFS_OFS8_MASK 256 #define ADC3OFS_OFS9_MASK 512 #define ADC3OFS_OFS10_MASK 1024 #define ADC3OFS_OFS11_MASK 2048 #define ADC3OFS_OFS12_MASK 4096 #define ADC3OFS_OFS13_MASK 8192 #define ADC3OFS_OFS14_MASK 16384 #define ADC3OFS_OFS15_MASK 32768 /*** ADC3PG - Plus-Side Gain Register; 0xFFFF8490 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC3PGH - Plus-Side Gain High Register; 0xFFFF8490 ***/ union { byte Byte; struct { byte PG8 :1; /* Gain error correction for the plus-side input value bit 8 */ byte PG9 :1; /* Gain error correction for the plus-side input value bit 9 */ byte PG10 :1; /* Gain error correction for the plus-side input value bit 10 */ byte PG11 :1; /* Gain error correction for the plus-side input value bit 11 */ byte PG12 :1; /* Gain error correction for the plus-side input value bit 12 */ byte PG13 :1; /* Gain error correction for the plus-side input value bit 13 */ byte PG14 :1; /* Gain error correction for the plus-side input value bit 14 */ byte PG15 :1; /* Gain error correction for the plus-side input value bit 15 */ } Bits; } ADC3PGHSTR; #define ADC3PGH _ADC3PG.Overlap_STR.ADC3PGHSTR.Byte #define ADC3PGH_PG8 _ADC3PG.Overlap_STR.ADC3PGHSTR.Bits.PG8 #define ADC3PGH_PG9 _ADC3PG.Overlap_STR.ADC3PGHSTR.Bits.PG9 #define ADC3PGH_PG10 _ADC3PG.Overlap_STR.ADC3PGHSTR.Bits.PG10 #define ADC3PGH_PG11 _ADC3PG.Overlap_STR.ADC3PGHSTR.Bits.PG11 #define ADC3PGH_PG12 _ADC3PG.Overlap_STR.ADC3PGHSTR.Bits.PG12 #define ADC3PGH_PG13 _ADC3PG.Overlap_STR.ADC3PGHSTR.Bits.PG13 #define ADC3PGH_PG14 _ADC3PG.Overlap_STR.ADC3PGHSTR.Bits.PG14 #define ADC3PGH_PG15 _ADC3PG.Overlap_STR.ADC3PGHSTR.Bits.PG15 #define ADC3PGH_PG8_MASK 1 #define ADC3PGH_PG9_MASK 2 #define ADC3PGH_PG10_MASK 4 #define ADC3PGH_PG11_MASK 8 #define ADC3PGH_PG12_MASK 16 #define ADC3PGH_PG13_MASK 32 #define ADC3PGH_PG14_MASK 64 #define ADC3PGH_PG15_MASK 128 /*** ADC3PGL - Plus-Side Gain Low Register; 0xFFFF8491 ***/ union { byte Byte; struct { byte PG0 :1; /* Gain error correction for the plus-side input value bit 0 */ byte PG1 :1; /* Gain error correction for the plus-side input value bit 1 */ byte PG2 :1; /* Gain error correction for the plus-side input value bit 2 */ byte PG3 :1; /* Gain error correction for the plus-side input value bit 3 */ byte PG4 :1; /* Gain error correction for the plus-side input value bit 4 */ byte PG5 :1; /* Gain error correction for the plus-side input value bit 5 */ byte PG6 :1; /* Gain error correction for the plus-side input value bit 6 */ byte PG7 :1; /* Gain error correction for the plus-side input value bit 7 */ } Bits; } ADC3PGLSTR; #define ADC3PGL _ADC3PG.Overlap_STR.ADC3PGLSTR.Byte #define ADC3PGL_PG0 _ADC3PG.Overlap_STR.ADC3PGLSTR.Bits.PG0 #define ADC3PGL_PG1 _ADC3PG.Overlap_STR.ADC3PGLSTR.Bits.PG1 #define ADC3PGL_PG2 _ADC3PG.Overlap_STR.ADC3PGLSTR.Bits.PG2 #define ADC3PGL_PG3 _ADC3PG.Overlap_STR.ADC3PGLSTR.Bits.PG3 #define ADC3PGL_PG4 _ADC3PG.Overlap_STR.ADC3PGLSTR.Bits.PG4 #define ADC3PGL_PG5 _ADC3PG.Overlap_STR.ADC3PGLSTR.Bits.PG5 #define ADC3PGL_PG6 _ADC3PG.Overlap_STR.ADC3PGLSTR.Bits.PG6 #define ADC3PGL_PG7 _ADC3PG.Overlap_STR.ADC3PGLSTR.Bits.PG7 #define ADC3PGL_PG0_MASK 1 #define ADC3PGL_PG1_MASK 2 #define ADC3PGL_PG2_MASK 4 #define ADC3PGL_PG3_MASK 8 #define ADC3PGL_PG4_MASK 16 #define ADC3PGL_PG5_MASK 32 #define ADC3PGL_PG6_MASK 64 #define ADC3PGL_PG7_MASK 128 } Overlap_STR; struct { word PG0 :1; /* Gain error correction for the plus-side input value bit 0 */ word PG1 :1; /* Gain error correction for the plus-side input value bit 1 */ word PG2 :1; /* Gain error correction for the plus-side input value bit 2 */ word PG3 :1; /* Gain error correction for the plus-side input value bit 3 */ word PG4 :1; /* Gain error correction for the plus-side input value bit 4 */ word PG5 :1; /* Gain error correction for the plus-side input value bit 5 */ word PG6 :1; /* Gain error correction for the plus-side input value bit 6 */ word PG7 :1; /* Gain error correction for the plus-side input value bit 7 */ word PG8 :1; /* Gain error correction for the plus-side input value bit 8 */ word PG9 :1; /* Gain error correction for the plus-side input value bit 9 */ word PG10 :1; /* Gain error correction for the plus-side input value bit 10 */ word PG11 :1; /* Gain error correction for the plus-side input value bit 11 */ word PG12 :1; /* Gain error correction for the plus-side input value bit 12 */ word PG13 :1; /* Gain error correction for the plus-side input value bit 13 */ word PG14 :1; /* Gain error correction for the plus-side input value bit 14 */ word PG15 :1; /* Gain error correction for the plus-side input value bit 15 */ } Bits; } ADC3PGSTR; extern volatile ADC3PGSTR _ADC3PG @0xFFFF8490; #define ADC3PG _ADC3PG.Word #define ADC3PG_PG0 _ADC3PG.Bits.PG0 #define ADC3PG_PG1 _ADC3PG.Bits.PG1 #define ADC3PG_PG2 _ADC3PG.Bits.PG2 #define ADC3PG_PG3 _ADC3PG.Bits.PG3 #define ADC3PG_PG4 _ADC3PG.Bits.PG4 #define ADC3PG_PG5 _ADC3PG.Bits.PG5 #define ADC3PG_PG6 _ADC3PG.Bits.PG6 #define ADC3PG_PG7 _ADC3PG.Bits.PG7 #define ADC3PG_PG8 _ADC3PG.Bits.PG8 #define ADC3PG_PG9 _ADC3PG.Bits.PG9 #define ADC3PG_PG10 _ADC3PG.Bits.PG10 #define ADC3PG_PG11 _ADC3PG.Bits.PG11 #define ADC3PG_PG12 _ADC3PG.Bits.PG12 #define ADC3PG_PG13 _ADC3PG.Bits.PG13 #define ADC3PG_PG14 _ADC3PG.Bits.PG14 #define ADC3PG_PG15 _ADC3PG.Bits.PG15 #define ADC3PG_PG0_MASK 1 #define ADC3PG_PG1_MASK 2 #define ADC3PG_PG2_MASK 4 #define ADC3PG_PG3_MASK 8 #define ADC3PG_PG4_MASK 16 #define ADC3PG_PG5_MASK 32 #define ADC3PG_PG6_MASK 64 #define ADC3PG_PG7_MASK 128 #define ADC3PG_PG8_MASK 256 #define ADC3PG_PG9_MASK 512 #define ADC3PG_PG10_MASK 1024 #define ADC3PG_PG11_MASK 2048 #define ADC3PG_PG12_MASK 4096 #define ADC3PG_PG13_MASK 8192 #define ADC3PG_PG14_MASK 16384 #define ADC3PG_PG15_MASK 32768 /*** ADC3MG - Minus-Side Gain Register; 0xFFFF8492 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC3MGH - Minus-Side Gain High Register; 0xFFFF8492 ***/ union { byte Byte; struct { byte MG8 :1; /* Gain error correction for the minus-side input value bit 8 */ byte MG9 :1; /* Gain error correction for the minus-side input value bit 9 */ byte MG10 :1; /* Gain error correction for the minus-side input value bit 10 */ byte MG11 :1; /* Gain error correction for the minus-side input value bit 11 */ byte MG12 :1; /* Gain error correction for the minus-side input value bit 12 */ byte MG13 :1; /* Gain error correction for the minus-side input value bit 13 */ byte MG14 :1; /* Gain error correction for the minus-side input value bit 14 */ byte MG15 :1; /* Gain error correction for the minus-side input value bit 15 */ } Bits; } ADC3MGHSTR; #define ADC3MGH _ADC3MG.Overlap_STR.ADC3MGHSTR.Byte #define ADC3MGH_MG8 _ADC3MG.Overlap_STR.ADC3MGHSTR.Bits.MG8 #define ADC3MGH_MG9 _ADC3MG.Overlap_STR.ADC3MGHSTR.Bits.MG9 #define ADC3MGH_MG10 _ADC3MG.Overlap_STR.ADC3MGHSTR.Bits.MG10 #define ADC3MGH_MG11 _ADC3MG.Overlap_STR.ADC3MGHSTR.Bits.MG11 #define ADC3MGH_MG12 _ADC3MG.Overlap_STR.ADC3MGHSTR.Bits.MG12 #define ADC3MGH_MG13 _ADC3MG.Overlap_STR.ADC3MGHSTR.Bits.MG13 #define ADC3MGH_MG14 _ADC3MG.Overlap_STR.ADC3MGHSTR.Bits.MG14 #define ADC3MGH_MG15 _ADC3MG.Overlap_STR.ADC3MGHSTR.Bits.MG15 #define ADC3MGH_MG8_MASK 1 #define ADC3MGH_MG9_MASK 2 #define ADC3MGH_MG10_MASK 4 #define ADC3MGH_MG11_MASK 8 #define ADC3MGH_MG12_MASK 16 #define ADC3MGH_MG13_MASK 32 #define ADC3MGH_MG14_MASK 64 #define ADC3MGH_MG15_MASK 128 /*** ADC3MGL - Minus-Side Gain Low Register; 0xFFFF8493 ***/ union { byte Byte; struct { byte MG0 :1; /* Gain error correction for the minus-side input value bit 0 */ byte MG1 :1; /* Gain error correction for the minus-side input value bit 1 */ byte MG2 :1; /* Gain error correction for the minus-side input value bit 2 */ byte MG3 :1; /* Gain error correction for the minus-side input value bit 3 */ byte MG4 :1; /* Gain error correction for the minus-side input value bit 4 */ byte MG5 :1; /* Gain error correction for the minus-side input value bit 5 */ byte MG6 :1; /* Gain error correction for the minus-side input value bit 6 */ byte MG7 :1; /* Gain error correction for the minus-side input value bit 7 */ } Bits; } ADC3MGLSTR; #define ADC3MGL _ADC3MG.Overlap_STR.ADC3MGLSTR.Byte #define ADC3MGL_MG0 _ADC3MG.Overlap_STR.ADC3MGLSTR.Bits.MG0 #define ADC3MGL_MG1 _ADC3MG.Overlap_STR.ADC3MGLSTR.Bits.MG1 #define ADC3MGL_MG2 _ADC3MG.Overlap_STR.ADC3MGLSTR.Bits.MG2 #define ADC3MGL_MG3 _ADC3MG.Overlap_STR.ADC3MGLSTR.Bits.MG3 #define ADC3MGL_MG4 _ADC3MG.Overlap_STR.ADC3MGLSTR.Bits.MG4 #define ADC3MGL_MG5 _ADC3MG.Overlap_STR.ADC3MGLSTR.Bits.MG5 #define ADC3MGL_MG6 _ADC3MG.Overlap_STR.ADC3MGLSTR.Bits.MG6 #define ADC3MGL_MG7 _ADC3MG.Overlap_STR.ADC3MGLSTR.Bits.MG7 #define ADC3MGL_MG0_MASK 1 #define ADC3MGL_MG1_MASK 2 #define ADC3MGL_MG2_MASK 4 #define ADC3MGL_MG3_MASK 8 #define ADC3MGL_MG4_MASK 16 #define ADC3MGL_MG5_MASK 32 #define ADC3MGL_MG6_MASK 64 #define ADC3MGL_MG7_MASK 128 } Overlap_STR; struct { word MG0 :1; /* Gain error correction for the minus-side input value bit 0 */ word MG1 :1; /* Gain error correction for the minus-side input value bit 1 */ word MG2 :1; /* Gain error correction for the minus-side input value bit 2 */ word MG3 :1; /* Gain error correction for the minus-side input value bit 3 */ word MG4 :1; /* Gain error correction for the minus-side input value bit 4 */ word MG5 :1; /* Gain error correction for the minus-side input value bit 5 */ word MG6 :1; /* Gain error correction for the minus-side input value bit 6 */ word MG7 :1; /* Gain error correction for the minus-side input value bit 7 */ word MG8 :1; /* Gain error correction for the minus-side input value bit 8 */ word MG9 :1; /* Gain error correction for the minus-side input value bit 9 */ word MG10 :1; /* Gain error correction for the minus-side input value bit 10 */ word MG11 :1; /* Gain error correction for the minus-side input value bit 11 */ word MG12 :1; /* Gain error correction for the minus-side input value bit 12 */ word MG13 :1; /* Gain error correction for the minus-side input value bit 13 */ word MG14 :1; /* Gain error correction for the minus-side input value bit 14 */ word MG15 :1; /* Gain error correction for the minus-side input value bit 15 */ } Bits; } ADC3MGSTR; extern volatile ADC3MGSTR _ADC3MG @0xFFFF8492; #define ADC3MG _ADC3MG.Word #define ADC3MG_MG0 _ADC3MG.Bits.MG0 #define ADC3MG_MG1 _ADC3MG.Bits.MG1 #define ADC3MG_MG2 _ADC3MG.Bits.MG2 #define ADC3MG_MG3 _ADC3MG.Bits.MG3 #define ADC3MG_MG4 _ADC3MG.Bits.MG4 #define ADC3MG_MG5 _ADC3MG.Bits.MG5 #define ADC3MG_MG6 _ADC3MG.Bits.MG6 #define ADC3MG_MG7 _ADC3MG.Bits.MG7 #define ADC3MG_MG8 _ADC3MG.Bits.MG8 #define ADC3MG_MG9 _ADC3MG.Bits.MG9 #define ADC3MG_MG10 _ADC3MG.Bits.MG10 #define ADC3MG_MG11 _ADC3MG.Bits.MG11 #define ADC3MG_MG12 _ADC3MG.Bits.MG12 #define ADC3MG_MG13 _ADC3MG.Bits.MG13 #define ADC3MG_MG14 _ADC3MG.Bits.MG14 #define ADC3MG_MG15 _ADC3MG.Bits.MG15 #define ADC3MG_MG0_MASK 1 #define ADC3MG_MG1_MASK 2 #define ADC3MG_MG2_MASK 4 #define ADC3MG_MG3_MASK 8 #define ADC3MG_MG4_MASK 16 #define ADC3MG_MG5_MASK 32 #define ADC3MG_MG6_MASK 64 #define ADC3MG_MG7_MASK 128 #define ADC3MG_MG8_MASK 256 #define ADC3MG_MG9_MASK 512 #define ADC3MG_MG10_MASK 1024 #define ADC3MG_MG11_MASK 2048 #define ADC3MG_MG12_MASK 4096 #define ADC3MG_MG13_MASK 8192 #define ADC3MG_MG14_MASK 16384 #define ADC3MG_MG15_MASK 32768 /*** ADC3CLPD - Plus-Side General Calibration Value D Register; 0xFFFF8494 ***/ typedef union { byte Byte; struct { byte CLPD0 :1; /* Plus-Side General Calibration Value D bit 0 */ byte CLPD1 :1; /* Plus-Side General Calibration Value D bit 1 */ byte CLPD2 :1; /* Plus-Side General Calibration Value D bit 2 */ byte CLPD3 :1; /* Plus-Side General Calibration Value D bit 3 */ byte CLPD4 :1; /* Plus-Side General Calibration Value D bit 4 */ byte CLPD5 :1; /* Plus-Side General Calibration Value D bit 5 */ byte :1; byte :1; } Bits; struct { byte grpCLPD :6; byte :1; byte :1; } MergedBits; } ADC3CLPDSTR; extern volatile ADC3CLPDSTR _ADC3CLPD @0xFFFF8494; #define ADC3CLPD _ADC3CLPD.Byte #define ADC3CLPD_CLPD0 _ADC3CLPD.Bits.CLPD0 #define ADC3CLPD_CLPD1 _ADC3CLPD.Bits.CLPD1 #define ADC3CLPD_CLPD2 _ADC3CLPD.Bits.CLPD2 #define ADC3CLPD_CLPD3 _ADC3CLPD.Bits.CLPD3 #define ADC3CLPD_CLPD4 _ADC3CLPD.Bits.CLPD4 #define ADC3CLPD_CLPD5 _ADC3CLPD.Bits.CLPD5 #define ADC3CLPD_CLPD _ADC3CLPD.MergedBits.grpCLPD #define ADC3CLPD_CLPD0_MASK 1 #define ADC3CLPD_CLPD1_MASK 2 #define ADC3CLPD_CLPD2_MASK 4 #define ADC3CLPD_CLPD3_MASK 8 #define ADC3CLPD_CLPD4_MASK 16 #define ADC3CLPD_CLPD5_MASK 32 #define ADC3CLPD_CLPD_MASK 63 #define ADC3CLPD_CLPD_BITNUM 0 /*** ADC3CLPS - Plus-Side General Calibration Value S Register; 0xFFFF8495 ***/ typedef union { byte Byte; struct { byte CLPS0 :1; /* Plus-Side General Calibration Value S bit 0 */ byte CLPS1 :1; /* Plus-Side General Calibration Value S bit 1 */ byte CLPS2 :1; /* Plus-Side General Calibration Value S bit 2 */ byte CLPS3 :1; /* Plus-Side General Calibration Value S bit 3 */ byte CLPS4 :1; /* Plus-Side General Calibration Value S bit 4 */ byte CLPS5 :1; /* Plus-Side General Calibration Value S bit 5 */ byte :1; byte :1; } Bits; struct { byte grpCLPS :6; byte :1; byte :1; } MergedBits; } ADC3CLPSSTR; extern volatile ADC3CLPSSTR _ADC3CLPS @0xFFFF8495; #define ADC3CLPS _ADC3CLPS.Byte #define ADC3CLPS_CLPS0 _ADC3CLPS.Bits.CLPS0 #define ADC3CLPS_CLPS1 _ADC3CLPS.Bits.CLPS1 #define ADC3CLPS_CLPS2 _ADC3CLPS.Bits.CLPS2 #define ADC3CLPS_CLPS3 _ADC3CLPS.Bits.CLPS3 #define ADC3CLPS_CLPS4 _ADC3CLPS.Bits.CLPS4 #define ADC3CLPS_CLPS5 _ADC3CLPS.Bits.CLPS5 #define ADC3CLPS_CLPS _ADC3CLPS.MergedBits.grpCLPS #define ADC3CLPS_CLPS0_MASK 1 #define ADC3CLPS_CLPS1_MASK 2 #define ADC3CLPS_CLPS2_MASK 4 #define ADC3CLPS_CLPS3_MASK 8 #define ADC3CLPS_CLPS4_MASK 16 #define ADC3CLPS_CLPS5_MASK 32 #define ADC3CLPS_CLPS_MASK 63 #define ADC3CLPS_CLPS_BITNUM 0 /*** ADC3CLP4 - Plus-Side General Calibration Value 4 Register; 0xFFFF8496 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC3CLP4H - Plus-Side General Calibration Value 4 High Register; 0xFFFF8496 ***/ union { byte Byte; struct { byte CLP48 :1; /* Plus-Side General Calibration Value 4 bit 8 */ byte CLP49 :1; /* Plus-Side General Calibration Value 4 bit 9 */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpCLP_48 :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ADC3CLP4HSTR; #define ADC3CLP4H _ADC3CLP4.Overlap_STR.ADC3CLP4HSTR.Byte #define ADC3CLP4H_CLP48 _ADC3CLP4.Overlap_STR.ADC3CLP4HSTR.Bits.CLP48 #define ADC3CLP4H_CLP49 _ADC3CLP4.Overlap_STR.ADC3CLP4HSTR.Bits.CLP49 #define ADC3CLP4H_CLP_48 _ADC3CLP4.Overlap_STR.ADC3CLP4HSTR.MergedBits.grpCLP_48 #define ADC3CLP4H_CLP ADC3CLP4H_CLP_48 #define ADC3CLP4H_CLP48_MASK 1 #define ADC3CLP4H_CLP49_MASK 2 #define ADC3CLP4H_CLP_48_MASK 3 #define ADC3CLP4H_CLP_48_BITNUM 0 /*** ADC3CLP4L - Plus-Side General Calibration Value 4 Low Register; 0xFFFF8497 ***/ union { byte Byte; struct { byte CLP40 :1; /* Plus-Side General Calibration Value 4 bit 0 */ byte CLP41 :1; /* Plus-Side General Calibration Value 4 bit 1 */ byte CLP42 :1; /* Plus-Side General Calibration Value 4 bit 2 */ byte CLP43 :1; /* Plus-Side General Calibration Value 4 bit 3 */ byte CLP44 :1; /* Plus-Side General Calibration Value 4 bit 4 */ byte CLP45 :1; /* Plus-Side General Calibration Value 4 bit 5 */ byte CLP46 :1; /* Plus-Side General Calibration Value 4 bit 6 */ byte CLP47 :1; /* Plus-Side General Calibration Value 4 bit 7 */ } Bits; } ADC3CLP4LSTR; #define ADC3CLP4L _ADC3CLP4.Overlap_STR.ADC3CLP4LSTR.Byte #define ADC3CLP4L_CLP40 _ADC3CLP4.Overlap_STR.ADC3CLP4LSTR.Bits.CLP40 #define ADC3CLP4L_CLP41 _ADC3CLP4.Overlap_STR.ADC3CLP4LSTR.Bits.CLP41 #define ADC3CLP4L_CLP42 _ADC3CLP4.Overlap_STR.ADC3CLP4LSTR.Bits.CLP42 #define ADC3CLP4L_CLP43 _ADC3CLP4.Overlap_STR.ADC3CLP4LSTR.Bits.CLP43 #define ADC3CLP4L_CLP44 _ADC3CLP4.Overlap_STR.ADC3CLP4LSTR.Bits.CLP44 #define ADC3CLP4L_CLP45 _ADC3CLP4.Overlap_STR.ADC3CLP4LSTR.Bits.CLP45 #define ADC3CLP4L_CLP46 _ADC3CLP4.Overlap_STR.ADC3CLP4LSTR.Bits.CLP46 #define ADC3CLP4L_CLP47 _ADC3CLP4.Overlap_STR.ADC3CLP4LSTR.Bits.CLP47 #define ADC3CLP4L_CLP40_MASK 1 #define ADC3CLP4L_CLP41_MASK 2 #define ADC3CLP4L_CLP42_MASK 4 #define ADC3CLP4L_CLP43_MASK 8 #define ADC3CLP4L_CLP44_MASK 16 #define ADC3CLP4L_CLP45_MASK 32 #define ADC3CLP4L_CLP46_MASK 64 #define ADC3CLP4L_CLP47_MASK 128 } Overlap_STR; struct { word CLP40 :1; /* Plus-Side General Calibration Value 4 bit 0 */ word CLP41 :1; /* Plus-Side General Calibration Value 4 bit 1 */ word CLP42 :1; /* Plus-Side General Calibration Value 4 bit 2 */ word CLP43 :1; /* Plus-Side General Calibration Value 4 bit 3 */ word CLP44 :1; /* Plus-Side General Calibration Value 4 bit 4 */ word CLP45 :1; /* Plus-Side General Calibration Value 4 bit 5 */ word CLP46 :1; /* Plus-Side General Calibration Value 4 bit 6 */ word CLP47 :1; /* Plus-Side General Calibration Value 4 bit 7 */ word CLP48 :1; /* Plus-Side General Calibration Value 4 bit 8 */ word CLP49 :1; /* Plus-Side General Calibration Value 4 bit 9 */ word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpCLP_40 :10; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } ADC3CLP4STR; extern volatile ADC3CLP4STR _ADC3CLP4 @0xFFFF8496; #define ADC3CLP4 _ADC3CLP4.Word #define ADC3CLP4_CLP40 _ADC3CLP4.Bits.CLP40 #define ADC3CLP4_CLP41 _ADC3CLP4.Bits.CLP41 #define ADC3CLP4_CLP42 _ADC3CLP4.Bits.CLP42 #define ADC3CLP4_CLP43 _ADC3CLP4.Bits.CLP43 #define ADC3CLP4_CLP44 _ADC3CLP4.Bits.CLP44 #define ADC3CLP4_CLP45 _ADC3CLP4.Bits.CLP45 #define ADC3CLP4_CLP46 _ADC3CLP4.Bits.CLP46 #define ADC3CLP4_CLP47 _ADC3CLP4.Bits.CLP47 #define ADC3CLP4_CLP48 _ADC3CLP4.Bits.CLP48 #define ADC3CLP4_CLP49 _ADC3CLP4.Bits.CLP49 #define ADC3CLP4_CLP_40 _ADC3CLP4.MergedBits.grpCLP_40 #define ADC3CLP4_CLP ADC3CLP4_CLP_40 #define ADC3CLP4_CLP40_MASK 1 #define ADC3CLP4_CLP41_MASK 2 #define ADC3CLP4_CLP42_MASK 4 #define ADC3CLP4_CLP43_MASK 8 #define ADC3CLP4_CLP44_MASK 16 #define ADC3CLP4_CLP45_MASK 32 #define ADC3CLP4_CLP46_MASK 64 #define ADC3CLP4_CLP47_MASK 128 #define ADC3CLP4_CLP48_MASK 256 #define ADC3CLP4_CLP49_MASK 512 #define ADC3CLP4_CLP_40_MASK 1023 #define ADC3CLP4_CLP_40_BITNUM 0 /*** ADC3CLP3 - Plus-Side General Calibration Value 3 Register; 0xFFFF8498 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC3CLP3H - Plus-Side General Calibration Value 3 High Register; 0xFFFF8498 ***/ union { byte Byte; struct { byte CLP38 :1; /* Plus-Side General Calibration Value 3 bits */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } ADC3CLP3HSTR; #define ADC3CLP3H _ADC3CLP3.Overlap_STR.ADC3CLP3HSTR.Byte #define ADC3CLP3H_CLP38 _ADC3CLP3.Overlap_STR.ADC3CLP3HSTR.Bits.CLP38 #define ADC3CLP3H_CLP38_MASK 1 /*** ADC3CLP3L - Plus-Side General Calibration Value 3 Low Register; 0xFFFF8499 ***/ union { byte Byte; struct { byte CLP30 :1; /* Plus-Side General Calibration Value 3 bit 0 */ byte CLP31 :1; /* Plus-Side General Calibration Value 3 bit 1 */ byte CLP32 :1; /* Plus-Side General Calibration Value 3 bit 2 */ byte CLP33 :1; /* Plus-Side General Calibration Value 3 bit 3 */ byte CLP34 :1; /* Plus-Side General Calibration Value 3 bit 4 */ byte CLP35 :1; /* Plus-Side General Calibration Value 3 bit 5 */ byte CLP36 :1; /* Plus-Side General Calibration Value 3 bit 6 */ byte CLP37 :1; /* Plus-Side General Calibration Value 3 bit 7 */ } Bits; } ADC3CLP3LSTR; #define ADC3CLP3L _ADC3CLP3.Overlap_STR.ADC3CLP3LSTR.Byte #define ADC3CLP3L_CLP30 _ADC3CLP3.Overlap_STR.ADC3CLP3LSTR.Bits.CLP30 #define ADC3CLP3L_CLP31 _ADC3CLP3.Overlap_STR.ADC3CLP3LSTR.Bits.CLP31 #define ADC3CLP3L_CLP32 _ADC3CLP3.Overlap_STR.ADC3CLP3LSTR.Bits.CLP32 #define ADC3CLP3L_CLP33 _ADC3CLP3.Overlap_STR.ADC3CLP3LSTR.Bits.CLP33 #define ADC3CLP3L_CLP34 _ADC3CLP3.Overlap_STR.ADC3CLP3LSTR.Bits.CLP34 #define ADC3CLP3L_CLP35 _ADC3CLP3.Overlap_STR.ADC3CLP3LSTR.Bits.CLP35 #define ADC3CLP3L_CLP36 _ADC3CLP3.Overlap_STR.ADC3CLP3LSTR.Bits.CLP36 #define ADC3CLP3L_CLP37 _ADC3CLP3.Overlap_STR.ADC3CLP3LSTR.Bits.CLP37 #define ADC3CLP3L_CLP30_MASK 1 #define ADC3CLP3L_CLP31_MASK 2 #define ADC3CLP3L_CLP32_MASK 4 #define ADC3CLP3L_CLP33_MASK 8 #define ADC3CLP3L_CLP34_MASK 16 #define ADC3CLP3L_CLP35_MASK 32 #define ADC3CLP3L_CLP36_MASK 64 #define ADC3CLP3L_CLP37_MASK 128 } Overlap_STR; struct { word CLP30 :1; /* Plus-Side General Calibration Value 3 bit 0 */ word CLP31 :1; /* Plus-Side General Calibration Value 3 bit 1 */ word CLP32 :1; /* Plus-Side General Calibration Value 3 bit 2 */ word CLP33 :1; /* Plus-Side General Calibration Value 3 bit 3 */ word CLP34 :1; /* Plus-Side General Calibration Value 3 bit 4 */ word CLP35 :1; /* Plus-Side General Calibration Value 3 bit 5 */ word CLP36 :1; /* Plus-Side General Calibration Value 3 bit 6 */ word CLP37 :1; /* Plus-Side General Calibration Value 3 bit 7 */ word CLP38 :1; /* Plus-Side General Calibration Value 3 bit 8 */ word :1; word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpCLP_30 :9; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } ADC3CLP3STR; extern volatile ADC3CLP3STR _ADC3CLP3 @0xFFFF8498; #define ADC3CLP3 _ADC3CLP3.Word #define ADC3CLP3_CLP30 _ADC3CLP3.Bits.CLP30 #define ADC3CLP3_CLP31 _ADC3CLP3.Bits.CLP31 #define ADC3CLP3_CLP32 _ADC3CLP3.Bits.CLP32 #define ADC3CLP3_CLP33 _ADC3CLP3.Bits.CLP33 #define ADC3CLP3_CLP34 _ADC3CLP3.Bits.CLP34 #define ADC3CLP3_CLP35 _ADC3CLP3.Bits.CLP35 #define ADC3CLP3_CLP36 _ADC3CLP3.Bits.CLP36 #define ADC3CLP3_CLP37 _ADC3CLP3.Bits.CLP37 #define ADC3CLP3_CLP38 _ADC3CLP3.Bits.CLP38 #define ADC3CLP3_CLP_30 _ADC3CLP3.MergedBits.grpCLP_30 #define ADC3CLP3_CLP ADC3CLP3_CLP_30 #define ADC3CLP3_CLP30_MASK 1 #define ADC3CLP3_CLP31_MASK 2 #define ADC3CLP3_CLP32_MASK 4 #define ADC3CLP3_CLP33_MASK 8 #define ADC3CLP3_CLP34_MASK 16 #define ADC3CLP3_CLP35_MASK 32 #define ADC3CLP3_CLP36_MASK 64 #define ADC3CLP3_CLP37_MASK 128 #define ADC3CLP3_CLP38_MASK 256 #define ADC3CLP3_CLP_30_MASK 511 #define ADC3CLP3_CLP_30_BITNUM 0 /*** ADC3CLP2 - Plus-Side General Calibration Value 2 Register; 0xFFFF849A ***/ typedef union { byte Byte; struct { byte CLP20 :1; /* Plus-Side General Calibration Value 2 bit 0 */ byte CLP21 :1; /* Plus-Side General Calibration Value 2 bit 1 */ byte CLP22 :1; /* Plus-Side General Calibration Value 2 bit 2 */ byte CLP23 :1; /* Plus-Side General Calibration Value 2 bit 3 */ byte CLP24 :1; /* Plus-Side General Calibration Value 2 bit 4 */ byte CLP25 :1; /* Plus-Side General Calibration Value 2 bit 5 */ byte CLP26 :1; /* Plus-Side General Calibration Value 2 bit 6 */ byte CLP27 :1; /* Plus-Side General Calibration Value 2 bit 7 */ } Bits; } ADC3CLP2STR; extern volatile ADC3CLP2STR _ADC3CLP2 @0xFFFF849A; #define ADC3CLP2 _ADC3CLP2.Byte #define ADC3CLP2_CLP20 _ADC3CLP2.Bits.CLP20 #define ADC3CLP2_CLP21 _ADC3CLP2.Bits.CLP21 #define ADC3CLP2_CLP22 _ADC3CLP2.Bits.CLP22 #define ADC3CLP2_CLP23 _ADC3CLP2.Bits.CLP23 #define ADC3CLP2_CLP24 _ADC3CLP2.Bits.CLP24 #define ADC3CLP2_CLP25 _ADC3CLP2.Bits.CLP25 #define ADC3CLP2_CLP26 _ADC3CLP2.Bits.CLP26 #define ADC3CLP2_CLP27 _ADC3CLP2.Bits.CLP27 #define ADC3CLP2_CLP20_MASK 1 #define ADC3CLP2_CLP21_MASK 2 #define ADC3CLP2_CLP22_MASK 4 #define ADC3CLP2_CLP23_MASK 8 #define ADC3CLP2_CLP24_MASK 16 #define ADC3CLP2_CLP25_MASK 32 #define ADC3CLP2_CLP26_MASK 64 #define ADC3CLP2_CLP27_MASK 128 /*** ADC3CLP1 - Plus-Side General Calibration Value 1 Register; 0xFFFF849B ***/ typedef union { byte Byte; struct { byte CLP10 :1; /* Plus-Side General Calibration Value 1 bit 0 */ byte CLP11 :1; /* Plus-Side General Calibration Value 1 bit 1 */ byte CLP12 :1; /* Plus-Side General Calibration Value 1 bit 2 */ byte CLP13 :1; /* Plus-Side General Calibration Value 1 bit 3 */ byte CLP14 :1; /* Plus-Side General Calibration Value 1 bit 4 */ byte CLP15 :1; /* Plus-Side General Calibration Value 1 bit 5 */ byte CLP16 :1; /* Plus-Side General Calibration Value 1 bit 6 */ byte :1; } Bits; struct { byte grpCLP_10 :7; byte :1; } MergedBits; } ADC3CLP1STR; extern volatile ADC3CLP1STR _ADC3CLP1 @0xFFFF849B; #define ADC3CLP1 _ADC3CLP1.Byte #define ADC3CLP1_CLP10 _ADC3CLP1.Bits.CLP10 #define ADC3CLP1_CLP11 _ADC3CLP1.Bits.CLP11 #define ADC3CLP1_CLP12 _ADC3CLP1.Bits.CLP12 #define ADC3CLP1_CLP13 _ADC3CLP1.Bits.CLP13 #define ADC3CLP1_CLP14 _ADC3CLP1.Bits.CLP14 #define ADC3CLP1_CLP15 _ADC3CLP1.Bits.CLP15 #define ADC3CLP1_CLP16 _ADC3CLP1.Bits.CLP16 #define ADC3CLP1_CLP_10 _ADC3CLP1.MergedBits.grpCLP_10 #define ADC3CLP1_CLP ADC3CLP1_CLP_10 #define ADC3CLP1_CLP10_MASK 1 #define ADC3CLP1_CLP11_MASK 2 #define ADC3CLP1_CLP12_MASK 4 #define ADC3CLP1_CLP13_MASK 8 #define ADC3CLP1_CLP14_MASK 16 #define ADC3CLP1_CLP15_MASK 32 #define ADC3CLP1_CLP16_MASK 64 #define ADC3CLP1_CLP_10_MASK 127 #define ADC3CLP1_CLP_10_BITNUM 0 /*** ADC3CLP0 - Plus-Side General Calibration Value 0 Register; 0xFFFF849C ***/ typedef union { byte Byte; struct { byte CLP00 :1; /* Plus-Side General Calibration Value 0 bit 0 */ byte CLP01 :1; /* Plus-Side General Calibration Value 0 bit 1 */ byte CLP02 :1; /* Plus-Side General Calibration Value 0 bit 2 */ byte CLP03 :1; /* Plus-Side General Calibration Value 0 bit 3 */ byte CLP04 :1; /* Plus-Side General Calibration Value 0 bit 4 */ byte CLP05 :1; /* Plus-Side General Calibration Value 0 bit 5 */ byte :1; byte :1; } Bits; struct { byte grpCLP0 :6; byte :1; byte :1; } MergedBits; } ADC3CLP0STR; extern volatile ADC3CLP0STR _ADC3CLP0 @0xFFFF849C; #define ADC3CLP0 _ADC3CLP0.Byte #define ADC3CLP0_CLP00 _ADC3CLP0.Bits.CLP00 #define ADC3CLP0_CLP01 _ADC3CLP0.Bits.CLP01 #define ADC3CLP0_CLP02 _ADC3CLP0.Bits.CLP02 #define ADC3CLP0_CLP03 _ADC3CLP0.Bits.CLP03 #define ADC3CLP0_CLP04 _ADC3CLP0.Bits.CLP04 #define ADC3CLP0_CLP05 _ADC3CLP0.Bits.CLP05 #define ADC3CLP0_CLP0 _ADC3CLP0.MergedBits.grpCLP0 #define ADC3CLP0_CLP00_MASK 1 #define ADC3CLP0_CLP01_MASK 2 #define ADC3CLP0_CLP02_MASK 4 #define ADC3CLP0_CLP03_MASK 8 #define ADC3CLP0_CLP04_MASK 16 #define ADC3CLP0_CLP05_MASK 32 #define ADC3CLP0_CLP0_MASK 63 #define ADC3CLP0_CLP0_BITNUM 0 /*** ADC3CLMD - Minus-Side General Calibration Value D Register; 0xFFFF849E ***/ typedef union { byte Byte; struct { byte CLMD0 :1; /* Minus-Side General Calibration Value D bit 0 */ byte CLMD1 :1; /* Minus-Side General Calibration Value D bit 1 */ byte CLMD2 :1; /* Minus-Side General Calibration Value D bit 2 */ byte CLMD3 :1; /* Minus-Side General Calibration Value D bit 3 */ byte CLMD4 :1; /* Minus-Side General Calibration Value D bit 4 */ byte CLMD5 :1; /* Minus-Side General Calibration Value D bit 5 */ byte :1; byte :1; } Bits; struct { byte grpCLMD :6; byte :1; byte :1; } MergedBits; } ADC3CLMDSTR; extern volatile ADC3CLMDSTR _ADC3CLMD @0xFFFF849E; #define ADC3CLMD _ADC3CLMD.Byte #define ADC3CLMD_CLMD0 _ADC3CLMD.Bits.CLMD0 #define ADC3CLMD_CLMD1 _ADC3CLMD.Bits.CLMD1 #define ADC3CLMD_CLMD2 _ADC3CLMD.Bits.CLMD2 #define ADC3CLMD_CLMD3 _ADC3CLMD.Bits.CLMD3 #define ADC3CLMD_CLMD4 _ADC3CLMD.Bits.CLMD4 #define ADC3CLMD_CLMD5 _ADC3CLMD.Bits.CLMD5 #define ADC3CLMD_CLMD _ADC3CLMD.MergedBits.grpCLMD #define ADC3CLMD_CLMD0_MASK 1 #define ADC3CLMD_CLMD1_MASK 2 #define ADC3CLMD_CLMD2_MASK 4 #define ADC3CLMD_CLMD3_MASK 8 #define ADC3CLMD_CLMD4_MASK 16 #define ADC3CLMD_CLMD5_MASK 32 #define ADC3CLMD_CLMD_MASK 63 #define ADC3CLMD_CLMD_BITNUM 0 /*** ADC3CLMS - Minus-Side General Calibration Value S Register; 0xFFFF849F ***/ typedef union { byte Byte; struct { byte CLMS0 :1; /* Minus-Side General Calibration Value S bit 0 */ byte CLMS1 :1; /* Minus-Side General Calibration Value S bit 1 */ byte CLMS2 :1; /* Minus-Side General Calibration Value S bit 2 */ byte CLMS3 :1; /* Minus-Side General Calibration Value S bit 3 */ byte CLMS4 :1; /* Minus-Side General Calibration Value S bit 4 */ byte CLMS5 :1; /* Minus-Side General Calibration Value S bit 5 */ byte :1; byte :1; } Bits; struct { byte grpCLMS :6; byte :1; byte :1; } MergedBits; } ADC3CLMSSTR; extern volatile ADC3CLMSSTR _ADC3CLMS @0xFFFF849F; #define ADC3CLMS _ADC3CLMS.Byte #define ADC3CLMS_CLMS0 _ADC3CLMS.Bits.CLMS0 #define ADC3CLMS_CLMS1 _ADC3CLMS.Bits.CLMS1 #define ADC3CLMS_CLMS2 _ADC3CLMS.Bits.CLMS2 #define ADC3CLMS_CLMS3 _ADC3CLMS.Bits.CLMS3 #define ADC3CLMS_CLMS4 _ADC3CLMS.Bits.CLMS4 #define ADC3CLMS_CLMS5 _ADC3CLMS.Bits.CLMS5 #define ADC3CLMS_CLMS _ADC3CLMS.MergedBits.grpCLMS #define ADC3CLMS_CLMS0_MASK 1 #define ADC3CLMS_CLMS1_MASK 2 #define ADC3CLMS_CLMS2_MASK 4 #define ADC3CLMS_CLMS3_MASK 8 #define ADC3CLMS_CLMS4_MASK 16 #define ADC3CLMS_CLMS5_MASK 32 #define ADC3CLMS_CLMS_MASK 63 #define ADC3CLMS_CLMS_BITNUM 0 /*** ADC3CLM4 - Minus-Side General Calibration Value 4 Register; 0xFFFF84A0 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC3CLM4H - Minus-Side General Calibration Value 4 High Register; 0xFFFF84A0 ***/ union { byte Byte; struct { byte CLM48 :1; /* Minus-Side General Calibration Value 4 bit 8 */ byte CLM49 :1; /* Minus-Side General Calibration Value 4 bit 9 */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpCLM_48 :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ADC3CLM4HSTR; #define ADC3CLM4H _ADC3CLM4.Overlap_STR.ADC3CLM4HSTR.Byte #define ADC3CLM4H_CLM48 _ADC3CLM4.Overlap_STR.ADC3CLM4HSTR.Bits.CLM48 #define ADC3CLM4H_CLM49 _ADC3CLM4.Overlap_STR.ADC3CLM4HSTR.Bits.CLM49 #define ADC3CLM4H_CLM_48 _ADC3CLM4.Overlap_STR.ADC3CLM4HSTR.MergedBits.grpCLM_48 #define ADC3CLM4H_CLM ADC3CLM4H_CLM_48 #define ADC3CLM4H_CLM48_MASK 1 #define ADC3CLM4H_CLM49_MASK 2 #define ADC3CLM4H_CLM_48_MASK 3 #define ADC3CLM4H_CLM_48_BITNUM 0 /*** ADC3CLM4L - Minus-Side General Calibration Value 4 Low Register; 0xFFFF84A1 ***/ union { byte Byte; struct { byte CLM40 :1; /* Minus-Side General Calibration Value 4 bit 0 */ byte CLM41 :1; /* Minus-Side General Calibration Value 4 bit 1 */ byte CLM42 :1; /* Minus-Side General Calibration Value 4 bit 2 */ byte CLM43 :1; /* Minus-Side General Calibration Value 4 bit 3 */ byte CLM44 :1; /* Minus-Side General Calibration Value 4 bit 4 */ byte CLM45 :1; /* Minus-Side General Calibration Value 4 bit 5 */ byte CLM46 :1; /* Minus-Side General Calibration Value 4 bit 6 */ byte CLM47 :1; /* Minus-Side General Calibration Value 4 bit 7 */ } Bits; } ADC3CLM4LSTR; #define ADC3CLM4L _ADC3CLM4.Overlap_STR.ADC3CLM4LSTR.Byte #define ADC3CLM4L_CLM40 _ADC3CLM4.Overlap_STR.ADC3CLM4LSTR.Bits.CLM40 #define ADC3CLM4L_CLM41 _ADC3CLM4.Overlap_STR.ADC3CLM4LSTR.Bits.CLM41 #define ADC3CLM4L_CLM42 _ADC3CLM4.Overlap_STR.ADC3CLM4LSTR.Bits.CLM42 #define ADC3CLM4L_CLM43 _ADC3CLM4.Overlap_STR.ADC3CLM4LSTR.Bits.CLM43 #define ADC3CLM4L_CLM44 _ADC3CLM4.Overlap_STR.ADC3CLM4LSTR.Bits.CLM44 #define ADC3CLM4L_CLM45 _ADC3CLM4.Overlap_STR.ADC3CLM4LSTR.Bits.CLM45 #define ADC3CLM4L_CLM46 _ADC3CLM4.Overlap_STR.ADC3CLM4LSTR.Bits.CLM46 #define ADC3CLM4L_CLM47 _ADC3CLM4.Overlap_STR.ADC3CLM4LSTR.Bits.CLM47 #define ADC3CLM4L_CLM40_MASK 1 #define ADC3CLM4L_CLM41_MASK 2 #define ADC3CLM4L_CLM42_MASK 4 #define ADC3CLM4L_CLM43_MASK 8 #define ADC3CLM4L_CLM44_MASK 16 #define ADC3CLM4L_CLM45_MASK 32 #define ADC3CLM4L_CLM46_MASK 64 #define ADC3CLM4L_CLM47_MASK 128 } Overlap_STR; struct { word CLM40 :1; /* Minus-Side General Calibration Value 4 bit 0 */ word CLM41 :1; /* Minus-Side General Calibration Value 4 bit 1 */ word CLM42 :1; /* Minus-Side General Calibration Value 4 bit 2 */ word CLM43 :1; /* Minus-Side General Calibration Value 4 bit 3 */ word CLM44 :1; /* Minus-Side General Calibration Value 4 bit 4 */ word CLM45 :1; /* Minus-Side General Calibration Value 4 bit 5 */ word CLM46 :1; /* Minus-Side General Calibration Value 4 bit 6 */ word CLM47 :1; /* Minus-Side General Calibration Value 4 bit 7 */ word CLM48 :1; /* Minus-Side General Calibration Value 4 bit 8 */ word CLM49 :1; /* Minus-Side General Calibration Value 4 bit 9 */ word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpCLM_40 :10; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } ADC3CLM4STR; extern volatile ADC3CLM4STR _ADC3CLM4 @0xFFFF84A0; #define ADC3CLM4 _ADC3CLM4.Word #define ADC3CLM4_CLM40 _ADC3CLM4.Bits.CLM40 #define ADC3CLM4_CLM41 _ADC3CLM4.Bits.CLM41 #define ADC3CLM4_CLM42 _ADC3CLM4.Bits.CLM42 #define ADC3CLM4_CLM43 _ADC3CLM4.Bits.CLM43 #define ADC3CLM4_CLM44 _ADC3CLM4.Bits.CLM44 #define ADC3CLM4_CLM45 _ADC3CLM4.Bits.CLM45 #define ADC3CLM4_CLM46 _ADC3CLM4.Bits.CLM46 #define ADC3CLM4_CLM47 _ADC3CLM4.Bits.CLM47 #define ADC3CLM4_CLM48 _ADC3CLM4.Bits.CLM48 #define ADC3CLM4_CLM49 _ADC3CLM4.Bits.CLM49 #define ADC3CLM4_CLM_40 _ADC3CLM4.MergedBits.grpCLM_40 #define ADC3CLM4_CLM ADC3CLM4_CLM_40 #define ADC3CLM4_CLM40_MASK 1 #define ADC3CLM4_CLM41_MASK 2 #define ADC3CLM4_CLM42_MASK 4 #define ADC3CLM4_CLM43_MASK 8 #define ADC3CLM4_CLM44_MASK 16 #define ADC3CLM4_CLM45_MASK 32 #define ADC3CLM4_CLM46_MASK 64 #define ADC3CLM4_CLM47_MASK 128 #define ADC3CLM4_CLM48_MASK 256 #define ADC3CLM4_CLM49_MASK 512 #define ADC3CLM4_CLM_40_MASK 1023 #define ADC3CLM4_CLM_40_BITNUM 0 /*** ADC3CLM3 - Minus-Side General Calibration Value 3 Register; 0xFFFF84A2 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC3CLM3H - Minus-Side General Calibration Value 3 High Register; 0xFFFF84A2 ***/ union { byte Byte; struct { byte CLM38 :1; /* Minus-Side General Calibration Value 3 bits */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } ADC3CLM3HSTR; #define ADC3CLM3H _ADC3CLM3.Overlap_STR.ADC3CLM3HSTR.Byte #define ADC3CLM3H_CLM38 _ADC3CLM3.Overlap_STR.ADC3CLM3HSTR.Bits.CLM38 #define ADC3CLM3H_CLM38_MASK 1 /*** ADC3CLM3L - Minus-Side General Calibration Value 3 Low Register; 0xFFFF84A3 ***/ union { byte Byte; struct { byte CLM30 :1; /* Minus-Side General Calibration Value 3 bit 0 */ byte CLM31 :1; /* Minus-Side General Calibration Value 3 bit 1 */ byte CLM32 :1; /* Minus-Side General Calibration Value 3 bit 2 */ byte CLM33 :1; /* Minus-Side General Calibration Value 3 bit 3 */ byte CLM34 :1; /* Minus-Side General Calibration Value 3 bit 4 */ byte CLM35 :1; /* Minus-Side General Calibration Value 3 bit 5 */ byte CLM36 :1; /* Minus-Side General Calibration Value 3 bit 6 */ byte CLM37 :1; /* Minus-Side General Calibration Value 3 bit 7 */ } Bits; } ADC3CLM3LSTR; #define ADC3CLM3L _ADC3CLM3.Overlap_STR.ADC3CLM3LSTR.Byte #define ADC3CLM3L_CLM30 _ADC3CLM3.Overlap_STR.ADC3CLM3LSTR.Bits.CLM30 #define ADC3CLM3L_CLM31 _ADC3CLM3.Overlap_STR.ADC3CLM3LSTR.Bits.CLM31 #define ADC3CLM3L_CLM32 _ADC3CLM3.Overlap_STR.ADC3CLM3LSTR.Bits.CLM32 #define ADC3CLM3L_CLM33 _ADC3CLM3.Overlap_STR.ADC3CLM3LSTR.Bits.CLM33 #define ADC3CLM3L_CLM34 _ADC3CLM3.Overlap_STR.ADC3CLM3LSTR.Bits.CLM34 #define ADC3CLM3L_CLM35 _ADC3CLM3.Overlap_STR.ADC3CLM3LSTR.Bits.CLM35 #define ADC3CLM3L_CLM36 _ADC3CLM3.Overlap_STR.ADC3CLM3LSTR.Bits.CLM36 #define ADC3CLM3L_CLM37 _ADC3CLM3.Overlap_STR.ADC3CLM3LSTR.Bits.CLM37 #define ADC3CLM3L_CLM30_MASK 1 #define ADC3CLM3L_CLM31_MASK 2 #define ADC3CLM3L_CLM32_MASK 4 #define ADC3CLM3L_CLM33_MASK 8 #define ADC3CLM3L_CLM34_MASK 16 #define ADC3CLM3L_CLM35_MASK 32 #define ADC3CLM3L_CLM36_MASK 64 #define ADC3CLM3L_CLM37_MASK 128 } Overlap_STR; struct { word CLM30 :1; /* Minus-Side General Calibration Value 3 bit 0 */ word CLM31 :1; /* Minus-Side General Calibration Value 3 bit 1 */ word CLM32 :1; /* Minus-Side General Calibration Value 3 bit 2 */ word CLM33 :1; /* Minus-Side General Calibration Value 3 bit 3 */ word CLM34 :1; /* Minus-Side General Calibration Value 3 bit 4 */ word CLM35 :1; /* Minus-Side General Calibration Value 3 bit 5 */ word CLM36 :1; /* Minus-Side General Calibration Value 3 bit 6 */ word CLM37 :1; /* Minus-Side General Calibration Value 3 bit 7 */ word CLM38 :1; /* Minus-Side General Calibration Value 3 bit 8 */ word :1; word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpCLM_30 :9; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } ADC3CLM3STR; extern volatile ADC3CLM3STR _ADC3CLM3 @0xFFFF84A2; #define ADC3CLM3 _ADC3CLM3.Word #define ADC3CLM3_CLM30 _ADC3CLM3.Bits.CLM30 #define ADC3CLM3_CLM31 _ADC3CLM3.Bits.CLM31 #define ADC3CLM3_CLM32 _ADC3CLM3.Bits.CLM32 #define ADC3CLM3_CLM33 _ADC3CLM3.Bits.CLM33 #define ADC3CLM3_CLM34 _ADC3CLM3.Bits.CLM34 #define ADC3CLM3_CLM35 _ADC3CLM3.Bits.CLM35 #define ADC3CLM3_CLM36 _ADC3CLM3.Bits.CLM36 #define ADC3CLM3_CLM37 _ADC3CLM3.Bits.CLM37 #define ADC3CLM3_CLM38 _ADC3CLM3.Bits.CLM38 #define ADC3CLM3_CLM_30 _ADC3CLM3.MergedBits.grpCLM_30 #define ADC3CLM3_CLM ADC3CLM3_CLM_30 #define ADC3CLM3_CLM30_MASK 1 #define ADC3CLM3_CLM31_MASK 2 #define ADC3CLM3_CLM32_MASK 4 #define ADC3CLM3_CLM33_MASK 8 #define ADC3CLM3_CLM34_MASK 16 #define ADC3CLM3_CLM35_MASK 32 #define ADC3CLM3_CLM36_MASK 64 #define ADC3CLM3_CLM37_MASK 128 #define ADC3CLM3_CLM38_MASK 256 #define ADC3CLM3_CLM_30_MASK 511 #define ADC3CLM3_CLM_30_BITNUM 0 /*** ADC3CLM2 - Minus-Side General Calibration Value 2 Register; 0xFFFF84A4 ***/ typedef union { byte Byte; struct { byte CLM20 :1; /* Minus-Side General Calibration Value 2 bit 0 */ byte CLM21 :1; /* Minus-Side General Calibration Value 2 bit 1 */ byte CLM22 :1; /* Minus-Side General Calibration Value 2 bit 2 */ byte CLM23 :1; /* Minus-Side General Calibration Value 2 bit 3 */ byte CLM24 :1; /* Minus-Side General Calibration Value 2 bit 4 */ byte CLM25 :1; /* Minus-Side General Calibration Value 2 bit 5 */ byte CLM26 :1; /* Minus-Side General Calibration Value 2 bit 6 */ byte CLM27 :1; /* Minus-Side General Calibration Value 2 bit 7 */ } Bits; } ADC3CLM2STR; extern volatile ADC3CLM2STR _ADC3CLM2 @0xFFFF84A4; #define ADC3CLM2 _ADC3CLM2.Byte #define ADC3CLM2_CLM20 _ADC3CLM2.Bits.CLM20 #define ADC3CLM2_CLM21 _ADC3CLM2.Bits.CLM21 #define ADC3CLM2_CLM22 _ADC3CLM2.Bits.CLM22 #define ADC3CLM2_CLM23 _ADC3CLM2.Bits.CLM23 #define ADC3CLM2_CLM24 _ADC3CLM2.Bits.CLM24 #define ADC3CLM2_CLM25 _ADC3CLM2.Bits.CLM25 #define ADC3CLM2_CLM26 _ADC3CLM2.Bits.CLM26 #define ADC3CLM2_CLM27 _ADC3CLM2.Bits.CLM27 #define ADC3CLM2_CLM20_MASK 1 #define ADC3CLM2_CLM21_MASK 2 #define ADC3CLM2_CLM22_MASK 4 #define ADC3CLM2_CLM23_MASK 8 #define ADC3CLM2_CLM24_MASK 16 #define ADC3CLM2_CLM25_MASK 32 #define ADC3CLM2_CLM26_MASK 64 #define ADC3CLM2_CLM27_MASK 128 /*** ADC3CLM1 - Minus-Side General Calibration Value 1 Register; 0xFFFF84A5 ***/ typedef union { byte Byte; struct { byte CLM10 :1; /* Minus-Side General Calibration Value 1 bit 0 */ byte CLM11 :1; /* Minus-Side General Calibration Value 1 bit 1 */ byte CLM12 :1; /* Minus-Side General Calibration Value 1 bit 2 */ byte CLM13 :1; /* Minus-Side General Calibration Value 1 bit 3 */ byte CLM14 :1; /* Minus-Side General Calibration Value 1 bit 4 */ byte CLM15 :1; /* Minus-Side General Calibration Value 1 bit 5 */ byte CLM16 :1; /* Minus-Side General Calibration Value 1 bit 6 */ byte :1; } Bits; struct { byte grpCLM_10 :7; byte :1; } MergedBits; } ADC3CLM1STR; extern volatile ADC3CLM1STR _ADC3CLM1 @0xFFFF84A5; #define ADC3CLM1 _ADC3CLM1.Byte #define ADC3CLM1_CLM10 _ADC3CLM1.Bits.CLM10 #define ADC3CLM1_CLM11 _ADC3CLM1.Bits.CLM11 #define ADC3CLM1_CLM12 _ADC3CLM1.Bits.CLM12 #define ADC3CLM1_CLM13 _ADC3CLM1.Bits.CLM13 #define ADC3CLM1_CLM14 _ADC3CLM1.Bits.CLM14 #define ADC3CLM1_CLM15 _ADC3CLM1.Bits.CLM15 #define ADC3CLM1_CLM16 _ADC3CLM1.Bits.CLM16 #define ADC3CLM1_CLM_10 _ADC3CLM1.MergedBits.grpCLM_10 #define ADC3CLM1_CLM ADC3CLM1_CLM_10 #define ADC3CLM1_CLM10_MASK 1 #define ADC3CLM1_CLM11_MASK 2 #define ADC3CLM1_CLM12_MASK 4 #define ADC3CLM1_CLM13_MASK 8 #define ADC3CLM1_CLM14_MASK 16 #define ADC3CLM1_CLM15_MASK 32 #define ADC3CLM1_CLM16_MASK 64 #define ADC3CLM1_CLM_10_MASK 127 #define ADC3CLM1_CLM_10_BITNUM 0 /*** ADC3CLM0 - Minus-Side General Calibration Value 0 Register; 0xFFFF84A6 ***/ typedef union { byte Byte; struct { byte CLM00 :1; /* Minus-Side General Calibration Value 0 bit 0 */ byte CLM01 :1; /* Minus-Side General Calibration Value 0 bit 1 */ byte CLM02 :1; /* Minus-Side General Calibration Value 0 bit 2 */ byte CLM03 :1; /* Minus-Side General Calibration Value 0 bit 3 */ byte CLM04 :1; /* Minus-Side General Calibration Value 0 bit 4 */ byte CLM05 :1; /* Minus-Side General Calibration Value 0 bit 5 */ byte :1; byte :1; } Bits; struct { byte grpCLM0 :6; byte :1; byte :1; } MergedBits; } ADC3CLM0STR; extern volatile ADC3CLM0STR _ADC3CLM0 @0xFFFF84A6; #define ADC3CLM0 _ADC3CLM0.Byte #define ADC3CLM0_CLM00 _ADC3CLM0.Bits.CLM00 #define ADC3CLM0_CLM01 _ADC3CLM0.Bits.CLM01 #define ADC3CLM0_CLM02 _ADC3CLM0.Bits.CLM02 #define ADC3CLM0_CLM03 _ADC3CLM0.Bits.CLM03 #define ADC3CLM0_CLM04 _ADC3CLM0.Bits.CLM04 #define ADC3CLM0_CLM05 _ADC3CLM0.Bits.CLM05 #define ADC3CLM0_CLM0 _ADC3CLM0.MergedBits.grpCLM0 #define ADC3CLM0_CLM00_MASK 1 #define ADC3CLM0_CLM01_MASK 2 #define ADC3CLM0_CLM02_MASK 4 #define ADC3CLM0_CLM03_MASK 8 #define ADC3CLM0_CLM04_MASK 16 #define ADC3CLM0_CLM05_MASK 32 #define ADC3CLM0_CLM0_MASK 63 #define ADC3CLM0_CLM0_BITNUM 0 /*** ADC4SC1A - Status and Control Register 1A; 0xFFFF84C0 ***/ typedef union { byte Byte; struct { byte ADCHA0 :1; /* Input Channel Select Bit 0 */ byte ADCHA1 :1; /* Input Channel Select Bit 1 */ byte ADCHA2 :1; /* Input Channel Select Bit 2 */ byte ADCHA3 :1; /* Input Channel Select Bit 3 */ byte ADCHA4 :1; /* Input Channel Select Bit 4 */ byte DIFFA :1; /* Differential Mode Enable - DIFFA configures the ADC to operate in differential mode */ byte AIENA :1; /* Interrupt Enable - AIENA enables conversion complete interrupts. When COCOA becomes set while the respective AIENA is high, an interrupt is asserted */ byte COCOA :1; /* Conversion Complete Flag */ } Bits; struct { byte grpADCHA :5; byte grpDIFFx :1; byte grpAIENx :1; byte grpCOCOx :1; } MergedBits; } ADC4SC1ASTR; extern volatile ADC4SC1ASTR _ADC4SC1A @0xFFFF84C0; #define ADC4SC1A _ADC4SC1A.Byte #define ADC4SC1A_ADCHA0 _ADC4SC1A.Bits.ADCHA0 #define ADC4SC1A_ADCHA1 _ADC4SC1A.Bits.ADCHA1 #define ADC4SC1A_ADCHA2 _ADC4SC1A.Bits.ADCHA2 #define ADC4SC1A_ADCHA3 _ADC4SC1A.Bits.ADCHA3 #define ADC4SC1A_ADCHA4 _ADC4SC1A.Bits.ADCHA4 #define ADC4SC1A_DIFFA _ADC4SC1A.Bits.DIFFA #define ADC4SC1A_AIENA _ADC4SC1A.Bits.AIENA #define ADC4SC1A_COCOA _ADC4SC1A.Bits.COCOA #define ADC4SC1A_ADCHA _ADC4SC1A.MergedBits.grpADCHA #define ADC4SC1A_ADCHA0_MASK 1 #define ADC4SC1A_ADCHA1_MASK 2 #define ADC4SC1A_ADCHA2_MASK 4 #define ADC4SC1A_ADCHA3_MASK 8 #define ADC4SC1A_ADCHA4_MASK 16 #define ADC4SC1A_DIFFA_MASK 32 #define ADC4SC1A_AIENA_MASK 64 #define ADC4SC1A_COCOA_MASK 128 #define ADC4SC1A_ADCHA_MASK 31 #define ADC4SC1A_ADCHA_BITNUM 0 /*** ADC4SC1B - Status and Control Register 1B; 0xFFFF84C1 ***/ typedef union { byte Byte; struct { byte ADCHB0 :1; /* Input Channel Select Bit 0 */ byte ADCHB1 :1; /* Input Channel Select Bit 1 */ byte ADCHB2 :1; /* Input Channel Select Bit 2 */ byte ADCHB3 :1; /* Input Channel Select Bit 3 */ byte ADCHB4 :1; /* Input Channel Select Bit 4 */ byte DIFFB :1; /* Differential Mode Enable - DIFFB configures the ADC to operate in differential mode */ byte AIENB :1; /* Interrupt Enable - AIENB enables conversion complete interrupts. When COCOB becomes set while the respective AIENB is high, an interrupt is asserted */ byte COCOB :1; /* Conversion Complete Flag */ } Bits; struct { byte grpADCHB :5; byte :1; byte :1; byte :1; } MergedBits; } ADC4SC1BSTR; extern volatile ADC4SC1BSTR _ADC4SC1B @0xFFFF84C1; #define ADC4SC1B _ADC4SC1B.Byte #define ADC4SC1B_ADCHB0 _ADC4SC1B.Bits.ADCHB0 #define ADC4SC1B_ADCHB1 _ADC4SC1B.Bits.ADCHB1 #define ADC4SC1B_ADCHB2 _ADC4SC1B.Bits.ADCHB2 #define ADC4SC1B_ADCHB3 _ADC4SC1B.Bits.ADCHB3 #define ADC4SC1B_ADCHB4 _ADC4SC1B.Bits.ADCHB4 #define ADC4SC1B_DIFFB _ADC4SC1B.Bits.DIFFB #define ADC4SC1B_AIENB _ADC4SC1B.Bits.AIENB #define ADC4SC1B_COCOB _ADC4SC1B.Bits.COCOB #define ADC4SC1B_ADCHB _ADC4SC1B.MergedBits.grpADCHB #define ADC4SC1B_ADCHB0_MASK 1 #define ADC4SC1B_ADCHB1_MASK 2 #define ADC4SC1B_ADCHB2_MASK 4 #define ADC4SC1B_ADCHB3_MASK 8 #define ADC4SC1B_ADCHB4_MASK 16 #define ADC4SC1B_DIFFB_MASK 32 #define ADC4SC1B_AIENB_MASK 64 #define ADC4SC1B_COCOB_MASK 128 #define ADC4SC1B_ADCHB_MASK 31 #define ADC4SC1B_ADCHB_BITNUM 0 /*** ADC4CFG1 - Configuration Register 1; 0xFFFF84C2 ***/ typedef union { byte Byte; struct { byte ADICLK0 :1; /* Input Clock Select Bit 0 */ byte ADICLK1 :1; /* Input Clock Select Bit 1 */ byte MODE0 :1; /* Conversion Mode Selection Bit 0 */ byte MODE1 :1; /* Conversion Mode Selection Bit 1 */ byte ADLSMP :1; /* Long Sample Time Configuration */ byte ADIV0 :1; /* Clock Divide Select Bit 0 */ byte ADIV1 :1; /* Clock Divide Select Bit 1 */ byte ADLPC :1; /* Low Power Configuration */ } Bits; struct { byte grpADICLK :2; byte grpMODE :2; byte :1; byte grpADIV :2; byte :1; } MergedBits; } ADC4CFG1STR; extern volatile ADC4CFG1STR _ADC4CFG1 @0xFFFF84C2; #define ADC4CFG1 _ADC4CFG1.Byte #define ADC4CFG1_ADICLK0 _ADC4CFG1.Bits.ADICLK0 #define ADC4CFG1_ADICLK1 _ADC4CFG1.Bits.ADICLK1 #define ADC4CFG1_MODE0 _ADC4CFG1.Bits.MODE0 #define ADC4CFG1_MODE1 _ADC4CFG1.Bits.MODE1 #define ADC4CFG1_ADLSMP _ADC4CFG1.Bits.ADLSMP #define ADC4CFG1_ADIV0 _ADC4CFG1.Bits.ADIV0 #define ADC4CFG1_ADIV1 _ADC4CFG1.Bits.ADIV1 #define ADC4CFG1_ADLPC _ADC4CFG1.Bits.ADLPC #define ADC4CFG1_ADICLK _ADC4CFG1.MergedBits.grpADICLK #define ADC4CFG1_MODE _ADC4CFG1.MergedBits.grpMODE #define ADC4CFG1_ADIV _ADC4CFG1.MergedBits.grpADIV #define ADC4CFG1_ADICLK0_MASK 1 #define ADC4CFG1_ADICLK1_MASK 2 #define ADC4CFG1_MODE0_MASK 4 #define ADC4CFG1_MODE1_MASK 8 #define ADC4CFG1_ADLSMP_MASK 16 #define ADC4CFG1_ADIV0_MASK 32 #define ADC4CFG1_ADIV1_MASK 64 #define ADC4CFG1_ADLPC_MASK 128 #define ADC4CFG1_ADICLK_MASK 3 #define ADC4CFG1_ADICLK_BITNUM 0 #define ADC4CFG1_MODE_MASK 12 #define ADC4CFG1_MODE_BITNUM 2 #define ADC4CFG1_ADIV_MASK 96 #define ADC4CFG1_ADIV_BITNUM 5 /*** ADC4CFG2 - Configuration Register 2; 0xFFFF84C3 ***/ typedef union { byte Byte; struct { byte ADLSTS0 :1; /* Long Sample Time Select Bit 0 */ byte ADLSTS1 :1; /* Long Sample Time Select Bit 1 */ byte ADHSC :1; /* High Speed Configuration */ byte ADACKEN :1; /* Asynchronous Clock Output Enable */ byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpADLSTS :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ADC4CFG2STR; extern volatile ADC4CFG2STR _ADC4CFG2 @0xFFFF84C3; #define ADC4CFG2 _ADC4CFG2.Byte #define ADC4CFG2_ADLSTS0 _ADC4CFG2.Bits.ADLSTS0 #define ADC4CFG2_ADLSTS1 _ADC4CFG2.Bits.ADLSTS1 #define ADC4CFG2_ADHSC _ADC4CFG2.Bits.ADHSC #define ADC4CFG2_ADACKEN _ADC4CFG2.Bits.ADACKEN #define ADC4CFG2_ADLSTS _ADC4CFG2.MergedBits.grpADLSTS #define ADC4CFG2_ADLSTS0_MASK 1 #define ADC4CFG2_ADLSTS1_MASK 2 #define ADC4CFG2_ADHSC_MASK 4 #define ADC4CFG2_ADACKEN_MASK 8 #define ADC4CFG2_ADLSTS_MASK 3 #define ADC4CFG2_ADLSTS_BITNUM 0 /*** ADC4RA - Data Result Register A; 0xFFFF84C4 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC4RHA - Data Result High Register A; 0xFFFF84C4 ***/ union { byte Byte; struct { byte D8 :1; /* ADC Result Data Bit 8 */ byte D9 :1; /* ADC Result Data Bit 9 */ byte D10 :1; /* ADC Result Data Bit 10 */ byte D11 :1; /* ADC Result Data Bit 11 */ byte D12 :1; /* ADC Result Data Bit 12 */ byte D13 :1; /* ADC Result Data Bit 13 */ byte D14 :1; /* ADC Result Data Bit 14 */ byte D15 :1; /* ADC Result Data Bit 15 */ } Bits; } ADC4RHASTR; #define ADC4RHA _ADC4RA.Overlap_STR.ADC4RHASTR.Byte #define ADC4RHA_D8 _ADC4RA.Overlap_STR.ADC4RHASTR.Bits.D8 #define ADC4RHA_D9 _ADC4RA.Overlap_STR.ADC4RHASTR.Bits.D9 #define ADC4RHA_D10 _ADC4RA.Overlap_STR.ADC4RHASTR.Bits.D10 #define ADC4RHA_D11 _ADC4RA.Overlap_STR.ADC4RHASTR.Bits.D11 #define ADC4RHA_D12 _ADC4RA.Overlap_STR.ADC4RHASTR.Bits.D12 #define ADC4RHA_D13 _ADC4RA.Overlap_STR.ADC4RHASTR.Bits.D13 #define ADC4RHA_D14 _ADC4RA.Overlap_STR.ADC4RHASTR.Bits.D14 #define ADC4RHA_D15 _ADC4RA.Overlap_STR.ADC4RHASTR.Bits.D15 #define ADC4RHA_D8_MASK 1 #define ADC4RHA_D9_MASK 2 #define ADC4RHA_D10_MASK 4 #define ADC4RHA_D11_MASK 8 #define ADC4RHA_D12_MASK 16 #define ADC4RHA_D13_MASK 32 #define ADC4RHA_D14_MASK 64 #define ADC4RHA_D15_MASK 128 /*** ADC4RLA - Data Result Low Register A; 0xFFFF84C5 ***/ union { byte Byte; struct { byte D0 :1; /* ADC Result Data Bit 0 */ byte D1 :1; /* ADC Result Data Bit 1 */ byte D2 :1; /* ADC Result Data Bit 2 */ byte D3 :1; /* ADC Result Data Bit 3 */ byte D4 :1; /* ADC Result Data Bit 4 */ byte D5 :1; /* ADC Result Data Bit 5 */ byte D6 :1; /* ADC Result Data Bit 6 */ byte D7 :1; /* ADC Result Data Bit 7 */ } Bits; } ADC4RLASTR; #define ADC4RLA _ADC4RA.Overlap_STR.ADC4RLASTR.Byte #define ADC4RLA_D0 _ADC4RA.Overlap_STR.ADC4RLASTR.Bits.D0 #define ADC4RLA_D1 _ADC4RA.Overlap_STR.ADC4RLASTR.Bits.D1 #define ADC4RLA_D2 _ADC4RA.Overlap_STR.ADC4RLASTR.Bits.D2 #define ADC4RLA_D3 _ADC4RA.Overlap_STR.ADC4RLASTR.Bits.D3 #define ADC4RLA_D4 _ADC4RA.Overlap_STR.ADC4RLASTR.Bits.D4 #define ADC4RLA_D5 _ADC4RA.Overlap_STR.ADC4RLASTR.Bits.D5 #define ADC4RLA_D6 _ADC4RA.Overlap_STR.ADC4RLASTR.Bits.D6 #define ADC4RLA_D7 _ADC4RA.Overlap_STR.ADC4RLASTR.Bits.D7 #define ADC4RLA_D0_MASK 1 #define ADC4RLA_D1_MASK 2 #define ADC4RLA_D2_MASK 4 #define ADC4RLA_D3_MASK 8 #define ADC4RLA_D4_MASK 16 #define ADC4RLA_D5_MASK 32 #define ADC4RLA_D6_MASK 64 #define ADC4RLA_D7_MASK 128 } Overlap_STR; struct { word D0 :1; /* ADC Result Data Bit 0 */ word D1 :1; /* ADC Result Data Bit 1 */ word D2 :1; /* ADC Result Data Bit 2 */ word D3 :1; /* ADC Result Data Bit 3 */ word D4 :1; /* ADC Result Data Bit 4 */ word D5 :1; /* ADC Result Data Bit 5 */ word D6 :1; /* ADC Result Data Bit 6 */ word D7 :1; /* ADC Result Data Bit 7 */ word D8 :1; /* ADC Result Data Bit 8 */ word D9 :1; /* ADC Result Data Bit 9 */ word D10 :1; /* ADC Result Data Bit 10 */ word D11 :1; /* ADC Result Data Bit 11 */ word D12 :1; /* ADC Result Data Bit 12 */ word D13 :1; /* ADC Result Data Bit 13 */ word D14 :1; /* ADC Result Data Bit 14 */ word D15 :1; /* ADC Result Data Bit 15 */ } Bits; } ADC4RASTR; extern volatile ADC4RASTR _ADC4RA @0xFFFF84C4; #define ADC4RA _ADC4RA.Word #define ADC4RA_D0 _ADC4RA.Bits.D0 #define ADC4RA_D1 _ADC4RA.Bits.D1 #define ADC4RA_D2 _ADC4RA.Bits.D2 #define ADC4RA_D3 _ADC4RA.Bits.D3 #define ADC4RA_D4 _ADC4RA.Bits.D4 #define ADC4RA_D5 _ADC4RA.Bits.D5 #define ADC4RA_D6 _ADC4RA.Bits.D6 #define ADC4RA_D7 _ADC4RA.Bits.D7 #define ADC4RA_D8 _ADC4RA.Bits.D8 #define ADC4RA_D9 _ADC4RA.Bits.D9 #define ADC4RA_D10 _ADC4RA.Bits.D10 #define ADC4RA_D11 _ADC4RA.Bits.D11 #define ADC4RA_D12 _ADC4RA.Bits.D12 #define ADC4RA_D13 _ADC4RA.Bits.D13 #define ADC4RA_D14 _ADC4RA.Bits.D14 #define ADC4RA_D15 _ADC4RA.Bits.D15 #define ADC4RA_D0_MASK 1 #define ADC4RA_D1_MASK 2 #define ADC4RA_D2_MASK 4 #define ADC4RA_D3_MASK 8 #define ADC4RA_D4_MASK 16 #define ADC4RA_D5_MASK 32 #define ADC4RA_D6_MASK 64 #define ADC4RA_D7_MASK 128 #define ADC4RA_D8_MASK 256 #define ADC4RA_D9_MASK 512 #define ADC4RA_D10_MASK 1024 #define ADC4RA_D11_MASK 2048 #define ADC4RA_D12_MASK 4096 #define ADC4RA_D13_MASK 8192 #define ADC4RA_D14_MASK 16384 #define ADC4RA_D15_MASK 32768 /*** ADC4RB - Data Result Register B; 0xFFFF84C6 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC4RHB - Data Result High Register B; 0xFFFF84C6 ***/ union { byte Byte; struct { byte D8 :1; /* ADC Result Data Bit 8 */ byte D9 :1; /* ADC Result Data Bit 9 */ byte D10 :1; /* ADC Result Data Bit 10 */ byte D11 :1; /* ADC Result Data Bit 11 */ byte D12 :1; /* ADC Result Data Bit 12 */ byte D13 :1; /* ADC Result Data Bit 13 */ byte D14 :1; /* ADC Result Data Bit 14 */ byte D15 :1; /* ADC Result Data Bit 15 */ } Bits; } ADC4RHBSTR; #define ADC4RHB _ADC4RB.Overlap_STR.ADC4RHBSTR.Byte #define ADC4RHB_D8 _ADC4RB.Overlap_STR.ADC4RHBSTR.Bits.D8 #define ADC4RHB_D9 _ADC4RB.Overlap_STR.ADC4RHBSTR.Bits.D9 #define ADC4RHB_D10 _ADC4RB.Overlap_STR.ADC4RHBSTR.Bits.D10 #define ADC4RHB_D11 _ADC4RB.Overlap_STR.ADC4RHBSTR.Bits.D11 #define ADC4RHB_D12 _ADC4RB.Overlap_STR.ADC4RHBSTR.Bits.D12 #define ADC4RHB_D13 _ADC4RB.Overlap_STR.ADC4RHBSTR.Bits.D13 #define ADC4RHB_D14 _ADC4RB.Overlap_STR.ADC4RHBSTR.Bits.D14 #define ADC4RHB_D15 _ADC4RB.Overlap_STR.ADC4RHBSTR.Bits.D15 #define ADC4RHB_D8_MASK 1 #define ADC4RHB_D9_MASK 2 #define ADC4RHB_D10_MASK 4 #define ADC4RHB_D11_MASK 8 #define ADC4RHB_D12_MASK 16 #define ADC4RHB_D13_MASK 32 #define ADC4RHB_D14_MASK 64 #define ADC4RHB_D15_MASK 128 /*** ADC4RLB - Data Result Low Register B; 0xFFFF84C7 ***/ union { byte Byte; struct { byte D0 :1; /* ADC Result Data Bit 0 */ byte D1 :1; /* ADC Result Data Bit 1 */ byte D2 :1; /* ADC Result Data Bit 2 */ byte D3 :1; /* ADC Result Data Bit 3 */ byte D4 :1; /* ADC Result Data Bit 4 */ byte D5 :1; /* ADC Result Data Bit 5 */ byte D6 :1; /* ADC Result Data Bit 6 */ byte D7 :1; /* ADC Result Data Bit 7 */ } Bits; } ADC4RLBSTR; #define ADC4RLB _ADC4RB.Overlap_STR.ADC4RLBSTR.Byte #define ADC4RLB_D0 _ADC4RB.Overlap_STR.ADC4RLBSTR.Bits.D0 #define ADC4RLB_D1 _ADC4RB.Overlap_STR.ADC4RLBSTR.Bits.D1 #define ADC4RLB_D2 _ADC4RB.Overlap_STR.ADC4RLBSTR.Bits.D2 #define ADC4RLB_D3 _ADC4RB.Overlap_STR.ADC4RLBSTR.Bits.D3 #define ADC4RLB_D4 _ADC4RB.Overlap_STR.ADC4RLBSTR.Bits.D4 #define ADC4RLB_D5 _ADC4RB.Overlap_STR.ADC4RLBSTR.Bits.D5 #define ADC4RLB_D6 _ADC4RB.Overlap_STR.ADC4RLBSTR.Bits.D6 #define ADC4RLB_D7 _ADC4RB.Overlap_STR.ADC4RLBSTR.Bits.D7 #define ADC4RLB_D0_MASK 1 #define ADC4RLB_D1_MASK 2 #define ADC4RLB_D2_MASK 4 #define ADC4RLB_D3_MASK 8 #define ADC4RLB_D4_MASK 16 #define ADC4RLB_D5_MASK 32 #define ADC4RLB_D6_MASK 64 #define ADC4RLB_D7_MASK 128 } Overlap_STR; struct { word D0 :1; /* ADC Result Data Bit 0 */ word D1 :1; /* ADC Result Data Bit 1 */ word D2 :1; /* ADC Result Data Bit 2 */ word D3 :1; /* ADC Result Data Bit 3 */ word D4 :1; /* ADC Result Data Bit 4 */ word D5 :1; /* ADC Result Data Bit 5 */ word D6 :1; /* ADC Result Data Bit 6 */ word D7 :1; /* ADC Result Data Bit 7 */ word D8 :1; /* ADC Result Data Bit 8 */ word D9 :1; /* ADC Result Data Bit 9 */ word D10 :1; /* ADC Result Data Bit 10 */ word D11 :1; /* ADC Result Data Bit 11 */ word D12 :1; /* ADC Result Data Bit 12 */ word D13 :1; /* ADC Result Data Bit 13 */ word D14 :1; /* ADC Result Data Bit 14 */ word D15 :1; /* ADC Result Data Bit 15 */ } Bits; } ADC4RBSTR; extern volatile ADC4RBSTR _ADC4RB @0xFFFF84C6; #define ADC4RB _ADC4RB.Word #define ADC4RB_D0 _ADC4RB.Bits.D0 #define ADC4RB_D1 _ADC4RB.Bits.D1 #define ADC4RB_D2 _ADC4RB.Bits.D2 #define ADC4RB_D3 _ADC4RB.Bits.D3 #define ADC4RB_D4 _ADC4RB.Bits.D4 #define ADC4RB_D5 _ADC4RB.Bits.D5 #define ADC4RB_D6 _ADC4RB.Bits.D6 #define ADC4RB_D7 _ADC4RB.Bits.D7 #define ADC4RB_D8 _ADC4RB.Bits.D8 #define ADC4RB_D9 _ADC4RB.Bits.D9 #define ADC4RB_D10 _ADC4RB.Bits.D10 #define ADC4RB_D11 _ADC4RB.Bits.D11 #define ADC4RB_D12 _ADC4RB.Bits.D12 #define ADC4RB_D13 _ADC4RB.Bits.D13 #define ADC4RB_D14 _ADC4RB.Bits.D14 #define ADC4RB_D15 _ADC4RB.Bits.D15 #define ADC4RB_D0_MASK 1 #define ADC4RB_D1_MASK 2 #define ADC4RB_D2_MASK 4 #define ADC4RB_D3_MASK 8 #define ADC4RB_D4_MASK 16 #define ADC4RB_D5_MASK 32 #define ADC4RB_D6_MASK 64 #define ADC4RB_D7_MASK 128 #define ADC4RB_D8_MASK 256 #define ADC4RB_D9_MASK 512 #define ADC4RB_D10_MASK 1024 #define ADC4RB_D11_MASK 2048 #define ADC4RB_D12_MASK 4096 #define ADC4RB_D13_MASK 8192 #define ADC4RB_D14_MASK 16384 #define ADC4RB_D15_MASK 32768 /*** ADC4CV1 - Compare Value 1 Register; 0xFFFF84C8 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC4CV1H - Compare Value 1 High Register; 0xFFFF84C8 ***/ union { byte Byte; struct { byte CV18 :1; /* Compare Function Value 8 */ byte CV19 :1; /* Compare Function Value 9 */ byte CV110 :1; /* Compare Function Value 10 */ byte CV111 :1; /* Compare Function Value 11 */ byte CV112 :1; /* Compare Function Value 12 */ byte CV113 :1; /* Compare Function Value 13 */ byte CV114 :1; /* Compare Function Value 14 */ byte CV115 :1; /* Compare Function Value 15 */ } Bits; struct { byte grpCV_18 :2; byte grpCV1_10 :6; } MergedBits; } ADC4CV1HSTR; #define ADC4CV1H _ADC4CV1.Overlap_STR.ADC4CV1HSTR.Byte #define ADC4CV1H_CV18 _ADC4CV1.Overlap_STR.ADC4CV1HSTR.Bits.CV18 #define ADC4CV1H_CV19 _ADC4CV1.Overlap_STR.ADC4CV1HSTR.Bits.CV19 #define ADC4CV1H_CV110 _ADC4CV1.Overlap_STR.ADC4CV1HSTR.Bits.CV110 #define ADC4CV1H_CV111 _ADC4CV1.Overlap_STR.ADC4CV1HSTR.Bits.CV111 #define ADC4CV1H_CV112 _ADC4CV1.Overlap_STR.ADC4CV1HSTR.Bits.CV112 #define ADC4CV1H_CV113 _ADC4CV1.Overlap_STR.ADC4CV1HSTR.Bits.CV113 #define ADC4CV1H_CV114 _ADC4CV1.Overlap_STR.ADC4CV1HSTR.Bits.CV114 #define ADC4CV1H_CV115 _ADC4CV1.Overlap_STR.ADC4CV1HSTR.Bits.CV115 #define ADC4CV1H_CV_18 _ADC4CV1.Overlap_STR.ADC4CV1HSTR.MergedBits.grpCV_18 #define ADC4CV1H_CV1_10 _ADC4CV1.Overlap_STR.ADC4CV1HSTR.MergedBits.grpCV1_10 #define ADC4CV1H_CV ADC4CV1H_CV_18 #define ADC4CV1H_CV1 ADC4CV1H_CV1_10 #define ADC4CV1H_CV18_MASK 1 #define ADC4CV1H_CV19_MASK 2 #define ADC4CV1H_CV110_MASK 4 #define ADC4CV1H_CV111_MASK 8 #define ADC4CV1H_CV112_MASK 16 #define ADC4CV1H_CV113_MASK 32 #define ADC4CV1H_CV114_MASK 64 #define ADC4CV1H_CV115_MASK 128 #define ADC4CV1H_CV_18_MASK 3 #define ADC4CV1H_CV_18_BITNUM 0 #define ADC4CV1H_CV1_10_MASK 252 #define ADC4CV1H_CV1_10_BITNUM 2 /*** ADC4CV1L - Compare Value 1 Low Register; 0xFFFF84C9 ***/ union { byte Byte; struct { byte CV10 :1; /* Compare Function Value 0 */ byte CV11 :1; /* Compare Function Value 1 */ byte CV12 :1; /* Compare Function Value 2 */ byte CV13 :1; /* Compare Function Value 3 */ byte CV14 :1; /* Compare Function Value 4 */ byte CV15 :1; /* Compare Function Value 5 */ byte CV16 :1; /* Compare Function Value 6 */ byte CV17 :1; /* Compare Function Value 7 */ } Bits; } ADC4CV1LSTR; #define ADC4CV1L _ADC4CV1.Overlap_STR.ADC4CV1LSTR.Byte #define ADC4CV1L_CV10 _ADC4CV1.Overlap_STR.ADC4CV1LSTR.Bits.CV10 #define ADC4CV1L_CV11 _ADC4CV1.Overlap_STR.ADC4CV1LSTR.Bits.CV11 #define ADC4CV1L_CV12 _ADC4CV1.Overlap_STR.ADC4CV1LSTR.Bits.CV12 #define ADC4CV1L_CV13 _ADC4CV1.Overlap_STR.ADC4CV1LSTR.Bits.CV13 #define ADC4CV1L_CV14 _ADC4CV1.Overlap_STR.ADC4CV1LSTR.Bits.CV14 #define ADC4CV1L_CV15 _ADC4CV1.Overlap_STR.ADC4CV1LSTR.Bits.CV15 #define ADC4CV1L_CV16 _ADC4CV1.Overlap_STR.ADC4CV1LSTR.Bits.CV16 #define ADC4CV1L_CV17 _ADC4CV1.Overlap_STR.ADC4CV1LSTR.Bits.CV17 #define ADC4CV1L_CV10_MASK 1 #define ADC4CV1L_CV11_MASK 2 #define ADC4CV1L_CV12_MASK 4 #define ADC4CV1L_CV13_MASK 8 #define ADC4CV1L_CV14_MASK 16 #define ADC4CV1L_CV15_MASK 32 #define ADC4CV1L_CV16_MASK 64 #define ADC4CV1L_CV17_MASK 128 } Overlap_STR; struct { word CV10 :1; /* Compare Function Value 0 */ word CV11 :1; /* Compare Function Value 1 */ word CV12 :1; /* Compare Function Value 2 */ word CV13 :1; /* Compare Function Value 3 */ word CV14 :1; /* Compare Function Value 4 */ word CV15 :1; /* Compare Function Value 5 */ word CV16 :1; /* Compare Function Value 6 */ word CV17 :1; /* Compare Function Value 7 */ word CV18 :1; /* Compare Function Value 8 */ word CV19 :1; /* Compare Function Value 9 */ word CV110 :1; /* Compare Function Value 10 */ word CV111 :1; /* Compare Function Value 11 */ word CV112 :1; /* Compare Function Value 12 */ word CV113 :1; /* Compare Function Value 13 */ word CV114 :1; /* Compare Function Value 14 */ word CV115 :1; /* Compare Function Value 15 */ } Bits; struct { word grpCV_10 :10; word grpCV1_10 :6; } MergedBits; } ADC4CV1STR; extern volatile ADC4CV1STR _ADC4CV1 @0xFFFF84C8; #define ADC4CV1 _ADC4CV1.Word #define ADC4CV1_CV10 _ADC4CV1.Bits.CV10 #define ADC4CV1_CV11 _ADC4CV1.Bits.CV11 #define ADC4CV1_CV12 _ADC4CV1.Bits.CV12 #define ADC4CV1_CV13 _ADC4CV1.Bits.CV13 #define ADC4CV1_CV14 _ADC4CV1.Bits.CV14 #define ADC4CV1_CV15 _ADC4CV1.Bits.CV15 #define ADC4CV1_CV16 _ADC4CV1.Bits.CV16 #define ADC4CV1_CV17 _ADC4CV1.Bits.CV17 #define ADC4CV1_CV18 _ADC4CV1.Bits.CV18 #define ADC4CV1_CV19 _ADC4CV1.Bits.CV19 #define ADC4CV1_CV110 _ADC4CV1.Bits.CV110 #define ADC4CV1_CV111 _ADC4CV1.Bits.CV111 #define ADC4CV1_CV112 _ADC4CV1.Bits.CV112 #define ADC4CV1_CV113 _ADC4CV1.Bits.CV113 #define ADC4CV1_CV114 _ADC4CV1.Bits.CV114 #define ADC4CV1_CV115 _ADC4CV1.Bits.CV115 #define ADC4CV1_CV_10 _ADC4CV1.MergedBits.grpCV_10 #define ADC4CV1_CV1_10 _ADC4CV1.MergedBits.grpCV1_10 #define ADC4CV1_CV ADC4CV1_CV_10 #define ADC4CV1_CV1 ADC4CV1_CV1_10 #define ADC4CV1_CV10_MASK 1 #define ADC4CV1_CV11_MASK 2 #define ADC4CV1_CV12_MASK 4 #define ADC4CV1_CV13_MASK 8 #define ADC4CV1_CV14_MASK 16 #define ADC4CV1_CV15_MASK 32 #define ADC4CV1_CV16_MASK 64 #define ADC4CV1_CV17_MASK 128 #define ADC4CV1_CV18_MASK 256 #define ADC4CV1_CV19_MASK 512 #define ADC4CV1_CV110_MASK 1024 #define ADC4CV1_CV111_MASK 2048 #define ADC4CV1_CV112_MASK 4096 #define ADC4CV1_CV113_MASK 8192 #define ADC4CV1_CV114_MASK 16384 #define ADC4CV1_CV115_MASK 32768 #define ADC4CV1_CV_10_MASK 1023 #define ADC4CV1_CV_10_BITNUM 0 #define ADC4CV1_CV1_10_MASK 64512 #define ADC4CV1_CV1_10_BITNUM 10 /*** ADC4CV2 - Compare Value 2 Register; 0xFFFF84CA ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC4CV2H - Compare Value 2 High Register; 0xFFFF84CA ***/ union { byte Byte; struct { byte CV28 :1; /* Compare Function Value 8 */ byte CV29 :1; /* Compare Function Value 9 */ byte CV210 :1; /* Compare Function Value 10 */ byte CV211 :1; /* Compare Function Value 11 */ byte CV212 :1; /* Compare Function Value 12 */ byte CV213 :1; /* Compare Function Value 13 */ byte CV214 :1; /* Compare Function Value 14 */ byte CV215 :1; /* Compare Function Value 15 */ } Bits; struct { byte grpCV_28 :2; byte grpCV2_10 :6; } MergedBits; } ADC4CV2HSTR; #define ADC4CV2H _ADC4CV2.Overlap_STR.ADC4CV2HSTR.Byte #define ADC4CV2H_CV28 _ADC4CV2.Overlap_STR.ADC4CV2HSTR.Bits.CV28 #define ADC4CV2H_CV29 _ADC4CV2.Overlap_STR.ADC4CV2HSTR.Bits.CV29 #define ADC4CV2H_CV210 _ADC4CV2.Overlap_STR.ADC4CV2HSTR.Bits.CV210 #define ADC4CV2H_CV211 _ADC4CV2.Overlap_STR.ADC4CV2HSTR.Bits.CV211 #define ADC4CV2H_CV212 _ADC4CV2.Overlap_STR.ADC4CV2HSTR.Bits.CV212 #define ADC4CV2H_CV213 _ADC4CV2.Overlap_STR.ADC4CV2HSTR.Bits.CV213 #define ADC4CV2H_CV214 _ADC4CV2.Overlap_STR.ADC4CV2HSTR.Bits.CV214 #define ADC4CV2H_CV215 _ADC4CV2.Overlap_STR.ADC4CV2HSTR.Bits.CV215 #define ADC4CV2H_CV_28 _ADC4CV2.Overlap_STR.ADC4CV2HSTR.MergedBits.grpCV_28 #define ADC4CV2H_CV2_10 _ADC4CV2.Overlap_STR.ADC4CV2HSTR.MergedBits.grpCV2_10 #define ADC4CV2H_CV ADC4CV2H_CV_28 #define ADC4CV2H_CV2 ADC4CV2H_CV2_10 #define ADC4CV2H_CV28_MASK 1 #define ADC4CV2H_CV29_MASK 2 #define ADC4CV2H_CV210_MASK 4 #define ADC4CV2H_CV211_MASK 8 #define ADC4CV2H_CV212_MASK 16 #define ADC4CV2H_CV213_MASK 32 #define ADC4CV2H_CV214_MASK 64 #define ADC4CV2H_CV215_MASK 128 #define ADC4CV2H_CV_28_MASK 3 #define ADC4CV2H_CV_28_BITNUM 0 #define ADC4CV2H_CV2_10_MASK 252 #define ADC4CV2H_CV2_10_BITNUM 2 /*** ADC4CV2L - Compare Value 2 Low Register; 0xFFFF84CB ***/ union { byte Byte; struct { byte CV20 :1; /* Compare Function Value 0 */ byte CV21 :1; /* Compare Function Value 1 */ byte CV22 :1; /* Compare Function Value 2 */ byte CV23 :1; /* Compare Function Value 3 */ byte CV24 :1; /* Compare Function Value 4 */ byte CV25 :1; /* Compare Function Value 5 */ byte CV26 :1; /* Compare Function Value 6 */ byte CV27 :1; /* Compare Function Value 7 */ } Bits; } ADC4CV2LSTR; #define ADC4CV2L _ADC4CV2.Overlap_STR.ADC4CV2LSTR.Byte #define ADC4CV2L_CV20 _ADC4CV2.Overlap_STR.ADC4CV2LSTR.Bits.CV20 #define ADC4CV2L_CV21 _ADC4CV2.Overlap_STR.ADC4CV2LSTR.Bits.CV21 #define ADC4CV2L_CV22 _ADC4CV2.Overlap_STR.ADC4CV2LSTR.Bits.CV22 #define ADC4CV2L_CV23 _ADC4CV2.Overlap_STR.ADC4CV2LSTR.Bits.CV23 #define ADC4CV2L_CV24 _ADC4CV2.Overlap_STR.ADC4CV2LSTR.Bits.CV24 #define ADC4CV2L_CV25 _ADC4CV2.Overlap_STR.ADC4CV2LSTR.Bits.CV25 #define ADC4CV2L_CV26 _ADC4CV2.Overlap_STR.ADC4CV2LSTR.Bits.CV26 #define ADC4CV2L_CV27 _ADC4CV2.Overlap_STR.ADC4CV2LSTR.Bits.CV27 #define ADC4CV2L_CV20_MASK 1 #define ADC4CV2L_CV21_MASK 2 #define ADC4CV2L_CV22_MASK 4 #define ADC4CV2L_CV23_MASK 8 #define ADC4CV2L_CV24_MASK 16 #define ADC4CV2L_CV25_MASK 32 #define ADC4CV2L_CV26_MASK 64 #define ADC4CV2L_CV27_MASK 128 } Overlap_STR; struct { word CV20 :1; /* Compare Function Value 0 */ word CV21 :1; /* Compare Function Value 1 */ word CV22 :1; /* Compare Function Value 2 */ word CV23 :1; /* Compare Function Value 3 */ word CV24 :1; /* Compare Function Value 4 */ word CV25 :1; /* Compare Function Value 5 */ word CV26 :1; /* Compare Function Value 6 */ word CV27 :1; /* Compare Function Value 7 */ word CV28 :1; /* Compare Function Value 8 */ word CV29 :1; /* Compare Function Value 9 */ word CV210 :1; /* Compare Function Value 10 */ word CV211 :1; /* Compare Function Value 11 */ word CV212 :1; /* Compare Function Value 12 */ word CV213 :1; /* Compare Function Value 13 */ word CV214 :1; /* Compare Function Value 14 */ word CV215 :1; /* Compare Function Value 15 */ } Bits; struct { word grpCV_20 :10; word grpCV2_10 :6; } MergedBits; } ADC4CV2STR; extern volatile ADC4CV2STR _ADC4CV2 @0xFFFF84CA; #define ADC4CV2 _ADC4CV2.Word #define ADC4CV2_CV20 _ADC4CV2.Bits.CV20 #define ADC4CV2_CV21 _ADC4CV2.Bits.CV21 #define ADC4CV2_CV22 _ADC4CV2.Bits.CV22 #define ADC4CV2_CV23 _ADC4CV2.Bits.CV23 #define ADC4CV2_CV24 _ADC4CV2.Bits.CV24 #define ADC4CV2_CV25 _ADC4CV2.Bits.CV25 #define ADC4CV2_CV26 _ADC4CV2.Bits.CV26 #define ADC4CV2_CV27 _ADC4CV2.Bits.CV27 #define ADC4CV2_CV28 _ADC4CV2.Bits.CV28 #define ADC4CV2_CV29 _ADC4CV2.Bits.CV29 #define ADC4CV2_CV210 _ADC4CV2.Bits.CV210 #define ADC4CV2_CV211 _ADC4CV2.Bits.CV211 #define ADC4CV2_CV212 _ADC4CV2.Bits.CV212 #define ADC4CV2_CV213 _ADC4CV2.Bits.CV213 #define ADC4CV2_CV214 _ADC4CV2.Bits.CV214 #define ADC4CV2_CV215 _ADC4CV2.Bits.CV215 #define ADC4CV2_CV_20 _ADC4CV2.MergedBits.grpCV_20 #define ADC4CV2_CV2_10 _ADC4CV2.MergedBits.grpCV2_10 #define ADC4CV2_CV ADC4CV2_CV_20 #define ADC4CV2_CV2 ADC4CV2_CV2_10 #define ADC4CV2_CV20_MASK 1 #define ADC4CV2_CV21_MASK 2 #define ADC4CV2_CV22_MASK 4 #define ADC4CV2_CV23_MASK 8 #define ADC4CV2_CV24_MASK 16 #define ADC4CV2_CV25_MASK 32 #define ADC4CV2_CV26_MASK 64 #define ADC4CV2_CV27_MASK 128 #define ADC4CV2_CV28_MASK 256 #define ADC4CV2_CV29_MASK 512 #define ADC4CV2_CV210_MASK 1024 #define ADC4CV2_CV211_MASK 2048 #define ADC4CV2_CV212_MASK 4096 #define ADC4CV2_CV213_MASK 8192 #define ADC4CV2_CV214_MASK 16384 #define ADC4CV2_CV215_MASK 32768 #define ADC4CV2_CV_20_MASK 1023 #define ADC4CV2_CV_20_BITNUM 0 #define ADC4CV2_CV2_10_MASK 64512 #define ADC4CV2_CV2_10_BITNUM 10 /*** ADC4SC2 - Status and Control Register 2; 0xFFFF84CC ***/ typedef union { byte Byte; struct { byte REFSEL0 :1; /* Voltage Reference Selection, bit 0 */ byte REFSEL1 :1; /* Voltage Reference Selection, bit 1 */ byte :1; byte ACREN :1; /* Compare Function Range Enable */ byte ACFGT :1; /* Compare Function Greater Than Enable */ byte ACFE :1; /* Compare Function Enable - ACFE is used to enable the compare function */ byte ADTRG :1; /* Conversion Trigger Select-ADTRG is used to select the type of trigger to be used for initiating a conversion */ byte ADACT :1; /* Conversion Active - ADACT indicates that a conversion is in progress. ADACT is set when a conversion is initiated and cleared when a conversion is completed or aborted */ } Bits; struct { byte grpREFSEL :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ADC4SC2STR; extern volatile ADC4SC2STR _ADC4SC2 @0xFFFF84CC; #define ADC4SC2 _ADC4SC2.Byte #define ADC4SC2_REFSEL0 _ADC4SC2.Bits.REFSEL0 #define ADC4SC2_REFSEL1 _ADC4SC2.Bits.REFSEL1 #define ADC4SC2_ACREN _ADC4SC2.Bits.ACREN #define ADC4SC2_ACFGT _ADC4SC2.Bits.ACFGT #define ADC4SC2_ACFE _ADC4SC2.Bits.ACFE #define ADC4SC2_ADTRG _ADC4SC2.Bits.ADTRG #define ADC4SC2_ADACT _ADC4SC2.Bits.ADACT #define ADC4SC2_REFSEL _ADC4SC2.MergedBits.grpREFSEL #define ADC4SC2_REFSEL0_MASK 1 #define ADC4SC2_REFSEL1_MASK 2 #define ADC4SC2_ACREN_MASK 8 #define ADC4SC2_ACFGT_MASK 16 #define ADC4SC2_ACFE_MASK 32 #define ADC4SC2_ADTRG_MASK 64 #define ADC4SC2_ADACT_MASK 128 #define ADC4SC2_REFSEL_MASK 3 #define ADC4SC2_REFSEL_BITNUM 0 /*** ADC4SC3 - Status and Control Register 3; 0xFFFF84CD ***/ typedef union { byte Byte; struct { byte AVGS0 :1; /* Hardware Average select, bit 0 */ byte AVGS1 :1; /* Hardware Average select, bit 1 */ byte AVGE :1; /* Hardware average enable - AVGE enables the hardware average function of the ADC */ byte ADCO :1; /* Continuous Conversion Enable - ADCO enables continuous conversions */ byte :1; byte :1; byte CALF :1; /* Calibration Failed Flag - CALF displays the result of the calibration sequence */ byte CAL :1; /* Calibration - CAL begins the calibration sequence when set */ } Bits; struct { byte grpAVGS :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ADC4SC3STR; extern volatile ADC4SC3STR _ADC4SC3 @0xFFFF84CD; #define ADC4SC3 _ADC4SC3.Byte #define ADC4SC3_AVGS0 _ADC4SC3.Bits.AVGS0 #define ADC4SC3_AVGS1 _ADC4SC3.Bits.AVGS1 #define ADC4SC3_AVGE _ADC4SC3.Bits.AVGE #define ADC4SC3_ADCO _ADC4SC3.Bits.ADCO #define ADC4SC3_CALF _ADC4SC3.Bits.CALF #define ADC4SC3_CAL _ADC4SC3.Bits.CAL #define ADC4SC3_AVGS _ADC4SC3.MergedBits.grpAVGS #define ADC4SC3_AVGS0_MASK 1 #define ADC4SC3_AVGS1_MASK 2 #define ADC4SC3_AVGE_MASK 4 #define ADC4SC3_ADCO_MASK 8 #define ADC4SC3_CALF_MASK 64 #define ADC4SC3_CAL_MASK 128 #define ADC4SC3_AVGS_MASK 3 #define ADC4SC3_AVGS_BITNUM 0 /*** ADC4OFS - Offset Correction Register; 0xFFFF84CE ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC4OFSH - Offset Correction High Register; 0xFFFF84CE ***/ union { byte Byte; struct { byte OFS8 :1; /* Offset error correction value bit 8 */ byte OFS9 :1; /* Offset error correction value bit 9 */ byte OFS10 :1; /* Offset error correction value bit 10 */ byte OFS11 :1; /* Offset error correction value bit 11 */ byte OFS12 :1; /* Offset error correction value bit 12 */ byte OFS13 :1; /* Offset error correction value bit 13 */ byte OFS14 :1; /* Offset error correction value bit 14 */ byte OFS15 :1; /* Offset error correction value bit 15 */ } Bits; } ADC4OFSHSTR; #define ADC4OFSH _ADC4OFS.Overlap_STR.ADC4OFSHSTR.Byte #define ADC4OFSH_OFS8 _ADC4OFS.Overlap_STR.ADC4OFSHSTR.Bits.OFS8 #define ADC4OFSH_OFS9 _ADC4OFS.Overlap_STR.ADC4OFSHSTR.Bits.OFS9 #define ADC4OFSH_OFS10 _ADC4OFS.Overlap_STR.ADC4OFSHSTR.Bits.OFS10 #define ADC4OFSH_OFS11 _ADC4OFS.Overlap_STR.ADC4OFSHSTR.Bits.OFS11 #define ADC4OFSH_OFS12 _ADC4OFS.Overlap_STR.ADC4OFSHSTR.Bits.OFS12 #define ADC4OFSH_OFS13 _ADC4OFS.Overlap_STR.ADC4OFSHSTR.Bits.OFS13 #define ADC4OFSH_OFS14 _ADC4OFS.Overlap_STR.ADC4OFSHSTR.Bits.OFS14 #define ADC4OFSH_OFS15 _ADC4OFS.Overlap_STR.ADC4OFSHSTR.Bits.OFS15 #define ADC4OFSH_OFS8_MASK 1 #define ADC4OFSH_OFS9_MASK 2 #define ADC4OFSH_OFS10_MASK 4 #define ADC4OFSH_OFS11_MASK 8 #define ADC4OFSH_OFS12_MASK 16 #define ADC4OFSH_OFS13_MASK 32 #define ADC4OFSH_OFS14_MASK 64 #define ADC4OFSH_OFS15_MASK 128 /*** ADC4OFSL - Offset Correction Low Register; 0xFFFF84CF ***/ union { byte Byte; struct { byte OFS0 :1; /* Offset error correction value bit 0 */ byte OFS1 :1; /* Offset error correction value bit 1 */ byte OFS2 :1; /* Offset error correction value bit 2 */ byte OFS3 :1; /* Offset error correction value bit 3 */ byte OFS4 :1; /* Offset error correction value bit 4 */ byte OFS5 :1; /* Offset error correction value bit 5 */ byte OFS6 :1; /* Offset error correction value bit 6 */ byte OFS7 :1; /* Offset error correction value bit 7 */ } Bits; } ADC4OFSLSTR; #define ADC4OFSL _ADC4OFS.Overlap_STR.ADC4OFSLSTR.Byte #define ADC4OFSL_OFS0 _ADC4OFS.Overlap_STR.ADC4OFSLSTR.Bits.OFS0 #define ADC4OFSL_OFS1 _ADC4OFS.Overlap_STR.ADC4OFSLSTR.Bits.OFS1 #define ADC4OFSL_OFS2 _ADC4OFS.Overlap_STR.ADC4OFSLSTR.Bits.OFS2 #define ADC4OFSL_OFS3 _ADC4OFS.Overlap_STR.ADC4OFSLSTR.Bits.OFS3 #define ADC4OFSL_OFS4 _ADC4OFS.Overlap_STR.ADC4OFSLSTR.Bits.OFS4 #define ADC4OFSL_OFS5 _ADC4OFS.Overlap_STR.ADC4OFSLSTR.Bits.OFS5 #define ADC4OFSL_OFS6 _ADC4OFS.Overlap_STR.ADC4OFSLSTR.Bits.OFS6 #define ADC4OFSL_OFS7 _ADC4OFS.Overlap_STR.ADC4OFSLSTR.Bits.OFS7 #define ADC4OFSL_OFS0_MASK 1 #define ADC4OFSL_OFS1_MASK 2 #define ADC4OFSL_OFS2_MASK 4 #define ADC4OFSL_OFS3_MASK 8 #define ADC4OFSL_OFS4_MASK 16 #define ADC4OFSL_OFS5_MASK 32 #define ADC4OFSL_OFS6_MASK 64 #define ADC4OFSL_OFS7_MASK 128 } Overlap_STR; struct { word OFS0 :1; /* Offset error correction value bit 0 */ word OFS1 :1; /* Offset error correction value bit 1 */ word OFS2 :1; /* Offset error correction value bit 2 */ word OFS3 :1; /* Offset error correction value bit 3 */ word OFS4 :1; /* Offset error correction value bit 4 */ word OFS5 :1; /* Offset error correction value bit 5 */ word OFS6 :1; /* Offset error correction value bit 6 */ word OFS7 :1; /* Offset error correction value bit 7 */ word OFS8 :1; /* Offset error correction value bit 8 */ word OFS9 :1; /* Offset error correction value bit 9 */ word OFS10 :1; /* Offset error correction value bit 10 */ word OFS11 :1; /* Offset error correction value bit 11 */ word OFS12 :1; /* Offset error correction value bit 12 */ word OFS13 :1; /* Offset error correction value bit 13 */ word OFS14 :1; /* Offset error correction value bit 14 */ word OFS15 :1; /* Offset error correction value bit 15 */ } Bits; } ADC4OFSSTR; extern volatile ADC4OFSSTR _ADC4OFS @0xFFFF84CE; #define ADC4OFS _ADC4OFS.Word #define ADC4OFS_OFS0 _ADC4OFS.Bits.OFS0 #define ADC4OFS_OFS1 _ADC4OFS.Bits.OFS1 #define ADC4OFS_OFS2 _ADC4OFS.Bits.OFS2 #define ADC4OFS_OFS3 _ADC4OFS.Bits.OFS3 #define ADC4OFS_OFS4 _ADC4OFS.Bits.OFS4 #define ADC4OFS_OFS5 _ADC4OFS.Bits.OFS5 #define ADC4OFS_OFS6 _ADC4OFS.Bits.OFS6 #define ADC4OFS_OFS7 _ADC4OFS.Bits.OFS7 #define ADC4OFS_OFS8 _ADC4OFS.Bits.OFS8 #define ADC4OFS_OFS9 _ADC4OFS.Bits.OFS9 #define ADC4OFS_OFS10 _ADC4OFS.Bits.OFS10 #define ADC4OFS_OFS11 _ADC4OFS.Bits.OFS11 #define ADC4OFS_OFS12 _ADC4OFS.Bits.OFS12 #define ADC4OFS_OFS13 _ADC4OFS.Bits.OFS13 #define ADC4OFS_OFS14 _ADC4OFS.Bits.OFS14 #define ADC4OFS_OFS15 _ADC4OFS.Bits.OFS15 #define ADC4OFS_OFS0_MASK 1 #define ADC4OFS_OFS1_MASK 2 #define ADC4OFS_OFS2_MASK 4 #define ADC4OFS_OFS3_MASK 8 #define ADC4OFS_OFS4_MASK 16 #define ADC4OFS_OFS5_MASK 32 #define ADC4OFS_OFS6_MASK 64 #define ADC4OFS_OFS7_MASK 128 #define ADC4OFS_OFS8_MASK 256 #define ADC4OFS_OFS9_MASK 512 #define ADC4OFS_OFS10_MASK 1024 #define ADC4OFS_OFS11_MASK 2048 #define ADC4OFS_OFS12_MASK 4096 #define ADC4OFS_OFS13_MASK 8192 #define ADC4OFS_OFS14_MASK 16384 #define ADC4OFS_OFS15_MASK 32768 /*** ADC4PG - Plus-Side Gain Register; 0xFFFF84D0 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC4PGH - Plus-Side Gain High Register; 0xFFFF84D0 ***/ union { byte Byte; struct { byte PG8 :1; /* Gain error correction for the plus-side input value bit 8 */ byte PG9 :1; /* Gain error correction for the plus-side input value bit 9 */ byte PG10 :1; /* Gain error correction for the plus-side input value bit 10 */ byte PG11 :1; /* Gain error correction for the plus-side input value bit 11 */ byte PG12 :1; /* Gain error correction for the plus-side input value bit 12 */ byte PG13 :1; /* Gain error correction for the plus-side input value bit 13 */ byte PG14 :1; /* Gain error correction for the plus-side input value bit 14 */ byte PG15 :1; /* Gain error correction for the plus-side input value bit 15 */ } Bits; } ADC4PGHSTR; #define ADC4PGH _ADC4PG.Overlap_STR.ADC4PGHSTR.Byte #define ADC4PGH_PG8 _ADC4PG.Overlap_STR.ADC4PGHSTR.Bits.PG8 #define ADC4PGH_PG9 _ADC4PG.Overlap_STR.ADC4PGHSTR.Bits.PG9 #define ADC4PGH_PG10 _ADC4PG.Overlap_STR.ADC4PGHSTR.Bits.PG10 #define ADC4PGH_PG11 _ADC4PG.Overlap_STR.ADC4PGHSTR.Bits.PG11 #define ADC4PGH_PG12 _ADC4PG.Overlap_STR.ADC4PGHSTR.Bits.PG12 #define ADC4PGH_PG13 _ADC4PG.Overlap_STR.ADC4PGHSTR.Bits.PG13 #define ADC4PGH_PG14 _ADC4PG.Overlap_STR.ADC4PGHSTR.Bits.PG14 #define ADC4PGH_PG15 _ADC4PG.Overlap_STR.ADC4PGHSTR.Bits.PG15 #define ADC4PGH_PG8_MASK 1 #define ADC4PGH_PG9_MASK 2 #define ADC4PGH_PG10_MASK 4 #define ADC4PGH_PG11_MASK 8 #define ADC4PGH_PG12_MASK 16 #define ADC4PGH_PG13_MASK 32 #define ADC4PGH_PG14_MASK 64 #define ADC4PGH_PG15_MASK 128 /*** ADC4PGL - Plus-Side Gain Low Register; 0xFFFF84D1 ***/ union { byte Byte; struct { byte PG0 :1; /* Gain error correction for the plus-side input value bit 0 */ byte PG1 :1; /* Gain error correction for the plus-side input value bit 1 */ byte PG2 :1; /* Gain error correction for the plus-side input value bit 2 */ byte PG3 :1; /* Gain error correction for the plus-side input value bit 3 */ byte PG4 :1; /* Gain error correction for the plus-side input value bit 4 */ byte PG5 :1; /* Gain error correction for the plus-side input value bit 5 */ byte PG6 :1; /* Gain error correction for the plus-side input value bit 6 */ byte PG7 :1; /* Gain error correction for the plus-side input value bit 7 */ } Bits; } ADC4PGLSTR; #define ADC4PGL _ADC4PG.Overlap_STR.ADC4PGLSTR.Byte #define ADC4PGL_PG0 _ADC4PG.Overlap_STR.ADC4PGLSTR.Bits.PG0 #define ADC4PGL_PG1 _ADC4PG.Overlap_STR.ADC4PGLSTR.Bits.PG1 #define ADC4PGL_PG2 _ADC4PG.Overlap_STR.ADC4PGLSTR.Bits.PG2 #define ADC4PGL_PG3 _ADC4PG.Overlap_STR.ADC4PGLSTR.Bits.PG3 #define ADC4PGL_PG4 _ADC4PG.Overlap_STR.ADC4PGLSTR.Bits.PG4 #define ADC4PGL_PG5 _ADC4PG.Overlap_STR.ADC4PGLSTR.Bits.PG5 #define ADC4PGL_PG6 _ADC4PG.Overlap_STR.ADC4PGLSTR.Bits.PG6 #define ADC4PGL_PG7 _ADC4PG.Overlap_STR.ADC4PGLSTR.Bits.PG7 #define ADC4PGL_PG0_MASK 1 #define ADC4PGL_PG1_MASK 2 #define ADC4PGL_PG2_MASK 4 #define ADC4PGL_PG3_MASK 8 #define ADC4PGL_PG4_MASK 16 #define ADC4PGL_PG5_MASK 32 #define ADC4PGL_PG6_MASK 64 #define ADC4PGL_PG7_MASK 128 } Overlap_STR; struct { word PG0 :1; /* Gain error correction for the plus-side input value bit 0 */ word PG1 :1; /* Gain error correction for the plus-side input value bit 1 */ word PG2 :1; /* Gain error correction for the plus-side input value bit 2 */ word PG3 :1; /* Gain error correction for the plus-side input value bit 3 */ word PG4 :1; /* Gain error correction for the plus-side input value bit 4 */ word PG5 :1; /* Gain error correction for the plus-side input value bit 5 */ word PG6 :1; /* Gain error correction for the plus-side input value bit 6 */ word PG7 :1; /* Gain error correction for the plus-side input value bit 7 */ word PG8 :1; /* Gain error correction for the plus-side input value bit 8 */ word PG9 :1; /* Gain error correction for the plus-side input value bit 9 */ word PG10 :1; /* Gain error correction for the plus-side input value bit 10 */ word PG11 :1; /* Gain error correction for the plus-side input value bit 11 */ word PG12 :1; /* Gain error correction for the plus-side input value bit 12 */ word PG13 :1; /* Gain error correction for the plus-side input value bit 13 */ word PG14 :1; /* Gain error correction for the plus-side input value bit 14 */ word PG15 :1; /* Gain error correction for the plus-side input value bit 15 */ } Bits; } ADC4PGSTR; extern volatile ADC4PGSTR _ADC4PG @0xFFFF84D0; #define ADC4PG _ADC4PG.Word #define ADC4PG_PG0 _ADC4PG.Bits.PG0 #define ADC4PG_PG1 _ADC4PG.Bits.PG1 #define ADC4PG_PG2 _ADC4PG.Bits.PG2 #define ADC4PG_PG3 _ADC4PG.Bits.PG3 #define ADC4PG_PG4 _ADC4PG.Bits.PG4 #define ADC4PG_PG5 _ADC4PG.Bits.PG5 #define ADC4PG_PG6 _ADC4PG.Bits.PG6 #define ADC4PG_PG7 _ADC4PG.Bits.PG7 #define ADC4PG_PG8 _ADC4PG.Bits.PG8 #define ADC4PG_PG9 _ADC4PG.Bits.PG9 #define ADC4PG_PG10 _ADC4PG.Bits.PG10 #define ADC4PG_PG11 _ADC4PG.Bits.PG11 #define ADC4PG_PG12 _ADC4PG.Bits.PG12 #define ADC4PG_PG13 _ADC4PG.Bits.PG13 #define ADC4PG_PG14 _ADC4PG.Bits.PG14 #define ADC4PG_PG15 _ADC4PG.Bits.PG15 #define ADC4PG_PG0_MASK 1 #define ADC4PG_PG1_MASK 2 #define ADC4PG_PG2_MASK 4 #define ADC4PG_PG3_MASK 8 #define ADC4PG_PG4_MASK 16 #define ADC4PG_PG5_MASK 32 #define ADC4PG_PG6_MASK 64 #define ADC4PG_PG7_MASK 128 #define ADC4PG_PG8_MASK 256 #define ADC4PG_PG9_MASK 512 #define ADC4PG_PG10_MASK 1024 #define ADC4PG_PG11_MASK 2048 #define ADC4PG_PG12_MASK 4096 #define ADC4PG_PG13_MASK 8192 #define ADC4PG_PG14_MASK 16384 #define ADC4PG_PG15_MASK 32768 /*** ADC4MG - Minus-Side Gain Register; 0xFFFF84D2 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC4MGH - Minus-Side Gain High Register; 0xFFFF84D2 ***/ union { byte Byte; struct { byte MG8 :1; /* Gain error correction for the minus-side input value bit 8 */ byte MG9 :1; /* Gain error correction for the minus-side input value bit 9 */ byte MG10 :1; /* Gain error correction for the minus-side input value bit 10 */ byte MG11 :1; /* Gain error correction for the minus-side input value bit 11 */ byte MG12 :1; /* Gain error correction for the minus-side input value bit 12 */ byte MG13 :1; /* Gain error correction for the minus-side input value bit 13 */ byte MG14 :1; /* Gain error correction for the minus-side input value bit 14 */ byte MG15 :1; /* Gain error correction for the minus-side input value bit 15 */ } Bits; } ADC4MGHSTR; #define ADC4MGH _ADC4MG.Overlap_STR.ADC4MGHSTR.Byte #define ADC4MGH_MG8 _ADC4MG.Overlap_STR.ADC4MGHSTR.Bits.MG8 #define ADC4MGH_MG9 _ADC4MG.Overlap_STR.ADC4MGHSTR.Bits.MG9 #define ADC4MGH_MG10 _ADC4MG.Overlap_STR.ADC4MGHSTR.Bits.MG10 #define ADC4MGH_MG11 _ADC4MG.Overlap_STR.ADC4MGHSTR.Bits.MG11 #define ADC4MGH_MG12 _ADC4MG.Overlap_STR.ADC4MGHSTR.Bits.MG12 #define ADC4MGH_MG13 _ADC4MG.Overlap_STR.ADC4MGHSTR.Bits.MG13 #define ADC4MGH_MG14 _ADC4MG.Overlap_STR.ADC4MGHSTR.Bits.MG14 #define ADC4MGH_MG15 _ADC4MG.Overlap_STR.ADC4MGHSTR.Bits.MG15 #define ADC4MGH_MG8_MASK 1 #define ADC4MGH_MG9_MASK 2 #define ADC4MGH_MG10_MASK 4 #define ADC4MGH_MG11_MASK 8 #define ADC4MGH_MG12_MASK 16 #define ADC4MGH_MG13_MASK 32 #define ADC4MGH_MG14_MASK 64 #define ADC4MGH_MG15_MASK 128 /*** ADC4MGL - Minus-Side Gain Low Register; 0xFFFF84D3 ***/ union { byte Byte; struct { byte MG0 :1; /* Gain error correction for the minus-side input value bit 0 */ byte MG1 :1; /* Gain error correction for the minus-side input value bit 1 */ byte MG2 :1; /* Gain error correction for the minus-side input value bit 2 */ byte MG3 :1; /* Gain error correction for the minus-side input value bit 3 */ byte MG4 :1; /* Gain error correction for the minus-side input value bit 4 */ byte MG5 :1; /* Gain error correction for the minus-side input value bit 5 */ byte MG6 :1; /* Gain error correction for the minus-side input value bit 6 */ byte MG7 :1; /* Gain error correction for the minus-side input value bit 7 */ } Bits; } ADC4MGLSTR; #define ADC4MGL _ADC4MG.Overlap_STR.ADC4MGLSTR.Byte #define ADC4MGL_MG0 _ADC4MG.Overlap_STR.ADC4MGLSTR.Bits.MG0 #define ADC4MGL_MG1 _ADC4MG.Overlap_STR.ADC4MGLSTR.Bits.MG1 #define ADC4MGL_MG2 _ADC4MG.Overlap_STR.ADC4MGLSTR.Bits.MG2 #define ADC4MGL_MG3 _ADC4MG.Overlap_STR.ADC4MGLSTR.Bits.MG3 #define ADC4MGL_MG4 _ADC4MG.Overlap_STR.ADC4MGLSTR.Bits.MG4 #define ADC4MGL_MG5 _ADC4MG.Overlap_STR.ADC4MGLSTR.Bits.MG5 #define ADC4MGL_MG6 _ADC4MG.Overlap_STR.ADC4MGLSTR.Bits.MG6 #define ADC4MGL_MG7 _ADC4MG.Overlap_STR.ADC4MGLSTR.Bits.MG7 #define ADC4MGL_MG0_MASK 1 #define ADC4MGL_MG1_MASK 2 #define ADC4MGL_MG2_MASK 4 #define ADC4MGL_MG3_MASK 8 #define ADC4MGL_MG4_MASK 16 #define ADC4MGL_MG5_MASK 32 #define ADC4MGL_MG6_MASK 64 #define ADC4MGL_MG7_MASK 128 } Overlap_STR; struct { word MG0 :1; /* Gain error correction for the minus-side input value bit 0 */ word MG1 :1; /* Gain error correction for the minus-side input value bit 1 */ word MG2 :1; /* Gain error correction for the minus-side input value bit 2 */ word MG3 :1; /* Gain error correction for the minus-side input value bit 3 */ word MG4 :1; /* Gain error correction for the minus-side input value bit 4 */ word MG5 :1; /* Gain error correction for the minus-side input value bit 5 */ word MG6 :1; /* Gain error correction for the minus-side input value bit 6 */ word MG7 :1; /* Gain error correction for the minus-side input value bit 7 */ word MG8 :1; /* Gain error correction for the minus-side input value bit 8 */ word MG9 :1; /* Gain error correction for the minus-side input value bit 9 */ word MG10 :1; /* Gain error correction for the minus-side input value bit 10 */ word MG11 :1; /* Gain error correction for the minus-side input value bit 11 */ word MG12 :1; /* Gain error correction for the minus-side input value bit 12 */ word MG13 :1; /* Gain error correction for the minus-side input value bit 13 */ word MG14 :1; /* Gain error correction for the minus-side input value bit 14 */ word MG15 :1; /* Gain error correction for the minus-side input value bit 15 */ } Bits; } ADC4MGSTR; extern volatile ADC4MGSTR _ADC4MG @0xFFFF84D2; #define ADC4MG _ADC4MG.Word #define ADC4MG_MG0 _ADC4MG.Bits.MG0 #define ADC4MG_MG1 _ADC4MG.Bits.MG1 #define ADC4MG_MG2 _ADC4MG.Bits.MG2 #define ADC4MG_MG3 _ADC4MG.Bits.MG3 #define ADC4MG_MG4 _ADC4MG.Bits.MG4 #define ADC4MG_MG5 _ADC4MG.Bits.MG5 #define ADC4MG_MG6 _ADC4MG.Bits.MG6 #define ADC4MG_MG7 _ADC4MG.Bits.MG7 #define ADC4MG_MG8 _ADC4MG.Bits.MG8 #define ADC4MG_MG9 _ADC4MG.Bits.MG9 #define ADC4MG_MG10 _ADC4MG.Bits.MG10 #define ADC4MG_MG11 _ADC4MG.Bits.MG11 #define ADC4MG_MG12 _ADC4MG.Bits.MG12 #define ADC4MG_MG13 _ADC4MG.Bits.MG13 #define ADC4MG_MG14 _ADC4MG.Bits.MG14 #define ADC4MG_MG15 _ADC4MG.Bits.MG15 #define ADC4MG_MG0_MASK 1 #define ADC4MG_MG1_MASK 2 #define ADC4MG_MG2_MASK 4 #define ADC4MG_MG3_MASK 8 #define ADC4MG_MG4_MASK 16 #define ADC4MG_MG5_MASK 32 #define ADC4MG_MG6_MASK 64 #define ADC4MG_MG7_MASK 128 #define ADC4MG_MG8_MASK 256 #define ADC4MG_MG9_MASK 512 #define ADC4MG_MG10_MASK 1024 #define ADC4MG_MG11_MASK 2048 #define ADC4MG_MG12_MASK 4096 #define ADC4MG_MG13_MASK 8192 #define ADC4MG_MG14_MASK 16384 #define ADC4MG_MG15_MASK 32768 /*** ADC4CLPD - Plus-Side General Calibration Value D Register; 0xFFFF84D4 ***/ typedef union { byte Byte; struct { byte CLPD0 :1; /* Plus-Side General Calibration Value D bit 0 */ byte CLPD1 :1; /* Plus-Side General Calibration Value D bit 1 */ byte CLPD2 :1; /* Plus-Side General Calibration Value D bit 2 */ byte CLPD3 :1; /* Plus-Side General Calibration Value D bit 3 */ byte CLPD4 :1; /* Plus-Side General Calibration Value D bit 4 */ byte CLPD5 :1; /* Plus-Side General Calibration Value D bit 5 */ byte :1; byte :1; } Bits; struct { byte grpCLPD :6; byte :1; byte :1; } MergedBits; } ADC4CLPDSTR; extern volatile ADC4CLPDSTR _ADC4CLPD @0xFFFF84D4; #define ADC4CLPD _ADC4CLPD.Byte #define ADC4CLPD_CLPD0 _ADC4CLPD.Bits.CLPD0 #define ADC4CLPD_CLPD1 _ADC4CLPD.Bits.CLPD1 #define ADC4CLPD_CLPD2 _ADC4CLPD.Bits.CLPD2 #define ADC4CLPD_CLPD3 _ADC4CLPD.Bits.CLPD3 #define ADC4CLPD_CLPD4 _ADC4CLPD.Bits.CLPD4 #define ADC4CLPD_CLPD5 _ADC4CLPD.Bits.CLPD5 #define ADC4CLPD_CLPD _ADC4CLPD.MergedBits.grpCLPD #define ADC4CLPD_CLPD0_MASK 1 #define ADC4CLPD_CLPD1_MASK 2 #define ADC4CLPD_CLPD2_MASK 4 #define ADC4CLPD_CLPD3_MASK 8 #define ADC4CLPD_CLPD4_MASK 16 #define ADC4CLPD_CLPD5_MASK 32 #define ADC4CLPD_CLPD_MASK 63 #define ADC4CLPD_CLPD_BITNUM 0 /*** ADC4CLPS - Plus-Side General Calibration Value S Register; 0xFFFF84D5 ***/ typedef union { byte Byte; struct { byte CLPS0 :1; /* Plus-Side General Calibration Value S bit 0 */ byte CLPS1 :1; /* Plus-Side General Calibration Value S bit 1 */ byte CLPS2 :1; /* Plus-Side General Calibration Value S bit 2 */ byte CLPS3 :1; /* Plus-Side General Calibration Value S bit 3 */ byte CLPS4 :1; /* Plus-Side General Calibration Value S bit 4 */ byte CLPS5 :1; /* Plus-Side General Calibration Value S bit 5 */ byte :1; byte :1; } Bits; struct { byte grpCLPS :6; byte :1; byte :1; } MergedBits; } ADC4CLPSSTR; extern volatile ADC4CLPSSTR _ADC4CLPS @0xFFFF84D5; #define ADC4CLPS _ADC4CLPS.Byte #define ADC4CLPS_CLPS0 _ADC4CLPS.Bits.CLPS0 #define ADC4CLPS_CLPS1 _ADC4CLPS.Bits.CLPS1 #define ADC4CLPS_CLPS2 _ADC4CLPS.Bits.CLPS2 #define ADC4CLPS_CLPS3 _ADC4CLPS.Bits.CLPS3 #define ADC4CLPS_CLPS4 _ADC4CLPS.Bits.CLPS4 #define ADC4CLPS_CLPS5 _ADC4CLPS.Bits.CLPS5 #define ADC4CLPS_CLPS _ADC4CLPS.MergedBits.grpCLPS #define ADC4CLPS_CLPS0_MASK 1 #define ADC4CLPS_CLPS1_MASK 2 #define ADC4CLPS_CLPS2_MASK 4 #define ADC4CLPS_CLPS3_MASK 8 #define ADC4CLPS_CLPS4_MASK 16 #define ADC4CLPS_CLPS5_MASK 32 #define ADC4CLPS_CLPS_MASK 63 #define ADC4CLPS_CLPS_BITNUM 0 /*** ADC4CLP4 - Plus-Side General Calibration Value 4 Register; 0xFFFF84D6 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC4CLP4H - Plus-Side General Calibration Value 4 High Register; 0xFFFF84D6 ***/ union { byte Byte; struct { byte CLP48 :1; /* Plus-Side General Calibration Value 4 bit 8 */ byte CLP49 :1; /* Plus-Side General Calibration Value 4 bit 9 */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpCLP_48 :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ADC4CLP4HSTR; #define ADC4CLP4H _ADC4CLP4.Overlap_STR.ADC4CLP4HSTR.Byte #define ADC4CLP4H_CLP48 _ADC4CLP4.Overlap_STR.ADC4CLP4HSTR.Bits.CLP48 #define ADC4CLP4H_CLP49 _ADC4CLP4.Overlap_STR.ADC4CLP4HSTR.Bits.CLP49 #define ADC4CLP4H_CLP_48 _ADC4CLP4.Overlap_STR.ADC4CLP4HSTR.MergedBits.grpCLP_48 #define ADC4CLP4H_CLP ADC4CLP4H_CLP_48 #define ADC4CLP4H_CLP48_MASK 1 #define ADC4CLP4H_CLP49_MASK 2 #define ADC4CLP4H_CLP_48_MASK 3 #define ADC4CLP4H_CLP_48_BITNUM 0 /*** ADC4CLP4L - Plus-Side General Calibration Value 4 Low Register; 0xFFFF84D7 ***/ union { byte Byte; struct { byte CLP40 :1; /* Plus-Side General Calibration Value 4 bit 0 */ byte CLP41 :1; /* Plus-Side General Calibration Value 4 bit 1 */ byte CLP42 :1; /* Plus-Side General Calibration Value 4 bit 2 */ byte CLP43 :1; /* Plus-Side General Calibration Value 4 bit 3 */ byte CLP44 :1; /* Plus-Side General Calibration Value 4 bit 4 */ byte CLP45 :1; /* Plus-Side General Calibration Value 4 bit 5 */ byte CLP46 :1; /* Plus-Side General Calibration Value 4 bit 6 */ byte CLP47 :1; /* Plus-Side General Calibration Value 4 bit 7 */ } Bits; } ADC4CLP4LSTR; #define ADC4CLP4L _ADC4CLP4.Overlap_STR.ADC4CLP4LSTR.Byte #define ADC4CLP4L_CLP40 _ADC4CLP4.Overlap_STR.ADC4CLP4LSTR.Bits.CLP40 #define ADC4CLP4L_CLP41 _ADC4CLP4.Overlap_STR.ADC4CLP4LSTR.Bits.CLP41 #define ADC4CLP4L_CLP42 _ADC4CLP4.Overlap_STR.ADC4CLP4LSTR.Bits.CLP42 #define ADC4CLP4L_CLP43 _ADC4CLP4.Overlap_STR.ADC4CLP4LSTR.Bits.CLP43 #define ADC4CLP4L_CLP44 _ADC4CLP4.Overlap_STR.ADC4CLP4LSTR.Bits.CLP44 #define ADC4CLP4L_CLP45 _ADC4CLP4.Overlap_STR.ADC4CLP4LSTR.Bits.CLP45 #define ADC4CLP4L_CLP46 _ADC4CLP4.Overlap_STR.ADC4CLP4LSTR.Bits.CLP46 #define ADC4CLP4L_CLP47 _ADC4CLP4.Overlap_STR.ADC4CLP4LSTR.Bits.CLP47 #define ADC4CLP4L_CLP40_MASK 1 #define ADC4CLP4L_CLP41_MASK 2 #define ADC4CLP4L_CLP42_MASK 4 #define ADC4CLP4L_CLP43_MASK 8 #define ADC4CLP4L_CLP44_MASK 16 #define ADC4CLP4L_CLP45_MASK 32 #define ADC4CLP4L_CLP46_MASK 64 #define ADC4CLP4L_CLP47_MASK 128 } Overlap_STR; struct { word CLP40 :1; /* Plus-Side General Calibration Value 4 bit 0 */ word CLP41 :1; /* Plus-Side General Calibration Value 4 bit 1 */ word CLP42 :1; /* Plus-Side General Calibration Value 4 bit 2 */ word CLP43 :1; /* Plus-Side General Calibration Value 4 bit 3 */ word CLP44 :1; /* Plus-Side General Calibration Value 4 bit 4 */ word CLP45 :1; /* Plus-Side General Calibration Value 4 bit 5 */ word CLP46 :1; /* Plus-Side General Calibration Value 4 bit 6 */ word CLP47 :1; /* Plus-Side General Calibration Value 4 bit 7 */ word CLP48 :1; /* Plus-Side General Calibration Value 4 bit 8 */ word CLP49 :1; /* Plus-Side General Calibration Value 4 bit 9 */ word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpCLP_40 :10; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } ADC4CLP4STR; extern volatile ADC4CLP4STR _ADC4CLP4 @0xFFFF84D6; #define ADC4CLP4 _ADC4CLP4.Word #define ADC4CLP4_CLP40 _ADC4CLP4.Bits.CLP40 #define ADC4CLP4_CLP41 _ADC4CLP4.Bits.CLP41 #define ADC4CLP4_CLP42 _ADC4CLP4.Bits.CLP42 #define ADC4CLP4_CLP43 _ADC4CLP4.Bits.CLP43 #define ADC4CLP4_CLP44 _ADC4CLP4.Bits.CLP44 #define ADC4CLP4_CLP45 _ADC4CLP4.Bits.CLP45 #define ADC4CLP4_CLP46 _ADC4CLP4.Bits.CLP46 #define ADC4CLP4_CLP47 _ADC4CLP4.Bits.CLP47 #define ADC4CLP4_CLP48 _ADC4CLP4.Bits.CLP48 #define ADC4CLP4_CLP49 _ADC4CLP4.Bits.CLP49 #define ADC4CLP4_CLP_40 _ADC4CLP4.MergedBits.grpCLP_40 #define ADC4CLP4_CLP ADC4CLP4_CLP_40 #define ADC4CLP4_CLP40_MASK 1 #define ADC4CLP4_CLP41_MASK 2 #define ADC4CLP4_CLP42_MASK 4 #define ADC4CLP4_CLP43_MASK 8 #define ADC4CLP4_CLP44_MASK 16 #define ADC4CLP4_CLP45_MASK 32 #define ADC4CLP4_CLP46_MASK 64 #define ADC4CLP4_CLP47_MASK 128 #define ADC4CLP4_CLP48_MASK 256 #define ADC4CLP4_CLP49_MASK 512 #define ADC4CLP4_CLP_40_MASK 1023 #define ADC4CLP4_CLP_40_BITNUM 0 /*** ADC4CLP3 - Plus-Side General Calibration Value 3 Register; 0xFFFF84D8 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC4CLP3H - Plus-Side General Calibration Value 3 High Register; 0xFFFF84D8 ***/ union { byte Byte; struct { byte CLP38 :1; /* Plus-Side General Calibration Value 3 bits */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } ADC4CLP3HSTR; #define ADC4CLP3H _ADC4CLP3.Overlap_STR.ADC4CLP3HSTR.Byte #define ADC4CLP3H_CLP38 _ADC4CLP3.Overlap_STR.ADC4CLP3HSTR.Bits.CLP38 #define ADC4CLP3H_CLP38_MASK 1 /*** ADC4CLP3L - Plus-Side General Calibration Value 3 Low Register; 0xFFFF84D9 ***/ union { byte Byte; struct { byte CLP30 :1; /* Plus-Side General Calibration Value 3 bit 0 */ byte CLP31 :1; /* Plus-Side General Calibration Value 3 bit 1 */ byte CLP32 :1; /* Plus-Side General Calibration Value 3 bit 2 */ byte CLP33 :1; /* Plus-Side General Calibration Value 3 bit 3 */ byte CLP34 :1; /* Plus-Side General Calibration Value 3 bit 4 */ byte CLP35 :1; /* Plus-Side General Calibration Value 3 bit 5 */ byte CLP36 :1; /* Plus-Side General Calibration Value 3 bit 6 */ byte CLP37 :1; /* Plus-Side General Calibration Value 3 bit 7 */ } Bits; } ADC4CLP3LSTR; #define ADC4CLP3L _ADC4CLP3.Overlap_STR.ADC4CLP3LSTR.Byte #define ADC4CLP3L_CLP30 _ADC4CLP3.Overlap_STR.ADC4CLP3LSTR.Bits.CLP30 #define ADC4CLP3L_CLP31 _ADC4CLP3.Overlap_STR.ADC4CLP3LSTR.Bits.CLP31 #define ADC4CLP3L_CLP32 _ADC4CLP3.Overlap_STR.ADC4CLP3LSTR.Bits.CLP32 #define ADC4CLP3L_CLP33 _ADC4CLP3.Overlap_STR.ADC4CLP3LSTR.Bits.CLP33 #define ADC4CLP3L_CLP34 _ADC4CLP3.Overlap_STR.ADC4CLP3LSTR.Bits.CLP34 #define ADC4CLP3L_CLP35 _ADC4CLP3.Overlap_STR.ADC4CLP3LSTR.Bits.CLP35 #define ADC4CLP3L_CLP36 _ADC4CLP3.Overlap_STR.ADC4CLP3LSTR.Bits.CLP36 #define ADC4CLP3L_CLP37 _ADC4CLP3.Overlap_STR.ADC4CLP3LSTR.Bits.CLP37 #define ADC4CLP3L_CLP30_MASK 1 #define ADC4CLP3L_CLP31_MASK 2 #define ADC4CLP3L_CLP32_MASK 4 #define ADC4CLP3L_CLP33_MASK 8 #define ADC4CLP3L_CLP34_MASK 16 #define ADC4CLP3L_CLP35_MASK 32 #define ADC4CLP3L_CLP36_MASK 64 #define ADC4CLP3L_CLP37_MASK 128 } Overlap_STR; struct { word CLP30 :1; /* Plus-Side General Calibration Value 3 bit 0 */ word CLP31 :1; /* Plus-Side General Calibration Value 3 bit 1 */ word CLP32 :1; /* Plus-Side General Calibration Value 3 bit 2 */ word CLP33 :1; /* Plus-Side General Calibration Value 3 bit 3 */ word CLP34 :1; /* Plus-Side General Calibration Value 3 bit 4 */ word CLP35 :1; /* Plus-Side General Calibration Value 3 bit 5 */ word CLP36 :1; /* Plus-Side General Calibration Value 3 bit 6 */ word CLP37 :1; /* Plus-Side General Calibration Value 3 bit 7 */ word CLP38 :1; /* Plus-Side General Calibration Value 3 bit 8 */ word :1; word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpCLP_30 :9; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } ADC4CLP3STR; extern volatile ADC4CLP3STR _ADC4CLP3 @0xFFFF84D8; #define ADC4CLP3 _ADC4CLP3.Word #define ADC4CLP3_CLP30 _ADC4CLP3.Bits.CLP30 #define ADC4CLP3_CLP31 _ADC4CLP3.Bits.CLP31 #define ADC4CLP3_CLP32 _ADC4CLP3.Bits.CLP32 #define ADC4CLP3_CLP33 _ADC4CLP3.Bits.CLP33 #define ADC4CLP3_CLP34 _ADC4CLP3.Bits.CLP34 #define ADC4CLP3_CLP35 _ADC4CLP3.Bits.CLP35 #define ADC4CLP3_CLP36 _ADC4CLP3.Bits.CLP36 #define ADC4CLP3_CLP37 _ADC4CLP3.Bits.CLP37 #define ADC4CLP3_CLP38 _ADC4CLP3.Bits.CLP38 #define ADC4CLP3_CLP_30 _ADC4CLP3.MergedBits.grpCLP_30 #define ADC4CLP3_CLP ADC4CLP3_CLP_30 #define ADC4CLP3_CLP30_MASK 1 #define ADC4CLP3_CLP31_MASK 2 #define ADC4CLP3_CLP32_MASK 4 #define ADC4CLP3_CLP33_MASK 8 #define ADC4CLP3_CLP34_MASK 16 #define ADC4CLP3_CLP35_MASK 32 #define ADC4CLP3_CLP36_MASK 64 #define ADC4CLP3_CLP37_MASK 128 #define ADC4CLP3_CLP38_MASK 256 #define ADC4CLP3_CLP_30_MASK 511 #define ADC4CLP3_CLP_30_BITNUM 0 /*** ADC4CLP2 - Plus-Side General Calibration Value 2 Register; 0xFFFF84DA ***/ typedef union { byte Byte; struct { byte CLP20 :1; /* Plus-Side General Calibration Value 2 bit 0 */ byte CLP21 :1; /* Plus-Side General Calibration Value 2 bit 1 */ byte CLP22 :1; /* Plus-Side General Calibration Value 2 bit 2 */ byte CLP23 :1; /* Plus-Side General Calibration Value 2 bit 3 */ byte CLP24 :1; /* Plus-Side General Calibration Value 2 bit 4 */ byte CLP25 :1; /* Plus-Side General Calibration Value 2 bit 5 */ byte CLP26 :1; /* Plus-Side General Calibration Value 2 bit 6 */ byte CLP27 :1; /* Plus-Side General Calibration Value 2 bit 7 */ } Bits; } ADC4CLP2STR; extern volatile ADC4CLP2STR _ADC4CLP2 @0xFFFF84DA; #define ADC4CLP2 _ADC4CLP2.Byte #define ADC4CLP2_CLP20 _ADC4CLP2.Bits.CLP20 #define ADC4CLP2_CLP21 _ADC4CLP2.Bits.CLP21 #define ADC4CLP2_CLP22 _ADC4CLP2.Bits.CLP22 #define ADC4CLP2_CLP23 _ADC4CLP2.Bits.CLP23 #define ADC4CLP2_CLP24 _ADC4CLP2.Bits.CLP24 #define ADC4CLP2_CLP25 _ADC4CLP2.Bits.CLP25 #define ADC4CLP2_CLP26 _ADC4CLP2.Bits.CLP26 #define ADC4CLP2_CLP27 _ADC4CLP2.Bits.CLP27 #define ADC4CLP2_CLP20_MASK 1 #define ADC4CLP2_CLP21_MASK 2 #define ADC4CLP2_CLP22_MASK 4 #define ADC4CLP2_CLP23_MASK 8 #define ADC4CLP2_CLP24_MASK 16 #define ADC4CLP2_CLP25_MASK 32 #define ADC4CLP2_CLP26_MASK 64 #define ADC4CLP2_CLP27_MASK 128 /*** ADC4CLP1 - Plus-Side General Calibration Value 1 Register; 0xFFFF84DB ***/ typedef union { byte Byte; struct { byte CLP10 :1; /* Plus-Side General Calibration Value 1 bit 0 */ byte CLP11 :1; /* Plus-Side General Calibration Value 1 bit 1 */ byte CLP12 :1; /* Plus-Side General Calibration Value 1 bit 2 */ byte CLP13 :1; /* Plus-Side General Calibration Value 1 bit 3 */ byte CLP14 :1; /* Plus-Side General Calibration Value 1 bit 4 */ byte CLP15 :1; /* Plus-Side General Calibration Value 1 bit 5 */ byte CLP16 :1; /* Plus-Side General Calibration Value 1 bit 6 */ byte :1; } Bits; struct { byte grpCLP_10 :7; byte :1; } MergedBits; } ADC4CLP1STR; extern volatile ADC4CLP1STR _ADC4CLP1 @0xFFFF84DB; #define ADC4CLP1 _ADC4CLP1.Byte #define ADC4CLP1_CLP10 _ADC4CLP1.Bits.CLP10 #define ADC4CLP1_CLP11 _ADC4CLP1.Bits.CLP11 #define ADC4CLP1_CLP12 _ADC4CLP1.Bits.CLP12 #define ADC4CLP1_CLP13 _ADC4CLP1.Bits.CLP13 #define ADC4CLP1_CLP14 _ADC4CLP1.Bits.CLP14 #define ADC4CLP1_CLP15 _ADC4CLP1.Bits.CLP15 #define ADC4CLP1_CLP16 _ADC4CLP1.Bits.CLP16 #define ADC4CLP1_CLP_10 _ADC4CLP1.MergedBits.grpCLP_10 #define ADC4CLP1_CLP ADC4CLP1_CLP_10 #define ADC4CLP1_CLP10_MASK 1 #define ADC4CLP1_CLP11_MASK 2 #define ADC4CLP1_CLP12_MASK 4 #define ADC4CLP1_CLP13_MASK 8 #define ADC4CLP1_CLP14_MASK 16 #define ADC4CLP1_CLP15_MASK 32 #define ADC4CLP1_CLP16_MASK 64 #define ADC4CLP1_CLP_10_MASK 127 #define ADC4CLP1_CLP_10_BITNUM 0 /*** ADC4CLP0 - Plus-Side General Calibration Value 0 Register; 0xFFFF84DC ***/ typedef union { byte Byte; struct { byte CLP00 :1; /* Plus-Side General Calibration Value 0 bit 0 */ byte CLP01 :1; /* Plus-Side General Calibration Value 0 bit 1 */ byte CLP02 :1; /* Plus-Side General Calibration Value 0 bit 2 */ byte CLP03 :1; /* Plus-Side General Calibration Value 0 bit 3 */ byte CLP04 :1; /* Plus-Side General Calibration Value 0 bit 4 */ byte CLP05 :1; /* Plus-Side General Calibration Value 0 bit 5 */ byte :1; byte :1; } Bits; struct { byte grpCLP0 :6; byte :1; byte :1; } MergedBits; } ADC4CLP0STR; extern volatile ADC4CLP0STR _ADC4CLP0 @0xFFFF84DC; #define ADC4CLP0 _ADC4CLP0.Byte #define ADC4CLP0_CLP00 _ADC4CLP0.Bits.CLP00 #define ADC4CLP0_CLP01 _ADC4CLP0.Bits.CLP01 #define ADC4CLP0_CLP02 _ADC4CLP0.Bits.CLP02 #define ADC4CLP0_CLP03 _ADC4CLP0.Bits.CLP03 #define ADC4CLP0_CLP04 _ADC4CLP0.Bits.CLP04 #define ADC4CLP0_CLP05 _ADC4CLP0.Bits.CLP05 #define ADC4CLP0_CLP0 _ADC4CLP0.MergedBits.grpCLP0 #define ADC4CLP0_CLP00_MASK 1 #define ADC4CLP0_CLP01_MASK 2 #define ADC4CLP0_CLP02_MASK 4 #define ADC4CLP0_CLP03_MASK 8 #define ADC4CLP0_CLP04_MASK 16 #define ADC4CLP0_CLP05_MASK 32 #define ADC4CLP0_CLP0_MASK 63 #define ADC4CLP0_CLP0_BITNUM 0 /*** ADC4CLMD - Minus-Side General Calibration Value D Register; 0xFFFF84DE ***/ typedef union { byte Byte; struct { byte CLMD0 :1; /* Minus-Side General Calibration Value D bit 0 */ byte CLMD1 :1; /* Minus-Side General Calibration Value D bit 1 */ byte CLMD2 :1; /* Minus-Side General Calibration Value D bit 2 */ byte CLMD3 :1; /* Minus-Side General Calibration Value D bit 3 */ byte CLMD4 :1; /* Minus-Side General Calibration Value D bit 4 */ byte CLMD5 :1; /* Minus-Side General Calibration Value D bit 5 */ byte :1; byte :1; } Bits; struct { byte grpCLMD :6; byte :1; byte :1; } MergedBits; } ADC4CLMDSTR; extern volatile ADC4CLMDSTR _ADC4CLMD @0xFFFF84DE; #define ADC4CLMD _ADC4CLMD.Byte #define ADC4CLMD_CLMD0 _ADC4CLMD.Bits.CLMD0 #define ADC4CLMD_CLMD1 _ADC4CLMD.Bits.CLMD1 #define ADC4CLMD_CLMD2 _ADC4CLMD.Bits.CLMD2 #define ADC4CLMD_CLMD3 _ADC4CLMD.Bits.CLMD3 #define ADC4CLMD_CLMD4 _ADC4CLMD.Bits.CLMD4 #define ADC4CLMD_CLMD5 _ADC4CLMD.Bits.CLMD5 #define ADC4CLMD_CLMD _ADC4CLMD.MergedBits.grpCLMD #define ADC4CLMD_CLMD0_MASK 1 #define ADC4CLMD_CLMD1_MASK 2 #define ADC4CLMD_CLMD2_MASK 4 #define ADC4CLMD_CLMD3_MASK 8 #define ADC4CLMD_CLMD4_MASK 16 #define ADC4CLMD_CLMD5_MASK 32 #define ADC4CLMD_CLMD_MASK 63 #define ADC4CLMD_CLMD_BITNUM 0 /*** ADC4CLMS - Minus-Side General Calibration Value S Register; 0xFFFF84DF ***/ typedef union { byte Byte; struct { byte CLMS0 :1; /* Minus-Side General Calibration Value S bit 0 */ byte CLMS1 :1; /* Minus-Side General Calibration Value S bit 1 */ byte CLMS2 :1; /* Minus-Side General Calibration Value S bit 2 */ byte CLMS3 :1; /* Minus-Side General Calibration Value S bit 3 */ byte CLMS4 :1; /* Minus-Side General Calibration Value S bit 4 */ byte CLMS5 :1; /* Minus-Side General Calibration Value S bit 5 */ byte :1; byte :1; } Bits; struct { byte grpCLMS :6; byte :1; byte :1; } MergedBits; } ADC4CLMSSTR; extern volatile ADC4CLMSSTR _ADC4CLMS @0xFFFF84DF; #define ADC4CLMS _ADC4CLMS.Byte #define ADC4CLMS_CLMS0 _ADC4CLMS.Bits.CLMS0 #define ADC4CLMS_CLMS1 _ADC4CLMS.Bits.CLMS1 #define ADC4CLMS_CLMS2 _ADC4CLMS.Bits.CLMS2 #define ADC4CLMS_CLMS3 _ADC4CLMS.Bits.CLMS3 #define ADC4CLMS_CLMS4 _ADC4CLMS.Bits.CLMS4 #define ADC4CLMS_CLMS5 _ADC4CLMS.Bits.CLMS5 #define ADC4CLMS_CLMS _ADC4CLMS.MergedBits.grpCLMS #define ADC4CLMS_CLMS0_MASK 1 #define ADC4CLMS_CLMS1_MASK 2 #define ADC4CLMS_CLMS2_MASK 4 #define ADC4CLMS_CLMS3_MASK 8 #define ADC4CLMS_CLMS4_MASK 16 #define ADC4CLMS_CLMS5_MASK 32 #define ADC4CLMS_CLMS_MASK 63 #define ADC4CLMS_CLMS_BITNUM 0 /*** ADC4CLM4 - Minus-Side General Calibration Value 4 Register; 0xFFFF84E0 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC4CLM4H - Minus-Side General Calibration Value 4 High Register; 0xFFFF84E0 ***/ union { byte Byte; struct { byte CLM48 :1; /* Minus-Side General Calibration Value 4 bit 8 */ byte CLM49 :1; /* Minus-Side General Calibration Value 4 bit 9 */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpCLM_48 :2; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } ADC4CLM4HSTR; #define ADC4CLM4H _ADC4CLM4.Overlap_STR.ADC4CLM4HSTR.Byte #define ADC4CLM4H_CLM48 _ADC4CLM4.Overlap_STR.ADC4CLM4HSTR.Bits.CLM48 #define ADC4CLM4H_CLM49 _ADC4CLM4.Overlap_STR.ADC4CLM4HSTR.Bits.CLM49 #define ADC4CLM4H_CLM_48 _ADC4CLM4.Overlap_STR.ADC4CLM4HSTR.MergedBits.grpCLM_48 #define ADC4CLM4H_CLM ADC4CLM4H_CLM_48 #define ADC4CLM4H_CLM48_MASK 1 #define ADC4CLM4H_CLM49_MASK 2 #define ADC4CLM4H_CLM_48_MASK 3 #define ADC4CLM4H_CLM_48_BITNUM 0 /*** ADC4CLM4L - Minus-Side General Calibration Value 4 Low Register; 0xFFFF84E1 ***/ union { byte Byte; struct { byte CLM40 :1; /* Minus-Side General Calibration Value 4 bit 0 */ byte CLM41 :1; /* Minus-Side General Calibration Value 4 bit 1 */ byte CLM42 :1; /* Minus-Side General Calibration Value 4 bit 2 */ byte CLM43 :1; /* Minus-Side General Calibration Value 4 bit 3 */ byte CLM44 :1; /* Minus-Side General Calibration Value 4 bit 4 */ byte CLM45 :1; /* Minus-Side General Calibration Value 4 bit 5 */ byte CLM46 :1; /* Minus-Side General Calibration Value 4 bit 6 */ byte CLM47 :1; /* Minus-Side General Calibration Value 4 bit 7 */ } Bits; } ADC4CLM4LSTR; #define ADC4CLM4L _ADC4CLM4.Overlap_STR.ADC4CLM4LSTR.Byte #define ADC4CLM4L_CLM40 _ADC4CLM4.Overlap_STR.ADC4CLM4LSTR.Bits.CLM40 #define ADC4CLM4L_CLM41 _ADC4CLM4.Overlap_STR.ADC4CLM4LSTR.Bits.CLM41 #define ADC4CLM4L_CLM42 _ADC4CLM4.Overlap_STR.ADC4CLM4LSTR.Bits.CLM42 #define ADC4CLM4L_CLM43 _ADC4CLM4.Overlap_STR.ADC4CLM4LSTR.Bits.CLM43 #define ADC4CLM4L_CLM44 _ADC4CLM4.Overlap_STR.ADC4CLM4LSTR.Bits.CLM44 #define ADC4CLM4L_CLM45 _ADC4CLM4.Overlap_STR.ADC4CLM4LSTR.Bits.CLM45 #define ADC4CLM4L_CLM46 _ADC4CLM4.Overlap_STR.ADC4CLM4LSTR.Bits.CLM46 #define ADC4CLM4L_CLM47 _ADC4CLM4.Overlap_STR.ADC4CLM4LSTR.Bits.CLM47 #define ADC4CLM4L_CLM40_MASK 1 #define ADC4CLM4L_CLM41_MASK 2 #define ADC4CLM4L_CLM42_MASK 4 #define ADC4CLM4L_CLM43_MASK 8 #define ADC4CLM4L_CLM44_MASK 16 #define ADC4CLM4L_CLM45_MASK 32 #define ADC4CLM4L_CLM46_MASK 64 #define ADC4CLM4L_CLM47_MASK 128 } Overlap_STR; struct { word CLM40 :1; /* Minus-Side General Calibration Value 4 bit 0 */ word CLM41 :1; /* Minus-Side General Calibration Value 4 bit 1 */ word CLM42 :1; /* Minus-Side General Calibration Value 4 bit 2 */ word CLM43 :1; /* Minus-Side General Calibration Value 4 bit 3 */ word CLM44 :1; /* Minus-Side General Calibration Value 4 bit 4 */ word CLM45 :1; /* Minus-Side General Calibration Value 4 bit 5 */ word CLM46 :1; /* Minus-Side General Calibration Value 4 bit 6 */ word CLM47 :1; /* Minus-Side General Calibration Value 4 bit 7 */ word CLM48 :1; /* Minus-Side General Calibration Value 4 bit 8 */ word CLM49 :1; /* Minus-Side General Calibration Value 4 bit 9 */ word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpCLM_40 :10; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } ADC4CLM4STR; extern volatile ADC4CLM4STR _ADC4CLM4 @0xFFFF84E0; #define ADC4CLM4 _ADC4CLM4.Word #define ADC4CLM4_CLM40 _ADC4CLM4.Bits.CLM40 #define ADC4CLM4_CLM41 _ADC4CLM4.Bits.CLM41 #define ADC4CLM4_CLM42 _ADC4CLM4.Bits.CLM42 #define ADC4CLM4_CLM43 _ADC4CLM4.Bits.CLM43 #define ADC4CLM4_CLM44 _ADC4CLM4.Bits.CLM44 #define ADC4CLM4_CLM45 _ADC4CLM4.Bits.CLM45 #define ADC4CLM4_CLM46 _ADC4CLM4.Bits.CLM46 #define ADC4CLM4_CLM47 _ADC4CLM4.Bits.CLM47 #define ADC4CLM4_CLM48 _ADC4CLM4.Bits.CLM48 #define ADC4CLM4_CLM49 _ADC4CLM4.Bits.CLM49 #define ADC4CLM4_CLM_40 _ADC4CLM4.MergedBits.grpCLM_40 #define ADC4CLM4_CLM ADC4CLM4_CLM_40 #define ADC4CLM4_CLM40_MASK 1 #define ADC4CLM4_CLM41_MASK 2 #define ADC4CLM4_CLM42_MASK 4 #define ADC4CLM4_CLM43_MASK 8 #define ADC4CLM4_CLM44_MASK 16 #define ADC4CLM4_CLM45_MASK 32 #define ADC4CLM4_CLM46_MASK 64 #define ADC4CLM4_CLM47_MASK 128 #define ADC4CLM4_CLM48_MASK 256 #define ADC4CLM4_CLM49_MASK 512 #define ADC4CLM4_CLM_40_MASK 1023 #define ADC4CLM4_CLM_40_BITNUM 0 /*** ADC4CLM3 - Minus-Side General Calibration Value 3 Register; 0xFFFF84E2 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** ADC4CLM3H - Minus-Side General Calibration Value 3 High Register; 0xFFFF84E2 ***/ union { byte Byte; struct { byte CLM38 :1; /* Minus-Side General Calibration Value 3 bits */ byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; } Bits; } ADC4CLM3HSTR; #define ADC4CLM3H _ADC4CLM3.Overlap_STR.ADC4CLM3HSTR.Byte #define ADC4CLM3H_CLM38 _ADC4CLM3.Overlap_STR.ADC4CLM3HSTR.Bits.CLM38 #define ADC4CLM3H_CLM38_MASK 1 /*** ADC4CLM3L - Minus-Side General Calibration Value 3 Low Register; 0xFFFF84E3 ***/ union { byte Byte; struct { byte CLM30 :1; /* Minus-Side General Calibration Value 3 bit 0 */ byte CLM31 :1; /* Minus-Side General Calibration Value 3 bit 1 */ byte CLM32 :1; /* Minus-Side General Calibration Value 3 bit 2 */ byte CLM33 :1; /* Minus-Side General Calibration Value 3 bit 3 */ byte CLM34 :1; /* Minus-Side General Calibration Value 3 bit 4 */ byte CLM35 :1; /* Minus-Side General Calibration Value 3 bit 5 */ byte CLM36 :1; /* Minus-Side General Calibration Value 3 bit 6 */ byte CLM37 :1; /* Minus-Side General Calibration Value 3 bit 7 */ } Bits; } ADC4CLM3LSTR; #define ADC4CLM3L _ADC4CLM3.Overlap_STR.ADC4CLM3LSTR.Byte #define ADC4CLM3L_CLM30 _ADC4CLM3.Overlap_STR.ADC4CLM3LSTR.Bits.CLM30 #define ADC4CLM3L_CLM31 _ADC4CLM3.Overlap_STR.ADC4CLM3LSTR.Bits.CLM31 #define ADC4CLM3L_CLM32 _ADC4CLM3.Overlap_STR.ADC4CLM3LSTR.Bits.CLM32 #define ADC4CLM3L_CLM33 _ADC4CLM3.Overlap_STR.ADC4CLM3LSTR.Bits.CLM33 #define ADC4CLM3L_CLM34 _ADC4CLM3.Overlap_STR.ADC4CLM3LSTR.Bits.CLM34 #define ADC4CLM3L_CLM35 _ADC4CLM3.Overlap_STR.ADC4CLM3LSTR.Bits.CLM35 #define ADC4CLM3L_CLM36 _ADC4CLM3.Overlap_STR.ADC4CLM3LSTR.Bits.CLM36 #define ADC4CLM3L_CLM37 _ADC4CLM3.Overlap_STR.ADC4CLM3LSTR.Bits.CLM37 #define ADC4CLM3L_CLM30_MASK 1 #define ADC4CLM3L_CLM31_MASK 2 #define ADC4CLM3L_CLM32_MASK 4 #define ADC4CLM3L_CLM33_MASK 8 #define ADC4CLM3L_CLM34_MASK 16 #define ADC4CLM3L_CLM35_MASK 32 #define ADC4CLM3L_CLM36_MASK 64 #define ADC4CLM3L_CLM37_MASK 128 } Overlap_STR; struct { word CLM30 :1; /* Minus-Side General Calibration Value 3 bit 0 */ word CLM31 :1; /* Minus-Side General Calibration Value 3 bit 1 */ word CLM32 :1; /* Minus-Side General Calibration Value 3 bit 2 */ word CLM33 :1; /* Minus-Side General Calibration Value 3 bit 3 */ word CLM34 :1; /* Minus-Side General Calibration Value 3 bit 4 */ word CLM35 :1; /* Minus-Side General Calibration Value 3 bit 5 */ word CLM36 :1; /* Minus-Side General Calibration Value 3 bit 6 */ word CLM37 :1; /* Minus-Side General Calibration Value 3 bit 7 */ word CLM38 :1; /* Minus-Side General Calibration Value 3 bit 8 */ word :1; word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpCLM_30 :9; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } ADC4CLM3STR; extern volatile ADC4CLM3STR _ADC4CLM3 @0xFFFF84E2; #define ADC4CLM3 _ADC4CLM3.Word #define ADC4CLM3_CLM30 _ADC4CLM3.Bits.CLM30 #define ADC4CLM3_CLM31 _ADC4CLM3.Bits.CLM31 #define ADC4CLM3_CLM32 _ADC4CLM3.Bits.CLM32 #define ADC4CLM3_CLM33 _ADC4CLM3.Bits.CLM33 #define ADC4CLM3_CLM34 _ADC4CLM3.Bits.CLM34 #define ADC4CLM3_CLM35 _ADC4CLM3.Bits.CLM35 #define ADC4CLM3_CLM36 _ADC4CLM3.Bits.CLM36 #define ADC4CLM3_CLM37 _ADC4CLM3.Bits.CLM37 #define ADC4CLM3_CLM38 _ADC4CLM3.Bits.CLM38 #define ADC4CLM3_CLM_30 _ADC4CLM3.MergedBits.grpCLM_30 #define ADC4CLM3_CLM ADC4CLM3_CLM_30 #define ADC4CLM3_CLM30_MASK 1 #define ADC4CLM3_CLM31_MASK 2 #define ADC4CLM3_CLM32_MASK 4 #define ADC4CLM3_CLM33_MASK 8 #define ADC4CLM3_CLM34_MASK 16 #define ADC4CLM3_CLM35_MASK 32 #define ADC4CLM3_CLM36_MASK 64 #define ADC4CLM3_CLM37_MASK 128 #define ADC4CLM3_CLM38_MASK 256 #define ADC4CLM3_CLM_30_MASK 511 #define ADC4CLM3_CLM_30_BITNUM 0 /*** ADC4CLM2 - Minus-Side General Calibration Value 2 Register; 0xFFFF84E4 ***/ typedef union { byte Byte; struct { byte CLM20 :1; /* Minus-Side General Calibration Value 2 bit 0 */ byte CLM21 :1; /* Minus-Side General Calibration Value 2 bit 1 */ byte CLM22 :1; /* Minus-Side General Calibration Value 2 bit 2 */ byte CLM23 :1; /* Minus-Side General Calibration Value 2 bit 3 */ byte CLM24 :1; /* Minus-Side General Calibration Value 2 bit 4 */ byte CLM25 :1; /* Minus-Side General Calibration Value 2 bit 5 */ byte CLM26 :1; /* Minus-Side General Calibration Value 2 bit 6 */ byte CLM27 :1; /* Minus-Side General Calibration Value 2 bit 7 */ } Bits; } ADC4CLM2STR; extern volatile ADC4CLM2STR _ADC4CLM2 @0xFFFF84E4; #define ADC4CLM2 _ADC4CLM2.Byte #define ADC4CLM2_CLM20 _ADC4CLM2.Bits.CLM20 #define ADC4CLM2_CLM21 _ADC4CLM2.Bits.CLM21 #define ADC4CLM2_CLM22 _ADC4CLM2.Bits.CLM22 #define ADC4CLM2_CLM23 _ADC4CLM2.Bits.CLM23 #define ADC4CLM2_CLM24 _ADC4CLM2.Bits.CLM24 #define ADC4CLM2_CLM25 _ADC4CLM2.Bits.CLM25 #define ADC4CLM2_CLM26 _ADC4CLM2.Bits.CLM26 #define ADC4CLM2_CLM27 _ADC4CLM2.Bits.CLM27 #define ADC4CLM2_CLM20_MASK 1 #define ADC4CLM2_CLM21_MASK 2 #define ADC4CLM2_CLM22_MASK 4 #define ADC4CLM2_CLM23_MASK 8 #define ADC4CLM2_CLM24_MASK 16 #define ADC4CLM2_CLM25_MASK 32 #define ADC4CLM2_CLM26_MASK 64 #define ADC4CLM2_CLM27_MASK 128 /*** ADC4CLM1 - Minus-Side General Calibration Value 1 Register; 0xFFFF84E5 ***/ typedef union { byte Byte; struct { byte CLM10 :1; /* Minus-Side General Calibration Value 1 bit 0 */ byte CLM11 :1; /* Minus-Side General Calibration Value 1 bit 1 */ byte CLM12 :1; /* Minus-Side General Calibration Value 1 bit 2 */ byte CLM13 :1; /* Minus-Side General Calibration Value 1 bit 3 */ byte CLM14 :1; /* Minus-Side General Calibration Value 1 bit 4 */ byte CLM15 :1; /* Minus-Side General Calibration Value 1 bit 5 */ byte CLM16 :1; /* Minus-Side General Calibration Value 1 bit 6 */ byte :1; } Bits; struct { byte grpCLM_10 :7; byte :1; } MergedBits; } ADC4CLM1STR; extern volatile ADC4CLM1STR _ADC4CLM1 @0xFFFF84E5; #define ADC4CLM1 _ADC4CLM1.Byte #define ADC4CLM1_CLM10 _ADC4CLM1.Bits.CLM10 #define ADC4CLM1_CLM11 _ADC4CLM1.Bits.CLM11 #define ADC4CLM1_CLM12 _ADC4CLM1.Bits.CLM12 #define ADC4CLM1_CLM13 _ADC4CLM1.Bits.CLM13 #define ADC4CLM1_CLM14 _ADC4CLM1.Bits.CLM14 #define ADC4CLM1_CLM15 _ADC4CLM1.Bits.CLM15 #define ADC4CLM1_CLM16 _ADC4CLM1.Bits.CLM16 #define ADC4CLM1_CLM_10 _ADC4CLM1.MergedBits.grpCLM_10 #define ADC4CLM1_CLM ADC4CLM1_CLM_10 #define ADC4CLM1_CLM10_MASK 1 #define ADC4CLM1_CLM11_MASK 2 #define ADC4CLM1_CLM12_MASK 4 #define ADC4CLM1_CLM13_MASK 8 #define ADC4CLM1_CLM14_MASK 16 #define ADC4CLM1_CLM15_MASK 32 #define ADC4CLM1_CLM16_MASK 64 #define ADC4CLM1_CLM_10_MASK 127 #define ADC4CLM1_CLM_10_BITNUM 0 /*** ADC4CLM0 - Minus-Side General Calibration Value 0 Register; 0xFFFF84E6 ***/ typedef union { byte Byte; struct { byte CLM00 :1; /* Minus-Side General Calibration Value 0 bit 0 */ byte CLM01 :1; /* Minus-Side General Calibration Value 0 bit 1 */ byte CLM02 :1; /* Minus-Side General Calibration Value 0 bit 2 */ byte CLM03 :1; /* Minus-Side General Calibration Value 0 bit 3 */ byte CLM04 :1; /* Minus-Side General Calibration Value 0 bit 4 */ byte CLM05 :1; /* Minus-Side General Calibration Value 0 bit 5 */ byte :1; byte :1; } Bits; struct { byte grpCLM0 :6; byte :1; byte :1; } MergedBits; } ADC4CLM0STR; extern volatile ADC4CLM0STR _ADC4CLM0 @0xFFFF84E6; #define ADC4CLM0 _ADC4CLM0.Byte #define ADC4CLM0_CLM00 _ADC4CLM0.Bits.CLM00 #define ADC4CLM0_CLM01 _ADC4CLM0.Bits.CLM01 #define ADC4CLM0_CLM02 _ADC4CLM0.Bits.CLM02 #define ADC4CLM0_CLM03 _ADC4CLM0.Bits.CLM03 #define ADC4CLM0_CLM04 _ADC4CLM0.Bits.CLM04 #define ADC4CLM0_CLM05 _ADC4CLM0.Bits.CLM05 #define ADC4CLM0_CLM0 _ADC4CLM0.MergedBits.grpCLM0 #define ADC4CLM0_CLM00_MASK 1 #define ADC4CLM0_CLM01_MASK 2 #define ADC4CLM0_CLM02_MASK 4 #define ADC4CLM0_CLM03_MASK 8 #define ADC4CLM0_CLM04_MASK 16 #define ADC4CLM0_CLM05_MASK 32 #define ADC4CLM0_CLM0_MASK 63 #define ADC4CLM0_CLM0_BITNUM 0 /*** PRACMP1CS - PRACMP1 Control and Status Register; 0xFFFF8520 ***/ typedef union { byte Byte; struct { byte ACIEN :1; /* ACMP Interrupt Enable */ byte ACINTS0 :1; /* ACMP Interrupt Select, bit 0 */ byte ACINTS1 :1; /* ACMP Interrupt Select, bit 1 */ byte ACMPO :1; /* ACMP Output Bit */ byte ACOPE :1; /* ACMP Output Pin Enable */ byte :1; byte ACMPF :1; /* ACMP Interrupt Flag */ byte ACEN :1; /* ACMP Module Enable */ } Bits; struct { byte :1; byte grpACINTS :2; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } PRACMP1CSSTR; extern volatile PRACMP1CSSTR _PRACMP1CS @0xFFFF8520; #define PRACMP1CS _PRACMP1CS.Byte #define PRACMP1CS_ACIEN _PRACMP1CS.Bits.ACIEN #define PRACMP1CS_ACINTS0 _PRACMP1CS.Bits.ACINTS0 #define PRACMP1CS_ACINTS1 _PRACMP1CS.Bits.ACINTS1 #define PRACMP1CS_ACMPO _PRACMP1CS.Bits.ACMPO #define PRACMP1CS_ACOPE _PRACMP1CS.Bits.ACOPE #define PRACMP1CS_ACMPF _PRACMP1CS.Bits.ACMPF #define PRACMP1CS_ACEN _PRACMP1CS.Bits.ACEN #define PRACMP1CS_ACINTS _PRACMP1CS.MergedBits.grpACINTS #define PRACMP1CS_ACIEN_MASK 1 #define PRACMP1CS_ACINTS0_MASK 2 #define PRACMP1CS_ACINTS1_MASK 4 #define PRACMP1CS_ACMPO_MASK 8 #define PRACMP1CS_ACOPE_MASK 16 #define PRACMP1CS_ACMPF_MASK 64 #define PRACMP1CS_ACEN_MASK 128 #define PRACMP1CS_ACINTS_MASK 6 #define PRACMP1CS_ACINTS_BITNUM 1 /*** PRACMP1C0 - PRACMP1 Control 0 Register; 0xFFFF8521 ***/ typedef union { byte Byte; struct { byte ACNSEL0 :1; /* ACMP Negative Input Select, bit 0 */ byte ACNSEL1 :1; /* ACMP Negative Input Select, bit 1 */ byte ACNSEL2 :1; /* ACMP Negative Input Select, bit 2 */ byte :1; byte ACPSEL0 :1; /* ACMP Positive Input Select, bit 0 */ byte ACPSEL1 :1; /* ACMP Positive Input Select, bit 1 */ byte ACPSEL2 :1; /* ACMP Positive Input Select, bit 2 */ byte :1; } Bits; struct { byte grpACNSEL :3; byte :1; byte grpACPSEL :3; byte :1; } MergedBits; } PRACMP1C0STR; extern volatile PRACMP1C0STR _PRACMP1C0 @0xFFFF8521; #define PRACMP1C0 _PRACMP1C0.Byte #define PRACMP1C0_ACNSEL0 _PRACMP1C0.Bits.ACNSEL0 #define PRACMP1C0_ACNSEL1 _PRACMP1C0.Bits.ACNSEL1 #define PRACMP1C0_ACNSEL2 _PRACMP1C0.Bits.ACNSEL2 #define PRACMP1C0_ACPSEL0 _PRACMP1C0.Bits.ACPSEL0 #define PRACMP1C0_ACPSEL1 _PRACMP1C0.Bits.ACPSEL1 #define PRACMP1C0_ACPSEL2 _PRACMP1C0.Bits.ACPSEL2 /* PRACMP1C_ARR: Access 3 PRACMP1Cx registers in an array */ #define PRACMP1C_ARR ((volatile byte *) &PRACMP1C0) #define PRACMP1C0_ACNSEL _PRACMP1C0.MergedBits.grpACNSEL #define PRACMP1C0_ACPSEL _PRACMP1C0.MergedBits.grpACPSEL #define PRACMP1C0_ACNSEL0_MASK 1 #define PRACMP1C0_ACNSEL1_MASK 2 #define PRACMP1C0_ACNSEL2_MASK 4 #define PRACMP1C0_ACPSEL0_MASK 16 #define PRACMP1C0_ACPSEL1_MASK 32 #define PRACMP1C0_ACPSEL2_MASK 64 #define PRACMP1C0_ACNSEL_MASK 7 #define PRACMP1C0_ACNSEL_BITNUM 0 #define PRACMP1C0_ACPSEL_MASK 112 #define PRACMP1C0_ACPSEL_BITNUM 4 /*** PRACMP1C1 - PRACMP1 Control 1 Register; 0xFFFF8522 ***/ typedef union { byte Byte; struct { byte PRGOS0 :1; /* Programmable Reference Generator Output Selection, bit 0 */ byte PRGOS1 :1; /* Programmable Reference Generator Output Selection, bit 1 */ byte PRGOS2 :1; /* Programmable Reference Generator Output Selection, bit 2 */ byte PRGOS3 :1; /* Programmable Reference Generator Output Selection, bit 3 */ byte PRGOS4 :1; /* Programmable Reference Generator Output Selection, bit 4 */ byte :1; byte PRGINS :1; /* Programmable Reference Generator Input Selection */ byte PRGEN :1; /* Programmable Reference Generator Enable */ } Bits; struct { byte grpPRGOS :5; byte :1; byte :1; byte :1; } MergedBits; } PRACMP1C1STR; extern volatile PRACMP1C1STR _PRACMP1C1 @0xFFFF8522; #define PRACMP1C1 _PRACMP1C1.Byte #define PRACMP1C1_PRGOS0 _PRACMP1C1.Bits.PRGOS0 #define PRACMP1C1_PRGOS1 _PRACMP1C1.Bits.PRGOS1 #define PRACMP1C1_PRGOS2 _PRACMP1C1.Bits.PRGOS2 #define PRACMP1C1_PRGOS3 _PRACMP1C1.Bits.PRGOS3 #define PRACMP1C1_PRGOS4 _PRACMP1C1.Bits.PRGOS4 #define PRACMP1C1_PRGINS _PRACMP1C1.Bits.PRGINS #define PRACMP1C1_PRGEN _PRACMP1C1.Bits.PRGEN #define PRACMP1C1_PRGOS _PRACMP1C1.MergedBits.grpPRGOS #define PRACMP1C1_PRGOS0_MASK 1 #define PRACMP1C1_PRGOS1_MASK 2 #define PRACMP1C1_PRGOS2_MASK 4 #define PRACMP1C1_PRGOS3_MASK 8 #define PRACMP1C1_PRGOS4_MASK 16 #define PRACMP1C1_PRGINS_MASK 64 #define PRACMP1C1_PRGEN_MASK 128 #define PRACMP1C1_PRGOS_MASK 31 #define PRACMP1C1_PRGOS_BITNUM 0 /*** PRACMP1C2 - PRACMP1 Control 2 Register; 0xFFFF8523 ***/ typedef union { byte Byte; struct { byte ACIPE0 :1; /* ACMP Input Pin 0 Enable - ACIPE0 is used to control the PRACMP external pin 0 as analog input */ byte ACIPE1 :1; /* ACMP Input Pin 1 Enable - ACIPE1 is used to control the PRACMP external pin 1 as analog input */ byte ACIPE2 :1; /* ACMP Input Pin 2 Enable - ACIPE2 is used to control the PRACMP external pin 2 as analog input */ byte ACIPE3 :1; /* ACMP Input Pin 3 Enable - ACIPE3 is used to control the PRACMP external pin 3 as analog input */ byte ACIPE4 :1; /* ACMP Input Pin 4 Enable - ACIPE4 is used to control the PRACMP external pin 4 as analog input */ byte ACIPE5 :1; /* ACMP Input Pin 5 Enable - ACIPE5 is used to control the PRACMP external pin 5 as analog input */ byte ACIPE6 :1; /* ACMP Input Pin 6 Enable - ACIPE6 is used to control the PRACMP external pin 6 as analog input */ byte :1; } Bits; struct { byte grpACIPE :7; byte :1; } MergedBits; } PRACMP1C2STR; extern volatile PRACMP1C2STR _PRACMP1C2 @0xFFFF8523; #define PRACMP1C2 _PRACMP1C2.Byte #define PRACMP1C2_ACIPE0 _PRACMP1C2.Bits.ACIPE0 #define PRACMP1C2_ACIPE1 _PRACMP1C2.Bits.ACIPE1 #define PRACMP1C2_ACIPE2 _PRACMP1C2.Bits.ACIPE2 #define PRACMP1C2_ACIPE3 _PRACMP1C2.Bits.ACIPE3 #define PRACMP1C2_ACIPE4 _PRACMP1C2.Bits.ACIPE4 #define PRACMP1C2_ACIPE5 _PRACMP1C2.Bits.ACIPE5 #define PRACMP1C2_ACIPE6 _PRACMP1C2.Bits.ACIPE6 #define PRACMP1C2_ACIPE _PRACMP1C2.MergedBits.grpACIPE #define PRACMP1C2_ACIPE0_MASK 1 #define PRACMP1C2_ACIPE1_MASK 2 #define PRACMP1C2_ACIPE2_MASK 4 #define PRACMP1C2_ACIPE3_MASK 8 #define PRACMP1C2_ACIPE4_MASK 16 #define PRACMP1C2_ACIPE5_MASK 32 #define PRACMP1C2_ACIPE6_MASK 64 #define PRACMP1C2_ACIPE_MASK 127 #define PRACMP1C2_ACIPE_BITNUM 0 /*** PRACMP2CS - PRACMP2 Control and Status Register; 0xFFFF8540 ***/ typedef union { byte Byte; struct { byte ACIEN :1; /* ACMP Interrupt Enable */ byte ACINTS0 :1; /* ACMP Interrupt Select, bit 0 */ byte ACINTS1 :1; /* ACMP Interrupt Select, bit 1 */ byte ACMPO :1; /* ACMP Output Bit */ byte ACOPE :1; /* ACMP Output Pin Enable */ byte :1; byte ACMPF :1; /* ACMP Interrupt Flag */ byte ACEN :1; /* ACMP Module Enable */ } Bits; struct { byte :1; byte grpACINTS :2; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } PRACMP2CSSTR; extern volatile PRACMP2CSSTR _PRACMP2CS @0xFFFF8540; #define PRACMP2CS _PRACMP2CS.Byte #define PRACMP2CS_ACIEN _PRACMP2CS.Bits.ACIEN #define PRACMP2CS_ACINTS0 _PRACMP2CS.Bits.ACINTS0 #define PRACMP2CS_ACINTS1 _PRACMP2CS.Bits.ACINTS1 #define PRACMP2CS_ACMPO _PRACMP2CS.Bits.ACMPO #define PRACMP2CS_ACOPE _PRACMP2CS.Bits.ACOPE #define PRACMP2CS_ACMPF _PRACMP2CS.Bits.ACMPF #define PRACMP2CS_ACEN _PRACMP2CS.Bits.ACEN #define PRACMP2CS_ACINTS _PRACMP2CS.MergedBits.grpACINTS #define PRACMP2CS_ACIEN_MASK 1 #define PRACMP2CS_ACINTS0_MASK 2 #define PRACMP2CS_ACINTS1_MASK 4 #define PRACMP2CS_ACMPO_MASK 8 #define PRACMP2CS_ACOPE_MASK 16 #define PRACMP2CS_ACMPF_MASK 64 #define PRACMP2CS_ACEN_MASK 128 #define PRACMP2CS_ACINTS_MASK 6 #define PRACMP2CS_ACINTS_BITNUM 1 /*** PRACMP2C0 - PRACMP2 Control 0 Register; 0xFFFF8541 ***/ typedef union { byte Byte; struct { byte ACNSEL0 :1; /* ACMP Negative Input Select, bit 0 */ byte ACNSEL1 :1; /* ACMP Negative Input Select, bit 1 */ byte ACNSEL2 :1; /* ACMP Negative Input Select, bit 2 */ byte :1; byte ACPSEL0 :1; /* ACMP Positive Input Select, bit 0 */ byte ACPSEL1 :1; /* ACMP Positive Input Select, bit 1 */ byte ACPSEL2 :1; /* ACMP Positive Input Select, bit 2 */ byte :1; } Bits; struct { byte grpACNSEL :3; byte :1; byte grpACPSEL :3; byte :1; } MergedBits; } PRACMP2C0STR; extern volatile PRACMP2C0STR _PRACMP2C0 @0xFFFF8541; #define PRACMP2C0 _PRACMP2C0.Byte #define PRACMP2C0_ACNSEL0 _PRACMP2C0.Bits.ACNSEL0 #define PRACMP2C0_ACNSEL1 _PRACMP2C0.Bits.ACNSEL1 #define PRACMP2C0_ACNSEL2 _PRACMP2C0.Bits.ACNSEL2 #define PRACMP2C0_ACPSEL0 _PRACMP2C0.Bits.ACPSEL0 #define PRACMP2C0_ACPSEL1 _PRACMP2C0.Bits.ACPSEL1 #define PRACMP2C0_ACPSEL2 _PRACMP2C0.Bits.ACPSEL2 /* PRACMP2C_ARR: Access 3 PRACMP2Cx registers in an array */ #define PRACMP2C_ARR ((volatile byte *) &PRACMP2C0) #define PRACMP2C0_ACNSEL _PRACMP2C0.MergedBits.grpACNSEL #define PRACMP2C0_ACPSEL _PRACMP2C0.MergedBits.grpACPSEL #define PRACMP2C0_ACNSEL0_MASK 1 #define PRACMP2C0_ACNSEL1_MASK 2 #define PRACMP2C0_ACNSEL2_MASK 4 #define PRACMP2C0_ACPSEL0_MASK 16 #define PRACMP2C0_ACPSEL1_MASK 32 #define PRACMP2C0_ACPSEL2_MASK 64 #define PRACMP2C0_ACNSEL_MASK 7 #define PRACMP2C0_ACNSEL_BITNUM 0 #define PRACMP2C0_ACPSEL_MASK 112 #define PRACMP2C0_ACPSEL_BITNUM 4 /*** PRACMP2C1 - PRACMP2 Control 1 Register; 0xFFFF8542 ***/ typedef union { byte Byte; struct { byte PRGOS0 :1; /* Programmable Reference Generator Output Selection, bit 0 */ byte PRGOS1 :1; /* Programmable Reference Generator Output Selection, bit 1 */ byte PRGOS2 :1; /* Programmable Reference Generator Output Selection, bit 2 */ byte PRGOS3 :1; /* Programmable Reference Generator Output Selection, bit 3 */ byte PRGOS4 :1; /* Programmable Reference Generator Output Selection, bit 4 */ byte :1; byte PRGINS :1; /* Programmable Reference Generator Input Selection */ byte PRGEN :1; /* Programmable Reference Generator Enable */ } Bits; struct { byte grpPRGOS :5; byte :1; byte :1; byte :1; } MergedBits; } PRACMP2C1STR; extern volatile PRACMP2C1STR _PRACMP2C1 @0xFFFF8542; #define PRACMP2C1 _PRACMP2C1.Byte #define PRACMP2C1_PRGOS0 _PRACMP2C1.Bits.PRGOS0 #define PRACMP2C1_PRGOS1 _PRACMP2C1.Bits.PRGOS1 #define PRACMP2C1_PRGOS2 _PRACMP2C1.Bits.PRGOS2 #define PRACMP2C1_PRGOS3 _PRACMP2C1.Bits.PRGOS3 #define PRACMP2C1_PRGOS4 _PRACMP2C1.Bits.PRGOS4 #define PRACMP2C1_PRGINS _PRACMP2C1.Bits.PRGINS #define PRACMP2C1_PRGEN _PRACMP2C1.Bits.PRGEN #define PRACMP2C1_PRGOS _PRACMP2C1.MergedBits.grpPRGOS #define PRACMP2C1_PRGOS0_MASK 1 #define PRACMP2C1_PRGOS1_MASK 2 #define PRACMP2C1_PRGOS2_MASK 4 #define PRACMP2C1_PRGOS3_MASK 8 #define PRACMP2C1_PRGOS4_MASK 16 #define PRACMP2C1_PRGINS_MASK 64 #define PRACMP2C1_PRGEN_MASK 128 #define PRACMP2C1_PRGOS_MASK 31 #define PRACMP2C1_PRGOS_BITNUM 0 /*** PRACMP2C2 - PRACMP2 Control 2 Register; 0xFFFF8543 ***/ typedef union { byte Byte; struct { byte ACIPE0 :1; /* ACMP Input Pin 0 Enable - ACIPE0 is used to control the PRACMP external pin 0 as analog input */ byte ACIPE1 :1; /* ACMP Input Pin 1 Enable - ACIPE1 is used to control the PRACMP external pin 1 as analog input */ byte ACIPE2 :1; /* ACMP Input Pin 2 Enable - ACIPE2 is used to control the PRACMP external pin 2 as analog input */ byte ACIPE3 :1; /* ACMP Input Pin 3 Enable - ACIPE3 is used to control the PRACMP external pin 3 as analog input */ byte ACIPE4 :1; /* ACMP Input Pin 4 Enable - ACIPE4 is used to control the PRACMP external pin 4 as analog input */ byte ACIPE5 :1; /* ACMP Input Pin 5 Enable - ACIPE5 is used to control the PRACMP external pin 5 as analog input */ byte ACIPE6 :1; /* ACMP Input Pin 6 Enable - ACIPE6 is used to control the PRACMP external pin 6 as analog input */ byte :1; } Bits; struct { byte grpACIPE :7; byte :1; } MergedBits; } PRACMP2C2STR; extern volatile PRACMP2C2STR _PRACMP2C2 @0xFFFF8543; #define PRACMP2C2 _PRACMP2C2.Byte #define PRACMP2C2_ACIPE0 _PRACMP2C2.Bits.ACIPE0 #define PRACMP2C2_ACIPE1 _PRACMP2C2.Bits.ACIPE1 #define PRACMP2C2_ACIPE2 _PRACMP2C2.Bits.ACIPE2 #define PRACMP2C2_ACIPE3 _PRACMP2C2.Bits.ACIPE3 #define PRACMP2C2_ACIPE4 _PRACMP2C2.Bits.ACIPE4 #define PRACMP2C2_ACIPE5 _PRACMP2C2.Bits.ACIPE5 #define PRACMP2C2_ACIPE6 _PRACMP2C2.Bits.ACIPE6 #define PRACMP2C2_ACIPE _PRACMP2C2.MergedBits.grpACIPE #define PRACMP2C2_ACIPE0_MASK 1 #define PRACMP2C2_ACIPE1_MASK 2 #define PRACMP2C2_ACIPE2_MASK 4 #define PRACMP2C2_ACIPE3_MASK 8 #define PRACMP2C2_ACIPE4_MASK 16 #define PRACMP2C2_ACIPE5_MASK 32 #define PRACMP2C2_ACIPE6_MASK 64 #define PRACMP2C2_ACIPE_MASK 127 #define PRACMP2C2_ACIPE_BITNUM 0 /*** MTIM1SC - MTIM Clock Configuration Register; 0xFFFF8560 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte TSTP :1; /* MTIM Counter Stop */ byte TRST :1; /* MTIM Counter Reset */ byte TOIE :1; /* MTIM Overflow Interrupt Enable */ byte TOF :1; /* MTIM Overflow Flag */ } Bits; } MTIM1SCSTR; extern volatile MTIM1SCSTR _MTIM1SC @0xFFFF8560; #define MTIM1SC _MTIM1SC.Byte #define MTIM1SC_TSTP _MTIM1SC.Bits.TSTP #define MTIM1SC_TRST _MTIM1SC.Bits.TRST #define MTIM1SC_TOIE _MTIM1SC.Bits.TOIE #define MTIM1SC_TOF _MTIM1SC.Bits.TOF #define MTIM1SC_TSTP_MASK 16 #define MTIM1SC_TRST_MASK 32 #define MTIM1SC_TOIE_MASK 64 #define MTIM1SC_TOF_MASK 128 /*** MTIM1CLK - MTIM Clock Configuration Register; 0xFFFF8561 ***/ typedef union { byte Byte; struct { byte PS0 :1; /* Clock source Prescaler Bit 0 */ byte PS1 :1; /* Clock source Prescaler Bit 1 */ byte PS2 :1; /* Clock source Prescaler Bit 2 */ byte PS3 :1; /* Clock source Prescaler Bit 3 */ byte CLKS0 :1; /* Clock source Select Bit 0 */ byte CLKS1 :1; /* Clock source Select Bit 1 */ byte :1; byte :1; } Bits; struct { byte grpPS :4; byte grpCLKS :2; byte :1; byte :1; } MergedBits; } MTIM1CLKSTR; extern volatile MTIM1CLKSTR _MTIM1CLK @0xFFFF8561; #define MTIM1CLK _MTIM1CLK.Byte #define MTIM1CLK_PS0 _MTIM1CLK.Bits.PS0 #define MTIM1CLK_PS1 _MTIM1CLK.Bits.PS1 #define MTIM1CLK_PS2 _MTIM1CLK.Bits.PS2 #define MTIM1CLK_PS3 _MTIM1CLK.Bits.PS3 #define MTIM1CLK_CLKS0 _MTIM1CLK.Bits.CLKS0 #define MTIM1CLK_CLKS1 _MTIM1CLK.Bits.CLKS1 #define MTIM1CLK_PS _MTIM1CLK.MergedBits.grpPS #define MTIM1CLK_CLKS _MTIM1CLK.MergedBits.grpCLKS #define MTIM1CLK_PS0_MASK 1 #define MTIM1CLK_PS1_MASK 2 #define MTIM1CLK_PS2_MASK 4 #define MTIM1CLK_PS3_MASK 8 #define MTIM1CLK_CLKS0_MASK 16 #define MTIM1CLK_CLKS1_MASK 32 #define MTIM1CLK_PS_MASK 15 #define MTIM1CLK_PS_BITNUM 0 #define MTIM1CLK_CLKS_MASK 48 #define MTIM1CLK_CLKS_BITNUM 4 /*** MTIM1CNT - MTIM Counter Register; 0xFFFF8562 ***/ typedef union { byte Byte; } MTIM1CNTSTR; extern volatile MTIM1CNTSTR _MTIM1CNT @0xFFFF8562; #define MTIM1CNT _MTIM1CNT.Byte /*** MTIM1MOD - MTIM Modulo Register; 0xFFFF8563 ***/ typedef union { byte Byte; } MTIM1MODSTR; extern volatile MTIM1MODSTR _MTIM1MOD @0xFFFF8563; #define MTIM1MOD _MTIM1MOD.Byte /*** MTIM2SC - MTIM Clock Configuration Register; 0xFFFF8580 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte TSTP :1; /* MTIM Counter Stop */ byte TRST :1; /* MTIM Counter Reset */ byte TOIE :1; /* MTIM Overflow Interrupt Enable */ byte TOF :1; /* MTIM Overflow Flag */ } Bits; } MTIM2SCSTR; extern volatile MTIM2SCSTR _MTIM2SC @0xFFFF8580; #define MTIM2SC _MTIM2SC.Byte #define MTIM2SC_TSTP _MTIM2SC.Bits.TSTP #define MTIM2SC_TRST _MTIM2SC.Bits.TRST #define MTIM2SC_TOIE _MTIM2SC.Bits.TOIE #define MTIM2SC_TOF _MTIM2SC.Bits.TOF #define MTIM2SC_TSTP_MASK 16 #define MTIM2SC_TRST_MASK 32 #define MTIM2SC_TOIE_MASK 64 #define MTIM2SC_TOF_MASK 128 /*** MTIM2CLK - MTIM Clock Configuration Register; 0xFFFF8581 ***/ typedef union { byte Byte; struct { byte PS0 :1; /* Clock source Prescaler Bit 0 */ byte PS1 :1; /* Clock source Prescaler Bit 1 */ byte PS2 :1; /* Clock source Prescaler Bit 2 */ byte PS3 :1; /* Clock source Prescaler Bit 3 */ byte CLKS0 :1; /* Clock source Select Bit 0 */ byte CLKS1 :1; /* Clock source Select Bit 1 */ byte :1; byte :1; } Bits; struct { byte grpPS :4; byte grpCLKS :2; byte :1; byte :1; } MergedBits; } MTIM2CLKSTR; extern volatile MTIM2CLKSTR _MTIM2CLK @0xFFFF8581; #define MTIM2CLK _MTIM2CLK.Byte #define MTIM2CLK_PS0 _MTIM2CLK.Bits.PS0 #define MTIM2CLK_PS1 _MTIM2CLK.Bits.PS1 #define MTIM2CLK_PS2 _MTIM2CLK.Bits.PS2 #define MTIM2CLK_PS3 _MTIM2CLK.Bits.PS3 #define MTIM2CLK_CLKS0 _MTIM2CLK.Bits.CLKS0 #define MTIM2CLK_CLKS1 _MTIM2CLK.Bits.CLKS1 #define MTIM2CLK_PS _MTIM2CLK.MergedBits.grpPS #define MTIM2CLK_CLKS _MTIM2CLK.MergedBits.grpCLKS #define MTIM2CLK_PS0_MASK 1 #define MTIM2CLK_PS1_MASK 2 #define MTIM2CLK_PS2_MASK 4 #define MTIM2CLK_PS3_MASK 8 #define MTIM2CLK_CLKS0_MASK 16 #define MTIM2CLK_CLKS1_MASK 32 #define MTIM2CLK_PS_MASK 15 #define MTIM2CLK_PS_BITNUM 0 #define MTIM2CLK_CLKS_MASK 48 #define MTIM2CLK_CLKS_BITNUM 4 /*** MTIM2CNT - MTIM Counter Register; 0xFFFF8582 ***/ typedef union { byte Byte; } MTIM2CNTSTR; extern volatile MTIM2CNTSTR _MTIM2CNT @0xFFFF8582; #define MTIM2CNT _MTIM2CNT.Byte /*** MTIM2MOD - MTIM Modulo Register; 0xFFFF8583 ***/ typedef union { byte Byte; } MTIM2MODSTR; extern volatile MTIM2MODSTR _MTIM2MOD @0xFFFF8583; #define MTIM2MOD _MTIM2MOD.Byte /*** MTIM3SC - MTIM16 Status and Control Register; 0xFFFF85A0 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte TSTP :1; /* MTIM16 Counter Stop */ byte TRST :1; /* MTIM16 Counter Reset */ byte TOIE :1; /* MTIM16 Overflow Interrupt Enable */ byte TOF :1; /* MTIM16 Overflow Flag */ } Bits; } MTIM3SCSTR; extern volatile MTIM3SCSTR _MTIM3SC @0xFFFF85A0; #define MTIM3SC _MTIM3SC.Byte #define MTIM3SC_TSTP _MTIM3SC.Bits.TSTP #define MTIM3SC_TRST _MTIM3SC.Bits.TRST #define MTIM3SC_TOIE _MTIM3SC.Bits.TOIE #define MTIM3SC_TOF _MTIM3SC.Bits.TOF #define MTIM3SC_TSTP_MASK 16 #define MTIM3SC_TRST_MASK 32 #define MTIM3SC_TOIE_MASK 64 #define MTIM3SC_TOF_MASK 128 /*** MTIM3CLK - MTIM16 Clock Configuration Register; 0xFFFF85A1 ***/ typedef union { byte Byte; struct { byte PS0 :1; /* Clock source Prescaler Bit 0 */ byte PS1 :1; /* Clock source Prescaler Bit 1 */ byte PS2 :1; /* Clock source Prescaler Bit 2 */ byte PS3 :1; /* Clock source Prescaler Bit 3 */ byte CLKS0 :1; /* Clock source Select Bit 0 */ byte CLKS1 :1; /* Clock source Select Bit 1 */ byte :1; byte :1; } Bits; struct { byte grpPS :4; byte grpCLKS :2; byte :1; byte :1; } MergedBits; } MTIM3CLKSTR; extern volatile MTIM3CLKSTR _MTIM3CLK @0xFFFF85A1; #define MTIM3CLK _MTIM3CLK.Byte #define MTIM3CLK_PS0 _MTIM3CLK.Bits.PS0 #define MTIM3CLK_PS1 _MTIM3CLK.Bits.PS1 #define MTIM3CLK_PS2 _MTIM3CLK.Bits.PS2 #define MTIM3CLK_PS3 _MTIM3CLK.Bits.PS3 #define MTIM3CLK_CLKS0 _MTIM3CLK.Bits.CLKS0 #define MTIM3CLK_CLKS1 _MTIM3CLK.Bits.CLKS1 #define MTIM3CLK_PS _MTIM3CLK.MergedBits.grpPS #define MTIM3CLK_CLKS _MTIM3CLK.MergedBits.grpCLKS #define MTIM3CLK_PS0_MASK 1 #define MTIM3CLK_PS1_MASK 2 #define MTIM3CLK_PS2_MASK 4 #define MTIM3CLK_PS3_MASK 8 #define MTIM3CLK_CLKS0_MASK 16 #define MTIM3CLK_CLKS1_MASK 32 #define MTIM3CLK_PS_MASK 15 #define MTIM3CLK_PS_BITNUM 0 #define MTIM3CLK_CLKS_MASK 48 #define MTIM3CLK_CLKS_BITNUM 4 /*** MTIM3CNT - MTIM16 Counter Register; 0xFFFF85A2 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** MTIM3CNTH - MTIM16 Counter Register High; 0xFFFF85A2 ***/ union { byte Byte; } MTIM3CNTHSTR; #define MTIM3CNTH _MTIM3CNT.Overlap_STR.MTIM3CNTHSTR.Byte /*** MTIM3CNTL - MTIM16 Counter Register Low; 0xFFFF85A3 ***/ union { byte Byte; } MTIM3CNTLSTR; #define MTIM3CNTL _MTIM3CNT.Overlap_STR.MTIM3CNTLSTR.Byte } Overlap_STR; } MTIM3CNTSTR; extern volatile MTIM3CNTSTR _MTIM3CNT @0xFFFF85A2; #define MTIM3CNT _MTIM3CNT.Word /*** MTIM3MOD - MTIM16 Modulo Register; 0xFFFF85A4 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** MTIM3MODH - MTIM16 Modulo Register High; 0xFFFF85A4 ***/ union { byte Byte; } MTIM3MODHSTR; #define MTIM3MODH _MTIM3MOD.Overlap_STR.MTIM3MODHSTR.Byte /*** MTIM3MODL - MTIM16 Modulo Register Low; 0xFFFF85A5 ***/ union { byte Byte; } MTIM3MODLSTR; #define MTIM3MODL _MTIM3MOD.Overlap_STR.MTIM3MODLSTR.Byte } Overlap_STR; } MTIM3MODSTR; extern volatile MTIM3MODSTR _MTIM3MOD @0xFFFF85A4; #define MTIM3MOD _MTIM3MOD.Word /*** CRCH - CRC High Register; 0xFFFF85C0 ***/ typedef union { byte Byte; struct { byte BIT8 :1; /* High byte of CRC register ,bit 8 */ byte BIT9 :1; /* High byte of CRC register ,bit 9 */ byte BIT10 :1; /* High byte of CRC register ,bit 10 */ byte BIT11 :1; /* High byte of CRC register ,bit 11 */ byte BIT12 :1; /* High byte of CRC register ,bit 12 */ byte BIT13 :1; /* High byte of CRC register ,bit 13 */ byte BIT14 :1; /* High byte of CRC register ,bit 14 */ byte BIT15 :1; /* High byte of CRC register ,bit 15 */ } Bits; } CRCHSTR; extern volatile CRCHSTR _CRCH @0xFFFF85C0; #define CRCH _CRCH.Byte #define CRCH_BIT8 _CRCH.Bits.BIT8 #define CRCH_BIT9 _CRCH.Bits.BIT9 #define CRCH_BIT10 _CRCH.Bits.BIT10 #define CRCH_BIT11 _CRCH.Bits.BIT11 #define CRCH_BIT12 _CRCH.Bits.BIT12 #define CRCH_BIT13 _CRCH.Bits.BIT13 #define CRCH_BIT14 _CRCH.Bits.BIT14 #define CRCH_BIT15 _CRCH.Bits.BIT15 #define CRCH_BIT8_MASK 1 #define CRCH_BIT9_MASK 2 #define CRCH_BIT10_MASK 4 #define CRCH_BIT11_MASK 8 #define CRCH_BIT12_MASK 16 #define CRCH_BIT13_MASK 32 #define CRCH_BIT14_MASK 64 #define CRCH_BIT15_MASK 128 /*** CRCL - CRC Low Register; 0xFFFF85C1 ***/ typedef union { byte Byte; struct { byte BIT0 :1; /* Low byte of CRC register, bit 0 */ byte BIT1 :1; /* Low byte of CRC register, bit 1 */ byte BIT2 :1; /* Low byte of CRC register, bit 2 */ byte BIT3 :1; /* Low byte of CRC register, bit 3 */ byte BIT4 :1; /* Low byte of CRC register, bit 4 */ byte BIT5 :1; /* Low byte of CRC register, bit 5 */ byte BIT6 :1; /* Low byte of CRC register, bit 6 */ byte BIT7 :1; /* Low byte of CRC register, bit 7 */ } Bits; } CRCLSTR; extern volatile CRCLSTR _CRCL @0xFFFF85C1; #define CRCL _CRCL.Byte #define CRCL_BIT0 _CRCL.Bits.BIT0 #define CRCL_BIT1 _CRCL.Bits.BIT1 #define CRCL_BIT2 _CRCL.Bits.BIT2 #define CRCL_BIT3 _CRCL.Bits.BIT3 #define CRCL_BIT4 _CRCL.Bits.BIT4 #define CRCL_BIT5 _CRCL.Bits.BIT5 #define CRCL_BIT6 _CRCL.Bits.BIT6 #define CRCL_BIT7 _CRCL.Bits.BIT7 #define CRCL_BIT0_MASK 1 #define CRCL_BIT1_MASK 2 #define CRCL_BIT2_MASK 4 #define CRCL_BIT3_MASK 8 #define CRCL_BIT4_MASK 16 #define CRCL_BIT5_MASK 32 #define CRCL_BIT6_MASK 64 #define CRCL_BIT7_MASK 128 /*** TRANSPOSE - CRC Transpose Register; 0xFFFF85C2 ***/ typedef union { byte Byte; struct { byte BIT0 :1; /* CRC transpose register, bit 0 */ byte BIT1 :1; /* CRC transpose register, bit 1 */ byte BIT2 :1; /* CRC transpose register, bit 2 */ byte BIT3 :1; /* CRC transpose register, bit 3 */ byte BIT4 :1; /* CRC transpose register, bit 4 */ byte BIT5 :1; /* CRC transpose register, bit 5 */ byte BIT6 :1; /* CRC transpose register, bit 6 */ byte BIT7 :1; /* CRC transpose register, bit 7 */ } Bits; } TRANSPOSESTR; extern volatile TRANSPOSESTR _TRANSPOSE @0xFFFF85C2; #define TRANSPOSE _TRANSPOSE.Byte #define TRANSPOSE_BIT0 _TRANSPOSE.Bits.BIT0 #define TRANSPOSE_BIT1 _TRANSPOSE.Bits.BIT1 #define TRANSPOSE_BIT2 _TRANSPOSE.Bits.BIT2 #define TRANSPOSE_BIT3 _TRANSPOSE.Bits.BIT3 #define TRANSPOSE_BIT4 _TRANSPOSE.Bits.BIT4 #define TRANSPOSE_BIT5 _TRANSPOSE.Bits.BIT5 #define TRANSPOSE_BIT6 _TRANSPOSE.Bits.BIT6 #define TRANSPOSE_BIT7 _TRANSPOSE.Bits.BIT7 #define TRANSPOSE_BIT0_MASK 1 #define TRANSPOSE_BIT1_MASK 2 #define TRANSPOSE_BIT2_MASK 4 #define TRANSPOSE_BIT3_MASK 8 #define TRANSPOSE_BIT4_MASK 16 #define TRANSPOSE_BIT5_MASK 32 #define TRANSPOSE_BIT6_MASK 64 #define TRANSPOSE_BIT7_MASK 128 /*** TPMSC - TPM Status and Control Register; 0xFFFF8600 ***/ typedef union { byte Byte; struct { byte PS0 :1; /* Prescale Divisor Select Bit 0 */ byte PS1 :1; /* Prescale Divisor Select Bit 1 */ byte PS2 :1; /* Prescale Divisor Select Bit 2 */ byte CLKSA :1; /* Clock Source Select A */ byte CLKSB :1; /* Clock Source Select B */ byte CPWMS :1; /* Center-Aligned PWM Select */ byte TOIE :1; /* Timer Overflow Interrupt Enable */ byte TOF :1; /* Timer Overflow Flag */ } Bits; struct { byte grpPS :3; byte grpCLKSx :2; byte :1; byte :1; byte :1; } MergedBits; } TPMSCSTR; extern volatile TPMSCSTR _TPMSC @0xFFFF8600; #define TPMSC _TPMSC.Byte #define TPMSC_PS0 _TPMSC.Bits.PS0 #define TPMSC_PS1 _TPMSC.Bits.PS1 #define TPMSC_PS2 _TPMSC.Bits.PS2 #define TPMSC_CLKSA _TPMSC.Bits.CLKSA #define TPMSC_CLKSB _TPMSC.Bits.CLKSB #define TPMSC_CPWMS _TPMSC.Bits.CPWMS #define TPMSC_TOIE _TPMSC.Bits.TOIE #define TPMSC_TOF _TPMSC.Bits.TOF #define TPMSC_PS _TPMSC.MergedBits.grpPS #define TPMSC_CLKSx _TPMSC.MergedBits.grpCLKSx #define TPMSC_PS0_MASK 1 #define TPMSC_PS1_MASK 2 #define TPMSC_PS2_MASK 4 #define TPMSC_CLKSA_MASK 8 #define TPMSC_CLKSB_MASK 16 #define TPMSC_CPWMS_MASK 32 #define TPMSC_TOIE_MASK 64 #define TPMSC_TOF_MASK 128 #define TPMSC_PS_MASK 7 #define TPMSC_PS_BITNUM 0 #define TPMSC_CLKSx_MASK 24 #define TPMSC_CLKSx_BITNUM 3 /*** TPMCNT - TPM Timer Counter Register; 0xFFFF8601 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TPMCNTH - TPM Timer Counter Register High; 0xFFFF8601 ***/ union { byte Byte; } TPMCNTHSTR; #define TPMCNTH _TPMCNT.Overlap_STR.TPMCNTHSTR.Byte /*** TPMCNTL - TPM Timer Counter Register Low; 0xFFFF8602 ***/ union { byte Byte; } TPMCNTLSTR; #define TPMCNTL _TPMCNT.Overlap_STR.TPMCNTLSTR.Byte } Overlap_STR; } TPMCNTSTR; extern volatile TPMCNTSTR _TPMCNT @0xFFFF8601; #define TPMCNT _TPMCNT.Word /*** TPMMOD - TPM Timer Counter Modulo Register; 0xFFFF8603 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TPMMODH - TPM Timer Counter Modulo Register High; 0xFFFF8603 ***/ union { byte Byte; } TPMMODHSTR; #define TPMMODH _TPMMOD.Overlap_STR.TPMMODHSTR.Byte /*** TPMMODL - TPM Timer Counter Modulo Register Low; 0xFFFF8604 ***/ union { byte Byte; } TPMMODLSTR; #define TPMMODL _TPMMOD.Overlap_STR.TPMMODLSTR.Byte } Overlap_STR; } TPMMODSTR; extern volatile TPMMODSTR _TPMMOD @0xFFFF8603; #define TPMMOD _TPMMOD.Word /*** TPMC0SC - TPM Timer Channel 0 Status and Control Register; 0xFFFF8605 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte ELS0A :1; /* Edge/Level Select Bit A */ byte ELS0B :1; /* Edge/Level Select Bit B */ byte MS0A :1; /* Mode Select A for TPM Channel 0 */ byte MS0B :1; /* Mode Select B for TPM Channel 0 */ byte CH0IE :1; /* Channel 0 Interrupt Enable */ byte CH0F :1; /* Channel 0 Flag */ } Bits; struct { byte :1; byte :1; byte grpELS0x :2; byte grpMS0x :2; byte :1; byte :1; } MergedBits; } TPMC0SCSTR; extern volatile TPMC0SCSTR _TPMC0SC @0xFFFF8605; #define TPMC0SC _TPMC0SC.Byte #define TPMC0SC_ELS0A _TPMC0SC.Bits.ELS0A #define TPMC0SC_ELS0B _TPMC0SC.Bits.ELS0B #define TPMC0SC_MS0A _TPMC0SC.Bits.MS0A #define TPMC0SC_MS0B _TPMC0SC.Bits.MS0B #define TPMC0SC_CH0IE _TPMC0SC.Bits.CH0IE #define TPMC0SC_CH0F _TPMC0SC.Bits.CH0F #define TPMC0SC_ELS0x _TPMC0SC.MergedBits.grpELS0x #define TPMC0SC_MS0x _TPMC0SC.MergedBits.grpMS0x #define TPMC0SC_ELS0A_MASK 4 #define TPMC0SC_ELS0B_MASK 8 #define TPMC0SC_MS0A_MASK 16 #define TPMC0SC_MS0B_MASK 32 #define TPMC0SC_CH0IE_MASK 64 #define TPMC0SC_CH0F_MASK 128 #define TPMC0SC_ELS0x_MASK 12 #define TPMC0SC_ELS0x_BITNUM 2 #define TPMC0SC_MS0x_MASK 48 #define TPMC0SC_MS0x_BITNUM 4 /*** TPMC0V - TPM Timer Channel 0 Value Register; 0xFFFF8606 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TPMC0VH - TPM Timer Channel 0 Value Register High; 0xFFFF8606 ***/ union { byte Byte; } TPMC0VHSTR; #define TPMC0VH _TPMC0V.Overlap_STR.TPMC0VHSTR.Byte /*** TPMC0VL - TPM Timer Channel 0 Value Register Low; 0xFFFF8607 ***/ union { byte Byte; } TPMC0VLSTR; #define TPMC0VL _TPMC0V.Overlap_STR.TPMC0VLSTR.Byte } Overlap_STR; } TPMC0VSTR; extern volatile TPMC0VSTR _TPMC0V @0xFFFF8606; #define TPMC0V _TPMC0V.Word /*** TPMC1SC - TPM Timer Channel 1 Status and Control Register; 0xFFFF8608 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte ELS1A :1; /* Edge/Level Select Bit A */ byte ELS1B :1; /* Edge/Level Select Bit B */ byte MS1A :1; /* Mode Select A for TPM Channel 1 */ byte MS1B :1; /* Mode Select B for TPM Channel 1 */ byte CH1IE :1; /* Channel 1 Interrupt Enable */ byte CH1F :1; /* Channel 1 Flag */ } Bits; struct { byte :1; byte :1; byte grpELS1x :2; byte grpMS1x :2; byte :1; byte :1; } MergedBits; } TPMC1SCSTR; extern volatile TPMC1SCSTR _TPMC1SC @0xFFFF8608; #define TPMC1SC _TPMC1SC.Byte #define TPMC1SC_ELS1A _TPMC1SC.Bits.ELS1A #define TPMC1SC_ELS1B _TPMC1SC.Bits.ELS1B #define TPMC1SC_MS1A _TPMC1SC.Bits.MS1A #define TPMC1SC_MS1B _TPMC1SC.Bits.MS1B #define TPMC1SC_CH1IE _TPMC1SC.Bits.CH1IE #define TPMC1SC_CH1F _TPMC1SC.Bits.CH1F #define TPMC1SC_ELS1x _TPMC1SC.MergedBits.grpELS1x #define TPMC1SC_MS1x _TPMC1SC.MergedBits.grpMS1x #define TPMC1SC_ELS1A_MASK 4 #define TPMC1SC_ELS1B_MASK 8 #define TPMC1SC_MS1A_MASK 16 #define TPMC1SC_MS1B_MASK 32 #define TPMC1SC_CH1IE_MASK 64 #define TPMC1SC_CH1F_MASK 128 #define TPMC1SC_ELS1x_MASK 12 #define TPMC1SC_ELS1x_BITNUM 2 #define TPMC1SC_MS1x_MASK 48 #define TPMC1SC_MS1x_BITNUM 4 /*** TPMC1V - TPM Timer Channel 1 Value Register; 0xFFFF8609 ***/ typedef union { word Word; /* Overlapped registers: */ struct { /*** TPMC1VH - TPM Timer Channel 1 Value Register High; 0xFFFF8609 ***/ union { byte Byte; } TPMC1VHSTR; #define TPMC1VH _TPMC1V.Overlap_STR.TPMC1VHSTR.Byte /*** TPMC1VL - TPM Timer Channel 1 Value Register Low; 0xFFFF860A ***/ union { byte Byte; } TPMC1VLSTR; #define TPMC1VL _TPMC1V.Overlap_STR.TPMC1VLSTR.Byte } Overlap_STR; } TPMC1VSTR; extern volatile TPMC1VSTR _TPMC1V @0xFFFF8609; #define TPMC1V _TPMC1V.Word /*** IRTC_YEARMON_bcd - RTC Year and Month Counters Register (BCD format); 0xFFFF8640 ***/ typedef union { word Word; union { /* Several registers at the same address */ /*** IRTC_YEARMON_bcd - RTC Year and Month Counters Register (BCD format); Several registers at the same address ***/ union { struct { word MONTH_units0 :1; /* Month count value units bits, bit 0 */ word MONTH_units1 :1; /* Month count value units bits, bit 1 */ word MONTH_units2 :1; /* Month count value units bits, bit 2 */ word MONTH_units3 :1; /* Month count value units bits, bit 3 */ word MONTH_tens0 :1; /* Month count value tens bits, bit 0 */ word MONTH_tens1 :1; /* Month count value tens bits, bit 1 */ word MONTH_tens2 :1; /* Month count value tens bits, bit 2 */ word MONTH_tens3 :1; /* Month count value tens bits, bit 3 */ word YEAR0 :1; /* Year count value bits, bit 0 */ word YEAR1 :1; /* Year count value bits, bit 1 */ word YEAR2 :1; /* Year count value bits, bit 2 */ word YEAR3 :1; /* Year count value bits, bit 3 */ word YEAR4 :1; /* Year count value bits, bit 4 */ word YEAR5 :1; /* Year count value bits, bit 5 */ word YEAR6 :1; /* Year count value bits, bit 6 */ word YEAR7 :1; /* Year count value bits, bit 7 */ } Bits; struct { word grpMONTH_units :4; word grpMONTH_tens :4; word grpYEAR :8; } MergedBits; } IRTC_YEARMON_bcdSTR; #define IRTC_YEARMON_bcd _IRTC_YEARMON_bcd.Word #define IRTC_YEARMON_bcd_MONTH_units0 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_bcdSTR.Bits.MONTH_units0 #define IRTC_YEARMON_bcd_MONTH_units1 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_bcdSTR.Bits.MONTH_units1 #define IRTC_YEARMON_bcd_MONTH_units2 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_bcdSTR.Bits.MONTH_units2 #define IRTC_YEARMON_bcd_MONTH_units3 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_bcdSTR.Bits.MONTH_units3 #define IRTC_YEARMON_bcd_MONTH_tens0 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_bcdSTR.Bits.MONTH_tens0 #define IRTC_YEARMON_bcd_MONTH_tens1 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_bcdSTR.Bits.MONTH_tens1 #define IRTC_YEARMON_bcd_MONTH_tens2 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_bcdSTR.Bits.MONTH_tens2 #define IRTC_YEARMON_bcd_MONTH_tens3 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_bcdSTR.Bits.MONTH_tens3 #define IRTC_YEARMON_bcd_YEAR0 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_bcdSTR.Bits.YEAR0 #define IRTC_YEARMON_bcd_YEAR1 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_bcdSTR.Bits.YEAR1 #define IRTC_YEARMON_bcd_YEAR2 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_bcdSTR.Bits.YEAR2 #define IRTC_YEARMON_bcd_YEAR3 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_bcdSTR.Bits.YEAR3 #define IRTC_YEARMON_bcd_YEAR4 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_bcdSTR.Bits.YEAR4 #define IRTC_YEARMON_bcd_YEAR5 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_bcdSTR.Bits.YEAR5 #define IRTC_YEARMON_bcd_YEAR6 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_bcdSTR.Bits.YEAR6 #define IRTC_YEARMON_bcd_YEAR7 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_bcdSTR.Bits.YEAR7 #define IRTC_YEARMON_bcd_MONTH_units _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_bcdSTR.MergedBits.grpMONTH_units #define IRTC_YEARMON_bcd_MONTH_tens _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_bcdSTR.MergedBits.grpMONTH_tens #define IRTC_YEARMON_bcd_YEAR _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_bcdSTR.MergedBits.grpYEAR #define IRTC_YEARMON_bcd_MONTH_units0_MASK 1 #define IRTC_YEARMON_bcd_MONTH_units1_MASK 2 #define IRTC_YEARMON_bcd_MONTH_units2_MASK 4 #define IRTC_YEARMON_bcd_MONTH_units3_MASK 8 #define IRTC_YEARMON_bcd_MONTH_tens0_MASK 16 #define IRTC_YEARMON_bcd_MONTH_tens1_MASK 32 #define IRTC_YEARMON_bcd_MONTH_tens2_MASK 64 #define IRTC_YEARMON_bcd_MONTH_tens3_MASK 128 #define IRTC_YEARMON_bcd_YEAR0_MASK 256 #define IRTC_YEARMON_bcd_YEAR1_MASK 512 #define IRTC_YEARMON_bcd_YEAR2_MASK 1024 #define IRTC_YEARMON_bcd_YEAR3_MASK 2048 #define IRTC_YEARMON_bcd_YEAR4_MASK 4096 #define IRTC_YEARMON_bcd_YEAR5_MASK 8192 #define IRTC_YEARMON_bcd_YEAR6_MASK 16384 #define IRTC_YEARMON_bcd_YEAR7_MASK 32768 #define IRTC_YEARMON_bcd_MONTH_units_MASK 15 #define IRTC_YEARMON_bcd_MONTH_units_BITNUM 0 #define IRTC_YEARMON_bcd_MONTH_tens_MASK 240 #define IRTC_YEARMON_bcd_MONTH_tens_BITNUM 4 #define IRTC_YEARMON_bcd_YEAR_MASK 65280 #define IRTC_YEARMON_bcd_YEAR_BITNUM 8 /*** IRTC_YEARMON_bin - RTC Year and Month Counters Register (binary format); Several registers at the same address ***/ union { struct { word MONTH0 :1; /* Month count value bits, bit 0 */ word MONTH1 :1; /* Month count value bits, bit 1 */ word MONTH2 :1; /* Month count value bits, bit 2 */ word MONTH3 :1; /* Month count value bits, bit 3 */ word :1; word :1; word :1; word :1; word YEAR0 :1; /* Year count value bits, bit 0 */ word YEAR1 :1; /* Year count value bits, bit 1 */ word YEAR2 :1; /* Year count value bits, bit 2 */ word YEAR3 :1; /* Year count value bits, bit 3 */ word YEAR4 :1; /* Year count value bits, bit 4 */ word YEAR5 :1; /* Year count value bits, bit 5 */ word YEAR6 :1; /* Year count value bits, bit 6 */ word YEAR7 :1; /* Year count value bits, bit 7 */ } Bits; struct { word grpMONTH :4; word :1; word :1; word :1; word :1; word grpYEAR :8; } MergedBits; } IRTC_YEARMON_binSTR; #define IRTC_YEARMON_bin _IRTC_YEARMON_bcd.Word #define IRTC_YEARMON_bin_MONTH0 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_binSTR.Bits.MONTH0 #define IRTC_YEARMON_bin_MONTH1 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_binSTR.Bits.MONTH1 #define IRTC_YEARMON_bin_MONTH2 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_binSTR.Bits.MONTH2 #define IRTC_YEARMON_bin_MONTH3 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_binSTR.Bits.MONTH3 #define IRTC_YEARMON_bin_YEAR0 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_binSTR.Bits.YEAR0 #define IRTC_YEARMON_bin_YEAR1 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_binSTR.Bits.YEAR1 #define IRTC_YEARMON_bin_YEAR2 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_binSTR.Bits.YEAR2 #define IRTC_YEARMON_bin_YEAR3 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_binSTR.Bits.YEAR3 #define IRTC_YEARMON_bin_YEAR4 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_binSTR.Bits.YEAR4 #define IRTC_YEARMON_bin_YEAR5 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_binSTR.Bits.YEAR5 #define IRTC_YEARMON_bin_YEAR6 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_binSTR.Bits.YEAR6 #define IRTC_YEARMON_bin_YEAR7 _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_binSTR.Bits.YEAR7 #define IRTC_YEARMON_bin_MONTH _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_binSTR.MergedBits.grpMONTH #define IRTC_YEARMON_bin_YEAR _IRTC_YEARMON_bcd.SameAddr_STR.IRTC_YEARMON_binSTR.MergedBits.grpYEAR #define IRTC_YEARMON_bin_MONTH0_MASK 1 #define IRTC_YEARMON_bin_MONTH1_MASK 2 #define IRTC_YEARMON_bin_MONTH2_MASK 4 #define IRTC_YEARMON_bin_MONTH3_MASK 8 #define IRTC_YEARMON_bin_YEAR0_MASK 256 #define IRTC_YEARMON_bin_YEAR1_MASK 512 #define IRTC_YEARMON_bin_YEAR2_MASK 1024 #define IRTC_YEARMON_bin_YEAR3_MASK 2048 #define IRTC_YEARMON_bin_YEAR4_MASK 4096 #define IRTC_YEARMON_bin_YEAR5_MASK 8192 #define IRTC_YEARMON_bin_YEAR6_MASK 16384 #define IRTC_YEARMON_bin_YEAR7_MASK 32768 #define IRTC_YEARMON_bin_MONTH_MASK 15 #define IRTC_YEARMON_bin_MONTH_BITNUM 0 #define IRTC_YEARMON_bin_YEAR_MASK 65280 #define IRTC_YEARMON_bin_YEAR_BITNUM 8 } SameAddr_STR; /*Several registers at the same address */ } IRTC_YEARMON_bcdSTR; extern volatile IRTC_YEARMON_bcdSTR _IRTC_YEARMON_bcd @0xFFFF8640; /*** IRTC_DAYS_bcd - RTC Days Counter Register (BCD format); 0xFFFF8642 ***/ typedef union { word Word; union { /* Several registers at the same address */ /*** IRTC_DAYS_bcd - RTC Days Counter Register (BCD format); Several registers at the same address ***/ union { struct { word DAYS_units0 :1; /* Day Setting - units. Indicates the current day count, bit 0 */ word DAYS_units1 :1; /* Day Setting - units. Indicates the current day count, bit 1 */ word DAYS_units2 :1; /* Day Setting - units. Indicates the current day count, bit 2 */ word DAYS_units3 :1; /* Day Setting - units. Indicates the current day count, bit 3 */ word DAYS_tens0 :1; /* Day Setting - tens. Indicates the current day count, bit 0 */ word DAYS_tens1 :1; /* Day Setting - tens. Indicates the current day count, bit 1 */ word DAYS_tens2 :1; /* Day Setting - tens. Indicates the current day count, bit 2 */ word DAYS_tens3 :1; /* Day Setting - tens. Indicates the current day count, bit 3 */ word DAY_OF_WEEK0 :1; /* Indicates the current day count, bit 0, bit 0 */ word DAY_OF_WEEK1 :1; /* Indicates the current day count, bit 0, bit 1 */ word DAY_OF_WEEK2 :1; /* Indicates the current day count, bit 0, bit 2 */ word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpDAYS_units :4; word grpDAYS_tens :4; word grpDAY_OF_WEEK :3; word :1; word :1; word :1; word :1; word :1; } MergedBits; } IRTC_DAYS_bcdSTR; #define IRTC_DAYS_bcd _IRTC_DAYS_bcd.Word #define IRTC_DAYS_bcd_DAYS_units0 _IRTC_DAYS_bcd.SameAddr_STR.IRTC_DAYS_bcdSTR.Bits.DAYS_units0 #define IRTC_DAYS_bcd_DAYS_units1 _IRTC_DAYS_bcd.SameAddr_STR.IRTC_DAYS_bcdSTR.Bits.DAYS_units1 #define IRTC_DAYS_bcd_DAYS_units2 _IRTC_DAYS_bcd.SameAddr_STR.IRTC_DAYS_bcdSTR.Bits.DAYS_units2 #define IRTC_DAYS_bcd_DAYS_units3 _IRTC_DAYS_bcd.SameAddr_STR.IRTC_DAYS_bcdSTR.Bits.DAYS_units3 #define IRTC_DAYS_bcd_DAYS_tens0 _IRTC_DAYS_bcd.SameAddr_STR.IRTC_DAYS_bcdSTR.Bits.DAYS_tens0 #define IRTC_DAYS_bcd_DAYS_tens1 _IRTC_DAYS_bcd.SameAddr_STR.IRTC_DAYS_bcdSTR.Bits.DAYS_tens1 #define IRTC_DAYS_bcd_DAYS_tens2 _IRTC_DAYS_bcd.SameAddr_STR.IRTC_DAYS_bcdSTR.Bits.DAYS_tens2 #define IRTC_DAYS_bcd_DAYS_tens3 _IRTC_DAYS_bcd.SameAddr_STR.IRTC_DAYS_bcdSTR.Bits.DAYS_tens3 #define IRTC_DAYS_bcd_DAY_OF_WEEK0 _IRTC_DAYS_bcd.SameAddr_STR.IRTC_DAYS_bcdSTR.Bits.DAY_OF_WEEK0 #define IRTC_DAYS_bcd_DAY_OF_WEEK1 _IRTC_DAYS_bcd.SameAddr_STR.IRTC_DAYS_bcdSTR.Bits.DAY_OF_WEEK1 #define IRTC_DAYS_bcd_DAY_OF_WEEK2 _IRTC_DAYS_bcd.SameAddr_STR.IRTC_DAYS_bcdSTR.Bits.DAY_OF_WEEK2 #define IRTC_DAYS_bcd_DAYS_units _IRTC_DAYS_bcd.SameAddr_STR.IRTC_DAYS_bcdSTR.MergedBits.grpDAYS_units #define IRTC_DAYS_bcd_DAYS_tens _IRTC_DAYS_bcd.SameAddr_STR.IRTC_DAYS_bcdSTR.MergedBits.grpDAYS_tens #define IRTC_DAYS_bcd_DAY_OF_WEEK _IRTC_DAYS_bcd.SameAddr_STR.IRTC_DAYS_bcdSTR.MergedBits.grpDAY_OF_WEEK #define IRTC_DAYS_bcd_DAYS_units0_MASK 1 #define IRTC_DAYS_bcd_DAYS_units1_MASK 2 #define IRTC_DAYS_bcd_DAYS_units2_MASK 4 #define IRTC_DAYS_bcd_DAYS_units3_MASK 8 #define IRTC_DAYS_bcd_DAYS_tens0_MASK 16 #define IRTC_DAYS_bcd_DAYS_tens1_MASK 32 #define IRTC_DAYS_bcd_DAYS_tens2_MASK 64 #define IRTC_DAYS_bcd_DAYS_tens3_MASK 128 #define IRTC_DAYS_bcd_DAY_OF_WEEK0_MASK 256 #define IRTC_DAYS_bcd_DAY_OF_WEEK1_MASK 512 #define IRTC_DAYS_bcd_DAY_OF_WEEK2_MASK 1024 #define IRTC_DAYS_bcd_DAYS_units_MASK 15 #define IRTC_DAYS_bcd_DAYS_units_BITNUM 0 #define IRTC_DAYS_bcd_DAYS_tens_MASK 240 #define IRTC_DAYS_bcd_DAYS_tens_BITNUM 4 #define IRTC_DAYS_bcd_DAY_OF_WEEK_MASK 1792 #define IRTC_DAYS_bcd_DAY_OF_WEEK_BITNUM 8 /*** IRTC_DAYS_bin - RTC Days Counter Register (binary format); Several registers at the same address ***/ union { struct { word DAYS0 :1; /* Day Setting. Indicates the current day count. Valid Count: 1 - 31, bit 0 */ word DAYS1 :1; /* Day Setting. Indicates the current day count. Valid Count: 1 - 31, bit 1 */ word DAYS2 :1; /* Day Setting. Indicates the current day count. Valid Count: 1 - 31, bit 2 */ word DAYS3 :1; /* Day Setting. Indicates the current day count. Valid Count: 1 - 31, bit 3 */ word DAYS4 :1; /* Day Setting. Indicates the current day count. Valid Count: 1 - 31, bit 4 */ word :1; word :1; word :1; word DAY_OF_WEEK0 :1; /* Indicates the current day count, bit 0, bit 0 */ word DAY_OF_WEEK1 :1; /* Indicates the current day count, bit 0, bit 1 */ word DAY_OF_WEEK2 :1; /* Indicates the current day count, bit 0, bit 2 */ word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpDAYS :5; word :1; word :1; word :1; word grpDAY_OF_WEEK :3; word :1; word :1; word :1; word :1; word :1; } MergedBits; } IRTC_DAYS_binSTR; #define IRTC_DAYS_bin _IRTC_DAYS_bcd.Word #define IRTC_DAYS_bin_DAYS0 _IRTC_DAYS_bcd.SameAddr_STR.IRTC_DAYS_binSTR.Bits.DAYS0 #define IRTC_DAYS_bin_DAYS1 _IRTC_DAYS_bcd.SameAddr_STR.IRTC_DAYS_binSTR.Bits.DAYS1 #define IRTC_DAYS_bin_DAYS2 _IRTC_DAYS_bcd.SameAddr_STR.IRTC_DAYS_binSTR.Bits.DAYS2 #define IRTC_DAYS_bin_DAYS3 _IRTC_DAYS_bcd.SameAddr_STR.IRTC_DAYS_binSTR.Bits.DAYS3 #define IRTC_DAYS_bin_DAYS4 _IRTC_DAYS_bcd.SameAddr_STR.IRTC_DAYS_binSTR.Bits.DAYS4 #define IRTC_DAYS_bin_DAY_OF_WEEK0 _IRTC_DAYS_bcd.SameAddr_STR.IRTC_DAYS_binSTR.Bits.DAY_OF_WEEK0 #define IRTC_DAYS_bin_DAY_OF_WEEK1 _IRTC_DAYS_bcd.SameAddr_STR.IRTC_DAYS_binSTR.Bits.DAY_OF_WEEK1 #define IRTC_DAYS_bin_DAY_OF_WEEK2 _IRTC_DAYS_bcd.SameAddr_STR.IRTC_DAYS_binSTR.Bits.DAY_OF_WEEK2 #define IRTC_DAYS_bin_DAYS _IRTC_DAYS_bcd.SameAddr_STR.IRTC_DAYS_binSTR.MergedBits.grpDAYS #define IRTC_DAYS_bin_DAY_OF_WEEK _IRTC_DAYS_bcd.SameAddr_STR.IRTC_DAYS_binSTR.MergedBits.grpDAY_OF_WEEK #define IRTC_DAYS_bin_DAYS0_MASK 1 #define IRTC_DAYS_bin_DAYS1_MASK 2 #define IRTC_DAYS_bin_DAYS2_MASK 4 #define IRTC_DAYS_bin_DAYS3_MASK 8 #define IRTC_DAYS_bin_DAYS4_MASK 16 #define IRTC_DAYS_bin_DAY_OF_WEEK0_MASK 256 #define IRTC_DAYS_bin_DAY_OF_WEEK1_MASK 512 #define IRTC_DAYS_bin_DAY_OF_WEEK2_MASK 1024 #define IRTC_DAYS_bin_DAYS_MASK 31 #define IRTC_DAYS_bin_DAYS_BITNUM 0 #define IRTC_DAYS_bin_DAY_OF_WEEK_MASK 1792 #define IRTC_DAYS_bin_DAY_OF_WEEK_BITNUM 8 } SameAddr_STR; /*Several registers at the same address */ } IRTC_DAYS_bcdSTR; extern volatile IRTC_DAYS_bcdSTR _IRTC_DAYS_bcd @0xFFFF8642; /*** IRTC_HOURMIN_bcd - RTC Hours and Minutes Counter Register (BCD format); 0xFFFF8644 ***/ typedef union { word Word; union { /* Several registers at the same address */ /*** IRTC_HOURMIN_bcd - RTC Hours and Minutes Counter Register (BCD format); Several registers at the same address ***/ union { struct { word MINUTES_ones0 :1; /* Indicates the current minutes - ones, bit 0 */ word MINUTES_ones1 :1; /* Indicates the current minutes - ones, bit 1 */ word MINUTES_ones2 :1; /* Indicates the current minutes - ones, bit 2 */ word MINUTES_ones3 :1; /* Indicates the current minutes - ones, bit 3 */ word MINUTES_tens0 :1; /* Indicates the current minutes - tens, bit 0 */ word MINUTES_tens1 :1; /* Indicates the current minutes - tens, bit 1 */ word MINUTES_tens2 :1; /* Indicates the current minutes - tens, bit 2 */ word MINUTES_tens3 :1; /* Indicates the current minutes - tens, bit 3 */ word HOURS_units0 :1; /* Indicates the current hour - units, bit 0 */ word HOURS_units1 :1; /* Indicates the current hour - units, bit 1 */ word HOURS_units2 :1; /* Indicates the current hour - units, bit 2 */ word HOURS_units3 :1; /* Indicates the current hour - units, bit 3 */ word HOURS_tens0 :1; /* Indicates the current hour - tens, bit 0 */ word HOURS_tens1 :1; /* Indicates the current hour - tens, bit 1 */ word HOURS_tens2 :1; /* Indicates the current hour - tens, bit 2 */ word HOURS_tens3 :1; /* Indicates the current hour - tens, bit 3 */ } Bits; struct { word grpMINUTES_ones :4; word grpMINUTES_tens :4; word grpHOURS_units :4; word grpHOURS_tens :4; } MergedBits; } IRTC_HOURMIN_bcdSTR; #define IRTC_HOURMIN_bcd _IRTC_HOURMIN_bcd.Word #define IRTC_HOURMIN_bcd_MINUTES_ones0 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_bcdSTR.Bits.MINUTES_ones0 #define IRTC_HOURMIN_bcd_MINUTES_ones1 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_bcdSTR.Bits.MINUTES_ones1 #define IRTC_HOURMIN_bcd_MINUTES_ones2 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_bcdSTR.Bits.MINUTES_ones2 #define IRTC_HOURMIN_bcd_MINUTES_ones3 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_bcdSTR.Bits.MINUTES_ones3 #define IRTC_HOURMIN_bcd_MINUTES_tens0 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_bcdSTR.Bits.MINUTES_tens0 #define IRTC_HOURMIN_bcd_MINUTES_tens1 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_bcdSTR.Bits.MINUTES_tens1 #define IRTC_HOURMIN_bcd_MINUTES_tens2 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_bcdSTR.Bits.MINUTES_tens2 #define IRTC_HOURMIN_bcd_MINUTES_tens3 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_bcdSTR.Bits.MINUTES_tens3 #define IRTC_HOURMIN_bcd_HOURS_units0 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_bcdSTR.Bits.HOURS_units0 #define IRTC_HOURMIN_bcd_HOURS_units1 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_bcdSTR.Bits.HOURS_units1 #define IRTC_HOURMIN_bcd_HOURS_units2 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_bcdSTR.Bits.HOURS_units2 #define IRTC_HOURMIN_bcd_HOURS_units3 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_bcdSTR.Bits.HOURS_units3 #define IRTC_HOURMIN_bcd_HOURS_tens0 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_bcdSTR.Bits.HOURS_tens0 #define IRTC_HOURMIN_bcd_HOURS_tens1 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_bcdSTR.Bits.HOURS_tens1 #define IRTC_HOURMIN_bcd_HOURS_tens2 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_bcdSTR.Bits.HOURS_tens2 #define IRTC_HOURMIN_bcd_HOURS_tens3 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_bcdSTR.Bits.HOURS_tens3 #define IRTC_HOURMIN_bcd_MINUTES_ones _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_bcdSTR.MergedBits.grpMINUTES_ones #define IRTC_HOURMIN_bcd_MINUTES_tens _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_bcdSTR.MergedBits.grpMINUTES_tens #define IRTC_HOURMIN_bcd_HOURS_units _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_bcdSTR.MergedBits.grpHOURS_units #define IRTC_HOURMIN_bcd_HOURS_tens _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_bcdSTR.MergedBits.grpHOURS_tens #define IRTC_HOURMIN_bcd_MINUTES_ones0_MASK 1 #define IRTC_HOURMIN_bcd_MINUTES_ones1_MASK 2 #define IRTC_HOURMIN_bcd_MINUTES_ones2_MASK 4 #define IRTC_HOURMIN_bcd_MINUTES_ones3_MASK 8 #define IRTC_HOURMIN_bcd_MINUTES_tens0_MASK 16 #define IRTC_HOURMIN_bcd_MINUTES_tens1_MASK 32 #define IRTC_HOURMIN_bcd_MINUTES_tens2_MASK 64 #define IRTC_HOURMIN_bcd_MINUTES_tens3_MASK 128 #define IRTC_HOURMIN_bcd_HOURS_units0_MASK 256 #define IRTC_HOURMIN_bcd_HOURS_units1_MASK 512 #define IRTC_HOURMIN_bcd_HOURS_units2_MASK 1024 #define IRTC_HOURMIN_bcd_HOURS_units3_MASK 2048 #define IRTC_HOURMIN_bcd_HOURS_tens0_MASK 4096 #define IRTC_HOURMIN_bcd_HOURS_tens1_MASK 8192 #define IRTC_HOURMIN_bcd_HOURS_tens2_MASK 16384 #define IRTC_HOURMIN_bcd_HOURS_tens3_MASK 32768 #define IRTC_HOURMIN_bcd_MINUTES_ones_MASK 15 #define IRTC_HOURMIN_bcd_MINUTES_ones_BITNUM 0 #define IRTC_HOURMIN_bcd_MINUTES_tens_MASK 240 #define IRTC_HOURMIN_bcd_MINUTES_tens_BITNUM 4 #define IRTC_HOURMIN_bcd_HOURS_units_MASK 3840 #define IRTC_HOURMIN_bcd_HOURS_units_BITNUM 8 #define IRTC_HOURMIN_bcd_HOURS_tens_MASK 61440 #define IRTC_HOURMIN_bcd_HOURS_tens_BITNUM 12 /*** IRTC_HOURMIN_bin - RTC Hours and Minutes Counter Register (binary format); Several registers at the same address ***/ union { struct { word MINUTES0 :1; /* Indicates the current minutes. It can be set to any value between 0 and 59 (0x3B), bit 0 */ word MINUTES1 :1; /* Indicates the current minutes. It can be set to any value between 0 and 59 (0x3B), bit 1 */ word MINUTES2 :1; /* Indicates the current minutes. It can be set to any value between 0 and 59 (0x3B), bit 2 */ word MINUTES3 :1; /* Indicates the current minutes. It can be set to any value between 0 and 59 (0x3B), bit 3 */ word MINUTES4 :1; /* Indicates the current minutes. It can be set to any value between 0 and 59 (0x3B), bit 4 */ word MINUTES5 :1; /* Indicates the current minutes. It can be set to any value between 0 and 59 (0x3B), bit 5 */ word :1; word :1; word HOURS0 :1; /* Indicates the current hour. It can be set to any value between 0 and 23 (0x17), bit 0 */ word HOURS1 :1; /* Indicates the current hour. It can be set to any value between 0 and 23 (0x17), bit 1 */ word HOURS2 :1; /* Indicates the current hour. It can be set to any value between 0 and 23 (0x17), bit 2 */ word HOURS3 :1; /* Indicates the current hour. It can be set to any value between 0 and 23 (0x17), bit 3 */ word HOURS4 :1; /* Indicates the current hour. It can be set to any value between 0 and 23 (0x17), bit 4 */ word :1; word :1; word :1; } Bits; struct { word grpMINUTES :6; word :1; word :1; word grpHOURS :5; word :1; word :1; word :1; } MergedBits; } IRTC_HOURMIN_binSTR; #define IRTC_HOURMIN_bin _IRTC_HOURMIN_bcd.Word #define IRTC_HOURMIN_bin_MINUTES0 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_binSTR.Bits.MINUTES0 #define IRTC_HOURMIN_bin_MINUTES1 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_binSTR.Bits.MINUTES1 #define IRTC_HOURMIN_bin_MINUTES2 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_binSTR.Bits.MINUTES2 #define IRTC_HOURMIN_bin_MINUTES3 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_binSTR.Bits.MINUTES3 #define IRTC_HOURMIN_bin_MINUTES4 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_binSTR.Bits.MINUTES4 #define IRTC_HOURMIN_bin_MINUTES5 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_binSTR.Bits.MINUTES5 #define IRTC_HOURMIN_bin_HOURS0 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_binSTR.Bits.HOURS0 #define IRTC_HOURMIN_bin_HOURS1 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_binSTR.Bits.HOURS1 #define IRTC_HOURMIN_bin_HOURS2 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_binSTR.Bits.HOURS2 #define IRTC_HOURMIN_bin_HOURS3 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_binSTR.Bits.HOURS3 #define IRTC_HOURMIN_bin_HOURS4 _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_binSTR.Bits.HOURS4 #define IRTC_HOURMIN_bin_MINUTES _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_binSTR.MergedBits.grpMINUTES #define IRTC_HOURMIN_bin_HOURS _IRTC_HOURMIN_bcd.SameAddr_STR.IRTC_HOURMIN_binSTR.MergedBits.grpHOURS #define IRTC_HOURMIN_bin_MINUTES0_MASK 1 #define IRTC_HOURMIN_bin_MINUTES1_MASK 2 #define IRTC_HOURMIN_bin_MINUTES2_MASK 4 #define IRTC_HOURMIN_bin_MINUTES3_MASK 8 #define IRTC_HOURMIN_bin_MINUTES4_MASK 16 #define IRTC_HOURMIN_bin_MINUTES5_MASK 32 #define IRTC_HOURMIN_bin_HOURS0_MASK 256 #define IRTC_HOURMIN_bin_HOURS1_MASK 512 #define IRTC_HOURMIN_bin_HOURS2_MASK 1024 #define IRTC_HOURMIN_bin_HOURS3_MASK 2048 #define IRTC_HOURMIN_bin_HOURS4_MASK 4096 #define IRTC_HOURMIN_bin_MINUTES_MASK 63 #define IRTC_HOURMIN_bin_MINUTES_BITNUM 0 #define IRTC_HOURMIN_bin_HOURS_MASK 7936 #define IRTC_HOURMIN_bin_HOURS_BITNUM 8 } SameAddr_STR; /*Several registers at the same address */ } IRTC_HOURMIN_bcdSTR; extern volatile IRTC_HOURMIN_bcdSTR _IRTC_HOURMIN_bcd @0xFFFF8644; /*** IRTC_SECONDS_bcd - RTC Seconds Counter Register (BCD format); 0xFFFF8646 ***/ typedef union { word Word; union { /* Several registers at the same address */ /*** IRTC_SECONDS_bcd - RTC Seconds Counter Register (BCD format); Several registers at the same address ***/ union { struct { word SECONDS_units0 :1; /* Indicates the current seconds - units, bit 0 */ word SECONDS_units1 :1; /* Indicates the current seconds - units, bit 1 */ word SECONDS_units2 :1; /* Indicates the current seconds - units, bit 2 */ word SECONDS_units3 :1; /* Indicates the current seconds - units, bit 3 */ word SECONDS_tens0 :1; /* Indicates the current seconds - tens, bit 0 */ word SECONDS_tens1 :1; /* Indicates the current seconds - tens, bit 1 */ word SECONDS_tens2 :1; /* Indicates the current seconds - tens, bit 2 */ word SECONDS_tens3 :1; /* Indicates the current seconds - tens, bit 3 */ word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpSECONDS_units :4; word grpSECONDS_tens :4; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } IRTC_SECONDS_bcdSTR; #define IRTC_SECONDS_bcd _IRTC_SECONDS_bcd.Word #define IRTC_SECONDS_bcd_SECONDS_units0 _IRTC_SECONDS_bcd.SameAddr_STR.IRTC_SECONDS_bcdSTR.Bits.SECONDS_units0 #define IRTC_SECONDS_bcd_SECONDS_units1 _IRTC_SECONDS_bcd.SameAddr_STR.IRTC_SECONDS_bcdSTR.Bits.SECONDS_units1 #define IRTC_SECONDS_bcd_SECONDS_units2 _IRTC_SECONDS_bcd.SameAddr_STR.IRTC_SECONDS_bcdSTR.Bits.SECONDS_units2 #define IRTC_SECONDS_bcd_SECONDS_units3 _IRTC_SECONDS_bcd.SameAddr_STR.IRTC_SECONDS_bcdSTR.Bits.SECONDS_units3 #define IRTC_SECONDS_bcd_SECONDS_tens0 _IRTC_SECONDS_bcd.SameAddr_STR.IRTC_SECONDS_bcdSTR.Bits.SECONDS_tens0 #define IRTC_SECONDS_bcd_SECONDS_tens1 _IRTC_SECONDS_bcd.SameAddr_STR.IRTC_SECONDS_bcdSTR.Bits.SECONDS_tens1 #define IRTC_SECONDS_bcd_SECONDS_tens2 _IRTC_SECONDS_bcd.SameAddr_STR.IRTC_SECONDS_bcdSTR.Bits.SECONDS_tens2 #define IRTC_SECONDS_bcd_SECONDS_tens3 _IRTC_SECONDS_bcd.SameAddr_STR.IRTC_SECONDS_bcdSTR.Bits.SECONDS_tens3 #define IRTC_SECONDS_bcd_SECONDS_units _IRTC_SECONDS_bcd.SameAddr_STR.IRTC_SECONDS_bcdSTR.MergedBits.grpSECONDS_units #define IRTC_SECONDS_bcd_SECONDS_tens _IRTC_SECONDS_bcd.SameAddr_STR.IRTC_SECONDS_bcdSTR.MergedBits.grpSECONDS_tens #define IRTC_SECONDS_bcd_SECONDS_units0_MASK 1 #define IRTC_SECONDS_bcd_SECONDS_units1_MASK 2 #define IRTC_SECONDS_bcd_SECONDS_units2_MASK 4 #define IRTC_SECONDS_bcd_SECONDS_units3_MASK 8 #define IRTC_SECONDS_bcd_SECONDS_tens0_MASK 16 #define IRTC_SECONDS_bcd_SECONDS_tens1_MASK 32 #define IRTC_SECONDS_bcd_SECONDS_tens2_MASK 64 #define IRTC_SECONDS_bcd_SECONDS_tens3_MASK 128 #define IRTC_SECONDS_bcd_SECONDS_units_MASK 15 #define IRTC_SECONDS_bcd_SECONDS_units_BITNUM 0 #define IRTC_SECONDS_bcd_SECONDS_tens_MASK 240 #define IRTC_SECONDS_bcd_SECONDS_tens_BITNUM 4 /*** IRTC_SECONDS_bin - RTC Seconds Counter Register (binary format); Several registers at the same address ***/ union { struct { word SECONDS0 :1; /* Indicates the current seconds. It can be set to any value between 0 and 59 (0x3B), bit 0 */ word SECONDS1 :1; /* Indicates the current seconds. It can be set to any value between 0 and 59 (0x3B), bit 1 */ word SECONDS2 :1; /* Indicates the current seconds. It can be set to any value between 0 and 59 (0x3B), bit 2 */ word SECONDS3 :1; /* Indicates the current seconds. It can be set to any value between 0 and 59 (0x3B), bit 3 */ word SECONDS4 :1; /* Indicates the current seconds. It can be set to any value between 0 and 59 (0x3B), bit 4 */ word SECONDS5 :1; /* Indicates the current seconds. It can be set to any value between 0 and 59 (0x3B), bit 5 */ word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpSECONDS :6; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } IRTC_SECONDS_binSTR; #define IRTC_SECONDS_bin _IRTC_SECONDS_bcd.Word #define IRTC_SECONDS_bin_SECONDS0 _IRTC_SECONDS_bcd.SameAddr_STR.IRTC_SECONDS_binSTR.Bits.SECONDS0 #define IRTC_SECONDS_bin_SECONDS1 _IRTC_SECONDS_bcd.SameAddr_STR.IRTC_SECONDS_binSTR.Bits.SECONDS1 #define IRTC_SECONDS_bin_SECONDS2 _IRTC_SECONDS_bcd.SameAddr_STR.IRTC_SECONDS_binSTR.Bits.SECONDS2 #define IRTC_SECONDS_bin_SECONDS3 _IRTC_SECONDS_bcd.SameAddr_STR.IRTC_SECONDS_binSTR.Bits.SECONDS3 #define IRTC_SECONDS_bin_SECONDS4 _IRTC_SECONDS_bcd.SameAddr_STR.IRTC_SECONDS_binSTR.Bits.SECONDS4 #define IRTC_SECONDS_bin_SECONDS5 _IRTC_SECONDS_bcd.SameAddr_STR.IRTC_SECONDS_binSTR.Bits.SECONDS5 #define IRTC_SECONDS_bin_SECONDS _IRTC_SECONDS_bcd.SameAddr_STR.IRTC_SECONDS_binSTR.MergedBits.grpSECONDS #define IRTC_SECONDS_bin_SECONDS0_MASK 1 #define IRTC_SECONDS_bin_SECONDS1_MASK 2 #define IRTC_SECONDS_bin_SECONDS2_MASK 4 #define IRTC_SECONDS_bin_SECONDS3_MASK 8 #define IRTC_SECONDS_bin_SECONDS4_MASK 16 #define IRTC_SECONDS_bin_SECONDS5_MASK 32 #define IRTC_SECONDS_bin_SECONDS_MASK 63 #define IRTC_SECONDS_bin_SECONDS_BITNUM 0 } SameAddr_STR; /*Several registers at the same address */ } IRTC_SECONDS_bcdSTR; extern volatile IRTC_SECONDS_bcdSTR _IRTC_SECONDS_bcd @0xFFFF8646; /*** IRTC_ALM_YRMON_bcd - RTC Year and Month Alarm Register (BCD format); 0xFFFF8648 ***/ typedef union { word Word; union { /* Several registers at the same address */ /*** IRTC_ALM_YRMON_bcd - RTC Year and Month Alarm Register (BCD format); Several registers at the same address ***/ union { struct { word ALM_MONTH_units0 :1; /* Month alarm value bits - units, bit 0 */ word ALM_MONTH_units1 :1; /* Month alarm value bits - units, bit 1 */ word ALM_MONTH_units2 :1; /* Month alarm value bits - units, bit 2 */ word ALM_MONTH_units3 :1; /* Month alarm value bits - units, bit 3 */ word ALM_MONTH_tens0 :1; /* Month alarm value bits - tens, bit 0 */ word ALM_MONTH_tens1 :1; /* Month alarm value bits - tens, bit 1 */ word ALM_MONTH_tens2 :1; /* Month alarm value bits - tens, bit 2 */ word ALM_MONTH_tens3 :1; /* Month alarm value bits - tens, bit 3 */ word ALM_YEAR0 :1; /* Year count value bits, bit 0 */ word ALM_YEAR1 :1; /* Year count value bits, bit 1 */ word ALM_YEAR2 :1; /* Year count value bits, bit 2 */ word ALM_YEAR3 :1; /* Year count value bits, bit 3 */ word ALM_YEAR4 :1; /* Year count value bits, bit 4 */ word ALM_YEAR5 :1; /* Year count value bits, bit 5 */ word ALM_YEAR6 :1; /* Year count value bits, bit 6 */ word ALM_YEAR7 :1; /* Year count value bits, bit 7 */ } Bits; struct { word grpALM_MONTH_units :4; word grpALM_MONTH_tens :4; word grpALM_YEAR :8; } MergedBits; } IRTC_ALM_YRMON_bcdSTR; #define IRTC_ALM_YRMON_bcd _IRTC_ALM_YRMON_bcd.Word #define IRTC_ALM_YRMON_bcd_ALM_MONTH_units0 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_bcdSTR.Bits.ALM_MONTH_units0 #define IRTC_ALM_YRMON_bcd_ALM_MONTH_units1 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_bcdSTR.Bits.ALM_MONTH_units1 #define IRTC_ALM_YRMON_bcd_ALM_MONTH_units2 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_bcdSTR.Bits.ALM_MONTH_units2 #define IRTC_ALM_YRMON_bcd_ALM_MONTH_units3 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_bcdSTR.Bits.ALM_MONTH_units3 #define IRTC_ALM_YRMON_bcd_ALM_MONTH_tens0 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_bcdSTR.Bits.ALM_MONTH_tens0 #define IRTC_ALM_YRMON_bcd_ALM_MONTH_tens1 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_bcdSTR.Bits.ALM_MONTH_tens1 #define IRTC_ALM_YRMON_bcd_ALM_MONTH_tens2 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_bcdSTR.Bits.ALM_MONTH_tens2 #define IRTC_ALM_YRMON_bcd_ALM_MONTH_tens3 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_bcdSTR.Bits.ALM_MONTH_tens3 #define IRTC_ALM_YRMON_bcd_ALM_YEAR0 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_bcdSTR.Bits.ALM_YEAR0 #define IRTC_ALM_YRMON_bcd_ALM_YEAR1 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_bcdSTR.Bits.ALM_YEAR1 #define IRTC_ALM_YRMON_bcd_ALM_YEAR2 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_bcdSTR.Bits.ALM_YEAR2 #define IRTC_ALM_YRMON_bcd_ALM_YEAR3 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_bcdSTR.Bits.ALM_YEAR3 #define IRTC_ALM_YRMON_bcd_ALM_YEAR4 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_bcdSTR.Bits.ALM_YEAR4 #define IRTC_ALM_YRMON_bcd_ALM_YEAR5 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_bcdSTR.Bits.ALM_YEAR5 #define IRTC_ALM_YRMON_bcd_ALM_YEAR6 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_bcdSTR.Bits.ALM_YEAR6 #define IRTC_ALM_YRMON_bcd_ALM_YEAR7 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_bcdSTR.Bits.ALM_YEAR7 #define IRTC_ALM_YRMON_bcd_ALM_MONTH_units _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_bcdSTR.MergedBits.grpALM_MONTH_units #define IRTC_ALM_YRMON_bcd_ALM_MONTH_tens _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_bcdSTR.MergedBits.grpALM_MONTH_tens #define IRTC_ALM_YRMON_bcd_ALM_YEAR _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_bcdSTR.MergedBits.grpALM_YEAR #define IRTC_ALM_YRMON_bcd_ALM_MONTH_units0_MASK 1 #define IRTC_ALM_YRMON_bcd_ALM_MONTH_units1_MASK 2 #define IRTC_ALM_YRMON_bcd_ALM_MONTH_units2_MASK 4 #define IRTC_ALM_YRMON_bcd_ALM_MONTH_units3_MASK 8 #define IRTC_ALM_YRMON_bcd_ALM_MONTH_tens0_MASK 16 #define IRTC_ALM_YRMON_bcd_ALM_MONTH_tens1_MASK 32 #define IRTC_ALM_YRMON_bcd_ALM_MONTH_tens2_MASK 64 #define IRTC_ALM_YRMON_bcd_ALM_MONTH_tens3_MASK 128 #define IRTC_ALM_YRMON_bcd_ALM_YEAR0_MASK 256 #define IRTC_ALM_YRMON_bcd_ALM_YEAR1_MASK 512 #define IRTC_ALM_YRMON_bcd_ALM_YEAR2_MASK 1024 #define IRTC_ALM_YRMON_bcd_ALM_YEAR3_MASK 2048 #define IRTC_ALM_YRMON_bcd_ALM_YEAR4_MASK 4096 #define IRTC_ALM_YRMON_bcd_ALM_YEAR5_MASK 8192 #define IRTC_ALM_YRMON_bcd_ALM_YEAR6_MASK 16384 #define IRTC_ALM_YRMON_bcd_ALM_YEAR7_MASK 32768 #define IRTC_ALM_YRMON_bcd_ALM_MONTH_units_MASK 15 #define IRTC_ALM_YRMON_bcd_ALM_MONTH_units_BITNUM 0 #define IRTC_ALM_YRMON_bcd_ALM_MONTH_tens_MASK 240 #define IRTC_ALM_YRMON_bcd_ALM_MONTH_tens_BITNUM 4 #define IRTC_ALM_YRMON_bcd_ALM_YEAR_MASK 65280 #define IRTC_ALM_YRMON_bcd_ALM_YEAR_BITNUM 8 /*** IRTC_ALM_YRMON_bin - RTC Year and Month Alarm Register (binary format); Several registers at the same address ***/ union { struct { word ALM_MONTH0 :1; /* Month alarm value bits, bit 0 */ word ALM_MONTH1 :1; /* Month alarm value bits, bit 1 */ word ALM_MONTH2 :1; /* Month alarm value bits, bit 2 */ word ALM_MONTH3 :1; /* Month alarm value bits, bit 3 */ word :1; word :1; word :1; word :1; word ALM_YEAR0 :1; /* Year count value bits, bit 0 */ word ALM_YEAR1 :1; /* Year count value bits, bit 1 */ word ALM_YEAR2 :1; /* Year count value bits, bit 2 */ word ALM_YEAR3 :1; /* Year count value bits, bit 3 */ word ALM_YEAR4 :1; /* Year count value bits, bit 4 */ word ALM_YEAR5 :1; /* Year count value bits, bit 5 */ word ALM_YEAR6 :1; /* Year count value bits, bit 6 */ word ALM_YEAR7 :1; /* Year count value bits, bit 7 */ } Bits; struct { word grpALM_MONTH :4; word :1; word :1; word :1; word :1; word grpALM_YEAR :8; } MergedBits; } IRTC_ALM_YRMON_binSTR; #define IRTC_ALM_YRMON_bin _IRTC_ALM_YRMON_bcd.Word #define IRTC_ALM_YRMON_bin_ALM_MONTH0 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_binSTR.Bits.ALM_MONTH0 #define IRTC_ALM_YRMON_bin_ALM_MONTH1 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_binSTR.Bits.ALM_MONTH1 #define IRTC_ALM_YRMON_bin_ALM_MONTH2 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_binSTR.Bits.ALM_MONTH2 #define IRTC_ALM_YRMON_bin_ALM_MONTH3 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_binSTR.Bits.ALM_MONTH3 #define IRTC_ALM_YRMON_bin_ALM_YEAR0 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_binSTR.Bits.ALM_YEAR0 #define IRTC_ALM_YRMON_bin_ALM_YEAR1 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_binSTR.Bits.ALM_YEAR1 #define IRTC_ALM_YRMON_bin_ALM_YEAR2 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_binSTR.Bits.ALM_YEAR2 #define IRTC_ALM_YRMON_bin_ALM_YEAR3 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_binSTR.Bits.ALM_YEAR3 #define IRTC_ALM_YRMON_bin_ALM_YEAR4 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_binSTR.Bits.ALM_YEAR4 #define IRTC_ALM_YRMON_bin_ALM_YEAR5 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_binSTR.Bits.ALM_YEAR5 #define IRTC_ALM_YRMON_bin_ALM_YEAR6 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_binSTR.Bits.ALM_YEAR6 #define IRTC_ALM_YRMON_bin_ALM_YEAR7 _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_binSTR.Bits.ALM_YEAR7 #define IRTC_ALM_YRMON_bin_ALM_MONTH _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_binSTR.MergedBits.grpALM_MONTH #define IRTC_ALM_YRMON_bin_ALM_YEAR _IRTC_ALM_YRMON_bcd.SameAddr_STR.IRTC_ALM_YRMON_binSTR.MergedBits.grpALM_YEAR #define IRTC_ALM_YRMON_bin_ALM_MONTH0_MASK 1 #define IRTC_ALM_YRMON_bin_ALM_MONTH1_MASK 2 #define IRTC_ALM_YRMON_bin_ALM_MONTH2_MASK 4 #define IRTC_ALM_YRMON_bin_ALM_MONTH3_MASK 8 #define IRTC_ALM_YRMON_bin_ALM_YEAR0_MASK 256 #define IRTC_ALM_YRMON_bin_ALM_YEAR1_MASK 512 #define IRTC_ALM_YRMON_bin_ALM_YEAR2_MASK 1024 #define IRTC_ALM_YRMON_bin_ALM_YEAR3_MASK 2048 #define IRTC_ALM_YRMON_bin_ALM_YEAR4_MASK 4096 #define IRTC_ALM_YRMON_bin_ALM_YEAR5_MASK 8192 #define IRTC_ALM_YRMON_bin_ALM_YEAR6_MASK 16384 #define IRTC_ALM_YRMON_bin_ALM_YEAR7_MASK 32768 #define IRTC_ALM_YRMON_bin_ALM_MONTH_MASK 15 #define IRTC_ALM_YRMON_bin_ALM_MONTH_BITNUM 0 #define IRTC_ALM_YRMON_bin_ALM_YEAR_MASK 65280 #define IRTC_ALM_YRMON_bin_ALM_YEAR_BITNUM 8 } SameAddr_STR; /*Several registers at the same address */ } IRTC_ALM_YRMON_bcdSTR; extern volatile IRTC_ALM_YRMON_bcdSTR _IRTC_ALM_YRMON_bcd @0xFFFF8648; /*** IRTC_ALM_DAYS_bcd - RTC Day Alarm Register (BCD format); 0xFFFF864A ***/ typedef union { word Word; union { /* Several registers at the same address */ /*** IRTC_ALM_DAYS_bcd - RTC Day Alarm Register (BCD format); Several registers at the same address ***/ union { struct { word ALM_DAYS_units0 :1; /* Indicates the current day setting of the alarm - units, bit 0 */ word ALM_DAYS_units1 :1; /* Indicates the current day setting of the alarm - units, bit 1 */ word ALM_DAYS_units2 :1; /* Indicates the current day setting of the alarm - units, bit 2 */ word ALM_DAYS_units3 :1; /* Indicates the current day setting of the alarm - units, bit 3 */ word ALM_DAYS_tens0 :1; /* Indicates the current day setting of the alarm - tens, bit 0 */ word ALM_DAYS_tens1 :1; /* Indicates the current day setting of the alarm - tens, bit 1 */ word ALM_DAYS_tens2 :1; /* Indicates the current day setting of the alarm - tens, bit 2 */ word ALM_DAYS_tens3 :1; /* Indicates the current day setting of the alarm - tens, bit 3 */ word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpALM_DAYS_units :4; word grpALM_DAYS_tens :4; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } IRTC_ALM_DAYS_bcdSTR; #define IRTC_ALM_DAYS_bcd _IRTC_ALM_DAYS_bcd.Word #define IRTC_ALM_DAYS_bcd_ALM_DAYS_units0 _IRTC_ALM_DAYS_bcd.SameAddr_STR.IRTC_ALM_DAYS_bcdSTR.Bits.ALM_DAYS_units0 #define IRTC_ALM_DAYS_bcd_ALM_DAYS_units1 _IRTC_ALM_DAYS_bcd.SameAddr_STR.IRTC_ALM_DAYS_bcdSTR.Bits.ALM_DAYS_units1 #define IRTC_ALM_DAYS_bcd_ALM_DAYS_units2 _IRTC_ALM_DAYS_bcd.SameAddr_STR.IRTC_ALM_DAYS_bcdSTR.Bits.ALM_DAYS_units2 #define IRTC_ALM_DAYS_bcd_ALM_DAYS_units3 _IRTC_ALM_DAYS_bcd.SameAddr_STR.IRTC_ALM_DAYS_bcdSTR.Bits.ALM_DAYS_units3 #define IRTC_ALM_DAYS_bcd_ALM_DAYS_tens0 _IRTC_ALM_DAYS_bcd.SameAddr_STR.IRTC_ALM_DAYS_bcdSTR.Bits.ALM_DAYS_tens0 #define IRTC_ALM_DAYS_bcd_ALM_DAYS_tens1 _IRTC_ALM_DAYS_bcd.SameAddr_STR.IRTC_ALM_DAYS_bcdSTR.Bits.ALM_DAYS_tens1 #define IRTC_ALM_DAYS_bcd_ALM_DAYS_tens2 _IRTC_ALM_DAYS_bcd.SameAddr_STR.IRTC_ALM_DAYS_bcdSTR.Bits.ALM_DAYS_tens2 #define IRTC_ALM_DAYS_bcd_ALM_DAYS_tens3 _IRTC_ALM_DAYS_bcd.SameAddr_STR.IRTC_ALM_DAYS_bcdSTR.Bits.ALM_DAYS_tens3 #define IRTC_ALM_DAYS_bcd_ALM_DAYS_units _IRTC_ALM_DAYS_bcd.SameAddr_STR.IRTC_ALM_DAYS_bcdSTR.MergedBits.grpALM_DAYS_units #define IRTC_ALM_DAYS_bcd_ALM_DAYS_tens _IRTC_ALM_DAYS_bcd.SameAddr_STR.IRTC_ALM_DAYS_bcdSTR.MergedBits.grpALM_DAYS_tens #define IRTC_ALM_DAYS_bcd_ALM_DAYS_units0_MASK 1 #define IRTC_ALM_DAYS_bcd_ALM_DAYS_units1_MASK 2 #define IRTC_ALM_DAYS_bcd_ALM_DAYS_units2_MASK 4 #define IRTC_ALM_DAYS_bcd_ALM_DAYS_units3_MASK 8 #define IRTC_ALM_DAYS_bcd_ALM_DAYS_tens0_MASK 16 #define IRTC_ALM_DAYS_bcd_ALM_DAYS_tens1_MASK 32 #define IRTC_ALM_DAYS_bcd_ALM_DAYS_tens2_MASK 64 #define IRTC_ALM_DAYS_bcd_ALM_DAYS_tens3_MASK 128 #define IRTC_ALM_DAYS_bcd_ALM_DAYS_units_MASK 15 #define IRTC_ALM_DAYS_bcd_ALM_DAYS_units_BITNUM 0 #define IRTC_ALM_DAYS_bcd_ALM_DAYS_tens_MASK 240 #define IRTC_ALM_DAYS_bcd_ALM_DAYS_tens_BITNUM 4 /*** IRTC_ALM_DAYS_bin - RTC Day Alarm Register (binary format); Several registers at the same address ***/ union { struct { word ALM_DAYS0 :1; /* Indicates the current day setting of the alarm, bit 0 */ word ALM_DAYS1 :1; /* Indicates the current day setting of the alarm, bit 1 */ word ALM_DAYS2 :1; /* Indicates the current day setting of the alarm, bit 2 */ word ALM_DAYS3 :1; /* Indicates the current day setting of the alarm, bit 3 */ word ALM_DAYS4 :1; /* Indicates the current day setting of the alarm, bit 4 */ word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpALM_DAYS :5; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } IRTC_ALM_DAYS_binSTR; #define IRTC_ALM_DAYS_bin _IRTC_ALM_DAYS_bcd.Word #define IRTC_ALM_DAYS_bin_ALM_DAYS0 _IRTC_ALM_DAYS_bcd.SameAddr_STR.IRTC_ALM_DAYS_binSTR.Bits.ALM_DAYS0 #define IRTC_ALM_DAYS_bin_ALM_DAYS1 _IRTC_ALM_DAYS_bcd.SameAddr_STR.IRTC_ALM_DAYS_binSTR.Bits.ALM_DAYS1 #define IRTC_ALM_DAYS_bin_ALM_DAYS2 _IRTC_ALM_DAYS_bcd.SameAddr_STR.IRTC_ALM_DAYS_binSTR.Bits.ALM_DAYS2 #define IRTC_ALM_DAYS_bin_ALM_DAYS3 _IRTC_ALM_DAYS_bcd.SameAddr_STR.IRTC_ALM_DAYS_binSTR.Bits.ALM_DAYS3 #define IRTC_ALM_DAYS_bin_ALM_DAYS4 _IRTC_ALM_DAYS_bcd.SameAddr_STR.IRTC_ALM_DAYS_binSTR.Bits.ALM_DAYS4 #define IRTC_ALM_DAYS_bin_ALM_DAYS _IRTC_ALM_DAYS_bcd.SameAddr_STR.IRTC_ALM_DAYS_binSTR.MergedBits.grpALM_DAYS #define IRTC_ALM_DAYS_bin_ALM_DAYS0_MASK 1 #define IRTC_ALM_DAYS_bin_ALM_DAYS1_MASK 2 #define IRTC_ALM_DAYS_bin_ALM_DAYS2_MASK 4 #define IRTC_ALM_DAYS_bin_ALM_DAYS3_MASK 8 #define IRTC_ALM_DAYS_bin_ALM_DAYS4_MASK 16 #define IRTC_ALM_DAYS_bin_ALM_DAYS_MASK 31 #define IRTC_ALM_DAYS_bin_ALM_DAYS_BITNUM 0 } SameAddr_STR; /*Several registers at the same address */ } IRTC_ALM_DAYS_bcdSTR; extern volatile IRTC_ALM_DAYS_bcdSTR _IRTC_ALM_DAYS_bcd @0xFFFF864A; /*** IRTC_ALM_HM_bcd - RTC Hours and Minutes Alarm Register (BCD format); 0xFFFF864C ***/ typedef union { word Word; union { /* Several registers at the same address */ /*** IRTC_ALM_HM_bcd - RTC Hours and Minutes Alarm Register (BCD format); Several registers at the same address ***/ union { struct { word ALM_MINUTES_units0 :1; /* Minutes setting of the alarm - units, bit 0 */ word ALM_MINUTES_units1 :1; /* Minutes setting of the alarm - units, bit 1 */ word ALM_MINUTES_units2 :1; /* Minutes setting of the alarm - units, bit 2 */ word ALM_MINUTES_units3 :1; /* Minutes setting of the alarm - units, bit 3 */ word ALM_MINUTES_tens0 :1; /* Minutes setting of the alarm - tens, bit 0 */ word ALM_MINUTES_tens1 :1; /* Minutes setting of the alarm - tens, bit 1 */ word ALM_MINUTES_tens2 :1; /* Minutes setting of the alarm - tens, bit 2 */ word ALM_MINUTES_tens3 :1; /* Minutes setting of the alarm - tens, bit 3 */ word ALM_HOURS_units0 :1; /* Hours setting of the alarm - units, bit 0 */ word ALM_HOURS_units1 :1; /* Hours setting of the alarm - units, bit 1 */ word ALM_HOURS_units2 :1; /* Hours setting of the alarm - units, bit 2 */ word ALM_HOURS_units3 :1; /* Hours setting of the alarm - units, bit 3 */ word ALM_HOURS_tens0 :1; /* Hours setting of the alarm - tens, bit 0 */ word ALM_HOURS_tens1 :1; /* Hours setting of the alarm - tens, bit 1 */ word ALM_HOURS_tens2 :1; /* Hours setting of the alarm - tens, bit 2 */ word ALM_HOURS_tens3 :1; /* Hours setting of the alarm - tens, bit 3 */ } Bits; struct { word grpALM_MINUTES_units :4; word grpALM_MINUTES_tens :4; word grpALM_HOURS_units :4; word grpALM_HOURS_tens :4; } MergedBits; } IRTC_ALM_HM_bcdSTR; #define IRTC_ALM_HM_bcd _IRTC_ALM_HM_bcd.Word #define IRTC_ALM_HM_bcd_ALM_MINUTES_units0 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_bcdSTR.Bits.ALM_MINUTES_units0 #define IRTC_ALM_HM_bcd_ALM_MINUTES_units1 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_bcdSTR.Bits.ALM_MINUTES_units1 #define IRTC_ALM_HM_bcd_ALM_MINUTES_units2 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_bcdSTR.Bits.ALM_MINUTES_units2 #define IRTC_ALM_HM_bcd_ALM_MINUTES_units3 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_bcdSTR.Bits.ALM_MINUTES_units3 #define IRTC_ALM_HM_bcd_ALM_MINUTES_tens0 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_bcdSTR.Bits.ALM_MINUTES_tens0 #define IRTC_ALM_HM_bcd_ALM_MINUTES_tens1 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_bcdSTR.Bits.ALM_MINUTES_tens1 #define IRTC_ALM_HM_bcd_ALM_MINUTES_tens2 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_bcdSTR.Bits.ALM_MINUTES_tens2 #define IRTC_ALM_HM_bcd_ALM_MINUTES_tens3 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_bcdSTR.Bits.ALM_MINUTES_tens3 #define IRTC_ALM_HM_bcd_ALM_HOURS_units0 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_bcdSTR.Bits.ALM_HOURS_units0 #define IRTC_ALM_HM_bcd_ALM_HOURS_units1 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_bcdSTR.Bits.ALM_HOURS_units1 #define IRTC_ALM_HM_bcd_ALM_HOURS_units2 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_bcdSTR.Bits.ALM_HOURS_units2 #define IRTC_ALM_HM_bcd_ALM_HOURS_units3 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_bcdSTR.Bits.ALM_HOURS_units3 #define IRTC_ALM_HM_bcd_ALM_HOURS_tens0 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_bcdSTR.Bits.ALM_HOURS_tens0 #define IRTC_ALM_HM_bcd_ALM_HOURS_tens1 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_bcdSTR.Bits.ALM_HOURS_tens1 #define IRTC_ALM_HM_bcd_ALM_HOURS_tens2 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_bcdSTR.Bits.ALM_HOURS_tens2 #define IRTC_ALM_HM_bcd_ALM_HOURS_tens3 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_bcdSTR.Bits.ALM_HOURS_tens3 #define IRTC_ALM_HM_bcd_ALM_MINUTES_units _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_bcdSTR.MergedBits.grpALM_MINUTES_units #define IRTC_ALM_HM_bcd_ALM_MINUTES_tens _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_bcdSTR.MergedBits.grpALM_MINUTES_tens #define IRTC_ALM_HM_bcd_ALM_HOURS_units _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_bcdSTR.MergedBits.grpALM_HOURS_units #define IRTC_ALM_HM_bcd_ALM_HOURS_tens _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_bcdSTR.MergedBits.grpALM_HOURS_tens #define IRTC_ALM_HM_bcd_ALM_MINUTES_units0_MASK 1 #define IRTC_ALM_HM_bcd_ALM_MINUTES_units1_MASK 2 #define IRTC_ALM_HM_bcd_ALM_MINUTES_units2_MASK 4 #define IRTC_ALM_HM_bcd_ALM_MINUTES_units3_MASK 8 #define IRTC_ALM_HM_bcd_ALM_MINUTES_tens0_MASK 16 #define IRTC_ALM_HM_bcd_ALM_MINUTES_tens1_MASK 32 #define IRTC_ALM_HM_bcd_ALM_MINUTES_tens2_MASK 64 #define IRTC_ALM_HM_bcd_ALM_MINUTES_tens3_MASK 128 #define IRTC_ALM_HM_bcd_ALM_HOURS_units0_MASK 256 #define IRTC_ALM_HM_bcd_ALM_HOURS_units1_MASK 512 #define IRTC_ALM_HM_bcd_ALM_HOURS_units2_MASK 1024 #define IRTC_ALM_HM_bcd_ALM_HOURS_units3_MASK 2048 #define IRTC_ALM_HM_bcd_ALM_HOURS_tens0_MASK 4096 #define IRTC_ALM_HM_bcd_ALM_HOURS_tens1_MASK 8192 #define IRTC_ALM_HM_bcd_ALM_HOURS_tens2_MASK 16384 #define IRTC_ALM_HM_bcd_ALM_HOURS_tens3_MASK 32768 #define IRTC_ALM_HM_bcd_ALM_MINUTES_units_MASK 15 #define IRTC_ALM_HM_bcd_ALM_MINUTES_units_BITNUM 0 #define IRTC_ALM_HM_bcd_ALM_MINUTES_tens_MASK 240 #define IRTC_ALM_HM_bcd_ALM_MINUTES_tens_BITNUM 4 #define IRTC_ALM_HM_bcd_ALM_HOURS_units_MASK 3840 #define IRTC_ALM_HM_bcd_ALM_HOURS_units_BITNUM 8 #define IRTC_ALM_HM_bcd_ALM_HOURS_tens_MASK 61440 #define IRTC_ALM_HM_bcd_ALM_HOURS_tens_BITNUM 12 /*** IRTC_ALM_HM_bin - RTC Hours and Minutes Alarm Register (binary format); Several registers at the same address ***/ union { struct { word ALM_MINUTES0 :1; /* Minutes setting of the alarm. It can be set to any value between 0 and 59 (0x3B), bit 0 */ word ALM_MINUTES1 :1; /* Minutes setting of the alarm. It can be set to any value between 0 and 59 (0x3B), bit 1 */ word ALM_MINUTES2 :1; /* Minutes setting of the alarm. It can be set to any value between 0 and 59 (0x3B), bit 2 */ word ALM_MINUTES3 :1; /* Minutes setting of the alarm. It can be set to any value between 0 and 59 (0x3B), bit 3 */ word ALM_MINUTES4 :1; /* Minutes setting of the alarm. It can be set to any value between 0 and 59 (0x3B), bit 4 */ word ALM_MINUTES5 :1; /* Minutes setting of the alarm. It can be set to any value between 0 and 59 (0x3B), bit 5 */ word :1; word :1; word ALM_HOURS0 :1; /* Hours setting of the alarm. It can be set to any value between 0 and 23 (0x17), bit 0 */ word ALM_HOURS1 :1; /* Hours setting of the alarm. It can be set to any value between 0 and 23 (0x17), bit 1 */ word ALM_HOURS2 :1; /* Hours setting of the alarm. It can be set to any value between 0 and 23 (0x17), bit 2 */ word ALM_HOURS3 :1; /* Hours setting of the alarm. It can be set to any value between 0 and 23 (0x17), bit 3 */ word ALM_HOURS4 :1; /* Hours setting of the alarm. It can be set to any value between 0 and 23 (0x17), bit 4 */ word :1; word :1; word :1; } Bits; struct { word grpALM_MINUTES :6; word :1; word :1; word grpALM_HOURS :5; word :1; word :1; word :1; } MergedBits; } IRTC_ALM_HM_binSTR; #define IRTC_ALM_HM_bin _IRTC_ALM_HM_bcd.Word #define IRTC_ALM_HM_bin_ALM_MINUTES0 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_binSTR.Bits.ALM_MINUTES0 #define IRTC_ALM_HM_bin_ALM_MINUTES1 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_binSTR.Bits.ALM_MINUTES1 #define IRTC_ALM_HM_bin_ALM_MINUTES2 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_binSTR.Bits.ALM_MINUTES2 #define IRTC_ALM_HM_bin_ALM_MINUTES3 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_binSTR.Bits.ALM_MINUTES3 #define IRTC_ALM_HM_bin_ALM_MINUTES4 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_binSTR.Bits.ALM_MINUTES4 #define IRTC_ALM_HM_bin_ALM_MINUTES5 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_binSTR.Bits.ALM_MINUTES5 #define IRTC_ALM_HM_bin_ALM_HOURS0 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_binSTR.Bits.ALM_HOURS0 #define IRTC_ALM_HM_bin_ALM_HOURS1 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_binSTR.Bits.ALM_HOURS1 #define IRTC_ALM_HM_bin_ALM_HOURS2 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_binSTR.Bits.ALM_HOURS2 #define IRTC_ALM_HM_bin_ALM_HOURS3 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_binSTR.Bits.ALM_HOURS3 #define IRTC_ALM_HM_bin_ALM_HOURS4 _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_binSTR.Bits.ALM_HOURS4 #define IRTC_ALM_HM_bin_ALM_MINUTES _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_binSTR.MergedBits.grpALM_MINUTES #define IRTC_ALM_HM_bin_ALM_HOURS _IRTC_ALM_HM_bcd.SameAddr_STR.IRTC_ALM_HM_binSTR.MergedBits.grpALM_HOURS #define IRTC_ALM_HM_bin_ALM_MINUTES0_MASK 1 #define IRTC_ALM_HM_bin_ALM_MINUTES1_MASK 2 #define IRTC_ALM_HM_bin_ALM_MINUTES2_MASK 4 #define IRTC_ALM_HM_bin_ALM_MINUTES3_MASK 8 #define IRTC_ALM_HM_bin_ALM_MINUTES4_MASK 16 #define IRTC_ALM_HM_bin_ALM_MINUTES5_MASK 32 #define IRTC_ALM_HM_bin_ALM_HOURS0_MASK 256 #define IRTC_ALM_HM_bin_ALM_HOURS1_MASK 512 #define IRTC_ALM_HM_bin_ALM_HOURS2_MASK 1024 #define IRTC_ALM_HM_bin_ALM_HOURS3_MASK 2048 #define IRTC_ALM_HM_bin_ALM_HOURS4_MASK 4096 #define IRTC_ALM_HM_bin_ALM_MINUTES_MASK 63 #define IRTC_ALM_HM_bin_ALM_MINUTES_BITNUM 0 #define IRTC_ALM_HM_bin_ALM_HOURS_MASK 7936 #define IRTC_ALM_HM_bin_ALM_HOURS_BITNUM 8 } SameAddr_STR; /*Several registers at the same address */ } IRTC_ALM_HM_bcdSTR; extern volatile IRTC_ALM_HM_bcdSTR _IRTC_ALM_HM_bcd @0xFFFF864C; /*** IRTC_ALM_SEC_bcd - RTC Seconds Alarm Register (BCD format); 0xFFFF864E ***/ typedef union { word Word; union { /* Several registers at the same address */ /*** IRTC_ALM_SEC_bcd - RTC Seconds Alarm Register (BCD format); Several registers at the same address ***/ union { struct { word ALM_SECONDS_units0 :1; /* Seconds setting of the alarm - units, bit 0 */ word ALM_SECONDS_units1 :1; /* Seconds setting of the alarm - units, bit 1 */ word ALM_SECONDS_units2 :1; /* Seconds setting of the alarm - units, bit 2 */ word ALM_SECONDS_units3 :1; /* Seconds setting of the alarm - units, bit 3 */ word ALM_SECONDS_tens0 :1; /* Seconds setting of the alarm - tens, bit 0 */ word ALM_SECONDS_tens1 :1; /* Seconds setting of the alarm - tens, bit 1 */ word ALM_SECONDS_tens2 :1; /* Seconds setting of the alarm - tens, bit 2 */ word ALM_SECONDS_tens3 :1; /* Seconds setting of the alarm - tens, bit 3 */ word DEC_S :1; /* Controls the decrement of seconds counter */ word INC_S :1; /* Controls the increment of seconds counter */ word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpALM_SECONDS_units :4; word grpALM_SECONDS_tens :4; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } IRTC_ALM_SEC_bcdSTR; #define IRTC_ALM_SEC_bcd _IRTC_ALM_SEC_bcd.Word #define IRTC_ALM_SEC_bcd_ALM_SECONDS_units0 _IRTC_ALM_SEC_bcd.SameAddr_STR.IRTC_ALM_SEC_bcdSTR.Bits.ALM_SECONDS_units0 #define IRTC_ALM_SEC_bcd_ALM_SECONDS_units1 _IRTC_ALM_SEC_bcd.SameAddr_STR.IRTC_ALM_SEC_bcdSTR.Bits.ALM_SECONDS_units1 #define IRTC_ALM_SEC_bcd_ALM_SECONDS_units2 _IRTC_ALM_SEC_bcd.SameAddr_STR.IRTC_ALM_SEC_bcdSTR.Bits.ALM_SECONDS_units2 #define IRTC_ALM_SEC_bcd_ALM_SECONDS_units3 _IRTC_ALM_SEC_bcd.SameAddr_STR.IRTC_ALM_SEC_bcdSTR.Bits.ALM_SECONDS_units3 #define IRTC_ALM_SEC_bcd_ALM_SECONDS_tens0 _IRTC_ALM_SEC_bcd.SameAddr_STR.IRTC_ALM_SEC_bcdSTR.Bits.ALM_SECONDS_tens0 #define IRTC_ALM_SEC_bcd_ALM_SECONDS_tens1 _IRTC_ALM_SEC_bcd.SameAddr_STR.IRTC_ALM_SEC_bcdSTR.Bits.ALM_SECONDS_tens1 #define IRTC_ALM_SEC_bcd_ALM_SECONDS_tens2 _IRTC_ALM_SEC_bcd.SameAddr_STR.IRTC_ALM_SEC_bcdSTR.Bits.ALM_SECONDS_tens2 #define IRTC_ALM_SEC_bcd_ALM_SECONDS_tens3 _IRTC_ALM_SEC_bcd.SameAddr_STR.IRTC_ALM_SEC_bcdSTR.Bits.ALM_SECONDS_tens3 #define IRTC_ALM_SEC_bcd_DEC_S _IRTC_ALM_SEC_bcd.SameAddr_STR.IRTC_ALM_SEC_bcdSTR.Bits.DEC_S #define IRTC_ALM_SEC_bcd_INC_S _IRTC_ALM_SEC_bcd.SameAddr_STR.IRTC_ALM_SEC_bcdSTR.Bits.INC_S #define IRTC_ALM_SEC_bcd_ALM_SECONDS_units _IRTC_ALM_SEC_bcd.SameAddr_STR.IRTC_ALM_SEC_bcdSTR.MergedBits.grpALM_SECONDS_units #define IRTC_ALM_SEC_bcd_ALM_SECONDS_tens _IRTC_ALM_SEC_bcd.SameAddr_STR.IRTC_ALM_SEC_bcdSTR.MergedBits.grpALM_SECONDS_tens #define IRTC_ALM_SEC_bcd_ALM_SECONDS_units0_MASK 1 #define IRTC_ALM_SEC_bcd_ALM_SECONDS_units1_MASK 2 #define IRTC_ALM_SEC_bcd_ALM_SECONDS_units2_MASK 4 #define IRTC_ALM_SEC_bcd_ALM_SECONDS_units3_MASK 8 #define IRTC_ALM_SEC_bcd_ALM_SECONDS_tens0_MASK 16 #define IRTC_ALM_SEC_bcd_ALM_SECONDS_tens1_MASK 32 #define IRTC_ALM_SEC_bcd_ALM_SECONDS_tens2_MASK 64 #define IRTC_ALM_SEC_bcd_ALM_SECONDS_tens3_MASK 128 #define IRTC_ALM_SEC_bcd_DEC_S_MASK 256 #define IRTC_ALM_SEC_bcd_INC_S_MASK 512 #define IRTC_ALM_SEC_bcd_ALM_SECONDS_units_MASK 15 #define IRTC_ALM_SEC_bcd_ALM_SECONDS_units_BITNUM 0 #define IRTC_ALM_SEC_bcd_ALM_SECONDS_tens_MASK 240 #define IRTC_ALM_SEC_bcd_ALM_SECONDS_tens_BITNUM 4 /*** IRTC_ALM_SEC_bin - RTC Seconds Alarm Register (binary format); Several registers at the same address ***/ union { struct { word ALM_SECONDS0 :1; /* Seconds setting of the alarm. It can be set to any value between 0 and 59 (0x3B), bit 0 */ word ALM_SECONDS1 :1; /* Seconds setting of the alarm. It can be set to any value between 0 and 59 (0x3B), bit 1 */ word ALM_SECONDS2 :1; /* Seconds setting of the alarm. It can be set to any value between 0 and 59 (0x3B), bit 2 */ word ALM_SECONDS3 :1; /* Seconds setting of the alarm. It can be set to any value between 0 and 59 (0x3B), bit 3 */ word ALM_SECONDS4 :1; /* Seconds setting of the alarm. It can be set to any value between 0 and 59 (0x3B), bit 4 */ word ALM_SECONDS5 :1; /* Seconds setting of the alarm. It can be set to any value between 0 and 59 (0x3B), bit 5 */ word :1; word :1; word DEC_S :1; /* Controls the decrement of seconds counter */ word INC_S :1; /* Controls the increment of seconds counter */ word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpALM_SECONDS :6; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } IRTC_ALM_SEC_binSTR; #define IRTC_ALM_SEC_bin _IRTC_ALM_SEC_bcd.Word #define IRTC_ALM_SEC_bin_ALM_SECONDS0 _IRTC_ALM_SEC_bcd.SameAddr_STR.IRTC_ALM_SEC_binSTR.Bits.ALM_SECONDS0 #define IRTC_ALM_SEC_bin_ALM_SECONDS1 _IRTC_ALM_SEC_bcd.SameAddr_STR.IRTC_ALM_SEC_binSTR.Bits.ALM_SECONDS1 #define IRTC_ALM_SEC_bin_ALM_SECONDS2 _IRTC_ALM_SEC_bcd.SameAddr_STR.IRTC_ALM_SEC_binSTR.Bits.ALM_SECONDS2 #define IRTC_ALM_SEC_bin_ALM_SECONDS3 _IRTC_ALM_SEC_bcd.SameAddr_STR.IRTC_ALM_SEC_binSTR.Bits.ALM_SECONDS3 #define IRTC_ALM_SEC_bin_ALM_SECONDS4 _IRTC_ALM_SEC_bcd.SameAddr_STR.IRTC_ALM_SEC_binSTR.Bits.ALM_SECONDS4 #define IRTC_ALM_SEC_bin_ALM_SECONDS5 _IRTC_ALM_SEC_bcd.SameAddr_STR.IRTC_ALM_SEC_binSTR.Bits.ALM_SECONDS5 #define IRTC_ALM_SEC_bin_DEC_S _IRTC_ALM_SEC_bcd.SameAddr_STR.IRTC_ALM_SEC_binSTR.Bits.DEC_S #define IRTC_ALM_SEC_bin_INC_S _IRTC_ALM_SEC_bcd.SameAddr_STR.IRTC_ALM_SEC_binSTR.Bits.INC_S #define IRTC_ALM_SEC_bin_ALM_SECONDS _IRTC_ALM_SEC_bcd.SameAddr_STR.IRTC_ALM_SEC_binSTR.MergedBits.grpALM_SECONDS #define IRTC_ALM_SEC_bin_ALM_SECONDS0_MASK 1 #define IRTC_ALM_SEC_bin_ALM_SECONDS1_MASK 2 #define IRTC_ALM_SEC_bin_ALM_SECONDS2_MASK 4 #define IRTC_ALM_SEC_bin_ALM_SECONDS3_MASK 8 #define IRTC_ALM_SEC_bin_ALM_SECONDS4_MASK 16 #define IRTC_ALM_SEC_bin_ALM_SECONDS5_MASK 32 #define IRTC_ALM_SEC_bin_DEC_S_MASK 256 #define IRTC_ALM_SEC_bin_INC_S_MASK 512 #define IRTC_ALM_SEC_bin_ALM_SECONDS_MASK 63 #define IRTC_ALM_SEC_bin_ALM_SECONDS_BITNUM 0 } SameAddr_STR; /*Several registers at the same address */ } IRTC_ALM_SEC_bcdSTR; extern volatile IRTC_ALM_SEC_bcdSTR _IRTC_ALM_SEC_bcd @0xFFFF864E; /*** IRTC_CTRL - RTC Control Register; 0xFFFF8650 ***/ typedef union { word Word; struct { word WE0 :1; /* Write enable bits, bit 0 */ word WE1 :1; /* Write enable bits, bit 1 */ word ALARM_MATCH0 :1; /* Alarm match bits, bit 0 */ word ALARM_MATCH1 :1; /* Alarm match bits, bit 1 */ word :1; word :1; word DSTEN :1; /* Daylight saving enable */ word BCDEN :1; /* BCD format enable */ word SWR :1; /* Software reset */ word TAMPER_DETECT_DURATION0 :1; /* Tamper detect duration bits, bit 0 */ word TAMPER_DETECT_DURATION1 :1; /* Tamper detect duration bits, bit 1 */ word TAMPER_DETECT_DURATION2 :1; /* Tamper detect duration bits, bit 2 */ word TAMPER_DETECT_DURATION3 :1; /* Tamper detect duration bits, bit 3 */ word OFF_CHIP_CLK0 :1; /* Off-chip clock output enable bits, bit 0 */ word OFF_CHIP_CLK1 :1; /* Off-chip clock output enable bits, bit 1 */ word OCLK :1; /* Oscillator clock output enable */ } Bits; struct { word grpWE :2; word grpALARM_MATCH :2; word :1; word :1; word :1; word :1; word :1; word grpTAMPER_DETECT_DURATION :4; word grpOFF_CHIP_CLK :2; word :1; } MergedBits; } IRTC_CTRLSTR; extern volatile IRTC_CTRLSTR _IRTC_CTRL @0xFFFF8650; #define IRTC_CTRL _IRTC_CTRL.Word #define IRTC_CTRL_WE0 _IRTC_CTRL.Bits.WE0 #define IRTC_CTRL_WE1 _IRTC_CTRL.Bits.WE1 #define IRTC_CTRL_ALARM_MATCH0 _IRTC_CTRL.Bits.ALARM_MATCH0 #define IRTC_CTRL_ALARM_MATCH1 _IRTC_CTRL.Bits.ALARM_MATCH1 #define IRTC_CTRL_DSTEN _IRTC_CTRL.Bits.DSTEN #define IRTC_CTRL_BCDEN _IRTC_CTRL.Bits.BCDEN #define IRTC_CTRL_SWR _IRTC_CTRL.Bits.SWR #define IRTC_CTRL_TAMPER_DETECT_DURATION0 _IRTC_CTRL.Bits.TAMPER_DETECT_DURATION0 #define IRTC_CTRL_TAMPER_DETECT_DURATION1 _IRTC_CTRL.Bits.TAMPER_DETECT_DURATION1 #define IRTC_CTRL_TAMPER_DETECT_DURATION2 _IRTC_CTRL.Bits.TAMPER_DETECT_DURATION2 #define IRTC_CTRL_TAMPER_DETECT_DURATION3 _IRTC_CTRL.Bits.TAMPER_DETECT_DURATION3 #define IRTC_CTRL_OFF_CHIP_CLK0 _IRTC_CTRL.Bits.OFF_CHIP_CLK0 #define IRTC_CTRL_OFF_CHIP_CLK1 _IRTC_CTRL.Bits.OFF_CHIP_CLK1 #define IRTC_CTRL_OCLK _IRTC_CTRL.Bits.OCLK #define IRTC_CTRL_WE _IRTC_CTRL.MergedBits.grpWE #define IRTC_CTRL_ALARM_MATCH _IRTC_CTRL.MergedBits.grpALARM_MATCH #define IRTC_CTRL_TAMPER_DETECT_DURATION _IRTC_CTRL.MergedBits.grpTAMPER_DETECT_DURATION #define IRTC_CTRL_OFF_CHIP_CLK _IRTC_CTRL.MergedBits.grpOFF_CHIP_CLK #define IRTC_CTRL_WE0_MASK 1 #define IRTC_CTRL_WE1_MASK 2 #define IRTC_CTRL_ALARM_MATCH0_MASK 4 #define IRTC_CTRL_ALARM_MATCH1_MASK 8 #define IRTC_CTRL_DSTEN_MASK 64 #define IRTC_CTRL_BCDEN_MASK 128 #define IRTC_CTRL_SWR_MASK 256 #define IRTC_CTRL_TAMPER_DETECT_DURATION0_MASK 512 #define IRTC_CTRL_TAMPER_DETECT_DURATION1_MASK 1024 #define IRTC_CTRL_TAMPER_DETECT_DURATION2_MASK 2048 #define IRTC_CTRL_TAMPER_DETECT_DURATION3_MASK 4096 #define IRTC_CTRL_OFF_CHIP_CLK0_MASK 8192 #define IRTC_CTRL_OFF_CHIP_CLK1_MASK 16384 #define IRTC_CTRL_OCLK_MASK 32768 #define IRTC_CTRL_WE_MASK 3 #define IRTC_CTRL_WE_BITNUM 0 #define IRTC_CTRL_ALARM_MATCH_MASK 12 #define IRTC_CTRL_ALARM_MATCH_BITNUM 2 #define IRTC_CTRL_TAMPER_DETECT_DURATION_MASK 7680 #define IRTC_CTRL_TAMPER_DETECT_DURATION_BITNUM 9 #define IRTC_CTRL_OFF_CHIP_CLK_MASK 24576 #define IRTC_CTRL_OFF_CHIP_CLK_BITNUM 13 /*** IRTC_STATUS - RTC Status Register; 0xFFFF8652 ***/ typedef union { word Word; struct { word INVAL :1; /* Invalid time bit */ word C_DON :1; /* Compensation one bit */ word BERR :1; /* Bus error bit */ word OCAL :1; /* Calibration output bit or compensation interval bit */ word WPE :1; /* Write protect enable */ word CLV :1; /* CPU low voltage */ word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } Bits; } IRTC_STATUSSTR; extern volatile IRTC_STATUSSTR _IRTC_STATUS @0xFFFF8652; #define IRTC_STATUS _IRTC_STATUS.Word #define IRTC_STATUS_INVAL _IRTC_STATUS.Bits.INVAL #define IRTC_STATUS_C_DON _IRTC_STATUS.Bits.C_DON #define IRTC_STATUS_BERR _IRTC_STATUS.Bits.BERR #define IRTC_STATUS_OCAL _IRTC_STATUS.Bits.OCAL #define IRTC_STATUS_WPE _IRTC_STATUS.Bits.WPE #define IRTC_STATUS_CLV _IRTC_STATUS.Bits.CLV #define IRTC_STATUS_INVAL_MASK 1 #define IRTC_STATUS_C_DON_MASK 2 #define IRTC_STATUS_BERR_MASK 4 #define IRTC_STATUS_OCAL_MASK 8 #define IRTC_STATUS_WPE_MASK 16 #define IRTC_STATUS_CLV_MASK 32 /*** IRTC_ISR - RTC Interrupt Status Register; 0xFFFF8654 ***/ typedef union { word Word; struct { word TMPR :1; /* Tamper detect interrupt */ word STW :1; /* Countdown timer expiry flag */ word ALM :1; /* Alarm flag */ word DAY :1; /* Day flag */ word HR :1; /* Hour flag */ word MIN :1; /* Minutes flag */ word _1HZ :1; /* Interrupt flag 1 Hz. Indicates an interrupt has occurred. If enabled, this bit is set every half a second */ word _2HZ :1; /* Interrupt flag 2 Hz. Indicates an interrupt has occurred. If enabled, this bit is set every half a second */ word SAM0 :1; /* Sampling timer 0 interrupt flag. Indicates than an interrupt has occurred at the corresponding sampling rate */ word SAM1 :1; /* Sampling timer 1 interrupt flag. Indicates than an interrupt has occurred at the corresponding sampling rate */ word SAM2 :1; /* Sampling timer 2 interrupt flag. Indicates than an interrupt has occurred at the corresponding sampling rate */ word SAM3 :1; /* Sampling timer 3 interrupt flag. Indicates than an interrupt has occurred at the corresponding sampling rate */ word SAM4 :1; /* Sampling timer 4 interrupt flag. Indicates than an interrupt has occurred at the corresponding sampling rate */ word SAM5 :1; /* Sampling timer 5 interrupt flag. Indicates than an interrupt has occurred at the corresponding sampling rate */ word SAM6 :1; /* Sampling timer 6 interrupt flag. Indicates than an interrupt has occurred at the corresponding sampling rate */ word SAM7 :1; /* Sampling timer 7 interrupt flag. Indicates than an interrupt has occurred at the corresponding sampling rate */ } Bits; struct { word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word grpSAM :8; } MergedBits; } IRTC_ISRSTR; extern volatile IRTC_ISRSTR _IRTC_ISR @0xFFFF8654; #define IRTC_ISR _IRTC_ISR.Word #define IRTC_ISR_TMPR _IRTC_ISR.Bits.TMPR #define IRTC_ISR_STW _IRTC_ISR.Bits.STW #define IRTC_ISR_ALM _IRTC_ISR.Bits.ALM #define IRTC_ISR_DAY _IRTC_ISR.Bits.DAY #define IRTC_ISR_HR _IRTC_ISR.Bits.HR #define IRTC_ISR_MIN _IRTC_ISR.Bits.MIN #define IRTC_ISR_1HZ _IRTC_ISR.Bits._1HZ #define IRTC_ISR_2HZ _IRTC_ISR.Bits._2HZ #define IRTC_ISR_SAM0 _IRTC_ISR.Bits.SAM0 #define IRTC_ISR_SAM1 _IRTC_ISR.Bits.SAM1 #define IRTC_ISR_SAM2 _IRTC_ISR.Bits.SAM2 #define IRTC_ISR_SAM3 _IRTC_ISR.Bits.SAM3 #define IRTC_ISR_SAM4 _IRTC_ISR.Bits.SAM4 #define IRTC_ISR_SAM5 _IRTC_ISR.Bits.SAM5 #define IRTC_ISR_SAM6 _IRTC_ISR.Bits.SAM6 #define IRTC_ISR_SAM7 _IRTC_ISR.Bits.SAM7 #define IRTC_ISR_SAM _IRTC_ISR.MergedBits.grpSAM #define IRTC_ISR_TMPR_MASK 1 #define IRTC_ISR_STW_MASK 2 #define IRTC_ISR_ALM_MASK 4 #define IRTC_ISR_DAY_MASK 8 #define IRTC_ISR_HR_MASK 16 #define IRTC_ISR_MIN_MASK 32 #define IRTC_ISR_1HZ_MASK 64 #define IRTC_ISR_2HZ_MASK 128 #define IRTC_ISR_SAM0_MASK 256 #define IRTC_ISR_SAM1_MASK 512 #define IRTC_ISR_SAM2_MASK 1024 #define IRTC_ISR_SAM3_MASK 2048 #define IRTC_ISR_SAM4_MASK 4096 #define IRTC_ISR_SAM5_MASK 8192 #define IRTC_ISR_SAM6_MASK 16384 #define IRTC_ISR_SAM7_MASK 32768 #define IRTC_ISR_SAM_MASK 65280 #define IRTC_ISR_SAM_BITNUM 8 /*** IRTC_IER - RTC Interrupt Enable Register; 0xFFFF8656 ***/ typedef union { word Word; struct { word TMPR :1; /* Tamper detect interrupt */ word STW :1; /* Countdown timer expiry flag */ word ALM :1; /* Alarm flag */ word DAY :1; /* Day flag */ word HR :1; /* Hour flag */ word MIN :1; /* Minutes flag */ word _1HZ :1; /* Sampling timer interrupt at 1 Hz frequency */ word _2HZ :1; /* Sampling timer interrupt at 2 Hz frequency */ word SAM0 :1; /* Sampling timer 0 interrupt enable */ word SAM1 :1; /* Sampling timer 1 interrupt enable */ word SAM2 :1; /* Sampling timer 2 interrupt enable */ word SAM3 :1; /* Sampling timer 3 interrupt enable */ word SAM4 :1; /* Sampling timer 4 interrupt enable */ word SAM5 :1; /* Sampling timer 5 interrupt enable */ word SAM6 :1; /* Sampling timer 6 interrupt enable */ word SAM7 :1; /* Sampling timer 7 interrupt enable */ } Bits; struct { word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word grpSAM :8; } MergedBits; } IRTC_IERSTR; extern volatile IRTC_IERSTR _IRTC_IER @0xFFFF8656; #define IRTC_IER _IRTC_IER.Word #define IRTC_IER_TMPR _IRTC_IER.Bits.TMPR #define IRTC_IER_STW _IRTC_IER.Bits.STW #define IRTC_IER_ALM _IRTC_IER.Bits.ALM #define IRTC_IER_DAY _IRTC_IER.Bits.DAY #define IRTC_IER_HR _IRTC_IER.Bits.HR #define IRTC_IER_MIN _IRTC_IER.Bits.MIN #define IRTC_IER_1HZ _IRTC_IER.Bits._1HZ #define IRTC_IER_2HZ _IRTC_IER.Bits._2HZ #define IRTC_IER_SAM0 _IRTC_IER.Bits.SAM0 #define IRTC_IER_SAM1 _IRTC_IER.Bits.SAM1 #define IRTC_IER_SAM2 _IRTC_IER.Bits.SAM2 #define IRTC_IER_SAM3 _IRTC_IER.Bits.SAM3 #define IRTC_IER_SAM4 _IRTC_IER.Bits.SAM4 #define IRTC_IER_SAM5 _IRTC_IER.Bits.SAM5 #define IRTC_IER_SAM6 _IRTC_IER.Bits.SAM6 #define IRTC_IER_SAM7 _IRTC_IER.Bits.SAM7 #define IRTC_IER_SAM _IRTC_IER.MergedBits.grpSAM #define IRTC_IER_TMPR_MASK 1 #define IRTC_IER_STW_MASK 2 #define IRTC_IER_ALM_MASK 4 #define IRTC_IER_DAY_MASK 8 #define IRTC_IER_HR_MASK 16 #define IRTC_IER_MIN_MASK 32 #define IRTC_IER_1HZ_MASK 64 #define IRTC_IER_2HZ_MASK 128 #define IRTC_IER_SAM0_MASK 256 #define IRTC_IER_SAM1_MASK 512 #define IRTC_IER_SAM2_MASK 1024 #define IRTC_IER_SAM3_MASK 2048 #define IRTC_IER_SAM4_MASK 4096 #define IRTC_IER_SAM5_MASK 8192 #define IRTC_IER_SAM6_MASK 16384 #define IRTC_IER_SAM7_MASK 32768 #define IRTC_IER_SAM_MASK 65280 #define IRTC_IER_SAM_BITNUM 8 /*** IRTC_COUNT_DN_bcd - RTC Countdown (Minutes) Timer Register (BCD format); 0xFFFF8658 ***/ typedef union { word Word; union { /* Several registers at the same address */ /*** IRTC_COUNT_DN_bcd - RTC Countdown (Minutes) Timer Register (BCD format); Several registers at the same address ***/ union { struct { word COUNTDOWN_COUNT_units0 :1; /* Countdown counter value bits - units, bit 0 */ word COUNTDOWN_COUNT_units1 :1; /* Countdown counter value bits - units, bit 1 */ word COUNTDOWN_COUNT_units2 :1; /* Countdown counter value bits - units, bit 2 */ word COUNTDOWN_COUNT_units3 :1; /* Countdown counter value bits - units, bit 3 */ word COUNTDOWN_COUNT_tens0 :1; /* Countdown counter value bits - tens, bit 0 */ word COUNTDOWN_COUNT_tens1 :1; /* Countdown counter value bits - tens, bit 1 */ word COUNTDOWN_COUNT_tens2 :1; /* Countdown counter value bits - tens, bit 2 */ word COUNTDOWN_COUNT_tens3 :1; /* Countdown counter value bits - tens, bit 3 */ word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpCOUNTDOWN_COUNT_units :4; word grpCOUNTDOWN_COUNT_tens :4; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } IRTC_COUNT_DN_bcdSTR; #define IRTC_COUNT_DN_bcd _IRTC_COUNT_DN_bcd.Word #define IRTC_COUNT_DN_bcd_COUNTDOWN_COUNT_units0 _IRTC_COUNT_DN_bcd.SameAddr_STR.IRTC_COUNT_DN_bcdSTR.Bits.COUNTDOWN_COUNT_units0 #define IRTC_COUNT_DN_bcd_COUNTDOWN_COUNT_units1 _IRTC_COUNT_DN_bcd.SameAddr_STR.IRTC_COUNT_DN_bcdSTR.Bits.COUNTDOWN_COUNT_units1 #define IRTC_COUNT_DN_bcd_COUNTDOWN_COUNT_units2 _IRTC_COUNT_DN_bcd.SameAddr_STR.IRTC_COUNT_DN_bcdSTR.Bits.COUNTDOWN_COUNT_units2 #define IRTC_COUNT_DN_bcd_COUNTDOWN_COUNT_units3 _IRTC_COUNT_DN_bcd.SameAddr_STR.IRTC_COUNT_DN_bcdSTR.Bits.COUNTDOWN_COUNT_units3 #define IRTC_COUNT_DN_bcd_COUNTDOWN_COUNT_tens0 _IRTC_COUNT_DN_bcd.SameAddr_STR.IRTC_COUNT_DN_bcdSTR.Bits.COUNTDOWN_COUNT_tens0 #define IRTC_COUNT_DN_bcd_COUNTDOWN_COUNT_tens1 _IRTC_COUNT_DN_bcd.SameAddr_STR.IRTC_COUNT_DN_bcdSTR.Bits.COUNTDOWN_COUNT_tens1 #define IRTC_COUNT_DN_bcd_COUNTDOWN_COUNT_tens2 _IRTC_COUNT_DN_bcd.SameAddr_STR.IRTC_COUNT_DN_bcdSTR.Bits.COUNTDOWN_COUNT_tens2 #define IRTC_COUNT_DN_bcd_COUNTDOWN_COUNT_tens3 _IRTC_COUNT_DN_bcd.SameAddr_STR.IRTC_COUNT_DN_bcdSTR.Bits.COUNTDOWN_COUNT_tens3 #define IRTC_COUNT_DN_bcd_COUNTDOWN_COUNT_units _IRTC_COUNT_DN_bcd.SameAddr_STR.IRTC_COUNT_DN_bcdSTR.MergedBits.grpCOUNTDOWN_COUNT_units #define IRTC_COUNT_DN_bcd_COUNTDOWN_COUNT_tens _IRTC_COUNT_DN_bcd.SameAddr_STR.IRTC_COUNT_DN_bcdSTR.MergedBits.grpCOUNTDOWN_COUNT_tens #define IRTC_COUNT_DN_bcd_COUNTDOWN_COUNT_units0_MASK 1 #define IRTC_COUNT_DN_bcd_COUNTDOWN_COUNT_units1_MASK 2 #define IRTC_COUNT_DN_bcd_COUNTDOWN_COUNT_units2_MASK 4 #define IRTC_COUNT_DN_bcd_COUNTDOWN_COUNT_units3_MASK 8 #define IRTC_COUNT_DN_bcd_COUNTDOWN_COUNT_tens0_MASK 16 #define IRTC_COUNT_DN_bcd_COUNTDOWN_COUNT_tens1_MASK 32 #define IRTC_COUNT_DN_bcd_COUNTDOWN_COUNT_tens2_MASK 64 #define IRTC_COUNT_DN_bcd_COUNTDOWN_COUNT_tens3_MASK 128 #define IRTC_COUNT_DN_bcd_COUNTDOWN_COUNT_units_MASK 15 #define IRTC_COUNT_DN_bcd_COUNTDOWN_COUNT_units_BITNUM 0 #define IRTC_COUNT_DN_bcd_COUNTDOWN_COUNT_tens_MASK 240 #define IRTC_COUNT_DN_bcd_COUNTDOWN_COUNT_tens_BITNUM 4 /*** IRTC_COUNT_DN_bin - RTC Countdown (Minutes) Timer Register (binary format); Several registers at the same address ***/ union { struct { word COUNTDOWN_COUNT0 :1; /* Countdown counter value bits, bit 0 */ word COUNTDOWN_COUNT1 :1; /* Countdown counter value bits, bit 1 */ word COUNTDOWN_COUNT2 :1; /* Countdown counter value bits, bit 2 */ word COUNTDOWN_COUNT3 :1; /* Countdown counter value bits, bit 3 */ word COUNTDOWN_COUNT4 :1; /* Countdown counter value bits, bit 4 */ word COUNTDOWN_COUNT5 :1; /* Countdown counter value bits, bit 5 */ word COUNTDOWN_COUNT6 :1; /* Countdown counter value bits, bit 6 */ word COUNTDOWN_COUNT7 :1; /* Countdown counter value bits, bit 7 */ word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpCOUNTDOWN_COUNT :8; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } IRTC_COUNT_DN_binSTR; #define IRTC_COUNT_DN_bin _IRTC_COUNT_DN_bcd.Word #define IRTC_COUNT_DN_bin_COUNTDOWN_COUNT0 _IRTC_COUNT_DN_bcd.SameAddr_STR.IRTC_COUNT_DN_binSTR.Bits.COUNTDOWN_COUNT0 #define IRTC_COUNT_DN_bin_COUNTDOWN_COUNT1 _IRTC_COUNT_DN_bcd.SameAddr_STR.IRTC_COUNT_DN_binSTR.Bits.COUNTDOWN_COUNT1 #define IRTC_COUNT_DN_bin_COUNTDOWN_COUNT2 _IRTC_COUNT_DN_bcd.SameAddr_STR.IRTC_COUNT_DN_binSTR.Bits.COUNTDOWN_COUNT2 #define IRTC_COUNT_DN_bin_COUNTDOWN_COUNT3 _IRTC_COUNT_DN_bcd.SameAddr_STR.IRTC_COUNT_DN_binSTR.Bits.COUNTDOWN_COUNT3 #define IRTC_COUNT_DN_bin_COUNTDOWN_COUNT4 _IRTC_COUNT_DN_bcd.SameAddr_STR.IRTC_COUNT_DN_binSTR.Bits.COUNTDOWN_COUNT4 #define IRTC_COUNT_DN_bin_COUNTDOWN_COUNT5 _IRTC_COUNT_DN_bcd.SameAddr_STR.IRTC_COUNT_DN_binSTR.Bits.COUNTDOWN_COUNT5 #define IRTC_COUNT_DN_bin_COUNTDOWN_COUNT6 _IRTC_COUNT_DN_bcd.SameAddr_STR.IRTC_COUNT_DN_binSTR.Bits.COUNTDOWN_COUNT6 #define IRTC_COUNT_DN_bin_COUNTDOWN_COUNT7 _IRTC_COUNT_DN_bcd.SameAddr_STR.IRTC_COUNT_DN_binSTR.Bits.COUNTDOWN_COUNT7 #define IRTC_COUNT_DN_bin_COUNTDOWN_COUNT _IRTC_COUNT_DN_bcd.SameAddr_STR.IRTC_COUNT_DN_binSTR.MergedBits.grpCOUNTDOWN_COUNT #define IRTC_COUNT_DN_bin_COUNTDOWN_COUNT0_MASK 1 #define IRTC_COUNT_DN_bin_COUNTDOWN_COUNT1_MASK 2 #define IRTC_COUNT_DN_bin_COUNTDOWN_COUNT2_MASK 4 #define IRTC_COUNT_DN_bin_COUNTDOWN_COUNT3_MASK 8 #define IRTC_COUNT_DN_bin_COUNTDOWN_COUNT4_MASK 16 #define IRTC_COUNT_DN_bin_COUNTDOWN_COUNT5_MASK 32 #define IRTC_COUNT_DN_bin_COUNTDOWN_COUNT6_MASK 64 #define IRTC_COUNT_DN_bin_COUNTDOWN_COUNT7_MASK 128 #define IRTC_COUNT_DN_bin_COUNTDOWN_COUNT_MASK 255 #define IRTC_COUNT_DN_bin_COUNTDOWN_COUNT_BITNUM 0 } SameAddr_STR; /*Several registers at the same address */ } IRTC_COUNT_DN_bcdSTR; extern volatile IRTC_COUNT_DN_bcdSTR _IRTC_COUNT_DN_bcd @0xFFFF8658; /*** IRTC_CFG_DATA - RTC Configuration Data Register; 0xFFFF8660 ***/ typedef union { word Word; struct { word CFG0 :1; /* Directly output from RTC bit 0 */ word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } Bits; } IRTC_CFG_DATASTR; extern volatile IRTC_CFG_DATASTR _IRTC_CFG_DATA @0xFFFF8660; #define IRTC_CFG_DATA _IRTC_CFG_DATA.Word #define IRTC_CFG_DATA_CFG0 _IRTC_CFG_DATA.Bits.CFG0 #define IRTC_CFG_DATA_CFG0_MASK 1 /*** IRTC_DST_HOUR_bcd - RTC Daylight Saving Hour Register; 0xFFFF8662 ***/ typedef union { word Word; union { /* Several registers at the same address */ /*** IRTC_DST_HOUR_bcd - RTC Daylight Saving Hour Register; Several registers at the same address ***/ union { struct { word DST_END_HOUR_units0 :1; /* Hour units value when daylight saving has to end bits, bit 0 */ word DST_END_HOUR_units1 :1; /* Hour units value when daylight saving has to end bits, bit 1 */ word DST_END_HOUR_units2 :1; /* Hour units value when daylight saving has to end bits, bit 2 */ word DST_END_HOUR_units3 :1; /* Hour units value when daylight saving has to end bits, bit 3 */ word DST_END_HOUR_tens0 :1; /* Hour tens value when daylight saving has to end bits, bit 0 */ word DST_END_HOUR_tens1 :1; /* Hour tens value when daylight saving has to end bits, bit 1 */ word DST_END_HOUR_tens2 :1; /* Hour tens value when daylight saving has to end bits, bit 2 */ word DST_END_HOUR_tens3 :1; /* Hour tens value when daylight saving has to end bits, bit 3 */ word DST_START_HOUR_units0 :1; /* Hour units value when daylight saving has to start bits, bit 0 */ word DST_START_HOUR_units1 :1; /* Hour units value when daylight saving has to start bits, bit 1 */ word DST_START_HOUR_units2 :1; /* Hour units value when daylight saving has to start bits, bit 2 */ word DST_START_HOUR_units3 :1; /* Hour units value when daylight saving has to start bits, bit 3 */ word DST_START_HOUR_tens0 :1; /* Hour tens value when daylight saving has to start bits, bit 0 */ word DST_START_HOUR_tens1 :1; /* Hour tens value when daylight saving has to start bits, bit 1 */ word DST_START_HOUR_tens2 :1; /* Hour tens value when daylight saving has to start bits, bit 2 */ word DST_START_HOUR_tens3 :1; /* Hour tens value when daylight saving has to start bits, bit 3 */ } Bits; struct { word grpDST_END_HOUR_units :4; word grpDST_END_HOUR_tens :4; word grpDST_START_HOUR_units :4; word grpDST_START_HOUR_tens :4; } MergedBits; } IRTC_DST_HOUR_bcdSTR; #define IRTC_DST_HOUR_bcd _IRTC_DST_HOUR_bcd.Word #define IRTC_DST_HOUR_bcd_DST_END_HOUR_units0 _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_bcdSTR.Bits.DST_END_HOUR_units0 #define IRTC_DST_HOUR_bcd_DST_END_HOUR_units1 _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_bcdSTR.Bits.DST_END_HOUR_units1 #define IRTC_DST_HOUR_bcd_DST_END_HOUR_units2 _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_bcdSTR.Bits.DST_END_HOUR_units2 #define IRTC_DST_HOUR_bcd_DST_END_HOUR_units3 _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_bcdSTR.Bits.DST_END_HOUR_units3 #define IRTC_DST_HOUR_bcd_DST_END_HOUR_tens0 _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_bcdSTR.Bits.DST_END_HOUR_tens0 #define IRTC_DST_HOUR_bcd_DST_END_HOUR_tens1 _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_bcdSTR.Bits.DST_END_HOUR_tens1 #define IRTC_DST_HOUR_bcd_DST_END_HOUR_tens2 _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_bcdSTR.Bits.DST_END_HOUR_tens2 #define IRTC_DST_HOUR_bcd_DST_END_HOUR_tens3 _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_bcdSTR.Bits.DST_END_HOUR_tens3 #define IRTC_DST_HOUR_bcd_DST_START_HOUR_units0 _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_bcdSTR.Bits.DST_START_HOUR_units0 #define IRTC_DST_HOUR_bcd_DST_START_HOUR_units1 _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_bcdSTR.Bits.DST_START_HOUR_units1 #define IRTC_DST_HOUR_bcd_DST_START_HOUR_units2 _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_bcdSTR.Bits.DST_START_HOUR_units2 #define IRTC_DST_HOUR_bcd_DST_START_HOUR_units3 _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_bcdSTR.Bits.DST_START_HOUR_units3 #define IRTC_DST_HOUR_bcd_DST_START_HOUR_tens0 _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_bcdSTR.Bits.DST_START_HOUR_tens0 #define IRTC_DST_HOUR_bcd_DST_START_HOUR_tens1 _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_bcdSTR.Bits.DST_START_HOUR_tens1 #define IRTC_DST_HOUR_bcd_DST_START_HOUR_tens2 _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_bcdSTR.Bits.DST_START_HOUR_tens2 #define IRTC_DST_HOUR_bcd_DST_START_HOUR_tens3 _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_bcdSTR.Bits.DST_START_HOUR_tens3 #define IRTC_DST_HOUR_bcd_DST_END_HOUR_units _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_bcdSTR.MergedBits.grpDST_END_HOUR_units #define IRTC_DST_HOUR_bcd_DST_END_HOUR_tens _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_bcdSTR.MergedBits.grpDST_END_HOUR_tens #define IRTC_DST_HOUR_bcd_DST_START_HOUR_units _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_bcdSTR.MergedBits.grpDST_START_HOUR_units #define IRTC_DST_HOUR_bcd_DST_START_HOUR_tens _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_bcdSTR.MergedBits.grpDST_START_HOUR_tens #define IRTC_DST_HOUR_bcd_DST_END_HOUR_units0_MASK 1 #define IRTC_DST_HOUR_bcd_DST_END_HOUR_units1_MASK 2 #define IRTC_DST_HOUR_bcd_DST_END_HOUR_units2_MASK 4 #define IRTC_DST_HOUR_bcd_DST_END_HOUR_units3_MASK 8 #define IRTC_DST_HOUR_bcd_DST_END_HOUR_tens0_MASK 16 #define IRTC_DST_HOUR_bcd_DST_END_HOUR_tens1_MASK 32 #define IRTC_DST_HOUR_bcd_DST_END_HOUR_tens2_MASK 64 #define IRTC_DST_HOUR_bcd_DST_END_HOUR_tens3_MASK 128 #define IRTC_DST_HOUR_bcd_DST_START_HOUR_units0_MASK 256 #define IRTC_DST_HOUR_bcd_DST_START_HOUR_units1_MASK 512 #define IRTC_DST_HOUR_bcd_DST_START_HOUR_units2_MASK 1024 #define IRTC_DST_HOUR_bcd_DST_START_HOUR_units3_MASK 2048 #define IRTC_DST_HOUR_bcd_DST_START_HOUR_tens0_MASK 4096 #define IRTC_DST_HOUR_bcd_DST_START_HOUR_tens1_MASK 8192 #define IRTC_DST_HOUR_bcd_DST_START_HOUR_tens2_MASK 16384 #define IRTC_DST_HOUR_bcd_DST_START_HOUR_tens3_MASK 32768 #define IRTC_DST_HOUR_bcd_DST_END_HOUR_units_MASK 15 #define IRTC_DST_HOUR_bcd_DST_END_HOUR_units_BITNUM 0 #define IRTC_DST_HOUR_bcd_DST_END_HOUR_tens_MASK 240 #define IRTC_DST_HOUR_bcd_DST_END_HOUR_tens_BITNUM 4 #define IRTC_DST_HOUR_bcd_DST_START_HOUR_units_MASK 3840 #define IRTC_DST_HOUR_bcd_DST_START_HOUR_units_BITNUM 8 #define IRTC_DST_HOUR_bcd_DST_START_HOUR_tens_MASK 61440 #define IRTC_DST_HOUR_bcd_DST_START_HOUR_tens_BITNUM 12 /*** IRTC_DST_HOUR_bin - RTC Daylight Saving Hour Register; Several registers at the same address ***/ union { struct { word DST_END_HOUR0 :1; /* Hour value when daylight saving has to end bits, bit 0 */ word DST_END_HOUR1 :1; /* Hour value when daylight saving has to end bits, bit 1 */ word DST_END_HOUR2 :1; /* Hour value when daylight saving has to end bits, bit 2 */ word DST_END_HOUR3 :1; /* Hour value when daylight saving has to end bits, bit 3 */ word DST_END_HOUR4 :1; /* Hour value when daylight saving has to end bits, bit 4 */ word :1; word :1; word :1; word DST_START_HOUR0 :1; /* Hour value when daylight saving has to start bits, bit 0 */ word DST_START_HOUR1 :1; /* Hour value when daylight saving has to start bits, bit 1 */ word DST_START_HOUR2 :1; /* Hour value when daylight saving has to start bits, bit 2 */ word DST_START_HOUR3 :1; /* Hour value when daylight saving has to start bits, bit 3 */ word DST_START_HOUR4 :1; /* Hour value when daylight saving has to start bits, bit 4 */ word :1; word :1; word :1; } Bits; struct { word grpDST_END_HOUR :5; word :1; word :1; word :1; word grpDST_START_HOUR :5; word :1; word :1; word :1; } MergedBits; } IRTC_DST_HOUR_binSTR; #define IRTC_DST_HOUR_bin _IRTC_DST_HOUR_bcd.Word #define IRTC_DST_HOUR_bin_DST_END_HOUR0 _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_binSTR.Bits.DST_END_HOUR0 #define IRTC_DST_HOUR_bin_DST_END_HOUR1 _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_binSTR.Bits.DST_END_HOUR1 #define IRTC_DST_HOUR_bin_DST_END_HOUR2 _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_binSTR.Bits.DST_END_HOUR2 #define IRTC_DST_HOUR_bin_DST_END_HOUR3 _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_binSTR.Bits.DST_END_HOUR3 #define IRTC_DST_HOUR_bin_DST_END_HOUR4 _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_binSTR.Bits.DST_END_HOUR4 #define IRTC_DST_HOUR_bin_DST_START_HOUR0 _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_binSTR.Bits.DST_START_HOUR0 #define IRTC_DST_HOUR_bin_DST_START_HOUR1 _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_binSTR.Bits.DST_START_HOUR1 #define IRTC_DST_HOUR_bin_DST_START_HOUR2 _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_binSTR.Bits.DST_START_HOUR2 #define IRTC_DST_HOUR_bin_DST_START_HOUR3 _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_binSTR.Bits.DST_START_HOUR3 #define IRTC_DST_HOUR_bin_DST_START_HOUR4 _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_binSTR.Bits.DST_START_HOUR4 #define IRTC_DST_HOUR_bin_DST_END_HOUR _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_binSTR.MergedBits.grpDST_END_HOUR #define IRTC_DST_HOUR_bin_DST_START_HOUR _IRTC_DST_HOUR_bcd.SameAddr_STR.IRTC_DST_HOUR_binSTR.MergedBits.grpDST_START_HOUR #define IRTC_DST_HOUR_bin_DST_END_HOUR0_MASK 1 #define IRTC_DST_HOUR_bin_DST_END_HOUR1_MASK 2 #define IRTC_DST_HOUR_bin_DST_END_HOUR2_MASK 4 #define IRTC_DST_HOUR_bin_DST_END_HOUR3_MASK 8 #define IRTC_DST_HOUR_bin_DST_END_HOUR4_MASK 16 #define IRTC_DST_HOUR_bin_DST_START_HOUR0_MASK 256 #define IRTC_DST_HOUR_bin_DST_START_HOUR1_MASK 512 #define IRTC_DST_HOUR_bin_DST_START_HOUR2_MASK 1024 #define IRTC_DST_HOUR_bin_DST_START_HOUR3_MASK 2048 #define IRTC_DST_HOUR_bin_DST_START_HOUR4_MASK 4096 #define IRTC_DST_HOUR_bin_DST_END_HOUR_MASK 31 #define IRTC_DST_HOUR_bin_DST_END_HOUR_BITNUM 0 #define IRTC_DST_HOUR_bin_DST_START_HOUR_MASK 7936 #define IRTC_DST_HOUR_bin_DST_START_HOUR_BITNUM 8 } SameAddr_STR; /*Several registers at the same address */ } IRTC_DST_HOUR_bcdSTR; extern volatile IRTC_DST_HOUR_bcdSTR _IRTC_DST_HOUR_bcd @0xFFFF8662; /*** IRTC_DST_MNTH_bcd - RTC Daylight Saving Month Register; 0xFFFF8664 ***/ typedef union { word Word; union { /* Several registers at the same address */ /*** IRTC_DST_MNTH_bcd - RTC Daylight Saving Month Register; Several registers at the same address ***/ union { struct { word DST_END_MONTH_units0 :1; /* Month units value when daylight saving has to end bits, bit 0 */ word DST_END_MONTH_units1 :1; /* Month units value when daylight saving has to end bits, bit 1 */ word DST_END_MONTH_units2 :1; /* Month units value when daylight saving has to end bits, bit 2 */ word DST_END_MONTH_units3 :1; /* Month units value when daylight saving has to end bits, bit 3 */ word DST_END_MONTH_tens0 :1; /* Month tens value when daylight saving has to end bits, bit 0 */ word DST_END_MONTH_tens1 :1; /* Month tens value when daylight saving has to end bits, bit 1 */ word DST_END_MONTH_tens2 :1; /* Month tens value when daylight saving has to end bits, bit 2 */ word DST_END_MONTH_tens3 :1; /* Month tens value when daylight saving has to end bits, bit 3 */ word DST_START_MONTH_units0 :1; /* Month units value when daylight saving has to start bits, bit 0 */ word DST_START_MONTH_units1 :1; /* Month units value when daylight saving has to start bits, bit 1 */ word DST_START_MONTH_units2 :1; /* Month units value when daylight saving has to start bits, bit 2 */ word DST_START_MONTH_units3 :1; /* Month units value when daylight saving has to start bits, bit 3 */ word DST_START_MONTH_tens0 :1; /* Month tens value when daylight saving has to start bits, bit 0 */ word DST_START_MONTH_tens1 :1; /* Month tens value when daylight saving has to start bits, bit 1 */ word DST_START_MONTH_tens2 :1; /* Month tens value when daylight saving has to start bits, bit 2 */ word DST_START_MONTH_tens3 :1; /* Month tens value when daylight saving has to start bits, bit 3 */ } Bits; struct { word grpDST_END_MONTH_units :4; word grpDST_END_MONTH_tens :4; word grpDST_START_MONTH_units :4; word grpDST_START_MONTH_tens :4; } MergedBits; } IRTC_DST_MNTH_bcdSTR; #define IRTC_DST_MNTH_bcd _IRTC_DST_MNTH_bcd.Word #define IRTC_DST_MNTH_bcd_DST_END_MONTH_units0 _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_bcdSTR.Bits.DST_END_MONTH_units0 #define IRTC_DST_MNTH_bcd_DST_END_MONTH_units1 _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_bcdSTR.Bits.DST_END_MONTH_units1 #define IRTC_DST_MNTH_bcd_DST_END_MONTH_units2 _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_bcdSTR.Bits.DST_END_MONTH_units2 #define IRTC_DST_MNTH_bcd_DST_END_MONTH_units3 _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_bcdSTR.Bits.DST_END_MONTH_units3 #define IRTC_DST_MNTH_bcd_DST_END_MONTH_tens0 _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_bcdSTR.Bits.DST_END_MONTH_tens0 #define IRTC_DST_MNTH_bcd_DST_END_MONTH_tens1 _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_bcdSTR.Bits.DST_END_MONTH_tens1 #define IRTC_DST_MNTH_bcd_DST_END_MONTH_tens2 _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_bcdSTR.Bits.DST_END_MONTH_tens2 #define IRTC_DST_MNTH_bcd_DST_END_MONTH_tens3 _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_bcdSTR.Bits.DST_END_MONTH_tens3 #define IRTC_DST_MNTH_bcd_DST_START_MONTH_units0 _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_bcdSTR.Bits.DST_START_MONTH_units0 #define IRTC_DST_MNTH_bcd_DST_START_MONTH_units1 _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_bcdSTR.Bits.DST_START_MONTH_units1 #define IRTC_DST_MNTH_bcd_DST_START_MONTH_units2 _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_bcdSTR.Bits.DST_START_MONTH_units2 #define IRTC_DST_MNTH_bcd_DST_START_MONTH_units3 _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_bcdSTR.Bits.DST_START_MONTH_units3 #define IRTC_DST_MNTH_bcd_DST_START_MONTH_tens0 _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_bcdSTR.Bits.DST_START_MONTH_tens0 #define IRTC_DST_MNTH_bcd_DST_START_MONTH_tens1 _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_bcdSTR.Bits.DST_START_MONTH_tens1 #define IRTC_DST_MNTH_bcd_DST_START_MONTH_tens2 _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_bcdSTR.Bits.DST_START_MONTH_tens2 #define IRTC_DST_MNTH_bcd_DST_START_MONTH_tens3 _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_bcdSTR.Bits.DST_START_MONTH_tens3 #define IRTC_DST_MNTH_bcd_DST_END_MONTH_units _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_bcdSTR.MergedBits.grpDST_END_MONTH_units #define IRTC_DST_MNTH_bcd_DST_END_MONTH_tens _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_bcdSTR.MergedBits.grpDST_END_MONTH_tens #define IRTC_DST_MNTH_bcd_DST_START_MONTH_units _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_bcdSTR.MergedBits.grpDST_START_MONTH_units #define IRTC_DST_MNTH_bcd_DST_START_MONTH_tens _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_bcdSTR.MergedBits.grpDST_START_MONTH_tens #define IRTC_DST_MNTH_bcd_DST_END_MONTH_units0_MASK 1 #define IRTC_DST_MNTH_bcd_DST_END_MONTH_units1_MASK 2 #define IRTC_DST_MNTH_bcd_DST_END_MONTH_units2_MASK 4 #define IRTC_DST_MNTH_bcd_DST_END_MONTH_units3_MASK 8 #define IRTC_DST_MNTH_bcd_DST_END_MONTH_tens0_MASK 16 #define IRTC_DST_MNTH_bcd_DST_END_MONTH_tens1_MASK 32 #define IRTC_DST_MNTH_bcd_DST_END_MONTH_tens2_MASK 64 #define IRTC_DST_MNTH_bcd_DST_END_MONTH_tens3_MASK 128 #define IRTC_DST_MNTH_bcd_DST_START_MONTH_units0_MASK 256 #define IRTC_DST_MNTH_bcd_DST_START_MONTH_units1_MASK 512 #define IRTC_DST_MNTH_bcd_DST_START_MONTH_units2_MASK 1024 #define IRTC_DST_MNTH_bcd_DST_START_MONTH_units3_MASK 2048 #define IRTC_DST_MNTH_bcd_DST_START_MONTH_tens0_MASK 4096 #define IRTC_DST_MNTH_bcd_DST_START_MONTH_tens1_MASK 8192 #define IRTC_DST_MNTH_bcd_DST_START_MONTH_tens2_MASK 16384 #define IRTC_DST_MNTH_bcd_DST_START_MONTH_tens3_MASK 32768 #define IRTC_DST_MNTH_bcd_DST_END_MONTH_units_MASK 15 #define IRTC_DST_MNTH_bcd_DST_END_MONTH_units_BITNUM 0 #define IRTC_DST_MNTH_bcd_DST_END_MONTH_tens_MASK 240 #define IRTC_DST_MNTH_bcd_DST_END_MONTH_tens_BITNUM 4 #define IRTC_DST_MNTH_bcd_DST_START_MONTH_units_MASK 3840 #define IRTC_DST_MNTH_bcd_DST_START_MONTH_units_BITNUM 8 #define IRTC_DST_MNTH_bcd_DST_START_MONTH_tens_MASK 61440 #define IRTC_DST_MNTH_bcd_DST_START_MONTH_tens_BITNUM 12 /*** IRTC_DST_MNTH_bin - RTC Daylight Saving Month Register; Several registers at the same address ***/ union { struct { word DST_END_MONTH0 :1; /* Month value when daylight saving has to end bits, bit 0 */ word DST_END_MONTH1 :1; /* Month value when daylight saving has to end bits, bit 1 */ word DST_END_MONTH2 :1; /* Month value when daylight saving has to end bits, bit 2 */ word DST_END_MONTH3 :1; /* Month value when daylight saving has to end bits, bit 3 */ word :1; word :1; word :1; word :1; word DST_START_MONTH0 :1; /* Month value when daylight saving has to start bits, bit 0 */ word DST_START_MONTH1 :1; /* Month value when daylight saving has to start bits, bit 1 */ word DST_START_MONTH2 :1; /* Month value when daylight saving has to start bits, bit 2 */ word DST_START_MONTH3 :1; /* Month value when daylight saving has to start bits, bit 3 */ word :1; word :1; word :1; word :1; } Bits; struct { word grpDST_END_MONTH :4; word :1; word :1; word :1; word :1; word grpDST_START_MONTH :4; word :1; word :1; word :1; word :1; } MergedBits; } IRTC_DST_MNTH_binSTR; #define IRTC_DST_MNTH_bin _IRTC_DST_MNTH_bcd.Word #define IRTC_DST_MNTH_bin_DST_END_MONTH0 _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_binSTR.Bits.DST_END_MONTH0 #define IRTC_DST_MNTH_bin_DST_END_MONTH1 _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_binSTR.Bits.DST_END_MONTH1 #define IRTC_DST_MNTH_bin_DST_END_MONTH2 _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_binSTR.Bits.DST_END_MONTH2 #define IRTC_DST_MNTH_bin_DST_END_MONTH3 _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_binSTR.Bits.DST_END_MONTH3 #define IRTC_DST_MNTH_bin_DST_START_MONTH0 _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_binSTR.Bits.DST_START_MONTH0 #define IRTC_DST_MNTH_bin_DST_START_MONTH1 _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_binSTR.Bits.DST_START_MONTH1 #define IRTC_DST_MNTH_bin_DST_START_MONTH2 _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_binSTR.Bits.DST_START_MONTH2 #define IRTC_DST_MNTH_bin_DST_START_MONTH3 _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_binSTR.Bits.DST_START_MONTH3 #define IRTC_DST_MNTH_bin_DST_END_MONTH _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_binSTR.MergedBits.grpDST_END_MONTH #define IRTC_DST_MNTH_bin_DST_START_MONTH _IRTC_DST_MNTH_bcd.SameAddr_STR.IRTC_DST_MNTH_binSTR.MergedBits.grpDST_START_MONTH #define IRTC_DST_MNTH_bin_DST_END_MONTH0_MASK 1 #define IRTC_DST_MNTH_bin_DST_END_MONTH1_MASK 2 #define IRTC_DST_MNTH_bin_DST_END_MONTH2_MASK 4 #define IRTC_DST_MNTH_bin_DST_END_MONTH3_MASK 8 #define IRTC_DST_MNTH_bin_DST_START_MONTH0_MASK 256 #define IRTC_DST_MNTH_bin_DST_START_MONTH1_MASK 512 #define IRTC_DST_MNTH_bin_DST_START_MONTH2_MASK 1024 #define IRTC_DST_MNTH_bin_DST_START_MONTH3_MASK 2048 #define IRTC_DST_MNTH_bin_DST_END_MONTH_MASK 15 #define IRTC_DST_MNTH_bin_DST_END_MONTH_BITNUM 0 #define IRTC_DST_MNTH_bin_DST_START_MONTH_MASK 3840 #define IRTC_DST_MNTH_bin_DST_START_MONTH_BITNUM 8 } SameAddr_STR; /*Several registers at the same address */ } IRTC_DST_MNTH_bcdSTR; extern volatile IRTC_DST_MNTH_bcdSTR _IRTC_DST_MNTH_bcd @0xFFFF8664; /*** IRTC_DST_DAY_bcd - RTC Daylight Saving Day Register; 0xFFFF8666 ***/ typedef union { word Word; union { /* Several registers at the same address */ /*** IRTC_DST_DAY_bcd - RTC Daylight Saving Day Register; Several registers at the same address ***/ union { struct { word DST_END_DAY_units0 :1; /* Day units value when daylight saving has to end bits, bit 0 */ word DST_END_DAY_units1 :1; /* Day units value when daylight saving has to end bits, bit 1 */ word DST_END_DAY_units2 :1; /* Day units value when daylight saving has to end bits, bit 2 */ word DST_END_DAY_units3 :1; /* Day units value when daylight saving has to end bits, bit 3 */ word DST_END_DAY_tens0 :1; /* Day tens value when daylight saving has to end bits, bit 0 */ word DST_END_DAY_tens1 :1; /* Day tens value when daylight saving has to end bits, bit 1 */ word DST_END_DAY_tens2 :1; /* Day tens value when daylight saving has to end bits, bit 2 */ word DST_END_DAY_tens3 :1; /* Day tens value when daylight saving has to end bits, bit 3 */ word DST_START_DAY_units0 :1; /* Day units value when daylight saving has to start bits, bit 0 */ word DST_START_DAY_units1 :1; /* Day units value when daylight saving has to start bits, bit 1 */ word DST_START_DAY_units2 :1; /* Day units value when daylight saving has to start bits, bit 2 */ word DST_START_DAY_units3 :1; /* Day units value when daylight saving has to start bits, bit 3 */ word DST_START_DAY_tens0 :1; /* Day tens value when daylight saving has to start bits, bit 0 */ word DST_START_DAY_tens1 :1; /* Day tens value when daylight saving has to start bits, bit 1 */ word DST_START_DAY_tens2 :1; /* Day tens value when daylight saving has to start bits, bit 2 */ word DST_START_DAY_tens3 :1; /* Day tens value when daylight saving has to start bits, bit 3 */ } Bits; struct { word grpDST_END_DAY_units :4; word grpDST_END_DAY_tens :4; word grpDST_START_DAY_units :4; word grpDST_START_DAY_tens :4; } MergedBits; } IRTC_DST_DAY_bcdSTR; #define IRTC_DST_DAY_bcd _IRTC_DST_DAY_bcd.Word #define IRTC_DST_DAY_bcd_DST_END_DAY_units0 _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_bcdSTR.Bits.DST_END_DAY_units0 #define IRTC_DST_DAY_bcd_DST_END_DAY_units1 _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_bcdSTR.Bits.DST_END_DAY_units1 #define IRTC_DST_DAY_bcd_DST_END_DAY_units2 _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_bcdSTR.Bits.DST_END_DAY_units2 #define IRTC_DST_DAY_bcd_DST_END_DAY_units3 _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_bcdSTR.Bits.DST_END_DAY_units3 #define IRTC_DST_DAY_bcd_DST_END_DAY_tens0 _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_bcdSTR.Bits.DST_END_DAY_tens0 #define IRTC_DST_DAY_bcd_DST_END_DAY_tens1 _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_bcdSTR.Bits.DST_END_DAY_tens1 #define IRTC_DST_DAY_bcd_DST_END_DAY_tens2 _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_bcdSTR.Bits.DST_END_DAY_tens2 #define IRTC_DST_DAY_bcd_DST_END_DAY_tens3 _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_bcdSTR.Bits.DST_END_DAY_tens3 #define IRTC_DST_DAY_bcd_DST_START_DAY_units0 _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_bcdSTR.Bits.DST_START_DAY_units0 #define IRTC_DST_DAY_bcd_DST_START_DAY_units1 _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_bcdSTR.Bits.DST_START_DAY_units1 #define IRTC_DST_DAY_bcd_DST_START_DAY_units2 _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_bcdSTR.Bits.DST_START_DAY_units2 #define IRTC_DST_DAY_bcd_DST_START_DAY_units3 _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_bcdSTR.Bits.DST_START_DAY_units3 #define IRTC_DST_DAY_bcd_DST_START_DAY_tens0 _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_bcdSTR.Bits.DST_START_DAY_tens0 #define IRTC_DST_DAY_bcd_DST_START_DAY_tens1 _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_bcdSTR.Bits.DST_START_DAY_tens1 #define IRTC_DST_DAY_bcd_DST_START_DAY_tens2 _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_bcdSTR.Bits.DST_START_DAY_tens2 #define IRTC_DST_DAY_bcd_DST_START_DAY_tens3 _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_bcdSTR.Bits.DST_START_DAY_tens3 #define IRTC_DST_DAY_bcd_DST_END_DAY_units _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_bcdSTR.MergedBits.grpDST_END_DAY_units #define IRTC_DST_DAY_bcd_DST_END_DAY_tens _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_bcdSTR.MergedBits.grpDST_END_DAY_tens #define IRTC_DST_DAY_bcd_DST_START_DAY_units _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_bcdSTR.MergedBits.grpDST_START_DAY_units #define IRTC_DST_DAY_bcd_DST_START_DAY_tens _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_bcdSTR.MergedBits.grpDST_START_DAY_tens #define IRTC_DST_DAY_bcd_DST_END_DAY_units0_MASK 1 #define IRTC_DST_DAY_bcd_DST_END_DAY_units1_MASK 2 #define IRTC_DST_DAY_bcd_DST_END_DAY_units2_MASK 4 #define IRTC_DST_DAY_bcd_DST_END_DAY_units3_MASK 8 #define IRTC_DST_DAY_bcd_DST_END_DAY_tens0_MASK 16 #define IRTC_DST_DAY_bcd_DST_END_DAY_tens1_MASK 32 #define IRTC_DST_DAY_bcd_DST_END_DAY_tens2_MASK 64 #define IRTC_DST_DAY_bcd_DST_END_DAY_tens3_MASK 128 #define IRTC_DST_DAY_bcd_DST_START_DAY_units0_MASK 256 #define IRTC_DST_DAY_bcd_DST_START_DAY_units1_MASK 512 #define IRTC_DST_DAY_bcd_DST_START_DAY_units2_MASK 1024 #define IRTC_DST_DAY_bcd_DST_START_DAY_units3_MASK 2048 #define IRTC_DST_DAY_bcd_DST_START_DAY_tens0_MASK 4096 #define IRTC_DST_DAY_bcd_DST_START_DAY_tens1_MASK 8192 #define IRTC_DST_DAY_bcd_DST_START_DAY_tens2_MASK 16384 #define IRTC_DST_DAY_bcd_DST_START_DAY_tens3_MASK 32768 #define IRTC_DST_DAY_bcd_DST_END_DAY_units_MASK 15 #define IRTC_DST_DAY_bcd_DST_END_DAY_units_BITNUM 0 #define IRTC_DST_DAY_bcd_DST_END_DAY_tens_MASK 240 #define IRTC_DST_DAY_bcd_DST_END_DAY_tens_BITNUM 4 #define IRTC_DST_DAY_bcd_DST_START_DAY_units_MASK 3840 #define IRTC_DST_DAY_bcd_DST_START_DAY_units_BITNUM 8 #define IRTC_DST_DAY_bcd_DST_START_DAY_tens_MASK 61440 #define IRTC_DST_DAY_bcd_DST_START_DAY_tens_BITNUM 12 /*** IRTC_DST_DAY_bin - RTC Daylight Saving Day Register; Several registers at the same address ***/ union { struct { word DST_END_DAY0 :1; /* Day value when daylight saving has to end bits, bit 0 */ word DST_END_DAY1 :1; /* Day value when daylight saving has to end bits, bit 1 */ word DST_END_DAY2 :1; /* Day value when daylight saving has to end bits, bit 2 */ word DST_END_DAY3 :1; /* Day value when daylight saving has to end bits, bit 3 */ word DST_END_DAY4 :1; /* Day value when daylight saving has to end bits, bit 4 */ word :1; word :1; word :1; word DST_START_DAY0 :1; /* Day value when daylight saving has to start bits, bit 0 */ word DST_START_DAY1 :1; /* Day value when daylight saving has to start bits, bit 1 */ word DST_START_DAY2 :1; /* Day value when daylight saving has to start bits, bit 2 */ word DST_START_DAY3 :1; /* Day value when daylight saving has to start bits, bit 3 */ word DST_START_DAY4 :1; /* Day value when daylight saving has to start bits, bit 4 */ word :1; word :1; word :1; } Bits; struct { word grpDST_END_DAY :5; word :1; word :1; word :1; word grpDST_START_DAY :5; word :1; word :1; word :1; } MergedBits; } IRTC_DST_DAY_binSTR; #define IRTC_DST_DAY_bin _IRTC_DST_DAY_bcd.Word #define IRTC_DST_DAY_bin_DST_END_DAY0 _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_binSTR.Bits.DST_END_DAY0 #define IRTC_DST_DAY_bin_DST_END_DAY1 _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_binSTR.Bits.DST_END_DAY1 #define IRTC_DST_DAY_bin_DST_END_DAY2 _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_binSTR.Bits.DST_END_DAY2 #define IRTC_DST_DAY_bin_DST_END_DAY3 _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_binSTR.Bits.DST_END_DAY3 #define IRTC_DST_DAY_bin_DST_END_DAY4 _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_binSTR.Bits.DST_END_DAY4 #define IRTC_DST_DAY_bin_DST_START_DAY0 _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_binSTR.Bits.DST_START_DAY0 #define IRTC_DST_DAY_bin_DST_START_DAY1 _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_binSTR.Bits.DST_START_DAY1 #define IRTC_DST_DAY_bin_DST_START_DAY2 _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_binSTR.Bits.DST_START_DAY2 #define IRTC_DST_DAY_bin_DST_START_DAY3 _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_binSTR.Bits.DST_START_DAY3 #define IRTC_DST_DAY_bin_DST_START_DAY4 _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_binSTR.Bits.DST_START_DAY4 #define IRTC_DST_DAY_bin_DST_END_DAY _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_binSTR.MergedBits.grpDST_END_DAY #define IRTC_DST_DAY_bin_DST_START_DAY _IRTC_DST_DAY_bcd.SameAddr_STR.IRTC_DST_DAY_binSTR.MergedBits.grpDST_START_DAY #define IRTC_DST_DAY_bin_DST_END_DAY0_MASK 1 #define IRTC_DST_DAY_bin_DST_END_DAY1_MASK 2 #define IRTC_DST_DAY_bin_DST_END_DAY2_MASK 4 #define IRTC_DST_DAY_bin_DST_END_DAY3_MASK 8 #define IRTC_DST_DAY_bin_DST_END_DAY4_MASK 16 #define IRTC_DST_DAY_bin_DST_START_DAY0_MASK 256 #define IRTC_DST_DAY_bin_DST_START_DAY1_MASK 512 #define IRTC_DST_DAY_bin_DST_START_DAY2_MASK 1024 #define IRTC_DST_DAY_bin_DST_START_DAY3_MASK 2048 #define IRTC_DST_DAY_bin_DST_START_DAY4_MASK 4096 #define IRTC_DST_DAY_bin_DST_END_DAY_MASK 31 #define IRTC_DST_DAY_bin_DST_END_DAY_BITNUM 0 #define IRTC_DST_DAY_bin_DST_START_DAY_MASK 7936 #define IRTC_DST_DAY_bin_DST_START_DAY_BITNUM 8 } SameAddr_STR; /*Several registers at the same address */ } IRTC_DST_DAY_bcdSTR; extern volatile IRTC_DST_DAY_bcdSTR _IRTC_DST_DAY_bcd @0xFFFF8666; /*** IRTC_COMPEN - RTC Compensation Register; 0xFFFF8668 ***/ typedef union { word Word; struct { word COMPENSATION_VALUE0 :1; /* Compensation value bits, bit 0 */ word COMPENSATION_VALUE1 :1; /* Compensation value bits, bit 1 */ word COMPENSATION_VALUE2 :1; /* Compensation value bits, bit 2 */ word COMPENSATION_VALUE3 :1; /* Compensation value bits, bit 3 */ word COMPENSATION_VALUE4 :1; /* Compensation value bits, bit 4 */ word COMPENSATION_VALUE5 :1; /* Compensation value bits, bit 5 */ word COMPENSATION_VALUE6 :1; /* Compensation value bits, bit 6 */ word COMPENSATION_VALUE7 :1; /* Compensation value bits, bit 7 */ word COMPENSTAION_INTERVAL0 :1; /* Compensation interval value bits, bit 0 */ word COMPENSTAION_INTERVAL1 :1; /* Compensation interval value bits, bit 1 */ word COMPENSTAION_INTERVAL2 :1; /* Compensation interval value bits, bit 2 */ word COMPENSTAION_INTERVAL3 :1; /* Compensation interval value bits, bit 3 */ word COMPENSTAION_INTERVAL4 :1; /* Compensation interval value bits, bit 4 */ word COMPENSTAION_INTERVAL5 :1; /* Compensation interval value bits, bit 5 */ word COMPENSTAION_INTERVAL6 :1; /* Compensation interval value bits, bit 6 */ word COMPENSTAION_INTERVAL7 :1; /* Compensation interval value bits, bit 7 */ } Bits; struct { word grpCOMPENSATION_VALUE :8; word grpCOMPENSTAION_INTERVAL :8; } MergedBits; } IRTC_COMPENSTR; extern volatile IRTC_COMPENSTR _IRTC_COMPEN @0xFFFF8668; #define IRTC_COMPEN _IRTC_COMPEN.Word #define IRTC_COMPEN_COMPENSATION_VALUE0 _IRTC_COMPEN.Bits.COMPENSATION_VALUE0 #define IRTC_COMPEN_COMPENSATION_VALUE1 _IRTC_COMPEN.Bits.COMPENSATION_VALUE1 #define IRTC_COMPEN_COMPENSATION_VALUE2 _IRTC_COMPEN.Bits.COMPENSATION_VALUE2 #define IRTC_COMPEN_COMPENSATION_VALUE3 _IRTC_COMPEN.Bits.COMPENSATION_VALUE3 #define IRTC_COMPEN_COMPENSATION_VALUE4 _IRTC_COMPEN.Bits.COMPENSATION_VALUE4 #define IRTC_COMPEN_COMPENSATION_VALUE5 _IRTC_COMPEN.Bits.COMPENSATION_VALUE5 #define IRTC_COMPEN_COMPENSATION_VALUE6 _IRTC_COMPEN.Bits.COMPENSATION_VALUE6 #define IRTC_COMPEN_COMPENSATION_VALUE7 _IRTC_COMPEN.Bits.COMPENSATION_VALUE7 #define IRTC_COMPEN_COMPENSTAION_INTERVAL0 _IRTC_COMPEN.Bits.COMPENSTAION_INTERVAL0 #define IRTC_COMPEN_COMPENSTAION_INTERVAL1 _IRTC_COMPEN.Bits.COMPENSTAION_INTERVAL1 #define IRTC_COMPEN_COMPENSTAION_INTERVAL2 _IRTC_COMPEN.Bits.COMPENSTAION_INTERVAL2 #define IRTC_COMPEN_COMPENSTAION_INTERVAL3 _IRTC_COMPEN.Bits.COMPENSTAION_INTERVAL3 #define IRTC_COMPEN_COMPENSTAION_INTERVAL4 _IRTC_COMPEN.Bits.COMPENSTAION_INTERVAL4 #define IRTC_COMPEN_COMPENSTAION_INTERVAL5 _IRTC_COMPEN.Bits.COMPENSTAION_INTERVAL5 #define IRTC_COMPEN_COMPENSTAION_INTERVAL6 _IRTC_COMPEN.Bits.COMPENSTAION_INTERVAL6 #define IRTC_COMPEN_COMPENSTAION_INTERVAL7 _IRTC_COMPEN.Bits.COMPENSTAION_INTERVAL7 #define IRTC_COMPEN_COMPENSATION_VALUE _IRTC_COMPEN.MergedBits.grpCOMPENSATION_VALUE #define IRTC_COMPEN_COMPENSTAION_INTERVAL _IRTC_COMPEN.MergedBits.grpCOMPENSTAION_INTERVAL #define IRTC_COMPEN_COMPENSATION_VALUE0_MASK 1 #define IRTC_COMPEN_COMPENSATION_VALUE1_MASK 2 #define IRTC_COMPEN_COMPENSATION_VALUE2_MASK 4 #define IRTC_COMPEN_COMPENSATION_VALUE3_MASK 8 #define IRTC_COMPEN_COMPENSATION_VALUE4_MASK 16 #define IRTC_COMPEN_COMPENSATION_VALUE5_MASK 32 #define IRTC_COMPEN_COMPENSATION_VALUE6_MASK 64 #define IRTC_COMPEN_COMPENSATION_VALUE7_MASK 128 #define IRTC_COMPEN_COMPENSTAION_INTERVAL0_MASK 256 #define IRTC_COMPEN_COMPENSTAION_INTERVAL1_MASK 512 #define IRTC_COMPEN_COMPENSTAION_INTERVAL2_MASK 1024 #define IRTC_COMPEN_COMPENSTAION_INTERVAL3_MASK 2048 #define IRTC_COMPEN_COMPENSTAION_INTERVAL4_MASK 4096 #define IRTC_COMPEN_COMPENSTAION_INTERVAL5_MASK 8192 #define IRTC_COMPEN_COMPENSTAION_INTERVAL6_MASK 16384 #define IRTC_COMPEN_COMPENSTAION_INTERVAL7_MASK 32768 #define IRTC_COMPEN_COMPENSATION_VALUE_MASK 255 #define IRTC_COMPEN_COMPENSATION_VALUE_BITNUM 0 #define IRTC_COMPEN_COMPENSTAION_INTERVAL_MASK 65280 #define IRTC_COMPEN_COMPENSTAION_INTERVAL_BITNUM 8 /*** IRTC_TTSR_MY_bcd - RTC Tamper Time Stamp Month & Year Register; 0xFFFF866A ***/ typedef union { word Word; union { /* Several registers at the same address */ /*** IRTC_TTSR_MY_bcd - RTC Tamper Time Stamp Month & Year Register; Several registers at the same address ***/ union { struct { word TIME_STAMP_MONTHS_units0 :1; /* Tamper detect month units value bits, bit 0 */ word TIME_STAMP_MONTHS_units1 :1; /* Tamper detect month units value bits, bit 1 */ word TIME_STAMP_MONTHS_units2 :1; /* Tamper detect month units value bits, bit 2 */ word TIME_STAMP_MONTHS_units3 :1; /* Tamper detect month units value bits, bit 3 */ word TIME_STAMP_MONTHS_tens0 :1; /* Tamper detect month tens value bits, bit 0 */ word TIME_STAMP_MONTHS_tens1 :1; /* Tamper detect month tens value bits, bit 1 */ word TIME_STAMP_MONTHS_tens2 :1; /* Tamper detect month tens value bits, bit 2 */ word TIME_STAMP_MONTHS_tens3 :1; /* Tamper detect month tens value bits, bit 3 */ word TIME_STAMP_YEAR0 :1; /* Tamper detect year value bits, bit 0 */ word TIME_STAMP_YEAR1 :1; /* Tamper detect year value bits, bit 1 */ word TIME_STAMP_YEAR2 :1; /* Tamper detect year value bits, bit 2 */ word TIME_STAMP_YEAR3 :1; /* Tamper detect year value bits, bit 3 */ word TIME_STAMP_YEAR4 :1; /* Tamper detect year value bits, bit 4 */ word TIME_STAMP_YEAR5 :1; /* Tamper detect year value bits, bit 5 */ word TIME_STAMP_YEAR6 :1; /* Tamper detect year value bits, bit 6 */ word TIME_STAMP_YEAR7 :1; /* Tamper detect year value bits, bit 7 */ } Bits; struct { word grpTIME_STAMP_MONTHS_units :4; word grpTIME_STAMP_MONTHS_tens :4; word grpTIME_STAMP_YEAR :8; } MergedBits; } IRTC_TTSR_MY_bcdSTR; #define IRTC_TTSR_MY_bcd _IRTC_TTSR_MY_bcd.Word #define IRTC_TTSR_MY_bcd_TIME_STAMP_MONTHS_units0 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_bcdSTR.Bits.TIME_STAMP_MONTHS_units0 #define IRTC_TTSR_MY_bcd_TIME_STAMP_MONTHS_units1 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_bcdSTR.Bits.TIME_STAMP_MONTHS_units1 #define IRTC_TTSR_MY_bcd_TIME_STAMP_MONTHS_units2 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_bcdSTR.Bits.TIME_STAMP_MONTHS_units2 #define IRTC_TTSR_MY_bcd_TIME_STAMP_MONTHS_units3 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_bcdSTR.Bits.TIME_STAMP_MONTHS_units3 #define IRTC_TTSR_MY_bcd_TIME_STAMP_MONTHS_tens0 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_bcdSTR.Bits.TIME_STAMP_MONTHS_tens0 #define IRTC_TTSR_MY_bcd_TIME_STAMP_MONTHS_tens1 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_bcdSTR.Bits.TIME_STAMP_MONTHS_tens1 #define IRTC_TTSR_MY_bcd_TIME_STAMP_MONTHS_tens2 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_bcdSTR.Bits.TIME_STAMP_MONTHS_tens2 #define IRTC_TTSR_MY_bcd_TIME_STAMP_MONTHS_tens3 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_bcdSTR.Bits.TIME_STAMP_MONTHS_tens3 #define IRTC_TTSR_MY_bcd_TIME_STAMP_YEAR0 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_bcdSTR.Bits.TIME_STAMP_YEAR0 #define IRTC_TTSR_MY_bcd_TIME_STAMP_YEAR1 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_bcdSTR.Bits.TIME_STAMP_YEAR1 #define IRTC_TTSR_MY_bcd_TIME_STAMP_YEAR2 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_bcdSTR.Bits.TIME_STAMP_YEAR2 #define IRTC_TTSR_MY_bcd_TIME_STAMP_YEAR3 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_bcdSTR.Bits.TIME_STAMP_YEAR3 #define IRTC_TTSR_MY_bcd_TIME_STAMP_YEAR4 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_bcdSTR.Bits.TIME_STAMP_YEAR4 #define IRTC_TTSR_MY_bcd_TIME_STAMP_YEAR5 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_bcdSTR.Bits.TIME_STAMP_YEAR5 #define IRTC_TTSR_MY_bcd_TIME_STAMP_YEAR6 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_bcdSTR.Bits.TIME_STAMP_YEAR6 #define IRTC_TTSR_MY_bcd_TIME_STAMP_YEAR7 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_bcdSTR.Bits.TIME_STAMP_YEAR7 #define IRTC_TTSR_MY_bcd_TIME_STAMP_MONTHS_units _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_bcdSTR.MergedBits.grpTIME_STAMP_MONTHS_units #define IRTC_TTSR_MY_bcd_TIME_STAMP_MONTHS_tens _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_bcdSTR.MergedBits.grpTIME_STAMP_MONTHS_tens #define IRTC_TTSR_MY_bcd_TIME_STAMP_YEAR _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_bcdSTR.MergedBits.grpTIME_STAMP_YEAR #define IRTC_TTSR_MY_bcd_TIME_STAMP_MONTHS_units0_MASK 1 #define IRTC_TTSR_MY_bcd_TIME_STAMP_MONTHS_units1_MASK 2 #define IRTC_TTSR_MY_bcd_TIME_STAMP_MONTHS_units2_MASK 4 #define IRTC_TTSR_MY_bcd_TIME_STAMP_MONTHS_units3_MASK 8 #define IRTC_TTSR_MY_bcd_TIME_STAMP_MONTHS_tens0_MASK 16 #define IRTC_TTSR_MY_bcd_TIME_STAMP_MONTHS_tens1_MASK 32 #define IRTC_TTSR_MY_bcd_TIME_STAMP_MONTHS_tens2_MASK 64 #define IRTC_TTSR_MY_bcd_TIME_STAMP_MONTHS_tens3_MASK 128 #define IRTC_TTSR_MY_bcd_TIME_STAMP_YEAR0_MASK 256 #define IRTC_TTSR_MY_bcd_TIME_STAMP_YEAR1_MASK 512 #define IRTC_TTSR_MY_bcd_TIME_STAMP_YEAR2_MASK 1024 #define IRTC_TTSR_MY_bcd_TIME_STAMP_YEAR3_MASK 2048 #define IRTC_TTSR_MY_bcd_TIME_STAMP_YEAR4_MASK 4096 #define IRTC_TTSR_MY_bcd_TIME_STAMP_YEAR5_MASK 8192 #define IRTC_TTSR_MY_bcd_TIME_STAMP_YEAR6_MASK 16384 #define IRTC_TTSR_MY_bcd_TIME_STAMP_YEAR7_MASK 32768 #define IRTC_TTSR_MY_bcd_TIME_STAMP_MONTHS_units_MASK 15 #define IRTC_TTSR_MY_bcd_TIME_STAMP_MONTHS_units_BITNUM 0 #define IRTC_TTSR_MY_bcd_TIME_STAMP_MONTHS_tens_MASK 240 #define IRTC_TTSR_MY_bcd_TIME_STAMP_MONTHS_tens_BITNUM 4 #define IRTC_TTSR_MY_bcd_TIME_STAMP_YEAR_MASK 65280 #define IRTC_TTSR_MY_bcd_TIME_STAMP_YEAR_BITNUM 8 /*** IRTC_TTSR_MY_bin - RTC Tamper Time Stamp Month & Year Register; Several registers at the same address ***/ union { struct { word TIME_STAMP_MONTHS0 :1; /* Tamper detect month value bits, bit 0 */ word TIME_STAMP_MONTHS1 :1; /* Tamper detect month value bits, bit 1 */ word TIME_STAMP_MONTHS2 :1; /* Tamper detect month value bits, bit 2 */ word TIME_STAMP_MONTHS3 :1; /* Tamper detect month value bits, bit 3 */ word :1; word :1; word :1; word :1; word TIME_STAMP_YEAR0 :1; /* Tamper detect year value bits, bit 0 */ word TIME_STAMP_YEAR1 :1; /* Tamper detect year value bits, bit 1 */ word TIME_STAMP_YEAR2 :1; /* Tamper detect year value bits, bit 2 */ word TIME_STAMP_YEAR3 :1; /* Tamper detect year value bits, bit 3 */ word TIME_STAMP_YEAR4 :1; /* Tamper detect year value bits, bit 4 */ word TIME_STAMP_YEAR5 :1; /* Tamper detect year value bits, bit 5 */ word TIME_STAMP_YEAR6 :1; /* Tamper detect year value bits, bit 6 */ word TIME_STAMP_YEAR7 :1; /* Tamper detect year value bits, bit 7 */ } Bits; struct { word grpTIME_STAMP_MONTHS :4; word :1; word :1; word :1; word :1; word grpTIME_STAMP_YEAR :8; } MergedBits; } IRTC_TTSR_MY_binSTR; #define IRTC_TTSR_MY_bin _IRTC_TTSR_MY_bcd.Word #define IRTC_TTSR_MY_bin_TIME_STAMP_MONTHS0 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_binSTR.Bits.TIME_STAMP_MONTHS0 #define IRTC_TTSR_MY_bin_TIME_STAMP_MONTHS1 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_binSTR.Bits.TIME_STAMP_MONTHS1 #define IRTC_TTSR_MY_bin_TIME_STAMP_MONTHS2 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_binSTR.Bits.TIME_STAMP_MONTHS2 #define IRTC_TTSR_MY_bin_TIME_STAMP_MONTHS3 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_binSTR.Bits.TIME_STAMP_MONTHS3 #define IRTC_TTSR_MY_bin_TIME_STAMP_YEAR0 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_binSTR.Bits.TIME_STAMP_YEAR0 #define IRTC_TTSR_MY_bin_TIME_STAMP_YEAR1 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_binSTR.Bits.TIME_STAMP_YEAR1 #define IRTC_TTSR_MY_bin_TIME_STAMP_YEAR2 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_binSTR.Bits.TIME_STAMP_YEAR2 #define IRTC_TTSR_MY_bin_TIME_STAMP_YEAR3 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_binSTR.Bits.TIME_STAMP_YEAR3 #define IRTC_TTSR_MY_bin_TIME_STAMP_YEAR4 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_binSTR.Bits.TIME_STAMP_YEAR4 #define IRTC_TTSR_MY_bin_TIME_STAMP_YEAR5 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_binSTR.Bits.TIME_STAMP_YEAR5 #define IRTC_TTSR_MY_bin_TIME_STAMP_YEAR6 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_binSTR.Bits.TIME_STAMP_YEAR6 #define IRTC_TTSR_MY_bin_TIME_STAMP_YEAR7 _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_binSTR.Bits.TIME_STAMP_YEAR7 #define IRTC_TTSR_MY_bin_TIME_STAMP_MONTHS _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_binSTR.MergedBits.grpTIME_STAMP_MONTHS #define IRTC_TTSR_MY_bin_TIME_STAMP_YEAR _IRTC_TTSR_MY_bcd.SameAddr_STR.IRTC_TTSR_MY_binSTR.MergedBits.grpTIME_STAMP_YEAR #define IRTC_TTSR_MY_bin_TIME_STAMP_MONTHS0_MASK 1 #define IRTC_TTSR_MY_bin_TIME_STAMP_MONTHS1_MASK 2 #define IRTC_TTSR_MY_bin_TIME_STAMP_MONTHS2_MASK 4 #define IRTC_TTSR_MY_bin_TIME_STAMP_MONTHS3_MASK 8 #define IRTC_TTSR_MY_bin_TIME_STAMP_YEAR0_MASK 256 #define IRTC_TTSR_MY_bin_TIME_STAMP_YEAR1_MASK 512 #define IRTC_TTSR_MY_bin_TIME_STAMP_YEAR2_MASK 1024 #define IRTC_TTSR_MY_bin_TIME_STAMP_YEAR3_MASK 2048 #define IRTC_TTSR_MY_bin_TIME_STAMP_YEAR4_MASK 4096 #define IRTC_TTSR_MY_bin_TIME_STAMP_YEAR5_MASK 8192 #define IRTC_TTSR_MY_bin_TIME_STAMP_YEAR6_MASK 16384 #define IRTC_TTSR_MY_bin_TIME_STAMP_YEAR7_MASK 32768 #define IRTC_TTSR_MY_bin_TIME_STAMP_MONTHS_MASK 15 #define IRTC_TTSR_MY_bin_TIME_STAMP_MONTHS_BITNUM 0 #define IRTC_TTSR_MY_bin_TIME_STAMP_YEAR_MASK 65280 #define IRTC_TTSR_MY_bin_TIME_STAMP_YEAR_BITNUM 8 } SameAddr_STR; /*Several registers at the same address */ } IRTC_TTSR_MY_bcdSTR; extern volatile IRTC_TTSR_MY_bcdSTR _IRTC_TTSR_MY_bcd @0xFFFF866A; /*** IRTC_TTSR_DAY_bcd - RTC Tamper Time Stamp Day Register; 0xFFFF866C ***/ typedef union { word Word; union { /* Several registers at the same address */ /*** IRTC_TTSR_DAY_bcd - RTC Tamper Time Stamp Day Register; Several registers at the same address ***/ union { struct { word TIME_STAMP_DAY_units0 :1; /* Tamper detect days units value bits, bit 0 */ word TIME_STAMP_DAY_units1 :1; /* Tamper detect days units value bits, bit 1 */ word TIME_STAMP_DAY_units2 :1; /* Tamper detect days units value bits, bit 2 */ word TIME_STAMP_DAY_units3 :1; /* Tamper detect days units value bits, bit 3 */ word TIME_STAMP_DAY_tens0 :1; /* Tamper detect days tens value bits, bit 0 */ word TIME_STAMP_DAY_tens1 :1; /* Tamper detect days tens value bits, bit 1 */ word TIME_STAMP_DAY_tens2 :1; /* Tamper detect days tens value bits, bit 2 */ word TIME_STAMP_DAY_tens3 :1; /* Tamper detect days tens value bits, bit 3 */ word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpTIME_STAMP_DAY_units :4; word grpTIME_STAMP_DAY_tens :4; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } IRTC_TTSR_DAY_bcdSTR; #define IRTC_TTSR_DAY_bcd _IRTC_TTSR_DAY_bcd.Word #define IRTC_TTSR_DAY_bcd_TIME_STAMP_DAY_units0 _IRTC_TTSR_DAY_bcd.SameAddr_STR.IRTC_TTSR_DAY_bcdSTR.Bits.TIME_STAMP_DAY_units0 #define IRTC_TTSR_DAY_bcd_TIME_STAMP_DAY_units1 _IRTC_TTSR_DAY_bcd.SameAddr_STR.IRTC_TTSR_DAY_bcdSTR.Bits.TIME_STAMP_DAY_units1 #define IRTC_TTSR_DAY_bcd_TIME_STAMP_DAY_units2 _IRTC_TTSR_DAY_bcd.SameAddr_STR.IRTC_TTSR_DAY_bcdSTR.Bits.TIME_STAMP_DAY_units2 #define IRTC_TTSR_DAY_bcd_TIME_STAMP_DAY_units3 _IRTC_TTSR_DAY_bcd.SameAddr_STR.IRTC_TTSR_DAY_bcdSTR.Bits.TIME_STAMP_DAY_units3 #define IRTC_TTSR_DAY_bcd_TIME_STAMP_DAY_tens0 _IRTC_TTSR_DAY_bcd.SameAddr_STR.IRTC_TTSR_DAY_bcdSTR.Bits.TIME_STAMP_DAY_tens0 #define IRTC_TTSR_DAY_bcd_TIME_STAMP_DAY_tens1 _IRTC_TTSR_DAY_bcd.SameAddr_STR.IRTC_TTSR_DAY_bcdSTR.Bits.TIME_STAMP_DAY_tens1 #define IRTC_TTSR_DAY_bcd_TIME_STAMP_DAY_tens2 _IRTC_TTSR_DAY_bcd.SameAddr_STR.IRTC_TTSR_DAY_bcdSTR.Bits.TIME_STAMP_DAY_tens2 #define IRTC_TTSR_DAY_bcd_TIME_STAMP_DAY_tens3 _IRTC_TTSR_DAY_bcd.SameAddr_STR.IRTC_TTSR_DAY_bcdSTR.Bits.TIME_STAMP_DAY_tens3 #define IRTC_TTSR_DAY_bcd_TIME_STAMP_DAY_units _IRTC_TTSR_DAY_bcd.SameAddr_STR.IRTC_TTSR_DAY_bcdSTR.MergedBits.grpTIME_STAMP_DAY_units #define IRTC_TTSR_DAY_bcd_TIME_STAMP_DAY_tens _IRTC_TTSR_DAY_bcd.SameAddr_STR.IRTC_TTSR_DAY_bcdSTR.MergedBits.grpTIME_STAMP_DAY_tens #define IRTC_TTSR_DAY_bcd_TIME_STAMP_DAY_units0_MASK 1 #define IRTC_TTSR_DAY_bcd_TIME_STAMP_DAY_units1_MASK 2 #define IRTC_TTSR_DAY_bcd_TIME_STAMP_DAY_units2_MASK 4 #define IRTC_TTSR_DAY_bcd_TIME_STAMP_DAY_units3_MASK 8 #define IRTC_TTSR_DAY_bcd_TIME_STAMP_DAY_tens0_MASK 16 #define IRTC_TTSR_DAY_bcd_TIME_STAMP_DAY_tens1_MASK 32 #define IRTC_TTSR_DAY_bcd_TIME_STAMP_DAY_tens2_MASK 64 #define IRTC_TTSR_DAY_bcd_TIME_STAMP_DAY_tens3_MASK 128 #define IRTC_TTSR_DAY_bcd_TIME_STAMP_DAY_units_MASK 15 #define IRTC_TTSR_DAY_bcd_TIME_STAMP_DAY_units_BITNUM 0 #define IRTC_TTSR_DAY_bcd_TIME_STAMP_DAY_tens_MASK 240 #define IRTC_TTSR_DAY_bcd_TIME_STAMP_DAY_tens_BITNUM 4 /*** IRTC_TTSR_DAY_bin - RTC Tamper Time Stamp Day Register; Several registers at the same address ***/ union { struct { word TIME_STAMP_DAY0 :1; /* Tamper detect days value bits, bit 0 */ word TIME_STAMP_DAY1 :1; /* Tamper detect days value bits, bit 1 */ word TIME_STAMP_DAY2 :1; /* Tamper detect days value bits, bit 2 */ word TIME_STAMP_DAY3 :1; /* Tamper detect days value bits, bit 3 */ word TIME_STAMP_DAY4 :1; /* Tamper detect days value bits, bit 4 */ word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpTIME_STAMP_DAY :5; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } IRTC_TTSR_DAY_binSTR; #define IRTC_TTSR_DAY_bin _IRTC_TTSR_DAY_bcd.Word #define IRTC_TTSR_DAY_bin_TIME_STAMP_DAY0 _IRTC_TTSR_DAY_bcd.SameAddr_STR.IRTC_TTSR_DAY_binSTR.Bits.TIME_STAMP_DAY0 #define IRTC_TTSR_DAY_bin_TIME_STAMP_DAY1 _IRTC_TTSR_DAY_bcd.SameAddr_STR.IRTC_TTSR_DAY_binSTR.Bits.TIME_STAMP_DAY1 #define IRTC_TTSR_DAY_bin_TIME_STAMP_DAY2 _IRTC_TTSR_DAY_bcd.SameAddr_STR.IRTC_TTSR_DAY_binSTR.Bits.TIME_STAMP_DAY2 #define IRTC_TTSR_DAY_bin_TIME_STAMP_DAY3 _IRTC_TTSR_DAY_bcd.SameAddr_STR.IRTC_TTSR_DAY_binSTR.Bits.TIME_STAMP_DAY3 #define IRTC_TTSR_DAY_bin_TIME_STAMP_DAY4 _IRTC_TTSR_DAY_bcd.SameAddr_STR.IRTC_TTSR_DAY_binSTR.Bits.TIME_STAMP_DAY4 #define IRTC_TTSR_DAY_bin_TIME_STAMP_DAY _IRTC_TTSR_DAY_bcd.SameAddr_STR.IRTC_TTSR_DAY_binSTR.MergedBits.grpTIME_STAMP_DAY #define IRTC_TTSR_DAY_bin_TIME_STAMP_DAY0_MASK 1 #define IRTC_TTSR_DAY_bin_TIME_STAMP_DAY1_MASK 2 #define IRTC_TTSR_DAY_bin_TIME_STAMP_DAY2_MASK 4 #define IRTC_TTSR_DAY_bin_TIME_STAMP_DAY3_MASK 8 #define IRTC_TTSR_DAY_bin_TIME_STAMP_DAY4_MASK 16 #define IRTC_TTSR_DAY_bin_TIME_STAMP_DAY_MASK 31 #define IRTC_TTSR_DAY_bin_TIME_STAMP_DAY_BITNUM 0 } SameAddr_STR; /*Several registers at the same address */ } IRTC_TTSR_DAY_bcdSTR; extern volatile IRTC_TTSR_DAY_bcdSTR _IRTC_TTSR_DAY_bcd @0xFFFF866C; /*** IRTC_TTSR_HM_bcd - RTC Tamper Time Stamp Hours & Minutes Register; 0xFFFF866E ***/ typedef union { word Word; union { /* Several registers at the same address */ /*** IRTC_TTSR_HM_bcd - RTC Tamper Time Stamp Hours & Minutes Register; Several registers at the same address ***/ union { struct { word TIME_STAMP_MINUTES_units0 :1; /* Tamper detect minutes units value bits, bit 0 */ word TIME_STAMP_MINUTES_units1 :1; /* Tamper detect minutes units value bits, bit 1 */ word TIME_STAMP_MINUTES_units2 :1; /* Tamper detect minutes units value bits, bit 2 */ word TIME_STAMP_MINUTES_units3 :1; /* Tamper detect minutes units value bits, bit 3 */ word TIME_STAMP_MINUTES_tens0 :1; /* Tamper detect minutes tens value bits, bit 0 */ word TIME_STAMP_MINUTES_tens1 :1; /* Tamper detect minutes tens value bits, bit 1 */ word TIME_STAMP_MINUTES_tens2 :1; /* Tamper detect minutes tens value bits, bit 2 */ word TIME_STAMP_MINUTES_tens3 :1; /* Tamper detect minutes tens value bits, bit 3 */ word TIME_STAMP_HOURS_units0 :1; /* Tamper detect hours units value bits, bit 0 */ word TIME_STAMP_HOURS_units1 :1; /* Tamper detect hours units value bits, bit 1 */ word TIME_STAMP_HOURS_units2 :1; /* Tamper detect hours units value bits, bit 2 */ word TIME_STAMP_HOURS_units3 :1; /* Tamper detect hours units value bits, bit 3 */ word TIME_STAMP_HOURS_tens0 :1; /* Tamper detect hours tens value bits, bit 0 */ word TIME_STAMP_HOURS_tens1 :1; /* Tamper detect hours tens value bits, bit 1 */ word TIME_STAMP_HOURS_tens2 :1; /* Tamper detect hours tens value bits, bit 2 */ word TIME_STAMP_HOURS_tens3 :1; /* Tamper detect hours tens value bits, bit 3 */ } Bits; struct { word grpTIME_STAMP_MINUTES_units :4; word grpTIME_STAMP_MINUTES_tens :4; word grpTIME_STAMP_HOURS_units :4; word grpTIME_STAMP_HOURS_tens :4; } MergedBits; } IRTC_TTSR_HM_bcdSTR; #define IRTC_TTSR_HM_bcd _IRTC_TTSR_HM_bcd.Word #define IRTC_TTSR_HM_bcd_TIME_STAMP_MINUTES_units0 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_bcdSTR.Bits.TIME_STAMP_MINUTES_units0 #define IRTC_TTSR_HM_bcd_TIME_STAMP_MINUTES_units1 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_bcdSTR.Bits.TIME_STAMP_MINUTES_units1 #define IRTC_TTSR_HM_bcd_TIME_STAMP_MINUTES_units2 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_bcdSTR.Bits.TIME_STAMP_MINUTES_units2 #define IRTC_TTSR_HM_bcd_TIME_STAMP_MINUTES_units3 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_bcdSTR.Bits.TIME_STAMP_MINUTES_units3 #define IRTC_TTSR_HM_bcd_TIME_STAMP_MINUTES_tens0 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_bcdSTR.Bits.TIME_STAMP_MINUTES_tens0 #define IRTC_TTSR_HM_bcd_TIME_STAMP_MINUTES_tens1 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_bcdSTR.Bits.TIME_STAMP_MINUTES_tens1 #define IRTC_TTSR_HM_bcd_TIME_STAMP_MINUTES_tens2 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_bcdSTR.Bits.TIME_STAMP_MINUTES_tens2 #define IRTC_TTSR_HM_bcd_TIME_STAMP_MINUTES_tens3 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_bcdSTR.Bits.TIME_STAMP_MINUTES_tens3 #define IRTC_TTSR_HM_bcd_TIME_STAMP_HOURS_units0 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_bcdSTR.Bits.TIME_STAMP_HOURS_units0 #define IRTC_TTSR_HM_bcd_TIME_STAMP_HOURS_units1 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_bcdSTR.Bits.TIME_STAMP_HOURS_units1 #define IRTC_TTSR_HM_bcd_TIME_STAMP_HOURS_units2 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_bcdSTR.Bits.TIME_STAMP_HOURS_units2 #define IRTC_TTSR_HM_bcd_TIME_STAMP_HOURS_units3 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_bcdSTR.Bits.TIME_STAMP_HOURS_units3 #define IRTC_TTSR_HM_bcd_TIME_STAMP_HOURS_tens0 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_bcdSTR.Bits.TIME_STAMP_HOURS_tens0 #define IRTC_TTSR_HM_bcd_TIME_STAMP_HOURS_tens1 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_bcdSTR.Bits.TIME_STAMP_HOURS_tens1 #define IRTC_TTSR_HM_bcd_TIME_STAMP_HOURS_tens2 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_bcdSTR.Bits.TIME_STAMP_HOURS_tens2 #define IRTC_TTSR_HM_bcd_TIME_STAMP_HOURS_tens3 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_bcdSTR.Bits.TIME_STAMP_HOURS_tens3 #define IRTC_TTSR_HM_bcd_TIME_STAMP_MINUTES_units _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_bcdSTR.MergedBits.grpTIME_STAMP_MINUTES_units #define IRTC_TTSR_HM_bcd_TIME_STAMP_MINUTES_tens _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_bcdSTR.MergedBits.grpTIME_STAMP_MINUTES_tens #define IRTC_TTSR_HM_bcd_TIME_STAMP_HOURS_units _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_bcdSTR.MergedBits.grpTIME_STAMP_HOURS_units #define IRTC_TTSR_HM_bcd_TIME_STAMP_HOURS_tens _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_bcdSTR.MergedBits.grpTIME_STAMP_HOURS_tens #define IRTC_TTSR_HM_bcd_TIME_STAMP_MINUTES_units0_MASK 1 #define IRTC_TTSR_HM_bcd_TIME_STAMP_MINUTES_units1_MASK 2 #define IRTC_TTSR_HM_bcd_TIME_STAMP_MINUTES_units2_MASK 4 #define IRTC_TTSR_HM_bcd_TIME_STAMP_MINUTES_units3_MASK 8 #define IRTC_TTSR_HM_bcd_TIME_STAMP_MINUTES_tens0_MASK 16 #define IRTC_TTSR_HM_bcd_TIME_STAMP_MINUTES_tens1_MASK 32 #define IRTC_TTSR_HM_bcd_TIME_STAMP_MINUTES_tens2_MASK 64 #define IRTC_TTSR_HM_bcd_TIME_STAMP_MINUTES_tens3_MASK 128 #define IRTC_TTSR_HM_bcd_TIME_STAMP_HOURS_units0_MASK 256 #define IRTC_TTSR_HM_bcd_TIME_STAMP_HOURS_units1_MASK 512 #define IRTC_TTSR_HM_bcd_TIME_STAMP_HOURS_units2_MASK 1024 #define IRTC_TTSR_HM_bcd_TIME_STAMP_HOURS_units3_MASK 2048 #define IRTC_TTSR_HM_bcd_TIME_STAMP_HOURS_tens0_MASK 4096 #define IRTC_TTSR_HM_bcd_TIME_STAMP_HOURS_tens1_MASK 8192 #define IRTC_TTSR_HM_bcd_TIME_STAMP_HOURS_tens2_MASK 16384 #define IRTC_TTSR_HM_bcd_TIME_STAMP_HOURS_tens3_MASK 32768 #define IRTC_TTSR_HM_bcd_TIME_STAMP_MINUTES_units_MASK 15 #define IRTC_TTSR_HM_bcd_TIME_STAMP_MINUTES_units_BITNUM 0 #define IRTC_TTSR_HM_bcd_TIME_STAMP_MINUTES_tens_MASK 240 #define IRTC_TTSR_HM_bcd_TIME_STAMP_MINUTES_tens_BITNUM 4 #define IRTC_TTSR_HM_bcd_TIME_STAMP_HOURS_units_MASK 3840 #define IRTC_TTSR_HM_bcd_TIME_STAMP_HOURS_units_BITNUM 8 #define IRTC_TTSR_HM_bcd_TIME_STAMP_HOURS_tens_MASK 61440 #define IRTC_TTSR_HM_bcd_TIME_STAMP_HOURS_tens_BITNUM 12 /*** IRTC_TTSR_HM_bin - RTC Tamper Time Stamp Hours & Minutes Register; Several registers at the same address ***/ union { struct { word TIME_STAMP_MINUTES0 :1; /* Tamper detect minutes value bits, bit 0 */ word TIME_STAMP_MINUTES1 :1; /* Tamper detect minutes value bits, bit 1 */ word TIME_STAMP_MINUTES2 :1; /* Tamper detect minutes value bits, bit 2 */ word TIME_STAMP_MINUTES3 :1; /* Tamper detect minutes value bits, bit 3 */ word TIME_STAMP_MINUTES4 :1; /* Tamper detect minutes value bits, bit 4 */ word TIME_STAMP_MINUTES5 :1; /* Tamper detect minutes value bits, bit 5 */ word :1; word :1; word TIME_STAMP_HOURS0 :1; /* Tamper detect hours value bits, bit 0 */ word TIME_STAMP_HOURS1 :1; /* Tamper detect hours value bits, bit 1 */ word TIME_STAMP_HOURS2 :1; /* Tamper detect hours value bits, bit 2 */ word TIME_STAMP_HOURS3 :1; /* Tamper detect hours value bits, bit 3 */ word TIME_STAMP_HOURS4 :1; /* Tamper detect hours value bits, bit 4 */ word :1; word :1; word :1; } Bits; struct { word grpTIME_STAMP_MINUTES :6; word :1; word :1; word grpTIME_STAMP_HOURS :5; word :1; word :1; word :1; } MergedBits; } IRTC_TTSR_HM_binSTR; #define IRTC_TTSR_HM_bin _IRTC_TTSR_HM_bcd.Word #define IRTC_TTSR_HM_bin_TIME_STAMP_MINUTES0 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_binSTR.Bits.TIME_STAMP_MINUTES0 #define IRTC_TTSR_HM_bin_TIME_STAMP_MINUTES1 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_binSTR.Bits.TIME_STAMP_MINUTES1 #define IRTC_TTSR_HM_bin_TIME_STAMP_MINUTES2 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_binSTR.Bits.TIME_STAMP_MINUTES2 #define IRTC_TTSR_HM_bin_TIME_STAMP_MINUTES3 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_binSTR.Bits.TIME_STAMP_MINUTES3 #define IRTC_TTSR_HM_bin_TIME_STAMP_MINUTES4 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_binSTR.Bits.TIME_STAMP_MINUTES4 #define IRTC_TTSR_HM_bin_TIME_STAMP_MINUTES5 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_binSTR.Bits.TIME_STAMP_MINUTES5 #define IRTC_TTSR_HM_bin_TIME_STAMP_HOURS0 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_binSTR.Bits.TIME_STAMP_HOURS0 #define IRTC_TTSR_HM_bin_TIME_STAMP_HOURS1 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_binSTR.Bits.TIME_STAMP_HOURS1 #define IRTC_TTSR_HM_bin_TIME_STAMP_HOURS2 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_binSTR.Bits.TIME_STAMP_HOURS2 #define IRTC_TTSR_HM_bin_TIME_STAMP_HOURS3 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_binSTR.Bits.TIME_STAMP_HOURS3 #define IRTC_TTSR_HM_bin_TIME_STAMP_HOURS4 _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_binSTR.Bits.TIME_STAMP_HOURS4 #define IRTC_TTSR_HM_bin_TIME_STAMP_MINUTES _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_binSTR.MergedBits.grpTIME_STAMP_MINUTES #define IRTC_TTSR_HM_bin_TIME_STAMP_HOURS _IRTC_TTSR_HM_bcd.SameAddr_STR.IRTC_TTSR_HM_binSTR.MergedBits.grpTIME_STAMP_HOURS #define IRTC_TTSR_HM_bin_TIME_STAMP_MINUTES0_MASK 1 #define IRTC_TTSR_HM_bin_TIME_STAMP_MINUTES1_MASK 2 #define IRTC_TTSR_HM_bin_TIME_STAMP_MINUTES2_MASK 4 #define IRTC_TTSR_HM_bin_TIME_STAMP_MINUTES3_MASK 8 #define IRTC_TTSR_HM_bin_TIME_STAMP_MINUTES4_MASK 16 #define IRTC_TTSR_HM_bin_TIME_STAMP_MINUTES5_MASK 32 #define IRTC_TTSR_HM_bin_TIME_STAMP_HOURS0_MASK 256 #define IRTC_TTSR_HM_bin_TIME_STAMP_HOURS1_MASK 512 #define IRTC_TTSR_HM_bin_TIME_STAMP_HOURS2_MASK 1024 #define IRTC_TTSR_HM_bin_TIME_STAMP_HOURS3_MASK 2048 #define IRTC_TTSR_HM_bin_TIME_STAMP_HOURS4_MASK 4096 #define IRTC_TTSR_HM_bin_TIME_STAMP_MINUTES_MASK 63 #define IRTC_TTSR_HM_bin_TIME_STAMP_MINUTES_BITNUM 0 #define IRTC_TTSR_HM_bin_TIME_STAMP_HOURS_MASK 7936 #define IRTC_TTSR_HM_bin_TIME_STAMP_HOURS_BITNUM 8 } SameAddr_STR; /*Several registers at the same address */ } IRTC_TTSR_HM_bcdSTR; extern volatile IRTC_TTSR_HM_bcdSTR _IRTC_TTSR_HM_bcd @0xFFFF866E; /*** IRTC_TTSR_SEC_bcd - RTC Tamper Time Stamp Seconds Register; 0xFFFF8670 ***/ typedef union { word Word; union { /* Several registers at the same address */ /*** IRTC_TTSR_SEC_bcd - RTC Tamper Time Stamp Seconds Register; Several registers at the same address ***/ union { struct { word TIME_STAMP_SECONDS_units0 :1; /* Tamper detect seconds units value bits, bit 0 */ word TIME_STAMP_SECONDS_units1 :1; /* Tamper detect seconds units value bits, bit 1 */ word TIME_STAMP_SECONDS_units2 :1; /* Tamper detect seconds units value bits, bit 2 */ word TIME_STAMP_SECONDS_units3 :1; /* Tamper detect seconds units value bits, bit 3 */ word TIME_STAMP_SECONDS_tens0 :1; /* Tamper detect seconds tens value bits, bit 0 */ word TIME_STAMP_SECONDS_tens1 :1; /* Tamper detect seconds tens value bits, bit 1 */ word TIME_STAMP_SECONDS_tens2 :1; /* Tamper detect seconds tens value bits, bit 2 */ word TIME_STAMP_SECONDS_tens3 :1; /* Tamper detect seconds tens value bits, bit 3 */ word STATUS0 :1; /* Tamper detect status bits, bit 0 */ word STATUS1 :1; /* Tamper detect status bits, bit 1 */ word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpTIME_STAMP_SECONDS_units :4; word grpTIME_STAMP_SECONDS_tens :4; word grpSTATUS :2; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } IRTC_TTSR_SEC_bcdSTR; #define IRTC_TTSR_SEC_bcd _IRTC_TTSR_SEC_bcd.Word #define IRTC_TTSR_SEC_bcd_TIME_STAMP_SECONDS_units0 _IRTC_TTSR_SEC_bcd.SameAddr_STR.IRTC_TTSR_SEC_bcdSTR.Bits.TIME_STAMP_SECONDS_units0 #define IRTC_TTSR_SEC_bcd_TIME_STAMP_SECONDS_units1 _IRTC_TTSR_SEC_bcd.SameAddr_STR.IRTC_TTSR_SEC_bcdSTR.Bits.TIME_STAMP_SECONDS_units1 #define IRTC_TTSR_SEC_bcd_TIME_STAMP_SECONDS_units2 _IRTC_TTSR_SEC_bcd.SameAddr_STR.IRTC_TTSR_SEC_bcdSTR.Bits.TIME_STAMP_SECONDS_units2 #define IRTC_TTSR_SEC_bcd_TIME_STAMP_SECONDS_units3 _IRTC_TTSR_SEC_bcd.SameAddr_STR.IRTC_TTSR_SEC_bcdSTR.Bits.TIME_STAMP_SECONDS_units3 #define IRTC_TTSR_SEC_bcd_TIME_STAMP_SECONDS_tens0 _IRTC_TTSR_SEC_bcd.SameAddr_STR.IRTC_TTSR_SEC_bcdSTR.Bits.TIME_STAMP_SECONDS_tens0 #define IRTC_TTSR_SEC_bcd_TIME_STAMP_SECONDS_tens1 _IRTC_TTSR_SEC_bcd.SameAddr_STR.IRTC_TTSR_SEC_bcdSTR.Bits.TIME_STAMP_SECONDS_tens1 #define IRTC_TTSR_SEC_bcd_TIME_STAMP_SECONDS_tens2 _IRTC_TTSR_SEC_bcd.SameAddr_STR.IRTC_TTSR_SEC_bcdSTR.Bits.TIME_STAMP_SECONDS_tens2 #define IRTC_TTSR_SEC_bcd_TIME_STAMP_SECONDS_tens3 _IRTC_TTSR_SEC_bcd.SameAddr_STR.IRTC_TTSR_SEC_bcdSTR.Bits.TIME_STAMP_SECONDS_tens3 #define IRTC_TTSR_SEC_bcd_STATUS0 _IRTC_TTSR_SEC_bcd.SameAddr_STR.IRTC_TTSR_SEC_bcdSTR.Bits.STATUS0 #define IRTC_TTSR_SEC_bcd_STATUS1 _IRTC_TTSR_SEC_bcd.SameAddr_STR.IRTC_TTSR_SEC_bcdSTR.Bits.STATUS1 #define IRTC_TTSR_SEC_bcd_TIME_STAMP_SECONDS_units _IRTC_TTSR_SEC_bcd.SameAddr_STR.IRTC_TTSR_SEC_bcdSTR.MergedBits.grpTIME_STAMP_SECONDS_units #define IRTC_TTSR_SEC_bcd_TIME_STAMP_SECONDS_tens _IRTC_TTSR_SEC_bcd.SameAddr_STR.IRTC_TTSR_SEC_bcdSTR.MergedBits.grpTIME_STAMP_SECONDS_tens #define IRTC_TTSR_SEC_bcd_STATUS _IRTC_TTSR_SEC_bcd.SameAddr_STR.IRTC_TTSR_SEC_bcdSTR.MergedBits.grpSTATUS #define IRTC_TTSR_SEC_bcd_TIME_STAMP_SECONDS_units0_MASK 1 #define IRTC_TTSR_SEC_bcd_TIME_STAMP_SECONDS_units1_MASK 2 #define IRTC_TTSR_SEC_bcd_TIME_STAMP_SECONDS_units2_MASK 4 #define IRTC_TTSR_SEC_bcd_TIME_STAMP_SECONDS_units3_MASK 8 #define IRTC_TTSR_SEC_bcd_TIME_STAMP_SECONDS_tens0_MASK 16 #define IRTC_TTSR_SEC_bcd_TIME_STAMP_SECONDS_tens1_MASK 32 #define IRTC_TTSR_SEC_bcd_TIME_STAMP_SECONDS_tens2_MASK 64 #define IRTC_TTSR_SEC_bcd_TIME_STAMP_SECONDS_tens3_MASK 128 #define IRTC_TTSR_SEC_bcd_STATUS0_MASK 256 #define IRTC_TTSR_SEC_bcd_STATUS1_MASK 512 #define IRTC_TTSR_SEC_bcd_TIME_STAMP_SECONDS_units_MASK 15 #define IRTC_TTSR_SEC_bcd_TIME_STAMP_SECONDS_units_BITNUM 0 #define IRTC_TTSR_SEC_bcd_TIME_STAMP_SECONDS_tens_MASK 240 #define IRTC_TTSR_SEC_bcd_TIME_STAMP_SECONDS_tens_BITNUM 4 #define IRTC_TTSR_SEC_bcd_STATUS_MASK 768 #define IRTC_TTSR_SEC_bcd_STATUS_BITNUM 8 /*** IRTC_TTSR_SEC_bin - RTC Tamper Time Stamp Seconds Register; Several registers at the same address ***/ union { struct { word TIME_STAMP_SECONDS0 :1; /* Tamper detect seconds value bits, bit 0 */ word TIME_STAMP_SECONDS1 :1; /* Tamper detect seconds value bits, bit 1 */ word TIME_STAMP_SECONDS2 :1; /* Tamper detect seconds value bits, bit 2 */ word TIME_STAMP_SECONDS3 :1; /* Tamper detect seconds value bits, bit 3 */ word TIME_STAMP_SECONDS4 :1; /* Tamper detect seconds value bits, bit 4 */ word TIME_STAMP_SECONDS5 :1; /* Tamper detect seconds value bits, bit 5 */ word :1; word :1; word STATUS0 :1; /* Tamper detect status bits, bit 0 */ word STATUS1 :1; /* Tamper detect status bits, bit 1 */ word :1; word :1; word :1; word :1; word :1; word :1; } Bits; struct { word grpTIME_STAMP_SECONDS :6; word :1; word :1; word grpSTATUS :2; word :1; word :1; word :1; word :1; word :1; word :1; } MergedBits; } IRTC_TTSR_SEC_binSTR; #define IRTC_TTSR_SEC_bin _IRTC_TTSR_SEC_bcd.Word #define IRTC_TTSR_SEC_bin_TIME_STAMP_SECONDS0 _IRTC_TTSR_SEC_bcd.SameAddr_STR.IRTC_TTSR_SEC_binSTR.Bits.TIME_STAMP_SECONDS0 #define IRTC_TTSR_SEC_bin_TIME_STAMP_SECONDS1 _IRTC_TTSR_SEC_bcd.SameAddr_STR.IRTC_TTSR_SEC_binSTR.Bits.TIME_STAMP_SECONDS1 #define IRTC_TTSR_SEC_bin_TIME_STAMP_SECONDS2 _IRTC_TTSR_SEC_bcd.SameAddr_STR.IRTC_TTSR_SEC_binSTR.Bits.TIME_STAMP_SECONDS2 #define IRTC_TTSR_SEC_bin_TIME_STAMP_SECONDS3 _IRTC_TTSR_SEC_bcd.SameAddr_STR.IRTC_TTSR_SEC_binSTR.Bits.TIME_STAMP_SECONDS3 #define IRTC_TTSR_SEC_bin_TIME_STAMP_SECONDS4 _IRTC_TTSR_SEC_bcd.SameAddr_STR.IRTC_TTSR_SEC_binSTR.Bits.TIME_STAMP_SECONDS4 #define IRTC_TTSR_SEC_bin_TIME_STAMP_SECONDS5 _IRTC_TTSR_SEC_bcd.SameAddr_STR.IRTC_TTSR_SEC_binSTR.Bits.TIME_STAMP_SECONDS5 #define IRTC_TTSR_SEC_bin_STATUS0 _IRTC_TTSR_SEC_bcd.SameAddr_STR.IRTC_TTSR_SEC_binSTR.Bits.STATUS0 #define IRTC_TTSR_SEC_bin_STATUS1 _IRTC_TTSR_SEC_bcd.SameAddr_STR.IRTC_TTSR_SEC_binSTR.Bits.STATUS1 #define IRTC_TTSR_SEC_bin_TIME_STAMP_SECONDS _IRTC_TTSR_SEC_bcd.SameAddr_STR.IRTC_TTSR_SEC_binSTR.MergedBits.grpTIME_STAMP_SECONDS #define IRTC_TTSR_SEC_bin_STATUS _IRTC_TTSR_SEC_bcd.SameAddr_STR.IRTC_TTSR_SEC_binSTR.MergedBits.grpSTATUS #define IRTC_TTSR_SEC_bin_TIME_STAMP_SECONDS0_MASK 1 #define IRTC_TTSR_SEC_bin_TIME_STAMP_SECONDS1_MASK 2 #define IRTC_TTSR_SEC_bin_TIME_STAMP_SECONDS2_MASK 4 #define IRTC_TTSR_SEC_bin_TIME_STAMP_SECONDS3_MASK 8 #define IRTC_TTSR_SEC_bin_TIME_STAMP_SECONDS4_MASK 16 #define IRTC_TTSR_SEC_bin_TIME_STAMP_SECONDS5_MASK 32 #define IRTC_TTSR_SEC_bin_STATUS0_MASK 256 #define IRTC_TTSR_SEC_bin_STATUS1_MASK 512 #define IRTC_TTSR_SEC_bin_TIME_STAMP_SECONDS_MASK 63 #define IRTC_TTSR_SEC_bin_TIME_STAMP_SECONDS_BITNUM 0 #define IRTC_TTSR_SEC_bin_STATUS_MASK 768 #define IRTC_TTSR_SEC_bin_STATUS_BITNUM 8 } SameAddr_STR; /*Several registers at the same address */ } IRTC_TTSR_SEC_bcdSTR; extern volatile IRTC_TTSR_SEC_bcdSTR _IRTC_TTSR_SEC_bcd @0xFFFF8670; /*** IRTC_UP_CNTR_H - RTC Up-Counter Higher Register; 0xFFFF8672 ***/ typedef union { word Word; struct { word BYTE20 :1; /* Up counter upper word byte 2, bit 0 */ word BYTE21 :1; /* Up counter upper word byte 2, bit 1 */ word BYTE22 :1; /* Up counter upper word byte 2, bit 2 */ word BYTE23 :1; /* Up counter upper word byte 2, bit 3 */ word BYTE24 :1; /* Up counter upper word byte 2, bit 4 */ word BYTE25 :1; /* Up counter upper word byte 2, bit 5 */ word BYTE26 :1; /* Up counter upper word byte 2, bit 6 */ word BYTE27 :1; /* Up counter upper word byte 2, bit 7 */ word BYTE30 :1; /* Up counter upper word byte 3, bit 0 */ word BYTE31 :1; /* Up counter upper word byte 3, bit 1 */ word BYTE32 :1; /* Up counter upper word byte 3, bit 2 */ word BYTE33 :1; /* Up counter upper word byte 3, bit 3 */ word BYTE34 :1; /* Up counter upper word byte 3, bit 4 */ word BYTE35 :1; /* Up counter upper word byte 3, bit 5 */ word BYTE36 :1; /* Up counter upper word byte 3, bit 6 */ word BYTE37 :1; /* Up counter upper word byte 3, bit 7 */ } Bits; struct { word grpBYTE2 :8; word grpBYTE3 :8; } MergedBits; } IRTC_UP_CNTR_HSTR; extern volatile IRTC_UP_CNTR_HSTR _IRTC_UP_CNTR_H @0xFFFF8672; #define IRTC_UP_CNTR_H _IRTC_UP_CNTR_H.Word #define IRTC_UP_CNTR_H_BYTE20 _IRTC_UP_CNTR_H.Bits.BYTE20 #define IRTC_UP_CNTR_H_BYTE21 _IRTC_UP_CNTR_H.Bits.BYTE21 #define IRTC_UP_CNTR_H_BYTE22 _IRTC_UP_CNTR_H.Bits.BYTE22 #define IRTC_UP_CNTR_H_BYTE23 _IRTC_UP_CNTR_H.Bits.BYTE23 #define IRTC_UP_CNTR_H_BYTE24 _IRTC_UP_CNTR_H.Bits.BYTE24 #define IRTC_UP_CNTR_H_BYTE25 _IRTC_UP_CNTR_H.Bits.BYTE25 #define IRTC_UP_CNTR_H_BYTE26 _IRTC_UP_CNTR_H.Bits.BYTE26 #define IRTC_UP_CNTR_H_BYTE27 _IRTC_UP_CNTR_H.Bits.BYTE27 #define IRTC_UP_CNTR_H_BYTE30 _IRTC_UP_CNTR_H.Bits.BYTE30 #define IRTC_UP_CNTR_H_BYTE31 _IRTC_UP_CNTR_H.Bits.BYTE31 #define IRTC_UP_CNTR_H_BYTE32 _IRTC_UP_CNTR_H.Bits.BYTE32 #define IRTC_UP_CNTR_H_BYTE33 _IRTC_UP_CNTR_H.Bits.BYTE33 #define IRTC_UP_CNTR_H_BYTE34 _IRTC_UP_CNTR_H.Bits.BYTE34 #define IRTC_UP_CNTR_H_BYTE35 _IRTC_UP_CNTR_H.Bits.BYTE35 #define IRTC_UP_CNTR_H_BYTE36 _IRTC_UP_CNTR_H.Bits.BYTE36 #define IRTC_UP_CNTR_H_BYTE37 _IRTC_UP_CNTR_H.Bits.BYTE37 #define IRTC_UP_CNTR_H_BYTE2 _IRTC_UP_CNTR_H.MergedBits.grpBYTE2 #define IRTC_UP_CNTR_H_BYTE3 _IRTC_UP_CNTR_H.MergedBits.grpBYTE3 #define IRTC_UP_CNTR_H_BYTE20_MASK 1 #define IRTC_UP_CNTR_H_BYTE21_MASK 2 #define IRTC_UP_CNTR_H_BYTE22_MASK 4 #define IRTC_UP_CNTR_H_BYTE23_MASK 8 #define IRTC_UP_CNTR_H_BYTE24_MASK 16 #define IRTC_UP_CNTR_H_BYTE25_MASK 32 #define IRTC_UP_CNTR_H_BYTE26_MASK 64 #define IRTC_UP_CNTR_H_BYTE27_MASK 128 #define IRTC_UP_CNTR_H_BYTE30_MASK 256 #define IRTC_UP_CNTR_H_BYTE31_MASK 512 #define IRTC_UP_CNTR_H_BYTE32_MASK 1024 #define IRTC_UP_CNTR_H_BYTE33_MASK 2048 #define IRTC_UP_CNTR_H_BYTE34_MASK 4096 #define IRTC_UP_CNTR_H_BYTE35_MASK 8192 #define IRTC_UP_CNTR_H_BYTE36_MASK 16384 #define IRTC_UP_CNTR_H_BYTE37_MASK 32768 #define IRTC_UP_CNTR_H_BYTE2_MASK 255 #define IRTC_UP_CNTR_H_BYTE2_BITNUM 0 #define IRTC_UP_CNTR_H_BYTE3_MASK 65280 #define IRTC_UP_CNTR_H_BYTE3_BITNUM 8 /*** IRTC_UP_CNTR_L - RTC Up-Counter Lower Register; 0xFFFF8674 ***/ typedef union { word Word; struct { word BYTE00 :1; /* Up counter upper word byte 0, bit 0 */ word BYTE01 :1; /* Up counter upper word byte 0, bit 1 */ word BYTE02 :1; /* Up counter upper word byte 0, bit 2 */ word BYTE03 :1; /* Up counter upper word byte 0, bit 3 */ word BYTE04 :1; /* Up counter upper word byte 0, bit 4 */ word BYTE05 :1; /* Up counter upper word byte 0, bit 5 */ word BYTE06 :1; /* Up counter upper word byte 0, bit 6 */ word BYTE07 :1; /* Up counter upper word byte 0, bit 7 */ word BYTE10 :1; /* Up counter upper word byte 1, bit 0 */ word BYTE11 :1; /* Up counter upper word byte 1, bit 1 */ word BYTE12 :1; /* Up counter upper word byte 1, bit 2 */ word BYTE13 :1; /* Up counter upper word byte 1, bit 3 */ word BYTE14 :1; /* Up counter upper word byte 1, bit 4 */ word BYTE15 :1; /* Up counter upper word byte 1, bit 5 */ word BYTE16 :1; /* Up counter upper word byte 1, bit 6 */ word BYTE17 :1; /* Up counter upper word byte 1, bit 7 */ } Bits; struct { word grpBYTE0 :8; word grpBYTE1 :8; } MergedBits; } IRTC_UP_CNTR_LSTR; extern volatile IRTC_UP_CNTR_LSTR _IRTC_UP_CNTR_L @0xFFFF8674; #define IRTC_UP_CNTR_L _IRTC_UP_CNTR_L.Word #define IRTC_UP_CNTR_L_BYTE00 _IRTC_UP_CNTR_L.Bits.BYTE00 #define IRTC_UP_CNTR_L_BYTE01 _IRTC_UP_CNTR_L.Bits.BYTE01 #define IRTC_UP_CNTR_L_BYTE02 _IRTC_UP_CNTR_L.Bits.BYTE02 #define IRTC_UP_CNTR_L_BYTE03 _IRTC_UP_CNTR_L.Bits.BYTE03 #define IRTC_UP_CNTR_L_BYTE04 _IRTC_UP_CNTR_L.Bits.BYTE04 #define IRTC_UP_CNTR_L_BYTE05 _IRTC_UP_CNTR_L.Bits.BYTE05 #define IRTC_UP_CNTR_L_BYTE06 _IRTC_UP_CNTR_L.Bits.BYTE06 #define IRTC_UP_CNTR_L_BYTE07 _IRTC_UP_CNTR_L.Bits.BYTE07 #define IRTC_UP_CNTR_L_BYTE10 _IRTC_UP_CNTR_L.Bits.BYTE10 #define IRTC_UP_CNTR_L_BYTE11 _IRTC_UP_CNTR_L.Bits.BYTE11 #define IRTC_UP_CNTR_L_BYTE12 _IRTC_UP_CNTR_L.Bits.BYTE12 #define IRTC_UP_CNTR_L_BYTE13 _IRTC_UP_CNTR_L.Bits.BYTE13 #define IRTC_UP_CNTR_L_BYTE14 _IRTC_UP_CNTR_L.Bits.BYTE14 #define IRTC_UP_CNTR_L_BYTE15 _IRTC_UP_CNTR_L.Bits.BYTE15 #define IRTC_UP_CNTR_L_BYTE16 _IRTC_UP_CNTR_L.Bits.BYTE16 #define IRTC_UP_CNTR_L_BYTE17 _IRTC_UP_CNTR_L.Bits.BYTE17 #define IRTC_UP_CNTR_L_BYTE0 _IRTC_UP_CNTR_L.MergedBits.grpBYTE0 #define IRTC_UP_CNTR_L_BYTE1 _IRTC_UP_CNTR_L.MergedBits.grpBYTE1 #define IRTC_UP_CNTR_L_BYTE00_MASK 1 #define IRTC_UP_CNTR_L_BYTE01_MASK 2 #define IRTC_UP_CNTR_L_BYTE02_MASK 4 #define IRTC_UP_CNTR_L_BYTE03_MASK 8 #define IRTC_UP_CNTR_L_BYTE04_MASK 16 #define IRTC_UP_CNTR_L_BYTE05_MASK 32 #define IRTC_UP_CNTR_L_BYTE06_MASK 64 #define IRTC_UP_CNTR_L_BYTE07_MASK 128 #define IRTC_UP_CNTR_L_BYTE10_MASK 256 #define IRTC_UP_CNTR_L_BYTE11_MASK 512 #define IRTC_UP_CNTR_L_BYTE12_MASK 1024 #define IRTC_UP_CNTR_L_BYTE13_MASK 2048 #define IRTC_UP_CNTR_L_BYTE14_MASK 4096 #define IRTC_UP_CNTR_L_BYTE15_MASK 8192 #define IRTC_UP_CNTR_L_BYTE16_MASK 16384 #define IRTC_UP_CNTR_L_BYTE17_MASK 32768 #define IRTC_UP_CNTR_L_BYTE0_MASK 255 #define IRTC_UP_CNTR_L_BYTE0_BITNUM 0 #define IRTC_UP_CNTR_L_BYTE1_MASK 65280 #define IRTC_UP_CNTR_L_BYTE1_BITNUM 8 /*** LCDC0 - LCD Control Register 0; 0xFFFF8700 ***/ typedef union { byte Byte; struct { byte DUTY0 :1; /* LCD Duty Select Bit 0 */ byte DUTY1 :1; /* LCD Duty Select Bit 1 */ byte DUTY2 :1; /* LCD Duty Select Bit 2 */ byte LCLK0 :1; /* LCD Clock Prescaler Bit 0 */ byte LCLK1 :1; /* LCD Clock Prescaler Bit 1 */ byte LCLK2 :1; /* LCD Clock Prescaler Bit 2 */ byte SOURCE :1; /* LCD Clock Source Select */ byte LCDEN :1; /* LCD Driver Enable */ } Bits; struct { byte grpDUTY :3; byte grpLCLK :3; byte :1; byte :1; } MergedBits; } LCDC0STR; extern volatile LCDC0STR _LCDC0 @0xFFFF8700; #define LCDC0 _LCDC0.Byte #define LCDC0_DUTY0 _LCDC0.Bits.DUTY0 #define LCDC0_DUTY1 _LCDC0.Bits.DUTY1 #define LCDC0_DUTY2 _LCDC0.Bits.DUTY2 #define LCDC0_LCLK0 _LCDC0.Bits.LCLK0 #define LCDC0_LCLK1 _LCDC0.Bits.LCLK1 #define LCDC0_LCLK2 _LCDC0.Bits.LCLK2 #define LCDC0_SOURCE _LCDC0.Bits.SOURCE #define LCDC0_LCDEN _LCDC0.Bits.LCDEN /* LCDC_ARR: Access 2 LCDCx registers in an array */ #define LCDC_ARR ((volatile byte *) &LCDC0) #define LCDC0_DUTY _LCDC0.MergedBits.grpDUTY #define LCDC0_LCLK _LCDC0.MergedBits.grpLCLK #define LCDC0_DUTY0_MASK 1 #define LCDC0_DUTY1_MASK 2 #define LCDC0_DUTY2_MASK 4 #define LCDC0_LCLK0_MASK 8 #define LCDC0_LCLK1_MASK 16 #define LCDC0_LCLK2_MASK 32 #define LCDC0_SOURCE_MASK 64 #define LCDC0_LCDEN_MASK 128 #define LCDC0_DUTY_MASK 7 #define LCDC0_DUTY_BITNUM 0 #define LCDC0_LCLK_MASK 56 #define LCDC0_LCLK_BITNUM 3 /*** LCDC1 - LCD Control Register 1; 0xFFFF8701 ***/ typedef union { byte Byte; struct { byte LCDSTP :1; /* LCD Module Driver and Charge Pump Stop While in Stop2 or Stop3 Mode */ byte LCDWAI :1; /* LCD Module Driver and Charge Pump Stop While in Wait Mode */ byte FCDEN :1; /* Full Complementary Drive Enable */ byte :1; byte :1; byte :1; byte :1; byte LCDIEN :1; /* LCD Module Frame Frequency Interrupt Enable */ } Bits; } LCDC1STR; extern volatile LCDC1STR _LCDC1 @0xFFFF8701; #define LCDC1 _LCDC1.Byte #define LCDC1_LCDSTP _LCDC1.Bits.LCDSTP #define LCDC1_LCDWAI _LCDC1.Bits.LCDWAI #define LCDC1_FCDEN _LCDC1.Bits.FCDEN #define LCDC1_LCDIEN _LCDC1.Bits.LCDIEN #define LCDC1_LCDSTP_MASK 1 #define LCDC1_LCDWAI_MASK 2 #define LCDC1_FCDEN_MASK 4 #define LCDC1_LCDIEN_MASK 128 /*** LCDSUPPLY - LCD Voltage Supply Register; 0xFFFF8702 ***/ typedef union { byte Byte; struct { byte VSUPPLY0 :1; /* Voltage Supply Control Bit 0 */ byte VSUPPLY1 :1; /* Voltage Supply Control Bit 1 */ byte BBYPASS :1; /* Op Amp Control */ byte :1; byte LADJ0 :1; /* LCD Module Load Adjust Bit 0 */ byte LADJ1 :1; /* LCD Module Load Adjust Bit 1 */ byte HREFSEL :1; /* High Reference Select */ byte CPSEL :1; /* Charge Pump or Resistor Bias Select */ } Bits; struct { byte grpVSUPPLY :2; byte :1; byte :1; byte grpLADJ :2; byte :1; byte :1; } MergedBits; } LCDSUPPLYSTR; extern volatile LCDSUPPLYSTR _LCDSUPPLY @0xFFFF8702; #define LCDSUPPLY _LCDSUPPLY.Byte #define LCDSUPPLY_VSUPPLY0 _LCDSUPPLY.Bits.VSUPPLY0 #define LCDSUPPLY_VSUPPLY1 _LCDSUPPLY.Bits.VSUPPLY1 #define LCDSUPPLY_BBYPASS _LCDSUPPLY.Bits.BBYPASS #define LCDSUPPLY_LADJ0 _LCDSUPPLY.Bits.LADJ0 #define LCDSUPPLY_LADJ1 _LCDSUPPLY.Bits.LADJ1 #define LCDSUPPLY_HREFSEL _LCDSUPPLY.Bits.HREFSEL #define LCDSUPPLY_CPSEL _LCDSUPPLY.Bits.CPSEL #define LCDSUPPLY_VSUPPLY _LCDSUPPLY.MergedBits.grpVSUPPLY #define LCDSUPPLY_LADJ _LCDSUPPLY.MergedBits.grpLADJ #define LCDSUPPLY_VSUPPLY0_MASK 1 #define LCDSUPPLY_VSUPPLY1_MASK 2 #define LCDSUPPLY_BBYPASS_MASK 4 #define LCDSUPPLY_LADJ0_MASK 16 #define LCDSUPPLY_LADJ1_MASK 32 #define LCDSUPPLY_HREFSEL_MASK 64 #define LCDSUPPLY_CPSEL_MASK 128 #define LCDSUPPLY_VSUPPLY_MASK 3 #define LCDSUPPLY_VSUPPLY_BITNUM 0 #define LCDSUPPLY_LADJ_MASK 48 #define LCDSUPPLY_LADJ_BITNUM 4 /*** LCDRVC - LCD Regulated Voltage Control Register; 0xFFFF8703 ***/ typedef union { byte Byte; struct { byte RVTRIM0 :1; /* Regulated Voltage Trim Bit 0 */ byte RVTRIM1 :1; /* Regulated Voltage Trim Bit 1 */ byte RVTRIM2 :1; /* Regulated Voltage Trim Bit 2 */ byte RVTRIM3 :1; /* Regulated Voltage Trim Bit 3 */ byte :1; byte :1; byte :1; byte RVEN :1; /* Regulated Voltage Enable */ } Bits; struct { byte grpRVTRIM :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } LCDRVCSTR; extern volatile LCDRVCSTR _LCDRVC @0xFFFF8703; #define LCDRVC _LCDRVC.Byte #define LCDRVC_RVTRIM0 _LCDRVC.Bits.RVTRIM0 #define LCDRVC_RVTRIM1 _LCDRVC.Bits.RVTRIM1 #define LCDRVC_RVTRIM2 _LCDRVC.Bits.RVTRIM2 #define LCDRVC_RVTRIM3 _LCDRVC.Bits.RVTRIM3 #define LCDRVC_RVEN _LCDRVC.Bits.RVEN #define LCDRVC_RVTRIM _LCDRVC.MergedBits.grpRVTRIM #define LCDRVC_RVTRIM0_MASK 1 #define LCDRVC_RVTRIM1_MASK 2 #define LCDRVC_RVTRIM2_MASK 4 #define LCDRVC_RVTRIM3_MASK 8 #define LCDRVC_RVEN_MASK 128 #define LCDRVC_RVTRIM_MASK 15 #define LCDRVC_RVTRIM_BITNUM 0 /*** LCDBCTL - LCD Blink Control Register; 0xFFFF8704 ***/ typedef union { byte Byte; struct { byte BRATE0 :1; /* Blink-Rate Configuration Bit 0 */ byte BRATE1 :1; /* Blink-Rate Configuration Bit 1 */ byte BRATE2 :1; /* Blink-Rate Configuration Bit 2 */ byte BMODE :1; /* Blink Mode */ byte :1; byte BLANK :1; /* Blank Display Mode */ byte ALT :1; /* Alternate Display Mode */ byte BLINK :1; /* Blink Command */ } Bits; struct { byte grpBRATE :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } LCDBCTLSTR; extern volatile LCDBCTLSTR _LCDBCTL @0xFFFF8704; #define LCDBCTL _LCDBCTL.Byte #define LCDBCTL_BRATE0 _LCDBCTL.Bits.BRATE0 #define LCDBCTL_BRATE1 _LCDBCTL.Bits.BRATE1 #define LCDBCTL_BRATE2 _LCDBCTL.Bits.BRATE2 #define LCDBCTL_BMODE _LCDBCTL.Bits.BMODE #define LCDBCTL_BLANK _LCDBCTL.Bits.BLANK #define LCDBCTL_ALT _LCDBCTL.Bits.ALT #define LCDBCTL_BLINK _LCDBCTL.Bits.BLINK #define LCDBCTL_BRATE _LCDBCTL.MergedBits.grpBRATE #define LCDBCTL_BRATE0_MASK 1 #define LCDBCTL_BRATE1_MASK 2 #define LCDBCTL_BRATE2_MASK 4 #define LCDBCTL_BMODE_MASK 8 #define LCDBCTL_BLANK_MASK 32 #define LCDBCTL_ALT_MASK 64 #define LCDBCTL_BLINK_MASK 128 #define LCDBCTL_BRATE_MASK 7 #define LCDBCTL_BRATE_BITNUM 0 /*** LCDS - LCD Status Register; 0xFFFF8705 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte :1; byte LCDIF :1; /* LCD Interrupt Flag */ } Bits; } LCDSSTR; extern volatile LCDSSTR _LCDS @0xFFFF8705; #define LCDS _LCDS.Byte #define LCDS_LCDIF _LCDS.Bits.LCDIF #define LCDS_LCDIF_MASK 128 /*** LCDPEN0 - LCD Pin Enable Register 0; 0xFFFF8706 ***/ typedef union { byte Byte; struct { byte PEN0 :1; /* Enable LCD pin 0 for LCD operation */ byte PEN1 :1; /* Enable LCD pin 1 for LCD operation */ byte PEN2 :1; /* Enable LCD pin 2 for LCD operation */ byte PEN3 :1; /* Enable LCD pin 3 for LCD operation */ byte PEN4 :1; /* Enable LCD pin 4 for LCD operation */ byte PEN5 :1; /* Enable LCD pin 5 for LCD operation */ byte PEN6 :1; /* Enable LCD pin 6 for LCD operation */ byte PEN7 :1; /* Enable LCD pin 7 for LCD operation */ } Bits; } LCDPEN0STR; extern volatile LCDPEN0STR _LCDPEN0 @0xFFFF8706; #define LCDPEN0 _LCDPEN0.Byte #define LCDPEN0_PEN0 _LCDPEN0.Bits.PEN0 #define LCDPEN0_PEN1 _LCDPEN0.Bits.PEN1 #define LCDPEN0_PEN2 _LCDPEN0.Bits.PEN2 #define LCDPEN0_PEN3 _LCDPEN0.Bits.PEN3 #define LCDPEN0_PEN4 _LCDPEN0.Bits.PEN4 #define LCDPEN0_PEN5 _LCDPEN0.Bits.PEN5 #define LCDPEN0_PEN6 _LCDPEN0.Bits.PEN6 #define LCDPEN0_PEN7 _LCDPEN0.Bits.PEN7 /* LCDPEN_ARR: Access 6 LCDPENx registers in an array */ #define LCDPEN_ARR ((volatile byte *) &LCDPEN0) #define LCDPEN0_PEN0_MASK 1 #define LCDPEN0_PEN1_MASK 2 #define LCDPEN0_PEN2_MASK 4 #define LCDPEN0_PEN3_MASK 8 #define LCDPEN0_PEN4_MASK 16 #define LCDPEN0_PEN5_MASK 32 #define LCDPEN0_PEN6_MASK 64 #define LCDPEN0_PEN7_MASK 128 /*** LCDPEN1 - LCD Pin Enable Register 1; 0xFFFF8707 ***/ typedef union { byte Byte; struct { byte PEN8 :1; /* Enable LCD pin 8 for LCD operation */ byte PEN9 :1; /* Enable LCD pin 9 for LCD operation */ byte PEN10 :1; /* Enable LCD pin 10 for LCD operation */ byte PEN11 :1; /* Enable LCD pin 11 for LCD operation */ byte PEN12 :1; /* Enable LCD pin 12 for LCD operation */ byte PEN13 :1; /* Enable LCD pin 13 for LCD operation */ byte PEN14 :1; /* Enable LCD pin 14 for LCD operation */ byte PEN15 :1; /* Enable LCD pin 15 for LCD operation */ } Bits; } LCDPEN1STR; extern volatile LCDPEN1STR _LCDPEN1 @0xFFFF8707; #define LCDPEN1 _LCDPEN1.Byte #define LCDPEN1_PEN8 _LCDPEN1.Bits.PEN8 #define LCDPEN1_PEN9 _LCDPEN1.Bits.PEN9 #define LCDPEN1_PEN10 _LCDPEN1.Bits.PEN10 #define LCDPEN1_PEN11 _LCDPEN1.Bits.PEN11 #define LCDPEN1_PEN12 _LCDPEN1.Bits.PEN12 #define LCDPEN1_PEN13 _LCDPEN1.Bits.PEN13 #define LCDPEN1_PEN14 _LCDPEN1.Bits.PEN14 #define LCDPEN1_PEN15 _LCDPEN1.Bits.PEN15 #define LCDPEN1_PEN8_MASK 1 #define LCDPEN1_PEN9_MASK 2 #define LCDPEN1_PEN10_MASK 4 #define LCDPEN1_PEN11_MASK 8 #define LCDPEN1_PEN12_MASK 16 #define LCDPEN1_PEN13_MASK 32 #define LCDPEN1_PEN14_MASK 64 #define LCDPEN1_PEN15_MASK 128 /*** LCDPEN2 - LCD Pin Enable Register 2; 0xFFFF8708 ***/ typedef union { byte Byte; struct { byte PEN16 :1; /* Enable LCD pin 16 for LCD operation */ byte PEN17 :1; /* Enable LCD pin 17 for LCD operation */ byte PEN18 :1; /* Enable LCD pin 18 for LCD operation */ byte PEN19 :1; /* Enable LCD pin 19 for LCD operation */ byte PEN20 :1; /* Enable LCD pin 20 for LCD operation */ byte PEN21 :1; /* Enable LCD pin 21 for LCD operation */ byte PEN22 :1; /* Enable LCD pin 22 for LCD operation */ byte PEN23 :1; /* Enable LCD pin 23 for LCD operation */ } Bits; } LCDPEN2STR; extern volatile LCDPEN2STR _LCDPEN2 @0xFFFF8708; #define LCDPEN2 _LCDPEN2.Byte #define LCDPEN2_PEN16 _LCDPEN2.Bits.PEN16 #define LCDPEN2_PEN17 _LCDPEN2.Bits.PEN17 #define LCDPEN2_PEN18 _LCDPEN2.Bits.PEN18 #define LCDPEN2_PEN19 _LCDPEN2.Bits.PEN19 #define LCDPEN2_PEN20 _LCDPEN2.Bits.PEN20 #define LCDPEN2_PEN21 _LCDPEN2.Bits.PEN21 #define LCDPEN2_PEN22 _LCDPEN2.Bits.PEN22 #define LCDPEN2_PEN23 _LCDPEN2.Bits.PEN23 #define LCDPEN2_PEN16_MASK 1 #define LCDPEN2_PEN17_MASK 2 #define LCDPEN2_PEN18_MASK 4 #define LCDPEN2_PEN19_MASK 8 #define LCDPEN2_PEN20_MASK 16 #define LCDPEN2_PEN21_MASK 32 #define LCDPEN2_PEN22_MASK 64 #define LCDPEN2_PEN23_MASK 128 /*** LCDPEN3 - LCD Pin Enable Register 3; 0xFFFF8709 ***/ typedef union { byte Byte; struct { byte PEN24 :1; /* Enable LCD pin 24 for LCD operation */ byte PEN25 :1; /* Enable LCD pin 25 for LCD operation */ byte PEN26 :1; /* Enable LCD pin 26 for LCD operation */ byte PEN27 :1; /* Enable LCD pin 27 for LCD operation */ byte PEN28 :1; /* Enable LCD pin 28 for LCD operation */ byte PEN29 :1; /* Enable LCD pin 29 for LCD operation */ byte PEN30 :1; /* Enable LCD pin 30 for LCD operation */ byte PEN31 :1; /* Enable LCD pin 31 for LCD operation */ } Bits; } LCDPEN3STR; extern volatile LCDPEN3STR _LCDPEN3 @0xFFFF8709; #define LCDPEN3 _LCDPEN3.Byte #define LCDPEN3_PEN24 _LCDPEN3.Bits.PEN24 #define LCDPEN3_PEN25 _LCDPEN3.Bits.PEN25 #define LCDPEN3_PEN26 _LCDPEN3.Bits.PEN26 #define LCDPEN3_PEN27 _LCDPEN3.Bits.PEN27 #define LCDPEN3_PEN28 _LCDPEN3.Bits.PEN28 #define LCDPEN3_PEN29 _LCDPEN3.Bits.PEN29 #define LCDPEN3_PEN30 _LCDPEN3.Bits.PEN30 #define LCDPEN3_PEN31 _LCDPEN3.Bits.PEN31 #define LCDPEN3_PEN24_MASK 1 #define LCDPEN3_PEN25_MASK 2 #define LCDPEN3_PEN26_MASK 4 #define LCDPEN3_PEN27_MASK 8 #define LCDPEN3_PEN28_MASK 16 #define LCDPEN3_PEN29_MASK 32 #define LCDPEN3_PEN30_MASK 64 #define LCDPEN3_PEN31_MASK 128 /*** LCDPEN4 - LCD Pin Enable Register 4; 0xFFFF870A ***/ typedef union { byte Byte; struct { byte PEN32 :1; /* Enable LCD pin 32 for LCD operation */ byte PEN33 :1; /* Enable LCD pin 33 for LCD operation */ byte PEN34 :1; /* Enable LCD pin 34 for LCD operation */ byte PEN35 :1; /* Enable LCD pin 35 for LCD operation */ byte PEN36 :1; /* Enable LCD pin 36 for LCD operation */ byte PEN37 :1; /* Enable LCD pin 37 for LCD operation */ byte PEN38 :1; /* Enable LCD pin 38 for LCD operation */ byte PEN39 :1; /* Enable LCD pin 39 for LCD operation */ } Bits; } LCDPEN4STR; extern volatile LCDPEN4STR _LCDPEN4 @0xFFFF870A; #define LCDPEN4 _LCDPEN4.Byte #define LCDPEN4_PEN32 _LCDPEN4.Bits.PEN32 #define LCDPEN4_PEN33 _LCDPEN4.Bits.PEN33 #define LCDPEN4_PEN34 _LCDPEN4.Bits.PEN34 #define LCDPEN4_PEN35 _LCDPEN4.Bits.PEN35 #define LCDPEN4_PEN36 _LCDPEN4.Bits.PEN36 #define LCDPEN4_PEN37 _LCDPEN4.Bits.PEN37 #define LCDPEN4_PEN38 _LCDPEN4.Bits.PEN38 #define LCDPEN4_PEN39 _LCDPEN4.Bits.PEN39 #define LCDPEN4_PEN32_MASK 1 #define LCDPEN4_PEN33_MASK 2 #define LCDPEN4_PEN34_MASK 4 #define LCDPEN4_PEN35_MASK 8 #define LCDPEN4_PEN36_MASK 16 #define LCDPEN4_PEN37_MASK 32 #define LCDPEN4_PEN38_MASK 64 #define LCDPEN4_PEN39_MASK 128 /*** LCDPEN5 - LCD Pin Enable Register 5; 0xFFFF870B ***/ typedef union { byte Byte; struct { byte PEN40 :1; /* Enable LCD pin 40 for LCD operation */ byte PEN41 :1; /* Enable LCD pin 41 for LCD operation */ byte PEN42 :1; /* Enable LCD pin 42 for LCD operation */ byte PEN43 :1; /* Enable LCD pin 43 for LCD operation */ byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpPEN_40 :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } LCDPEN5STR; extern volatile LCDPEN5STR _LCDPEN5 @0xFFFF870B; #define LCDPEN5 _LCDPEN5.Byte #define LCDPEN5_PEN40 _LCDPEN5.Bits.PEN40 #define LCDPEN5_PEN41 _LCDPEN5.Bits.PEN41 #define LCDPEN5_PEN42 _LCDPEN5.Bits.PEN42 #define LCDPEN5_PEN43 _LCDPEN5.Bits.PEN43 #define LCDPEN5_PEN_40 _LCDPEN5.MergedBits.grpPEN_40 #define LCDPEN5_PEN LCDPEN5_PEN_40 #define LCDPEN5_PEN40_MASK 1 #define LCDPEN5_PEN41_MASK 2 #define LCDPEN5_PEN42_MASK 4 #define LCDPEN5_PEN43_MASK 8 #define LCDPEN5_PEN_40_MASK 15 #define LCDPEN5_PEN_40_BITNUM 0 /*** LCDBPEN0 - LCD Backplane Enable Register 0; 0xFFFF870E ***/ typedef union { byte Byte; struct { byte BPEN0 :1; /* Enable LCD pin 0 to operate as an LCD backplane or an LCD frontplane */ byte BPEN1 :1; /* Enable LCD pin 1 to operate as an LCD backplane or an LCD frontplane */ byte BPEN2 :1; /* Enable LCD pin 2 to operate as an LCD backplane or an LCD frontplane */ byte BPEN3 :1; /* Enable LCD pin 3 to operate as an LCD backplane or an LCD frontplane */ byte BPEN4 :1; /* Enable LCD pin 4 to operate as an LCD backplane or an LCD frontplane */ byte BPEN5 :1; /* Enable LCD pin 5 to operate as an LCD backplane or an LCD frontplane */ byte BPEN6 :1; /* Enable LCD pin 6 to operate as an LCD backplane or an LCD frontplane */ byte BPEN7 :1; /* Enable LCD pin 7 to operate as an LCD backplane or an LCD frontplane */ } Bits; } LCDBPEN0STR; extern volatile LCDBPEN0STR _LCDBPEN0 @0xFFFF870E; #define LCDBPEN0 _LCDBPEN0.Byte #define LCDBPEN0_BPEN0 _LCDBPEN0.Bits.BPEN0 #define LCDBPEN0_BPEN1 _LCDBPEN0.Bits.BPEN1 #define LCDBPEN0_BPEN2 _LCDBPEN0.Bits.BPEN2 #define LCDBPEN0_BPEN3 _LCDBPEN0.Bits.BPEN3 #define LCDBPEN0_BPEN4 _LCDBPEN0.Bits.BPEN4 #define LCDBPEN0_BPEN5 _LCDBPEN0.Bits.BPEN5 #define LCDBPEN0_BPEN6 _LCDBPEN0.Bits.BPEN6 #define LCDBPEN0_BPEN7 _LCDBPEN0.Bits.BPEN7 /* LCDBPEN_ARR: Access 6 LCDBPENx registers in an array */ #define LCDBPEN_ARR ((volatile byte *) &LCDBPEN0) #define LCDBPEN0_BPEN0_MASK 1 #define LCDBPEN0_BPEN1_MASK 2 #define LCDBPEN0_BPEN2_MASK 4 #define LCDBPEN0_BPEN3_MASK 8 #define LCDBPEN0_BPEN4_MASK 16 #define LCDBPEN0_BPEN5_MASK 32 #define LCDBPEN0_BPEN6_MASK 64 #define LCDBPEN0_BPEN7_MASK 128 /*** LCDBPEN1 - LCD Backplane Enable Register 1; 0xFFFF870F ***/ typedef union { byte Byte; struct { byte BPEN8 :1; /* Enable LCD pin 8 to operate as an LCD backplane or an LCD frontplane */ byte BPEN9 :1; /* Enable LCD pin 9 to operate as an LCD backplane or an LCD frontplane */ byte BPEN10 :1; /* Enable LCD pin 10 to operate as an LCD backplane or an LCD frontplane */ byte BPEN11 :1; /* Enable LCD pin 11 to operate as an LCD backplane or an LCD frontplane */ byte BPEN12 :1; /* Enable LCD pin 12 to operate as an LCD backplane or an LCD frontplane */ byte BPEN13 :1; /* Enable LCD pin 13 to operate as an LCD backplane or an LCD frontplane */ byte BPEN14 :1; /* Enable LCD pin 14 to operate as an LCD backplane or an LCD frontplane */ byte BPEN15 :1; /* Enable LCD pin 15 to operate as an LCD backplane or an LCD frontplane */ } Bits; } LCDBPEN1STR; extern volatile LCDBPEN1STR _LCDBPEN1 @0xFFFF870F; #define LCDBPEN1 _LCDBPEN1.Byte #define LCDBPEN1_BPEN8 _LCDBPEN1.Bits.BPEN8 #define LCDBPEN1_BPEN9 _LCDBPEN1.Bits.BPEN9 #define LCDBPEN1_BPEN10 _LCDBPEN1.Bits.BPEN10 #define LCDBPEN1_BPEN11 _LCDBPEN1.Bits.BPEN11 #define LCDBPEN1_BPEN12 _LCDBPEN1.Bits.BPEN12 #define LCDBPEN1_BPEN13 _LCDBPEN1.Bits.BPEN13 #define LCDBPEN1_BPEN14 _LCDBPEN1.Bits.BPEN14 #define LCDBPEN1_BPEN15 _LCDBPEN1.Bits.BPEN15 #define LCDBPEN1_BPEN8_MASK 1 #define LCDBPEN1_BPEN9_MASK 2 #define LCDBPEN1_BPEN10_MASK 4 #define LCDBPEN1_BPEN11_MASK 8 #define LCDBPEN1_BPEN12_MASK 16 #define LCDBPEN1_BPEN13_MASK 32 #define LCDBPEN1_BPEN14_MASK 64 #define LCDBPEN1_BPEN15_MASK 128 /*** LCDBPEN2 - LCD Backplane Enable Register 2; 0xFFFF8710 ***/ typedef union { byte Byte; struct { byte BPEN16 :1; /* Enable LCD pin 16 to operate as an LCD backplane or an LCD frontplane */ byte BPEN17 :1; /* Enable LCD pin 17 to operate as an LCD backplane or an LCD frontplane */ byte BPEN18 :1; /* Enable LCD pin 18 to operate as an LCD backplane or an LCD frontplane */ byte BPEN19 :1; /* Enable LCD pin 19 to operate as an LCD backplane or an LCD frontplane */ byte BPEN20 :1; /* Enable LCD pin 20 to operate as an LCD backplane or an LCD frontplane */ byte BPEN21 :1; /* Enable LCD pin 21 to operate as an LCD backplane or an LCD frontplane */ byte BPEN22 :1; /* Enable LCD pin 22 to operate as an LCD backplane or an LCD frontplane */ byte BPEN23 :1; /* Enable LCD pin 23 to operate as an LCD backplane or an LCD frontplane */ } Bits; } LCDBPEN2STR; extern volatile LCDBPEN2STR _LCDBPEN2 @0xFFFF8710; #define LCDBPEN2 _LCDBPEN2.Byte #define LCDBPEN2_BPEN16 _LCDBPEN2.Bits.BPEN16 #define LCDBPEN2_BPEN17 _LCDBPEN2.Bits.BPEN17 #define LCDBPEN2_BPEN18 _LCDBPEN2.Bits.BPEN18 #define LCDBPEN2_BPEN19 _LCDBPEN2.Bits.BPEN19 #define LCDBPEN2_BPEN20 _LCDBPEN2.Bits.BPEN20 #define LCDBPEN2_BPEN21 _LCDBPEN2.Bits.BPEN21 #define LCDBPEN2_BPEN22 _LCDBPEN2.Bits.BPEN22 #define LCDBPEN2_BPEN23 _LCDBPEN2.Bits.BPEN23 #define LCDBPEN2_BPEN16_MASK 1 #define LCDBPEN2_BPEN17_MASK 2 #define LCDBPEN2_BPEN18_MASK 4 #define LCDBPEN2_BPEN19_MASK 8 #define LCDBPEN2_BPEN20_MASK 16 #define LCDBPEN2_BPEN21_MASK 32 #define LCDBPEN2_BPEN22_MASK 64 #define LCDBPEN2_BPEN23_MASK 128 /*** LCDBPEN3 - LCD Backplane Enable Register 3; 0xFFFF8711 ***/ typedef union { byte Byte; struct { byte BPEN24 :1; /* Enable LCD pin 24 to operate as an LCD backplane or an LCD frontplane */ byte BPEN25 :1; /* Enable LCD pin 25 to operate as an LCD backplane or an LCD frontplane */ byte BPEN26 :1; /* Enable LCD pin 26 to operate as an LCD backplane or an LCD frontplane */ byte BPEN27 :1; /* Enable LCD pin 27 to operate as an LCD backplane or an LCD frontplane */ byte BPEN28 :1; /* Enable LCD pin 28 to operate as an LCD backplane or an LCD frontplane */ byte BPEN29 :1; /* Enable LCD pin 29 to operate as an LCD backplane or an LCD frontplane */ byte BPEN30 :1; /* Enable LCD pin 30 to operate as an LCD backplane or an LCD frontplane */ byte BPEN31 :1; /* Enable LCD pin 31 to operate as an LCD backplane or an LCD frontplane */ } Bits; } LCDBPEN3STR; extern volatile LCDBPEN3STR _LCDBPEN3 @0xFFFF8711; #define LCDBPEN3 _LCDBPEN3.Byte #define LCDBPEN3_BPEN24 _LCDBPEN3.Bits.BPEN24 #define LCDBPEN3_BPEN25 _LCDBPEN3.Bits.BPEN25 #define LCDBPEN3_BPEN26 _LCDBPEN3.Bits.BPEN26 #define LCDBPEN3_BPEN27 _LCDBPEN3.Bits.BPEN27 #define LCDBPEN3_BPEN28 _LCDBPEN3.Bits.BPEN28 #define LCDBPEN3_BPEN29 _LCDBPEN3.Bits.BPEN29 #define LCDBPEN3_BPEN30 _LCDBPEN3.Bits.BPEN30 #define LCDBPEN3_BPEN31 _LCDBPEN3.Bits.BPEN31 #define LCDBPEN3_BPEN24_MASK 1 #define LCDBPEN3_BPEN25_MASK 2 #define LCDBPEN3_BPEN26_MASK 4 #define LCDBPEN3_BPEN27_MASK 8 #define LCDBPEN3_BPEN28_MASK 16 #define LCDBPEN3_BPEN29_MASK 32 #define LCDBPEN3_BPEN30_MASK 64 #define LCDBPEN3_BPEN31_MASK 128 /*** LCDBPEN4 - LCD Backplane Enable Register 4; 0xFFFF8712 ***/ typedef union { byte Byte; struct { byte BPEN32 :1; /* Enable LCD pin 32 to operate as an LCD backplane or an LCD frontplane */ byte BPEN33 :1; /* Enable LCD pin 33 to operate as an LCD backplane or an LCD frontplane */ byte BPEN34 :1; /* Enable LCD pin 34 to operate as an LCD backplane or an LCD frontplane */ byte BPEN35 :1; /* Enable LCD pin 35 to operate as an LCD backplane or an LCD frontplane */ byte BPEN36 :1; /* Enable LCD pin 36 to operate as an LCD backplane or an LCD frontplane */ byte BPEN37 :1; /* Enable LCD pin 37 to operate as an LCD backplane or an LCD frontplane */ byte BPEN38 :1; /* Enable LCD pin 38 to operate as an LCD backplane or an LCD frontplane */ byte BPEN39 :1; /* Enable LCD pin 39 to operate as an LCD backplane or an LCD frontplane */ } Bits; } LCDBPEN4STR; extern volatile LCDBPEN4STR _LCDBPEN4 @0xFFFF8712; #define LCDBPEN4 _LCDBPEN4.Byte #define LCDBPEN4_BPEN32 _LCDBPEN4.Bits.BPEN32 #define LCDBPEN4_BPEN33 _LCDBPEN4.Bits.BPEN33 #define LCDBPEN4_BPEN34 _LCDBPEN4.Bits.BPEN34 #define LCDBPEN4_BPEN35 _LCDBPEN4.Bits.BPEN35 #define LCDBPEN4_BPEN36 _LCDBPEN4.Bits.BPEN36 #define LCDBPEN4_BPEN37 _LCDBPEN4.Bits.BPEN37 #define LCDBPEN4_BPEN38 _LCDBPEN4.Bits.BPEN38 #define LCDBPEN4_BPEN39 _LCDBPEN4.Bits.BPEN39 #define LCDBPEN4_BPEN32_MASK 1 #define LCDBPEN4_BPEN33_MASK 2 #define LCDBPEN4_BPEN34_MASK 4 #define LCDBPEN4_BPEN35_MASK 8 #define LCDBPEN4_BPEN36_MASK 16 #define LCDBPEN4_BPEN37_MASK 32 #define LCDBPEN4_BPEN38_MASK 64 #define LCDBPEN4_BPEN39_MASK 128 /*** LCDBPEN5 - LCD Backplane Enable Register 5; 0xFFFF8713 ***/ typedef union { byte Byte; struct { byte BPEN40 :1; /* Enable LCD pin 40 to operate as an LCD backplane or an LCD frontplane */ byte BPEN41 :1; /* Enable LCD pin 41 to operate as an LCD backplane or an LCD frontplane */ byte BPEN42 :1; /* Enable LCD pin 42 to operate as an LCD backplane or an LCD frontplane */ byte BPEN43 :1; /* Enable LCD pin 43 to operate as an LCD backplane or an LCD frontplane */ byte :1; byte :1; byte :1; byte :1; } Bits; struct { byte grpBPEN_40 :4; byte :1; byte :1; byte :1; byte :1; } MergedBits; } LCDBPEN5STR; extern volatile LCDBPEN5STR _LCDBPEN5 @0xFFFF8713; #define LCDBPEN5 _LCDBPEN5.Byte #define LCDBPEN5_BPEN40 _LCDBPEN5.Bits.BPEN40 #define LCDBPEN5_BPEN41 _LCDBPEN5.Bits.BPEN41 #define LCDBPEN5_BPEN42 _LCDBPEN5.Bits.BPEN42 #define LCDBPEN5_BPEN43 _LCDBPEN5.Bits.BPEN43 #define LCDBPEN5_BPEN_40 _LCDBPEN5.MergedBits.grpBPEN_40 #define LCDBPEN5_BPEN LCDBPEN5_BPEN_40 #define LCDBPEN5_BPEN40_MASK 1 #define LCDBPEN5_BPEN41_MASK 2 #define LCDBPEN5_BPEN42_MASK 4 #define LCDBPEN5_BPEN43_MASK 8 #define LCDBPEN5_BPEN_40_MASK 15 #define LCDBPEN5_BPEN_40_BITNUM 0 /*** LCDWF0 - LCD Waveform Register 0; 0xFFFF8716 ***/ typedef union { byte Byte; struct { byte BPALCD0 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD0 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD0 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD0 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD0 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD0 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD0 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD0 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF0STR; extern volatile LCDWF0STR _LCDWF0 @0xFFFF8716; #define LCDWF0 _LCDWF0.Byte #define LCDWF0_BPALCD0 _LCDWF0.Bits.BPALCD0 #define LCDWF0_BPBLCD0 _LCDWF0.Bits.BPBLCD0 #define LCDWF0_BPCLCD0 _LCDWF0.Bits.BPCLCD0 #define LCDWF0_BPDLCD0 _LCDWF0.Bits.BPDLCD0 #define LCDWF0_BPELCD0 _LCDWF0.Bits.BPELCD0 #define LCDWF0_BPFLCD0 _LCDWF0.Bits.BPFLCD0 #define LCDWF0_BPGLCD0 _LCDWF0.Bits.BPGLCD0 #define LCDWF0_BPHLCD0 _LCDWF0.Bits.BPHLCD0 /* LCDWF_ARR: Access 44 LCDWFx registers in an array */ #define LCDWF_ARR ((volatile byte *) &LCDWF0) #define LCDWF0_BPALCD0_MASK 1 #define LCDWF0_BPBLCD0_MASK 2 #define LCDWF0_BPCLCD0_MASK 4 #define LCDWF0_BPDLCD0_MASK 8 #define LCDWF0_BPELCD0_MASK 16 #define LCDWF0_BPFLCD0_MASK 32 #define LCDWF0_BPGLCD0_MASK 64 #define LCDWF0_BPHLCD0_MASK 128 /*** LCDWF1 - LCD Waveform Register 1; 0xFFFF8717 ***/ typedef union { byte Byte; struct { byte BPALCD1 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD1 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD1 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD1 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD1 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD1 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD1 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD1 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF1STR; extern volatile LCDWF1STR _LCDWF1 @0xFFFF8717; #define LCDWF1 _LCDWF1.Byte #define LCDWF1_BPALCD1 _LCDWF1.Bits.BPALCD1 #define LCDWF1_BPBLCD1 _LCDWF1.Bits.BPBLCD1 #define LCDWF1_BPCLCD1 _LCDWF1.Bits.BPCLCD1 #define LCDWF1_BPDLCD1 _LCDWF1.Bits.BPDLCD1 #define LCDWF1_BPELCD1 _LCDWF1.Bits.BPELCD1 #define LCDWF1_BPFLCD1 _LCDWF1.Bits.BPFLCD1 #define LCDWF1_BPGLCD1 _LCDWF1.Bits.BPGLCD1 #define LCDWF1_BPHLCD1 _LCDWF1.Bits.BPHLCD1 #define LCDWF1_BPALCD1_MASK 1 #define LCDWF1_BPBLCD1_MASK 2 #define LCDWF1_BPCLCD1_MASK 4 #define LCDWF1_BPDLCD1_MASK 8 #define LCDWF1_BPELCD1_MASK 16 #define LCDWF1_BPFLCD1_MASK 32 #define LCDWF1_BPGLCD1_MASK 64 #define LCDWF1_BPHLCD1_MASK 128 /*** LCDWF2 - LCD Waveform Register 2; 0xFFFF8718 ***/ typedef union { byte Byte; struct { byte BPALCD2 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD2 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD2 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD2 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD2 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD2 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD2 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD2 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF2STR; extern volatile LCDWF2STR _LCDWF2 @0xFFFF8718; #define LCDWF2 _LCDWF2.Byte #define LCDWF2_BPALCD2 _LCDWF2.Bits.BPALCD2 #define LCDWF2_BPBLCD2 _LCDWF2.Bits.BPBLCD2 #define LCDWF2_BPCLCD2 _LCDWF2.Bits.BPCLCD2 #define LCDWF2_BPDLCD2 _LCDWF2.Bits.BPDLCD2 #define LCDWF2_BPELCD2 _LCDWF2.Bits.BPELCD2 #define LCDWF2_BPFLCD2 _LCDWF2.Bits.BPFLCD2 #define LCDWF2_BPGLCD2 _LCDWF2.Bits.BPGLCD2 #define LCDWF2_BPHLCD2 _LCDWF2.Bits.BPHLCD2 #define LCDWF2_BPALCD2_MASK 1 #define LCDWF2_BPBLCD2_MASK 2 #define LCDWF2_BPCLCD2_MASK 4 #define LCDWF2_BPDLCD2_MASK 8 #define LCDWF2_BPELCD2_MASK 16 #define LCDWF2_BPFLCD2_MASK 32 #define LCDWF2_BPGLCD2_MASK 64 #define LCDWF2_BPHLCD2_MASK 128 /*** LCDWF3 - LCD Waveform Register 3; 0xFFFF8719 ***/ typedef union { byte Byte; struct { byte BPALCD3 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD3 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD3 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD3 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD3 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD3 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD3 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD3 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF3STR; extern volatile LCDWF3STR _LCDWF3 @0xFFFF8719; #define LCDWF3 _LCDWF3.Byte #define LCDWF3_BPALCD3 _LCDWF3.Bits.BPALCD3 #define LCDWF3_BPBLCD3 _LCDWF3.Bits.BPBLCD3 #define LCDWF3_BPCLCD3 _LCDWF3.Bits.BPCLCD3 #define LCDWF3_BPDLCD3 _LCDWF3.Bits.BPDLCD3 #define LCDWF3_BPELCD3 _LCDWF3.Bits.BPELCD3 #define LCDWF3_BPFLCD3 _LCDWF3.Bits.BPFLCD3 #define LCDWF3_BPGLCD3 _LCDWF3.Bits.BPGLCD3 #define LCDWF3_BPHLCD3 _LCDWF3.Bits.BPHLCD3 #define LCDWF3_BPALCD3_MASK 1 #define LCDWF3_BPBLCD3_MASK 2 #define LCDWF3_BPCLCD3_MASK 4 #define LCDWF3_BPDLCD3_MASK 8 #define LCDWF3_BPELCD3_MASK 16 #define LCDWF3_BPFLCD3_MASK 32 #define LCDWF3_BPGLCD3_MASK 64 #define LCDWF3_BPHLCD3_MASK 128 /*** LCDWF4 - LCD Waveform Register 4; 0xFFFF871A ***/ typedef union { byte Byte; struct { byte BPALCD4 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD4 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD4 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD4 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD4 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD4 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD4 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD4 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF4STR; extern volatile LCDWF4STR _LCDWF4 @0xFFFF871A; #define LCDWF4 _LCDWF4.Byte #define LCDWF4_BPALCD4 _LCDWF4.Bits.BPALCD4 #define LCDWF4_BPBLCD4 _LCDWF4.Bits.BPBLCD4 #define LCDWF4_BPCLCD4 _LCDWF4.Bits.BPCLCD4 #define LCDWF4_BPDLCD4 _LCDWF4.Bits.BPDLCD4 #define LCDWF4_BPELCD4 _LCDWF4.Bits.BPELCD4 #define LCDWF4_BPFLCD4 _LCDWF4.Bits.BPFLCD4 #define LCDWF4_BPGLCD4 _LCDWF4.Bits.BPGLCD4 #define LCDWF4_BPHLCD4 _LCDWF4.Bits.BPHLCD4 #define LCDWF4_BPALCD4_MASK 1 #define LCDWF4_BPBLCD4_MASK 2 #define LCDWF4_BPCLCD4_MASK 4 #define LCDWF4_BPDLCD4_MASK 8 #define LCDWF4_BPELCD4_MASK 16 #define LCDWF4_BPFLCD4_MASK 32 #define LCDWF4_BPGLCD4_MASK 64 #define LCDWF4_BPHLCD4_MASK 128 /*** LCDWF5 - LCD Waveform Register 5; 0xFFFF871B ***/ typedef union { byte Byte; struct { byte BPALCD5 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD5 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD5 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD5 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD5 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD5 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD5 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD5 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF5STR; extern volatile LCDWF5STR _LCDWF5 @0xFFFF871B; #define LCDWF5 _LCDWF5.Byte #define LCDWF5_BPALCD5 _LCDWF5.Bits.BPALCD5 #define LCDWF5_BPBLCD5 _LCDWF5.Bits.BPBLCD5 #define LCDWF5_BPCLCD5 _LCDWF5.Bits.BPCLCD5 #define LCDWF5_BPDLCD5 _LCDWF5.Bits.BPDLCD5 #define LCDWF5_BPELCD5 _LCDWF5.Bits.BPELCD5 #define LCDWF5_BPFLCD5 _LCDWF5.Bits.BPFLCD5 #define LCDWF5_BPGLCD5 _LCDWF5.Bits.BPGLCD5 #define LCDWF5_BPHLCD5 _LCDWF5.Bits.BPHLCD5 #define LCDWF5_BPALCD5_MASK 1 #define LCDWF5_BPBLCD5_MASK 2 #define LCDWF5_BPCLCD5_MASK 4 #define LCDWF5_BPDLCD5_MASK 8 #define LCDWF5_BPELCD5_MASK 16 #define LCDWF5_BPFLCD5_MASK 32 #define LCDWF5_BPGLCD5_MASK 64 #define LCDWF5_BPHLCD5_MASK 128 /*** LCDWF6 - LCD Waveform Register 6; 0xFFFF871C ***/ typedef union { byte Byte; struct { byte BPALCD6 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD6 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD6 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD6 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD6 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD6 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD6 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD6 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF6STR; extern volatile LCDWF6STR _LCDWF6 @0xFFFF871C; #define LCDWF6 _LCDWF6.Byte #define LCDWF6_BPALCD6 _LCDWF6.Bits.BPALCD6 #define LCDWF6_BPBLCD6 _LCDWF6.Bits.BPBLCD6 #define LCDWF6_BPCLCD6 _LCDWF6.Bits.BPCLCD6 #define LCDWF6_BPDLCD6 _LCDWF6.Bits.BPDLCD6 #define LCDWF6_BPELCD6 _LCDWF6.Bits.BPELCD6 #define LCDWF6_BPFLCD6 _LCDWF6.Bits.BPFLCD6 #define LCDWF6_BPGLCD6 _LCDWF6.Bits.BPGLCD6 #define LCDWF6_BPHLCD6 _LCDWF6.Bits.BPHLCD6 #define LCDWF6_BPALCD6_MASK 1 #define LCDWF6_BPBLCD6_MASK 2 #define LCDWF6_BPCLCD6_MASK 4 #define LCDWF6_BPDLCD6_MASK 8 #define LCDWF6_BPELCD6_MASK 16 #define LCDWF6_BPFLCD6_MASK 32 #define LCDWF6_BPGLCD6_MASK 64 #define LCDWF6_BPHLCD6_MASK 128 /*** LCDWF7 - LCD Waveform Register 7; 0xFFFF871D ***/ typedef union { byte Byte; struct { byte BPALCD7 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD7 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD7 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD7 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD7 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD7 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD7 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD7 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF7STR; extern volatile LCDWF7STR _LCDWF7 @0xFFFF871D; #define LCDWF7 _LCDWF7.Byte #define LCDWF7_BPALCD7 _LCDWF7.Bits.BPALCD7 #define LCDWF7_BPBLCD7 _LCDWF7.Bits.BPBLCD7 #define LCDWF7_BPCLCD7 _LCDWF7.Bits.BPCLCD7 #define LCDWF7_BPDLCD7 _LCDWF7.Bits.BPDLCD7 #define LCDWF7_BPELCD7 _LCDWF7.Bits.BPELCD7 #define LCDWF7_BPFLCD7 _LCDWF7.Bits.BPFLCD7 #define LCDWF7_BPGLCD7 _LCDWF7.Bits.BPGLCD7 #define LCDWF7_BPHLCD7 _LCDWF7.Bits.BPHLCD7 #define LCDWF7_BPALCD7_MASK 1 #define LCDWF7_BPBLCD7_MASK 2 #define LCDWF7_BPCLCD7_MASK 4 #define LCDWF7_BPDLCD7_MASK 8 #define LCDWF7_BPELCD7_MASK 16 #define LCDWF7_BPFLCD7_MASK 32 #define LCDWF7_BPGLCD7_MASK 64 #define LCDWF7_BPHLCD7_MASK 128 /*** LCDWF8 - LCD Waveform Register 8; 0xFFFF871E ***/ typedef union { byte Byte; struct { byte BPALCD8 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD8 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD8 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD8 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD8 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD8 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD8 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD8 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF8STR; extern volatile LCDWF8STR _LCDWF8 @0xFFFF871E; #define LCDWF8 _LCDWF8.Byte #define LCDWF8_BPALCD8 _LCDWF8.Bits.BPALCD8 #define LCDWF8_BPBLCD8 _LCDWF8.Bits.BPBLCD8 #define LCDWF8_BPCLCD8 _LCDWF8.Bits.BPCLCD8 #define LCDWF8_BPDLCD8 _LCDWF8.Bits.BPDLCD8 #define LCDWF8_BPELCD8 _LCDWF8.Bits.BPELCD8 #define LCDWF8_BPFLCD8 _LCDWF8.Bits.BPFLCD8 #define LCDWF8_BPGLCD8 _LCDWF8.Bits.BPGLCD8 #define LCDWF8_BPHLCD8 _LCDWF8.Bits.BPHLCD8 #define LCDWF8_BPALCD8_MASK 1 #define LCDWF8_BPBLCD8_MASK 2 #define LCDWF8_BPCLCD8_MASK 4 #define LCDWF8_BPDLCD8_MASK 8 #define LCDWF8_BPELCD8_MASK 16 #define LCDWF8_BPFLCD8_MASK 32 #define LCDWF8_BPGLCD8_MASK 64 #define LCDWF8_BPHLCD8_MASK 128 /*** LCDWF9 - LCD Waveform Register 9; 0xFFFF871F ***/ typedef union { byte Byte; struct { byte BPALCD9 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD9 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD9 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD9 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD9 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD9 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD9 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD9 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF9STR; extern volatile LCDWF9STR _LCDWF9 @0xFFFF871F; #define LCDWF9 _LCDWF9.Byte #define LCDWF9_BPALCD9 _LCDWF9.Bits.BPALCD9 #define LCDWF9_BPBLCD9 _LCDWF9.Bits.BPBLCD9 #define LCDWF9_BPCLCD9 _LCDWF9.Bits.BPCLCD9 #define LCDWF9_BPDLCD9 _LCDWF9.Bits.BPDLCD9 #define LCDWF9_BPELCD9 _LCDWF9.Bits.BPELCD9 #define LCDWF9_BPFLCD9 _LCDWF9.Bits.BPFLCD9 #define LCDWF9_BPGLCD9 _LCDWF9.Bits.BPGLCD9 #define LCDWF9_BPHLCD9 _LCDWF9.Bits.BPHLCD9 #define LCDWF9_BPALCD9_MASK 1 #define LCDWF9_BPBLCD9_MASK 2 #define LCDWF9_BPCLCD9_MASK 4 #define LCDWF9_BPDLCD9_MASK 8 #define LCDWF9_BPELCD9_MASK 16 #define LCDWF9_BPFLCD9_MASK 32 #define LCDWF9_BPGLCD9_MASK 64 #define LCDWF9_BPHLCD9_MASK 128 /*** LCDWF10 - LCD Waveform Register 10; 0xFFFF8720 ***/ typedef union { byte Byte; struct { byte BPALCD10 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD10 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD10 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD10 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD10 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD10 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD10 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD10 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF10STR; extern volatile LCDWF10STR _LCDWF10 @0xFFFF8720; #define LCDWF10 _LCDWF10.Byte #define LCDWF10_BPALCD10 _LCDWF10.Bits.BPALCD10 #define LCDWF10_BPBLCD10 _LCDWF10.Bits.BPBLCD10 #define LCDWF10_BPCLCD10 _LCDWF10.Bits.BPCLCD10 #define LCDWF10_BPDLCD10 _LCDWF10.Bits.BPDLCD10 #define LCDWF10_BPELCD10 _LCDWF10.Bits.BPELCD10 #define LCDWF10_BPFLCD10 _LCDWF10.Bits.BPFLCD10 #define LCDWF10_BPGLCD10 _LCDWF10.Bits.BPGLCD10 #define LCDWF10_BPHLCD10 _LCDWF10.Bits.BPHLCD10 #define LCDWF10_BPALCD10_MASK 1 #define LCDWF10_BPBLCD10_MASK 2 #define LCDWF10_BPCLCD10_MASK 4 #define LCDWF10_BPDLCD10_MASK 8 #define LCDWF10_BPELCD10_MASK 16 #define LCDWF10_BPFLCD10_MASK 32 #define LCDWF10_BPGLCD10_MASK 64 #define LCDWF10_BPHLCD10_MASK 128 /*** LCDWF11 - LCD Waveform Register 11; 0xFFFF8721 ***/ typedef union { byte Byte; struct { byte BPALCD11 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD11 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD11 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD11 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD11 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD11 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD11 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD11 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF11STR; extern volatile LCDWF11STR _LCDWF11 @0xFFFF8721; #define LCDWF11 _LCDWF11.Byte #define LCDWF11_BPALCD11 _LCDWF11.Bits.BPALCD11 #define LCDWF11_BPBLCD11 _LCDWF11.Bits.BPBLCD11 #define LCDWF11_BPCLCD11 _LCDWF11.Bits.BPCLCD11 #define LCDWF11_BPDLCD11 _LCDWF11.Bits.BPDLCD11 #define LCDWF11_BPELCD11 _LCDWF11.Bits.BPELCD11 #define LCDWF11_BPFLCD11 _LCDWF11.Bits.BPFLCD11 #define LCDWF11_BPGLCD11 _LCDWF11.Bits.BPGLCD11 #define LCDWF11_BPHLCD11 _LCDWF11.Bits.BPHLCD11 #define LCDWF11_BPALCD11_MASK 1 #define LCDWF11_BPBLCD11_MASK 2 #define LCDWF11_BPCLCD11_MASK 4 #define LCDWF11_BPDLCD11_MASK 8 #define LCDWF11_BPELCD11_MASK 16 #define LCDWF11_BPFLCD11_MASK 32 #define LCDWF11_BPGLCD11_MASK 64 #define LCDWF11_BPHLCD11_MASK 128 /*** LCDWF12 - LCD Waveform Register 12; 0xFFFF8722 ***/ typedef union { byte Byte; struct { byte BPALCD12 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD12 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD12 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD12 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD12 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD12 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD12 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD12 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF12STR; extern volatile LCDWF12STR _LCDWF12 @0xFFFF8722; #define LCDWF12 _LCDWF12.Byte #define LCDWF12_BPALCD12 _LCDWF12.Bits.BPALCD12 #define LCDWF12_BPBLCD12 _LCDWF12.Bits.BPBLCD12 #define LCDWF12_BPCLCD12 _LCDWF12.Bits.BPCLCD12 #define LCDWF12_BPDLCD12 _LCDWF12.Bits.BPDLCD12 #define LCDWF12_BPELCD12 _LCDWF12.Bits.BPELCD12 #define LCDWF12_BPFLCD12 _LCDWF12.Bits.BPFLCD12 #define LCDWF12_BPGLCD12 _LCDWF12.Bits.BPGLCD12 #define LCDWF12_BPHLCD12 _LCDWF12.Bits.BPHLCD12 #define LCDWF12_BPALCD12_MASK 1 #define LCDWF12_BPBLCD12_MASK 2 #define LCDWF12_BPCLCD12_MASK 4 #define LCDWF12_BPDLCD12_MASK 8 #define LCDWF12_BPELCD12_MASK 16 #define LCDWF12_BPFLCD12_MASK 32 #define LCDWF12_BPGLCD12_MASK 64 #define LCDWF12_BPHLCD12_MASK 128 /*** LCDWF13 - LCD Waveform Register 13; 0xFFFF8723 ***/ typedef union { byte Byte; struct { byte BPALCD13 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD13 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD13 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD13 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD13 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD13 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD13 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD13 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF13STR; extern volatile LCDWF13STR _LCDWF13 @0xFFFF8723; #define LCDWF13 _LCDWF13.Byte #define LCDWF13_BPALCD13 _LCDWF13.Bits.BPALCD13 #define LCDWF13_BPBLCD13 _LCDWF13.Bits.BPBLCD13 #define LCDWF13_BPCLCD13 _LCDWF13.Bits.BPCLCD13 #define LCDWF13_BPDLCD13 _LCDWF13.Bits.BPDLCD13 #define LCDWF13_BPELCD13 _LCDWF13.Bits.BPELCD13 #define LCDWF13_BPFLCD13 _LCDWF13.Bits.BPFLCD13 #define LCDWF13_BPGLCD13 _LCDWF13.Bits.BPGLCD13 #define LCDWF13_BPHLCD13 _LCDWF13.Bits.BPHLCD13 #define LCDWF13_BPALCD13_MASK 1 #define LCDWF13_BPBLCD13_MASK 2 #define LCDWF13_BPCLCD13_MASK 4 #define LCDWF13_BPDLCD13_MASK 8 #define LCDWF13_BPELCD13_MASK 16 #define LCDWF13_BPFLCD13_MASK 32 #define LCDWF13_BPGLCD13_MASK 64 #define LCDWF13_BPHLCD13_MASK 128 /*** LCDWF14 - LCD Waveform Register 14; 0xFFFF8724 ***/ typedef union { byte Byte; struct { byte BPALCD14 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD14 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD14 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD14 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD14 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD14 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD14 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD14 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF14STR; extern volatile LCDWF14STR _LCDWF14 @0xFFFF8724; #define LCDWF14 _LCDWF14.Byte #define LCDWF14_BPALCD14 _LCDWF14.Bits.BPALCD14 #define LCDWF14_BPBLCD14 _LCDWF14.Bits.BPBLCD14 #define LCDWF14_BPCLCD14 _LCDWF14.Bits.BPCLCD14 #define LCDWF14_BPDLCD14 _LCDWF14.Bits.BPDLCD14 #define LCDWF14_BPELCD14 _LCDWF14.Bits.BPELCD14 #define LCDWF14_BPFLCD14 _LCDWF14.Bits.BPFLCD14 #define LCDWF14_BPGLCD14 _LCDWF14.Bits.BPGLCD14 #define LCDWF14_BPHLCD14 _LCDWF14.Bits.BPHLCD14 #define LCDWF14_BPALCD14_MASK 1 #define LCDWF14_BPBLCD14_MASK 2 #define LCDWF14_BPCLCD14_MASK 4 #define LCDWF14_BPDLCD14_MASK 8 #define LCDWF14_BPELCD14_MASK 16 #define LCDWF14_BPFLCD14_MASK 32 #define LCDWF14_BPGLCD14_MASK 64 #define LCDWF14_BPHLCD14_MASK 128 /*** LCDWF15 - LCD Waveform Register 15; 0xFFFF8725 ***/ typedef union { byte Byte; struct { byte BPALCD15 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD15 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD15 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD15 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD15 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD15 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD15 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD15 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF15STR; extern volatile LCDWF15STR _LCDWF15 @0xFFFF8725; #define LCDWF15 _LCDWF15.Byte #define LCDWF15_BPALCD15 _LCDWF15.Bits.BPALCD15 #define LCDWF15_BPBLCD15 _LCDWF15.Bits.BPBLCD15 #define LCDWF15_BPCLCD15 _LCDWF15.Bits.BPCLCD15 #define LCDWF15_BPDLCD15 _LCDWF15.Bits.BPDLCD15 #define LCDWF15_BPELCD15 _LCDWF15.Bits.BPELCD15 #define LCDWF15_BPFLCD15 _LCDWF15.Bits.BPFLCD15 #define LCDWF15_BPGLCD15 _LCDWF15.Bits.BPGLCD15 #define LCDWF15_BPHLCD15 _LCDWF15.Bits.BPHLCD15 #define LCDWF15_BPALCD15_MASK 1 #define LCDWF15_BPBLCD15_MASK 2 #define LCDWF15_BPCLCD15_MASK 4 #define LCDWF15_BPDLCD15_MASK 8 #define LCDWF15_BPELCD15_MASK 16 #define LCDWF15_BPFLCD15_MASK 32 #define LCDWF15_BPGLCD15_MASK 64 #define LCDWF15_BPHLCD15_MASK 128 /*** LCDWF16 - LCD Waveform Register 16; 0xFFFF8726 ***/ typedef union { byte Byte; struct { byte BPALCD16 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD16 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD16 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD16 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD16 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD16 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD16 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD16 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF16STR; extern volatile LCDWF16STR _LCDWF16 @0xFFFF8726; #define LCDWF16 _LCDWF16.Byte #define LCDWF16_BPALCD16 _LCDWF16.Bits.BPALCD16 #define LCDWF16_BPBLCD16 _LCDWF16.Bits.BPBLCD16 #define LCDWF16_BPCLCD16 _LCDWF16.Bits.BPCLCD16 #define LCDWF16_BPDLCD16 _LCDWF16.Bits.BPDLCD16 #define LCDWF16_BPELCD16 _LCDWF16.Bits.BPELCD16 #define LCDWF16_BPFLCD16 _LCDWF16.Bits.BPFLCD16 #define LCDWF16_BPGLCD16 _LCDWF16.Bits.BPGLCD16 #define LCDWF16_BPHLCD16 _LCDWF16.Bits.BPHLCD16 #define LCDWF16_BPALCD16_MASK 1 #define LCDWF16_BPBLCD16_MASK 2 #define LCDWF16_BPCLCD16_MASK 4 #define LCDWF16_BPDLCD16_MASK 8 #define LCDWF16_BPELCD16_MASK 16 #define LCDWF16_BPFLCD16_MASK 32 #define LCDWF16_BPGLCD16_MASK 64 #define LCDWF16_BPHLCD16_MASK 128 /*** LCDWF17 - LCD Waveform Register 17; 0xFFFF8727 ***/ typedef union { byte Byte; struct { byte BPALCD17 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD17 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD17 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD17 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD17 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD17 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD17 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD17 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF17STR; extern volatile LCDWF17STR _LCDWF17 @0xFFFF8727; #define LCDWF17 _LCDWF17.Byte #define LCDWF17_BPALCD17 _LCDWF17.Bits.BPALCD17 #define LCDWF17_BPBLCD17 _LCDWF17.Bits.BPBLCD17 #define LCDWF17_BPCLCD17 _LCDWF17.Bits.BPCLCD17 #define LCDWF17_BPDLCD17 _LCDWF17.Bits.BPDLCD17 #define LCDWF17_BPELCD17 _LCDWF17.Bits.BPELCD17 #define LCDWF17_BPFLCD17 _LCDWF17.Bits.BPFLCD17 #define LCDWF17_BPGLCD17 _LCDWF17.Bits.BPGLCD17 #define LCDWF17_BPHLCD17 _LCDWF17.Bits.BPHLCD17 #define LCDWF17_BPALCD17_MASK 1 #define LCDWF17_BPBLCD17_MASK 2 #define LCDWF17_BPCLCD17_MASK 4 #define LCDWF17_BPDLCD17_MASK 8 #define LCDWF17_BPELCD17_MASK 16 #define LCDWF17_BPFLCD17_MASK 32 #define LCDWF17_BPGLCD17_MASK 64 #define LCDWF17_BPHLCD17_MASK 128 /*** LCDWF18 - LCD Waveform Register 18; 0xFFFF8728 ***/ typedef union { byte Byte; struct { byte BPALCD18 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD18 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD18 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD18 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD18 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD18 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD18 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD18 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF18STR; extern volatile LCDWF18STR _LCDWF18 @0xFFFF8728; #define LCDWF18 _LCDWF18.Byte #define LCDWF18_BPALCD18 _LCDWF18.Bits.BPALCD18 #define LCDWF18_BPBLCD18 _LCDWF18.Bits.BPBLCD18 #define LCDWF18_BPCLCD18 _LCDWF18.Bits.BPCLCD18 #define LCDWF18_BPDLCD18 _LCDWF18.Bits.BPDLCD18 #define LCDWF18_BPELCD18 _LCDWF18.Bits.BPELCD18 #define LCDWF18_BPFLCD18 _LCDWF18.Bits.BPFLCD18 #define LCDWF18_BPGLCD18 _LCDWF18.Bits.BPGLCD18 #define LCDWF18_BPHLCD18 _LCDWF18.Bits.BPHLCD18 #define LCDWF18_BPALCD18_MASK 1 #define LCDWF18_BPBLCD18_MASK 2 #define LCDWF18_BPCLCD18_MASK 4 #define LCDWF18_BPDLCD18_MASK 8 #define LCDWF18_BPELCD18_MASK 16 #define LCDWF18_BPFLCD18_MASK 32 #define LCDWF18_BPGLCD18_MASK 64 #define LCDWF18_BPHLCD18_MASK 128 /*** LCDWF19 - LCD Waveform Register 19; 0xFFFF8729 ***/ typedef union { byte Byte; struct { byte BPALCD19 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD19 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD19 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD19 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD19 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD19 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD19 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD19 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF19STR; extern volatile LCDWF19STR _LCDWF19 @0xFFFF8729; #define LCDWF19 _LCDWF19.Byte #define LCDWF19_BPALCD19 _LCDWF19.Bits.BPALCD19 #define LCDWF19_BPBLCD19 _LCDWF19.Bits.BPBLCD19 #define LCDWF19_BPCLCD19 _LCDWF19.Bits.BPCLCD19 #define LCDWF19_BPDLCD19 _LCDWF19.Bits.BPDLCD19 #define LCDWF19_BPELCD19 _LCDWF19.Bits.BPELCD19 #define LCDWF19_BPFLCD19 _LCDWF19.Bits.BPFLCD19 #define LCDWF19_BPGLCD19 _LCDWF19.Bits.BPGLCD19 #define LCDWF19_BPHLCD19 _LCDWF19.Bits.BPHLCD19 #define LCDWF19_BPALCD19_MASK 1 #define LCDWF19_BPBLCD19_MASK 2 #define LCDWF19_BPCLCD19_MASK 4 #define LCDWF19_BPDLCD19_MASK 8 #define LCDWF19_BPELCD19_MASK 16 #define LCDWF19_BPFLCD19_MASK 32 #define LCDWF19_BPGLCD19_MASK 64 #define LCDWF19_BPHLCD19_MASK 128 /*** LCDWF20 - LCD Waveform Register 20; 0xFFFF872A ***/ typedef union { byte Byte; struct { byte BPALCD20 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD20 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD20 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD20 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD20 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD20 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD20 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD20 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF20STR; extern volatile LCDWF20STR _LCDWF20 @0xFFFF872A; #define LCDWF20 _LCDWF20.Byte #define LCDWF20_BPALCD20 _LCDWF20.Bits.BPALCD20 #define LCDWF20_BPBLCD20 _LCDWF20.Bits.BPBLCD20 #define LCDWF20_BPCLCD20 _LCDWF20.Bits.BPCLCD20 #define LCDWF20_BPDLCD20 _LCDWF20.Bits.BPDLCD20 #define LCDWF20_BPELCD20 _LCDWF20.Bits.BPELCD20 #define LCDWF20_BPFLCD20 _LCDWF20.Bits.BPFLCD20 #define LCDWF20_BPGLCD20 _LCDWF20.Bits.BPGLCD20 #define LCDWF20_BPHLCD20 _LCDWF20.Bits.BPHLCD20 #define LCDWF20_BPALCD20_MASK 1 #define LCDWF20_BPBLCD20_MASK 2 #define LCDWF20_BPCLCD20_MASK 4 #define LCDWF20_BPDLCD20_MASK 8 #define LCDWF20_BPELCD20_MASK 16 #define LCDWF20_BPFLCD20_MASK 32 #define LCDWF20_BPGLCD20_MASK 64 #define LCDWF20_BPHLCD20_MASK 128 /*** LCDWF21 - LCD Waveform Register 21; 0xFFFF872B ***/ typedef union { byte Byte; struct { byte BPALCD21 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD21 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD21 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD21 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD21 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD21 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD21 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD21 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF21STR; extern volatile LCDWF21STR _LCDWF21 @0xFFFF872B; #define LCDWF21 _LCDWF21.Byte #define LCDWF21_BPALCD21 _LCDWF21.Bits.BPALCD21 #define LCDWF21_BPBLCD21 _LCDWF21.Bits.BPBLCD21 #define LCDWF21_BPCLCD21 _LCDWF21.Bits.BPCLCD21 #define LCDWF21_BPDLCD21 _LCDWF21.Bits.BPDLCD21 #define LCDWF21_BPELCD21 _LCDWF21.Bits.BPELCD21 #define LCDWF21_BPFLCD21 _LCDWF21.Bits.BPFLCD21 #define LCDWF21_BPGLCD21 _LCDWF21.Bits.BPGLCD21 #define LCDWF21_BPHLCD21 _LCDWF21.Bits.BPHLCD21 #define LCDWF21_BPALCD21_MASK 1 #define LCDWF21_BPBLCD21_MASK 2 #define LCDWF21_BPCLCD21_MASK 4 #define LCDWF21_BPDLCD21_MASK 8 #define LCDWF21_BPELCD21_MASK 16 #define LCDWF21_BPFLCD21_MASK 32 #define LCDWF21_BPGLCD21_MASK 64 #define LCDWF21_BPHLCD21_MASK 128 /*** LCDWF22 - LCD Waveform Register 22; 0xFFFF872C ***/ typedef union { byte Byte; struct { byte BPALCD22 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD22 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD22 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD22 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD22 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD22 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD22 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD22 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF22STR; extern volatile LCDWF22STR _LCDWF22 @0xFFFF872C; #define LCDWF22 _LCDWF22.Byte #define LCDWF22_BPALCD22 _LCDWF22.Bits.BPALCD22 #define LCDWF22_BPBLCD22 _LCDWF22.Bits.BPBLCD22 #define LCDWF22_BPCLCD22 _LCDWF22.Bits.BPCLCD22 #define LCDWF22_BPDLCD22 _LCDWF22.Bits.BPDLCD22 #define LCDWF22_BPELCD22 _LCDWF22.Bits.BPELCD22 #define LCDWF22_BPFLCD22 _LCDWF22.Bits.BPFLCD22 #define LCDWF22_BPGLCD22 _LCDWF22.Bits.BPGLCD22 #define LCDWF22_BPHLCD22 _LCDWF22.Bits.BPHLCD22 #define LCDWF22_BPALCD22_MASK 1 #define LCDWF22_BPBLCD22_MASK 2 #define LCDWF22_BPCLCD22_MASK 4 #define LCDWF22_BPDLCD22_MASK 8 #define LCDWF22_BPELCD22_MASK 16 #define LCDWF22_BPFLCD22_MASK 32 #define LCDWF22_BPGLCD22_MASK 64 #define LCDWF22_BPHLCD22_MASK 128 /*** LCDWF23 - LCD Waveform Register 23; 0xFFFF872D ***/ typedef union { byte Byte; struct { byte BPALCD23 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD23 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD23 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD23 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD23 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD23 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD23 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD23 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF23STR; extern volatile LCDWF23STR _LCDWF23 @0xFFFF872D; #define LCDWF23 _LCDWF23.Byte #define LCDWF23_BPALCD23 _LCDWF23.Bits.BPALCD23 #define LCDWF23_BPBLCD23 _LCDWF23.Bits.BPBLCD23 #define LCDWF23_BPCLCD23 _LCDWF23.Bits.BPCLCD23 #define LCDWF23_BPDLCD23 _LCDWF23.Bits.BPDLCD23 #define LCDWF23_BPELCD23 _LCDWF23.Bits.BPELCD23 #define LCDWF23_BPFLCD23 _LCDWF23.Bits.BPFLCD23 #define LCDWF23_BPGLCD23 _LCDWF23.Bits.BPGLCD23 #define LCDWF23_BPHLCD23 _LCDWF23.Bits.BPHLCD23 #define LCDWF23_BPALCD23_MASK 1 #define LCDWF23_BPBLCD23_MASK 2 #define LCDWF23_BPCLCD23_MASK 4 #define LCDWF23_BPDLCD23_MASK 8 #define LCDWF23_BPELCD23_MASK 16 #define LCDWF23_BPFLCD23_MASK 32 #define LCDWF23_BPGLCD23_MASK 64 #define LCDWF23_BPHLCD23_MASK 128 /*** LCDWF24 - LCD Waveform Register 24; 0xFFFF872E ***/ typedef union { byte Byte; struct { byte BPALCD24 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD24 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD24 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD24 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD24 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD24 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD24 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD24 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF24STR; extern volatile LCDWF24STR _LCDWF24 @0xFFFF872E; #define LCDWF24 _LCDWF24.Byte #define LCDWF24_BPALCD24 _LCDWF24.Bits.BPALCD24 #define LCDWF24_BPBLCD24 _LCDWF24.Bits.BPBLCD24 #define LCDWF24_BPCLCD24 _LCDWF24.Bits.BPCLCD24 #define LCDWF24_BPDLCD24 _LCDWF24.Bits.BPDLCD24 #define LCDWF24_BPELCD24 _LCDWF24.Bits.BPELCD24 #define LCDWF24_BPFLCD24 _LCDWF24.Bits.BPFLCD24 #define LCDWF24_BPGLCD24 _LCDWF24.Bits.BPGLCD24 #define LCDWF24_BPHLCD24 _LCDWF24.Bits.BPHLCD24 #define LCDWF24_BPALCD24_MASK 1 #define LCDWF24_BPBLCD24_MASK 2 #define LCDWF24_BPCLCD24_MASK 4 #define LCDWF24_BPDLCD24_MASK 8 #define LCDWF24_BPELCD24_MASK 16 #define LCDWF24_BPFLCD24_MASK 32 #define LCDWF24_BPGLCD24_MASK 64 #define LCDWF24_BPHLCD24_MASK 128 /*** LCDWF25 - LCD Waveform Register 25; 0xFFFF872F ***/ typedef union { byte Byte; struct { byte BPALCD25 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD25 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD25 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD25 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD25 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD25 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD25 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD25 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF25STR; extern volatile LCDWF25STR _LCDWF25 @0xFFFF872F; #define LCDWF25 _LCDWF25.Byte #define LCDWF25_BPALCD25 _LCDWF25.Bits.BPALCD25 #define LCDWF25_BPBLCD25 _LCDWF25.Bits.BPBLCD25 #define LCDWF25_BPCLCD25 _LCDWF25.Bits.BPCLCD25 #define LCDWF25_BPDLCD25 _LCDWF25.Bits.BPDLCD25 #define LCDWF25_BPELCD25 _LCDWF25.Bits.BPELCD25 #define LCDWF25_BPFLCD25 _LCDWF25.Bits.BPFLCD25 #define LCDWF25_BPGLCD25 _LCDWF25.Bits.BPGLCD25 #define LCDWF25_BPHLCD25 _LCDWF25.Bits.BPHLCD25 #define LCDWF25_BPALCD25_MASK 1 #define LCDWF25_BPBLCD25_MASK 2 #define LCDWF25_BPCLCD25_MASK 4 #define LCDWF25_BPDLCD25_MASK 8 #define LCDWF25_BPELCD25_MASK 16 #define LCDWF25_BPFLCD25_MASK 32 #define LCDWF25_BPGLCD25_MASK 64 #define LCDWF25_BPHLCD25_MASK 128 /*** LCDWF26 - LCD Waveform Register 26; 0xFFFF8730 ***/ typedef union { byte Byte; struct { byte BPALCD26 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD26 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD26 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD26 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD26 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD26 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD26 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD26 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF26STR; extern volatile LCDWF26STR _LCDWF26 @0xFFFF8730; #define LCDWF26 _LCDWF26.Byte #define LCDWF26_BPALCD26 _LCDWF26.Bits.BPALCD26 #define LCDWF26_BPBLCD26 _LCDWF26.Bits.BPBLCD26 #define LCDWF26_BPCLCD26 _LCDWF26.Bits.BPCLCD26 #define LCDWF26_BPDLCD26 _LCDWF26.Bits.BPDLCD26 #define LCDWF26_BPELCD26 _LCDWF26.Bits.BPELCD26 #define LCDWF26_BPFLCD26 _LCDWF26.Bits.BPFLCD26 #define LCDWF26_BPGLCD26 _LCDWF26.Bits.BPGLCD26 #define LCDWF26_BPHLCD26 _LCDWF26.Bits.BPHLCD26 #define LCDWF26_BPALCD26_MASK 1 #define LCDWF26_BPBLCD26_MASK 2 #define LCDWF26_BPCLCD26_MASK 4 #define LCDWF26_BPDLCD26_MASK 8 #define LCDWF26_BPELCD26_MASK 16 #define LCDWF26_BPFLCD26_MASK 32 #define LCDWF26_BPGLCD26_MASK 64 #define LCDWF26_BPHLCD26_MASK 128 /*** LCDWF27 - LCD Waveform Register 27; 0xFFFF8731 ***/ typedef union { byte Byte; struct { byte BPALCD27 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD27 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD27 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD27 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD27 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD27 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD27 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD27 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF27STR; extern volatile LCDWF27STR _LCDWF27 @0xFFFF8731; #define LCDWF27 _LCDWF27.Byte #define LCDWF27_BPALCD27 _LCDWF27.Bits.BPALCD27 #define LCDWF27_BPBLCD27 _LCDWF27.Bits.BPBLCD27 #define LCDWF27_BPCLCD27 _LCDWF27.Bits.BPCLCD27 #define LCDWF27_BPDLCD27 _LCDWF27.Bits.BPDLCD27 #define LCDWF27_BPELCD27 _LCDWF27.Bits.BPELCD27 #define LCDWF27_BPFLCD27 _LCDWF27.Bits.BPFLCD27 #define LCDWF27_BPGLCD27 _LCDWF27.Bits.BPGLCD27 #define LCDWF27_BPHLCD27 _LCDWF27.Bits.BPHLCD27 #define LCDWF27_BPALCD27_MASK 1 #define LCDWF27_BPBLCD27_MASK 2 #define LCDWF27_BPCLCD27_MASK 4 #define LCDWF27_BPDLCD27_MASK 8 #define LCDWF27_BPELCD27_MASK 16 #define LCDWF27_BPFLCD27_MASK 32 #define LCDWF27_BPGLCD27_MASK 64 #define LCDWF27_BPHLCD27_MASK 128 /*** LCDWF28 - LCD Waveform Register 28; 0xFFFF8732 ***/ typedef union { byte Byte; struct { byte BPALCD28 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD28 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD28 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD28 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD28 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD28 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD28 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD28 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF28STR; extern volatile LCDWF28STR _LCDWF28 @0xFFFF8732; #define LCDWF28 _LCDWF28.Byte #define LCDWF28_BPALCD28 _LCDWF28.Bits.BPALCD28 #define LCDWF28_BPBLCD28 _LCDWF28.Bits.BPBLCD28 #define LCDWF28_BPCLCD28 _LCDWF28.Bits.BPCLCD28 #define LCDWF28_BPDLCD28 _LCDWF28.Bits.BPDLCD28 #define LCDWF28_BPELCD28 _LCDWF28.Bits.BPELCD28 #define LCDWF28_BPFLCD28 _LCDWF28.Bits.BPFLCD28 #define LCDWF28_BPGLCD28 _LCDWF28.Bits.BPGLCD28 #define LCDWF28_BPHLCD28 _LCDWF28.Bits.BPHLCD28 #define LCDWF28_BPALCD28_MASK 1 #define LCDWF28_BPBLCD28_MASK 2 #define LCDWF28_BPCLCD28_MASK 4 #define LCDWF28_BPDLCD28_MASK 8 #define LCDWF28_BPELCD28_MASK 16 #define LCDWF28_BPFLCD28_MASK 32 #define LCDWF28_BPGLCD28_MASK 64 #define LCDWF28_BPHLCD28_MASK 128 /*** LCDWF29 - LCD Waveform Register 29; 0xFFFF8733 ***/ typedef union { byte Byte; struct { byte BPALCD29 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD29 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD29 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD29 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD29 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD29 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD29 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD29 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF29STR; extern volatile LCDWF29STR _LCDWF29 @0xFFFF8733; #define LCDWF29 _LCDWF29.Byte #define LCDWF29_BPALCD29 _LCDWF29.Bits.BPALCD29 #define LCDWF29_BPBLCD29 _LCDWF29.Bits.BPBLCD29 #define LCDWF29_BPCLCD29 _LCDWF29.Bits.BPCLCD29 #define LCDWF29_BPDLCD29 _LCDWF29.Bits.BPDLCD29 #define LCDWF29_BPELCD29 _LCDWF29.Bits.BPELCD29 #define LCDWF29_BPFLCD29 _LCDWF29.Bits.BPFLCD29 #define LCDWF29_BPGLCD29 _LCDWF29.Bits.BPGLCD29 #define LCDWF29_BPHLCD29 _LCDWF29.Bits.BPHLCD29 #define LCDWF29_BPALCD29_MASK 1 #define LCDWF29_BPBLCD29_MASK 2 #define LCDWF29_BPCLCD29_MASK 4 #define LCDWF29_BPDLCD29_MASK 8 #define LCDWF29_BPELCD29_MASK 16 #define LCDWF29_BPFLCD29_MASK 32 #define LCDWF29_BPGLCD29_MASK 64 #define LCDWF29_BPHLCD29_MASK 128 /*** LCDWF30 - LCD Waveform Register 30; 0xFFFF8734 ***/ typedef union { byte Byte; struct { byte BPALCD30 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD30 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD30 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD30 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD30 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD30 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD30 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD30 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF30STR; extern volatile LCDWF30STR _LCDWF30 @0xFFFF8734; #define LCDWF30 _LCDWF30.Byte #define LCDWF30_BPALCD30 _LCDWF30.Bits.BPALCD30 #define LCDWF30_BPBLCD30 _LCDWF30.Bits.BPBLCD30 #define LCDWF30_BPCLCD30 _LCDWF30.Bits.BPCLCD30 #define LCDWF30_BPDLCD30 _LCDWF30.Bits.BPDLCD30 #define LCDWF30_BPELCD30 _LCDWF30.Bits.BPELCD30 #define LCDWF30_BPFLCD30 _LCDWF30.Bits.BPFLCD30 #define LCDWF30_BPGLCD30 _LCDWF30.Bits.BPGLCD30 #define LCDWF30_BPHLCD30 _LCDWF30.Bits.BPHLCD30 #define LCDWF30_BPALCD30_MASK 1 #define LCDWF30_BPBLCD30_MASK 2 #define LCDWF30_BPCLCD30_MASK 4 #define LCDWF30_BPDLCD30_MASK 8 #define LCDWF30_BPELCD30_MASK 16 #define LCDWF30_BPFLCD30_MASK 32 #define LCDWF30_BPGLCD30_MASK 64 #define LCDWF30_BPHLCD30_MASK 128 /*** LCDWF31 - LCD Waveform Register 31; 0xFFFF8735 ***/ typedef union { byte Byte; struct { byte BPALCD31 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD31 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD31 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD31 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD31 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD31 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD31 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD31 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF31STR; extern volatile LCDWF31STR _LCDWF31 @0xFFFF8735; #define LCDWF31 _LCDWF31.Byte #define LCDWF31_BPALCD31 _LCDWF31.Bits.BPALCD31 #define LCDWF31_BPBLCD31 _LCDWF31.Bits.BPBLCD31 #define LCDWF31_BPCLCD31 _LCDWF31.Bits.BPCLCD31 #define LCDWF31_BPDLCD31 _LCDWF31.Bits.BPDLCD31 #define LCDWF31_BPELCD31 _LCDWF31.Bits.BPELCD31 #define LCDWF31_BPFLCD31 _LCDWF31.Bits.BPFLCD31 #define LCDWF31_BPGLCD31 _LCDWF31.Bits.BPGLCD31 #define LCDWF31_BPHLCD31 _LCDWF31.Bits.BPHLCD31 #define LCDWF31_BPALCD31_MASK 1 #define LCDWF31_BPBLCD31_MASK 2 #define LCDWF31_BPCLCD31_MASK 4 #define LCDWF31_BPDLCD31_MASK 8 #define LCDWF31_BPELCD31_MASK 16 #define LCDWF31_BPFLCD31_MASK 32 #define LCDWF31_BPGLCD31_MASK 64 #define LCDWF31_BPHLCD31_MASK 128 /*** LCDWF32 - LCD Waveform Register 32; 0xFFFF8736 ***/ typedef union { byte Byte; struct { byte BPALCD32 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD32 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD32 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD32 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD32 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD32 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD32 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD32 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF32STR; extern volatile LCDWF32STR _LCDWF32 @0xFFFF8736; #define LCDWF32 _LCDWF32.Byte #define LCDWF32_BPALCD32 _LCDWF32.Bits.BPALCD32 #define LCDWF32_BPBLCD32 _LCDWF32.Bits.BPBLCD32 #define LCDWF32_BPCLCD32 _LCDWF32.Bits.BPCLCD32 #define LCDWF32_BPDLCD32 _LCDWF32.Bits.BPDLCD32 #define LCDWF32_BPELCD32 _LCDWF32.Bits.BPELCD32 #define LCDWF32_BPFLCD32 _LCDWF32.Bits.BPFLCD32 #define LCDWF32_BPGLCD32 _LCDWF32.Bits.BPGLCD32 #define LCDWF32_BPHLCD32 _LCDWF32.Bits.BPHLCD32 #define LCDWF32_BPALCD32_MASK 1 #define LCDWF32_BPBLCD32_MASK 2 #define LCDWF32_BPCLCD32_MASK 4 #define LCDWF32_BPDLCD32_MASK 8 #define LCDWF32_BPELCD32_MASK 16 #define LCDWF32_BPFLCD32_MASK 32 #define LCDWF32_BPGLCD32_MASK 64 #define LCDWF32_BPHLCD32_MASK 128 /*** LCDWF33 - LCD Waveform Register 33; 0xFFFF8737 ***/ typedef union { byte Byte; struct { byte BPALCD33 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD33 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD33 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD33 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD33 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD33 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD33 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD33 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF33STR; extern volatile LCDWF33STR _LCDWF33 @0xFFFF8737; #define LCDWF33 _LCDWF33.Byte #define LCDWF33_BPALCD33 _LCDWF33.Bits.BPALCD33 #define LCDWF33_BPBLCD33 _LCDWF33.Bits.BPBLCD33 #define LCDWF33_BPCLCD33 _LCDWF33.Bits.BPCLCD33 #define LCDWF33_BPDLCD33 _LCDWF33.Bits.BPDLCD33 #define LCDWF33_BPELCD33 _LCDWF33.Bits.BPELCD33 #define LCDWF33_BPFLCD33 _LCDWF33.Bits.BPFLCD33 #define LCDWF33_BPGLCD33 _LCDWF33.Bits.BPGLCD33 #define LCDWF33_BPHLCD33 _LCDWF33.Bits.BPHLCD33 #define LCDWF33_BPALCD33_MASK 1 #define LCDWF33_BPBLCD33_MASK 2 #define LCDWF33_BPCLCD33_MASK 4 #define LCDWF33_BPDLCD33_MASK 8 #define LCDWF33_BPELCD33_MASK 16 #define LCDWF33_BPFLCD33_MASK 32 #define LCDWF33_BPGLCD33_MASK 64 #define LCDWF33_BPHLCD33_MASK 128 /*** LCDWF34 - LCD Waveform Register 34; 0xFFFF8738 ***/ typedef union { byte Byte; struct { byte BPALCD34 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD34 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD34 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD34 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD34 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD34 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD34 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD34 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF34STR; extern volatile LCDWF34STR _LCDWF34 @0xFFFF8738; #define LCDWF34 _LCDWF34.Byte #define LCDWF34_BPALCD34 _LCDWF34.Bits.BPALCD34 #define LCDWF34_BPBLCD34 _LCDWF34.Bits.BPBLCD34 #define LCDWF34_BPCLCD34 _LCDWF34.Bits.BPCLCD34 #define LCDWF34_BPDLCD34 _LCDWF34.Bits.BPDLCD34 #define LCDWF34_BPELCD34 _LCDWF34.Bits.BPELCD34 #define LCDWF34_BPFLCD34 _LCDWF34.Bits.BPFLCD34 #define LCDWF34_BPGLCD34 _LCDWF34.Bits.BPGLCD34 #define LCDWF34_BPHLCD34 _LCDWF34.Bits.BPHLCD34 #define LCDWF34_BPALCD34_MASK 1 #define LCDWF34_BPBLCD34_MASK 2 #define LCDWF34_BPCLCD34_MASK 4 #define LCDWF34_BPDLCD34_MASK 8 #define LCDWF34_BPELCD34_MASK 16 #define LCDWF34_BPFLCD34_MASK 32 #define LCDWF34_BPGLCD34_MASK 64 #define LCDWF34_BPHLCD34_MASK 128 /*** LCDWF35 - LCD Waveform Register 35; 0xFFFF8739 ***/ typedef union { byte Byte; struct { byte BPALCD35 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD35 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD35 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD35 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD35 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD35 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD35 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD35 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF35STR; extern volatile LCDWF35STR _LCDWF35 @0xFFFF8739; #define LCDWF35 _LCDWF35.Byte #define LCDWF35_BPALCD35 _LCDWF35.Bits.BPALCD35 #define LCDWF35_BPBLCD35 _LCDWF35.Bits.BPBLCD35 #define LCDWF35_BPCLCD35 _LCDWF35.Bits.BPCLCD35 #define LCDWF35_BPDLCD35 _LCDWF35.Bits.BPDLCD35 #define LCDWF35_BPELCD35 _LCDWF35.Bits.BPELCD35 #define LCDWF35_BPFLCD35 _LCDWF35.Bits.BPFLCD35 #define LCDWF35_BPGLCD35 _LCDWF35.Bits.BPGLCD35 #define LCDWF35_BPHLCD35 _LCDWF35.Bits.BPHLCD35 #define LCDWF35_BPALCD35_MASK 1 #define LCDWF35_BPBLCD35_MASK 2 #define LCDWF35_BPCLCD35_MASK 4 #define LCDWF35_BPDLCD35_MASK 8 #define LCDWF35_BPELCD35_MASK 16 #define LCDWF35_BPFLCD35_MASK 32 #define LCDWF35_BPGLCD35_MASK 64 #define LCDWF35_BPHLCD35_MASK 128 /*** LCDWF36 - LCD Waveform Register 36; 0xFFFF873A ***/ typedef union { byte Byte; struct { byte BPALCD36 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD36 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD36 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD36 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD36 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD36 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD36 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD36 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF36STR; extern volatile LCDWF36STR _LCDWF36 @0xFFFF873A; #define LCDWF36 _LCDWF36.Byte #define LCDWF36_BPALCD36 _LCDWF36.Bits.BPALCD36 #define LCDWF36_BPBLCD36 _LCDWF36.Bits.BPBLCD36 #define LCDWF36_BPCLCD36 _LCDWF36.Bits.BPCLCD36 #define LCDWF36_BPDLCD36 _LCDWF36.Bits.BPDLCD36 #define LCDWF36_BPELCD36 _LCDWF36.Bits.BPELCD36 #define LCDWF36_BPFLCD36 _LCDWF36.Bits.BPFLCD36 #define LCDWF36_BPGLCD36 _LCDWF36.Bits.BPGLCD36 #define LCDWF36_BPHLCD36 _LCDWF36.Bits.BPHLCD36 #define LCDWF36_BPALCD36_MASK 1 #define LCDWF36_BPBLCD36_MASK 2 #define LCDWF36_BPCLCD36_MASK 4 #define LCDWF36_BPDLCD36_MASK 8 #define LCDWF36_BPELCD36_MASK 16 #define LCDWF36_BPFLCD36_MASK 32 #define LCDWF36_BPGLCD36_MASK 64 #define LCDWF36_BPHLCD36_MASK 128 /*** LCDWF37 - LCD Waveform Register 37; 0xFFFF873B ***/ typedef union { byte Byte; struct { byte BPALCD37 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD37 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD37 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD37 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD37 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD37 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD37 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD37 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF37STR; extern volatile LCDWF37STR _LCDWF37 @0xFFFF873B; #define LCDWF37 _LCDWF37.Byte #define LCDWF37_BPALCD37 _LCDWF37.Bits.BPALCD37 #define LCDWF37_BPBLCD37 _LCDWF37.Bits.BPBLCD37 #define LCDWF37_BPCLCD37 _LCDWF37.Bits.BPCLCD37 #define LCDWF37_BPDLCD37 _LCDWF37.Bits.BPDLCD37 #define LCDWF37_BPELCD37 _LCDWF37.Bits.BPELCD37 #define LCDWF37_BPFLCD37 _LCDWF37.Bits.BPFLCD37 #define LCDWF37_BPGLCD37 _LCDWF37.Bits.BPGLCD37 #define LCDWF37_BPHLCD37 _LCDWF37.Bits.BPHLCD37 #define LCDWF37_BPALCD37_MASK 1 #define LCDWF37_BPBLCD37_MASK 2 #define LCDWF37_BPCLCD37_MASK 4 #define LCDWF37_BPDLCD37_MASK 8 #define LCDWF37_BPELCD37_MASK 16 #define LCDWF37_BPFLCD37_MASK 32 #define LCDWF37_BPGLCD37_MASK 64 #define LCDWF37_BPHLCD37_MASK 128 /*** LCDWF38 - LCD Waveform Register 38; 0xFFFF873C ***/ typedef union { byte Byte; struct { byte BPALCD38 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD38 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD38 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD38 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD38 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD38 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD38 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD38 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF38STR; extern volatile LCDWF38STR _LCDWF38 @0xFFFF873C; #define LCDWF38 _LCDWF38.Byte #define LCDWF38_BPALCD38 _LCDWF38.Bits.BPALCD38 #define LCDWF38_BPBLCD38 _LCDWF38.Bits.BPBLCD38 #define LCDWF38_BPCLCD38 _LCDWF38.Bits.BPCLCD38 #define LCDWF38_BPDLCD38 _LCDWF38.Bits.BPDLCD38 #define LCDWF38_BPELCD38 _LCDWF38.Bits.BPELCD38 #define LCDWF38_BPFLCD38 _LCDWF38.Bits.BPFLCD38 #define LCDWF38_BPGLCD38 _LCDWF38.Bits.BPGLCD38 #define LCDWF38_BPHLCD38 _LCDWF38.Bits.BPHLCD38 #define LCDWF38_BPALCD38_MASK 1 #define LCDWF38_BPBLCD38_MASK 2 #define LCDWF38_BPCLCD38_MASK 4 #define LCDWF38_BPDLCD38_MASK 8 #define LCDWF38_BPELCD38_MASK 16 #define LCDWF38_BPFLCD38_MASK 32 #define LCDWF38_BPGLCD38_MASK 64 #define LCDWF38_BPHLCD38_MASK 128 /*** LCDWF39 - LCD Waveform Register 39; 0xFFFF873D ***/ typedef union { byte Byte; struct { byte BPALCD39 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD39 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD39 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD39 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD39 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD39 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD39 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD39 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF39STR; extern volatile LCDWF39STR _LCDWF39 @0xFFFF873D; #define LCDWF39 _LCDWF39.Byte #define LCDWF39_BPALCD39 _LCDWF39.Bits.BPALCD39 #define LCDWF39_BPBLCD39 _LCDWF39.Bits.BPBLCD39 #define LCDWF39_BPCLCD39 _LCDWF39.Bits.BPCLCD39 #define LCDWF39_BPDLCD39 _LCDWF39.Bits.BPDLCD39 #define LCDWF39_BPELCD39 _LCDWF39.Bits.BPELCD39 #define LCDWF39_BPFLCD39 _LCDWF39.Bits.BPFLCD39 #define LCDWF39_BPGLCD39 _LCDWF39.Bits.BPGLCD39 #define LCDWF39_BPHLCD39 _LCDWF39.Bits.BPHLCD39 #define LCDWF39_BPALCD39_MASK 1 #define LCDWF39_BPBLCD39_MASK 2 #define LCDWF39_BPCLCD39_MASK 4 #define LCDWF39_BPDLCD39_MASK 8 #define LCDWF39_BPELCD39_MASK 16 #define LCDWF39_BPFLCD39_MASK 32 #define LCDWF39_BPGLCD39_MASK 64 #define LCDWF39_BPHLCD39_MASK 128 /*** LCDWF40 - LCD Waveform Register 40; 0xFFFF873E ***/ typedef union { byte Byte; struct { byte BPALCD40 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD40 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD40 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD40 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD40 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD40 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD40 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD40 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF40STR; extern volatile LCDWF40STR _LCDWF40 @0xFFFF873E; #define LCDWF40 _LCDWF40.Byte #define LCDWF40_BPALCD40 _LCDWF40.Bits.BPALCD40 #define LCDWF40_BPBLCD40 _LCDWF40.Bits.BPBLCD40 #define LCDWF40_BPCLCD40 _LCDWF40.Bits.BPCLCD40 #define LCDWF40_BPDLCD40 _LCDWF40.Bits.BPDLCD40 #define LCDWF40_BPELCD40 _LCDWF40.Bits.BPELCD40 #define LCDWF40_BPFLCD40 _LCDWF40.Bits.BPFLCD40 #define LCDWF40_BPGLCD40 _LCDWF40.Bits.BPGLCD40 #define LCDWF40_BPHLCD40 _LCDWF40.Bits.BPHLCD40 #define LCDWF40_BPALCD40_MASK 1 #define LCDWF40_BPBLCD40_MASK 2 #define LCDWF40_BPCLCD40_MASK 4 #define LCDWF40_BPDLCD40_MASK 8 #define LCDWF40_BPELCD40_MASK 16 #define LCDWF40_BPFLCD40_MASK 32 #define LCDWF40_BPGLCD40_MASK 64 #define LCDWF40_BPHLCD40_MASK 128 /*** LCDWF41 - LCD Waveform Register 41; 0xFFFF873F ***/ typedef union { byte Byte; struct { byte BPALCD41 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD41 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD41 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD41 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD41 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD41 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD41 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD41 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF41STR; extern volatile LCDWF41STR _LCDWF41 @0xFFFF873F; #define LCDWF41 _LCDWF41.Byte #define LCDWF41_BPALCD41 _LCDWF41.Bits.BPALCD41 #define LCDWF41_BPBLCD41 _LCDWF41.Bits.BPBLCD41 #define LCDWF41_BPCLCD41 _LCDWF41.Bits.BPCLCD41 #define LCDWF41_BPDLCD41 _LCDWF41.Bits.BPDLCD41 #define LCDWF41_BPELCD41 _LCDWF41.Bits.BPELCD41 #define LCDWF41_BPFLCD41 _LCDWF41.Bits.BPFLCD41 #define LCDWF41_BPGLCD41 _LCDWF41.Bits.BPGLCD41 #define LCDWF41_BPHLCD41 _LCDWF41.Bits.BPHLCD41 #define LCDWF41_BPALCD41_MASK 1 #define LCDWF41_BPBLCD41_MASK 2 #define LCDWF41_BPCLCD41_MASK 4 #define LCDWF41_BPDLCD41_MASK 8 #define LCDWF41_BPELCD41_MASK 16 #define LCDWF41_BPFLCD41_MASK 32 #define LCDWF41_BPGLCD41_MASK 64 #define LCDWF41_BPHLCD41_MASK 128 /*** LCDWF42 - LCD Waveform Register 42; 0xFFFF8740 ***/ typedef union { byte Byte; struct { byte BPALCD42 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD42 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD42 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD42 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD42 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD42 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD42 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD42 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF42STR; extern volatile LCDWF42STR _LCDWF42 @0xFFFF8740; #define LCDWF42 _LCDWF42.Byte #define LCDWF42_BPALCD42 _LCDWF42.Bits.BPALCD42 #define LCDWF42_BPBLCD42 _LCDWF42.Bits.BPBLCD42 #define LCDWF42_BPCLCD42 _LCDWF42.Bits.BPCLCD42 #define LCDWF42_BPDLCD42 _LCDWF42.Bits.BPDLCD42 #define LCDWF42_BPELCD42 _LCDWF42.Bits.BPELCD42 #define LCDWF42_BPFLCD42 _LCDWF42.Bits.BPFLCD42 #define LCDWF42_BPGLCD42 _LCDWF42.Bits.BPGLCD42 #define LCDWF42_BPHLCD42 _LCDWF42.Bits.BPHLCD42 #define LCDWF42_BPALCD42_MASK 1 #define LCDWF42_BPBLCD42_MASK 2 #define LCDWF42_BPCLCD42_MASK 4 #define LCDWF42_BPDLCD42_MASK 8 #define LCDWF42_BPELCD42_MASK 16 #define LCDWF42_BPFLCD42_MASK 32 #define LCDWF42_BPGLCD42_MASK 64 #define LCDWF42_BPHLCD42_MASK 128 /*** LCDWF43 - LCD Waveform Register 43; 0xFFFF8741 ***/ typedef union { byte Byte; struct { byte BPALCD43 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPBLCD43 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPCLCD43 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPDLCD43 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPELCD43 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPFLCD43 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPGLCD43 :1; /* Segment on/off Frontplane/Backplane Operation */ byte BPHLCD43 :1; /* Segment on/off Frontplane/Backplane Operation */ } Bits; } LCDWF43STR; extern volatile LCDWF43STR _LCDWF43 @0xFFFF8741; #define LCDWF43 _LCDWF43.Byte #define LCDWF43_BPALCD43 _LCDWF43.Bits.BPALCD43 #define LCDWF43_BPBLCD43 _LCDWF43.Bits.BPBLCD43 #define LCDWF43_BPCLCD43 _LCDWF43.Bits.BPCLCD43 #define LCDWF43_BPDLCD43 _LCDWF43.Bits.BPDLCD43 #define LCDWF43_BPELCD43 _LCDWF43.Bits.BPELCD43 #define LCDWF43_BPFLCD43 _LCDWF43.Bits.BPFLCD43 #define LCDWF43_BPGLCD43 _LCDWF43.Bits.BPGLCD43 #define LCDWF43_BPHLCD43 _LCDWF43.Bits.BPHLCD43 #define LCDWF43_BPALCD43_MASK 1 #define LCDWF43_BPBLCD43_MASK 2 #define LCDWF43_BPCLCD43_MASK 4 #define LCDWF43_BPDLCD43_MASK 8 #define LCDWF43_BPELCD43_MASK 16 #define LCDWF43_BPFLCD43_MASK 32 #define LCDWF43_BPGLCD43_MASK 64 #define LCDWF43_BPHLCD43_MASK 128 /*** F1CDIV - FLASH Clock Divider Register; 0xFFFF8780 ***/ typedef union { byte Byte; struct { byte FDIV0 :1; /* Divisor for FLASH Clock Divider, bit 0 */ byte FDIV1 :1; /* Divisor for FLASH Clock Divider, bit 1 */ byte FDIV2 :1; /* Divisor for FLASH Clock Divider, bit 2 */ byte FDIV3 :1; /* Divisor for FLASH Clock Divider, bit 3 */ byte FDIV4 :1; /* Divisor for FLASH Clock Divider, bit 4 */ byte FDIV5 :1; /* Divisor for FLASH Clock Divider, bit 5 */ byte PRDIV8 :1; /* Prescale (Divide) FLASH Clock by 8 */ byte FDIVLD :1; /* Divisor Loaded Status Flag */ } Bits; struct { byte grpFDIV :6; byte grpPRDIV_8 :1; byte :1; } MergedBits; } F1CDIVSTR; extern volatile F1CDIVSTR _F1CDIV @0xFFFF8780; #define F1CDIV _F1CDIV.Byte #define F1CDIV_FDIV0 _F1CDIV.Bits.FDIV0 #define F1CDIV_FDIV1 _F1CDIV.Bits.FDIV1 #define F1CDIV_FDIV2 _F1CDIV.Bits.FDIV2 #define F1CDIV_FDIV3 _F1CDIV.Bits.FDIV3 #define F1CDIV_FDIV4 _F1CDIV.Bits.FDIV4 #define F1CDIV_FDIV5 _F1CDIV.Bits.FDIV5 #define F1CDIV_PRDIV8 _F1CDIV.Bits.PRDIV8 #define F1CDIV_FDIVLD _F1CDIV.Bits.FDIVLD #define F1CDIV_FDIV _F1CDIV.MergedBits.grpFDIV #define F1CDIV_FDIV0_MASK 1 #define F1CDIV_FDIV1_MASK 2 #define F1CDIV_FDIV2_MASK 4 #define F1CDIV_FDIV3_MASK 8 #define F1CDIV_FDIV4_MASK 16 #define F1CDIV_FDIV5_MASK 32 #define F1CDIV_PRDIV8_MASK 64 #define F1CDIV_FDIVLD_MASK 128 #define F1CDIV_FDIV_MASK 63 #define F1CDIV_FDIV_BITNUM 0 /*** F1OPT - Flash Options Register; 0xFFFF8781 ***/ typedef union { byte Byte; struct { byte SEC0 :1; /* Flash Security Bit 0 */ byte SEC1 :1; /* Flash Security Bit 1 */ byte :1; byte :1; byte :1; byte :1; byte KEYEN0 :1; /* Backdoor Key Security Enable Bit 0 */ byte KEYEN1 :1; /* Backdoor Key Security Enable Bit 1 */ } Bits; struct { byte grpSEC :2; byte :1; byte :1; byte :1; byte :1; byte grpKEYEN :2; } MergedBits; } F1OPTSTR; extern volatile F1OPTSTR _F1OPT @0xFFFF8781; #define F1OPT _F1OPT.Byte #define F1OPT_SEC0 _F1OPT.Bits.SEC0 #define F1OPT_SEC1 _F1OPT.Bits.SEC1 #define F1OPT_KEYEN0 _F1OPT.Bits.KEYEN0 #define F1OPT_KEYEN1 _F1OPT.Bits.KEYEN1 #define F1OPT_SEC _F1OPT.MergedBits.grpSEC #define F1OPT_KEYEN _F1OPT.MergedBits.grpKEYEN #define F1OPT_SEC0_MASK 1 #define F1OPT_SEC1_MASK 2 #define F1OPT_KEYEN0_MASK 64 #define F1OPT_KEYEN1_MASK 128 #define F1OPT_SEC_MASK 3 #define F1OPT_SEC_BITNUM 0 #define F1OPT_KEYEN_MASK 192 #define F1OPT_KEYEN_BITNUM 6 /*** F1CNFG - Flash Configuration Register; 0xFFFF8783 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte KEYACC :1; /* Enable Security Key Writing */ byte CCIE :1; /* Command Complete Interrupt Enable */ byte CBEIE :1; /* Command Buffer Empty Interrupt Enable */ } Bits; } F1CNFGSTR; extern volatile F1CNFGSTR _F1CNFG @0xFFFF8783; #define F1CNFG _F1CNFG.Byte #define F1CNFG_KEYACC _F1CNFG.Bits.KEYACC #define F1CNFG_CCIE _F1CNFG.Bits.CCIE #define F1CNFG_CBEIE _F1CNFG.Bits.CBEIE #define F1CNFG_KEYACC_MASK 32 #define F1CNFG_CCIE_MASK 64 #define F1CNFG_CBEIE_MASK 128 /*** F1PROT - Flash Protection Register; 0xFFFF8784 ***/ typedef union { byte Byte; struct { byte FPOPEN :1; /* Flash Protection Open */ byte FPS0 :1; /* Flash Protection Size, bit 0 */ byte FPS1 :1; /* Flash Protection Size, bit 1 */ byte FPS2 :1; /* Flash Protection Size, bit 2 */ byte FPS3 :1; /* Flash Protection Size, bit 3 */ byte FPS4 :1; /* Flash Protection Size, bit 4 */ byte FPS5 :1; /* Flash Protection Size, bit 5 */ byte FPS6 :1; /* Flash Protection Size, bit 6 */ } Bits; struct { byte :1; byte grpFPS :7; } MergedBits; } F1PROTSTR; extern volatile F1PROTSTR _F1PROT @0xFFFF8784; #define F1PROT _F1PROT.Byte #define F1PROT_FPOPEN _F1PROT.Bits.FPOPEN #define F1PROT_FPS0 _F1PROT.Bits.FPS0 #define F1PROT_FPS1 _F1PROT.Bits.FPS1 #define F1PROT_FPS2 _F1PROT.Bits.FPS2 #define F1PROT_FPS3 _F1PROT.Bits.FPS3 #define F1PROT_FPS4 _F1PROT.Bits.FPS4 #define F1PROT_FPS5 _F1PROT.Bits.FPS5 #define F1PROT_FPS6 _F1PROT.Bits.FPS6 #define F1PROT_FPS _F1PROT.MergedBits.grpFPS #define F1PROT_FPOPEN_MASK 1 #define F1PROT_FPS0_MASK 2 #define F1PROT_FPS1_MASK 4 #define F1PROT_FPS2_MASK 8 #define F1PROT_FPS3_MASK 16 #define F1PROT_FPS4_MASK 32 #define F1PROT_FPS5_MASK 64 #define F1PROT_FPS6_MASK 128 #define F1PROT_FPS_MASK 254 #define F1PROT_FPS_BITNUM 1 /*** F1STAT - Flash Status Register; 0xFFFF8785 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte FBLANK :1; /* FLASH Flag Indicating the Erase Verify Operation Status */ byte :1; byte FACCERR :1; /* FLASH Access Error Flag */ byte FPVIOL :1; /* FLASH Protection Violation Flag */ byte FCCF :1; /* FLASH Command Complete Interrupt Flag */ byte FCBEF :1; /* FLASH Command Buffer Empty Flag */ } Bits; } F1STATSTR; extern volatile F1STATSTR _F1STAT @0xFFFF8785; #define F1STAT _F1STAT.Byte #define F1STAT_FBLANK _F1STAT.Bits.FBLANK #define F1STAT_FACCERR _F1STAT.Bits.FACCERR #define F1STAT_FPVIOL _F1STAT.Bits.FPVIOL #define F1STAT_FCCF _F1STAT.Bits.FCCF #define F1STAT_FCBEF _F1STAT.Bits.FCBEF #define F1STAT_FBLANK_MASK 4 #define F1STAT_FACCERR_MASK 16 #define F1STAT_FPVIOL_MASK 32 #define F1STAT_FCCF_MASK 64 #define F1STAT_FCBEF_MASK 128 /*** F1CMD - Flash Command Register; 0xFFFF8786 ***/ typedef union { byte Byte; struct { byte FCMD0 :1; /* Flash Command, bit 0 */ byte FCMD1 :1; /* Flash Command, bit 1 */ byte FCMD2 :1; /* Flash Command, bit 2 */ byte FCMD3 :1; /* Flash Command, bit 3 */ byte FCMD4 :1; /* Flash Command, bit 4 */ byte FCMD5 :1; /* Flash Command, bit 5 */ byte FCMD6 :1; /* Flash Command, bit 6 */ byte :1; } Bits; struct { byte grpFCMD :7; byte :1; } MergedBits; } F1CMDSTR; extern volatile F1CMDSTR _F1CMD @0xFFFF8786; #define F1CMD _F1CMD.Byte #define F1CMD_FCMD0 _F1CMD.Bits.FCMD0 #define F1CMD_FCMD1 _F1CMD.Bits.FCMD1 #define F1CMD_FCMD2 _F1CMD.Bits.FCMD2 #define F1CMD_FCMD3 _F1CMD.Bits.FCMD3 #define F1CMD_FCMD4 _F1CMD.Bits.FCMD4 #define F1CMD_FCMD5 _F1CMD.Bits.FCMD5 #define F1CMD_FCMD6 _F1CMD.Bits.FCMD6 #define F1CMD_FCMD _F1CMD.MergedBits.grpFCMD #define F1CMD_FCMD0_MASK 1 #define F1CMD_FCMD1_MASK 2 #define F1CMD_FCMD2_MASK 4 #define F1CMD_FCMD3_MASK 8 #define F1CMD_FCMD4_MASK 16 #define F1CMD_FCMD5_MASK 32 #define F1CMD_FCMD6_MASK 64 #define F1CMD_FCMD_MASK 127 #define F1CMD_FCMD_BITNUM 0 /*** F2CDIV - FLASH Clock Divider Register; 0xFFFF87A0 ***/ typedef union { byte Byte; struct { byte FDIV0 :1; /* Divisor for FLASH Clock Divider, bit 0 */ byte FDIV1 :1; /* Divisor for FLASH Clock Divider, bit 1 */ byte FDIV2 :1; /* Divisor for FLASH Clock Divider, bit 2 */ byte FDIV3 :1; /* Divisor for FLASH Clock Divider, bit 3 */ byte FDIV4 :1; /* Divisor for FLASH Clock Divider, bit 4 */ byte FDIV5 :1; /* Divisor for FLASH Clock Divider, bit 5 */ byte PRDIV8 :1; /* Prescale (Divide) FLASH Clock by 8 */ byte FDIVLD :1; /* Divisor Loaded Status Flag */ } Bits; struct { byte grpFDIV :6; byte grpPRDIV_8 :1; byte :1; } MergedBits; } F2CDIVSTR; extern volatile F2CDIVSTR _F2CDIV @0xFFFF87A0; #define F2CDIV _F2CDIV.Byte #define F2CDIV_FDIV0 _F2CDIV.Bits.FDIV0 #define F2CDIV_FDIV1 _F2CDIV.Bits.FDIV1 #define F2CDIV_FDIV2 _F2CDIV.Bits.FDIV2 #define F2CDIV_FDIV3 _F2CDIV.Bits.FDIV3 #define F2CDIV_FDIV4 _F2CDIV.Bits.FDIV4 #define F2CDIV_FDIV5 _F2CDIV.Bits.FDIV5 #define F2CDIV_PRDIV8 _F2CDIV.Bits.PRDIV8 #define F2CDIV_FDIVLD _F2CDIV.Bits.FDIVLD #define F2CDIV_FDIV _F2CDIV.MergedBits.grpFDIV #define F2CDIV_FDIV0_MASK 1 #define F2CDIV_FDIV1_MASK 2 #define F2CDIV_FDIV2_MASK 4 #define F2CDIV_FDIV3_MASK 8 #define F2CDIV_FDIV4_MASK 16 #define F2CDIV_FDIV5_MASK 32 #define F2CDIV_PRDIV8_MASK 64 #define F2CDIV_FDIVLD_MASK 128 #define F2CDIV_FDIV_MASK 63 #define F2CDIV_FDIV_BITNUM 0 /*** F2OPT - Flash Options Register; 0xFFFF87A1 ***/ typedef union { byte Byte; struct { byte SEC0 :1; /* Flash Security Bit 0 */ byte SEC1 :1; /* Flash Security Bit 1 */ byte :1; byte :1; byte :1; byte :1; byte KEYEN0 :1; /* Backdoor Key Security Enable Bit 0 */ byte KEYEN1 :1; /* Backdoor Key Security Enable Bit 1 */ } Bits; struct { byte grpSEC :2; byte :1; byte :1; byte :1; byte :1; byte grpKEYEN :2; } MergedBits; } F2OPTSTR; extern volatile F2OPTSTR _F2OPT @0xFFFF87A1; #define F2OPT _F2OPT.Byte #define F2OPT_SEC0 _F2OPT.Bits.SEC0 #define F2OPT_SEC1 _F2OPT.Bits.SEC1 #define F2OPT_KEYEN0 _F2OPT.Bits.KEYEN0 #define F2OPT_KEYEN1 _F2OPT.Bits.KEYEN1 #define F2OPT_SEC _F2OPT.MergedBits.grpSEC #define F2OPT_KEYEN _F2OPT.MergedBits.grpKEYEN #define F2OPT_SEC0_MASK 1 #define F2OPT_SEC1_MASK 2 #define F2OPT_KEYEN0_MASK 64 #define F2OPT_KEYEN1_MASK 128 #define F2OPT_SEC_MASK 3 #define F2OPT_SEC_BITNUM 0 #define F2OPT_KEYEN_MASK 192 #define F2OPT_KEYEN_BITNUM 6 /*** F2CNFG - Flash Configuration Register; 0xFFFF87A3 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte :1; byte :1; byte :1; byte KEYACC :1; /* Enable Security Key Writing */ byte CCIE :1; /* Command Complete Interrupt Enable */ byte CBEIE :1; /* Command Buffer Empty Interrupt Enable */ } Bits; } F2CNFGSTR; extern volatile F2CNFGSTR _F2CNFG @0xFFFF87A3; #define F2CNFG _F2CNFG.Byte #define F2CNFG_KEYACC _F2CNFG.Bits.KEYACC #define F2CNFG_CCIE _F2CNFG.Bits.CCIE #define F2CNFG_CBEIE _F2CNFG.Bits.CBEIE #define F2CNFG_KEYACC_MASK 32 #define F2CNFG_CCIE_MASK 64 #define F2CNFG_CBEIE_MASK 128 /*** F2PROT - Flash Protection Register; 0xFFFF87A4 ***/ typedef union { byte Byte; struct { byte FPOPEN :1; /* Flash Protection Open */ byte FPS0 :1; /* Flash Protection Size, bit 0 */ byte FPS1 :1; /* Flash Protection Size, bit 1 */ byte FPS2 :1; /* Flash Protection Size, bit 2 */ byte FPS3 :1; /* Flash Protection Size, bit 3 */ byte FPS4 :1; /* Flash Protection Size, bit 4 */ byte FPS5 :1; /* Flash Protection Size, bit 5 */ byte FPS6 :1; /* Flash Protection Size, bit 6 */ } Bits; struct { byte :1; byte grpFPS :7; } MergedBits; } F2PROTSTR; extern volatile F2PROTSTR _F2PROT @0xFFFF87A4; #define F2PROT _F2PROT.Byte #define F2PROT_FPOPEN _F2PROT.Bits.FPOPEN #define F2PROT_FPS0 _F2PROT.Bits.FPS0 #define F2PROT_FPS1 _F2PROT.Bits.FPS1 #define F2PROT_FPS2 _F2PROT.Bits.FPS2 #define F2PROT_FPS3 _F2PROT.Bits.FPS3 #define F2PROT_FPS4 _F2PROT.Bits.FPS4 #define F2PROT_FPS5 _F2PROT.Bits.FPS5 #define F2PROT_FPS6 _F2PROT.Bits.FPS6 #define F2PROT_FPS _F2PROT.MergedBits.grpFPS #define F2PROT_FPOPEN_MASK 1 #define F2PROT_FPS0_MASK 2 #define F2PROT_FPS1_MASK 4 #define F2PROT_FPS2_MASK 8 #define F2PROT_FPS3_MASK 16 #define F2PROT_FPS4_MASK 32 #define F2PROT_FPS5_MASK 64 #define F2PROT_FPS6_MASK 128 #define F2PROT_FPS_MASK 254 #define F2PROT_FPS_BITNUM 1 /*** F2STAT - Flash Status Register; 0xFFFF87A5 ***/ typedef union { byte Byte; struct { byte :1; byte :1; byte FBLANK :1; /* FLASH Flag Indicating the Erase Verify Operation Status */ byte :1; byte FACCERR :1; /* FLASH Access Error Flag */ byte FPVIOL :1; /* FLASH Protection Violation Flag */ byte FCCF :1; /* FLASH Command Complete Interrupt Flag */ byte FCBEF :1; /* FLASH Command Buffer Empty Flag */ } Bits; } F2STATSTR; extern volatile F2STATSTR _F2STAT @0xFFFF87A5; #define F2STAT _F2STAT.Byte #define F2STAT_FBLANK _F2STAT.Bits.FBLANK #define F2STAT_FACCERR _F2STAT.Bits.FACCERR #define F2STAT_FPVIOL _F2STAT.Bits.FPVIOL #define F2STAT_FCCF _F2STAT.Bits.FCCF #define F2STAT_FCBEF _F2STAT.Bits.FCBEF #define F2STAT_FBLANK_MASK 4 #define F2STAT_FACCERR_MASK 16 #define F2STAT_FPVIOL_MASK 32 #define F2STAT_FCCF_MASK 64 #define F2STAT_FCBEF_MASK 128 /*** F2CMD - Flash Command Register; 0xFFFF87A6 ***/ typedef union { byte Byte; struct { byte FCMD0 :1; /* Flash Command, bit 0 */ byte FCMD1 :1; /* Flash Command, bit 1 */ byte FCMD2 :1; /* Flash Command, bit 2 */ byte FCMD3 :1; /* Flash Command, bit 3 */ byte FCMD4 :1; /* Flash Command, bit 4 */ byte FCMD5 :1; /* Flash Command, bit 5 */ byte FCMD6 :1; /* Flash Command, bit 6 */ byte :1; } Bits; struct { byte grpFCMD :7; byte :1; } MergedBits; } F2CMDSTR; extern volatile F2CMDSTR _F2CMD @0xFFFF87A6; #define F2CMD _F2CMD.Byte #define F2CMD_FCMD0 _F2CMD.Bits.FCMD0 #define F2CMD_FCMD1 _F2CMD.Bits.FCMD1 #define F2CMD_FCMD2 _F2CMD.Bits.FCMD2 #define F2CMD_FCMD3 _F2CMD.Bits.FCMD3 #define F2CMD_FCMD4 _F2CMD.Bits.FCMD4 #define F2CMD_FCMD5 _F2CMD.Bits.FCMD5 #define F2CMD_FCMD6 _F2CMD.Bits.FCMD6 #define F2CMD_FCMD _F2CMD.MergedBits.grpFCMD #define F2CMD_FCMD0_MASK 1 #define F2CMD_FCMD1_MASK 2 #define F2CMD_FCMD2_MASK 4 #define F2CMD_FCMD3_MASK 8 #define F2CMD_FCMD4_MASK 16 #define F2CMD_FCMD5_MASK 32 #define F2CMD_FCMD6_MASK 64 #define F2CMD_FCMD_MASK 127 #define F2CMD_FCMD_BITNUM 0 /*** PDBSC - PDB Status and Control Register; 0xFFFFE000 ***/ typedef union { word Word; struct { word EN :1; /* Module Enable */ word IE :1; /* Interrupt Enable */ word TRIGSEL0 :1; /* Input Trigger Select, bit 0 */ word TRIGSEL1 :1; /* Input Trigger Select, bit 1 */ word TRIGSEL2 :1; /* Input Trigger Select, bit 2 */ word SWTRIG :1; /* Software Trigger */ word CONT :1; /* Continuous Mode Enable */ word IF :1; /* Interrupt Flag */ word :1; word :1; word :1; word :1; word :1; word PRESCALER0 :1; /* Clock Prescaler Select, bit 0 */ word PRESCALER1 :1; /* Clock Prescaler Select, bit 1 */ word PRESCALER2 :1; /* Clock Prescaler Select, bit 2 */ } Bits; struct { word :1; word :1; word grpTRIGSEL :3; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word grpPRESCALER :3; } MergedBits; } PDBSCSTR; extern volatile PDBSCSTR _PDBSC @0xFFFFE000; #define PDBSC _PDBSC.Word #define PDBSC_EN _PDBSC.Bits.EN #define PDBSC_IE _PDBSC.Bits.IE #define PDBSC_TRIGSEL0 _PDBSC.Bits.TRIGSEL0 #define PDBSC_TRIGSEL1 _PDBSC.Bits.TRIGSEL1 #define PDBSC_TRIGSEL2 _PDBSC.Bits.TRIGSEL2 #define PDBSC_SWTRIG _PDBSC.Bits.SWTRIG #define PDBSC_CONT _PDBSC.Bits.CONT #define PDBSC_IF _PDBSC.Bits.IF #define PDBSC_PRESCALER0 _PDBSC.Bits.PRESCALER0 #define PDBSC_PRESCALER1 _PDBSC.Bits.PRESCALER1 #define PDBSC_PRESCALER2 _PDBSC.Bits.PRESCALER2 #define PDBSC_TRIGSEL _PDBSC.MergedBits.grpTRIGSEL #define PDBSC_PRESCALER _PDBSC.MergedBits.grpPRESCALER #define PDBSC_EN_MASK 1 #define PDBSC_IE_MASK 2 #define PDBSC_TRIGSEL0_MASK 4 #define PDBSC_TRIGSEL1_MASK 8 #define PDBSC_TRIGSEL2_MASK 16 #define PDBSC_SWTRIG_MASK 32 #define PDBSC_CONT_MASK 64 #define PDBSC_IF_MASK 128 #define PDBSC_PRESCALER0_MASK 8192 #define PDBSC_PRESCALER1_MASK 16384 #define PDBSC_PRESCALER2_MASK 32768 #define PDBSC_TRIGSEL_MASK 28 #define PDBSC_TRIGSEL_BITNUM 2 #define PDBSC_PRESCALER_MASK 57344 #define PDBSC_PRESCALER_BITNUM 13 /*** PDBMOD - PDB Counter Modulus Register; 0xFFFFE002 ***/ typedef union { word Word; } PDBMODSTR; extern volatile PDBMODSTR _PDBMOD @0xFFFFE002; #define PDBMOD _PDBMOD.Word /*** PDBCNT - PDB Counter Value Register; 0xFFFFE004 ***/ typedef union { word Word; } PDBCNTSTR; extern volatile PDBCNTSTR _PDBCNT @0xFFFFE004; #define PDBCNT _PDBCNT.Word /*** PDBIDLY - PDB Interrupt Delay Register; 0xFFFFE006 ***/ typedef union { word Word; struct { word IDELAY0 :1; /* Interrupt Delay, bit 0 */ word IDELAY1 :1; /* Interrupt Delay, bit 1 */ word IDELAY2 :1; /* Interrupt Delay, bit 2 */ word IDELAY3 :1; /* Interrupt Delay, bit 3 */ word IDELAY4 :1; /* Interrupt Delay, bit 4 */ word IDELAY5 :1; /* Interrupt Delay, bit 5 */ word IDELAY6 :1; /* Interrupt Delay, bit 6 */ word IDELAY7 :1; /* Interrupt Delay, bit 7 */ word IDELAY8 :1; /* Interrupt Delay, bit 8 */ word IDELAY9 :1; /* Interrupt Delay, bit 9 */ word IDELAY10 :1; /* Interrupt Delay, bit 10 */ word IDELAY11 :1; /* Interrupt Delay, bit 11 */ word IDELAY12 :1; /* Interrupt Delay, bit 12 */ word IDELAY13 :1; /* Interrupt Delay, bit 13 */ word IDELAY14 :1; /* Interrupt Delay, bit 14 */ word IDELAY15 :1; /* Interrupt Delay, bit 15 */ } Bits; } PDBIDLYSTR; extern volatile PDBIDLYSTR _PDBIDLY @0xFFFFE006; #define PDBIDLY _PDBIDLY.Word #define PDBIDLY_IDELAY0 _PDBIDLY.Bits.IDELAY0 #define PDBIDLY_IDELAY1 _PDBIDLY.Bits.IDELAY1 #define PDBIDLY_IDELAY2 _PDBIDLY.Bits.IDELAY2 #define PDBIDLY_IDELAY3 _PDBIDLY.Bits.IDELAY3 #define PDBIDLY_IDELAY4 _PDBIDLY.Bits.IDELAY4 #define PDBIDLY_IDELAY5 _PDBIDLY.Bits.IDELAY5 #define PDBIDLY_IDELAY6 _PDBIDLY.Bits.IDELAY6 #define PDBIDLY_IDELAY7 _PDBIDLY.Bits.IDELAY7 #define PDBIDLY_IDELAY8 _PDBIDLY.Bits.IDELAY8 #define PDBIDLY_IDELAY9 _PDBIDLY.Bits.IDELAY9 #define PDBIDLY_IDELAY10 _PDBIDLY.Bits.IDELAY10 #define PDBIDLY_IDELAY11 _PDBIDLY.Bits.IDELAY11 #define PDBIDLY_IDELAY12 _PDBIDLY.Bits.IDELAY12 #define PDBIDLY_IDELAY13 _PDBIDLY.Bits.IDELAY13 #define PDBIDLY_IDELAY14 _PDBIDLY.Bits.IDELAY14 #define PDBIDLY_IDELAY15 _PDBIDLY.Bits.IDELAY15 #define PDBIDLY_IDELAY0_MASK 1 #define PDBIDLY_IDELAY1_MASK 2 #define PDBIDLY_IDELAY2_MASK 4 #define PDBIDLY_IDELAY3_MASK 8 #define PDBIDLY_IDELAY4_MASK 16 #define PDBIDLY_IDELAY5_MASK 32 #define PDBIDLY_IDELAY6_MASK 64 #define PDBIDLY_IDELAY7_MASK 128 #define PDBIDLY_IDELAY8_MASK 256 #define PDBIDLY_IDELAY9_MASK 512 #define PDBIDLY_IDELAY10_MASK 1024 #define PDBIDLY_IDELAY11_MASK 2048 #define PDBIDLY_IDELAY12_MASK 4096 #define PDBIDLY_IDELAY13_MASK 8192 #define PDBIDLY_IDELAY14_MASK 16384 #define PDBIDLY_IDELAY15_MASK 32768 /*** PDBCH1CR - PDB Channel 1 Control Register; 0xFFFFE008 ***/ typedef union { word Word; struct { word ENB :1; /* Trigger B Enable */ word ENA :1; /* Trigger A Enable */ word BOS0 :1; /* Channel 1 Trigger B Output Select, bit 0 */ word BOS1 :1; /* Channel 1 Trigger B Output Select, bit 1 */ word AOS0 :1; /* Channel 1 Trigger A Output Select, bit 0 */ word AOS1 :1; /* Channel 1 Trigger A Output Select, bit 1 */ word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word ERRB :1; /* Sequence error on TriggerB */ word ERRA :1; /* Sequence error on TriggerA */ } Bits; struct { word :1; word grpENx :1; word grpBOS :2; word grpAOS :2; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word grpERRx :1; } MergedBits; } PDBCH1CRSTR; extern volatile PDBCH1CRSTR _PDBCH1CR @0xFFFFE008; #define PDBCH1CR _PDBCH1CR.Word #define PDBCH1CR_ENB _PDBCH1CR.Bits.ENB #define PDBCH1CR_ENA _PDBCH1CR.Bits.ENA #define PDBCH1CR_BOS0 _PDBCH1CR.Bits.BOS0 #define PDBCH1CR_BOS1 _PDBCH1CR.Bits.BOS1 #define PDBCH1CR_AOS0 _PDBCH1CR.Bits.AOS0 #define PDBCH1CR_AOS1 _PDBCH1CR.Bits.AOS1 #define PDBCH1CR_ERRB _PDBCH1CR.Bits.ERRB #define PDBCH1CR_ERRA _PDBCH1CR.Bits.ERRA #define PDBCH1CR_BOS _PDBCH1CR.MergedBits.grpBOS #define PDBCH1CR_AOS _PDBCH1CR.MergedBits.grpAOS #define PDBCH1CR_ENB_MASK 1 #define PDBCH1CR_ENA_MASK 2 #define PDBCH1CR_BOS0_MASK 4 #define PDBCH1CR_BOS1_MASK 8 #define PDBCH1CR_AOS0_MASK 16 #define PDBCH1CR_AOS1_MASK 32 #define PDBCH1CR_ERRB_MASK 16384 #define PDBCH1CR_ERRA_MASK 32768 #define PDBCH1CR_BOS_MASK 12 #define PDBCH1CR_BOS_BITNUM 2 #define PDBCH1CR_AOS_MASK 48 #define PDBCH1CR_AOS_BITNUM 4 /*** PDBCH1DLYA - PDB Channel 1 Delay A Register; 0xFFFFE00A ***/ typedef union { word Word; struct { word DELAYA0 :1; /* Delay A, bit 0 */ word DELAYA1 :1; /* Delay A, bit 1 */ word DELAYA2 :1; /* Delay A, bit 2 */ word DELAYA3 :1; /* Delay A, bit 3 */ word DELAYA4 :1; /* Delay A, bit 4 */ word DELAYA5 :1; /* Delay A, bit 5 */ word DELAYA6 :1; /* Delay A, bit 6 */ word DELAYA7 :1; /* Delay A, bit 7 */ word DELAYA8 :1; /* Delay A, bit 8 */ word DELAYA9 :1; /* Delay A, bit 9 */ word DELAYA10 :1; /* Delay A, bit 10 */ word DELAYA11 :1; /* Delay A, bit 11 */ word DELAYA12 :1; /* Delay A, bit 12 */ word DELAYA13 :1; /* Delay A, bit 13 */ word DELAYA14 :1; /* Delay A, bit 14 */ word DELAYA15 :1; /* Delay A, bit 15 */ } Bits; } PDBCH1DLYASTR; extern volatile PDBCH1DLYASTR _PDBCH1DLYA @0xFFFFE00A; #define PDBCH1DLYA _PDBCH1DLYA.Word #define PDBCH1DLYA_DELAYA0 _PDBCH1DLYA.Bits.DELAYA0 #define PDBCH1DLYA_DELAYA1 _PDBCH1DLYA.Bits.DELAYA1 #define PDBCH1DLYA_DELAYA2 _PDBCH1DLYA.Bits.DELAYA2 #define PDBCH1DLYA_DELAYA3 _PDBCH1DLYA.Bits.DELAYA3 #define PDBCH1DLYA_DELAYA4 _PDBCH1DLYA.Bits.DELAYA4 #define PDBCH1DLYA_DELAYA5 _PDBCH1DLYA.Bits.DELAYA5 #define PDBCH1DLYA_DELAYA6 _PDBCH1DLYA.Bits.DELAYA6 #define PDBCH1DLYA_DELAYA7 _PDBCH1DLYA.Bits.DELAYA7 #define PDBCH1DLYA_DELAYA8 _PDBCH1DLYA.Bits.DELAYA8 #define PDBCH1DLYA_DELAYA9 _PDBCH1DLYA.Bits.DELAYA9 #define PDBCH1DLYA_DELAYA10 _PDBCH1DLYA.Bits.DELAYA10 #define PDBCH1DLYA_DELAYA11 _PDBCH1DLYA.Bits.DELAYA11 #define PDBCH1DLYA_DELAYA12 _PDBCH1DLYA.Bits.DELAYA12 #define PDBCH1DLYA_DELAYA13 _PDBCH1DLYA.Bits.DELAYA13 #define PDBCH1DLYA_DELAYA14 _PDBCH1DLYA.Bits.DELAYA14 #define PDBCH1DLYA_DELAYA15 _PDBCH1DLYA.Bits.DELAYA15 #define PDBCH1DLYA_DELAYA0_MASK 1 #define PDBCH1DLYA_DELAYA1_MASK 2 #define PDBCH1DLYA_DELAYA2_MASK 4 #define PDBCH1DLYA_DELAYA3_MASK 8 #define PDBCH1DLYA_DELAYA4_MASK 16 #define PDBCH1DLYA_DELAYA5_MASK 32 #define PDBCH1DLYA_DELAYA6_MASK 64 #define PDBCH1DLYA_DELAYA7_MASK 128 #define PDBCH1DLYA_DELAYA8_MASK 256 #define PDBCH1DLYA_DELAYA9_MASK 512 #define PDBCH1DLYA_DELAYA10_MASK 1024 #define PDBCH1DLYA_DELAYA11_MASK 2048 #define PDBCH1DLYA_DELAYA12_MASK 4096 #define PDBCH1DLYA_DELAYA13_MASK 8192 #define PDBCH1DLYA_DELAYA14_MASK 16384 #define PDBCH1DLYA_DELAYA15_MASK 32768 /*** PDBCH1DLYB - PDB Channel 1 Delay B Register; 0xFFFFE00C ***/ typedef union { word Word; struct { word DELAYB0 :1; /* Delay B, bit 0 */ word DELAYB1 :1; /* Delay B, bit 1 */ word DELAYB2 :1; /* Delay B, bit 2 */ word DELAYB3 :1; /* Delay B, bit 3 */ word DELAYB4 :1; /* Delay B, bit 4 */ word DELAYB5 :1; /* Delay B, bit 5 */ word DELAYB6 :1; /* Delay B, bit 6 */ word DELAYB7 :1; /* Delay B, bit 7 */ word DELAYB8 :1; /* Delay B, bit 8 */ word DELAYB9 :1; /* Delay B, bit 9 */ word DELAYB10 :1; /* Delay B, bit 10 */ word DELAYB11 :1; /* Delay B, bit 11 */ word DELAYB12 :1; /* Delay B, bit 12 */ word DELAYB13 :1; /* Delay B, bit 13 */ word DELAYB14 :1; /* Delay B, bit 14 */ word DELAYB15 :1; /* Delay B, bit 15 */ } Bits; } PDBCH1DLYBSTR; extern volatile PDBCH1DLYBSTR _PDBCH1DLYB @0xFFFFE00C; #define PDBCH1DLYB _PDBCH1DLYB.Word #define PDBCH1DLYB_DELAYB0 _PDBCH1DLYB.Bits.DELAYB0 #define PDBCH1DLYB_DELAYB1 _PDBCH1DLYB.Bits.DELAYB1 #define PDBCH1DLYB_DELAYB2 _PDBCH1DLYB.Bits.DELAYB2 #define PDBCH1DLYB_DELAYB3 _PDBCH1DLYB.Bits.DELAYB3 #define PDBCH1DLYB_DELAYB4 _PDBCH1DLYB.Bits.DELAYB4 #define PDBCH1DLYB_DELAYB5 _PDBCH1DLYB.Bits.DELAYB5 #define PDBCH1DLYB_DELAYB6 _PDBCH1DLYB.Bits.DELAYB6 #define PDBCH1DLYB_DELAYB7 _PDBCH1DLYB.Bits.DELAYB7 #define PDBCH1DLYB_DELAYB8 _PDBCH1DLYB.Bits.DELAYB8 #define PDBCH1DLYB_DELAYB9 _PDBCH1DLYB.Bits.DELAYB9 #define PDBCH1DLYB_DELAYB10 _PDBCH1DLYB.Bits.DELAYB10 #define PDBCH1DLYB_DELAYB11 _PDBCH1DLYB.Bits.DELAYB11 #define PDBCH1DLYB_DELAYB12 _PDBCH1DLYB.Bits.DELAYB12 #define PDBCH1DLYB_DELAYB13 _PDBCH1DLYB.Bits.DELAYB13 #define PDBCH1DLYB_DELAYB14 _PDBCH1DLYB.Bits.DELAYB14 #define PDBCH1DLYB_DELAYB15 _PDBCH1DLYB.Bits.DELAYB15 #define PDBCH1DLYB_DELAYB0_MASK 1 #define PDBCH1DLYB_DELAYB1_MASK 2 #define PDBCH1DLYB_DELAYB2_MASK 4 #define PDBCH1DLYB_DELAYB3_MASK 8 #define PDBCH1DLYB_DELAYB4_MASK 16 #define PDBCH1DLYB_DELAYB5_MASK 32 #define PDBCH1DLYB_DELAYB6_MASK 64 #define PDBCH1DLYB_DELAYB7_MASK 128 #define PDBCH1DLYB_DELAYB8_MASK 256 #define PDBCH1DLYB_DELAYB9_MASK 512 #define PDBCH1DLYB_DELAYB10_MASK 1024 #define PDBCH1DLYB_DELAYB11_MASK 2048 #define PDBCH1DLYB_DELAYB12_MASK 4096 #define PDBCH1DLYB_DELAYB13_MASK 8192 #define PDBCH1DLYB_DELAYB14_MASK 16384 #define PDBCH1DLYB_DELAYB15_MASK 32768 /*** PDBCH2CR - PDB Channel 2 Control Register; 0xFFFFE010 ***/ typedef union { word Word; struct { word ENB :1; /* Trigger B Enable */ word ENA :1; /* Trigger A Enable */ word BOS0 :1; /* Channel 2 Trigger B Output Select, bit 0 */ word BOS1 :1; /* Channel 2 Trigger B Output Select, bit 1 */ word AOS0 :1; /* Channel 2 Trigger A Output Select, bit 0 */ word AOS1 :1; /* Channel 2 Trigger A Output Select, bit 1 */ word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word ERRB :1; /* Sequence error on TriggerB */ word ERRA :1; /* Sequence error on TriggerA */ } Bits; struct { word :1; word grpENx :1; word grpBOS :2; word grpAOS :2; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word grpERRx :1; } MergedBits; } PDBCH2CRSTR; extern volatile PDBCH2CRSTR _PDBCH2CR @0xFFFFE010; #define PDBCH2CR _PDBCH2CR.Word #define PDBCH2CR_ENB _PDBCH2CR.Bits.ENB #define PDBCH2CR_ENA _PDBCH2CR.Bits.ENA #define PDBCH2CR_BOS0 _PDBCH2CR.Bits.BOS0 #define PDBCH2CR_BOS1 _PDBCH2CR.Bits.BOS1 #define PDBCH2CR_AOS0 _PDBCH2CR.Bits.AOS0 #define PDBCH2CR_AOS1 _PDBCH2CR.Bits.AOS1 #define PDBCH2CR_ERRB _PDBCH2CR.Bits.ERRB #define PDBCH2CR_ERRA _PDBCH2CR.Bits.ERRA #define PDBCH2CR_BOS _PDBCH2CR.MergedBits.grpBOS #define PDBCH2CR_AOS _PDBCH2CR.MergedBits.grpAOS #define PDBCH2CR_ENB_MASK 1 #define PDBCH2CR_ENA_MASK 2 #define PDBCH2CR_BOS0_MASK 4 #define PDBCH2CR_BOS1_MASK 8 #define PDBCH2CR_AOS0_MASK 16 #define PDBCH2CR_AOS1_MASK 32 #define PDBCH2CR_ERRB_MASK 16384 #define PDBCH2CR_ERRA_MASK 32768 #define PDBCH2CR_BOS_MASK 12 #define PDBCH2CR_BOS_BITNUM 2 #define PDBCH2CR_AOS_MASK 48 #define PDBCH2CR_AOS_BITNUM 4 /*** PDBCH2DLYA - PDB Channel 2 Delay A Register; 0xFFFFE012 ***/ typedef union { word Word; struct { word DELAYA0 :1; /* Delay A, bit 0 */ word DELAYA1 :1; /* Delay A, bit 1 */ word DELAYA2 :1; /* Delay A, bit 2 */ word DELAYA3 :1; /* Delay A, bit 3 */ word DELAYA4 :1; /* Delay A, bit 4 */ word DELAYA5 :1; /* Delay A, bit 5 */ word DELAYA6 :1; /* Delay A, bit 6 */ word DELAYA7 :1; /* Delay A, bit 7 */ word DELAYA8 :1; /* Delay A, bit 8 */ word DELAYA9 :1; /* Delay A, bit 9 */ word DELAYA10 :1; /* Delay A, bit 10 */ word DELAYA11 :1; /* Delay A, bit 11 */ word DELAYA12 :1; /* Delay A, bit 12 */ word DELAYA13 :1; /* Delay A, bit 13 */ word DELAYA14 :1; /* Delay A, bit 14 */ word DELAYA15 :1; /* Delay A, bit 15 */ } Bits; } PDBCH2DLYASTR; extern volatile PDBCH2DLYASTR _PDBCH2DLYA @0xFFFFE012; #define PDBCH2DLYA _PDBCH2DLYA.Word #define PDBCH2DLYA_DELAYA0 _PDBCH2DLYA.Bits.DELAYA0 #define PDBCH2DLYA_DELAYA1 _PDBCH2DLYA.Bits.DELAYA1 #define PDBCH2DLYA_DELAYA2 _PDBCH2DLYA.Bits.DELAYA2 #define PDBCH2DLYA_DELAYA3 _PDBCH2DLYA.Bits.DELAYA3 #define PDBCH2DLYA_DELAYA4 _PDBCH2DLYA.Bits.DELAYA4 #define PDBCH2DLYA_DELAYA5 _PDBCH2DLYA.Bits.DELAYA5 #define PDBCH2DLYA_DELAYA6 _PDBCH2DLYA.Bits.DELAYA6 #define PDBCH2DLYA_DELAYA7 _PDBCH2DLYA.Bits.DELAYA7 #define PDBCH2DLYA_DELAYA8 _PDBCH2DLYA.Bits.DELAYA8 #define PDBCH2DLYA_DELAYA9 _PDBCH2DLYA.Bits.DELAYA9 #define PDBCH2DLYA_DELAYA10 _PDBCH2DLYA.Bits.DELAYA10 #define PDBCH2DLYA_DELAYA11 _PDBCH2DLYA.Bits.DELAYA11 #define PDBCH2DLYA_DELAYA12 _PDBCH2DLYA.Bits.DELAYA12 #define PDBCH2DLYA_DELAYA13 _PDBCH2DLYA.Bits.DELAYA13 #define PDBCH2DLYA_DELAYA14 _PDBCH2DLYA.Bits.DELAYA14 #define PDBCH2DLYA_DELAYA15 _PDBCH2DLYA.Bits.DELAYA15 #define PDBCH2DLYA_DELAYA0_MASK 1 #define PDBCH2DLYA_DELAYA1_MASK 2 #define PDBCH2DLYA_DELAYA2_MASK 4 #define PDBCH2DLYA_DELAYA3_MASK 8 #define PDBCH2DLYA_DELAYA4_MASK 16 #define PDBCH2DLYA_DELAYA5_MASK 32 #define PDBCH2DLYA_DELAYA6_MASK 64 #define PDBCH2DLYA_DELAYA7_MASK 128 #define PDBCH2DLYA_DELAYA8_MASK 256 #define PDBCH2DLYA_DELAYA9_MASK 512 #define PDBCH2DLYA_DELAYA10_MASK 1024 #define PDBCH2DLYA_DELAYA11_MASK 2048 #define PDBCH2DLYA_DELAYA12_MASK 4096 #define PDBCH2DLYA_DELAYA13_MASK 8192 #define PDBCH2DLYA_DELAYA14_MASK 16384 #define PDBCH2DLYA_DELAYA15_MASK 32768 /*** PDBCH2DLYB - PDB Channel 2 Delay B Register; 0xFFFFE014 ***/ typedef union { word Word; struct { word DELAYB0 :1; /* Delay B, bit 0 */ word DELAYB1 :1; /* Delay B, bit 1 */ word DELAYB2 :1; /* Delay B, bit 2 */ word DELAYB3 :1; /* Delay B, bit 3 */ word DELAYB4 :1; /* Delay B, bit 4 */ word DELAYB5 :1; /* Delay B, bit 5 */ word DELAYB6 :1; /* Delay B, bit 6 */ word DELAYB7 :1; /* Delay B, bit 7 */ word DELAYB8 :1; /* Delay B, bit 8 */ word DELAYB9 :1; /* Delay B, bit 9 */ word DELAYB10 :1; /* Delay B, bit 10 */ word DELAYB11 :1; /* Delay B, bit 11 */ word DELAYB12 :1; /* Delay B, bit 12 */ word DELAYB13 :1; /* Delay B, bit 13 */ word DELAYB14 :1; /* Delay B, bit 14 */ word DELAYB15 :1; /* Delay B, bit 15 */ } Bits; } PDBCH2DLYBSTR; extern volatile PDBCH2DLYBSTR _PDBCH2DLYB @0xFFFFE014; #define PDBCH2DLYB _PDBCH2DLYB.Word #define PDBCH2DLYB_DELAYB0 _PDBCH2DLYB.Bits.DELAYB0 #define PDBCH2DLYB_DELAYB1 _PDBCH2DLYB.Bits.DELAYB1 #define PDBCH2DLYB_DELAYB2 _PDBCH2DLYB.Bits.DELAYB2 #define PDBCH2DLYB_DELAYB3 _PDBCH2DLYB.Bits.DELAYB3 #define PDBCH2DLYB_DELAYB4 _PDBCH2DLYB.Bits.DELAYB4 #define PDBCH2DLYB_DELAYB5 _PDBCH2DLYB.Bits.DELAYB5 #define PDBCH2DLYB_DELAYB6 _PDBCH2DLYB.Bits.DELAYB6 #define PDBCH2DLYB_DELAYB7 _PDBCH2DLYB.Bits.DELAYB7 #define PDBCH2DLYB_DELAYB8 _PDBCH2DLYB.Bits.DELAYB8 #define PDBCH2DLYB_DELAYB9 _PDBCH2DLYB.Bits.DELAYB9 #define PDBCH2DLYB_DELAYB10 _PDBCH2DLYB.Bits.DELAYB10 #define PDBCH2DLYB_DELAYB11 _PDBCH2DLYB.Bits.DELAYB11 #define PDBCH2DLYB_DELAYB12 _PDBCH2DLYB.Bits.DELAYB12 #define PDBCH2DLYB_DELAYB13 _PDBCH2DLYB.Bits.DELAYB13 #define PDBCH2DLYB_DELAYB14 _PDBCH2DLYB.Bits.DELAYB14 #define PDBCH2DLYB_DELAYB15 _PDBCH2DLYB.Bits.DELAYB15 #define PDBCH2DLYB_DELAYB0_MASK 1 #define PDBCH2DLYB_DELAYB1_MASK 2 #define PDBCH2DLYB_DELAYB2_MASK 4 #define PDBCH2DLYB_DELAYB3_MASK 8 #define PDBCH2DLYB_DELAYB4_MASK 16 #define PDBCH2DLYB_DELAYB5_MASK 32 #define PDBCH2DLYB_DELAYB6_MASK 64 #define PDBCH2DLYB_DELAYB7_MASK 128 #define PDBCH2DLYB_DELAYB8_MASK 256 #define PDBCH2DLYB_DELAYB9_MASK 512 #define PDBCH2DLYB_DELAYB10_MASK 1024 #define PDBCH2DLYB_DELAYB11_MASK 2048 #define PDBCH2DLYB_DELAYB12_MASK 4096 #define PDBCH2DLYB_DELAYB13_MASK 8192 #define PDBCH2DLYB_DELAYB14_MASK 16384 #define PDBCH2DLYB_DELAYB15_MASK 32768 /*** PDBCH3CR - PDB Channel 3 Control Register; 0xFFFFE018 ***/ typedef union { word Word; struct { word ENB :1; /* Trigger B Enable */ word ENA :1; /* Trigger A Enable */ word BOS0 :1; /* Channel 3 Trigger B Output Select, bit 0 */ word BOS1 :1; /* Channel 3 Trigger B Output Select, bit 1 */ word AOS0 :1; /* Channel 3 Trigger A Output Select, bit 0 */ word AOS1 :1; /* Channel 3 Trigger A Output Select, bit 1 */ word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word ERRB :1; /* Sequence error on TriggerB */ word ERRA :1; /* Sequence error on TriggerA */ } Bits; struct { word :1; word grpENx :1; word grpBOS :2; word grpAOS :2; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word grpERRx :1; } MergedBits; } PDBCH3CRSTR; extern volatile PDBCH3CRSTR _PDBCH3CR @0xFFFFE018; #define PDBCH3CR _PDBCH3CR.Word #define PDBCH3CR_ENB _PDBCH3CR.Bits.ENB #define PDBCH3CR_ENA _PDBCH3CR.Bits.ENA #define PDBCH3CR_BOS0 _PDBCH3CR.Bits.BOS0 #define PDBCH3CR_BOS1 _PDBCH3CR.Bits.BOS1 #define PDBCH3CR_AOS0 _PDBCH3CR.Bits.AOS0 #define PDBCH3CR_AOS1 _PDBCH3CR.Bits.AOS1 #define PDBCH3CR_ERRB _PDBCH3CR.Bits.ERRB #define PDBCH3CR_ERRA _PDBCH3CR.Bits.ERRA #define PDBCH3CR_BOS _PDBCH3CR.MergedBits.grpBOS #define PDBCH3CR_AOS _PDBCH3CR.MergedBits.grpAOS #define PDBCH3CR_ENB_MASK 1 #define PDBCH3CR_ENA_MASK 2 #define PDBCH3CR_BOS0_MASK 4 #define PDBCH3CR_BOS1_MASK 8 #define PDBCH3CR_AOS0_MASK 16 #define PDBCH3CR_AOS1_MASK 32 #define PDBCH3CR_ERRB_MASK 16384 #define PDBCH3CR_ERRA_MASK 32768 #define PDBCH3CR_BOS_MASK 12 #define PDBCH3CR_BOS_BITNUM 2 #define PDBCH3CR_AOS_MASK 48 #define PDBCH3CR_AOS_BITNUM 4 /*** PDBCH3DLYA - PDB Channel 3 Delay A Register; 0xFFFFE01A ***/ typedef union { word Word; struct { word DELAYA0 :1; /* Delay A, bit 0 */ word DELAYA1 :1; /* Delay A, bit 1 */ word DELAYA2 :1; /* Delay A, bit 2 */ word DELAYA3 :1; /* Delay A, bit 3 */ word DELAYA4 :1; /* Delay A, bit 4 */ word DELAYA5 :1; /* Delay A, bit 5 */ word DELAYA6 :1; /* Delay A, bit 6 */ word DELAYA7 :1; /* Delay A, bit 7 */ word DELAYA8 :1; /* Delay A, bit 8 */ word DELAYA9 :1; /* Delay A, bit 9 */ word DELAYA10 :1; /* Delay A, bit 10 */ word DELAYA11 :1; /* Delay A, bit 11 */ word DELAYA12 :1; /* Delay A, bit 12 */ word DELAYA13 :1; /* Delay A, bit 13 */ word DELAYA14 :1; /* Delay A, bit 14 */ word DELAYA15 :1; /* Delay A, bit 15 */ } Bits; } PDBCH3DLYASTR; extern volatile PDBCH3DLYASTR _PDBCH3DLYA @0xFFFFE01A; #define PDBCH3DLYA _PDBCH3DLYA.Word #define PDBCH3DLYA_DELAYA0 _PDBCH3DLYA.Bits.DELAYA0 #define PDBCH3DLYA_DELAYA1 _PDBCH3DLYA.Bits.DELAYA1 #define PDBCH3DLYA_DELAYA2 _PDBCH3DLYA.Bits.DELAYA2 #define PDBCH3DLYA_DELAYA3 _PDBCH3DLYA.Bits.DELAYA3 #define PDBCH3DLYA_DELAYA4 _PDBCH3DLYA.Bits.DELAYA4 #define PDBCH3DLYA_DELAYA5 _PDBCH3DLYA.Bits.DELAYA5 #define PDBCH3DLYA_DELAYA6 _PDBCH3DLYA.Bits.DELAYA6 #define PDBCH3DLYA_DELAYA7 _PDBCH3DLYA.Bits.DELAYA7 #define PDBCH3DLYA_DELAYA8 _PDBCH3DLYA.Bits.DELAYA8 #define PDBCH3DLYA_DELAYA9 _PDBCH3DLYA.Bits.DELAYA9 #define PDBCH3DLYA_DELAYA10 _PDBCH3DLYA.Bits.DELAYA10 #define PDBCH3DLYA_DELAYA11 _PDBCH3DLYA.Bits.DELAYA11 #define PDBCH3DLYA_DELAYA12 _PDBCH3DLYA.Bits.DELAYA12 #define PDBCH3DLYA_DELAYA13 _PDBCH3DLYA.Bits.DELAYA13 #define PDBCH3DLYA_DELAYA14 _PDBCH3DLYA.Bits.DELAYA14 #define PDBCH3DLYA_DELAYA15 _PDBCH3DLYA.Bits.DELAYA15 #define PDBCH3DLYA_DELAYA0_MASK 1 #define PDBCH3DLYA_DELAYA1_MASK 2 #define PDBCH3DLYA_DELAYA2_MASK 4 #define PDBCH3DLYA_DELAYA3_MASK 8 #define PDBCH3DLYA_DELAYA4_MASK 16 #define PDBCH3DLYA_DELAYA5_MASK 32 #define PDBCH3DLYA_DELAYA6_MASK 64 #define PDBCH3DLYA_DELAYA7_MASK 128 #define PDBCH3DLYA_DELAYA8_MASK 256 #define PDBCH3DLYA_DELAYA9_MASK 512 #define PDBCH3DLYA_DELAYA10_MASK 1024 #define PDBCH3DLYA_DELAYA11_MASK 2048 #define PDBCH3DLYA_DELAYA12_MASK 4096 #define PDBCH3DLYA_DELAYA13_MASK 8192 #define PDBCH3DLYA_DELAYA14_MASK 16384 #define PDBCH3DLYA_DELAYA15_MASK 32768 /*** PDBCH3DLYB - PDB Channel 3 Delay B Register; 0xFFFFE01C ***/ typedef union { word Word; struct { word DELAYB0 :1; /* Delay B, bit 0 */ word DELAYB1 :1; /* Delay B, bit 1 */ word DELAYB2 :1; /* Delay B, bit 2 */ word DELAYB3 :1; /* Delay B, bit 3 */ word DELAYB4 :1; /* Delay B, bit 4 */ word DELAYB5 :1; /* Delay B, bit 5 */ word DELAYB6 :1; /* Delay B, bit 6 */ word DELAYB7 :1; /* Delay B, bit 7 */ word DELAYB8 :1; /* Delay B, bit 8 */ word DELAYB9 :1; /* Delay B, bit 9 */ word DELAYB10 :1; /* Delay B, bit 10 */ word DELAYB11 :1; /* Delay B, bit 11 */ word DELAYB12 :1; /* Delay B, bit 12 */ word DELAYB13 :1; /* Delay B, bit 13 */ word DELAYB14 :1; /* Delay B, bit 14 */ word DELAYB15 :1; /* Delay B, bit 15 */ } Bits; } PDBCH3DLYBSTR; extern volatile PDBCH3DLYBSTR _PDBCH3DLYB @0xFFFFE01C; #define PDBCH3DLYB _PDBCH3DLYB.Word #define PDBCH3DLYB_DELAYB0 _PDBCH3DLYB.Bits.DELAYB0 #define PDBCH3DLYB_DELAYB1 _PDBCH3DLYB.Bits.DELAYB1 #define PDBCH3DLYB_DELAYB2 _PDBCH3DLYB.Bits.DELAYB2 #define PDBCH3DLYB_DELAYB3 _PDBCH3DLYB.Bits.DELAYB3 #define PDBCH3DLYB_DELAYB4 _PDBCH3DLYB.Bits.DELAYB4 #define PDBCH3DLYB_DELAYB5 _PDBCH3DLYB.Bits.DELAYB5 #define PDBCH3DLYB_DELAYB6 _PDBCH3DLYB.Bits.DELAYB6 #define PDBCH3DLYB_DELAYB7 _PDBCH3DLYB.Bits.DELAYB7 #define PDBCH3DLYB_DELAYB8 _PDBCH3DLYB.Bits.DELAYB8 #define PDBCH3DLYB_DELAYB9 _PDBCH3DLYB.Bits.DELAYB9 #define PDBCH3DLYB_DELAYB10 _PDBCH3DLYB.Bits.DELAYB10 #define PDBCH3DLYB_DELAYB11 _PDBCH3DLYB.Bits.DELAYB11 #define PDBCH3DLYB_DELAYB12 _PDBCH3DLYB.Bits.DELAYB12 #define PDBCH3DLYB_DELAYB13 _PDBCH3DLYB.Bits.DELAYB13 #define PDBCH3DLYB_DELAYB14 _PDBCH3DLYB.Bits.DELAYB14 #define PDBCH3DLYB_DELAYB15 _PDBCH3DLYB.Bits.DELAYB15 #define PDBCH3DLYB_DELAYB0_MASK 1 #define PDBCH3DLYB_DELAYB1_MASK 2 #define PDBCH3DLYB_DELAYB2_MASK 4 #define PDBCH3DLYB_DELAYB3_MASK 8 #define PDBCH3DLYB_DELAYB4_MASK 16 #define PDBCH3DLYB_DELAYB5_MASK 32 #define PDBCH3DLYB_DELAYB6_MASK 64 #define PDBCH3DLYB_DELAYB7_MASK 128 #define PDBCH3DLYB_DELAYB8_MASK 256 #define PDBCH3DLYB_DELAYB9_MASK 512 #define PDBCH3DLYB_DELAYB10_MASK 1024 #define PDBCH3DLYB_DELAYB11_MASK 2048 #define PDBCH3DLYB_DELAYB12_MASK 4096 #define PDBCH3DLYB_DELAYB13_MASK 8192 #define PDBCH3DLYB_DELAYB14_MASK 16384 #define PDBCH3DLYB_DELAYB15_MASK 32768 /*** PDBCH4CR - PDB Channel 4 Control Register; 0xFFFFE020 ***/ typedef union { word Word; struct { word ENB :1; /* Trigger B Enable */ word ENA :1; /* Trigger A Enable */ word BOS0 :1; /* Channel 4 Trigger B Output Select, bit 0 */ word BOS1 :1; /* Channel 4 Trigger B Output Select, bit 1 */ word AOS0 :1; /* Channel 4 Trigger A Output Select, bit 0 */ word AOS1 :1; /* Channel 4 Trigger A Output Select, bit 1 */ word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word ERRB :1; /* Sequence error on TriggerB */ word ERRA :1; /* Sequence error on TriggerA */ } Bits; struct { word :1; word grpENx :1; word grpBOS :2; word grpAOS :2; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word :1; word grpERRx :1; } MergedBits; } PDBCH4CRSTR; extern volatile PDBCH4CRSTR _PDBCH4CR @0xFFFFE020; #define PDBCH4CR _PDBCH4CR.Word #define PDBCH4CR_ENB _PDBCH4CR.Bits.ENB #define PDBCH4CR_ENA _PDBCH4CR.Bits.ENA #define PDBCH4CR_BOS0 _PDBCH4CR.Bits.BOS0 #define PDBCH4CR_BOS1 _PDBCH4CR.Bits.BOS1 #define PDBCH4CR_AOS0 _PDBCH4CR.Bits.AOS0 #define PDBCH4CR_AOS1 _PDBCH4CR.Bits.AOS1 #define PDBCH4CR_ERRB _PDBCH4CR.Bits.ERRB #define PDBCH4CR_ERRA _PDBCH4CR.Bits.ERRA #define PDBCH4CR_BOS _PDBCH4CR.MergedBits.grpBOS #define PDBCH4CR_AOS _PDBCH4CR.MergedBits.grpAOS #define PDBCH4CR_ENB_MASK 1 #define PDBCH4CR_ENA_MASK 2 #define PDBCH4CR_BOS0_MASK 4 #define PDBCH4CR_BOS1_MASK 8 #define PDBCH4CR_AOS0_MASK 16 #define PDBCH4CR_AOS1_MASK 32 #define PDBCH4CR_ERRB_MASK 16384 #define PDBCH4CR_ERRA_MASK 32768 #define PDBCH4CR_BOS_MASK 12 #define PDBCH4CR_BOS_BITNUM 2 #define PDBCH4CR_AOS_MASK 48 #define PDBCH4CR_AOS_BITNUM 4 /*** PDBCH4DLYA - PDB Channel 4 Delay A Register; 0xFFFFE022 ***/ typedef union { word Word; struct { word DELAYA0 :1; /* Delay A, bit 0 */ word DELAYA1 :1; /* Delay A, bit 1 */ word DELAYA2 :1; /* Delay A, bit 2 */ word DELAYA3 :1; /* Delay A, bit 3 */ word DELAYA4 :1; /* Delay A, bit 4 */ word DELAYA5 :1; /* Delay A, bit 5 */ word DELAYA6 :1; /* Delay A, bit 6 */ word DELAYA7 :1; /* Delay A, bit 7 */ word DELAYA8 :1; /* Delay A, bit 8 */ word DELAYA9 :1; /* Delay A, bit 9 */ word DELAYA10 :1; /* Delay A, bit 10 */ word DELAYA11 :1; /* Delay A, bit 11 */ word DELAYA12 :1; /* Delay A, bit 12 */ word DELAYA13 :1; /* Delay A, bit 13 */ word DELAYA14 :1; /* Delay A, bit 14 */ word DELAYA15 :1; /* Delay A, bit 15 */ } Bits; } PDBCH4DLYASTR; extern volatile PDBCH4DLYASTR _PDBCH4DLYA @0xFFFFE022; #define PDBCH4DLYA _PDBCH4DLYA.Word #define PDBCH4DLYA_DELAYA0 _PDBCH4DLYA.Bits.DELAYA0 #define PDBCH4DLYA_DELAYA1 _PDBCH4DLYA.Bits.DELAYA1 #define PDBCH4DLYA_DELAYA2 _PDBCH4DLYA.Bits.DELAYA2 #define PDBCH4DLYA_DELAYA3 _PDBCH4DLYA.Bits.DELAYA3 #define PDBCH4DLYA_DELAYA4 _PDBCH4DLYA.Bits.DELAYA4 #define PDBCH4DLYA_DELAYA5 _PDBCH4DLYA.Bits.DELAYA5 #define PDBCH4DLYA_DELAYA6 _PDBCH4DLYA.Bits.DELAYA6 #define PDBCH4DLYA_DELAYA7 _PDBCH4DLYA.Bits.DELAYA7 #define PDBCH4DLYA_DELAYA8 _PDBCH4DLYA.Bits.DELAYA8 #define PDBCH4DLYA_DELAYA9 _PDBCH4DLYA.Bits.DELAYA9 #define PDBCH4DLYA_DELAYA10 _PDBCH4DLYA.Bits.DELAYA10 #define PDBCH4DLYA_DELAYA11 _PDBCH4DLYA.Bits.DELAYA11 #define PDBCH4DLYA_DELAYA12 _PDBCH4DLYA.Bits.DELAYA12 #define PDBCH4DLYA_DELAYA13 _PDBCH4DLYA.Bits.DELAYA13 #define PDBCH4DLYA_DELAYA14 _PDBCH4DLYA.Bits.DELAYA14 #define PDBCH4DLYA_DELAYA15 _PDBCH4DLYA.Bits.DELAYA15 #define PDBCH4DLYA_DELAYA0_MASK 1 #define PDBCH4DLYA_DELAYA1_MASK 2 #define PDBCH4DLYA_DELAYA2_MASK 4 #define PDBCH4DLYA_DELAYA3_MASK 8 #define PDBCH4DLYA_DELAYA4_MASK 16 #define PDBCH4DLYA_DELAYA5_MASK 32 #define PDBCH4DLYA_DELAYA6_MASK 64 #define PDBCH4DLYA_DELAYA7_MASK 128 #define PDBCH4DLYA_DELAYA8_MASK 256 #define PDBCH4DLYA_DELAYA9_MASK 512 #define PDBCH4DLYA_DELAYA10_MASK 1024 #define PDBCH4DLYA_DELAYA11_MASK 2048 #define PDBCH4DLYA_DELAYA12_MASK 4096 #define PDBCH4DLYA_DELAYA13_MASK 8192 #define PDBCH4DLYA_DELAYA14_MASK 16384 #define PDBCH4DLYA_DELAYA15_MASK 32768 /*** PDBCH4DLYB - PDB Channel 4 Delay B Register; 0xFFFFE024 ***/ typedef union { word Word; struct { word DELAYB0 :1; /* Delay B, bit 0 */ word DELAYB1 :1; /* Delay B, bit 1 */ word DELAYB2 :1; /* Delay B, bit 2 */ word DELAYB3 :1; /* Delay B, bit 3 */ word DELAYB4 :1; /* Delay B, bit 4 */ word DELAYB5 :1; /* Delay B, bit 5 */ word DELAYB6 :1; /* Delay B, bit 6 */ word DELAYB7 :1; /* Delay B, bit 7 */ word DELAYB8 :1; /* Delay B, bit 8 */ word DELAYB9 :1; /* Delay B, bit 9 */ word DELAYB10 :1; /* Delay B, bit 10 */ word DELAYB11 :1; /* Delay B, bit 11 */ word DELAYB12 :1; /* Delay B, bit 12 */ word DELAYB13 :1; /* Delay B, bit 13 */ word DELAYB14 :1; /* Delay B, bit 14 */ word DELAYB15 :1; /* Delay B, bit 15 */ } Bits; } PDBCH4DLYBSTR; extern volatile PDBCH4DLYBSTR _PDBCH4DLYB @0xFFFFE024; #define PDBCH4DLYB _PDBCH4DLYB.Word #define PDBCH4DLYB_DELAYB0 _PDBCH4DLYB.Bits.DELAYB0 #define PDBCH4DLYB_DELAYB1 _PDBCH4DLYB.Bits.DELAYB1 #define PDBCH4DLYB_DELAYB2 _PDBCH4DLYB.Bits.DELAYB2 #define PDBCH4DLYB_DELAYB3 _PDBCH4DLYB.Bits.DELAYB3 #define PDBCH4DLYB_DELAYB4 _PDBCH4DLYB.Bits.DELAYB4 #define PDBCH4DLYB_DELAYB5 _PDBCH4DLYB.Bits.DELAYB5 #define PDBCH4DLYB_DELAYB6 _PDBCH4DLYB.Bits.DELAYB6 #define PDBCH4DLYB_DELAYB7 _PDBCH4DLYB.Bits.DELAYB7 #define PDBCH4DLYB_DELAYB8 _PDBCH4DLYB.Bits.DELAYB8 #define PDBCH4DLYB_DELAYB9 _PDBCH4DLYB.Bits.DELAYB9 #define PDBCH4DLYB_DELAYB10 _PDBCH4DLYB.Bits.DELAYB10 #define PDBCH4DLYB_DELAYB11 _PDBCH4DLYB.Bits.DELAYB11 #define PDBCH4DLYB_DELAYB12 _PDBCH4DLYB.Bits.DELAYB12 #define PDBCH4DLYB_DELAYB13 _PDBCH4DLYB.Bits.DELAYB13 #define PDBCH4DLYB_DELAYB14 _PDBCH4DLYB.Bits.DELAYB14 #define PDBCH4DLYB_DELAYB15 _PDBCH4DLYB.Bits.DELAYB15 #define PDBCH4DLYB_DELAYB0_MASK 1 #define PDBCH4DLYB_DELAYB1_MASK 2 #define PDBCH4DLYB_DELAYB2_MASK 4 #define PDBCH4DLYB_DELAYB3_MASK 8 #define PDBCH4DLYB_DELAYB4_MASK 16 #define PDBCH4DLYB_DELAYB5_MASK 32 #define PDBCH4DLYB_DELAYB6_MASK 64 #define PDBCH4DLYB_DELAYB7_MASK 128 #define PDBCH4DLYB_DELAYB8_MASK 256 #define PDBCH4DLYB_DELAYB9_MASK 512 #define PDBCH4DLYB_DELAYB10_MASK 1024 #define PDBCH4DLYB_DELAYB11_MASK 2048 #define PDBCH4DLYB_DELAYB12_MASK 4096 #define PDBCH4DLYB_DELAYB13_MASK 8192 #define PDBCH4DLYB_DELAYB14_MASK 16384 #define PDBCH4DLYB_DELAYB15_MASK 32768 /*** INTC_FRC - INTC Force Interrupt Register; 0xFFFFFFD0 ***/ typedef union { byte Byte; struct { byte LVL7 :1; /* Force Level 7 interrupt */ byte LVL6 :1; /* Force Level 6 interrupt */ byte LVL5 :1; /* Force Level 5 interrupt */ byte LVL4 :1; /* Force Level 4 interrupt */ byte LVL3 :1; /* Force Level 3 interrupt */ byte LVL2 :1; /* Force Level 2 interrupt */ byte LVL1 :1; /* Force Level 1 interrupt */ byte :1; } Bits; } INTC_FRCSTR; extern volatile INTC_FRCSTR _INTC_FRC @0xFFFFFFD0; #define INTC_FRC _INTC_FRC.Byte #define INTC_FRC_LVL7 _INTC_FRC.Bits.LVL7 #define INTC_FRC_LVL6 _INTC_FRC.Bits.LVL6 #define INTC_FRC_LVL5 _INTC_FRC.Bits.LVL5 #define INTC_FRC_LVL4 _INTC_FRC.Bits.LVL4 #define INTC_FRC_LVL3 _INTC_FRC.Bits.LVL3 #define INTC_FRC_LVL2 _INTC_FRC.Bits.LVL2 #define INTC_FRC_LVL1 _INTC_FRC.Bits.LVL1 #define INTC_FRC_LVL7_MASK 1 #define INTC_FRC_LVL6_MASK 2 #define INTC_FRC_LVL5_MASK 4 #define INTC_FRC_LVL4_MASK 8 #define INTC_FRC_LVL3_MASK 16 #define INTC_FRC_LVL2_MASK 32 #define INTC_FRC_LVL1_MASK 64 /*** INTC_PL6P7 - INTC Programmable Level 6, Priority 7 Register; 0xFFFFFFD8 ***/ typedef union { byte Byte; struct { byte REQN0 :1; /* Request number, bit 0 */ byte REQN1 :1; /* Request number, bit 1 */ byte REQN2 :1; /* Request number, bit 2 */ byte REQN3 :1; /* Request number, bit 3 */ byte REQN4 :1; /* Request number, bit 4 */ byte REQN5 :1; /* Request number, bit 5 */ byte :1; byte :1; } Bits; struct { byte grpREQN :6; byte :1; byte :1; } MergedBits; } INTC_PL6P7STR; extern volatile INTC_PL6P7STR _INTC_PL6P7 @0xFFFFFFD8; #define INTC_PL6P7 _INTC_PL6P7.Byte #define INTC_PL6P7_REQN0 _INTC_PL6P7.Bits.REQN0 #define INTC_PL6P7_REQN1 _INTC_PL6P7.Bits.REQN1 #define INTC_PL6P7_REQN2 _INTC_PL6P7.Bits.REQN2 #define INTC_PL6P7_REQN3 _INTC_PL6P7.Bits.REQN3 #define INTC_PL6P7_REQN4 _INTC_PL6P7.Bits.REQN4 #define INTC_PL6P7_REQN5 _INTC_PL6P7.Bits.REQN5 #define INTC_PL6P7_REQN _INTC_PL6P7.MergedBits.grpREQN #define INTC_PL6P7_REQN0_MASK 1 #define INTC_PL6P7_REQN1_MASK 2 #define INTC_PL6P7_REQN2_MASK 4 #define INTC_PL6P7_REQN3_MASK 8 #define INTC_PL6P7_REQN4_MASK 16 #define INTC_PL6P7_REQN5_MASK 32 #define INTC_PL6P7_REQN_MASK 63 #define INTC_PL6P7_REQN_BITNUM 0 /*** INTC_PL6P6 - INTC Programmable Level 6, Priority 6 Register; 0xFFFFFFD9 ***/ typedef union { byte Byte; struct { byte REQN0 :1; /* Request number, bit 0 */ byte REQN1 :1; /* Request number, bit 1 */ byte REQN2 :1; /* Request number, bit 2 */ byte REQN3 :1; /* Request number, bit 3 */ byte REQN4 :1; /* Request number, bit 4 */ byte REQN5 :1; /* Request number, bit 5 */ byte :1; byte :1; } Bits; struct { byte grpREQN :6; byte :1; byte :1; } MergedBits; } INTC_PL6P6STR; extern volatile INTC_PL6P6STR _INTC_PL6P6 @0xFFFFFFD9; #define INTC_PL6P6 _INTC_PL6P6.Byte #define INTC_PL6P6_REQN0 _INTC_PL6P6.Bits.REQN0 #define INTC_PL6P6_REQN1 _INTC_PL6P6.Bits.REQN1 #define INTC_PL6P6_REQN2 _INTC_PL6P6.Bits.REQN2 #define INTC_PL6P6_REQN3 _INTC_PL6P6.Bits.REQN3 #define INTC_PL6P6_REQN4 _INTC_PL6P6.Bits.REQN4 #define INTC_PL6P6_REQN5 _INTC_PL6P6.Bits.REQN5 #define INTC_PL6P6_REQN _INTC_PL6P6.MergedBits.grpREQN #define INTC_PL6P6_REQN0_MASK 1 #define INTC_PL6P6_REQN1_MASK 2 #define INTC_PL6P6_REQN2_MASK 4 #define INTC_PL6P6_REQN3_MASK 8 #define INTC_PL6P6_REQN4_MASK 16 #define INTC_PL6P6_REQN5_MASK 32 #define INTC_PL6P6_REQN_MASK 63 #define INTC_PL6P6_REQN_BITNUM 0 /*** INTC_WCR - INTC Wake-up Control Register; 0xFFFFFFDB ***/ typedef union { byte Byte; struct { byte MASK0 :1; /* Interrupt mask level, bit 0 */ byte MASK1 :1; /* Interrupt mask level, bit 1 */ byte MASK2 :1; /* Interrupt mask level, bit 2 */ byte :1; byte :1; byte :1; byte :1; byte ENB :1; /* Enable */ } Bits; struct { byte grpMASK :3; byte :1; byte :1; byte :1; byte :1; byte :1; } MergedBits; } INTC_WCRSTR; extern volatile INTC_WCRSTR _INTC_WCR @0xFFFFFFDB; #define INTC_WCR _INTC_WCR.Byte #define INTC_WCR_MASK0 _INTC_WCR.Bits.MASK0 #define INTC_WCR_MASK1 _INTC_WCR.Bits.MASK1 #define INTC_WCR_MASK2 _INTC_WCR.Bits.MASK2 #define INTC_WCR_ENB _INTC_WCR.Bits.ENB #define INTC_WCR_MASK _INTC_WCR.MergedBits.grpMASK #define INTC_WCR_MASK0_MASK 1 #define INTC_WCR_MASK1_MASK 2 #define INTC_WCR_MASK2_MASK 4 #define INTC_WCR_ENB_MASK 128 #define INTC_WCR_MASK_MASK 7 #define INTC_WCR_MASK_BITNUM 0 /*** INTC_SFRC - INTC Set Interrupt Force Register; 0xFFFFFFDE ***/ typedef union { byte Byte; struct { byte SET0 :1; /* Sets corresponding bits in the INTC_FRC register, bit 0 */ byte SET1 :1; /* Sets corresponding bits in the INTC_FRC register, bit 1 */ byte SET2 :1; /* Sets corresponding bits in the INTC_FRC register, bit 2 */ byte SET3 :1; /* Sets corresponding bits in the INTC_FRC register, bit 3 */ byte SET4 :1; /* Sets corresponding bits in the INTC_FRC register, bit 4 */ byte SET5 :1; /* Sets corresponding bits in the INTC_FRC register, bit 5 */ byte :1; byte :1; } Bits; struct { byte grpSET :6; byte :1; byte :1; } MergedBits; } INTC_SFRCSTR; extern volatile INTC_SFRCSTR _INTC_SFRC @0xFFFFFFDE; #define INTC_SFRC _INTC_SFRC.Byte #define INTC_SFRC_SET0 _INTC_SFRC.Bits.SET0 #define INTC_SFRC_SET1 _INTC_SFRC.Bits.SET1 #define INTC_SFRC_SET2 _INTC_SFRC.Bits.SET2 #define INTC_SFRC_SET3 _INTC_SFRC.Bits.SET3 #define INTC_SFRC_SET4 _INTC_SFRC.Bits.SET4 #define INTC_SFRC_SET5 _INTC_SFRC.Bits.SET5 #define INTC_SFRC_SET _INTC_SFRC.MergedBits.grpSET #define INTC_SFRC_SET0_MASK 1 #define INTC_SFRC_SET1_MASK 2 #define INTC_SFRC_SET2_MASK 4 #define INTC_SFRC_SET3_MASK 8 #define INTC_SFRC_SET4_MASK 16 #define INTC_SFRC_SET5_MASK 32 #define INTC_SFRC_SET_MASK 63 #define INTC_SFRC_SET_BITNUM 0 /*** INTC_CFRC - INTC Clear Interrupt Force Register; 0xFFFFFFDF ***/ typedef union { byte Byte; struct { byte CLR0 :1; /* Clears corresponding bits in the INTC_FRC register, bit 0 */ byte CLR1 :1; /* Clears corresponding bits in the INTC_FRC register, bit 1 */ byte CLR2 :1; /* Clears corresponding bits in the INTC_FRC register, bit 2 */ byte CLR3 :1; /* Clears corresponding bits in the INTC_FRC register, bit 3 */ byte CLR4 :1; /* Clears corresponding bits in the INTC_FRC register, bit 4 */ byte CLR5 :1; /* Clears corresponding bits in the INTC_FRC register, bit 5 */ byte :1; byte :1; } Bits; struct { byte grpCLR :6; byte :1; byte :1; } MergedBits; } INTC_CFRCSTR; extern volatile INTC_CFRCSTR _INTC_CFRC @0xFFFFFFDF; #define INTC_CFRC _INTC_CFRC.Byte #define INTC_CFRC_CLR0 _INTC_CFRC.Bits.CLR0 #define INTC_CFRC_CLR1 _INTC_CFRC.Bits.CLR1 #define INTC_CFRC_CLR2 _INTC_CFRC.Bits.CLR2 #define INTC_CFRC_CLR3 _INTC_CFRC.Bits.CLR3 #define INTC_CFRC_CLR4 _INTC_CFRC.Bits.CLR4 #define INTC_CFRC_CLR5 _INTC_CFRC.Bits.CLR5 #define INTC_CFRC_CLR _INTC_CFRC.MergedBits.grpCLR #define INTC_CFRC_CLR0_MASK 1 #define INTC_CFRC_CLR1_MASK 2 #define INTC_CFRC_CLR2_MASK 4 #define INTC_CFRC_CLR3_MASK 8 #define INTC_CFRC_CLR4_MASK 16 #define INTC_CFRC_CLR5_MASK 32 #define INTC_CFRC_CLR_MASK 63 #define INTC_CFRC_CLR_BITNUM 0 /*** INTC_SWIACK - INTC Software IACK Register; 0xFFFFFFE0 ***/ typedef union { byte Byte; struct { byte VECN0 :1; /* Vector number, bit 0 */ byte VECN1 :1; /* Vector number, bit 1 */ byte VECN2 :1; /* Vector number, bit 2 */ byte VECN3 :1; /* Vector number, bit 3 */ byte VECN4 :1; /* Vector number, bit 4 */ byte VECN5 :1; /* Vector number, bit 5 */ byte VECN6 :1; /* Vector number, bit 6 */ byte :1; } Bits; struct { byte grpVECN :7; byte :1; } MergedBits; } INTC_SWIACKSTR; extern volatile INTC_SWIACKSTR _INTC_SWIACK @0xFFFFFFE0; #define INTC_SWIACK _INTC_SWIACK.Byte #define INTC_SWIACK_VECN0 _INTC_SWIACK.Bits.VECN0 #define INTC_SWIACK_VECN1 _INTC_SWIACK.Bits.VECN1 #define INTC_SWIACK_VECN2 _INTC_SWIACK.Bits.VECN2 #define INTC_SWIACK_VECN3 _INTC_SWIACK.Bits.VECN3 #define INTC_SWIACK_VECN4 _INTC_SWIACK.Bits.VECN4 #define INTC_SWIACK_VECN5 _INTC_SWIACK.Bits.VECN5 #define INTC_SWIACK_VECN6 _INTC_SWIACK.Bits.VECN6 #define INTC_SWIACK_VECN _INTC_SWIACK.MergedBits.grpVECN #define INTC_SWIACK_VECN0_MASK 1 #define INTC_SWIACK_VECN1_MASK 2 #define INTC_SWIACK_VECN2_MASK 4 #define INTC_SWIACK_VECN3_MASK 8 #define INTC_SWIACK_VECN4_MASK 16 #define INTC_SWIACK_VECN5_MASK 32 #define INTC_SWIACK_VECN6_MASK 64 #define INTC_SWIACK_VECN_MASK 127 #define INTC_SWIACK_VECN_BITNUM 0 /*** INTC_LVL1IACK - INTC Level 1 IACK Register; 0xFFFFFFE4 ***/ typedef union { byte Byte; struct { byte VECN0 :1; /* Vector number, bit 0 */ byte VECN1 :1; /* Vector number, bit 1 */ byte VECN2 :1; /* Vector number, bit 2 */ byte VECN3 :1; /* Vector number, bit 3 */ byte VECN4 :1; /* Vector number, bit 4 */ byte VECN5 :1; /* Vector number, bit 5 */ byte VECN6 :1; /* Vector number, bit 6 */ byte :1; } Bits; struct { byte grpVECN :7; byte :1; } MergedBits; } INTC_LVL1IACKSTR; extern volatile INTC_LVL1IACKSTR _INTC_LVL1IACK @0xFFFFFFE4; #define INTC_LVL1IACK _INTC_LVL1IACK.Byte #define INTC_LVL1IACK_VECN0 _INTC_LVL1IACK.Bits.VECN0 #define INTC_LVL1IACK_VECN1 _INTC_LVL1IACK.Bits.VECN1 #define INTC_LVL1IACK_VECN2 _INTC_LVL1IACK.Bits.VECN2 #define INTC_LVL1IACK_VECN3 _INTC_LVL1IACK.Bits.VECN3 #define INTC_LVL1IACK_VECN4 _INTC_LVL1IACK.Bits.VECN4 #define INTC_LVL1IACK_VECN5 _INTC_LVL1IACK.Bits.VECN5 #define INTC_LVL1IACK_VECN6 _INTC_LVL1IACK.Bits.VECN6 #define INTC_LVL1IACK_VECN _INTC_LVL1IACK.MergedBits.grpVECN #define INTC_LVL1IACK_VECN0_MASK 1 #define INTC_LVL1IACK_VECN1_MASK 2 #define INTC_LVL1IACK_VECN2_MASK 4 #define INTC_LVL1IACK_VECN3_MASK 8 #define INTC_LVL1IACK_VECN4_MASK 16 #define INTC_LVL1IACK_VECN5_MASK 32 #define INTC_LVL1IACK_VECN6_MASK 64 #define INTC_LVL1IACK_VECN_MASK 127 #define INTC_LVL1IACK_VECN_BITNUM 0 /*** INTC_LVL2IACK - INTC Level 2 IACK Register; 0xFFFFFFE8 ***/ typedef union { byte Byte; struct { byte VECN0 :1; /* Vector number, bit 0 */ byte VECN1 :1; /* Vector number, bit 1 */ byte VECN2 :1; /* Vector number, bit 2 */ byte VECN3 :1; /* Vector number, bit 3 */ byte VECN4 :1; /* Vector number, bit 4 */ byte VECN5 :1; /* Vector number, bit 5 */ byte VECN6 :1; /* Vector number, bit 6 */ byte :1; } Bits; struct { byte grpVECN :7; byte :1; } MergedBits; } INTC_LVL2IACKSTR; extern volatile INTC_LVL2IACKSTR _INTC_LVL2IACK @0xFFFFFFE8; #define INTC_LVL2IACK _INTC_LVL2IACK.Byte #define INTC_LVL2IACK_VECN0 _INTC_LVL2IACK.Bits.VECN0 #define INTC_LVL2IACK_VECN1 _INTC_LVL2IACK.Bits.VECN1 #define INTC_LVL2IACK_VECN2 _INTC_LVL2IACK.Bits.VECN2 #define INTC_LVL2IACK_VECN3 _INTC_LVL2IACK.Bits.VECN3 #define INTC_LVL2IACK_VECN4 _INTC_LVL2IACK.Bits.VECN4 #define INTC_LVL2IACK_VECN5 _INTC_LVL2IACK.Bits.VECN5 #define INTC_LVL2IACK_VECN6 _INTC_LVL2IACK.Bits.VECN6 #define INTC_LVL2IACK_VECN _INTC_LVL2IACK.MergedBits.grpVECN #define INTC_LVL2IACK_VECN0_MASK 1 #define INTC_LVL2IACK_VECN1_MASK 2 #define INTC_LVL2IACK_VECN2_MASK 4 #define INTC_LVL2IACK_VECN3_MASK 8 #define INTC_LVL2IACK_VECN4_MASK 16 #define INTC_LVL2IACK_VECN5_MASK 32 #define INTC_LVL2IACK_VECN6_MASK 64 #define INTC_LVL2IACK_VECN_MASK 127 #define INTC_LVL2IACK_VECN_BITNUM 0 /*** INTC_LVL3IACK - INTC Level 3 IACK Register; 0xFFFFFFEC ***/ typedef union { byte Byte; struct { byte VECN0 :1; /* Vector number, bit 0 */ byte VECN1 :1; /* Vector number, bit 1 */ byte VECN2 :1; /* Vector number, bit 2 */ byte VECN3 :1; /* Vector number, bit 3 */ byte VECN4 :1; /* Vector number, bit 4 */ byte VECN5 :1; /* Vector number, bit 5 */ byte VECN6 :1; /* Vector number, bit 6 */ byte :1; } Bits; struct { byte grpVECN :7; byte :1; } MergedBits; } INTC_LVL3IACKSTR; extern volatile INTC_LVL3IACKSTR _INTC_LVL3IACK @0xFFFFFFEC; #define INTC_LVL3IACK _INTC_LVL3IACK.Byte #define INTC_LVL3IACK_VECN0 _INTC_LVL3IACK.Bits.VECN0 #define INTC_LVL3IACK_VECN1 _INTC_LVL3IACK.Bits.VECN1 #define INTC_LVL3IACK_VECN2 _INTC_LVL3IACK.Bits.VECN2 #define INTC_LVL3IACK_VECN3 _INTC_LVL3IACK.Bits.VECN3 #define INTC_LVL3IACK_VECN4 _INTC_LVL3IACK.Bits.VECN4 #define INTC_LVL3IACK_VECN5 _INTC_LVL3IACK.Bits.VECN5 #define INTC_LVL3IACK_VECN6 _INTC_LVL3IACK.Bits.VECN6 #define INTC_LVL3IACK_VECN _INTC_LVL3IACK.MergedBits.grpVECN #define INTC_LVL3IACK_VECN0_MASK 1 #define INTC_LVL3IACK_VECN1_MASK 2 #define INTC_LVL3IACK_VECN2_MASK 4 #define INTC_LVL3IACK_VECN3_MASK 8 #define INTC_LVL3IACK_VECN4_MASK 16 #define INTC_LVL3IACK_VECN5_MASK 32 #define INTC_LVL3IACK_VECN6_MASK 64 #define INTC_LVL3IACK_VECN_MASK 127 #define INTC_LVL3IACK_VECN_BITNUM 0 /*** INTC_LVL4IACK - INTC Level 4 IACK Register; 0xFFFFFFF0 ***/ typedef union { byte Byte; struct { byte VECN0 :1; /* Vector number, bit 0 */ byte VECN1 :1; /* Vector number, bit 1 */ byte VECN2 :1; /* Vector number, bit 2 */ byte VECN3 :1; /* Vector number, bit 3 */ byte VECN4 :1; /* Vector number, bit 4 */ byte VECN5 :1; /* Vector number, bit 5 */ byte VECN6 :1; /* Vector number, bit 6 */ byte :1; } Bits; struct { byte grpVECN :7; byte :1; } MergedBits; } INTC_LVL4IACKSTR; extern volatile INTC_LVL4IACKSTR _INTC_LVL4IACK @0xFFFFFFF0; #define INTC_LVL4IACK _INTC_LVL4IACK.Byte #define INTC_LVL4IACK_VECN0 _INTC_LVL4IACK.Bits.VECN0 #define INTC_LVL4IACK_VECN1 _INTC_LVL4IACK.Bits.VECN1 #define INTC_LVL4IACK_VECN2 _INTC_LVL4IACK.Bits.VECN2 #define INTC_LVL4IACK_VECN3 _INTC_LVL4IACK.Bits.VECN3 #define INTC_LVL4IACK_VECN4 _INTC_LVL4IACK.Bits.VECN4 #define INTC_LVL4IACK_VECN5 _INTC_LVL4IACK.Bits.VECN5 #define INTC_LVL4IACK_VECN6 _INTC_LVL4IACK.Bits.VECN6 #define INTC_LVL4IACK_VECN _INTC_LVL4IACK.MergedBits.grpVECN #define INTC_LVL4IACK_VECN0_MASK 1 #define INTC_LVL4IACK_VECN1_MASK 2 #define INTC_LVL4IACK_VECN2_MASK 4 #define INTC_LVL4IACK_VECN3_MASK 8 #define INTC_LVL4IACK_VECN4_MASK 16 #define INTC_LVL4IACK_VECN5_MASK 32 #define INTC_LVL4IACK_VECN6_MASK 64 #define INTC_LVL4IACK_VECN_MASK 127 #define INTC_LVL4IACK_VECN_BITNUM 0 /*** INTC_LVL5IACK - INTC Level 5 IACK Register; 0xFFFFFFF4 ***/ typedef union { byte Byte; struct { byte VECN0 :1; /* Vector number, bit 0 */ byte VECN1 :1; /* Vector number, bit 1 */ byte VECN2 :1; /* Vector number, bit 2 */ byte VECN3 :1; /* Vector number, bit 3 */ byte VECN4 :1; /* Vector number, bit 4 */ byte VECN5 :1; /* Vector number, bit 5 */ byte VECN6 :1; /* Vector number, bit 6 */ byte :1; } Bits; struct { byte grpVECN :7; byte :1; } MergedBits; } INTC_LVL5IACKSTR; extern volatile INTC_LVL5IACKSTR _INTC_LVL5IACK @0xFFFFFFF4; #define INTC_LVL5IACK _INTC_LVL5IACK.Byte #define INTC_LVL5IACK_VECN0 _INTC_LVL5IACK.Bits.VECN0 #define INTC_LVL5IACK_VECN1 _INTC_LVL5IACK.Bits.VECN1 #define INTC_LVL5IACK_VECN2 _INTC_LVL5IACK.Bits.VECN2 #define INTC_LVL5IACK_VECN3 _INTC_LVL5IACK.Bits.VECN3 #define INTC_LVL5IACK_VECN4 _INTC_LVL5IACK.Bits.VECN4 #define INTC_LVL5IACK_VECN5 _INTC_LVL5IACK.Bits.VECN5 #define INTC_LVL5IACK_VECN6 _INTC_LVL5IACK.Bits.VECN6 #define INTC_LVL5IACK_VECN _INTC_LVL5IACK.MergedBits.grpVECN #define INTC_LVL5IACK_VECN0_MASK 1 #define INTC_LVL5IACK_VECN1_MASK 2 #define INTC_LVL5IACK_VECN2_MASK 4 #define INTC_LVL5IACK_VECN3_MASK 8 #define INTC_LVL5IACK_VECN4_MASK 16 #define INTC_LVL5IACK_VECN5_MASK 32 #define INTC_LVL5IACK_VECN6_MASK 64 #define INTC_LVL5IACK_VECN_MASK 127 #define INTC_LVL5IACK_VECN_BITNUM 0 /*** INTC_LVL6IACK - INTC Level 6 IACK Register; 0xFFFFFFF8 ***/ typedef union { byte Byte; struct { byte VECN0 :1; /* Vector number, bit 0 */ byte VECN1 :1; /* Vector number, bit 1 */ byte VECN2 :1; /* Vector number, bit 2 */ byte VECN3 :1; /* Vector number, bit 3 */ byte VECN4 :1; /* Vector number, bit 4 */ byte VECN5 :1; /* Vector number, bit 5 */ byte VECN6 :1; /* Vector number, bit 6 */ byte :1; } Bits; struct { byte grpVECN :7; byte :1; } MergedBits; } INTC_LVL6IACKSTR; extern volatile INTC_LVL6IACKSTR _INTC_LVL6IACK @0xFFFFFFF8; #define INTC_LVL6IACK _INTC_LVL6IACK.Byte #define INTC_LVL6IACK_VECN0 _INTC_LVL6IACK.Bits.VECN0 #define INTC_LVL6IACK_VECN1 _INTC_LVL6IACK.Bits.VECN1 #define INTC_LVL6IACK_VECN2 _INTC_LVL6IACK.Bits.VECN2 #define INTC_LVL6IACK_VECN3 _INTC_LVL6IACK.Bits.VECN3 #define INTC_LVL6IACK_VECN4 _INTC_LVL6IACK.Bits.VECN4 #define INTC_LVL6IACK_VECN5 _INTC_LVL6IACK.Bits.VECN5 #define INTC_LVL6IACK_VECN6 _INTC_LVL6IACK.Bits.VECN6 #define INTC_LVL6IACK_VECN _INTC_LVL6IACK.MergedBits.grpVECN #define INTC_LVL6IACK_VECN0_MASK 1 #define INTC_LVL6IACK_VECN1_MASK 2 #define INTC_LVL6IACK_VECN2_MASK 4 #define INTC_LVL6IACK_VECN3_MASK 8 #define INTC_LVL6IACK_VECN4_MASK 16 #define INTC_LVL6IACK_VECN5_MASK 32 #define INTC_LVL6IACK_VECN6_MASK 64 #define INTC_LVL6IACK_VECN_MASK 127 #define INTC_LVL6IACK_VECN_BITNUM 0 /*** INTC_LVL7IACK - INTC Level 7 IACK Register; 0xFFFFFFFC ***/ typedef union { byte Byte; struct { byte VECN0 :1; /* Vector number, bit 0 */ byte VECN1 :1; /* Vector number, bit 1 */ byte VECN2 :1; /* Vector number, bit 2 */ byte VECN3 :1; /* Vector number, bit 3 */ byte VECN4 :1; /* Vector number, bit 4 */ byte VECN5 :1; /* Vector number, bit 5 */ byte VECN6 :1; /* Vector number, bit 6 */ byte :1; } Bits; struct { byte grpVECN :7; byte :1; } MergedBits; } INTC_LVL7IACKSTR; extern volatile INTC_LVL7IACKSTR _INTC_LVL7IACK @0xFFFFFFFC; #define INTC_LVL7IACK _INTC_LVL7IACK.Byte #define INTC_LVL7IACK_VECN0 _INTC_LVL7IACK.Bits.VECN0 #define INTC_LVL7IACK_VECN1 _INTC_LVL7IACK.Bits.VECN1 #define INTC_LVL7IACK_VECN2 _INTC_LVL7IACK.Bits.VECN2 #define INTC_LVL7IACK_VECN3 _INTC_LVL7IACK.Bits.VECN3 #define INTC_LVL7IACK_VECN4 _INTC_LVL7IACK.Bits.VECN4 #define INTC_LVL7IACK_VECN5 _INTC_LVL7IACK.Bits.VECN5 #define INTC_LVL7IACK_VECN6 _INTC_LVL7IACK.Bits.VECN6 #define INTC_LVL7IACK_VECN _INTC_LVL7IACK.MergedBits.grpVECN #define INTC_LVL7IACK_VECN0_MASK 1 #define INTC_LVL7IACK_VECN1_MASK 2 #define INTC_LVL7IACK_VECN2_MASK 4 #define INTC_LVL7IACK_VECN3_MASK 8 #define INTC_LVL7IACK_VECN4_MASK 16 #define INTC_LVL7IACK_VECN5_MASK 32 #define INTC_LVL7IACK_VECN6_MASK 64 #define INTC_LVL7IACK_VECN_MASK 127 #define INTC_LVL7IACK_VECN_BITNUM 0 /*** IRTC RAM ***/ /*** It is not recommended to mix usage of the StandbyRAM array and variables allocated into the appropriate section defined in the linker file at the same time. ***/ extern volatile byte StandbyRAM[32] @0xFFFF8680; /***********************************************/ /** D E P R E C I A T E D S Y M B O L S **/ /***********************************************/ /* --------------------------------------------------------------------------- */ /* The following symbols were removed, because they were invalid or irrelevant */ /* --------------------------------------------------------------------------- */ /* **** 7.4.2009 9:04:14 */ #define PTAPF1_A This_symb_has_been_depreciated #define PTAPF2_A This_symb_has_been_depreciated #define PTBPF1_B This_symb_has_been_depreciated #define PTBPF2_B This_symb_has_been_depreciated #define PTCPF1_C This_symb_has_been_depreciated #define PTCPF2_C This_symb_has_been_depreciated #define PTDPF1_D This_symb_has_been_depreciated #define PTDPF2_D This_symb_has_been_depreciated #define PTEPF1_E This_symb_has_been_depreciated #define PTEPF2_E This_symb_has_been_depreciated #define PTFPF1_F This_symb_has_been_depreciated #define PTFPF2_F This_symb_has_been_depreciated #define SIMIPS1_MTIM This_symb_has_been_depreciated #define SIMIPS2_MTBASE This_symb_has_been_depreciated #define IRTC_UP_CNTR_H_BYTE This_symb_has_been_depreciated #define IRTC_UP_CNTR_L_BYTE This_symb_has_been_depreciated /* **** 28.5.2009 13:18:25 */ #define VectorNumber_VReserved67 VectorNumber_Vpdb_err #define VReserved67 Vpdb_err #define PDBSCR PDBSC #define PDBSCR_EN PDBSC_EN #define PDBSCR_IE PDBSC_IE #define PDBSCR_TRIGSEL0 PDBSC_TRIGSEL0 #define PDBSCR_TRIGSEL1 PDBSC_TRIGSEL1 #define PDBSCR_TRIGSEL2 PDBSC_TRIGSEL2 #define PDBSCR_SWTRIG PDBSC_SWTRIG #define PDBSCR_CONT PDBSC_CONT #define PDBSCR_IF PDBSC_IF #define PDBSCR_PRESCALER0 PDBSC_PRESCALER0 #define PDBSCR_PRESCALER1 PDBSC_PRESCALER1 #define PDBSCR_PRESCALER2 PDBSC_PRESCALER2 #define PDBSCR_TRIGSEL PDBSC_TRIGSEL #define PDBSCR_PRESCALER PDBSC_PRESCALER #define PDBSCR_EN_MASK PDBSC_EN_MASK #define PDBSCR_IE_MASK PDBSC_IE_MASK #define PDBSCR_TRIGSEL0_MASK PDBSC_TRIGSEL0_MASK #define PDBSCR_TRIGSEL1_MASK PDBSC_TRIGSEL1_MASK #define PDBSCR_TRIGSEL2_MASK PDBSC_TRIGSEL2_MASK #define PDBSCR_SWTRIG_MASK PDBSC_SWTRIG_MASK #define PDBSCR_CONT_MASK PDBSC_CONT_MASK #define PDBSCR_IF_MASK PDBSC_IF_MASK #define PDBSCR_PRESCALER0_MASK PDBSC_PRESCALER0_MASK #define PDBSCR_PRESCALER1_MASK PDBSC_PRESCALER1_MASK #define PDBSCR_PRESCALER2_MASK PDBSC_PRESCALER2_MASK #define PDBSCR_TRIGSEL_MASK PDBSC_TRIGSEL_MASK #define PDBSCR_TRIGSEL_BITNUM PDBSC_TRIGSEL_BITNUM #define PDBSCR_PRESCALER_MASK PDBSC_PRESCALER_MASK #define PDBSCR_PRESCALER_BITNUM PDBSC_PRESCALER_BITNUM #define PDBCOUNT PDBCNT #define PDBCOUNT_COUNT0 PDBCNT_COUNT0 #define PDBCOUNT_COUNT1 PDBCNT_COUNT1 #define PDBCOUNT_COUNT2 PDBCNT_COUNT2 #define PDBCOUNT_COUNT3 PDBCNT_COUNT3 #define PDBCOUNT_COUNT4 PDBCNT_COUNT4 #define PDBCOUNT_COUNT5 PDBCNT_COUNT5 #define PDBCOUNT_COUNT6 PDBCNT_COUNT6 #define PDBCOUNT_COUNT7 PDBCNT_COUNT7 #define PDBCOUNT_COUNT8 PDBCNT_COUNT8 #define PDBCOUNT_COUNT9 PDBCNT_COUNT9 #define PDBCOUNT_COUNT10 PDBCNT_COUNT10 #define PDBCOUNT_COUNT11 PDBCNT_COUNT11 #define PDBCOUNT_COUNT12 PDBCNT_COUNT12 #define PDBCOUNT_COUNT13 PDBCNT_COUNT13 #define PDBCOUNT_COUNT14 PDBCNT_COUNT14 #define PDBCOUNT_COUNT15 PDBCNT_COUNT15 #define PDBCOUNT_COUNT0_MASK PDBCNT_COUNT0_MASK #define PDBCOUNT_COUNT1_MASK PDBCNT_COUNT1_MASK #define PDBCOUNT_COUNT2_MASK PDBCNT_COUNT2_MASK #define PDBCOUNT_COUNT3_MASK PDBCNT_COUNT3_MASK #define PDBCOUNT_COUNT4_MASK PDBCNT_COUNT4_MASK #define PDBCOUNT_COUNT5_MASK PDBCNT_COUNT5_MASK #define PDBCOUNT_COUNT6_MASK PDBCNT_COUNT6_MASK #define PDBCOUNT_COUNT7_MASK PDBCNT_COUNT7_MASK #define PDBCOUNT_COUNT8_MASK PDBCNT_COUNT8_MASK #define PDBCOUNT_COUNT9_MASK PDBCNT_COUNT9_MASK #define PDBCOUNT_COUNT10_MASK PDBCNT_COUNT10_MASK #define PDBCOUNT_COUNT11_MASK PDBCNT_COUNT11_MASK #define PDBCOUNT_COUNT12_MASK PDBCNT_COUNT12_MASK #define PDBCOUNT_COUNT13_MASK PDBCNT_COUNT13_MASK #define PDBCOUNT_COUNT14_MASK PDBCNT_COUNT14_MASK #define PDBCOUNT_COUNT15_MASK PDBCNT_COUNT15_MASK #define PDBIDELAY PDBIDLY #define PDBIDELAY_IDELAY0 PDBIDLY_IDELAY0 #define PDBIDELAY_IDELAY1 PDBIDLY_IDELAY1 #define PDBIDELAY_IDELAY2 PDBIDLY_IDELAY2 #define PDBIDELAY_IDELAY3 PDBIDLY_IDELAY3 #define PDBIDELAY_IDELAY4 PDBIDLY_IDELAY4 #define PDBIDELAY_IDELAY5 PDBIDLY_IDELAY5 #define PDBIDELAY_IDELAY6 PDBIDLY_IDELAY6 #define PDBIDELAY_IDELAY7 PDBIDLY_IDELAY7 #define PDBIDELAY_IDELAY8 PDBIDLY_IDELAY8 #define PDBIDELAY_IDELAY9 PDBIDLY_IDELAY9 #define PDBIDELAY_IDELAY10 PDBIDLY_IDELAY10 #define PDBIDELAY_IDELAY11 PDBIDLY_IDELAY11 #define PDBIDELAY_IDELAY12 PDBIDLY_IDELAY12 #define PDBIDELAY_IDELAY13 PDBIDLY_IDELAY13 #define PDBIDELAY_IDELAY14 PDBIDLY_IDELAY14 #define PDBIDELAY_IDELAY15 PDBIDLY_IDELAY15 #define PDBIDELAY_IDELAY0_MASK PDBIDLY_IDELAY0_MASK #define PDBIDELAY_IDELAY1_MASK PDBIDLY_IDELAY1_MASK #define PDBIDELAY_IDELAY2_MASK PDBIDLY_IDELAY2_MASK #define PDBIDELAY_IDELAY3_MASK PDBIDLY_IDELAY3_MASK #define PDBIDELAY_IDELAY4_MASK PDBIDLY_IDELAY4_MASK #define PDBIDELAY_IDELAY5_MASK PDBIDLY_IDELAY5_MASK #define PDBIDELAY_IDELAY6_MASK PDBIDLY_IDELAY6_MASK #define PDBIDELAY_IDELAY7_MASK PDBIDLY_IDELAY7_MASK #define PDBIDELAY_IDELAY8_MASK PDBIDLY_IDELAY8_MASK #define PDBIDELAY_IDELAY9_MASK PDBIDLY_IDELAY9_MASK #define PDBIDELAY_IDELAY10_MASK PDBIDLY_IDELAY10_MASK #define PDBIDELAY_IDELAY11_MASK PDBIDLY_IDELAY11_MASK #define PDBIDELAY_IDELAY12_MASK PDBIDLY_IDELAY12_MASK #define PDBIDELAY_IDELAY13_MASK PDBIDLY_IDELAY13_MASK #define PDBIDELAY_IDELAY14_MASK PDBIDLY_IDELAY14_MASK #define PDBIDELAY_IDELAY15_MASK PDBIDLY_IDELAY15_MASK #define PDBCH1DELA PDBCH1DLYA #define PDBCH1DELA_DELAY0 PDBCH1DLYA_DELAYA0 #define PDBCH1DELA_DELAY1 PDBCH1DLYA_DELAYA1 #define PDBCH1DELA_DELAY2 PDBCH1DLYA_DELAYA2 #define PDBCH1DELA_DELAY3 PDBCH1DLYA_DELAYA3 #define PDBCH1DELA_DELAY4 PDBCH1DLYA_DELAYA4 #define PDBCH1DELA_DELAY5 PDBCH1DLYA_DELAYA5 #define PDBCH1DELA_DELAY6 PDBCH1DLYA_DELAYA6 #define PDBCH1DELA_DELAY7 PDBCH1DLYA_DELAYA7 #define PDBCH1DELA_DELAY8 PDBCH1DLYA_DELAYA8 #define PDBCH1DELA_DELAY9 PDBCH1DLYA_DELAYA9 #define PDBCH1DELA_DELAY10 PDBCH1DLYA_DELAYA10 #define PDBCH1DELA_DELAY11 PDBCH1DLYA_DELAYA11 #define PDBCH1DELA_DELAY12 PDBCH1DLYA_DELAYA12 #define PDBCH1DELA_DELAY13 PDBCH1DLYA_DELAYA13 #define PDBCH1DELA_DELAY14 PDBCH1DLYA_DELAYA14 #define PDBCH1DELA_DELAY15 PDBCH1DLYA_DELAYA15 #define PDBCH1DELA_DELAY0_MASK PDBCH1DLYA_DELAYA0_MASK #define PDBCH1DELA_DELAY1_MASK PDBCH1DLYA_DELAYA1_MASK #define PDBCH1DELA_DELAY2_MASK PDBCH1DLYA_DELAYA2_MASK #define PDBCH1DELA_DELAY3_MASK PDBCH1DLYA_DELAYA3_MASK #define PDBCH1DELA_DELAY4_MASK PDBCH1DLYA_DELAYA4_MASK #define PDBCH1DELA_DELAY5_MASK PDBCH1DLYA_DELAYA5_MASK #define PDBCH1DELA_DELAY6_MASK PDBCH1DLYA_DELAYA6_MASK #define PDBCH1DELA_DELAY7_MASK PDBCH1DLYA_DELAYA7_MASK #define PDBCH1DELA_DELAY8_MASK PDBCH1DLYA_DELAYA8_MASK #define PDBCH1DELA_DELAY9_MASK PDBCH1DLYA_DELAYA9_MASK #define PDBCH1DELA_DELAY10_MASK PDBCH1DLYA_DELAYA10_MASK #define PDBCH1DELA_DELAY11_MASK PDBCH1DLYA_DELAYA11_MASK #define PDBCH1DELA_DELAY12_MASK PDBCH1DLYA_DELAYA12_MASK #define PDBCH1DELA_DELAY13_MASK PDBCH1DLYA_DELAYA13_MASK #define PDBCH1DELA_DELAY14_MASK PDBCH1DLYA_DELAYA14_MASK #define PDBCH1DELA_DELAY15_MASK PDBCH1DLYA_DELAYA15_MASK #define PDBCH1DELB PDBCH1DLYB #define PDBCH1DELB_DELAY0 PDBCH1DLYB_DELAYB0 #define PDBCH1DELB_DELAY1 PDBCH1DLYB_DELAYB1 #define PDBCH1DELB_DELAY2 PDBCH1DLYB_DELAYB2 #define PDBCH1DELB_DELAY3 PDBCH1DLYB_DELAYB3 #define PDBCH1DELB_DELAY4 PDBCH1DLYB_DELAYB4 #define PDBCH1DELB_DELAY5 PDBCH1DLYB_DELAYB5 #define PDBCH1DELB_DELAY6 PDBCH1DLYB_DELAYB6 #define PDBCH1DELB_DELAY7 PDBCH1DLYB_DELAYB7 #define PDBCH1DELB_DELAY8 PDBCH1DLYB_DELAYB8 #define PDBCH1DELB_DELAY9 PDBCH1DLYB_DELAYB9 #define PDBCH1DELB_DELAY10 PDBCH1DLYB_DELAYB10 #define PDBCH1DELB_DELAY11 PDBCH1DLYB_DELAYB11 #define PDBCH1DELB_DELAY12 PDBCH1DLYB_DELAYB12 #define PDBCH1DELB_DELAY13 PDBCH1DLYB_DELAYB13 #define PDBCH1DELB_DELAY14 PDBCH1DLYB_DELAYB14 #define PDBCH1DELB_DELAY15 PDBCH1DLYB_DELAYB15 #define PDBCH1DELB_DELAY0_MASK PDBCH1DLYB_DELAYB0_MASK #define PDBCH1DELB_DELAY1_MASK PDBCH1DLYB_DELAYB1_MASK #define PDBCH1DELB_DELAY2_MASK PDBCH1DLYB_DELAYB2_MASK #define PDBCH1DELB_DELAY3_MASK PDBCH1DLYB_DELAYB3_MASK #define PDBCH1DELB_DELAY4_MASK PDBCH1DLYB_DELAYB4_MASK #define PDBCH1DELB_DELAY5_MASK PDBCH1DLYB_DELAYB5_MASK #define PDBCH1DELB_DELAY6_MASK PDBCH1DLYB_DELAYB6_MASK #define PDBCH1DELB_DELAY7_MASK PDBCH1DLYB_DELAYB7_MASK #define PDBCH1DELB_DELAY8_MASK PDBCH1DLYB_DELAYB8_MASK #define PDBCH1DELB_DELAY9_MASK PDBCH1DLYB_DELAYB9_MASK #define PDBCH1DELB_DELAY10_MASK PDBCH1DLYB_DELAYB10_MASK #define PDBCH1DELB_DELAY11_MASK PDBCH1DLYB_DELAYB11_MASK #define PDBCH1DELB_DELAY12_MASK PDBCH1DLYB_DELAYB12_MASK #define PDBCH1DELB_DELAY13_MASK PDBCH1DLYB_DELAYB13_MASK #define PDBCH1DELB_DELAY14_MASK PDBCH1DLYB_DELAYB14_MASK #define PDBCH1DELB_DELAY15_MASK PDBCH1DLYB_DELAYB15_MASK #define PDBCH2DELA PDBCH2DLYA #define PDBCH2DELA_DELAY0 PDBCH2DLYA_DELAYA0 #define PDBCH2DELA_DELAY1 PDBCH2DLYA_DELAYA1 #define PDBCH2DELA_DELAY2 PDBCH2DLYA_DELAYA2 #define PDBCH2DELA_DELAY3 PDBCH2DLYA_DELAYA3 #define PDBCH2DELA_DELAY4 PDBCH2DLYA_DELAYA4 #define PDBCH2DELA_DELAY5 PDBCH2DLYA_DELAYA5 #define PDBCH2DELA_DELAY6 PDBCH2DLYA_DELAYA6 #define PDBCH2DELA_DELAY7 PDBCH2DLYA_DELAYA7 #define PDBCH2DELA_DELAY8 PDBCH2DLYA_DELAYA8 #define PDBCH2DELA_DELAY9 PDBCH2DLYA_DELAYA9 #define PDBCH2DELA_DELAY10 PDBCH2DLYA_DELAYA10 #define PDBCH2DELA_DELAY11 PDBCH2DLYA_DELAYA11 #define PDBCH2DELA_DELAY12 PDBCH2DLYA_DELAYA12 #define PDBCH2DELA_DELAY13 PDBCH2DLYA_DELAYA13 #define PDBCH2DELA_DELAY14 PDBCH2DLYA_DELAYA14 #define PDBCH2DELA_DELAY15 PDBCH2DLYA_DELAYA15 #define PDBCH2DELA_DELAY0_MASK PDBCH2DLYA_DELAYA0_MASK #define PDBCH2DELA_DELAY1_MASK PDBCH2DLYA_DELAYA1_MASK #define PDBCH2DELA_DELAY2_MASK PDBCH2DLYA_DELAYA2_MASK #define PDBCH2DELA_DELAY3_MASK PDBCH2DLYA_DELAYA3_MASK #define PDBCH2DELA_DELAY4_MASK PDBCH2DLYA_DELAYA4_MASK #define PDBCH2DELA_DELAY5_MASK PDBCH2DLYA_DELAYA5_MASK #define PDBCH2DELA_DELAY6_MASK PDBCH2DLYA_DELAYA6_MASK #define PDBCH2DELA_DELAY7_MASK PDBCH2DLYA_DELAYA7_MASK #define PDBCH2DELA_DELAY8_MASK PDBCH2DLYA_DELAYA8_MASK #define PDBCH2DELA_DELAY9_MASK PDBCH2DLYA_DELAYA9_MASK #define PDBCH2DELA_DELAY10_MASK PDBCH2DLYA_DELAYA10_MASK #define PDBCH2DELA_DELAY11_MASK PDBCH2DLYA_DELAYA11_MASK #define PDBCH2DELA_DELAY12_MASK PDBCH2DLYA_DELAYA12_MASK #define PDBCH2DELA_DELAY13_MASK PDBCH2DLYA_DELAYA13_MASK #define PDBCH2DELA_DELAY14_MASK PDBCH2DLYA_DELAYA14_MASK #define PDBCH2DELA_DELAY15_MASK PDBCH2DLYA_DELAYA15_MASK #define PDBCH2DELB PDBCH2DLYB #define PDBCH2DELB_DELAY0 PDBCH2DLYB_DELAYB0 #define PDBCH2DELB_DELAY1 PDBCH2DLYB_DELAYB1 #define PDBCH2DELB_DELAY2 PDBCH2DLYB_DELAYB2 #define PDBCH2DELB_DELAY3 PDBCH2DLYB_DELAYB3 #define PDBCH2DELB_DELAY4 PDBCH2DLYB_DELAYB4 #define PDBCH2DELB_DELAY5 PDBCH2DLYB_DELAYB5 #define PDBCH2DELB_DELAY6 PDBCH2DLYB_DELAYB6 #define PDBCH2DELB_DELAY7 PDBCH2DLYB_DELAYB7 #define PDBCH2DELB_DELAY8 PDBCH2DLYB_DELAYB8 #define PDBCH2DELB_DELAY9 PDBCH2DLYB_DELAYB9 #define PDBCH2DELB_DELAY10 PDBCH2DLYB_DELAYB10 #define PDBCH2DELB_DELAY11 PDBCH2DLYB_DELAYB11 #define PDBCH2DELB_DELAY12 PDBCH2DLYB_DELAYB12 #define PDBCH2DELB_DELAY13 PDBCH2DLYB_DELAYB13 #define PDBCH2DELB_DELAY14 PDBCH2DLYB_DELAYB14 #define PDBCH2DELB_DELAY15 PDBCH2DLYB_DELAYB15 #define PDBCH2DELB_DELAY0_MASK PDBCH2DLYB_DELAYB0_MASK #define PDBCH2DELB_DELAY1_MASK PDBCH2DLYB_DELAYB1_MASK #define PDBCH2DELB_DELAY2_MASK PDBCH2DLYB_DELAYB2_MASK #define PDBCH2DELB_DELAY3_MASK PDBCH2DLYB_DELAYB3_MASK #define PDBCH2DELB_DELAY4_MASK PDBCH2DLYB_DELAYB4_MASK #define PDBCH2DELB_DELAY5_MASK PDBCH2DLYB_DELAYB5_MASK #define PDBCH2DELB_DELAY6_MASK PDBCH2DLYB_DELAYB6_MASK #define PDBCH2DELB_DELAY7_MASK PDBCH2DLYB_DELAYB7_MASK #define PDBCH2DELB_DELAY8_MASK PDBCH2DLYB_DELAYB8_MASK #define PDBCH2DELB_DELAY9_MASK PDBCH2DLYB_DELAYB9_MASK #define PDBCH2DELB_DELAY10_MASK PDBCH2DLYB_DELAYB10_MASK #define PDBCH2DELB_DELAY11_MASK PDBCH2DLYB_DELAYB11_MASK #define PDBCH2DELB_DELAY12_MASK PDBCH2DLYB_DELAYB12_MASK #define PDBCH2DELB_DELAY13_MASK PDBCH2DLYB_DELAYB13_MASK #define PDBCH2DELB_DELAY14_MASK PDBCH2DLYB_DELAYB14_MASK #define PDBCH2DELB_DELAY15_MASK PDBCH2DLYB_DELAYB15_MASK #define PDBCH3DELA PDBCH3DLYA #define PDBCH3DELA_DELAY0 PDBCH3DLYA_DELAYA0 #define PDBCH3DELA_DELAY1 PDBCH3DLYA_DELAYA1 #define PDBCH3DELA_DELAY2 PDBCH3DLYA_DELAYA2 #define PDBCH3DELA_DELAY3 PDBCH3DLYA_DELAYA3 #define PDBCH3DELA_DELAY4 PDBCH3DLYA_DELAYA4 #define PDBCH3DELA_DELAY5 PDBCH3DLYA_DELAYA5 #define PDBCH3DELA_DELAY6 PDBCH3DLYA_DELAYA6 #define PDBCH3DELA_DELAY7 PDBCH3DLYA_DELAYA7 #define PDBCH3DELA_DELAY8 PDBCH3DLYA_DELAYA8 #define PDBCH3DELA_DELAY9 PDBCH3DLYA_DELAYA9 #define PDBCH3DELA_DELAY10 PDBCH3DLYA_DELAYA10 #define PDBCH3DELA_DELAY11 PDBCH3DLYA_DELAYA11 #define PDBCH3DELA_DELAY12 PDBCH3DLYA_DELAYA12 #define PDBCH3DELA_DELAY13 PDBCH3DLYA_DELAYA13 #define PDBCH3DELA_DELAY14 PDBCH3DLYA_DELAYA14 #define PDBCH3DELA_DELAY15 PDBCH3DLYA_DELAYA15 #define PDBCH3DELA_DELAY0_MASK PDBCH3DLYA_DELAYA0_MASK #define PDBCH3DELA_DELAY1_MASK PDBCH3DLYA_DELAYA1_MASK #define PDBCH3DELA_DELAY2_MASK PDBCH3DLYA_DELAYA2_MASK #define PDBCH3DELA_DELAY3_MASK PDBCH3DLYA_DELAYA3_MASK #define PDBCH3DELA_DELAY4_MASK PDBCH3DLYA_DELAYA4_MASK #define PDBCH3DELA_DELAY5_MASK PDBCH3DLYA_DELAYA5_MASK #define PDBCH3DELA_DELAY6_MASK PDBCH3DLYA_DELAYA6_MASK #define PDBCH3DELA_DELAY7_MASK PDBCH3DLYA_DELAYA7_MASK #define PDBCH3DELA_DELAY8_MASK PDBCH3DLYA_DELAYA8_MASK #define PDBCH3DELA_DELAY9_MASK PDBCH3DLYA_DELAYA9_MASK #define PDBCH3DELA_DELAY10_MASK PDBCH3DLYA_DELAYA10_MASK #define PDBCH3DELA_DELAY11_MASK PDBCH3DLYA_DELAYA11_MASK #define PDBCH3DELA_DELAY12_MASK PDBCH3DLYA_DELAYA12_MASK #define PDBCH3DELA_DELAY13_MASK PDBCH3DLYA_DELAYA13_MASK #define PDBCH3DELA_DELAY14_MASK PDBCH3DLYA_DELAYA14_MASK #define PDBCH3DELA_DELAY15_MASK PDBCH3DLYA_DELAYA15_MASK #define PDBCH3DELB PDBCH3DLYB #define PDBCH3DELB_DELAY0 PDBCH3DLYB_DELAYB0 #define PDBCH3DELB_DELAY1 PDBCH3DLYB_DELAYB1 #define PDBCH3DELB_DELAY2 PDBCH3DLYB_DELAYB2 #define PDBCH3DELB_DELAY3 PDBCH3DLYB_DELAYB3 #define PDBCH3DELB_DELAY4 PDBCH3DLYB_DELAYB4 #define PDBCH3DELB_DELAY5 PDBCH3DLYB_DELAYB5 #define PDBCH3DELB_DELAY6 PDBCH3DLYB_DELAYB6 #define PDBCH3DELB_DELAY7 PDBCH3DLYB_DELAYB7 #define PDBCH3DELB_DELAY8 PDBCH3DLYB_DELAYB8 #define PDBCH3DELB_DELAY9 PDBCH3DLYB_DELAYB9 #define PDBCH3DELB_DELAY10 PDBCH3DLYB_DELAYB10 #define PDBCH3DELB_DELAY11 PDBCH3DLYB_DELAYB11 #define PDBCH3DELB_DELAY12 PDBCH3DLYB_DELAYB12 #define PDBCH3DELB_DELAY13 PDBCH3DLYB_DELAYB13 #define PDBCH3DELB_DELAY14 PDBCH3DLYB_DELAYB14 #define PDBCH3DELB_DELAY15 PDBCH3DLYB_DELAYB15 #define PDBCH3DELB_DELAY0_MASK PDBCH3DLYB_DELAYB0_MASK #define PDBCH3DELB_DELAY1_MASK PDBCH3DLYB_DELAYB1_MASK #define PDBCH3DELB_DELAY2_MASK PDBCH3DLYB_DELAYB2_MASK #define PDBCH3DELB_DELAY3_MASK PDBCH3DLYB_DELAYB3_MASK #define PDBCH3DELB_DELAY4_MASK PDBCH3DLYB_DELAYB4_MASK #define PDBCH3DELB_DELAY5_MASK PDBCH3DLYB_DELAYB5_MASK #define PDBCH3DELB_DELAY6_MASK PDBCH3DLYB_DELAYB6_MASK #define PDBCH3DELB_DELAY7_MASK PDBCH3DLYB_DELAYB7_MASK #define PDBCH3DELB_DELAY8_MASK PDBCH3DLYB_DELAYB8_MASK #define PDBCH3DELB_DELAY9_MASK PDBCH3DLYB_DELAYB9_MASK #define PDBCH3DELB_DELAY10_MASK PDBCH3DLYB_DELAYB10_MASK #define PDBCH3DELB_DELAY11_MASK PDBCH3DLYB_DELAYB11_MASK #define PDBCH3DELB_DELAY12_MASK PDBCH3DLYB_DELAYB12_MASK #define PDBCH3DELB_DELAY13_MASK PDBCH3DLYB_DELAYB13_MASK #define PDBCH3DELB_DELAY14_MASK PDBCH3DLYB_DELAYB14_MASK #define PDBCH3DELB_DELAY15_MASK PDBCH3DLYB_DELAYB15_MASK #define PDBCH4DELA PDBCH4DLYA #define PDBCH4DELA_DELAY0 PDBCH4DLYA_DELAYA0 #define PDBCH4DELA_DELAY1 PDBCH4DLYA_DELAYA1 #define PDBCH4DELA_DELAY2 PDBCH4DLYA_DELAYA2 #define PDBCH4DELA_DELAY3 PDBCH4DLYA_DELAYA3 #define PDBCH4DELA_DELAY4 PDBCH4DLYA_DELAYA4 #define PDBCH4DELA_DELAY5 PDBCH4DLYA_DELAYA5 #define PDBCH4DELA_DELAY6 PDBCH4DLYA_DELAYA6 #define PDBCH4DELA_DELAY7 PDBCH4DLYA_DELAYA7 #define PDBCH4DELA_DELAY8 PDBCH4DLYA_DELAYA8 #define PDBCH4DELA_DELAY9 PDBCH4DLYA_DELAYA9 #define PDBCH4DELA_DELAY10 PDBCH4DLYA_DELAYA10 #define PDBCH4DELA_DELAY11 PDBCH4DLYA_DELAYA11 #define PDBCH4DELA_DELAY12 PDBCH4DLYA_DELAYA12 #define PDBCH4DELA_DELAY13 PDBCH4DLYA_DELAYA13 #define PDBCH4DELA_DELAY14 PDBCH4DLYA_DELAYA14 #define PDBCH4DELA_DELAY15 PDBCH4DLYA_DELAYA15 #define PDBCH4DELA_DELAY0_MASK PDBCH4DLYA_DELAYA0_MASK #define PDBCH4DELA_DELAY1_MASK PDBCH4DLYA_DELAYA1_MASK #define PDBCH4DELA_DELAY2_MASK PDBCH4DLYA_DELAYA2_MASK #define PDBCH4DELA_DELAY3_MASK PDBCH4DLYA_DELAYA3_MASK #define PDBCH4DELA_DELAY4_MASK PDBCH4DLYA_DELAYA4_MASK #define PDBCH4DELA_DELAY5_MASK PDBCH4DLYA_DELAYA5_MASK #define PDBCH4DELA_DELAY6_MASK PDBCH4DLYA_DELAYA6_MASK #define PDBCH4DELA_DELAY7_MASK PDBCH4DLYA_DELAYA7_MASK #define PDBCH4DELA_DELAY8_MASK PDBCH4DLYA_DELAYA8_MASK #define PDBCH4DELA_DELAY9_MASK PDBCH4DLYA_DELAYA9_MASK #define PDBCH4DELA_DELAY10_MASK PDBCH4DLYA_DELAYA10_MASK #define PDBCH4DELA_DELAY11_MASK PDBCH4DLYA_DELAYA11_MASK #define PDBCH4DELA_DELAY12_MASK PDBCH4DLYA_DELAYA12_MASK #define PDBCH4DELA_DELAY13_MASK PDBCH4DLYA_DELAYA13_MASK #define PDBCH4DELA_DELAY14_MASK PDBCH4DLYA_DELAYA14_MASK #define PDBCH4DELA_DELAY15_MASK PDBCH4DLYA_DELAYA15_MASK #define PDBCH4DELB PDBCH4DLYB #define PDBCH4DELB_DELAY0 PDBCH4DLYB_DELAYB0 #define PDBCH4DELB_DELAY1 PDBCH4DLYB_DELAYB1 #define PDBCH4DELB_DELAY2 PDBCH4DLYB_DELAYB2 #define PDBCH4DELB_DELAY3 PDBCH4DLYB_DELAYB3 #define PDBCH4DELB_DELAY4 PDBCH4DLYB_DELAYB4 #define PDBCH4DELB_DELAY5 PDBCH4DLYB_DELAYB5 #define PDBCH4DELB_DELAY6 PDBCH4DLYB_DELAYB6 #define PDBCH4DELB_DELAY7 PDBCH4DLYB_DELAYB7 #define PDBCH4DELB_DELAY8 PDBCH4DLYB_DELAYB8 #define PDBCH4DELB_DELAY9 PDBCH4DLYB_DELAYB9 #define PDBCH4DELB_DELAY10 PDBCH4DLYB_DELAYB10 #define PDBCH4DELB_DELAY11 PDBCH4DLYB_DELAYB11 #define PDBCH4DELB_DELAY12 PDBCH4DLYB_DELAYB12 #define PDBCH4DELB_DELAY13 PDBCH4DLYB_DELAYB13 #define PDBCH4DELB_DELAY14 PDBCH4DLYB_DELAYB14 #define PDBCH4DELB_DELAY15 PDBCH4DLYB_DELAYB15 #define PDBCH4DELB_DELAY0_MASK PDBCH4DLYB_DELAYB0_MASK #define PDBCH4DELB_DELAY1_MASK PDBCH4DLYB_DELAYB1_MASK #define PDBCH4DELB_DELAY2_MASK PDBCH4DLYB_DELAYB2_MASK #define PDBCH4DELB_DELAY3_MASK PDBCH4DLYB_DELAYB3_MASK #define PDBCH4DELB_DELAY4_MASK PDBCH4DLYB_DELAYB4_MASK #define PDBCH4DELB_DELAY5_MASK PDBCH4DLYB_DELAYB5_MASK #define PDBCH4DELB_DELAY6_MASK PDBCH4DLYB_DELAYB6_MASK #define PDBCH4DELB_DELAY7_MASK PDBCH4DLYB_DELAYB7_MASK #define PDBCH4DELB_DELAY8_MASK PDBCH4DLYB_DELAYB8_MASK #define PDBCH4DELB_DELAY9_MASK PDBCH4DLYB_DELAYB9_MASK #define PDBCH4DELB_DELAY10_MASK PDBCH4DLYB_DELAYB10_MASK #define PDBCH4DELB_DELAY11_MASK PDBCH4DLYB_DELAYB11_MASK #define PDBCH4DELB_DELAY12_MASK PDBCH4DLYB_DELAYB12_MASK #define PDBCH4DELB_DELAY13_MASK PDBCH4DLYB_DELAYB13_MASK #define PDBCH4DELB_DELAY14_MASK PDBCH4DLYB_DELAYB14_MASK #define PDBCH4DELB_DELAY15_MASK PDBCH4DLYB_DELAYB15_MASK /* **** 6.11.2009 11:04:02 */ #define PDBMOD_MOD0 This_symb_has_been_depreciated #define PDBMOD_MOD1 This_symb_has_been_depreciated #define PDBMOD_MOD2 This_symb_has_been_depreciated #define PDBMOD_MOD3 This_symb_has_been_depreciated #define PDBMOD_MOD4 This_symb_has_been_depreciated #define PDBMOD_MOD5 This_symb_has_been_depreciated #define PDBMOD_MOD6 This_symb_has_been_depreciated #define PDBMOD_MOD7 This_symb_has_been_depreciated #define PDBMOD_MOD8 This_symb_has_been_depreciated #define PDBMOD_MOD9 This_symb_has_been_depreciated #define PDBMOD_MOD10 This_symb_has_been_depreciated #define PDBMOD_MOD11 This_symb_has_been_depreciated #define PDBMOD_MOD12 This_symb_has_been_depreciated #define PDBMOD_MOD13 This_symb_has_been_depreciated #define PDBMOD_MOD14 This_symb_has_been_depreciated #define PDBMOD_MOD15 This_symb_has_been_depreciated #define PDBMOD_MOD0_MASK This_symb_has_been_depreciated #define PDBMOD_MOD1_MASK This_symb_has_been_depreciated #define PDBMOD_MOD2_MASK This_symb_has_been_depreciated #define PDBMOD_MOD3_MASK This_symb_has_been_depreciated #define PDBMOD_MOD4_MASK This_symb_has_been_depreciated #define PDBMOD_MOD5_MASK This_symb_has_been_depreciated #define PDBMOD_MOD6_MASK This_symb_has_been_depreciated #define PDBMOD_MOD7_MASK This_symb_has_been_depreciated #define PDBMOD_MOD8_MASK This_symb_has_been_depreciated #define PDBMOD_MOD9_MASK This_symb_has_been_depreciated #define PDBMOD_MOD10_MASK This_symb_has_been_depreciated #define PDBMOD_MOD11_MASK This_symb_has_been_depreciated #define PDBMOD_MOD12_MASK This_symb_has_been_depreciated #define PDBMOD_MOD13_MASK This_symb_has_been_depreciated #define PDBMOD_MOD14_MASK This_symb_has_been_depreciated #define PDBMOD_MOD15_MASK This_symb_has_been_depreciated #define PDBCNT_COUNT0 This_symb_has_been_depreciated #define PDBCNT_COUNT1 This_symb_has_been_depreciated #define PDBCNT_COUNT2 This_symb_has_been_depreciated #define PDBCNT_COUNT3 This_symb_has_been_depreciated #define PDBCNT_COUNT4 This_symb_has_been_depreciated #define PDBCNT_COUNT5 This_symb_has_been_depreciated #define PDBCNT_COUNT6 This_symb_has_been_depreciated #define PDBCNT_COUNT7 This_symb_has_been_depreciated #define PDBCNT_COUNT8 This_symb_has_been_depreciated #define PDBCNT_COUNT9 This_symb_has_been_depreciated #define PDBCNT_COUNT10 This_symb_has_been_depreciated #define PDBCNT_COUNT11 This_symb_has_been_depreciated #define PDBCNT_COUNT12 This_symb_has_been_depreciated #define PDBCNT_COUNT13 This_symb_has_been_depreciated #define PDBCNT_COUNT14 This_symb_has_been_depreciated #define PDBCNT_COUNT15 This_symb_has_been_depreciated #define PDBCNT_COUNT0_MASK This_symb_has_been_depreciated #define PDBCNT_COUNT1_MASK This_symb_has_been_depreciated #define PDBCNT_COUNT2_MASK This_symb_has_been_depreciated #define PDBCNT_COUNT3_MASK This_symb_has_been_depreciated #define PDBCNT_COUNT4_MASK This_symb_has_been_depreciated #define PDBCNT_COUNT5_MASK This_symb_has_been_depreciated #define PDBCNT_COUNT6_MASK This_symb_has_been_depreciated #define PDBCNT_COUNT7_MASK This_symb_has_been_depreciated #define PDBCNT_COUNT8_MASK This_symb_has_been_depreciated #define PDBCNT_COUNT9_MASK This_symb_has_been_depreciated #define PDBCNT_COUNT10_MASK This_symb_has_been_depreciated #define PDBCNT_COUNT11_MASK This_symb_has_been_depreciated #define PDBCNT_COUNT12_MASK This_symb_has_been_depreciated #define PDBCNT_COUNT13_MASK This_symb_has_been_depreciated #define PDBCNT_COUNT14_MASK This_symb_has_been_depreciated #define PDBCNT_COUNT15_MASK This_symb_has_been_depreciated /* **** 14.1.2010 15:43:35 */ #define IRTC_ALM_YRMON_bcd_AML_MONTH_units0 IRTC_ALM_YRMON_bcd_ALM_MONTH_units0 #define IRTC_ALM_YRMON_bcd_AML_MONTH_units1 IRTC_ALM_YRMON_bcd_ALM_MONTH_units1 #define IRTC_ALM_YRMON_bcd_AML_MONTH_units2 IRTC_ALM_YRMON_bcd_ALM_MONTH_units2 #define IRTC_ALM_YRMON_bcd_AML_MONTH_units3 IRTC_ALM_YRMON_bcd_ALM_MONTH_units3 #define IRTC_ALM_YRMON_bcd_AML_MONTH_tens0 IRTC_ALM_YRMON_bcd_ALM_MONTH_tens0 #define IRTC_ALM_YRMON_bcd_AML_MONTH_tens1 IRTC_ALM_YRMON_bcd_ALM_MONTH_tens1 #define IRTC_ALM_YRMON_bcd_AML_MONTH_tens2 IRTC_ALM_YRMON_bcd_ALM_MONTH_tens2 #define IRTC_ALM_YRMON_bcd_AML_MONTH_tens3 IRTC_ALM_YRMON_bcd_ALM_MONTH_tens3 #define IRTC_ALM_YRMON_bcd_AML_MONTH_units IRTC_ALM_YRMON_bcd_ALM_MONTH_units #define IRTC_ALM_YRMON_bcd_AML_MONTH_tens IRTC_ALM_YRMON_bcd_ALM_MONTH_tens #define IRTC_ALM_YRMON_bcd_AML_MONTH_units0_MASK IRTC_ALM_YRMON_bcd_ALM_MONTH_units0_MASK #define IRTC_ALM_YRMON_bcd_AML_MONTH_units1_MASK IRTC_ALM_YRMON_bcd_ALM_MONTH_units1_MASK #define IRTC_ALM_YRMON_bcd_AML_MONTH_units2_MASK IRTC_ALM_YRMON_bcd_ALM_MONTH_units2_MASK #define IRTC_ALM_YRMON_bcd_AML_MONTH_units3_MASK IRTC_ALM_YRMON_bcd_ALM_MONTH_units3_MASK #define IRTC_ALM_YRMON_bcd_AML_MONTH_tens0_MASK IRTC_ALM_YRMON_bcd_ALM_MONTH_tens0_MASK #define IRTC_ALM_YRMON_bcd_AML_MONTH_tens1_MASK IRTC_ALM_YRMON_bcd_ALM_MONTH_tens1_MASK #define IRTC_ALM_YRMON_bcd_AML_MONTH_tens2_MASK IRTC_ALM_YRMON_bcd_ALM_MONTH_tens2_MASK #define IRTC_ALM_YRMON_bcd_AML_MONTH_tens3_MASK IRTC_ALM_YRMON_bcd_ALM_MONTH_tens3_MASK #define IRTC_ALM_YRMON_bcd_AML_MONTH_units_MASK IRTC_ALM_YRMON_bcd_ALM_MONTH_units_MASK #define IRTC_ALM_YRMON_bcd_AML_MONTH_units_BITNUM IRTC_ALM_YRMON_bcd_ALM_MONTH_units_BITNUM #define IRTC_ALM_YRMON_bcd_AML_MONTH_tens_MASK IRTC_ALM_YRMON_bcd_ALM_MONTH_tens_MASK #define IRTC_ALM_YRMON_bcd_AML_MONTH_tens_BITNUM IRTC_ALM_YRMON_bcd_ALM_MONTH_tens_BITNUM #define IRTC_ALM_YRMON_bin_AML_MONTH0 IRTC_ALM_YRMON_bin_ALM_MONTH0 #define IRTC_ALM_YRMON_bin_AML_MONTH1 IRTC_ALM_YRMON_bin_ALM_MONTH1 #define IRTC_ALM_YRMON_bin_AML_MONTH2 IRTC_ALM_YRMON_bin_ALM_MONTH2 #define IRTC_ALM_YRMON_bin_AML_MONTH3 IRTC_ALM_YRMON_bin_ALM_MONTH3 #define IRTC_ALM_YRMON_bin_AML_MONTH IRTC_ALM_YRMON_bin_ALM_MONTH #define IRTC_ALM_YRMON_bin_AML_MONTH0_MASK IRTC_ALM_YRMON_bin_ALM_MONTH0_MASK #define IRTC_ALM_YRMON_bin_AML_MONTH1_MASK IRTC_ALM_YRMON_bin_ALM_MONTH1_MASK #define IRTC_ALM_YRMON_bin_AML_MONTH2_MASK IRTC_ALM_YRMON_bin_ALM_MONTH2_MASK #define IRTC_ALM_YRMON_bin_AML_MONTH3_MASK IRTC_ALM_YRMON_bin_ALM_MONTH3_MASK #define IRTC_ALM_YRMON_bin_AML_MONTH_MASK IRTC_ALM_YRMON_bin_ALM_MONTH_MASK #define IRTC_ALM_YRMON_bin_AML_MONTH_BITNUM IRTC_ALM_YRMON_bin_ALM_MONTH_BITNUM #pragma options align=reset #endif