; Based on CPU DB MCF51JE256_104, version 3.00.004 (RegistersPrg V2.31) ; ################################################################### ; Filename : mcf51je256.inc ; Processor : MCF51JE256 ; FileFormat: V2.31 ; DataSheet : MCF51JE256 Rev. 1 07/2009 ; Compiler : CodeWarrior compiler ; Date/Time : 14.1.2010, 12:08 ; Abstract : ; This header implements the mapping of I/O devices. ; ; Copyright : 1997 - 2010 Freescale Semiconductor, Inc. All Rights Reserved. ; ; http : www.freescale.com ; mail : support@freescale.com ; ; CPU Registers Revisions: ; - none ; ; File-Format-Revisions: ; - none ; ; Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific ; derivative device. To avoid extra current drain from floating input pins, the user’s reset ; initialization routine in the application program must either enable on-chip pull-up devices ; or change the direction of unconnected pins to outputs so the pins do not float. ; ################################################################### ;*** Interrupt Vectors ;****************************************** INITSP: .equ $00000000 INITPC: .equ $00000004 Vaccerr: .equ $00000008 Vadderr: .equ $0000000C Viinstr: .equ $00000010 VReserved5: .equ $00000014 VReserved6: .equ $00000018 VReserved7: .equ $0000001C Vprviol: .equ $00000020 Vtrace: .equ $00000024 Vunilaop: .equ $00000028 Vunilfop: .equ $0000002C Vdbgi: .equ $00000030 VReserved13: .equ $00000034 Vferror: .equ $00000038 VReserved15: .equ $0000003C VReserved16: .equ $00000040 VReserved17: .equ $00000044 VReserved18: .equ $00000048 VReserved19: .equ $0000004C VReserved20: .equ $00000050 VReserved21: .equ $00000054 VReserved22: .equ $00000058 VReserved23: .equ $0000005C Vspuri: .equ $00000060 VReserved25: .equ $00000064 VReserved26: .equ $00000068 VReserved27: .equ $0000006C VReserved28: .equ $00000070 VReserved29: .equ $00000074 VReserved30: .equ $00000078 VReserved31: .equ $0000007C Vtrap0: .equ $00000080 Vtrap1: .equ $00000084 Vtrap2: .equ $00000088 Vtrap3: .equ $0000008C Vtrap4: .equ $00000090 Vtrap5: .equ $00000094 Vtrap6: .equ $00000098 Vtrap7: .equ $0000009C Vtrap8: .equ $000000A0 Vtrap9: .equ $000000A4 Vtrap10: .equ $000000A8 Vtrap11: .equ $000000AC Vtrap12: .equ $000000B0 Vtrap13: .equ $000000B4 Vtrap14: .equ $000000B8 Vtrap15: .equ $000000BC VReserved48: .equ $000000C0 VReserved49: .equ $000000C4 VReserved50: .equ $000000C8 VReserved51: .equ $000000CC VReserved52: .equ $000000D0 VReserved53: .equ $000000D4 VReserved54: .equ $000000D8 VReserved55: .equ $000000DC VReserved56: .equ $000000E0 VReserved57: .equ $000000E4 VReserved58: .equ $000000E8 VReserved59: .equ $000000EC VReserved60: .equ $000000F0 Vunsinstr: .equ $000000F4 VReserved62: .equ $000000F8 VReserved63: .equ $000000FC Virq: .equ $00000100 Vlvd: .equ $00000104 Vlol: .equ $00000108 Vusb: .equ $0000010C Vpdb: .equ $00000110 Vdac: .equ $00000114 Vspi1: .equ $00000118 Vadc: .equ $0000011C VReserved72: .equ $00000120 Vtpm1ch0: .equ $00000124 Vtpm1ch1: .equ $00000128 Vtpm1ch2: .equ $0000012C Vtpm1ch3: .equ $00000130 Vtpm1ovf: .equ $00000134 Vspi2: .equ $00000138 Vcmt: .equ $0000013C Vtpm2ch0: .equ $00000140 Vtpm2ch1: .equ $00000144 Vtpm2ch2: .equ $00000148 Vtpm2ch3: .equ $0000014C Vtpm2ovf: .equ $00000150 Viic: .equ $00000154 Vpracmp: .equ $00000158 Vsci1err: .equ $0000015C Vsci1rx: .equ $00000160 Vsci1tx: .equ $00000164 Vsci2err: .equ $00000168 Vsci2rx: .equ $0000016C Vsci2tx: .equ $00000170 VReserved93: .equ $00000174 VReserved94: .equ $00000178 Vkbi1: .equ $0000017C Vkbi2: .equ $00000180 Vtod: .equ $00000184 VReserved98: .equ $00000188 VReserved99: .equ $0000018C VReserved100: .equ $00000190 VReserved101: .equ $00000194 VReserved102: .equ $00000198 VL7swi: .equ $0000019C VL6swi: .equ $000001A0 VL5swi: .equ $000001A4 VL4swi: .equ $000001A8 VL3swi: .equ $000001AC VL2swi: .equ $000001B0 VL1swi: .equ $000001B4 VReserved110: .equ $000001B8 VReserved111: .equ $000001BC Vftsr1: .equ $000001C0 Vftsr2: .equ $000001C4 VReserved114: .equ $000001C8 ; ;*** NV1FTRIM - Nonvolatile MCG Fine Trim; 0x000003FE *** NV1FTRIM: .equ $000003FE ;*** NV1FTRIM - Nonvolatile MCG Fine Trim; 0x000003FE *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NV1FTRIM_FTRIM: .equ 0 ; MCG Fine Trim ; bit position masks mNV1FTRIM_FTRIM: .equ %00000001 ;*** NV1MCGTRM - Nonvolatile MCG Trim Register; 0x000003FF *** NV1MCGTRM: .equ $000003FF ;*** NV1MCGTRM - Nonvolatile MCG Trim Register; 0x000003FF *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NV1MCGTRM_TRIM0: .equ 0 ; MCG Trim Setting, bit 0 NV1MCGTRM_TRIM1: .equ 1 ; MCG Trim Setting, bit 1 NV1MCGTRM_TRIM2: .equ 2 ; MCG Trim Setting, bit 2 NV1MCGTRM_TRIM3: .equ 3 ; MCG Trim Setting, bit 3 NV1MCGTRM_TRIM4: .equ 4 ; MCG Trim Setting, bit 4 NV1MCGTRM_TRIM5: .equ 5 ; MCG Trim Setting, bit 5 NV1MCGTRM_TRIM6: .equ 6 ; MCG Trim Setting, bit 6 NV1MCGTRM_TRIM7: .equ 7 ; MCG Trim Setting, bit 7 ; bit position masks mNV1MCGTRM_TRIM0: .equ %00000001 mNV1MCGTRM_TRIM1: .equ %00000010 mNV1MCGTRM_TRIM2: .equ %00000100 mNV1MCGTRM_TRIM3: .equ %00001000 mNV1MCGTRM_TRIM4: .equ %00010000 mNV1MCGTRM_TRIM5: .equ %00100000 mNV1MCGTRM_TRIM6: .equ %01000000 mNV1MCGTRM_TRIM7: .equ %10000000 ;*** NV1BACKKEY0 - Backdoor Comparison Key 0; 0x00000400 *** NV1BACKKEY0: .equ $00000400 ;*** NV1BACKKEY0 - Backdoor Comparison Key 0; 0x00000400 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NV1BACKKEY0_KEY0: .equ 0 ; Backdoor Comparison Key 0 Bits, bit 0 NV1BACKKEY0_KEY1: .equ 1 ; Backdoor Comparison Key 0 Bits, bit 1 NV1BACKKEY0_KEY2: .equ 2 ; Backdoor Comparison Key 0 Bits, bit 2 NV1BACKKEY0_KEY3: .equ 3 ; Backdoor Comparison Key 0 Bits, bit 3 NV1BACKKEY0_KEY4: .equ 4 ; Backdoor Comparison Key 0 Bits, bit 4 NV1BACKKEY0_KEY5: .equ 5 ; Backdoor Comparison Key 0 Bits, bit 5 NV1BACKKEY0_KEY6: .equ 6 ; Backdoor Comparison Key 0 Bits, bit 6 NV1BACKKEY0_KEY7: .equ 7 ; Backdoor Comparison Key 0 Bits, bit 7 ; bit position masks mNV1BACKKEY0_KEY0: .equ %00000001 mNV1BACKKEY0_KEY1: .equ %00000010 mNV1BACKKEY0_KEY2: .equ %00000100 mNV1BACKKEY0_KEY3: .equ %00001000 mNV1BACKKEY0_KEY4: .equ %00010000 mNV1BACKKEY0_KEY5: .equ %00100000 mNV1BACKKEY0_KEY6: .equ %01000000 mNV1BACKKEY0_KEY7: .equ %10000000 ;*** NV1BACKKEY1 - Backdoor Comparison Key 1; 0x00000401 *** NV1BACKKEY1: .equ $00000401 ;*** NV1BACKKEY1 - Backdoor Comparison Key 1; 0x00000401 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NV1BACKKEY1_KEY0: .equ 0 ; Backdoor Comparison Key 1 Bits, bit 0 NV1BACKKEY1_KEY1: .equ 1 ; Backdoor Comparison Key 1 Bits, bit 1 NV1BACKKEY1_KEY2: .equ 2 ; Backdoor Comparison Key 1 Bits, bit 2 NV1BACKKEY1_KEY3: .equ 3 ; Backdoor Comparison Key 1 Bits, bit 3 NV1BACKKEY1_KEY4: .equ 4 ; Backdoor Comparison Key 1 Bits, bit 4 NV1BACKKEY1_KEY5: .equ 5 ; Backdoor Comparison Key 1 Bits, bit 5 NV1BACKKEY1_KEY6: .equ 6 ; Backdoor Comparison Key 1 Bits, bit 6 NV1BACKKEY1_KEY7: .equ 7 ; Backdoor Comparison Key 1 Bits, bit 7 ; bit position masks mNV1BACKKEY1_KEY0: .equ %00000001 mNV1BACKKEY1_KEY1: .equ %00000010 mNV1BACKKEY1_KEY2: .equ %00000100 mNV1BACKKEY1_KEY3: .equ %00001000 mNV1BACKKEY1_KEY4: .equ %00010000 mNV1BACKKEY1_KEY5: .equ %00100000 mNV1BACKKEY1_KEY6: .equ %01000000 mNV1BACKKEY1_KEY7: .equ %10000000 ;*** NV1BACKKEY2 - Backdoor Comparison Key 2; 0x00000402 *** NV1BACKKEY2: .equ $00000402 ;*** NV1BACKKEY2 - Backdoor Comparison Key 2; 0x00000402 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NV1BACKKEY2_KEY0: .equ 0 ; Backdoor Comparison Key 2 Bits, bit 0 NV1BACKKEY2_KEY1: .equ 1 ; Backdoor Comparison Key 2 Bits, bit 1 NV1BACKKEY2_KEY2: .equ 2 ; Backdoor Comparison Key 2 Bits, bit 2 NV1BACKKEY2_KEY3: .equ 3 ; Backdoor Comparison Key 2 Bits, bit 3 NV1BACKKEY2_KEY4: .equ 4 ; Backdoor Comparison Key 2 Bits, bit 4 NV1BACKKEY2_KEY5: .equ 5 ; Backdoor Comparison Key 2 Bits, bit 5 NV1BACKKEY2_KEY6: .equ 6 ; Backdoor Comparison Key 2 Bits, bit 6 NV1BACKKEY2_KEY7: .equ 7 ; Backdoor Comparison Key 2 Bits, bit 7 ; bit position masks mNV1BACKKEY2_KEY0: .equ %00000001 mNV1BACKKEY2_KEY1: .equ %00000010 mNV1BACKKEY2_KEY2: .equ %00000100 mNV1BACKKEY2_KEY3: .equ %00001000 mNV1BACKKEY2_KEY4: .equ %00010000 mNV1BACKKEY2_KEY5: .equ %00100000 mNV1BACKKEY2_KEY6: .equ %01000000 mNV1BACKKEY2_KEY7: .equ %10000000 ;*** NV1BACKKEY3 - Backdoor Comparison Key 3; 0x00000403 *** NV1BACKKEY3: .equ $00000403 ;*** NV1BACKKEY3 - Backdoor Comparison Key 3; 0x00000403 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NV1BACKKEY3_KEY0: .equ 0 ; Backdoor Comparison Key 3 Bits, bit 0 NV1BACKKEY3_KEY1: .equ 1 ; Backdoor Comparison Key 3 Bits, bit 1 NV1BACKKEY3_KEY2: .equ 2 ; Backdoor Comparison Key 3 Bits, bit 2 NV1BACKKEY3_KEY3: .equ 3 ; Backdoor Comparison Key 3 Bits, bit 3 NV1BACKKEY3_KEY4: .equ 4 ; Backdoor Comparison Key 3 Bits, bit 4 NV1BACKKEY3_KEY5: .equ 5 ; Backdoor Comparison Key 3 Bits, bit 5 NV1BACKKEY3_KEY6: .equ 6 ; Backdoor Comparison Key 3 Bits, bit 6 NV1BACKKEY3_KEY7: .equ 7 ; Backdoor Comparison Key 3 Bits, bit 7 ; bit position masks mNV1BACKKEY3_KEY0: .equ %00000001 mNV1BACKKEY3_KEY1: .equ %00000010 mNV1BACKKEY3_KEY2: .equ %00000100 mNV1BACKKEY3_KEY3: .equ %00001000 mNV1BACKKEY3_KEY4: .equ %00010000 mNV1BACKKEY3_KEY5: .equ %00100000 mNV1BACKKEY3_KEY6: .equ %01000000 mNV1BACKKEY3_KEY7: .equ %10000000 ;*** NV1BACKKEY4 - Backdoor Comparison Key 4; 0x00000404 *** NV1BACKKEY4: .equ $00000404 ;*** NV1BACKKEY4 - Backdoor Comparison Key 4; 0x00000404 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NV1BACKKEY4_KEY0: .equ 0 ; Backdoor Comparison Key 4 Bits, bit 0 NV1BACKKEY4_KEY1: .equ 1 ; Backdoor Comparison Key 4 Bits, bit 1 NV1BACKKEY4_KEY2: .equ 2 ; Backdoor Comparison Key 4 Bits, bit 2 NV1BACKKEY4_KEY3: .equ 3 ; Backdoor Comparison Key 4 Bits, bit 3 NV1BACKKEY4_KEY4: .equ 4 ; Backdoor Comparison Key 4 Bits, bit 4 NV1BACKKEY4_KEY5: .equ 5 ; Backdoor Comparison Key 4 Bits, bit 5 NV1BACKKEY4_KEY6: .equ 6 ; Backdoor Comparison Key 4 Bits, bit 6 NV1BACKKEY4_KEY7: .equ 7 ; Backdoor Comparison Key 4 Bits, bit 7 ; bit position masks mNV1BACKKEY4_KEY0: .equ %00000001 mNV1BACKKEY4_KEY1: .equ %00000010 mNV1BACKKEY4_KEY2: .equ %00000100 mNV1BACKKEY4_KEY3: .equ %00001000 mNV1BACKKEY4_KEY4: .equ %00010000 mNV1BACKKEY4_KEY5: .equ %00100000 mNV1BACKKEY4_KEY6: .equ %01000000 mNV1BACKKEY4_KEY7: .equ %10000000 ;*** NV1BACKKEY5 - Backdoor Comparison Key 5; 0x00000405 *** NV1BACKKEY5: .equ $00000405 ;*** NV1BACKKEY5 - Backdoor Comparison Key 5; 0x00000405 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NV1BACKKEY5_KEY0: .equ 0 ; Backdoor Comparison Key 5 Bits, bit 0 NV1BACKKEY5_KEY1: .equ 1 ; Backdoor Comparison Key 5 Bits, bit 1 NV1BACKKEY5_KEY2: .equ 2 ; Backdoor Comparison Key 5 Bits, bit 2 NV1BACKKEY5_KEY3: .equ 3 ; Backdoor Comparison Key 5 Bits, bit 3 NV1BACKKEY5_KEY4: .equ 4 ; Backdoor Comparison Key 5 Bits, bit 4 NV1BACKKEY5_KEY5: .equ 5 ; Backdoor Comparison Key 5 Bits, bit 5 NV1BACKKEY5_KEY6: .equ 6 ; Backdoor Comparison Key 5 Bits, bit 6 NV1BACKKEY5_KEY7: .equ 7 ; Backdoor Comparison Key 5 Bits, bit 7 ; bit position masks mNV1BACKKEY5_KEY0: .equ %00000001 mNV1BACKKEY5_KEY1: .equ %00000010 mNV1BACKKEY5_KEY2: .equ %00000100 mNV1BACKKEY5_KEY3: .equ %00001000 mNV1BACKKEY5_KEY4: .equ %00010000 mNV1BACKKEY5_KEY5: .equ %00100000 mNV1BACKKEY5_KEY6: .equ %01000000 mNV1BACKKEY5_KEY7: .equ %10000000 ;*** NV1BACKKEY6 - Backdoor Comparison Key 6; 0x00000406 *** NV1BACKKEY6: .equ $00000406 ;*** NV1BACKKEY6 - Backdoor Comparison Key 6; 0x00000406 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NV1BACKKEY6_KEY0: .equ 0 ; Backdoor Comparison Key 6 Bits, bit 0 NV1BACKKEY6_KEY1: .equ 1 ; Backdoor Comparison Key 6 Bits, bit 1 NV1BACKKEY6_KEY2: .equ 2 ; Backdoor Comparison Key 6 Bits, bit 2 NV1BACKKEY6_KEY3: .equ 3 ; Backdoor Comparison Key 6 Bits, bit 3 NV1BACKKEY6_KEY4: .equ 4 ; Backdoor Comparison Key 6 Bits, bit 4 NV1BACKKEY6_KEY5: .equ 5 ; Backdoor Comparison Key 6 Bits, bit 5 NV1BACKKEY6_KEY6: .equ 6 ; Backdoor Comparison Key 6 Bits, bit 6 NV1BACKKEY6_KEY7: .equ 7 ; Backdoor Comparison Key 6 Bits, bit 7 ; bit position masks mNV1BACKKEY6_KEY0: .equ %00000001 mNV1BACKKEY6_KEY1: .equ %00000010 mNV1BACKKEY6_KEY2: .equ %00000100 mNV1BACKKEY6_KEY3: .equ %00001000 mNV1BACKKEY6_KEY4: .equ %00010000 mNV1BACKKEY6_KEY5: .equ %00100000 mNV1BACKKEY6_KEY6: .equ %01000000 mNV1BACKKEY6_KEY7: .equ %10000000 ;*** NV1BACKKEY7 - Backdoor Comparison Key 7; 0x00000407 *** NV1BACKKEY7: .equ $00000407 ;*** NV1BACKKEY7 - Backdoor Comparison Key 7; 0x00000407 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NV1BACKKEY7_KEY0: .equ 0 ; Backdoor Comparison Key 7 Bits, bit 0 NV1BACKKEY7_KEY1: .equ 1 ; Backdoor Comparison Key 7 Bits, bit 1 NV1BACKKEY7_KEY2: .equ 2 ; Backdoor Comparison Key 7 Bits, bit 2 NV1BACKKEY7_KEY3: .equ 3 ; Backdoor Comparison Key 7 Bits, bit 3 NV1BACKKEY7_KEY4: .equ 4 ; Backdoor Comparison Key 7 Bits, bit 4 NV1BACKKEY7_KEY5: .equ 5 ; Backdoor Comparison Key 7 Bits, bit 5 NV1BACKKEY7_KEY6: .equ 6 ; Backdoor Comparison Key 7 Bits, bit 6 NV1BACKKEY7_KEY7: .equ 7 ; Backdoor Comparison Key 7 Bits, bit 7 ; bit position masks mNV1BACKKEY7_KEY0: .equ %00000001 mNV1BACKKEY7_KEY1: .equ %00000010 mNV1BACKKEY7_KEY2: .equ %00000100 mNV1BACKKEY7_KEY3: .equ %00001000 mNV1BACKKEY7_KEY4: .equ %00010000 mNV1BACKKEY7_KEY5: .equ %00100000 mNV1BACKKEY7_KEY6: .equ %01000000 mNV1BACKKEY7_KEY7: .equ %10000000 ;*** F1CHKS - Flash Checksum Register; 0x00000408 *** F1CHKS: .equ $00000408 ;*** F1CHKS - Flash Checksum Register; 0x00000408 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET F1CHKS_CHECKSUM0: .equ 0 ; Flash checksum bits, bit 0 F1CHKS_CHECKSUM1: .equ 1 ; Flash checksum bits, bit 1 F1CHKS_CHECKSUM2: .equ 2 ; Flash checksum bits, bit 2 F1CHKS_CHECKSUM3: .equ 3 ; Flash checksum bits, bit 3 F1CHKS_CHECKSUM4: .equ 4 ; Flash checksum bits, bit 4 F1CHKS_CHECKSUM5: .equ 5 ; Flash checksum bits, bit 5 F1CHKS_CHECKSUM6: .equ 6 ; Flash checksum bits, bit 6 F1CHKS_CHECKSUM7: .equ 7 ; Flash checksum bits, bit 7 F1CHKS_CHECKSUM8: .equ 8 ; Flash checksum bits, bit 8 F1CHKS_CHECKSUM9: .equ 9 ; Flash checksum bits, bit 9 F1CHKS_CHECKSUM10: .equ 10 ; Flash checksum bits, bit 10 F1CHKS_CHECKSUM11: .equ 11 ; Flash checksum bits, bit 11 F1CHKS_CHECKSUM12: .equ 12 ; Flash checksum bits, bit 12 F1CHKS_CHECKSUM13: .equ 13 ; Flash checksum bits, bit 13 F1CHKS_CHECKSUM14: .equ 14 ; Flash checksum bits, bit 14 F1CHKS_CHECKSUM15: .equ 15 ; Flash checksum bits, bit 15 ; bit position masks mF1CHKS_CHECKSUM0: .equ %00000001 mF1CHKS_CHECKSUM1: .equ %00000010 mF1CHKS_CHECKSUM2: .equ %00000100 mF1CHKS_CHECKSUM3: .equ %00001000 mF1CHKS_CHECKSUM4: .equ %00010000 mF1CHKS_CHECKSUM5: .equ %00100000 mF1CHKS_CHECKSUM6: .equ %01000000 mF1CHKS_CHECKSUM7: .equ %10000000 mF1CHKS_CHECKSUM8: .equ %100000000 mF1CHKS_CHECKSUM9: .equ %1000000000 mF1CHKS_CHECKSUM10: .equ %10000000000 mF1CHKS_CHECKSUM11: .equ %100000000000 mF1CHKS_CHECKSUM12: .equ %1000000000000 mF1CHKS_CHECKSUM13: .equ %10000000000000 mF1CHKS_CHECKSUM14: .equ %100000000000000 mF1CHKS_CHECKSUM15: .equ %1000000000000000 ;*** F1CHKSH - Flash Checksum Register High Byte; 0x00000408 *** F1CHKSH: .equ $00000408 ;*** F1CHKSH - Flash Checksum Register High Byte; 0x00000408 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET F1CHKSH_CHECKSUM8: .equ 0 ; Flash checksum bit 8 F1CHKSH_CHECKSUM9: .equ 1 ; Flash checksum bit 9 F1CHKSH_CHECKSUM10: .equ 2 ; Flash checksum bit 10 F1CHKSH_CHECKSUM11: .equ 3 ; Flash checksum bit 11 F1CHKSH_CHECKSUM12: .equ 4 ; Flash checksum bit 12 F1CHKSH_CHECKSUM13: .equ 5 ; Flash checksum bit 13 F1CHKSH_CHECKSUM14: .equ 6 ; Flash checksum bit 14 F1CHKSH_CHECKSUM15: .equ 7 ; Flash checksum bit 15 ; bit position masks mF1CHKSH_CHECKSUM8: .equ %00000001 mF1CHKSH_CHECKSUM9: .equ %00000010 mF1CHKSH_CHECKSUM10: .equ %00000100 mF1CHKSH_CHECKSUM11: .equ %00001000 mF1CHKSH_CHECKSUM12: .equ %00010000 mF1CHKSH_CHECKSUM13: .equ %00100000 mF1CHKSH_CHECKSUM14: .equ %01000000 mF1CHKSH_CHECKSUM15: .equ %10000000 ;*** F1CHKSL - Flash Checksum Register Low Byte; 0x00000409 *** F1CHKSL: .equ $00000409 ;*** F1CHKSL - Flash Checksum Register Low Byte; 0x00000409 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET F1CHKSL_CHECKSUM0: .equ 0 ; Flash checksum bits, bit 0 F1CHKSL_CHECKSUM1: .equ 1 ; Flash checksum bits, bit 1 F1CHKSL_CHECKSUM2: .equ 2 ; Flash checksum bits, bit 2 F1CHKSL_CHECKSUM3: .equ 3 ; Flash checksum bits, bit 3 F1CHKSL_CHECKSUM4: .equ 4 ; Flash checksum bits, bit 4 F1CHKSL_CHECKSUM5: .equ 5 ; Flash checksum bits, bit 5 F1CHKSL_CHECKSUM6: .equ 6 ; Flash checksum bits, bit 6 F1CHKSL_CHECKSUM7: .equ 7 ; Flash checksum bits, bit 7 ; bit position masks mF1CHKSL_CHECKSUM0: .equ %00000001 mF1CHKSL_CHECKSUM1: .equ %00000010 mF1CHKSL_CHECKSUM2: .equ %00000100 mF1CHKSL_CHECKSUM3: .equ %00001000 mF1CHKSL_CHECKSUM4: .equ %00010000 mF1CHKSL_CHECKSUM5: .equ %00100000 mF1CHKSL_CHECKSUM6: .equ %01000000 mF1CHKSL_CHECKSUM7: .equ %10000000 ;*** CHKSBYP1 - Checksum Bypass Register; 0x0000040A *** CHKSBYP1: .equ $0000040A ;*** CHKSBYP1 - Checksum Bypass Register; 0x0000040A *** ;*** Partial_Erase_Semaphore1 - Flash partial erase semaphore; 0x0000040B *** Partial_Erase_Semaphore1: .equ $0000040B ;*** Partial_Erase_Semaphore1 - Flash partial erase semaphore; 0x0000040B *** ;*** NV1PROT - Nonvolatile Flash Protection Register; 0x0000040D *** NV1PROT: .equ $0000040D ;*** NV1PROT - Nonvolatile Flash Protection Register; 0x0000040D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NV1PROT_FPOPEN: .equ 0 ; Flash Protection Open NV1PROT_FPS0: .equ 1 ; Flash Protection Size, bit 0 NV1PROT_FPS1: .equ 2 ; Flash Protection Size, bit 1 NV1PROT_FPS2: .equ 3 ; Flash Protection Size, bit 2 NV1PROT_FPS3: .equ 4 ; Flash Protection Size, bit 3 NV1PROT_FPS4: .equ 5 ; Flash Protection Size, bit 4 NV1PROT_FPS5: .equ 6 ; Flash Protection Size, bit 5 NV1PROT_FPS6: .equ 7 ; Flash Protection Size, bit 6 ; bit position masks mNV1PROT_FPOPEN: .equ %00000001 mNV1PROT_FPS0: .equ %00000010 mNV1PROT_FPS1: .equ %00000100 mNV1PROT_FPS2: .equ %00001000 mNV1PROT_FPS3: .equ %00010000 mNV1PROT_FPS4: .equ %00100000 mNV1PROT_FPS5: .equ %01000000 mNV1PROT_FPS6: .equ %10000000 ;*** NV1OPT - Nonvolatile Flash Options Register; 0x0000040F *** NV1OPT: .equ $0000040F ;*** NV1OPT - Nonvolatile Flash Options Register; 0x0000040F *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NV1OPT_SEC0: .equ 0 ; Flash Security Bit 0 NV1OPT_SEC1: .equ 1 ; Flash Security Bit 1 NV1OPT_KEYEN0: .equ 6 ; Backdoor Key Security Enable Bit 0 NV1OPT_KEYEN1: .equ 7 ; Backdoor Key Security Enable Bit 1 ; bit position masks mNV1OPT_SEC0: .equ %00000001 mNV1OPT_SEC1: .equ %00000010 mNV1OPT_KEYEN0: .equ %01000000 mNV1OPT_KEYEN1: .equ %10000000 ;*** FLASHAS - Flash Array Select Register; 0x00000410 *** FLASHAS: .equ $00000410 ;*** FLASHAS - Flash Array Select Register; 0x00000410 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FLASHAS_ARRAYSEL0: .equ 0 ; Flash array select bit FLASHAS_ARRAYSEL1: .equ 1 ; Flash array select protection bit ; bit position masks mFLASHAS_ARRAYSEL0: .equ %00000001 mFLASHAS_ARRAYSEL1: .equ %00000010 ;*** NV2FTRIM - Nonvolatile MCG Fine Trim; 0x000203FE *** NV2FTRIM: .equ $000203FE ;*** NV2FTRIM - Nonvolatile MCG Fine Trim; 0x000203FE *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NV2FTRIM_FTRIM: .equ 0 ; MCG Fine Trim ; bit position masks mNV2FTRIM_FTRIM: .equ %00000001 ;*** NV2MCGTRM - Nonvolatile MCG Trim Register; 0x000203FF *** NV2MCGTRM: .equ $000203FF ;*** NV2MCGTRM - Nonvolatile MCG Trim Register; 0x000203FF *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NV2MCGTRM_TRIM0: .equ 0 ; MCG Trim Setting, bit 0 NV2MCGTRM_TRIM1: .equ 1 ; MCG Trim Setting, bit 1 NV2MCGTRM_TRIM2: .equ 2 ; MCG Trim Setting, bit 2 NV2MCGTRM_TRIM3: .equ 3 ; MCG Trim Setting, bit 3 NV2MCGTRM_TRIM4: .equ 4 ; MCG Trim Setting, bit 4 NV2MCGTRM_TRIM5: .equ 5 ; MCG Trim Setting, bit 5 NV2MCGTRM_TRIM6: .equ 6 ; MCG Trim Setting, bit 6 NV2MCGTRM_TRIM7: .equ 7 ; MCG Trim Setting, bit 7 ; bit position masks mNV2MCGTRM_TRIM0: .equ %00000001 mNV2MCGTRM_TRIM1: .equ %00000010 mNV2MCGTRM_TRIM2: .equ %00000100 mNV2MCGTRM_TRIM3: .equ %00001000 mNV2MCGTRM_TRIM4: .equ %00010000 mNV2MCGTRM_TRIM5: .equ %00100000 mNV2MCGTRM_TRIM6: .equ %01000000 mNV2MCGTRM_TRIM7: .equ %10000000 ;*** NV2BACKKEY0 - Backdoor Comparison Key 0; 0x00020400 *** NV2BACKKEY0: .equ $00020400 ;*** NV2BACKKEY0 - Backdoor Comparison Key 0; 0x00020400 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NV2BACKKEY0_KEY0: .equ 0 ; Backdoor Comparison Key 0 Bits, bit 0 NV2BACKKEY0_KEY1: .equ 1 ; Backdoor Comparison Key 0 Bits, bit 1 NV2BACKKEY0_KEY2: .equ 2 ; Backdoor Comparison Key 0 Bits, bit 2 NV2BACKKEY0_KEY3: .equ 3 ; Backdoor Comparison Key 0 Bits, bit 3 NV2BACKKEY0_KEY4: .equ 4 ; Backdoor Comparison Key 0 Bits, bit 4 NV2BACKKEY0_KEY5: .equ 5 ; Backdoor Comparison Key 0 Bits, bit 5 NV2BACKKEY0_KEY6: .equ 6 ; Backdoor Comparison Key 0 Bits, bit 6 NV2BACKKEY0_KEY7: .equ 7 ; Backdoor Comparison Key 0 Bits, bit 7 ; bit position masks mNV2BACKKEY0_KEY0: .equ %00000001 mNV2BACKKEY0_KEY1: .equ %00000010 mNV2BACKKEY0_KEY2: .equ %00000100 mNV2BACKKEY0_KEY3: .equ %00001000 mNV2BACKKEY0_KEY4: .equ %00010000 mNV2BACKKEY0_KEY5: .equ %00100000 mNV2BACKKEY0_KEY6: .equ %01000000 mNV2BACKKEY0_KEY7: .equ %10000000 ;*** NV2BACKKEY1 - Backdoor Comparison Key 1; 0x00020401 *** NV2BACKKEY1: .equ $00020401 ;*** NV2BACKKEY1 - Backdoor Comparison Key 1; 0x00020401 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NV2BACKKEY1_KEY0: .equ 0 ; Backdoor Comparison Key 1 Bits, bit 0 NV2BACKKEY1_KEY1: .equ 1 ; Backdoor Comparison Key 1 Bits, bit 1 NV2BACKKEY1_KEY2: .equ 2 ; Backdoor Comparison Key 1 Bits, bit 2 NV2BACKKEY1_KEY3: .equ 3 ; Backdoor Comparison Key 1 Bits, bit 3 NV2BACKKEY1_KEY4: .equ 4 ; Backdoor Comparison Key 1 Bits, bit 4 NV2BACKKEY1_KEY5: .equ 5 ; Backdoor Comparison Key 1 Bits, bit 5 NV2BACKKEY1_KEY6: .equ 6 ; Backdoor Comparison Key 1 Bits, bit 6 NV2BACKKEY1_KEY7: .equ 7 ; Backdoor Comparison Key 1 Bits, bit 7 ; bit position masks mNV2BACKKEY1_KEY0: .equ %00000001 mNV2BACKKEY1_KEY1: .equ %00000010 mNV2BACKKEY1_KEY2: .equ %00000100 mNV2BACKKEY1_KEY3: .equ %00001000 mNV2BACKKEY1_KEY4: .equ %00010000 mNV2BACKKEY1_KEY5: .equ %00100000 mNV2BACKKEY1_KEY6: .equ %01000000 mNV2BACKKEY1_KEY7: .equ %10000000 ;*** NV2BACKKEY2 - Backdoor Comparison Key 2; 0x00020402 *** NV2BACKKEY2: .equ $00020402 ;*** NV2BACKKEY2 - Backdoor Comparison Key 2; 0x00020402 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NV2BACKKEY2_KEY0: .equ 0 ; Backdoor Comparison Key 2 Bits, bit 0 NV2BACKKEY2_KEY1: .equ 1 ; Backdoor Comparison Key 2 Bits, bit 1 NV2BACKKEY2_KEY2: .equ 2 ; Backdoor Comparison Key 2 Bits, bit 2 NV2BACKKEY2_KEY3: .equ 3 ; Backdoor Comparison Key 2 Bits, bit 3 NV2BACKKEY2_KEY4: .equ 4 ; Backdoor Comparison Key 2 Bits, bit 4 NV2BACKKEY2_KEY5: .equ 5 ; Backdoor Comparison Key 2 Bits, bit 5 NV2BACKKEY2_KEY6: .equ 6 ; Backdoor Comparison Key 2 Bits, bit 6 NV2BACKKEY2_KEY7: .equ 7 ; Backdoor Comparison Key 2 Bits, bit 7 ; bit position masks mNV2BACKKEY2_KEY0: .equ %00000001 mNV2BACKKEY2_KEY1: .equ %00000010 mNV2BACKKEY2_KEY2: .equ %00000100 mNV2BACKKEY2_KEY3: .equ %00001000 mNV2BACKKEY2_KEY4: .equ %00010000 mNV2BACKKEY2_KEY5: .equ %00100000 mNV2BACKKEY2_KEY6: .equ %01000000 mNV2BACKKEY2_KEY7: .equ %10000000 ;*** NV2BACKKEY3 - Backdoor Comparison Key 3; 0x00020403 *** NV2BACKKEY3: .equ $00020403 ;*** NV2BACKKEY3 - Backdoor Comparison Key 3; 0x00020403 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NV2BACKKEY3_KEY0: .equ 0 ; Backdoor Comparison Key 3 Bits, bit 0 NV2BACKKEY3_KEY1: .equ 1 ; Backdoor Comparison Key 3 Bits, bit 1 NV2BACKKEY3_KEY2: .equ 2 ; Backdoor Comparison Key 3 Bits, bit 2 NV2BACKKEY3_KEY3: .equ 3 ; Backdoor Comparison Key 3 Bits, bit 3 NV2BACKKEY3_KEY4: .equ 4 ; Backdoor Comparison Key 3 Bits, bit 4 NV2BACKKEY3_KEY5: .equ 5 ; Backdoor Comparison Key 3 Bits, bit 5 NV2BACKKEY3_KEY6: .equ 6 ; Backdoor Comparison Key 3 Bits, bit 6 NV2BACKKEY3_KEY7: .equ 7 ; Backdoor Comparison Key 3 Bits, bit 7 ; bit position masks mNV2BACKKEY3_KEY0: .equ %00000001 mNV2BACKKEY3_KEY1: .equ %00000010 mNV2BACKKEY3_KEY2: .equ %00000100 mNV2BACKKEY3_KEY3: .equ %00001000 mNV2BACKKEY3_KEY4: .equ %00010000 mNV2BACKKEY3_KEY5: .equ %00100000 mNV2BACKKEY3_KEY6: .equ %01000000 mNV2BACKKEY3_KEY7: .equ %10000000 ;*** NV2BACKKEY4 - Backdoor Comparison Key 4; 0x00020404 *** NV2BACKKEY4: .equ $00020404 ;*** NV2BACKKEY4 - Backdoor Comparison Key 4; 0x00020404 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NV2BACKKEY4_KEY0: .equ 0 ; Backdoor Comparison Key 4 Bits, bit 0 NV2BACKKEY4_KEY1: .equ 1 ; Backdoor Comparison Key 4 Bits, bit 1 NV2BACKKEY4_KEY2: .equ 2 ; Backdoor Comparison Key 4 Bits, bit 2 NV2BACKKEY4_KEY3: .equ 3 ; Backdoor Comparison Key 4 Bits, bit 3 NV2BACKKEY4_KEY4: .equ 4 ; Backdoor Comparison Key 4 Bits, bit 4 NV2BACKKEY4_KEY5: .equ 5 ; Backdoor Comparison Key 4 Bits, bit 5 NV2BACKKEY4_KEY6: .equ 6 ; Backdoor Comparison Key 4 Bits, bit 6 NV2BACKKEY4_KEY7: .equ 7 ; Backdoor Comparison Key 4 Bits, bit 7 ; bit position masks mNV2BACKKEY4_KEY0: .equ %00000001 mNV2BACKKEY4_KEY1: .equ %00000010 mNV2BACKKEY4_KEY2: .equ %00000100 mNV2BACKKEY4_KEY3: .equ %00001000 mNV2BACKKEY4_KEY4: .equ %00010000 mNV2BACKKEY4_KEY5: .equ %00100000 mNV2BACKKEY4_KEY6: .equ %01000000 mNV2BACKKEY4_KEY7: .equ %10000000 ;*** NV2BACKKEY5 - Backdoor Comparison Key 5; 0x00020405 *** NV2BACKKEY5: .equ $00020405 ;*** NV2BACKKEY5 - Backdoor Comparison Key 5; 0x00020405 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NV2BACKKEY5_KEY0: .equ 0 ; Backdoor Comparison Key 5 Bits, bit 0 NV2BACKKEY5_KEY1: .equ 1 ; Backdoor Comparison Key 5 Bits, bit 1 NV2BACKKEY5_KEY2: .equ 2 ; Backdoor Comparison Key 5 Bits, bit 2 NV2BACKKEY5_KEY3: .equ 3 ; Backdoor Comparison Key 5 Bits, bit 3 NV2BACKKEY5_KEY4: .equ 4 ; Backdoor Comparison Key 5 Bits, bit 4 NV2BACKKEY5_KEY5: .equ 5 ; Backdoor Comparison Key 5 Bits, bit 5 NV2BACKKEY5_KEY6: .equ 6 ; Backdoor Comparison Key 5 Bits, bit 6 NV2BACKKEY5_KEY7: .equ 7 ; Backdoor Comparison Key 5 Bits, bit 7 ; bit position masks mNV2BACKKEY5_KEY0: .equ %00000001 mNV2BACKKEY5_KEY1: .equ %00000010 mNV2BACKKEY5_KEY2: .equ %00000100 mNV2BACKKEY5_KEY3: .equ %00001000 mNV2BACKKEY5_KEY4: .equ %00010000 mNV2BACKKEY5_KEY5: .equ %00100000 mNV2BACKKEY5_KEY6: .equ %01000000 mNV2BACKKEY5_KEY7: .equ %10000000 ;*** NV2BACKKEY6 - Backdoor Comparison Key 6; 0x00020406 *** NV2BACKKEY6: .equ $00020406 ;*** NV2BACKKEY6 - Backdoor Comparison Key 6; 0x00020406 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NV2BACKKEY6_KEY0: .equ 0 ; Backdoor Comparison Key 6 Bits, bit 0 NV2BACKKEY6_KEY1: .equ 1 ; Backdoor Comparison Key 6 Bits, bit 1 NV2BACKKEY6_KEY2: .equ 2 ; Backdoor Comparison Key 6 Bits, bit 2 NV2BACKKEY6_KEY3: .equ 3 ; Backdoor Comparison Key 6 Bits, bit 3 NV2BACKKEY6_KEY4: .equ 4 ; Backdoor Comparison Key 6 Bits, bit 4 NV2BACKKEY6_KEY5: .equ 5 ; Backdoor Comparison Key 6 Bits, bit 5 NV2BACKKEY6_KEY6: .equ 6 ; Backdoor Comparison Key 6 Bits, bit 6 NV2BACKKEY6_KEY7: .equ 7 ; Backdoor Comparison Key 6 Bits, bit 7 ; bit position masks mNV2BACKKEY6_KEY0: .equ %00000001 mNV2BACKKEY6_KEY1: .equ %00000010 mNV2BACKKEY6_KEY2: .equ %00000100 mNV2BACKKEY6_KEY3: .equ %00001000 mNV2BACKKEY6_KEY4: .equ %00010000 mNV2BACKKEY6_KEY5: .equ %00100000 mNV2BACKKEY6_KEY6: .equ %01000000 mNV2BACKKEY6_KEY7: .equ %10000000 ;*** NV2BACKKEY7 - Backdoor Comparison Key 7; 0x00020407 *** NV2BACKKEY7: .equ $00020407 ;*** NV2BACKKEY7 - Backdoor Comparison Key 7; 0x00020407 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NV2BACKKEY7_KEY0: .equ 0 ; Backdoor Comparison Key 7 Bits, bit 0 NV2BACKKEY7_KEY1: .equ 1 ; Backdoor Comparison Key 7 Bits, bit 1 NV2BACKKEY7_KEY2: .equ 2 ; Backdoor Comparison Key 7 Bits, bit 2 NV2BACKKEY7_KEY3: .equ 3 ; Backdoor Comparison Key 7 Bits, bit 3 NV2BACKKEY7_KEY4: .equ 4 ; Backdoor Comparison Key 7 Bits, bit 4 NV2BACKKEY7_KEY5: .equ 5 ; Backdoor Comparison Key 7 Bits, bit 5 NV2BACKKEY7_KEY6: .equ 6 ; Backdoor Comparison Key 7 Bits, bit 6 NV2BACKKEY7_KEY7: .equ 7 ; Backdoor Comparison Key 7 Bits, bit 7 ; bit position masks mNV2BACKKEY7_KEY0: .equ %00000001 mNV2BACKKEY7_KEY1: .equ %00000010 mNV2BACKKEY7_KEY2: .equ %00000100 mNV2BACKKEY7_KEY3: .equ %00001000 mNV2BACKKEY7_KEY4: .equ %00010000 mNV2BACKKEY7_KEY5: .equ %00100000 mNV2BACKKEY7_KEY6: .equ %01000000 mNV2BACKKEY7_KEY7: .equ %10000000 ;*** F2CHKS - Flash Checksum Register; 0x00020408 *** F2CHKS: .equ $00020408 ;*** F2CHKS - Flash Checksum Register; 0x00020408 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET F2CHKS_CHECKSUM0: .equ 0 ; Flash checksum bits, bit 0 F2CHKS_CHECKSUM1: .equ 1 ; Flash checksum bits, bit 1 F2CHKS_CHECKSUM2: .equ 2 ; Flash checksum bits, bit 2 F2CHKS_CHECKSUM3: .equ 3 ; Flash checksum bits, bit 3 F2CHKS_CHECKSUM4: .equ 4 ; Flash checksum bits, bit 4 F2CHKS_CHECKSUM5: .equ 5 ; Flash checksum bits, bit 5 F2CHKS_CHECKSUM6: .equ 6 ; Flash checksum bits, bit 6 F2CHKS_CHECKSUM7: .equ 7 ; Flash checksum bits, bit 7 F2CHKS_CHECKSUM8: .equ 8 ; Flash checksum bits, bit 8 F2CHKS_CHECKSUM9: .equ 9 ; Flash checksum bits, bit 9 F2CHKS_CHECKSUM10: .equ 10 ; Flash checksum bits, bit 10 F2CHKS_CHECKSUM11: .equ 11 ; Flash checksum bits, bit 11 F2CHKS_CHECKSUM12: .equ 12 ; Flash checksum bits, bit 12 F2CHKS_CHECKSUM13: .equ 13 ; Flash checksum bits, bit 13 F2CHKS_CHECKSUM14: .equ 14 ; Flash checksum bits, bit 14 F2CHKS_CHECKSUM15: .equ 15 ; Flash checksum bits, bit 15 ; bit position masks mF2CHKS_CHECKSUM0: .equ %00000001 mF2CHKS_CHECKSUM1: .equ %00000010 mF2CHKS_CHECKSUM2: .equ %00000100 mF2CHKS_CHECKSUM3: .equ %00001000 mF2CHKS_CHECKSUM4: .equ %00010000 mF2CHKS_CHECKSUM5: .equ %00100000 mF2CHKS_CHECKSUM6: .equ %01000000 mF2CHKS_CHECKSUM7: .equ %10000000 mF2CHKS_CHECKSUM8: .equ %100000000 mF2CHKS_CHECKSUM9: .equ %1000000000 mF2CHKS_CHECKSUM10: .equ %10000000000 mF2CHKS_CHECKSUM11: .equ %100000000000 mF2CHKS_CHECKSUM12: .equ %1000000000000 mF2CHKS_CHECKSUM13: .equ %10000000000000 mF2CHKS_CHECKSUM14: .equ %100000000000000 mF2CHKS_CHECKSUM15: .equ %1000000000000000 ;*** F2CHKSH - Flash Checksum Register High Byte; 0x00020408 *** F2CHKSH: .equ $00020408 ;*** F2CHKSH - Flash Checksum Register High Byte; 0x00020408 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET F2CHKSH_CHECKSUM8: .equ 0 ; Flash checksum bit 8 F2CHKSH_CHECKSUM9: .equ 1 ; Flash checksum bit 9 F2CHKSH_CHECKSUM10: .equ 2 ; Flash checksum bit 10 F2CHKSH_CHECKSUM11: .equ 3 ; Flash checksum bit 11 F2CHKSH_CHECKSUM12: .equ 4 ; Flash checksum bit 12 F2CHKSH_CHECKSUM13: .equ 5 ; Flash checksum bit 13 F2CHKSH_CHECKSUM14: .equ 6 ; Flash checksum bit 14 F2CHKSH_CHECKSUM15: .equ 7 ; Flash checksum bit 15 ; bit position masks mF2CHKSH_CHECKSUM8: .equ %00000001 mF2CHKSH_CHECKSUM9: .equ %00000010 mF2CHKSH_CHECKSUM10: .equ %00000100 mF2CHKSH_CHECKSUM11: .equ %00001000 mF2CHKSH_CHECKSUM12: .equ %00010000 mF2CHKSH_CHECKSUM13: .equ %00100000 mF2CHKSH_CHECKSUM14: .equ %01000000 mF2CHKSH_CHECKSUM15: .equ %10000000 ;*** F2CHKSL - Flash Checksum Register Low Byte; 0x00020409 *** F2CHKSL: .equ $00020409 ;*** F2CHKSL - Flash Checksum Register Low Byte; 0x00020409 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET F2CHKSL_CHECKSUM0: .equ 0 ; Flash checksum bits, bit 0 F2CHKSL_CHECKSUM1: .equ 1 ; Flash checksum bits, bit 1 F2CHKSL_CHECKSUM2: .equ 2 ; Flash checksum bits, bit 2 F2CHKSL_CHECKSUM3: .equ 3 ; Flash checksum bits, bit 3 F2CHKSL_CHECKSUM4: .equ 4 ; Flash checksum bits, bit 4 F2CHKSL_CHECKSUM5: .equ 5 ; Flash checksum bits, bit 5 F2CHKSL_CHECKSUM6: .equ 6 ; Flash checksum bits, bit 6 F2CHKSL_CHECKSUM7: .equ 7 ; Flash checksum bits, bit 7 ; bit position masks mF2CHKSL_CHECKSUM0: .equ %00000001 mF2CHKSL_CHECKSUM1: .equ %00000010 mF2CHKSL_CHECKSUM2: .equ %00000100 mF2CHKSL_CHECKSUM3: .equ %00001000 mF2CHKSL_CHECKSUM4: .equ %00010000 mF2CHKSL_CHECKSUM5: .equ %00100000 mF2CHKSL_CHECKSUM6: .equ %01000000 mF2CHKSL_CHECKSUM7: .equ %10000000 ;*** CHKSBYP2 - Checksum Bypass Register; 0x0002040A *** CHKSBYP2: .equ $0002040A ;*** CHKSBYP2 - Checksum Bypass Register; 0x0002040A *** ;*** Partial_Erase_Semaphore2 - Flash partial erase semaphore; 0x0002040B *** Partial_Erase_Semaphore2: .equ $0002040B ;*** Partial_Erase_Semaphore2 - Flash partial erase semaphore; 0x0002040B *** ;*** NV2PROT - Nonvolatile Flash Protection Register; 0x0002040D *** NV2PROT: .equ $0002040D ;*** NV2PROT - Nonvolatile Flash Protection Register; 0x0002040D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NV2PROT_FPOPEN: .equ 0 ; Flash Protection Open NV2PROT_FPS0: .equ 1 ; Flash Protection Size, bit 0 NV2PROT_FPS1: .equ 2 ; Flash Protection Size, bit 1 NV2PROT_FPS2: .equ 3 ; Flash Protection Size, bit 2 NV2PROT_FPS3: .equ 4 ; Flash Protection Size, bit 3 NV2PROT_FPS4: .equ 5 ; Flash Protection Size, bit 4 NV2PROT_FPS5: .equ 6 ; Flash Protection Size, bit 5 NV2PROT_FPS6: .equ 7 ; Flash Protection Size, bit 6 ; bit position masks mNV2PROT_FPOPEN: .equ %00000001 mNV2PROT_FPS0: .equ %00000010 mNV2PROT_FPS1: .equ %00000100 mNV2PROT_FPS2: .equ %00001000 mNV2PROT_FPS3: .equ %00010000 mNV2PROT_FPS4: .equ %00100000 mNV2PROT_FPS5: .equ %01000000 mNV2PROT_FPS6: .equ %10000000 ;*** NV2OPT - Nonvolatile Flash Options Register; 0x0002040F *** NV2OPT: .equ $0002040F ;*** NV2OPT - Nonvolatile Flash Options Register; 0x0002040F *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NV2OPT_SEC0: .equ 0 ; Flash Security Bit 0 NV2OPT_SEC1: .equ 1 ; Flash Security Bit 1 NV2OPT_KEYEN0: .equ 6 ; Backdoor Key Security Enable Bit 0 NV2OPT_KEYEN1: .equ 7 ; Backdoor Key Security Enable Bit 1 ; bit position masks mNV2OPT_SEC0: .equ %00000001 mNV2OPT_SEC1: .equ %00000010 mNV2OPT_KEYEN0: .equ %01000000 mNV2OPT_KEYEN1: .equ %10000000 ;*** RGPIO_DIR - RGPIO Data Direction Register; 0x00C00000 *** RGPIO_DIR: .equ $00C00000 ;*** RGPIO_DIR - RGPIO Data Direction Register; 0x00C00000 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET RGPIO_DIR_DIR0: .equ 0 ; RGPIO data direction bit 0 RGPIO_DIR_DIR1: .equ 1 ; RGPIO data direction bit 1 RGPIO_DIR_DIR2: .equ 2 ; RGPIO data direction bit 2 RGPIO_DIR_DIR3: .equ 3 ; RGPIO data direction bit 3 RGPIO_DIR_DIR4: .equ 4 ; RGPIO data direction bit 4 RGPIO_DIR_DIR5: .equ 5 ; RGPIO data direction bit 5 RGPIO_DIR_DIR6: .equ 6 ; RGPIO data direction bit 6 RGPIO_DIR_DIR7: .equ 7 ; RGPIO data direction bit 7 RGPIO_DIR_DIR8: .equ 8 ; RGPIO data direction bit 8 RGPIO_DIR_DIR9: .equ 9 ; RGPIO data direction bit 9 RGPIO_DIR_DIR10: .equ 10 ; RGPIO data direction bit 10 RGPIO_DIR_DIR11: .equ 11 ; RGPIO data direction bit 11 RGPIO_DIR_DIR12: .equ 12 ; RGPIO data direction bit 12 RGPIO_DIR_DIR13: .equ 13 ; RGPIO data direction bit 13 RGPIO_DIR_DIR14: .equ 14 ; RGPIO data direction bit 14 RGPIO_DIR_DIR15: .equ 15 ; RGPIO data direction bit 15 ; bit position masks mRGPIO_DIR_DIR0: .equ %00000001 mRGPIO_DIR_DIR1: .equ %00000010 mRGPIO_DIR_DIR2: .equ %00000100 mRGPIO_DIR_DIR3: .equ %00001000 mRGPIO_DIR_DIR4: .equ %00010000 mRGPIO_DIR_DIR5: .equ %00100000 mRGPIO_DIR_DIR6: .equ %01000000 mRGPIO_DIR_DIR7: .equ %10000000 mRGPIO_DIR_DIR8: .equ %100000000 mRGPIO_DIR_DIR9: .equ %1000000000 mRGPIO_DIR_DIR10: .equ %10000000000 mRGPIO_DIR_DIR11: .equ %100000000000 mRGPIO_DIR_DIR12: .equ %1000000000000 mRGPIO_DIR_DIR13: .equ %10000000000000 mRGPIO_DIR_DIR14: .equ %100000000000000 mRGPIO_DIR_DIR15: .equ %1000000000000000 ;*** RGPIO_DATA - RGPIO Data Register; 0x00C00002 *** RGPIO_DATA: .equ $00C00002 ;*** RGPIO_DATA - RGPIO Data Register; 0x00C00002 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET RGPIO_DATA_DATA0: .equ 0 ; RGPIO data bit 0 RGPIO_DATA_DATA1: .equ 1 ; RGPIO data bit 1 RGPIO_DATA_DATA2: .equ 2 ; RGPIO data bit 2 RGPIO_DATA_DATA3: .equ 3 ; RGPIO data bit 3 RGPIO_DATA_DATA4: .equ 4 ; RGPIO data bit 4 RGPIO_DATA_DATA5: .equ 5 ; RGPIO data bit 5 RGPIO_DATA_DATA6: .equ 6 ; RGPIO data bit 6 RGPIO_DATA_DATA7: .equ 7 ; RGPIO data bit 7 RGPIO_DATA_DATA8: .equ 8 ; RGPIO data bit 8 RGPIO_DATA_DATA9: .equ 9 ; RGPIO data bit 9 RGPIO_DATA_DATA10: .equ 10 ; RGPIO data bit 10 RGPIO_DATA_DATA11: .equ 11 ; RGPIO data bit 11 RGPIO_DATA_DATA12: .equ 12 ; RGPIO data bit 12 RGPIO_DATA_DATA13: .equ 13 ; RGPIO data bit 13 RGPIO_DATA_DATA14: .equ 14 ; RGPIO data bit 14 RGPIO_DATA_DATA15: .equ 15 ; RGPIO data bit 15 ; bit position masks mRGPIO_DATA_DATA0: .equ %00000001 mRGPIO_DATA_DATA1: .equ %00000010 mRGPIO_DATA_DATA2: .equ %00000100 mRGPIO_DATA_DATA3: .equ %00001000 mRGPIO_DATA_DATA4: .equ %00010000 mRGPIO_DATA_DATA5: .equ %00100000 mRGPIO_DATA_DATA6: .equ %01000000 mRGPIO_DATA_DATA7: .equ %10000000 mRGPIO_DATA_DATA8: .equ %100000000 mRGPIO_DATA_DATA9: .equ %1000000000 mRGPIO_DATA_DATA10: .equ %10000000000 mRGPIO_DATA_DATA11: .equ %100000000000 mRGPIO_DATA_DATA12: .equ %1000000000000 mRGPIO_DATA_DATA13: .equ %10000000000000 mRGPIO_DATA_DATA14: .equ %100000000000000 mRGPIO_DATA_DATA15: .equ %1000000000000000 ;*** RGPIO_ENB - RGPIO Pin Enable Register; 0x00C00004 *** RGPIO_ENB: .equ $00C00004 ;*** RGPIO_ENB - RGPIO Pin Enable Register; 0x00C00004 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET RGPIO_ENB_ENB0: .equ 0 ; RGPIO enable bit 0 RGPIO_ENB_ENB1: .equ 1 ; RGPIO enable bit 1 RGPIO_ENB_ENB2: .equ 2 ; RGPIO enable bit 2 RGPIO_ENB_ENB3: .equ 3 ; RGPIO enable bit 3 RGPIO_ENB_ENB4: .equ 4 ; RGPIO enable bit 4 RGPIO_ENB_ENB5: .equ 5 ; RGPIO enable bit 5 RGPIO_ENB_ENB6: .equ 6 ; RGPIO enable bit 6 RGPIO_ENB_ENB7: .equ 7 ; RGPIO enable bit 7 RGPIO_ENB_ENB8: .equ 8 ; RGPIO enable bit 8 RGPIO_ENB_ENB9: .equ 9 ; RGPIO enable bit 9 RGPIO_ENB_ENB10: .equ 10 ; RGPIO enable bit 10 RGPIO_ENB_ENB11: .equ 11 ; RGPIO enable bit 11 RGPIO_ENB_ENB12: .equ 12 ; RGPIO enable bit 12 RGPIO_ENB_ENB13: .equ 13 ; RGPIO enable bit 13 RGPIO_ENB_ENB14: .equ 14 ; RGPIO enable bit 14 RGPIO_ENB_ENB15: .equ 15 ; RGPIO enable bit 15 ; bit position masks mRGPIO_ENB_ENB0: .equ %00000001 mRGPIO_ENB_ENB1: .equ %00000010 mRGPIO_ENB_ENB2: .equ %00000100 mRGPIO_ENB_ENB3: .equ %00001000 mRGPIO_ENB_ENB4: .equ %00010000 mRGPIO_ENB_ENB5: .equ %00100000 mRGPIO_ENB_ENB6: .equ %01000000 mRGPIO_ENB_ENB7: .equ %10000000 mRGPIO_ENB_ENB8: .equ %100000000 mRGPIO_ENB_ENB9: .equ %1000000000 mRGPIO_ENB_ENB10: .equ %10000000000 mRGPIO_ENB_ENB11: .equ %100000000000 mRGPIO_ENB_ENB12: .equ %1000000000000 mRGPIO_ENB_ENB13: .equ %10000000000000 mRGPIO_ENB_ENB14: .equ %100000000000000 mRGPIO_ENB_ENB15: .equ %1000000000000000 ;*** RGPIO_CLR - RGPIO Clear Data Register; 0x00C00006 *** RGPIO_CLR: .equ $00C00006 ;*** RGPIO_CLR - RGPIO Clear Data Register; 0x00C00006 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET RGPIO_CLR_CLR0: .equ 0 ; RGPIO clear data bit 0 RGPIO_CLR_CLR1: .equ 1 ; RGPIO clear data bit 1 RGPIO_CLR_CLR2: .equ 2 ; RGPIO clear data bit 2 RGPIO_CLR_CLR3: .equ 3 ; RGPIO clear data bit 3 RGPIO_CLR_CLR4: .equ 4 ; RGPIO clear data bit 4 RGPIO_CLR_CLR5: .equ 5 ; RGPIO clear data bit 5 RGPIO_CLR_CLR6: .equ 6 ; RGPIO clear data bit 6 RGPIO_CLR_CLR7: .equ 7 ; RGPIO clear data bit 7 RGPIO_CLR_CLR8: .equ 8 ; RGPIO clear data bit 8 RGPIO_CLR_CLR9: .equ 9 ; RGPIO clear data bit 9 RGPIO_CLR_CLR10: .equ 10 ; RGPIO clear data bit 10 RGPIO_CLR_CLR11: .equ 11 ; RGPIO clear data bit 11 RGPIO_CLR_CLR12: .equ 12 ; RGPIO clear data bit 12 RGPIO_CLR_CLR13: .equ 13 ; RGPIO clear data bit 13 RGPIO_CLR_CLR14: .equ 14 ; RGPIO clear data bit 14 RGPIO_CLR_CLR15: .equ 15 ; RGPIO clear data bit 15 ; bit position masks mRGPIO_CLR_CLR0: .equ %00000001 mRGPIO_CLR_CLR1: .equ %00000010 mRGPIO_CLR_CLR2: .equ %00000100 mRGPIO_CLR_CLR3: .equ %00001000 mRGPIO_CLR_CLR4: .equ %00010000 mRGPIO_CLR_CLR5: .equ %00100000 mRGPIO_CLR_CLR6: .equ %01000000 mRGPIO_CLR_CLR7: .equ %10000000 mRGPIO_CLR_CLR8: .equ %100000000 mRGPIO_CLR_CLR9: .equ %1000000000 mRGPIO_CLR_CLR10: .equ %10000000000 mRGPIO_CLR_CLR11: .equ %100000000000 mRGPIO_CLR_CLR12: .equ %1000000000000 mRGPIO_CLR_CLR13: .equ %10000000000000 mRGPIO_CLR_CLR14: .equ %100000000000000 mRGPIO_CLR_CLR15: .equ %1000000000000000 ;*** RGPIO_SET - RGPIO Set Data Register; 0x00C0000A *** RGPIO_SET: .equ $00C0000A ;*** RGPIO_SET - RGPIO Set Data Register; 0x00C0000A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET RGPIO_SET_SET0: .equ 0 ; RGPIO set data bit 0 RGPIO_SET_SET1: .equ 1 ; RGPIO set data bit 1 RGPIO_SET_SET2: .equ 2 ; RGPIO set data bit 2 RGPIO_SET_SET3: .equ 3 ; RGPIO set data bit 3 RGPIO_SET_SET4: .equ 4 ; RGPIO set data bit 4 RGPIO_SET_SET5: .equ 5 ; RGPIO set data bit 5 RGPIO_SET_SET6: .equ 6 ; RGPIO set data bit 6 RGPIO_SET_SET7: .equ 7 ; RGPIO set data bit 7 RGPIO_SET_SET8: .equ 8 ; RGPIO set data bit 8 RGPIO_SET_SET9: .equ 9 ; RGPIO set data bit 9 RGPIO_SET_SET10: .equ 10 ; RGPIO set data bit 10 RGPIO_SET_SET11: .equ 11 ; RGPIO set data bit 11 RGPIO_SET_SET12: .equ 12 ; RGPIO set data bit 12 RGPIO_SET_SET13: .equ 13 ; RGPIO set data bit 13 RGPIO_SET_SET14: .equ 14 ; RGPIO set data bit 14 RGPIO_SET_SET15: .equ 15 ; RGPIO set data bit 15 ; bit position masks mRGPIO_SET_SET0: .equ %00000001 mRGPIO_SET_SET1: .equ %00000010 mRGPIO_SET_SET2: .equ %00000100 mRGPIO_SET_SET3: .equ %00001000 mRGPIO_SET_SET4: .equ %00010000 mRGPIO_SET_SET5: .equ %00100000 mRGPIO_SET_SET6: .equ %01000000 mRGPIO_SET_SET7: .equ %10000000 mRGPIO_SET_SET8: .equ %100000000 mRGPIO_SET_SET9: .equ %1000000000 mRGPIO_SET_SET10: .equ %10000000000 mRGPIO_SET_SET11: .equ %100000000000 mRGPIO_SET_SET12: .equ %1000000000000 mRGPIO_SET_SET13: .equ %10000000000000 mRGPIO_SET_SET14: .equ %100000000000000 mRGPIO_SET_SET15: .equ %1000000000000000 ;*** RGPIO_TOG - RGPIO Toggle Data Register; 0x00C0000E *** RGPIO_TOG: .equ $00C0000E ;*** RGPIO_TOG - RGPIO Toggle Data Register; 0x00C0000E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET RGPIO_TOG_TOG0: .equ 0 ; RGPIO toggle data bit 0 RGPIO_TOG_TOG1: .equ 1 ; RGPIO toggle data bit 1 RGPIO_TOG_TOG2: .equ 2 ; RGPIO toggle data bit 2 RGPIO_TOG_TOG3: .equ 3 ; RGPIO toggle data bit 3 RGPIO_TOG_TOG4: .equ 4 ; RGPIO toggle data bit 4 RGPIO_TOG_TOG5: .equ 5 ; RGPIO toggle data bit 5 RGPIO_TOG_TOG6: .equ 6 ; RGPIO toggle data bit 6 RGPIO_TOG_TOG7: .equ 7 ; RGPIO toggle data bit 7 RGPIO_TOG_TOG8: .equ 8 ; RGPIO toggle data bit 8 RGPIO_TOG_TOG9: .equ 9 ; RGPIO toggle data bit 9 RGPIO_TOG_TOG10: .equ 10 ; RGPIO toggle data bit 10 RGPIO_TOG_TOG11: .equ 11 ; RGPIO toggle data bit 11 RGPIO_TOG_TOG12: .equ 12 ; RGPIO toggle data bit 12 RGPIO_TOG_TOG13: .equ 13 ; RGPIO toggle data bit 13 RGPIO_TOG_TOG14: .equ 14 ; RGPIO toggle data bit 14 RGPIO_TOG_TOG15: .equ 15 ; RGPIO toggle data bit 15 ; bit position masks mRGPIO_TOG_TOG0: .equ %00000001 mRGPIO_TOG_TOG1: .equ %00000010 mRGPIO_TOG_TOG2: .equ %00000100 mRGPIO_TOG_TOG3: .equ %00001000 mRGPIO_TOG_TOG4: .equ %00010000 mRGPIO_TOG_TOG5: .equ %00100000 mRGPIO_TOG_TOG6: .equ %01000000 mRGPIO_TOG_TOG7: .equ %10000000 mRGPIO_TOG_TOG8: .equ %100000000 mRGPIO_TOG_TOG9: .equ %1000000000 mRGPIO_TOG_TOG10: .equ %10000000000 mRGPIO_TOG_TOG11: .equ %100000000000 mRGPIO_TOG_TOG12: .equ %1000000000000 mRGPIO_TOG_TOG13: .equ %10000000000000 mRGPIO_TOG_TOG14: .equ %100000000000000 mRGPIO_TOG_TOG15: .equ %1000000000000000 ;*** PTAD - Port A Data Register; 0xFFFF8000 *** PTAD: .equ $FFFF8000 ;*** PTAD - Port A Data Register; 0xFFFF8000 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTAD_PTAD0: .equ 0 ; Port A Data Register Bit 0 PTAD_PTAD1: .equ 1 ; Port A Data Register Bit 1 PTAD_PTAD2: .equ 2 ; Port A Data Register Bit 2 PTAD_PTAD3: .equ 3 ; Port A Data Register Bit 3 PTAD_PTAD4: .equ 4 ; Port A Data Register Bit 4 PTAD_PTAD5: .equ 5 ; Port A Data Register Bit 5 PTAD_PTAD6: .equ 6 ; Port A Data Register Bit 6 PTAD_PTAD7: .equ 7 ; Port A Data Register Bit 7 ; bit position masks mPTAD_PTAD0: .equ %00000001 mPTAD_PTAD1: .equ %00000010 mPTAD_PTAD2: .equ %00000100 mPTAD_PTAD3: .equ %00001000 mPTAD_PTAD4: .equ %00010000 mPTAD_PTAD5: .equ %00100000 mPTAD_PTAD6: .equ %01000000 mPTAD_PTAD7: .equ %10000000 ;*** PTADD - Port A Data Direction Register; 0xFFFF8001 *** PTADD: .equ $FFFF8001 ;*** PTADD - Port A Data Direction Register; 0xFFFF8001 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTADD_PTADD0: .equ 0 ; Data Direction for Port A Bit 0 PTADD_PTADD1: .equ 1 ; Data Direction for Port A Bit 1 PTADD_PTADD2: .equ 2 ; Data Direction for Port A Bit 2 PTADD_PTADD3: .equ 3 ; Data Direction for Port A Bit 3 PTADD_PTADD4: .equ 4 ; Data Direction for Port A Bit 4 PTADD_PTADD5: .equ 5 ; Data Direction for Port A Bit 5 PTADD_PTADD6: .equ 6 ; Data Direction for Port A Bit 6 PTADD_PTADD7: .equ 7 ; Data Direction for Port A Bit 7 ; bit position masks mPTADD_PTADD0: .equ %00000001 mPTADD_PTADD1: .equ %00000010 mPTADD_PTADD2: .equ %00000100 mPTADD_PTADD3: .equ %00001000 mPTADD_PTADD4: .equ %00010000 mPTADD_PTADD5: .equ %00100000 mPTADD_PTADD6: .equ %01000000 mPTADD_PTADD7: .equ %10000000 ;*** PTBD - Port B Data Register; 0xFFFF8002 *** PTBD: .equ $FFFF8002 ;*** PTBD - Port B Data Register; 0xFFFF8002 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTBD_PTBD0: .equ 0 ; Port B Data Register Bit 0 PTBD_PTBD1: .equ 1 ; Port B Data Register Bit 1 PTBD_PTBD2: .equ 2 ; Port B Data Register Bit 2 PTBD_PTBD3: .equ 3 ; Port B Data Register Bit 3 PTBD_PTBD4: .equ 4 ; Port B Data Register Bit 4 PTBD_PTBD5: .equ 5 ; Port B Data Register Bit 5 PTBD_PTBD6: .equ 6 ; Port B Data Register Bit 6 PTBD_PTBD7: .equ 7 ; Port B Data Register Bit 7 ; bit position masks mPTBD_PTBD0: .equ %00000001 mPTBD_PTBD1: .equ %00000010 mPTBD_PTBD2: .equ %00000100 mPTBD_PTBD3: .equ %00001000 mPTBD_PTBD4: .equ %00010000 mPTBD_PTBD5: .equ %00100000 mPTBD_PTBD6: .equ %01000000 mPTBD_PTBD7: .equ %10000000 ;*** PTBDD - Port B Data Direction Register; 0xFFFF8003 *** PTBDD: .equ $FFFF8003 ;*** PTBDD - Port B Data Direction Register; 0xFFFF8003 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTBDD_PTBDD0: .equ 0 ; Data Direction for Port B Bit 0 PTBDD_PTBDD1: .equ 1 ; Data Direction for Port B Bit 1 PTBDD_PTBDD2: .equ 2 ; Data Direction for Port B Bit 2 PTBDD_PTBDD3: .equ 3 ; Data Direction for Port B Bit 3 PTBDD_PTBDD4: .equ 4 ; Data Direction for Port B Bit 4 PTBDD_PTBDD5: .equ 5 ; Data Direction for Port B Bit 5 PTBDD_PTBDD6: .equ 6 ; Data Direction for Port B Bit 6 PTBDD_PTBDD7: .equ 7 ; Data Direction for Port B Bit 7 ; bit position masks mPTBDD_PTBDD0: .equ %00000001 mPTBDD_PTBDD1: .equ %00000010 mPTBDD_PTBDD2: .equ %00000100 mPTBDD_PTBDD3: .equ %00001000 mPTBDD_PTBDD4: .equ %00010000 mPTBDD_PTBDD5: .equ %00100000 mPTBDD_PTBDD6: .equ %01000000 mPTBDD_PTBDD7: .equ %10000000 ;*** PTCD - Port C Data Register; 0xFFFF8004 *** PTCD: .equ $FFFF8004 ;*** PTCD - Port C Data Register; 0xFFFF8004 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTCD_PTCD0: .equ 0 ; Port C Data Register Bit 0 PTCD_PTCD1: .equ 1 ; Port C Data Register Bit 1 PTCD_PTCD2: .equ 2 ; Port C Data Register Bit 2 PTCD_PTCD3: .equ 3 ; Port C Data Register Bit 3 PTCD_PTCD4: .equ 4 ; Port C Data Register Bit 4 PTCD_PTCD5: .equ 5 ; Port C Data Register Bit 5 PTCD_PTCD6: .equ 6 ; Port C Data Register Bit 6 PTCD_PTCD7: .equ 7 ; Port C Data Register Bit 7 ; bit position masks mPTCD_PTCD0: .equ %00000001 mPTCD_PTCD1: .equ %00000010 mPTCD_PTCD2: .equ %00000100 mPTCD_PTCD3: .equ %00001000 mPTCD_PTCD4: .equ %00010000 mPTCD_PTCD5: .equ %00100000 mPTCD_PTCD6: .equ %01000000 mPTCD_PTCD7: .equ %10000000 ;*** PTCDD - Port C Data Direction Register; 0xFFFF8005 *** PTCDD: .equ $FFFF8005 ;*** PTCDD - Port C Data Direction Register; 0xFFFF8005 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTCDD_PTCDD0: .equ 0 ; Data Direction for Port C Bit 0 PTCDD_PTCDD1: .equ 1 ; Data Direction for Port C Bit 1 PTCDD_PTCDD2: .equ 2 ; Data Direction for Port C Bit 2 PTCDD_PTCDD3: .equ 3 ; Data Direction for Port C Bit 3 PTCDD_PTCDD4: .equ 4 ; Data Direction for Port C Bit 4 PTCDD_PTCDD5: .equ 5 ; Data Direction for Port C Bit 5 PTCDD_PTCDD6: .equ 6 ; Data Direction for Port C Bit 6 PTCDD_PTCDD7: .equ 7 ; Data Direction for Port C Bit 7 ; bit position masks mPTCDD_PTCDD0: .equ %00000001 mPTCDD_PTCDD1: .equ %00000010 mPTCDD_PTCDD2: .equ %00000100 mPTCDD_PTCDD3: .equ %00001000 mPTCDD_PTCDD4: .equ %00010000 mPTCDD_PTCDD5: .equ %00100000 mPTCDD_PTCDD6: .equ %01000000 mPTCDD_PTCDD7: .equ %10000000 ;*** PTDD - Port D Data Register; 0xFFFF8006 *** PTDD: .equ $FFFF8006 ;*** PTDD - Port D Data Register; 0xFFFF8006 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTDD_PTDD0: .equ 0 ; Port D Data Register Bit 0 PTDD_PTDD1: .equ 1 ; Port D Data Register Bit 1 PTDD_PTDD2: .equ 2 ; Port D Data Register Bit 2 PTDD_PTDD3: .equ 3 ; Port D Data Register Bit 3 PTDD_PTDD4: .equ 4 ; Port D Data Register Bit 4 PTDD_PTDD5: .equ 5 ; Port D Data Register Bit 5 PTDD_PTDD6: .equ 6 ; Port D Data Register Bit 6 PTDD_PTDD7: .equ 7 ; Port D Data Register Bit 7 ; bit position masks mPTDD_PTDD0: .equ %00000001 mPTDD_PTDD1: .equ %00000010 mPTDD_PTDD2: .equ %00000100 mPTDD_PTDD3: .equ %00001000 mPTDD_PTDD4: .equ %00010000 mPTDD_PTDD5: .equ %00100000 mPTDD_PTDD6: .equ %01000000 mPTDD_PTDD7: .equ %10000000 ;*** PTDDD - Port D Data Direction Register; 0xFFFF8007 *** PTDDD: .equ $FFFF8007 ;*** PTDDD - Port D Data Direction Register; 0xFFFF8007 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTDDD_PTDDD0: .equ 0 ; Data Direction for Port D Bit 0 PTDDD_PTDDD1: .equ 1 ; Data Direction for Port D Bit 1 PTDDD_PTDDD2: .equ 2 ; Data Direction for Port D Bit 2 PTDDD_PTDDD3: .equ 3 ; Data Direction for Port D Bit 3 PTDDD_PTDDD4: .equ 4 ; Data Direction for Port D Bit 4 PTDDD_PTDDD5: .equ 5 ; Data Direction for Port D Bit 5 PTDDD_PTDDD6: .equ 6 ; Data Direction for Port D Bit 6 PTDDD_PTDDD7: .equ 7 ; Data Direction for Port D Bit 7 ; bit position masks mPTDDD_PTDDD0: .equ %00000001 mPTDDD_PTDDD1: .equ %00000010 mPTDDD_PTDDD2: .equ %00000100 mPTDDD_PTDDD3: .equ %00001000 mPTDDD_PTDDD4: .equ %00010000 mPTDDD_PTDDD5: .equ %00100000 mPTDDD_PTDDD6: .equ %01000000 mPTDDD_PTDDD7: .equ %10000000 ;*** DACDAT0 - DAC Data 0 Register; 0xFFFF8010 *** DACDAT0: .equ $FFFF8010 ;*** DACDAT0 - DAC Data 0 Register; 0xFFFF8010 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT0_DACDAT00: .equ 0 ; Buffer Data 0, bit 0 DACDAT0_DACDAT01: .equ 1 ; Buffer Data 0, bit 1 DACDAT0_DACDAT02: .equ 2 ; Buffer Data 0, bit 2 DACDAT0_DACDAT03: .equ 3 ; Buffer Data 0, bit 3 DACDAT0_DACDAT04: .equ 4 ; Buffer Data 0, bit 4 DACDAT0_DACDAT05: .equ 5 ; Buffer Data 0, bit 5 DACDAT0_DACDAT06: .equ 6 ; Buffer Data 0, bit 6 DACDAT0_DACDAT07: .equ 7 ; Buffer Data 0, bit 7 DACDAT0_DACDAT08: .equ 8 ; Buffer Data 0, bit 8 DACDAT0_DACDAT09: .equ 9 ; Buffer Data 0, bit 9 DACDAT0_DACDAT010: .equ 10 ; Buffer Data 0, bit 10 DACDAT0_DACDAT011: .equ 11 ; Buffer Data 0, bit 11 ; bit position masks mDACDAT0_DACDAT00: .equ %00000001 mDACDAT0_DACDAT01: .equ %00000010 mDACDAT0_DACDAT02: .equ %00000100 mDACDAT0_DACDAT03: .equ %00001000 mDACDAT0_DACDAT04: .equ %00010000 mDACDAT0_DACDAT05: .equ %00100000 mDACDAT0_DACDAT06: .equ %01000000 mDACDAT0_DACDAT07: .equ %10000000 mDACDAT0_DACDAT08: .equ %100000000 mDACDAT0_DACDAT09: .equ %1000000000 mDACDAT0_DACDAT010: .equ %10000000000 mDACDAT0_DACDAT011: .equ %100000000000 ;*** DACDAT0H - DAC Data 0 High Register; 0xFFFF8010 *** DACDAT0H: .equ $FFFF8010 ;*** DACDAT0H - DAC Data 0 High Register; 0xFFFF8010 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT0H_DACDAT08: .equ 0 ; Buffer Data 0 High, bit 8 DACDAT0H_DACDAT09: .equ 1 ; Buffer Data 0 High, bit 9 DACDAT0H_DACDAT010: .equ 2 ; Buffer Data 0 High, bit 10 DACDAT0H_DACDAT011: .equ 3 ; Buffer Data 0 High, bit 11 ; bit position masks mDACDAT0H_DACDAT08: .equ %00000001 mDACDAT0H_DACDAT09: .equ %00000010 mDACDAT0H_DACDAT010: .equ %00000100 mDACDAT0H_DACDAT011: .equ %00001000 ;*** DACDAT0L - DAC Data 0 Low Register; 0xFFFF8011 *** DACDAT0L: .equ $FFFF8011 ;*** DACDAT0L - DAC Data 0 Low Register; 0xFFFF8011 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT0L_DACDAT00: .equ 0 ; Buffer Data 0 Low, bit 0 DACDAT0L_DACDAT01: .equ 1 ; Buffer Data 0 Low, bit 1 DACDAT0L_DACDAT02: .equ 2 ; Buffer Data 0 Low, bit 2 DACDAT0L_DACDAT03: .equ 3 ; Buffer Data 0 Low, bit 3 DACDAT0L_DACDAT04: .equ 4 ; Buffer Data 0 Low, bit 4 DACDAT0L_DACDAT05: .equ 5 ; Buffer Data 0 Low, bit 5 DACDAT0L_DACDAT06: .equ 6 ; Buffer Data 0 Low, bit 6 DACDAT0L_DACDAT07: .equ 7 ; Buffer Data 0 Low, bit 7 ; bit position masks mDACDAT0L_DACDAT00: .equ %00000001 mDACDAT0L_DACDAT01: .equ %00000010 mDACDAT0L_DACDAT02: .equ %00000100 mDACDAT0L_DACDAT03: .equ %00001000 mDACDAT0L_DACDAT04: .equ %00010000 mDACDAT0L_DACDAT05: .equ %00100000 mDACDAT0L_DACDAT06: .equ %01000000 mDACDAT0L_DACDAT07: .equ %10000000 ;*** DACDAT1 - DAC Data 1 Register; 0xFFFF8012 *** DACDAT1: .equ $FFFF8012 ;*** DACDAT1 - DAC Data 1 Register; 0xFFFF8012 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT1_DACDAT10: .equ 0 ; Buffer Data 1, bit 0 DACDAT1_DACDAT11: .equ 1 ; Buffer Data 1, bit 1 DACDAT1_DACDAT12: .equ 2 ; Buffer Data 1, bit 2 DACDAT1_DACDAT13: .equ 3 ; Buffer Data 1, bit 3 DACDAT1_DACDAT14: .equ 4 ; Buffer Data 1, bit 4 DACDAT1_DACDAT15: .equ 5 ; Buffer Data 1, bit 5 DACDAT1_DACDAT16: .equ 6 ; Buffer Data 1, bit 6 DACDAT1_DACDAT17: .equ 7 ; Buffer Data 1, bit 7 DACDAT1_DACDAT18: .equ 8 ; Buffer Data 1, bit 8 DACDAT1_DACDAT19: .equ 9 ; Buffer Data 1, bit 9 DACDAT1_DACDAT110: .equ 10 ; Buffer Data 1, bit 10 DACDAT1_DACDAT111: .equ 11 ; Buffer Data 1, bit 11 ; bit position masks mDACDAT1_DACDAT10: .equ %00000001 mDACDAT1_DACDAT11: .equ %00000010 mDACDAT1_DACDAT12: .equ %00000100 mDACDAT1_DACDAT13: .equ %00001000 mDACDAT1_DACDAT14: .equ %00010000 mDACDAT1_DACDAT15: .equ %00100000 mDACDAT1_DACDAT16: .equ %01000000 mDACDAT1_DACDAT17: .equ %10000000 mDACDAT1_DACDAT18: .equ %100000000 mDACDAT1_DACDAT19: .equ %1000000000 mDACDAT1_DACDAT110: .equ %10000000000 mDACDAT1_DACDAT111: .equ %100000000000 ;*** DACDAT1H - DAC Data 1 High Register; 0xFFFF8012 *** DACDAT1H: .equ $FFFF8012 ;*** DACDAT1H - DAC Data 1 High Register; 0xFFFF8012 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT1H_DACDAT18: .equ 0 ; Buffer Data 1 High, bit 8 DACDAT1H_DACDAT19: .equ 1 ; Buffer Data 1 High, bit 9 DACDAT1H_DACDAT110: .equ 2 ; Buffer Data 1 High, bit 10 DACDAT1H_DACDAT111: .equ 3 ; Buffer Data 1 High, bit 11 ; bit position masks mDACDAT1H_DACDAT18: .equ %00000001 mDACDAT1H_DACDAT19: .equ %00000010 mDACDAT1H_DACDAT110: .equ %00000100 mDACDAT1H_DACDAT111: .equ %00001000 ;*** DACDAT1L - DAC Data 1 Low Register; 0xFFFF8013 *** DACDAT1L: .equ $FFFF8013 ;*** DACDAT1L - DAC Data 1 Low Register; 0xFFFF8013 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT1L_DACDAT10: .equ 0 ; Buffer Data 1 Low, bit 0 DACDAT1L_DACDAT11: .equ 1 ; Buffer Data 1 Low, bit 1 DACDAT1L_DACDAT12: .equ 2 ; Buffer Data 1 Low, bit 2 DACDAT1L_DACDAT13: .equ 3 ; Buffer Data 1 Low, bit 3 DACDAT1L_DACDAT14: .equ 4 ; Buffer Data 1 Low, bit 4 DACDAT1L_DACDAT15: .equ 5 ; Buffer Data 1 Low, bit 5 DACDAT1L_DACDAT16: .equ 6 ; Buffer Data 1 Low, bit 6 DACDAT1L_DACDAT17: .equ 7 ; Buffer Data 1 Low, bit 7 ; bit position masks mDACDAT1L_DACDAT10: .equ %00000001 mDACDAT1L_DACDAT11: .equ %00000010 mDACDAT1L_DACDAT12: .equ %00000100 mDACDAT1L_DACDAT13: .equ %00001000 mDACDAT1L_DACDAT14: .equ %00010000 mDACDAT1L_DACDAT15: .equ %00100000 mDACDAT1L_DACDAT16: .equ %01000000 mDACDAT1L_DACDAT17: .equ %10000000 ;*** DACDAT2 - DAC Data 2 Register; 0xFFFF8014 *** DACDAT2: .equ $FFFF8014 ;*** DACDAT2 - DAC Data 2 Register; 0xFFFF8014 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT2_DACDAT20: .equ 0 ; Buffer Data 2, bit 0 DACDAT2_DACDAT21: .equ 1 ; Buffer Data 2, bit 1 DACDAT2_DACDAT22: .equ 2 ; Buffer Data 2, bit 2 DACDAT2_DACDAT23: .equ 3 ; Buffer Data 2, bit 3 DACDAT2_DACDAT24: .equ 4 ; Buffer Data 2, bit 4 DACDAT2_DACDAT25: .equ 5 ; Buffer Data 2, bit 5 DACDAT2_DACDAT26: .equ 6 ; Buffer Data 2, bit 6 DACDAT2_DACDAT27: .equ 7 ; Buffer Data 2, bit 7 DACDAT2_DACDAT28: .equ 8 ; Buffer Data 2, bit 8 DACDAT2_DACDAT29: .equ 9 ; Buffer Data 2, bit 9 DACDAT2_DACDAT210: .equ 10 ; Buffer Data 2, bit 10 DACDAT2_DACDAT211: .equ 11 ; Buffer Data 2, bit 11 ; bit position masks mDACDAT2_DACDAT20: .equ %00000001 mDACDAT2_DACDAT21: .equ %00000010 mDACDAT2_DACDAT22: .equ %00000100 mDACDAT2_DACDAT23: .equ %00001000 mDACDAT2_DACDAT24: .equ %00010000 mDACDAT2_DACDAT25: .equ %00100000 mDACDAT2_DACDAT26: .equ %01000000 mDACDAT2_DACDAT27: .equ %10000000 mDACDAT2_DACDAT28: .equ %100000000 mDACDAT2_DACDAT29: .equ %1000000000 mDACDAT2_DACDAT210: .equ %10000000000 mDACDAT2_DACDAT211: .equ %100000000000 ;*** DACDAT2H - DAC Data 2 High Register; 0xFFFF8014 *** DACDAT2H: .equ $FFFF8014 ;*** DACDAT2H - DAC Data 2 High Register; 0xFFFF8014 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT2H_DACDAT28: .equ 0 ; Buffer Data 2 High, bit 8 DACDAT2H_DACDAT29: .equ 1 ; Buffer Data 2 High, bit 9 DACDAT2H_DACDAT210: .equ 2 ; Buffer Data 2 High, bit 10 DACDAT2H_DACDAT211: .equ 3 ; Buffer Data 2 High, bit 11 ; bit position masks mDACDAT2H_DACDAT28: .equ %00000001 mDACDAT2H_DACDAT29: .equ %00000010 mDACDAT2H_DACDAT210: .equ %00000100 mDACDAT2H_DACDAT211: .equ %00001000 ;*** DACDAT2L - DAC Data 2 Low Register; 0xFFFF8015 *** DACDAT2L: .equ $FFFF8015 ;*** DACDAT2L - DAC Data 2 Low Register; 0xFFFF8015 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT2L_DACDAT20: .equ 0 ; Buffer Data 2 Low, bit 0 DACDAT2L_DACDAT21: .equ 1 ; Buffer Data 2 Low, bit 1 DACDAT2L_DACDAT22: .equ 2 ; Buffer Data 2 Low, bit 2 DACDAT2L_DACDAT23: .equ 3 ; Buffer Data 2 Low, bit 3 DACDAT2L_DACDAT24: .equ 4 ; Buffer Data 2 Low, bit 4 DACDAT2L_DACDAT25: .equ 5 ; Buffer Data 2 Low, bit 5 DACDAT2L_DACDAT26: .equ 6 ; Buffer Data 2 Low, bit 6 DACDAT2L_DACDAT27: .equ 7 ; Buffer Data 2 Low, bit 7 ; bit position masks mDACDAT2L_DACDAT20: .equ %00000001 mDACDAT2L_DACDAT21: .equ %00000010 mDACDAT2L_DACDAT22: .equ %00000100 mDACDAT2L_DACDAT23: .equ %00001000 mDACDAT2L_DACDAT24: .equ %00010000 mDACDAT2L_DACDAT25: .equ %00100000 mDACDAT2L_DACDAT26: .equ %01000000 mDACDAT2L_DACDAT27: .equ %10000000 ;*** DACDAT3 - DAC Data 3 Register; 0xFFFF8016 *** DACDAT3: .equ $FFFF8016 ;*** DACDAT3 - DAC Data 3 Register; 0xFFFF8016 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT3_DACDAT30: .equ 0 ; Buffer Data 3, bit 0 DACDAT3_DACDAT31: .equ 1 ; Buffer Data 3, bit 1 DACDAT3_DACDAT32: .equ 2 ; Buffer Data 3, bit 2 DACDAT3_DACDAT33: .equ 3 ; Buffer Data 3, bit 3 DACDAT3_DACDAT34: .equ 4 ; Buffer Data 3, bit 4 DACDAT3_DACDAT35: .equ 5 ; Buffer Data 3, bit 5 DACDAT3_DACDAT36: .equ 6 ; Buffer Data 3, bit 6 DACDAT3_DACDAT37: .equ 7 ; Buffer Data 3, bit 7 DACDAT3_DACDAT38: .equ 8 ; Buffer Data 3, bit 8 DACDAT3_DACDAT39: .equ 9 ; Buffer Data 3, bit 9 DACDAT3_DACDAT310: .equ 10 ; Buffer Data 3, bit 10 DACDAT3_DACDAT311: .equ 11 ; Buffer Data 3, bit 11 ; bit position masks mDACDAT3_DACDAT30: .equ %00000001 mDACDAT3_DACDAT31: .equ %00000010 mDACDAT3_DACDAT32: .equ %00000100 mDACDAT3_DACDAT33: .equ %00001000 mDACDAT3_DACDAT34: .equ %00010000 mDACDAT3_DACDAT35: .equ %00100000 mDACDAT3_DACDAT36: .equ %01000000 mDACDAT3_DACDAT37: .equ %10000000 mDACDAT3_DACDAT38: .equ %100000000 mDACDAT3_DACDAT39: .equ %1000000000 mDACDAT3_DACDAT310: .equ %10000000000 mDACDAT3_DACDAT311: .equ %100000000000 ;*** DACDAT3H - DAC Data 3 High Register; 0xFFFF8016 *** DACDAT3H: .equ $FFFF8016 ;*** DACDAT3H - DAC Data 3 High Register; 0xFFFF8016 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT3H_DACDAT38: .equ 0 ; Buffer Data 3 High, bit 8 DACDAT3H_DACDAT39: .equ 1 ; Buffer Data 3 High, bit 9 DACDAT3H_DACDAT310: .equ 2 ; Buffer Data 3 High, bit 10 DACDAT3H_DACDAT311: .equ 3 ; Buffer Data 3 High, bit 11 ; bit position masks mDACDAT3H_DACDAT38: .equ %00000001 mDACDAT3H_DACDAT39: .equ %00000010 mDACDAT3H_DACDAT310: .equ %00000100 mDACDAT3H_DACDAT311: .equ %00001000 ;*** DACDAT3L - DAC Data 3 Low Register; 0xFFFF8017 *** DACDAT3L: .equ $FFFF8017 ;*** DACDAT3L - DAC Data 3 Low Register; 0xFFFF8017 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT3L_DACDAT30: .equ 0 ; Buffer Data 3 Low, bit 0 DACDAT3L_DACDAT31: .equ 1 ; Buffer Data 3 Low, bit 1 DACDAT3L_DACDAT32: .equ 2 ; Buffer Data 3 Low, bit 2 DACDAT3L_DACDAT33: .equ 3 ; Buffer Data 3 Low, bit 3 DACDAT3L_DACDAT34: .equ 4 ; Buffer Data 3 Low, bit 4 DACDAT3L_DACDAT35: .equ 5 ; Buffer Data 3 Low, bit 5 DACDAT3L_DACDAT36: .equ 6 ; Buffer Data 3 Low, bit 6 DACDAT3L_DACDAT37: .equ 7 ; Buffer Data 3 Low, bit 7 ; bit position masks mDACDAT3L_DACDAT30: .equ %00000001 mDACDAT3L_DACDAT31: .equ %00000010 mDACDAT3L_DACDAT32: .equ %00000100 mDACDAT3L_DACDAT33: .equ %00001000 mDACDAT3L_DACDAT34: .equ %00010000 mDACDAT3L_DACDAT35: .equ %00100000 mDACDAT3L_DACDAT36: .equ %01000000 mDACDAT3L_DACDAT37: .equ %10000000 ;*** DACDAT4 - DAC Data 4 Register; 0xFFFF8018 *** DACDAT4: .equ $FFFF8018 ;*** DACDAT4 - DAC Data 4 Register; 0xFFFF8018 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT4_DACDAT40: .equ 0 ; Buffer Data 3, bit 0 DACDAT4_DACDAT41: .equ 1 ; Buffer Data 3, bit 1 DACDAT4_DACDAT42: .equ 2 ; Buffer Data 3, bit 2 DACDAT4_DACDAT43: .equ 3 ; Buffer Data 3, bit 3 DACDAT4_DACDAT44: .equ 4 ; Buffer Data 3, bit 4 DACDAT4_DACDAT45: .equ 5 ; Buffer Data 3, bit 5 DACDAT4_DACDAT46: .equ 6 ; Buffer Data 3, bit 6 DACDAT4_DACDAT47: .equ 7 ; Buffer Data 3, bit 7 DACDAT4_DACDAT48: .equ 8 ; Buffer Data 3, bit 8 DACDAT4_DACDAT49: .equ 9 ; Buffer Data 3, bit 9 DACDAT4_DACDAT410: .equ 10 ; Buffer Data 3, bit 10 DACDAT4_DACDAT411: .equ 11 ; Buffer Data 3, bit 11 ; bit position masks mDACDAT4_DACDAT40: .equ %00000001 mDACDAT4_DACDAT41: .equ %00000010 mDACDAT4_DACDAT42: .equ %00000100 mDACDAT4_DACDAT43: .equ %00001000 mDACDAT4_DACDAT44: .equ %00010000 mDACDAT4_DACDAT45: .equ %00100000 mDACDAT4_DACDAT46: .equ %01000000 mDACDAT4_DACDAT47: .equ %10000000 mDACDAT4_DACDAT48: .equ %100000000 mDACDAT4_DACDAT49: .equ %1000000000 mDACDAT4_DACDAT410: .equ %10000000000 mDACDAT4_DACDAT411: .equ %100000000000 ;*** DACDAT4H - DAC Data 4 High Register; 0xFFFF8018 *** DACDAT4H: .equ $FFFF8018 ;*** DACDAT4H - DAC Data 4 High Register; 0xFFFF8018 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT4H_DACDAT48: .equ 0 ; Buffer Data 4 High, bit 8 DACDAT4H_DACDAT49: .equ 1 ; Buffer Data 4 High, bit 9 DACDAT4H_DACDAT410: .equ 2 ; Buffer Data 4 High, bit 10 DACDAT4H_DACDAT411: .equ 3 ; Buffer Data 4 High, bit 11 ; bit position masks mDACDAT4H_DACDAT48: .equ %00000001 mDACDAT4H_DACDAT49: .equ %00000010 mDACDAT4H_DACDAT410: .equ %00000100 mDACDAT4H_DACDAT411: .equ %00001000 ;*** DACDAT4L - DAC Data 4 Low Register; 0xFFFF8019 *** DACDAT4L: .equ $FFFF8019 ;*** DACDAT4L - DAC Data 4 Low Register; 0xFFFF8019 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT4L_DACDAT40: .equ 0 ; Buffer Data 4 Low, bit 0 DACDAT4L_DACDAT41: .equ 1 ; Buffer Data 4 Low, bit 1 DACDAT4L_DACDAT42: .equ 2 ; Buffer Data 4 Low, bit 2 DACDAT4L_DACDAT43: .equ 3 ; Buffer Data 4 Low, bit 3 DACDAT4L_DACDAT44: .equ 4 ; Buffer Data 4 Low, bit 4 DACDAT4L_DACDAT45: .equ 5 ; Buffer Data 4 Low, bit 5 DACDAT4L_DACDAT46: .equ 6 ; Buffer Data 4 Low, bit 6 DACDAT4L_DACDAT47: .equ 7 ; Buffer Data 4 Low, bit 7 ; bit position masks mDACDAT4L_DACDAT40: .equ %00000001 mDACDAT4L_DACDAT41: .equ %00000010 mDACDAT4L_DACDAT42: .equ %00000100 mDACDAT4L_DACDAT43: .equ %00001000 mDACDAT4L_DACDAT44: .equ %00010000 mDACDAT4L_DACDAT45: .equ %00100000 mDACDAT4L_DACDAT46: .equ %01000000 mDACDAT4L_DACDAT47: .equ %10000000 ;*** DACDAT5 - DAC Data 5 Register; 0xFFFF801A *** DACDAT5: .equ $FFFF801A ;*** DACDAT5 - DAC Data 5 Register; 0xFFFF801A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT5_DACDAT50: .equ 0 ; Buffer Data 5, bit 0 DACDAT5_DACDAT51: .equ 1 ; Buffer Data 5, bit 1 DACDAT5_DACDAT52: .equ 2 ; Buffer Data 5, bit 2 DACDAT5_DACDAT53: .equ 3 ; Buffer Data 5, bit 3 DACDAT5_DACDAT54: .equ 4 ; Buffer Data 5, bit 4 DACDAT5_DACDAT55: .equ 5 ; Buffer Data 5, bit 5 DACDAT5_DACDAT56: .equ 6 ; Buffer Data 5, bit 6 DACDAT5_DACDAT57: .equ 7 ; Buffer Data 5, bit 7 DACDAT5_DACDAT58: .equ 8 ; Buffer Data 5, bit 8 DACDAT5_DACDAT59: .equ 9 ; Buffer Data 5, bit 9 DACDAT5_DACDAT510: .equ 10 ; Buffer Data 5, bit 10 DACDAT5_DACDAT511: .equ 11 ; Buffer Data 5, bit 11 ; bit position masks mDACDAT5_DACDAT50: .equ %00000001 mDACDAT5_DACDAT51: .equ %00000010 mDACDAT5_DACDAT52: .equ %00000100 mDACDAT5_DACDAT53: .equ %00001000 mDACDAT5_DACDAT54: .equ %00010000 mDACDAT5_DACDAT55: .equ %00100000 mDACDAT5_DACDAT56: .equ %01000000 mDACDAT5_DACDAT57: .equ %10000000 mDACDAT5_DACDAT58: .equ %100000000 mDACDAT5_DACDAT59: .equ %1000000000 mDACDAT5_DACDAT510: .equ %10000000000 mDACDAT5_DACDAT511: .equ %100000000000 ;*** DACDAT5H - DAC Data 5 High Register; 0xFFFF801A *** DACDAT5H: .equ $FFFF801A ;*** DACDAT5H - DAC Data 5 High Register; 0xFFFF801A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT5H_DACDAT58: .equ 0 ; Buffer Data 5 High, bit 8 DACDAT5H_DACDAT59: .equ 1 ; Buffer Data 5 High, bit 9 DACDAT5H_DACDAT510: .equ 2 ; Buffer Data 5 High, bit 10 DACDAT5H_DACDAT511: .equ 3 ; Buffer Data 5 High, bit 11 ; bit position masks mDACDAT5H_DACDAT58: .equ %00000001 mDACDAT5H_DACDAT59: .equ %00000010 mDACDAT5H_DACDAT510: .equ %00000100 mDACDAT5H_DACDAT511: .equ %00001000 ;*** DACDAT5L - DAC Data 5 Low Register; 0xFFFF801B *** DACDAT5L: .equ $FFFF801B ;*** DACDAT5L - DAC Data 5 Low Register; 0xFFFF801B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT5L_DACDAT50: .equ 0 ; Buffer Data 5 Low, bit 0 DACDAT5L_DACDAT51: .equ 1 ; Buffer Data 5 Low, bit 1 DACDAT5L_DACDAT52: .equ 2 ; Buffer Data 5 Low, bit 2 DACDAT5L_DACDAT53: .equ 3 ; Buffer Data 5 Low, bit 3 DACDAT5L_DACDAT54: .equ 4 ; Buffer Data 5 Low, bit 4 DACDAT5L_DACDAT55: .equ 5 ; Buffer Data 5 Low, bit 5 DACDAT5L_DACDAT56: .equ 6 ; Buffer Data 5 Low, bit 6 DACDAT5L_DACDAT57: .equ 7 ; Buffer Data 5 Low, bit 7 ; bit position masks mDACDAT5L_DACDAT50: .equ %00000001 mDACDAT5L_DACDAT51: .equ %00000010 mDACDAT5L_DACDAT52: .equ %00000100 mDACDAT5L_DACDAT53: .equ %00001000 mDACDAT5L_DACDAT54: .equ %00010000 mDACDAT5L_DACDAT55: .equ %00100000 mDACDAT5L_DACDAT56: .equ %01000000 mDACDAT5L_DACDAT57: .equ %10000000 ;*** DACDAT6 - DAC Data 6 Register; 0xFFFF801C *** DACDAT6: .equ $FFFF801C ;*** DACDAT6 - DAC Data 6 Register; 0xFFFF801C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT6_DACDAT60: .equ 0 ; Buffer Data 6, bit 0 DACDAT6_DACDAT61: .equ 1 ; Buffer Data 6, bit 1 DACDAT6_DACDAT62: .equ 2 ; Buffer Data 6, bit 2 DACDAT6_DACDAT63: .equ 3 ; Buffer Data 6, bit 3 DACDAT6_DACDAT64: .equ 4 ; Buffer Data 6, bit 4 DACDAT6_DACDAT65: .equ 5 ; Buffer Data 6, bit 5 DACDAT6_DACDAT66: .equ 6 ; Buffer Data 6, bit 6 DACDAT6_DACDAT67: .equ 7 ; Buffer Data 6, bit 7 DACDAT6_DACDAT68: .equ 8 ; Buffer Data 6, bit 8 DACDAT6_DACDAT69: .equ 9 ; Buffer Data 6, bit 9 DACDAT6_DACDAT610: .equ 10 ; Buffer Data 6, bit 10 DACDAT6_DACDAT611: .equ 11 ; Buffer Data 6, bit 11 ; bit position masks mDACDAT6_DACDAT60: .equ %00000001 mDACDAT6_DACDAT61: .equ %00000010 mDACDAT6_DACDAT62: .equ %00000100 mDACDAT6_DACDAT63: .equ %00001000 mDACDAT6_DACDAT64: .equ %00010000 mDACDAT6_DACDAT65: .equ %00100000 mDACDAT6_DACDAT66: .equ %01000000 mDACDAT6_DACDAT67: .equ %10000000 mDACDAT6_DACDAT68: .equ %100000000 mDACDAT6_DACDAT69: .equ %1000000000 mDACDAT6_DACDAT610: .equ %10000000000 mDACDAT6_DACDAT611: .equ %100000000000 ;*** DACDAT6H - DAC Data 6 High Register; 0xFFFF801C *** DACDAT6H: .equ $FFFF801C ;*** DACDAT6H - DAC Data 6 High Register; 0xFFFF801C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT6H_DACDAT68: .equ 0 ; Buffer Data 6 High, bit 8 DACDAT6H_DACDAT69: .equ 1 ; Buffer Data 6 High, bit 9 DACDAT6H_DACDAT610: .equ 2 ; Buffer Data 6 High, bit 10 DACDAT6H_DACDAT611: .equ 3 ; Buffer Data 6 High, bit 11 ; bit position masks mDACDAT6H_DACDAT68: .equ %00000001 mDACDAT6H_DACDAT69: .equ %00000010 mDACDAT6H_DACDAT610: .equ %00000100 mDACDAT6H_DACDAT611: .equ %00001000 ;*** DACDAT6L - DAC Data 6 Low Register; 0xFFFF801D *** DACDAT6L: .equ $FFFF801D ;*** DACDAT6L - DAC Data 6 Low Register; 0xFFFF801D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT6L_DACDAT60: .equ 0 ; Buffer Data 6 Low, bit 0 DACDAT6L_DACDAT61: .equ 1 ; Buffer Data 6 Low, bit 1 DACDAT6L_DACDAT62: .equ 2 ; Buffer Data 6 Low, bit 2 DACDAT6L_DACDAT63: .equ 3 ; Buffer Data 6 Low, bit 3 DACDAT6L_DACDAT64: .equ 4 ; Buffer Data 6 Low, bit 4 DACDAT6L_DACDAT65: .equ 5 ; Buffer Data 6 Low, bit 5 DACDAT6L_DACDAT66: .equ 6 ; Buffer Data 6 Low, bit 6 DACDAT6L_DACDAT67: .equ 7 ; Buffer Data 6 Low, bit 7 ; bit position masks mDACDAT6L_DACDAT60: .equ %00000001 mDACDAT6L_DACDAT61: .equ %00000010 mDACDAT6L_DACDAT62: .equ %00000100 mDACDAT6L_DACDAT63: .equ %00001000 mDACDAT6L_DACDAT64: .equ %00010000 mDACDAT6L_DACDAT65: .equ %00100000 mDACDAT6L_DACDAT66: .equ %01000000 mDACDAT6L_DACDAT67: .equ %10000000 ;*** DACDAT7 - DAC Data 7 Register; 0xFFFF801E *** DACDAT7: .equ $FFFF801E ;*** DACDAT7 - DAC Data 7 Register; 0xFFFF801E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT7_DACDAT70: .equ 0 ; Buffer Data 7, bit 0 DACDAT7_DACDAT71: .equ 1 ; Buffer Data 7, bit 1 DACDAT7_DACDAT72: .equ 2 ; Buffer Data 7, bit 2 DACDAT7_DACDAT73: .equ 3 ; Buffer Data 7, bit 3 DACDAT7_DACDAT74: .equ 4 ; Buffer Data 7, bit 4 DACDAT7_DACDAT75: .equ 5 ; Buffer Data 7, bit 5 DACDAT7_DACDAT76: .equ 6 ; Buffer Data 7, bit 6 DACDAT7_DACDAT77: .equ 7 ; Buffer Data 7, bit 7 DACDAT7_DACDAT78: .equ 8 ; Buffer Data 7, bit 8 DACDAT7_DACDAT79: .equ 9 ; Buffer Data 7, bit 9 DACDAT7_DACDAT710: .equ 10 ; Buffer Data 7, bit 10 DACDAT7_DACDAT711: .equ 11 ; Buffer Data 7, bit 11 ; bit position masks mDACDAT7_DACDAT70: .equ %00000001 mDACDAT7_DACDAT71: .equ %00000010 mDACDAT7_DACDAT72: .equ %00000100 mDACDAT7_DACDAT73: .equ %00001000 mDACDAT7_DACDAT74: .equ %00010000 mDACDAT7_DACDAT75: .equ %00100000 mDACDAT7_DACDAT76: .equ %01000000 mDACDAT7_DACDAT77: .equ %10000000 mDACDAT7_DACDAT78: .equ %100000000 mDACDAT7_DACDAT79: .equ %1000000000 mDACDAT7_DACDAT710: .equ %10000000000 mDACDAT7_DACDAT711: .equ %100000000000 ;*** DACDAT7H - DAC Data 7 High Register; 0xFFFF801E *** DACDAT7H: .equ $FFFF801E ;*** DACDAT7H - DAC Data 7 High Register; 0xFFFF801E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT7H_DACDAT78: .equ 0 ; Buffer Data 7 High, bit 8 DACDAT7H_DACDAT79: .equ 1 ; Buffer Data 7 High, bit 9 DACDAT7H_DACDAT710: .equ 2 ; Buffer Data 7 High, bit 10 DACDAT7H_DACDAT711: .equ 3 ; Buffer Data 7 High, bit 11 ; bit position masks mDACDAT7H_DACDAT78: .equ %00000001 mDACDAT7H_DACDAT79: .equ %00000010 mDACDAT7H_DACDAT710: .equ %00000100 mDACDAT7H_DACDAT711: .equ %00001000 ;*** DACDAT7L - DAC Data 7 Low Register; 0xFFFF801F *** DACDAT7L: .equ $FFFF801F ;*** DACDAT7L - DAC Data 7 Low Register; 0xFFFF801F *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT7L_DACDAT70: .equ 0 ; Buffer Data 7 Low, bit 0 DACDAT7L_DACDAT71: .equ 1 ; Buffer Data 7 Low, bit 1 DACDAT7L_DACDAT72: .equ 2 ; Buffer Data 7 Low, bit 2 DACDAT7L_DACDAT73: .equ 3 ; Buffer Data 7 Low, bit 3 DACDAT7L_DACDAT74: .equ 4 ; Buffer Data 7 Low, bit 4 DACDAT7L_DACDAT75: .equ 5 ; Buffer Data 7 Low, bit 5 DACDAT7L_DACDAT76: .equ 6 ; Buffer Data 7 Low, bit 6 DACDAT7L_DACDAT77: .equ 7 ; Buffer Data 7 Low, bit 7 ; bit position masks mDACDAT7L_DACDAT70: .equ %00000001 mDACDAT7L_DACDAT71: .equ %00000010 mDACDAT7L_DACDAT72: .equ %00000100 mDACDAT7L_DACDAT73: .equ %00001000 mDACDAT7L_DACDAT74: .equ %00010000 mDACDAT7L_DACDAT75: .equ %00100000 mDACDAT7L_DACDAT76: .equ %01000000 mDACDAT7L_DACDAT77: .equ %10000000 ;*** DACDAT8 - DAC Data 8 Register; 0xFFFF8020 *** DACDAT8: .equ $FFFF8020 ;*** DACDAT8 - DAC Data 8 Register; 0xFFFF8020 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT8_DACDAT80: .equ 0 ; Buffer Data 8, bit 0 DACDAT8_DACDAT81: .equ 1 ; Buffer Data 8, bit 1 DACDAT8_DACDAT82: .equ 2 ; Buffer Data 8, bit 2 DACDAT8_DACDAT83: .equ 3 ; Buffer Data 8, bit 3 DACDAT8_DACDAT84: .equ 4 ; Buffer Data 8, bit 4 DACDAT8_DACDAT85: .equ 5 ; Buffer Data 8, bit 5 DACDAT8_DACDAT86: .equ 6 ; Buffer Data 8, bit 6 DACDAT8_DACDAT87: .equ 7 ; Buffer Data 8, bit 7 DACDAT8_DACDAT88: .equ 8 ; Buffer Data 8, bit 8 DACDAT8_DACDAT89: .equ 9 ; Buffer Data 8, bit 9 DACDAT8_DACDAT810: .equ 10 ; Buffer Data 8, bit 10 DACDAT8_DACDAT811: .equ 11 ; Buffer Data 8, bit 11 ; bit position masks mDACDAT8_DACDAT80: .equ %00000001 mDACDAT8_DACDAT81: .equ %00000010 mDACDAT8_DACDAT82: .equ %00000100 mDACDAT8_DACDAT83: .equ %00001000 mDACDAT8_DACDAT84: .equ %00010000 mDACDAT8_DACDAT85: .equ %00100000 mDACDAT8_DACDAT86: .equ %01000000 mDACDAT8_DACDAT87: .equ %10000000 mDACDAT8_DACDAT88: .equ %100000000 mDACDAT8_DACDAT89: .equ %1000000000 mDACDAT8_DACDAT810: .equ %10000000000 mDACDAT8_DACDAT811: .equ %100000000000 ;*** DACDAT8H - DAC Data 8 High Register; 0xFFFF8020 *** DACDAT8H: .equ $FFFF8020 ;*** DACDAT8H - DAC Data 8 High Register; 0xFFFF8020 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT8H_DACDAT88: .equ 0 ; Buffer Data 8 High, bit 8 DACDAT8H_DACDAT89: .equ 1 ; Buffer Data 8 High, bit 9 DACDAT8H_DACDAT810: .equ 2 ; Buffer Data 8 High, bit 10 DACDAT8H_DACDAT811: .equ 3 ; Buffer Data 8 High, bit 11 ; bit position masks mDACDAT8H_DACDAT88: .equ %00000001 mDACDAT8H_DACDAT89: .equ %00000010 mDACDAT8H_DACDAT810: .equ %00000100 mDACDAT8H_DACDAT811: .equ %00001000 ;*** DACDAT8L - DAC Data 8 Low Register; 0xFFFF8021 *** DACDAT8L: .equ $FFFF8021 ;*** DACDAT8L - DAC Data 8 Low Register; 0xFFFF8021 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT8L_DACDAT80: .equ 0 ; Buffer Data 8 Low, bit 0 DACDAT8L_DACDAT81: .equ 1 ; Buffer Data 8 Low, bit 1 DACDAT8L_DACDAT82: .equ 2 ; Buffer Data 8 Low, bit 2 DACDAT8L_DACDAT83: .equ 3 ; Buffer Data 8 Low, bit 3 DACDAT8L_DACDAT84: .equ 4 ; Buffer Data 8 Low, bit 4 DACDAT8L_DACDAT85: .equ 5 ; Buffer Data 8 Low, bit 5 DACDAT8L_DACDAT86: .equ 6 ; Buffer Data 8 Low, bit 6 DACDAT8L_DACDAT87: .equ 7 ; Buffer Data 8 Low, bit 7 ; bit position masks mDACDAT8L_DACDAT80: .equ %00000001 mDACDAT8L_DACDAT81: .equ %00000010 mDACDAT8L_DACDAT82: .equ %00000100 mDACDAT8L_DACDAT83: .equ %00001000 mDACDAT8L_DACDAT84: .equ %00010000 mDACDAT8L_DACDAT85: .equ %00100000 mDACDAT8L_DACDAT86: .equ %01000000 mDACDAT8L_DACDAT87: .equ %10000000 ;*** DACDAT9 - DAC Data 9 Register; 0xFFFF8022 *** DACDAT9: .equ $FFFF8022 ;*** DACDAT9 - DAC Data 9 Register; 0xFFFF8022 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT9_DACDAT90: .equ 0 ; Buffer Data 9, bit 0 DACDAT9_DACDAT91: .equ 1 ; Buffer Data 9, bit 1 DACDAT9_DACDAT92: .equ 2 ; Buffer Data 9, bit 2 DACDAT9_DACDAT93: .equ 3 ; Buffer Data 9, bit 3 DACDAT9_DACDAT94: .equ 4 ; Buffer Data 9, bit 4 DACDAT9_DACDAT95: .equ 5 ; Buffer Data 9, bit 5 DACDAT9_DACDAT96: .equ 6 ; Buffer Data 9, bit 6 DACDAT9_DACDAT97: .equ 7 ; Buffer Data 9, bit 7 DACDAT9_DACDAT98: .equ 8 ; Buffer Data 9, bit 8 DACDAT9_DACDAT99: .equ 9 ; Buffer Data 9, bit 9 DACDAT9_DACDAT910: .equ 10 ; Buffer Data 9, bit 10 DACDAT9_DACDAT911: .equ 11 ; Buffer Data 9, bit 11 ; bit position masks mDACDAT9_DACDAT90: .equ %00000001 mDACDAT9_DACDAT91: .equ %00000010 mDACDAT9_DACDAT92: .equ %00000100 mDACDAT9_DACDAT93: .equ %00001000 mDACDAT9_DACDAT94: .equ %00010000 mDACDAT9_DACDAT95: .equ %00100000 mDACDAT9_DACDAT96: .equ %01000000 mDACDAT9_DACDAT97: .equ %10000000 mDACDAT9_DACDAT98: .equ %100000000 mDACDAT9_DACDAT99: .equ %1000000000 mDACDAT9_DACDAT910: .equ %10000000000 mDACDAT9_DACDAT911: .equ %100000000000 ;*** DACDAT9H - DAC Data 9 High Register; 0xFFFF8022 *** DACDAT9H: .equ $FFFF8022 ;*** DACDAT9H - DAC Data 9 High Register; 0xFFFF8022 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT9H_DACDAT98: .equ 0 ; Buffer Data 9 High, bit 8 DACDAT9H_DACDAT99: .equ 1 ; Buffer Data 9 High, bit 9 DACDAT9H_DACDAT910: .equ 2 ; Buffer Data 9 High, bit 10 DACDAT9H_DACDAT911: .equ 3 ; Buffer Data 9 High, bit 11 ; bit position masks mDACDAT9H_DACDAT98: .equ %00000001 mDACDAT9H_DACDAT99: .equ %00000010 mDACDAT9H_DACDAT910: .equ %00000100 mDACDAT9H_DACDAT911: .equ %00001000 ;*** DACDAT9L - DAC Data 9 Low Register; 0xFFFF8023 *** DACDAT9L: .equ $FFFF8023 ;*** DACDAT9L - DAC Data 9 Low Register; 0xFFFF8023 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT9L_DACDAT90: .equ 0 ; Buffer Data 9 Low, bit 0 DACDAT9L_DACDAT91: .equ 1 ; Buffer Data 9 Low, bit 1 DACDAT9L_DACDAT92: .equ 2 ; Buffer Data 9 Low, bit 2 DACDAT9L_DACDAT93: .equ 3 ; Buffer Data 9 Low, bit 3 DACDAT9L_DACDAT94: .equ 4 ; Buffer Data 9 Low, bit 4 DACDAT9L_DACDAT95: .equ 5 ; Buffer Data 9 Low, bit 5 DACDAT9L_DACDAT96: .equ 6 ; Buffer Data 9 Low, bit 6 DACDAT9L_DACDAT97: .equ 7 ; Buffer Data 9 Low, bit 7 ; bit position masks mDACDAT9L_DACDAT90: .equ %00000001 mDACDAT9L_DACDAT91: .equ %00000010 mDACDAT9L_DACDAT92: .equ %00000100 mDACDAT9L_DACDAT93: .equ %00001000 mDACDAT9L_DACDAT94: .equ %00010000 mDACDAT9L_DACDAT95: .equ %00100000 mDACDAT9L_DACDAT96: .equ %01000000 mDACDAT9L_DACDAT97: .equ %10000000 ;*** DACDAT10 - DAC Data 10 Register; 0xFFFF8024 *** DACDAT10: .equ $FFFF8024 ;*** DACDAT10 - DAC Data 10 Register; 0xFFFF8024 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT10_DACDAT100: .equ 0 ; Buffer Data 10, bit 0 DACDAT10_DACDAT101: .equ 1 ; Buffer Data 10, bit 1 DACDAT10_DACDAT102: .equ 2 ; Buffer Data 10, bit 2 DACDAT10_DACDAT103: .equ 3 ; Buffer Data 10, bit 3 DACDAT10_DACDAT104: .equ 4 ; Buffer Data 10, bit 4 DACDAT10_DACDAT105: .equ 5 ; Buffer Data 10, bit 5 DACDAT10_DACDAT106: .equ 6 ; Buffer Data 10, bit 6 DACDAT10_DACDAT107: .equ 7 ; Buffer Data 10, bit 7 DACDAT10_DACDAT108: .equ 8 ; Buffer Data 10, bit 8 DACDAT10_DACDAT109: .equ 9 ; Buffer Data 10, bit 9 DACDAT10_DACDAT1010: .equ 10 ; Buffer Data 10, bit 10 DACDAT10_DACDAT1011: .equ 11 ; Buffer Data 10, bit 11 ; bit position masks mDACDAT10_DACDAT100: .equ %00000001 mDACDAT10_DACDAT101: .equ %00000010 mDACDAT10_DACDAT102: .equ %00000100 mDACDAT10_DACDAT103: .equ %00001000 mDACDAT10_DACDAT104: .equ %00010000 mDACDAT10_DACDAT105: .equ %00100000 mDACDAT10_DACDAT106: .equ %01000000 mDACDAT10_DACDAT107: .equ %10000000 mDACDAT10_DACDAT108: .equ %100000000 mDACDAT10_DACDAT109: .equ %1000000000 mDACDAT10_DACDAT1010: .equ %10000000000 mDACDAT10_DACDAT1011: .equ %100000000000 ;*** DACDAT10H - DAC Data 10 High Register; 0xFFFF8024 *** DACDAT10H: .equ $FFFF8024 ;*** DACDAT10H - DAC Data 10 High Register; 0xFFFF8024 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT10H_DACDAT108: .equ 0 ; Buffer Data 10 High, bit 8 DACDAT10H_DACDAT109: .equ 1 ; Buffer Data 10 High, bit 9 DACDAT10H_DACDAT1010: .equ 2 ; Buffer Data 10 High, bit 10 DACDAT10H_DACDAT1011: .equ 3 ; Buffer Data 10 High, bit 11 ; bit position masks mDACDAT10H_DACDAT108: .equ %00000001 mDACDAT10H_DACDAT109: .equ %00000010 mDACDAT10H_DACDAT1010: .equ %00000100 mDACDAT10H_DACDAT1011: .equ %00001000 ;*** DACDAT10L - DAC Data 10 Low Register; 0xFFFF8025 *** DACDAT10L: .equ $FFFF8025 ;*** DACDAT10L - DAC Data 10 Low Register; 0xFFFF8025 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT10L_DACDAT100: .equ 0 ; Buffer Data 10 Low, bit 0 DACDAT10L_DACDAT101: .equ 1 ; Buffer Data 10 Low, bit 1 DACDAT10L_DACDAT102: .equ 2 ; Buffer Data 10 Low, bit 2 DACDAT10L_DACDAT103: .equ 3 ; Buffer Data 10 Low, bit 3 DACDAT10L_DACDAT104: .equ 4 ; Buffer Data 10 Low, bit 4 DACDAT10L_DACDAT105: .equ 5 ; Buffer Data 10 Low, bit 5 DACDAT10L_DACDAT106: .equ 6 ; Buffer Data 10 Low, bit 6 DACDAT10L_DACDAT107: .equ 7 ; Buffer Data 10 Low, bit 7 ; bit position masks mDACDAT10L_DACDAT100: .equ %00000001 mDACDAT10L_DACDAT101: .equ %00000010 mDACDAT10L_DACDAT102: .equ %00000100 mDACDAT10L_DACDAT103: .equ %00001000 mDACDAT10L_DACDAT104: .equ %00010000 mDACDAT10L_DACDAT105: .equ %00100000 mDACDAT10L_DACDAT106: .equ %01000000 mDACDAT10L_DACDAT107: .equ %10000000 ;*** DACDAT11 - DAC Data 11 Register; 0xFFFF8026 *** DACDAT11: .equ $FFFF8026 ;*** DACDAT11 - DAC Data 11 Register; 0xFFFF8026 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT11_DACDAT110: .equ 0 ; Buffer Data 11, bit 0 DACDAT11_DACDAT111: .equ 1 ; Buffer Data 11, bit 1 DACDAT11_DACDAT112: .equ 2 ; Buffer Data 11, bit 2 DACDAT11_DACDAT113: .equ 3 ; Buffer Data 11, bit 3 DACDAT11_DACDAT114: .equ 4 ; Buffer Data 11, bit 4 DACDAT11_DACDAT115: .equ 5 ; Buffer Data 11, bit 5 DACDAT11_DACDAT116: .equ 6 ; Buffer Data 11, bit 6 DACDAT11_DACDAT117: .equ 7 ; Buffer Data 11, bit 7 DACDAT11_DACDAT118: .equ 8 ; Buffer Data 11, bit 8 DACDAT11_DACDAT119: .equ 9 ; Buffer Data 11, bit 9 DACDAT11_DACDAT1110: .equ 10 ; Buffer Data 11, bit 10 DACDAT11_DACDAT1111: .equ 11 ; Buffer Data 11, bit 11 ; bit position masks mDACDAT11_DACDAT110: .equ %00000001 mDACDAT11_DACDAT111: .equ %00000010 mDACDAT11_DACDAT112: .equ %00000100 mDACDAT11_DACDAT113: .equ %00001000 mDACDAT11_DACDAT114: .equ %00010000 mDACDAT11_DACDAT115: .equ %00100000 mDACDAT11_DACDAT116: .equ %01000000 mDACDAT11_DACDAT117: .equ %10000000 mDACDAT11_DACDAT118: .equ %100000000 mDACDAT11_DACDAT119: .equ %1000000000 mDACDAT11_DACDAT1110: .equ %10000000000 mDACDAT11_DACDAT1111: .equ %100000000000 ;*** DACDAT11H - DAC Data 11 High Register; 0xFFFF8026 *** DACDAT11H: .equ $FFFF8026 ;*** DACDAT11H - DAC Data 11 High Register; 0xFFFF8026 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT11H_DACDAT118: .equ 0 ; Buffer Data 11 High, bit 8 DACDAT11H_DACDAT119: .equ 1 ; Buffer Data 11 High, bit 9 DACDAT11H_DACDAT1110: .equ 2 ; Buffer Data 11 High, bit 10 DACDAT11H_DACDAT1111: .equ 3 ; Buffer Data 11 High, bit 11 ; bit position masks mDACDAT11H_DACDAT118: .equ %00000001 mDACDAT11H_DACDAT119: .equ %00000010 mDACDAT11H_DACDAT1110: .equ %00000100 mDACDAT11H_DACDAT1111: .equ %00001000 ;*** DACDAT11L - DAC Data 11 Low Register; 0xFFFF8027 *** DACDAT11L: .equ $FFFF8027 ;*** DACDAT11L - DAC Data 11 Low Register; 0xFFFF8027 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT11L_DACDAT110: .equ 0 ; Buffer Data 11 Low, bit 0 DACDAT11L_DACDAT111: .equ 1 ; Buffer Data 11 Low, bit 1 DACDAT11L_DACDAT112: .equ 2 ; Buffer Data 11 Low, bit 2 DACDAT11L_DACDAT113: .equ 3 ; Buffer Data 11 Low, bit 3 DACDAT11L_DACDAT114: .equ 4 ; Buffer Data 11 Low, bit 4 DACDAT11L_DACDAT115: .equ 5 ; Buffer Data 11 Low, bit 5 DACDAT11L_DACDAT116: .equ 6 ; Buffer Data 11 Low, bit 6 DACDAT11L_DACDAT117: .equ 7 ; Buffer Data 11 Low, bit 7 ; bit position masks mDACDAT11L_DACDAT110: .equ %00000001 mDACDAT11L_DACDAT111: .equ %00000010 mDACDAT11L_DACDAT112: .equ %00000100 mDACDAT11L_DACDAT113: .equ %00001000 mDACDAT11L_DACDAT114: .equ %00010000 mDACDAT11L_DACDAT115: .equ %00100000 mDACDAT11L_DACDAT116: .equ %01000000 mDACDAT11L_DACDAT117: .equ %10000000 ;*** DACDAT12 - DAC Data 12 Register; 0xFFFF8028 *** DACDAT12: .equ $FFFF8028 ;*** DACDAT12 - DAC Data 12 Register; 0xFFFF8028 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT12_DACDAT120: .equ 0 ; Buffer Data 12, bit 0 DACDAT12_DACDAT121: .equ 1 ; Buffer Data 12, bit 1 DACDAT12_DACDAT122: .equ 2 ; Buffer Data 12, bit 2 DACDAT12_DACDAT123: .equ 3 ; Buffer Data 12, bit 3 DACDAT12_DACDAT124: .equ 4 ; Buffer Data 12, bit 4 DACDAT12_DACDAT125: .equ 5 ; Buffer Data 12, bit 5 DACDAT12_DACDAT126: .equ 6 ; Buffer Data 12, bit 6 DACDAT12_DACDAT127: .equ 7 ; Buffer Data 12, bit 7 DACDAT12_DACDAT128: .equ 8 ; Buffer Data 12, bit 8 DACDAT12_DACDAT129: .equ 9 ; Buffer Data 12, bit 9 DACDAT12_DACDAT1210: .equ 10 ; Buffer Data 12, bit 10 DACDAT12_DACDAT1211: .equ 11 ; Buffer Data 12, bit 11 ; bit position masks mDACDAT12_DACDAT120: .equ %00000001 mDACDAT12_DACDAT121: .equ %00000010 mDACDAT12_DACDAT122: .equ %00000100 mDACDAT12_DACDAT123: .equ %00001000 mDACDAT12_DACDAT124: .equ %00010000 mDACDAT12_DACDAT125: .equ %00100000 mDACDAT12_DACDAT126: .equ %01000000 mDACDAT12_DACDAT127: .equ %10000000 mDACDAT12_DACDAT128: .equ %100000000 mDACDAT12_DACDAT129: .equ %1000000000 mDACDAT12_DACDAT1210: .equ %10000000000 mDACDAT12_DACDAT1211: .equ %100000000000 ;*** DACDAT12H - DAC Data 12 High Register; 0xFFFF8028 *** DACDAT12H: .equ $FFFF8028 ;*** DACDAT12H - DAC Data 12 High Register; 0xFFFF8028 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT12H_DACDAT128: .equ 0 ; Buffer Data 12 High, bit 8 DACDAT12H_DACDAT129: .equ 1 ; Buffer Data 12 High, bit 9 DACDAT12H_DACDAT1210: .equ 2 ; Buffer Data 12 High, bit 10 DACDAT12H_DACDAT1211: .equ 3 ; Buffer Data 12 High, bit 11 ; bit position masks mDACDAT12H_DACDAT128: .equ %00000001 mDACDAT12H_DACDAT129: .equ %00000010 mDACDAT12H_DACDAT1210: .equ %00000100 mDACDAT12H_DACDAT1211: .equ %00001000 ;*** DACDAT12L - DAC Data 12 Low Register; 0xFFFF8029 *** DACDAT12L: .equ $FFFF8029 ;*** DACDAT12L - DAC Data 12 Low Register; 0xFFFF8029 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT12L_DACDAT120: .equ 0 ; Buffer Data 12 Low, bit 0 DACDAT12L_DACDAT121: .equ 1 ; Buffer Data 12 Low, bit 1 DACDAT12L_DACDAT122: .equ 2 ; Buffer Data 12 Low, bit 2 DACDAT12L_DACDAT123: .equ 3 ; Buffer Data 12 Low, bit 3 DACDAT12L_DACDAT124: .equ 4 ; Buffer Data 12 Low, bit 4 DACDAT12L_DACDAT125: .equ 5 ; Buffer Data 12 Low, bit 5 DACDAT12L_DACDAT126: .equ 6 ; Buffer Data 12 Low, bit 6 DACDAT12L_DACDAT127: .equ 7 ; Buffer Data 12 Low, bit 7 ; bit position masks mDACDAT12L_DACDAT120: .equ %00000001 mDACDAT12L_DACDAT121: .equ %00000010 mDACDAT12L_DACDAT122: .equ %00000100 mDACDAT12L_DACDAT123: .equ %00001000 mDACDAT12L_DACDAT124: .equ %00010000 mDACDAT12L_DACDAT125: .equ %00100000 mDACDAT12L_DACDAT126: .equ %01000000 mDACDAT12L_DACDAT127: .equ %10000000 ;*** DACDAT13 - DAC Data 13 Register; 0xFFFF802A *** DACDAT13: .equ $FFFF802A ;*** DACDAT13 - DAC Data 13 Register; 0xFFFF802A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT13_DACDAT130: .equ 0 ; Buffer Data 13, bit 0 DACDAT13_DACDAT131: .equ 1 ; Buffer Data 13, bit 1 DACDAT13_DACDAT132: .equ 2 ; Buffer Data 13, bit 2 DACDAT13_DACDAT133: .equ 3 ; Buffer Data 13, bit 3 DACDAT13_DACDAT134: .equ 4 ; Buffer Data 13, bit 4 DACDAT13_DACDAT135: .equ 5 ; Buffer Data 13, bit 5 DACDAT13_DACDAT136: .equ 6 ; Buffer Data 13, bit 6 DACDAT13_DACDAT137: .equ 7 ; Buffer Data 13, bit 7 DACDAT13_DACDAT138: .equ 8 ; Buffer Data 13, bit 8 DACDAT13_DACDAT139: .equ 9 ; Buffer Data 13, bit 9 DACDAT13_DACDAT1310: .equ 10 ; Buffer Data 13, bit 10 DACDAT13_DACDAT1311: .equ 11 ; Buffer Data 13, bit 11 ; bit position masks mDACDAT13_DACDAT130: .equ %00000001 mDACDAT13_DACDAT131: .equ %00000010 mDACDAT13_DACDAT132: .equ %00000100 mDACDAT13_DACDAT133: .equ %00001000 mDACDAT13_DACDAT134: .equ %00010000 mDACDAT13_DACDAT135: .equ %00100000 mDACDAT13_DACDAT136: .equ %01000000 mDACDAT13_DACDAT137: .equ %10000000 mDACDAT13_DACDAT138: .equ %100000000 mDACDAT13_DACDAT139: .equ %1000000000 mDACDAT13_DACDAT1310: .equ %10000000000 mDACDAT13_DACDAT1311: .equ %100000000000 ;*** DACDAT13H - DAC Data 13 High Register; 0xFFFF802A *** DACDAT13H: .equ $FFFF802A ;*** DACDAT13H - DAC Data 13 High Register; 0xFFFF802A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT13H_DACDAT138: .equ 0 ; Buffer Data 13 High, bit 8 DACDAT13H_DACDAT139: .equ 1 ; Buffer Data 13 High, bit 9 DACDAT13H_DACDAT1310: .equ 2 ; Buffer Data 13 High, bit 10 DACDAT13H_DACDAT1311: .equ 3 ; Buffer Data 13 High, bit 11 ; bit position masks mDACDAT13H_DACDAT138: .equ %00000001 mDACDAT13H_DACDAT139: .equ %00000010 mDACDAT13H_DACDAT1310: .equ %00000100 mDACDAT13H_DACDAT1311: .equ %00001000 ;*** DACDAT13L - DAC Data 13 Low Register; 0xFFFF802B *** DACDAT13L: .equ $FFFF802B ;*** DACDAT13L - DAC Data 13 Low Register; 0xFFFF802B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT13L_DACDAT130: .equ 0 ; Buffer Data 13 Low, bit 0 DACDAT13L_DACDAT131: .equ 1 ; Buffer Data 13 Low, bit 1 DACDAT13L_DACDAT132: .equ 2 ; Buffer Data 13 Low, bit 2 DACDAT13L_DACDAT133: .equ 3 ; Buffer Data 13 Low, bit 3 DACDAT13L_DACDAT134: .equ 4 ; Buffer Data 13 Low, bit 4 DACDAT13L_DACDAT135: .equ 5 ; Buffer Data 13 Low, bit 5 DACDAT13L_DACDAT136: .equ 6 ; Buffer Data 13 Low, bit 6 DACDAT13L_DACDAT137: .equ 7 ; Buffer Data 13 Low, bit 7 ; bit position masks mDACDAT13L_DACDAT130: .equ %00000001 mDACDAT13L_DACDAT131: .equ %00000010 mDACDAT13L_DACDAT132: .equ %00000100 mDACDAT13L_DACDAT133: .equ %00001000 mDACDAT13L_DACDAT134: .equ %00010000 mDACDAT13L_DACDAT135: .equ %00100000 mDACDAT13L_DACDAT136: .equ %01000000 mDACDAT13L_DACDAT137: .equ %10000000 ;*** DACDAT14 - DAC Data 14 Register; 0xFFFF802C *** DACDAT14: .equ $FFFF802C ;*** DACDAT14 - DAC Data 14 Register; 0xFFFF802C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT14_DACDAT140: .equ 0 ; Buffer Data 14, bit 0 DACDAT14_DACDAT141: .equ 1 ; Buffer Data 14, bit 1 DACDAT14_DACDAT142: .equ 2 ; Buffer Data 14, bit 2 DACDAT14_DACDAT143: .equ 3 ; Buffer Data 14, bit 3 DACDAT14_DACDAT144: .equ 4 ; Buffer Data 14, bit 4 DACDAT14_DACDAT145: .equ 5 ; Buffer Data 14, bit 5 DACDAT14_DACDAT146: .equ 6 ; Buffer Data 14, bit 6 DACDAT14_DACDAT147: .equ 7 ; Buffer Data 14, bit 7 DACDAT14_DACDAT148: .equ 8 ; Buffer Data 14, bit 8 DACDAT14_DACDAT149: .equ 9 ; Buffer Data 14, bit 9 DACDAT14_DACDAT1410: .equ 10 ; Buffer Data 14, bit 10 DACDAT14_DACDAT1411: .equ 11 ; Buffer Data 14, bit 11 ; bit position masks mDACDAT14_DACDAT140: .equ %00000001 mDACDAT14_DACDAT141: .equ %00000010 mDACDAT14_DACDAT142: .equ %00000100 mDACDAT14_DACDAT143: .equ %00001000 mDACDAT14_DACDAT144: .equ %00010000 mDACDAT14_DACDAT145: .equ %00100000 mDACDAT14_DACDAT146: .equ %01000000 mDACDAT14_DACDAT147: .equ %10000000 mDACDAT14_DACDAT148: .equ %100000000 mDACDAT14_DACDAT149: .equ %1000000000 mDACDAT14_DACDAT1410: .equ %10000000000 mDACDAT14_DACDAT1411: .equ %100000000000 ;*** DACDAT14H - DAC Data 14 High Register; 0xFFFF802C *** DACDAT14H: .equ $FFFF802C ;*** DACDAT14H - DAC Data 14 High Register; 0xFFFF802C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT14H_DACDAT148: .equ 0 ; Buffer Data 14 High, bit 8 DACDAT14H_DACDAT149: .equ 1 ; Buffer Data 14 High, bit 9 DACDAT14H_DACDAT1410: .equ 2 ; Buffer Data 14 High, bit 10 DACDAT14H_DACDAT1411: .equ 3 ; Buffer Data 14 High, bit 11 ; bit position masks mDACDAT14H_DACDAT148: .equ %00000001 mDACDAT14H_DACDAT149: .equ %00000010 mDACDAT14H_DACDAT1410: .equ %00000100 mDACDAT14H_DACDAT1411: .equ %00001000 ;*** DACDAT14L - DAC Data 14 Low Register; 0xFFFF802D *** DACDAT14L: .equ $FFFF802D ;*** DACDAT14L - DAC Data 14 Low Register; 0xFFFF802D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT14L_DACDAT140: .equ 0 ; Buffer Data 14 Low, bit 0 DACDAT14L_DACDAT141: .equ 1 ; Buffer Data 14 Low, bit 1 DACDAT14L_DACDAT142: .equ 2 ; Buffer Data 14 Low, bit 2 DACDAT14L_DACDAT143: .equ 3 ; Buffer Data 14 Low, bit 3 DACDAT14L_DACDAT144: .equ 4 ; Buffer Data 14 Low, bit 4 DACDAT14L_DACDAT145: .equ 5 ; Buffer Data 14 Low, bit 5 DACDAT14L_DACDAT146: .equ 6 ; Buffer Data 14 Low, bit 6 DACDAT14L_DACDAT147: .equ 7 ; Buffer Data 14 Low, bit 7 ; bit position masks mDACDAT14L_DACDAT140: .equ %00000001 mDACDAT14L_DACDAT141: .equ %00000010 mDACDAT14L_DACDAT142: .equ %00000100 mDACDAT14L_DACDAT143: .equ %00001000 mDACDAT14L_DACDAT144: .equ %00010000 mDACDAT14L_DACDAT145: .equ %00100000 mDACDAT14L_DACDAT146: .equ %01000000 mDACDAT14L_DACDAT147: .equ %10000000 ;*** DACDAT15 - DAC Data 15 Register; 0xFFFF802E *** DACDAT15: .equ $FFFF802E ;*** DACDAT15 - DAC Data 15 Register; 0xFFFF802E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT15_DACDAT150: .equ 0 ; Buffer Data 15, bit 0 DACDAT15_DACDAT151: .equ 1 ; Buffer Data 15, bit 1 DACDAT15_DACDAT152: .equ 2 ; Buffer Data 15, bit 2 DACDAT15_DACDAT153: .equ 3 ; Buffer Data 15, bit 3 DACDAT15_DACDAT154: .equ 4 ; Buffer Data 15, bit 4 DACDAT15_DACDAT155: .equ 5 ; Buffer Data 15, bit 5 DACDAT15_DACDAT156: .equ 6 ; Buffer Data 15, bit 6 DACDAT15_DACDAT157: .equ 7 ; Buffer Data 15, bit 7 DACDAT15_DACDAT158: .equ 8 ; Buffer Data 15, bit 8 DACDAT15_DACDAT159: .equ 9 ; Buffer Data 15, bit 9 DACDAT15_DACDAT1510: .equ 10 ; Buffer Data 15, bit 10 DACDAT15_DACDAT1511: .equ 11 ; Buffer Data 15, bit 11 ; bit position masks mDACDAT15_DACDAT150: .equ %00000001 mDACDAT15_DACDAT151: .equ %00000010 mDACDAT15_DACDAT152: .equ %00000100 mDACDAT15_DACDAT153: .equ %00001000 mDACDAT15_DACDAT154: .equ %00010000 mDACDAT15_DACDAT155: .equ %00100000 mDACDAT15_DACDAT156: .equ %01000000 mDACDAT15_DACDAT157: .equ %10000000 mDACDAT15_DACDAT158: .equ %100000000 mDACDAT15_DACDAT159: .equ %1000000000 mDACDAT15_DACDAT1510: .equ %10000000000 mDACDAT15_DACDAT1511: .equ %100000000000 ;*** DACDAT15H - DAC Data 15 High Register; 0xFFFF802E *** DACDAT15H: .equ $FFFF802E ;*** DACDAT15H - DAC Data 15 High Register; 0xFFFF802E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT15H_DACDAT158: .equ 0 ; Buffer Data 15 High, bit 8 DACDAT15H_DACDAT159: .equ 1 ; Buffer Data 15 High, bit 9 DACDAT15H_DACDAT1510: .equ 2 ; Buffer Data 15 High, bit 10 DACDAT15H_DACDAT1511: .equ 3 ; Buffer Data 15 High, bit 11 ; bit position masks mDACDAT15H_DACDAT158: .equ %00000001 mDACDAT15H_DACDAT159: .equ %00000010 mDACDAT15H_DACDAT1510: .equ %00000100 mDACDAT15H_DACDAT1511: .equ %00001000 ;*** DACDAT15L - DAC Data 15 Low Register; 0xFFFF802F *** DACDAT15L: .equ $FFFF802F ;*** DACDAT15L - DAC Data 15 Low Register; 0xFFFF802F *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACDAT15L_DACDAT150: .equ 0 ; Buffer Data 15 Low, bit 0 DACDAT15L_DACDAT151: .equ 1 ; Buffer Data 15 Low, bit 1 DACDAT15L_DACDAT152: .equ 2 ; Buffer Data 15 Low, bit 2 DACDAT15L_DACDAT153: .equ 3 ; Buffer Data 15 Low, bit 3 DACDAT15L_DACDAT154: .equ 4 ; Buffer Data 15 Low, bit 4 DACDAT15L_DACDAT155: .equ 5 ; Buffer Data 15 Low, bit 5 DACDAT15L_DACDAT156: .equ 6 ; Buffer Data 15 Low, bit 6 DACDAT15L_DACDAT157: .equ 7 ; Buffer Data 15 Low, bit 7 ; bit position masks mDACDAT15L_DACDAT150: .equ %00000001 mDACDAT15L_DACDAT151: .equ %00000010 mDACDAT15L_DACDAT152: .equ %00000100 mDACDAT15L_DACDAT153: .equ %00001000 mDACDAT15L_DACDAT154: .equ %00010000 mDACDAT15L_DACDAT155: .equ %00100000 mDACDAT15L_DACDAT156: .equ %01000000 mDACDAT15L_DACDAT157: .equ %10000000 ;*** DACS - DAC Status Register; 0xFFFF8030 *** DACS: .equ $FFFF8030 ;*** DACS - DAC Status Register; 0xFFFF8030 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACS_DACRPB: .equ 0 ; DAC buffer read pointer bottom position flag DACS_DACRPT: .equ 1 ; DAC buffer read pointer top position flag DACS_DACWM: .equ 2 ; DAC buffer watermark flag ; bit position masks mDACS_DACRPB: .equ %00000001 mDACS_DACRPT: .equ %00000010 mDACS_DACWM: .equ %00000100 ;*** DACC0 - DAC Control 0 Register; 0xFFFF8031 *** DACC0: .equ $FFFF8031 ;*** DACC0 - DAC Control 0 Register; 0xFFFF8031 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACC0_DACBIE: .equ 0 ; DAC buffer read pointer bottom flag interrupt enable DACC0_DACTIE: .equ 1 ; DAC buffer read pointer top flag interrupt enable DACC0_DACWIE: .equ 2 ; DAC buffer watermark interrupt enable DACC0_LPEN: .equ 3 ; DAC low power control DACC0_DACSTRG: .equ 4 ; DAC software trigger - active high DACC0_DACTSEL: .equ 5 ; DAC trigger select DACC0_DACRFS: .equ 6 ; DAC Reference Select DACC0_DACEN: .equ 7 ; DAC enable - The DACEN bit starts the Programmable Reference Generator operation ; bit position masks mDACC0_DACBIE: .equ %00000001 mDACC0_DACTIE: .equ %00000010 mDACC0_DACWIE: .equ %00000100 mDACC0_LPEN: .equ %00001000 mDACC0_DACSTRG: .equ %00010000 mDACC0_DACTSEL: .equ %00100000 mDACC0_DACRFS: .equ %01000000 mDACC0_DACEN: .equ %10000000 ;*** DACC1 - DAC Control 1 Register; 0xFFFF8032 *** DACC1: .equ $FFFF8032 ;*** DACC1 - DAC Control 1 Register; 0xFFFF8032 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACC1_DACBFE: .equ 0 ; DAC Buffer Enable DACC1_DACBFMD0: .equ 1 ; DAC Buffer Work Mode Select, bit 0 DACC1_DACBFMD1: .equ 2 ; DAC Buffer Work Mode Select, bit 1 DACC1_DACBFWM0: .equ 3 ; DAC Buffer Watermark Select, bit 0 DACC1_DACBFWM1: .equ 4 ; DAC Buffer Watermark Select, bit 1 ; bit position masks mDACC1_DACBFE: .equ %00000001 mDACC1_DACBFMD0: .equ %00000010 mDACC1_DACBFMD1: .equ %00000100 mDACC1_DACBFWM0: .equ %00001000 mDACC1_DACBFWM1: .equ %00010000 ;*** DACC2 - DAC Control 2 Register; 0xFFFF8033 *** DACC2: .equ $FFFF8033 ;*** DACC2 - DAC Control 2 Register; 0xFFFF8033 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACC2_DACBFUP: .equ 0 ; DAC Buffer Upper Limit DACC2_DACBFRP: .equ 4 ; DAC Buffer Read Pointer ; bit position masks mDACC2_DACBFUP: .equ %00001111 mDACC2_DACBFRP: .equ %11110000 ;*** PRACMPCS - PRACMP Control and Status Register; 0xFFFF8034 *** PRACMPCS: .equ $FFFF8034 ;*** PRACMPCS - PRACMP Control and Status Register; 0xFFFF8034 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PRACMPCS_ACIEN: .equ 0 ; ACMP Interrupt Enable PRACMPCS_ACINTS0: .equ 1 ; ACMP Interrupt Select, bit 0 PRACMPCS_ACINTS1: .equ 2 ; ACMP Interrupt Select, bit 1 PRACMPCS_ACMPO: .equ 3 ; ACMP Output Bit PRACMPCS_ACOPE: .equ 4 ; ACMP Output Pin Enable PRACMPCS_ACMPF: .equ 6 ; ACMP Interrupt Flag PRACMPCS_ACEN: .equ 7 ; ACMP Module Enable ; bit position masks mPRACMPCS_ACIEN: .equ %00000001 mPRACMPCS_ACINTS0: .equ %00000010 mPRACMPCS_ACINTS1: .equ %00000100 mPRACMPCS_ACMPO: .equ %00001000 mPRACMPCS_ACOPE: .equ %00010000 mPRACMPCS_ACMPF: .equ %01000000 mPRACMPCS_ACEN: .equ %10000000 ;*** PRACMPC0 - PRACMP Control 0 Register; 0xFFFF8035 *** PRACMPC0: .equ $FFFF8035 ;*** PRACMPC0 - PRACMP Control 0 Register; 0xFFFF8035 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PRACMPC0_ACNSEL0: .equ 0 ; ACMP Negative Input Select, bit 0 PRACMPC0_ACNSEL1: .equ 1 ; ACMP Negative Input Select, bit 1 PRACMPC0_ACNSEL2: .equ 2 ; ACMP Negative Input Select, bit 2 PRACMPC0_ACPSEL0: .equ 4 ; ACMP Positive Input Select, bit 0 PRACMPC0_ACPSEL1: .equ 5 ; ACMP Positive Input Select, bit 1 PRACMPC0_ACPSEL2: .equ 6 ; ACMP Positive Input Select, bit 2 ; bit position masks mPRACMPC0_ACNSEL0: .equ %00000001 mPRACMPC0_ACNSEL1: .equ %00000010 mPRACMPC0_ACNSEL2: .equ %00000100 mPRACMPC0_ACPSEL0: .equ %00010000 mPRACMPC0_ACPSEL1: .equ %00100000 mPRACMPC0_ACPSEL2: .equ %01000000 ;*** PRACMPC1 - PRACMP Control 1 Register; 0xFFFF8036 *** PRACMPC1: .equ $FFFF8036 ;*** PRACMPC1 - PRACMP Control 1 Register; 0xFFFF8036 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PRACMPC1_PRGOS0: .equ 0 ; Programmable Reference Generator Output Selection, bit 0 PRACMPC1_PRGOS1: .equ 1 ; Programmable Reference Generator Output Selection, bit 1 PRACMPC1_PRGOS2: .equ 2 ; Programmable Reference Generator Output Selection, bit 2 PRACMPC1_PRGOS3: .equ 3 ; Programmable Reference Generator Output Selection, bit 3 PRACMPC1_PRGOS4: .equ 4 ; Programmable Reference Generator Output Selection, bit 4 PRACMPC1_PRGINS: .equ 6 ; Programmable Reference Generator Input Selection PRACMPC1_PRGEN: .equ 7 ; Programmable Reference Generator Enable ; bit position masks mPRACMPC1_PRGOS0: .equ %00000001 mPRACMPC1_PRGOS1: .equ %00000010 mPRACMPC1_PRGOS2: .equ %00000100 mPRACMPC1_PRGOS3: .equ %00001000 mPRACMPC1_PRGOS4: .equ %00010000 mPRACMPC1_PRGINS: .equ %01000000 mPRACMPC1_PRGEN: .equ %10000000 ;*** PRACMPC2 - PRACMP Control 2 Register; 0xFFFF8037 *** PRACMPC2: .equ $FFFF8037 ;*** PRACMPC2 - PRACMP Control 2 Register; 0xFFFF8037 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PRACMPC2_ACIPE0: .equ 0 ; ACMP Input Pin 0 Enable - ACIPE0 is used to control the PRACMP external pin 0 as analog input PRACMPC2_ACIPE1: .equ 1 ; ACMP Input Pin 1 Enable - ACIPE1 is used to control the PRACMP external pin 1 as analog input PRACMPC2_ACIPE2: .equ 2 ; ACMP Input Pin 2 Enable - ACIPE2 is used to control the PRACMP external pin 2 as analog input PRACMPC2_ACIPE3: .equ 3 ; ACMP Input Pin 3 Enable - ACIPE3 is used to control the PRACMP external pin 3 as analog input PRACMPC2_ACIPE4: .equ 4 ; ACMP Input Pin 4 Enable - ACIPE4 is used to control the PRACMP external pin 4 as analog input PRACMPC2_ACIPE5: .equ 5 ; ACMP Input Pin 5 Enable - ACIPE5 is used to control the PRACMP external pin 5 as analog input PRACMPC2_ACIPE6: .equ 6 ; ACMP Input Pin 6 Enable - ACIPE6 is used to control the PRACMP external pin 6 as analog input ; bit position masks mPRACMPC2_ACIPE0: .equ %00000001 mPRACMPC2_ACIPE1: .equ %00000010 mPRACMPC2_ACIPE2: .equ %00000100 mPRACMPC2_ACIPE3: .equ %00001000 mPRACMPC2_ACIPE4: .equ %00010000 mPRACMPC2_ACIPE5: .equ %00100000 mPRACMPC2_ACIPE6: .equ %01000000 ;*** MCGC1 - MCG Control Register 1; 0xFFFF8038 *** MCGC1: .equ $FFFF8038 ;*** MCGC1 - MCG Control Register 1; 0xFFFF8038 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET MCGC1_IREFSTEN: .equ 0 ; Internal Reference Stop Enable MCGC1_IRCLKEN: .equ 1 ; Internal Reference Clock Enable MCGC1_IREFS: .equ 2 ; Internal Reference Select MCGC1_RDIV0: .equ 3 ; Reference Divider, bit 0 MCGC1_RDIV1: .equ 4 ; Reference Divider, bit 1 MCGC1_RDIV2: .equ 5 ; Reference Divider, bit 2 MCGC1_CLKS0: .equ 6 ; Clock Source Select, bit 0 MCGC1_CLKS1: .equ 7 ; Clock Source Select, bit 1 ; bit position masks mMCGC1_IREFSTEN: .equ %00000001 mMCGC1_IRCLKEN: .equ %00000010 mMCGC1_IREFS: .equ %00000100 mMCGC1_RDIV0: .equ %00001000 mMCGC1_RDIV1: .equ %00010000 mMCGC1_RDIV2: .equ %00100000 mMCGC1_CLKS0: .equ %01000000 mMCGC1_CLKS1: .equ %10000000 ;*** MCGC2 - MCG Control Register 2; 0xFFFF8039 *** MCGC2: .equ $FFFF8039 ;*** MCGC2 - MCG Control Register 2; 0xFFFF8039 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET MCGC2_EREFSTEN: .equ 0 ; External Reference Stop Enable MCGC2_ERCLKEN: .equ 1 ; External Reference Enable MCGC2_EREFS: .equ 2 ; External Reference Select MCGC2_LP: .equ 3 ; Low Power Select MCGC2_HGO: .equ 4 ; High Gain Oscillator Select MCGC2_RANGE: .equ 5 ; Frequency Range Select MCGC2_BDIV0: .equ 6 ; Bus Frequency Divider, bit 0 MCGC2_BDIV1: .equ 7 ; Bus Frequency Divider, bit 1 ; bit position masks mMCGC2_EREFSTEN: .equ %00000001 mMCGC2_ERCLKEN: .equ %00000010 mMCGC2_EREFS: .equ %00000100 mMCGC2_LP: .equ %00001000 mMCGC2_HGO: .equ %00010000 mMCGC2_RANGE: .equ %00100000 mMCGC2_BDIV0: .equ %01000000 mMCGC2_BDIV1: .equ %10000000 ;*** MCGTRM - MCG Trim Register; 0xFFFF803A *** MCGTRM: .equ $FFFF803A ;*** MCGTRM - MCG Trim Register; 0xFFFF803A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET MCGTRM_TRIM0: .equ 0 ; MCG Trim Setting, bit 0 MCGTRM_TRIM1: .equ 1 ; MCG Trim Setting, bit 1 MCGTRM_TRIM2: .equ 2 ; MCG Trim Setting, bit 2 MCGTRM_TRIM3: .equ 3 ; MCG Trim Setting, bit 3 MCGTRM_TRIM4: .equ 4 ; MCG Trim Setting, bit 4 MCGTRM_TRIM5: .equ 5 ; MCG Trim Setting, bit 5 MCGTRM_TRIM6: .equ 6 ; MCG Trim Setting, bit 6 MCGTRM_TRIM7: .equ 7 ; MCG Trim Setting, bit 7 ; bit position masks mMCGTRM_TRIM0: .equ %00000001 mMCGTRM_TRIM1: .equ %00000010 mMCGTRM_TRIM2: .equ %00000100 mMCGTRM_TRIM3: .equ %00001000 mMCGTRM_TRIM4: .equ %00010000 mMCGTRM_TRIM5: .equ %00100000 mMCGTRM_TRIM6: .equ %01000000 mMCGTRM_TRIM7: .equ %10000000 ;*** MCGSC - MCG Status and Control Register; 0xFFFF803B *** MCGSC: .equ $FFFF803B ;*** MCGSC - MCG Status and Control Register; 0xFFFF803B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET MCGSC_FTRIM: .equ 0 ; MCG Fine Trim MCGSC_OSCINIT: .equ 1 ; OSC Initialization MCGSC_CLKST0: .equ 2 ; Clock Mode Status, bit 0 MCGSC_CLKST1: .equ 3 ; Clock Mode Status, bit 1 MCGSC_IREFST: .equ 4 ; Internal Reference Status MCGSC_PLLST: .equ 5 ; PLL Select Status MCGSC_LOCK: .equ 6 ; Lock Status MCGSC_LOLS: .equ 7 ; Loss of Lock Status ; bit position masks mMCGSC_FTRIM: .equ %00000001 mMCGSC_OSCINIT: .equ %00000010 mMCGSC_CLKST0: .equ %00000100 mMCGSC_CLKST1: .equ %00001000 mMCGSC_IREFST: .equ %00010000 mMCGSC_PLLST: .equ %00100000 mMCGSC_LOCK: .equ %01000000 mMCGSC_LOLS: .equ %10000000 ;*** MCGC3 - MCG Control Register 3; 0xFFFF803C *** MCGC3: .equ $FFFF803C ;*** MCGC3 - MCG Control Register 3; 0xFFFF803C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET MCGC3_VDIV0: .equ 0 ; VCO Divider, bit 0 MCGC3_VDIV1: .equ 1 ; VCO Divider, bit 1 MCGC3_VDIV2: .equ 2 ; VCO Divider, bit 2 MCGC3_VDIV3: .equ 3 ; VCO Divider, bit 3 MCGC3_DIV32: .equ 4 ; Divide-by-32 Enable MCGC3_CME: .equ 5 ; Clock Monitor Enable MCGC3_PLLS: .equ 6 ; PLL Select MCGC3_LOLIE: .equ 7 ; Loss of Lock Interrupt Enable ; bit position masks mMCGC3_VDIV0: .equ %00000001 mMCGC3_VDIV1: .equ %00000010 mMCGC3_VDIV2: .equ %00000100 mMCGC3_VDIV3: .equ %00001000 mMCGC3_DIV32: .equ %00010000 mMCGC3_CME: .equ %00100000 mMCGC3_PLLS: .equ %01000000 mMCGC3_LOLIE: .equ %10000000 ;*** MCGC4 - MCG Control Register 4; 0xFFFF803D *** MCGC4: .equ $FFFF803D ;*** MCGC4 - MCG Control Register 4; 0xFFFF803D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET MCGC4_DRST_DRS0: .equ 0 ; DCO Range Status / DCO Range Select, bit 0 MCGC4_DRST_DRS1: .equ 1 ; DCO Range Status / DCO Range Select, bit 1 MCGC4_DMX32: .equ 5 ; DCO Maximum frequency with 32.768 kHz reference ; bit position masks mMCGC4_DRST_DRS0: .equ %00000001 mMCGC4_DRST_DRS1: .equ %00000010 mMCGC4_DMX32: .equ %00100000 ;*** ADCSC1 - Status and Control Register 1A; 0xFFFF8040 *** ADCSC1: .equ $FFFF8040 ;*** ADCSC1 - Status and Control Register 1A; 0xFFFF8040 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADCSC1_ADCH0: .equ 0 ; Input Channel Select Bit 0 ADCSC1_ADCH1: .equ 1 ; Input Channel Select Bit 1 ADCSC1_ADCH2: .equ 2 ; Input Channel Select Bit 2 ADCSC1_ADCH3: .equ 3 ; Input Channel Select Bit 3 ADCSC1_ADCH4: .equ 4 ; Input Channel Select Bit 4 ADCSC1_DIFF: .equ 5 ; Differential Mode Enable - selects between single-ended and differential conversion on selected channel ADCSC1_AIEN: .equ 6 ; Interrupt Enable - AIEN enables conversion complete interrupts. When COCO becomes set while the respective AIEN is high, an interrupt is asserted ADCSC1_COCO: .equ 7 ; Conversion Complete Flag ; bit position masks mADCSC1_ADCH0: .equ %00000001 mADCSC1_ADCH1: .equ %00000010 mADCSC1_ADCH2: .equ %00000100 mADCSC1_ADCH3: .equ %00001000 mADCSC1_ADCH4: .equ %00010000 mADCSC1_DIFF: .equ %00100000 mADCSC1_AIEN: .equ %01000000 mADCSC1_COCO: .equ %10000000 ;*** ADCCFG1 - Configuration Register 1; 0xFFFF8048 *** ADCCFG1: .equ $FFFF8048 ;*** ADCCFG1 - Configuration Register 1; 0xFFFF8048 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADCCFG1_ADICLK0: .equ 0 ; Input Clock Select Bit 0 ADCCFG1_ADICLK1: .equ 1 ; Input Clock Select Bit 1 ADCCFG1_MODE0: .equ 2 ; Conversion Mode Selection Bit 0 ADCCFG1_MODE1: .equ 3 ; Conversion Mode Selection Bit 1 ADCCFG1_ADLSMP: .equ 4 ; Long Sample Time Configuration ADCCFG1_ADIV0: .equ 5 ; Clock Divide Select Bit 0 ADCCFG1_ADIV1: .equ 6 ; Clock Divide Select Bit 1 ADCCFG1_ADLPC: .equ 7 ; Low Power Configuration ; bit position masks mADCCFG1_ADICLK0: .equ %00000001 mADCCFG1_ADICLK1: .equ %00000010 mADCCFG1_MODE0: .equ %00000100 mADCCFG1_MODE1: .equ %00001000 mADCCFG1_ADLSMP: .equ %00010000 mADCCFG1_ADIV0: .equ %00100000 mADCCFG1_ADIV1: .equ %01000000 mADCCFG1_ADLPC: .equ %10000000 ;*** ADCCFG2 - Configuration Register 2; 0xFFFF8049 *** ADCCFG2: .equ $FFFF8049 ;*** ADCCFG2 - Configuration Register 2; 0xFFFF8049 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADCCFG2_ADLSTS0: .equ 0 ; Long Sample Time Select Bit 0 ADCCFG2_ADLSTS1: .equ 1 ; Long Sample Time Select Bit 1 ADCCFG2_ADHSC: .equ 2 ; High Speed Configuration ADCCFG2_ADACKEN: .equ 3 ; Asynchronous Clock Output Enable ; bit position masks mADCCFG2_ADLSTS0: .equ %00000001 mADCCFG2_ADLSTS1: .equ %00000010 mADCCFG2_ADHSC: .equ %00000100 mADCCFG2_ADACKEN: .equ %00001000 ;*** ADCR - Data Result Register; 0xFFFF804A *** ADCR: .equ $FFFF804A ;*** ADCR - Data Result Register; 0xFFFF804A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADCR_D0: .equ 0 ; ADC Result Data Bit 0 ADCR_D1: .equ 1 ; ADC Result Data Bit 1 ADCR_D2: .equ 2 ; ADC Result Data Bit 2 ADCR_D3: .equ 3 ; ADC Result Data Bit 3 ADCR_D4: .equ 4 ; ADC Result Data Bit 4 ADCR_D5: .equ 5 ; ADC Result Data Bit 5 ADCR_D6: .equ 6 ; ADC Result Data Bit 6 ADCR_D7: .equ 7 ; ADC Result Data Bit 7 ADCR_D8: .equ 8 ; ADC Result Data Bit 8 ADCR_D9: .equ 9 ; ADC Result Data Bit 9 ADCR_D10: .equ 10 ; ADC Result Data Bit 10 ADCR_D11: .equ 11 ; ADC Result Data Bit 11 ; bit position masks mADCR_D0: .equ %00000001 mADCR_D1: .equ %00000010 mADCR_D2: .equ %00000100 mADCR_D3: .equ %00001000 mADCR_D4: .equ %00010000 mADCR_D5: .equ %00100000 mADCR_D6: .equ %01000000 mADCR_D7: .equ %10000000 mADCR_D8: .equ %100000000 mADCR_D9: .equ %1000000000 mADCR_D10: .equ %10000000000 mADCR_D11: .equ %100000000000 ;*** ADCRH - Data Result High Register; 0xFFFF804A *** ADCRH: .equ $FFFF804A ;*** ADCRH - Data Result High Register; 0xFFFF804A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADCRH_D8: .equ 0 ; ADC Result Data Bit 8 ADCRH_D9: .equ 1 ; ADC Result Data Bit 9 ADCRH_D10: .equ 2 ; ADC Result Data Bit 10 ADCRH_D11: .equ 3 ; ADC Result Data Bit 11 ; bit position masks mADCRH_D8: .equ %00000001 mADCRH_D9: .equ %00000010 mADCRH_D10: .equ %00000100 mADCRH_D11: .equ %00001000 ;*** ADCRL - Data Result Low Register; 0xFFFF804B *** ADCRL: .equ $FFFF804B ;*** ADCRL - Data Result Low Register; 0xFFFF804B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADCRL_D0: .equ 0 ; ADC Result Data Bit 0 ADCRL_D1: .equ 1 ; ADC Result Data Bit 1 ADCRL_D2: .equ 2 ; ADC Result Data Bit 2 ADCRL_D3: .equ 3 ; ADC Result Data Bit 3 ADCRL_D4: .equ 4 ; ADC Result Data Bit 4 ADCRL_D5: .equ 5 ; ADC Result Data Bit 5 ADCRL_D6: .equ 6 ; ADC Result Data Bit 6 ADCRL_D7: .equ 7 ; ADC Result Data Bit 7 ; bit position masks mADCRL_D0: .equ %00000001 mADCRL_D1: .equ %00000010 mADCRL_D2: .equ %00000100 mADCRL_D3: .equ %00001000 mADCRL_D4: .equ %00010000 mADCRL_D5: .equ %00100000 mADCRL_D6: .equ %01000000 mADCRL_D7: .equ %10000000 ;*** VREFTRM - VREF Trim Register; 0xFFFF805C *** VREFTRM: .equ $FFFF805C ;*** VREFTRM - VREF Trim Register; 0xFFFF805C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET VREFTRM_TRM0: .equ 0 ; Trim Bits, bit 0 VREFTRM_TRM1: .equ 1 ; Trim Bits, bit 1 VREFTRM_TRM2: .equ 2 ; Trim Bits, bit 2 VREFTRM_TRM3: .equ 3 ; Trim Bits, bit 3 VREFTRM_TRM4: .equ 4 ; Trim Bits, bit 4 VREFTRM_TRM5: .equ 5 ; Trim Bits, bit 5 VREFTRM_TRM6: .equ 6 ; Trim Bits, bit 6 VREFTRM_TRM7: .equ 7 ; Trim Bits, bit 7 ; bit position masks mVREFTRM_TRM0: .equ %00000001 mVREFTRM_TRM1: .equ %00000010 mVREFTRM_TRM2: .equ %00000100 mVREFTRM_TRM3: .equ %00001000 mVREFTRM_TRM4: .equ %00010000 mVREFTRM_TRM5: .equ %00100000 mVREFTRM_TRM6: .equ %01000000 mVREFTRM_TRM7: .equ %10000000 ;*** VREFSC - VREF Control Register; 0xFFFF805D *** VREFSC: .equ $FFFF805D ;*** VREFSC - VREF Control Register; 0xFFFF805D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET VREFSC_MODE0: .equ 0 ; Mode selection, bit 0 VREFSC_MODE1: .equ 1 ; Mode selection, bit 1 VREFSC_VREFST: .equ 2 ; Internal Voltage Reference Stable VREFSC_VREFEN: .equ 7 ; Internal Voltage Reference Enable ; bit position masks mVREFSC_MODE0: .equ %00000001 mVREFSC_MODE1: .equ %00000010 mVREFSC_VREFST: .equ %00000100 mVREFSC_VREFEN: .equ %10000000 ;*** IRQSC - Interrupt request status and control register; 0xFFFF805F *** IRQSC: .equ $FFFF805F ;*** IRQSC - Interrupt request status and control register; 0xFFFF805F *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IRQSC_IRQMOD: .equ 0 ; IRQ Detection Mode IRQSC_IRQIE: .equ 1 ; IRQ Interrupt Enable IRQSC_IRQACK: .equ 2 ; IRQ Acknowledge IRQSC_IRQF: .equ 3 ; IRQ Flag IRQSC_IRQPE: .equ 4 ; IRQ Pin Enable IRQSC_IRQEDG: .equ 5 ; IRQ Edge Select IRQSC_IRQPDD: .equ 6 ; IRQ Pull Device Disable ; bit position masks mIRQSC_IRQMOD: .equ %00000001 mIRQSC_IRQIE: .equ %00000010 mIRQSC_IRQACK: .equ %00000100 mIRQSC_IRQF: .equ %00001000 mIRQSC_IRQPE: .equ %00010000 mIRQSC_IRQEDG: .equ %00100000 mIRQSC_IRQPDD: .equ %01000000 ;*** IICA1 - IIC Address Register; 0xFFFF8060 *** IICA1: .equ $FFFF8060 ;*** IICA1 - IIC Address Register; 0xFFFF8060 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICA1_AD1: .equ 1 ; Slave Address Bit 1 IICA1_AD2: .equ 2 ; Slave Address Bit 2 IICA1_AD3: .equ 3 ; Slave Address Bit 3 IICA1_AD4: .equ 4 ; Slave Address Bit 4 IICA1_AD5: .equ 5 ; Slave Address Bit 5 IICA1_AD6: .equ 6 ; Slave Address Bit 6 IICA1_AD7: .equ 7 ; Slave Address Bit 7 ; bit position masks mIICA1_AD1: .equ %00000010 mIICA1_AD2: .equ %00000100 mIICA1_AD3: .equ %00001000 mIICA1_AD4: .equ %00010000 mIICA1_AD5: .equ %00100000 mIICA1_AD6: .equ %01000000 mIICA1_AD7: .equ %10000000 ;*** IICA - IIC Address Register; 0xFFFF8060 *** IICA: .equ $FFFF8060 ;*** IICA - IIC Address Register; 0xFFFF8060 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICA_AD1: .equ 1 ; Slave Address Bit 1 IICA_AD2: .equ 2 ; Slave Address Bit 2 IICA_AD3: .equ 3 ; Slave Address Bit 3 IICA_AD4: .equ 4 ; Slave Address Bit 4 IICA_AD5: .equ 5 ; Slave Address Bit 5 IICA_AD6: .equ 6 ; Slave Address Bit 6 IICA_AD7: .equ 7 ; Slave Address Bit 7 ; bit position masks mIICA_AD1: .equ %00000010 mIICA_AD2: .equ %00000100 mIICA_AD3: .equ %00001000 mIICA_AD4: .equ %00010000 mIICA_AD5: .equ %00100000 mIICA_AD6: .equ %01000000 mIICA_AD7: .equ %10000000 ;*** IICF - IIC Frequency Divider Register; 0xFFFF8061 *** IICF: .equ $FFFF8061 ;*** IICF - IIC Frequency Divider Register; 0xFFFF8061 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICF_ICR0: .equ 0 ; IIC Clock Rate Bit 0 IICF_ICR1: .equ 1 ; IIC Clock Rate Bit 1 IICF_ICR2: .equ 2 ; IIC Clock Rate Bit 2 IICF_ICR3: .equ 3 ; IIC Clock Rate Bit 3 IICF_ICR4: .equ 4 ; IIC Clock Rate Bit 4 IICF_ICR5: .equ 5 ; IIC Clock Rate Bit 5 IICF_MULT0: .equ 6 ; Multiplier Factor Bit 0 IICF_MULT1: .equ 7 ; Multiplier Factor Bit 1 ; bit position masks mIICF_ICR0: .equ %00000001 mIICF_ICR1: .equ %00000010 mIICF_ICR2: .equ %00000100 mIICF_ICR3: .equ %00001000 mIICF_ICR4: .equ %00010000 mIICF_ICR5: .equ %00100000 mIICF_MULT0: .equ %01000000 mIICF_MULT1: .equ %10000000 ;*** IICC1 - IIC Control Register 1; 0xFFFF8062 *** IICC1: .equ $FFFF8062 ;*** IICC1 - IIC Control Register 1; 0xFFFF8062 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICC1_RSTA: .equ 2 ; Repeat START IICC1_TXAK: .equ 3 ; Transmit Acknowledge Enable IICC1_TX: .equ 4 ; Transmit Mode Select IICC1_MST: .equ 5 ; Master Mode Select IICC1_IICIE: .equ 6 ; IIC Interrupt Enable IICC1_IICEN: .equ 7 ; IIC Enable ; bit position masks mIICC1_RSTA: .equ %00000100 mIICC1_TXAK: .equ %00001000 mIICC1_TX: .equ %00010000 mIICC1_MST: .equ %00100000 mIICC1_IICIE: .equ %01000000 mIICC1_IICEN: .equ %10000000 ;*** IICC - IIC Control Register; 0xFFFF8062 *** IICC: .equ $FFFF8062 ;*** IICC - IIC Control Register; 0xFFFF8062 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICC_RSTA: .equ 2 ; Repeat START IICC_TXAK: .equ 3 ; Transmit Acknowledge Enable IICC_TX: .equ 4 ; Transmit Mode Select IICC_MST: .equ 5 ; Master Mode Select IICC_IICIE: .equ 6 ; IIC Interrupt Enable IICC_IICEN: .equ 7 ; IIC Enable ; bit position masks mIICC_RSTA: .equ %00000100 mIICC_TXAK: .equ %00001000 mIICC_TX: .equ %00010000 mIICC_MST: .equ %00100000 mIICC_IICIE: .equ %01000000 mIICC_IICEN: .equ %10000000 ;*** IICS - IIC Status Register; 0xFFFF8063 *** IICS: .equ $FFFF8063 ;*** IICS - IIC Status Register; 0xFFFF8063 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICS_RXAK: .equ 0 ; Receive Acknowledge IICS_IICIF: .equ 1 ; IIC Interrupt Flag IICS_SRW: .equ 2 ; Slave Read/Write IICS_ARBL: .equ 4 ; Arbitration Lost IICS_BUSY: .equ 5 ; Bus Busy IICS_IAAS: .equ 6 ; Addressed as a Slave IICS_TCF: .equ 7 ; Transfer Complete Flag ; bit position masks mIICS_RXAK: .equ %00000001 mIICS_IICIF: .equ %00000010 mIICS_SRW: .equ %00000100 mIICS_ARBL: .equ %00010000 mIICS_BUSY: .equ %00100000 mIICS_IAAS: .equ %01000000 mIICS_TCF: .equ %10000000 ;*** IICD - IIC Data I/O Register; 0xFFFF8064 *** IICD: .equ $FFFF8064 ;*** IICD - IIC Data I/O Register; 0xFFFF8064 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICD_DATA0: .equ 0 ; IIC Data Bit 0 IICD_DATA1: .equ 1 ; IIC Data Bit 1 IICD_DATA2: .equ 2 ; IIC Data Bit 2 IICD_DATA3: .equ 3 ; IIC Data Bit 3 IICD_DATA4: .equ 4 ; IIC Data Bit 4 IICD_DATA5: .equ 5 ; IIC Data Bit 5 IICD_DATA6: .equ 6 ; IIC Data Bit 6 IICD_DATA7: .equ 7 ; IIC Data Bit 7 ; bit position masks mIICD_DATA0: .equ %00000001 mIICD_DATA1: .equ %00000010 mIICD_DATA2: .equ %00000100 mIICD_DATA3: .equ %00001000 mIICD_DATA4: .equ %00010000 mIICD_DATA5: .equ %00100000 mIICD_DATA6: .equ %01000000 mIICD_DATA7: .equ %10000000 ;*** IICC2 - IIC Control Register 2; 0xFFFF8065 *** IICC2: .equ $FFFF8065 ;*** IICC2 - IIC Control Register 2; 0xFFFF8065 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICC2_AD8: .equ 0 ; Slave Address Bit 8 IICC2_AD9: .equ 1 ; Slave Address Bit 9 IICC2_AD10: .equ 2 ; Slave Address Bit 10 IICC2_ADEXT: .equ 6 ; Address Extension IICC2_GCAEN: .equ 7 ; General Call Address Enable ; bit position masks mIICC2_AD8: .equ %00000001 mIICC2_AD9: .equ %00000010 mIICC2_AD10: .equ %00000100 mIICC2_ADEXT: .equ %01000000 mIICC2_GCAEN: .equ %10000000 ;*** IICSMB - SMBus Control and Status Register; 0xFFFF8066 *** IICSMB: .equ $FFFF8066 ;*** IICSMB - SMBus Control and Status Register; 0xFFFF8066 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICSMB_SHTF: .equ 2 ; SCL High Timeout Flag IICSMB_SLTF: .equ 3 ; SCL Low Timeout Flag IICSMB_TCKSEL: .equ 4 ; Time Out Counter Clock Select IICSMB_SIICAEN: .equ 5 ; Second IIC Address Enable IICSMB_ALERTEN: .equ 6 ; SMBus Alert Response Address Enable IICSMB_FACK: .equ 7 ; Fast NACK/ACK enable ; bit position masks mIICSMB_SHTF: .equ %00000100 mIICSMB_SLTF: .equ %00001000 mIICSMB_TCKSEL: .equ %00010000 mIICSMB_SIICAEN: .equ %00100000 mIICSMB_ALERTEN: .equ %01000000 mIICSMB_FACK: .equ %10000000 ;*** IICA2 - IIC Address Register 2; 0xFFFF8067 *** IICA2: .equ $FFFF8067 ;*** IICA2 - IIC Address Register 2; 0xFFFF8067 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICA2_SAD1: .equ 1 ; SMBus Address Bit 1 IICA2_SAD2: .equ 2 ; SMBus Address Bit 2 IICA2_SAD3: .equ 3 ; SMBus Address Bit 3 IICA2_SAD4: .equ 4 ; SMBus Address Bit 4 IICA2_SAD5: .equ 5 ; SMBus Address Bit 5 IICA2_SAD6: .equ 6 ; SMBus Address Bit 6 IICA2_SAD7: .equ 7 ; SMBus Address Bit 7 ; bit position masks mIICA2_SAD1: .equ %00000010 mIICA2_SAD2: .equ %00000100 mIICA2_SAD3: .equ %00001000 mIICA2_SAD4: .equ %00010000 mIICA2_SAD5: .equ %00100000 mIICA2_SAD6: .equ %01000000 mIICA2_SAD7: .equ %10000000 ;*** IICSLT - IIC SCL Low Time Out register; 0xFFFF8068 *** IICSLT: .equ $FFFF8068 ;*** IICSLT - IIC SCL Low Time Out register; 0xFFFF8068 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICSLT_SSLT0: .equ 0 ; SCL Low Time Out Bits, bit 0 IICSLT_SSLT1: .equ 1 ; SCL Low Time Out Bits, bit 1 IICSLT_SSLT2: .equ 2 ; SCL Low Time Out Bits, bit 2 IICSLT_SSLT3: .equ 3 ; SCL Low Time Out Bits, bit 3 IICSLT_SSLT4: .equ 4 ; SCL Low Time Out Bits, bit 4 IICSLT_SSLT5: .equ 5 ; SCL Low Time Out Bits, bit 5 IICSLT_SSLT6: .equ 6 ; SCL Low Time Out Bits, bit 6 IICSLT_SSLT7: .equ 7 ; SCL Low Time Out Bits, bit 7 IICSLT_SSLT8: .equ 8 ; SCL Low Time Out Bits, bit 8 IICSLT_SSLT9: .equ 9 ; SCL Low Time Out Bits, bit 9 IICSLT_SSLT10: .equ 10 ; SCL Low Time Out Bits, bit 10 IICSLT_SSLT11: .equ 11 ; SCL Low Time Out Bits, bit 11 IICSLT_SSLT12: .equ 12 ; SCL Low Time Out Bits, bit 12 IICSLT_SSLT13: .equ 13 ; SCL Low Time Out Bits, bit 13 IICSLT_SSLT14: .equ 14 ; SCL Low Time Out Bits, bit 14 IICSLT_SSLT15: .equ 15 ; SCL Low Time Out Bits, bit 15 ; bit position masks mIICSLT_SSLT0: .equ %00000001 mIICSLT_SSLT1: .equ %00000010 mIICSLT_SSLT2: .equ %00000100 mIICSLT_SSLT3: .equ %00001000 mIICSLT_SSLT4: .equ %00010000 mIICSLT_SSLT5: .equ %00100000 mIICSLT_SSLT6: .equ %01000000 mIICSLT_SSLT7: .equ %10000000 mIICSLT_SSLT8: .equ %100000000 mIICSLT_SSLT9: .equ %1000000000 mIICSLT_SSLT10: .equ %10000000000 mIICSLT_SSLT11: .equ %100000000000 mIICSLT_SSLT12: .equ %1000000000000 mIICSLT_SSLT13: .equ %10000000000000 mIICSLT_SSLT14: .equ %100000000000000 mIICSLT_SSLT15: .equ %1000000000000000 ;*** IICSLTH - IIC SCL Low Time Out register - High byte; 0xFFFF8068 *** IICSLTH: .equ $FFFF8068 ;*** IICSLTH - IIC SCL Low Time Out register - High byte; 0xFFFF8068 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICSLTH_SSLT8: .equ 0 ; SCL Low Time Out Bit 8 IICSLTH_SSLT9: .equ 1 ; SCL Low Time Out Bit 9 IICSLTH_SSLT10: .equ 2 ; SCL Low Time Out Bit 10 IICSLTH_SSLT11: .equ 3 ; SCL Low Time Out Bit 11 IICSLTH_SSLT12: .equ 4 ; SCL Low Time Out Bit 12 IICSLTH_SSLT13: .equ 5 ; SCL Low Time Out Bit 13 IICSLTH_SSLT14: .equ 6 ; SCL Low Time Out Bit 14 IICSLTH_SSLT15: .equ 7 ; SCL Low Time Out Bit 15 ; bit position masks mIICSLTH_SSLT8: .equ %00000001 mIICSLTH_SSLT9: .equ %00000010 mIICSLTH_SSLT10: .equ %00000100 mIICSLTH_SSLT11: .equ %00001000 mIICSLTH_SSLT12: .equ %00010000 mIICSLTH_SSLT13: .equ %00100000 mIICSLTH_SSLT14: .equ %01000000 mIICSLTH_SSLT15: .equ %10000000 ;*** IICSLTL - IIC SCL Low Time Out register - Low byte; 0xFFFF8069 *** IICSLTL: .equ $FFFF8069 ;*** IICSLTL - IIC SCL Low Time Out register - Low byte; 0xFFFF8069 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICSLTL_SSLT0: .equ 0 ; SCL Low Time Out Bits, bit 0 IICSLTL_SSLT1: .equ 1 ; SCL Low Time Out Bits, bit 1 IICSLTL_SSLT2: .equ 2 ; SCL Low Time Out Bits, bit 2 IICSLTL_SSLT3: .equ 3 ; SCL Low Time Out Bits, bit 3 IICSLTL_SSLT4: .equ 4 ; SCL Low Time Out Bits, bit 4 IICSLTL_SSLT5: .equ 5 ; SCL Low Time Out Bits, bit 5 IICSLTL_SSLT6: .equ 6 ; SCL Low Time Out Bits, bit 6 IICSLTL_SSLT7: .equ 7 ; SCL Low Time Out Bits, bit 7 ; bit position masks mIICSLTL_SSLT0: .equ %00000001 mIICSLTL_SSLT1: .equ %00000010 mIICSLTL_SSLT2: .equ %00000100 mIICSLTL_SSLT3: .equ %00001000 mIICSLTL_SSLT4: .equ %00010000 mIICSLTL_SSLT5: .equ %00100000 mIICSLTL_SSLT6: .equ %01000000 mIICSLTL_SSLT7: .equ %10000000 ;*** IICFLT - IIC Filter register; 0xFFFF806A *** IICFLT: .equ $FFFF806A ;*** IICFLT - IIC Filter register; 0xFFFF806A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICFLT_FLT0: .equ 0 ; Filter value bit 0 IICFLT_FLT1: .equ 1 ; Filter value bit 1 IICFLT_FLT2: .equ 2 ; Filter value bit 2 IICFLT_FLT3: .equ 3 ; Filter value bit 3 ; bit position masks mIICFLT_FLT0: .equ %00000001 mIICFLT_FLT1: .equ %00000010 mIICFLT_FLT2: .equ %00000100 mIICFLT_FLT3: .equ %00001000 ;*** KBI1SC - KBI1 Status and Control Register; 0xFFFF806C *** KBI1SC: .equ $FFFF806C ;*** KBI1SC - KBI1 Status and Control Register; 0xFFFF806C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET KBI1SC_KBI1MOD: .equ 0 ; Keyboard Detection Mode KBI1SC_KB1IE: .equ 1 ; Keyboard Interrupt Enable KBI1SC_KB1ACK: .equ 2 ; Keyboard Interrupt Acknowledge KBI1SC_KB1F: .equ 3 ; Keyboard Interrupt Flag ; bit position masks mKBI1SC_KBI1MOD: .equ %00000001 mKBI1SC_KB1IE: .equ %00000010 mKBI1SC_KB1ACK: .equ %00000100 mKBI1SC_KB1F: .equ %00001000 ;*** KBI1PE - KBI1 Pin Enable Register; 0xFFFF806D *** KBI1PE: .equ $FFFF806D ;*** KBI1PE - KBI1 Pin Enable Register; 0xFFFF806D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET KBI1PE_KBI1PE0: .equ 0 ; Keyboard Pin Enable for KBI Port Bit 0 KBI1PE_KBI1PE1: .equ 1 ; Keyboard Pin Enable for KBI Port Bit 1 KBI1PE_KBI1PE2: .equ 2 ; Keyboard Pin Enable for KBI Port Bit 2 KBI1PE_KBI1PE3: .equ 3 ; Keyboard Pin Enable for KBI Port Bit 3 KBI1PE_KBI1PE4: .equ 4 ; Keyboard Pin Enable for KBI Port Bit 4 KBI1PE_KBI1PE5: .equ 5 ; Keyboard Pin Enable for KBI Port Bit 5 KBI1PE_KBI1PE6: .equ 6 ; Keyboard Pin Enable for KBI Port Bit 6 KBI1PE_KBI1PE7: .equ 7 ; Keyboard Pin Enable for KBI Port Bit 7 ; bit position masks mKBI1PE_KBI1PE0: .equ %00000001 mKBI1PE_KBI1PE1: .equ %00000010 mKBI1PE_KBI1PE2: .equ %00000100 mKBI1PE_KBI1PE3: .equ %00001000 mKBI1PE_KBI1PE4: .equ %00010000 mKBI1PE_KBI1PE5: .equ %00100000 mKBI1PE_KBI1PE6: .equ %01000000 mKBI1PE_KBI1PE7: .equ %10000000 ;*** KBI1ES - KBI1 Edge Select Register; 0xFFFF806E *** KBI1ES: .equ $FFFF806E ;*** KBI1ES - KBI1 Edge Select Register; 0xFFFF806E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET KBI1ES_KB1EDG0: .equ 0 ; Keyboard Edge Select Bit 0 KBI1ES_KB1EDG1: .equ 1 ; Keyboard Edge Select Bit 1 KBI1ES_KB1EDG2: .equ 2 ; Keyboard Edge Select Bit 2 KBI1ES_KB1EDG3: .equ 3 ; Keyboard Edge Select Bit 3 KBI1ES_KB1EDG4: .equ 4 ; Keyboard Edge Select Bit 4 KBI1ES_KB1EDG5: .equ 5 ; Keyboard Edge Select Bit 5 KBI1ES_KB1EDG6: .equ 6 ; Keyboard Edge Select Bit 6 KBI1ES_KB1EDG7: .equ 7 ; Keyboard Edge Select Bit 7 ; bit position masks mKBI1ES_KB1EDG0: .equ %00000001 mKBI1ES_KB1EDG1: .equ %00000010 mKBI1ES_KB1EDG2: .equ %00000100 mKBI1ES_KB1EDG3: .equ %00001000 mKBI1ES_KB1EDG4: .equ %00010000 mKBI1ES_KB1EDG5: .equ %00100000 mKBI1ES_KB1EDG6: .equ %01000000 mKBI1ES_KB1EDG7: .equ %10000000 ;*** SPI1C1 - SPI1 Control Register 1; 0xFFFF8070 *** SPI1C1: .equ $FFFF8070 ;*** SPI1C1 - SPI1 Control Register 1; 0xFFFF8070 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI1C1_LSBFE: .equ 0 ; LSB First (Shifter Direction) SPI1C1_SSOE: .equ 1 ; Slave Select Output Enable SPI1C1_CPHA: .equ 2 ; Clock Phase SPI1C1_CPOL: .equ 3 ; Clock Polarity SPI1C1_MSTR: .equ 4 ; Master/Slave Mode Select SPI1C1_SPTIE: .equ 5 ; SPI Transmit Interrupt Enable SPI1C1_SPE: .equ 6 ; SPI System Enable SPI1C1_SPIE: .equ 7 ; SPI Interrupt Enable (for SPRF and MODF) ; bit position masks mSPI1C1_LSBFE: .equ %00000001 mSPI1C1_SSOE: .equ %00000010 mSPI1C1_CPHA: .equ %00000100 mSPI1C1_CPOL: .equ %00001000 mSPI1C1_MSTR: .equ %00010000 mSPI1C1_SPTIE: .equ %00100000 mSPI1C1_SPE: .equ %01000000 mSPI1C1_SPIE: .equ %10000000 ;*** SPI1C2 - SPI1 Control Register 2; 0xFFFF8071 *** SPI1C2: .equ $FFFF8071 ;*** SPI1C2 - SPI1 Control Register 2; 0xFFFF8071 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI1C2_SPC0: .equ 0 ; SPI Pin Control 0 SPI1C2_SPISWAI: .equ 1 ; SPI Stop in Wait Mode SPI1C2_BIDIROE: .equ 3 ; Bidirectional Mode Output Enable SPI1C2_MODFEN: .equ 4 ; Master Mode-Fault Function Enable SPI1C2_SPIMODE: .equ 6 ; SPI 8- or 16-bit Mode Select SPI1C2_SPMIE: .equ 7 ; SPI Match Interrupt Enable ; bit position masks mSPI1C2_SPC0: .equ %00000001 mSPI1C2_SPISWAI: .equ %00000010 mSPI1C2_BIDIROE: .equ %00001000 mSPI1C2_MODFEN: .equ %00010000 mSPI1C2_SPIMODE: .equ %01000000 mSPI1C2_SPMIE: .equ %10000000 ;*** SPI1BR - SPI1 Baud Rate Register; 0xFFFF8072 *** SPI1BR: .equ $FFFF8072 ;*** SPI1BR - SPI1 Baud Rate Register; 0xFFFF8072 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI1BR_SPR0: .equ 0 ; SPI Baud Rate Divisor Bit 0 SPI1BR_SPR1: .equ 1 ; SPI Baud Rate Divisor Bit 1 SPI1BR_SPR2: .equ 2 ; SPI Baud Rate Divisor Bit 2 SPI1BR_SPR3: .equ 3 ; SPI Baud Rate Divisor Bit 3 SPI1BR_SPPR0: .equ 4 ; SPI Baud Rate Prescale Divisor Bit 0 SPI1BR_SPPR1: .equ 5 ; SPI Baud Rate Prescale Divisor Bit 1 SPI1BR_SPPR2: .equ 6 ; SPI Baud Rate Prescale Divisor Bit 2 ; bit position masks mSPI1BR_SPR0: .equ %00000001 mSPI1BR_SPR1: .equ %00000010 mSPI1BR_SPR2: .equ %00000100 mSPI1BR_SPR3: .equ %00001000 mSPI1BR_SPPR0: .equ %00010000 mSPI1BR_SPPR1: .equ %00100000 mSPI1BR_SPPR2: .equ %01000000 ;*** SPI1S - SPI1 Status Register; 0xFFFF8073 *** SPI1S: .equ $FFFF8073 ;*** SPI1S - SPI1 Status Register; 0xFFFF8073 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI1S_RFIFOEF: .equ 0 ; SPI Read FIFO Empty Flag SPI1S_TXFULLF: .equ 1 ; SPI Transmit FIFO Full Flag SPI1S_TNEAREF: .equ 2 ; SPI Transmit FIFO Nearly Empty Flag SPI1S_RNFULLF: .equ 3 ; SPI Receive FIFO Nearly Full Flag SPI1S_MODF: .equ 4 ; Master Mode Fault Flag SPI1S_SPTEF: .equ 5 ; SPI Transmit Buffer Empty Flag SPI1S_SPMF: .equ 6 ; SPI Match Flag SPI1S_SPRF: .equ 7 ; SPI Read Buffer Full Flag ; bit position masks mSPI1S_RFIFOEF: .equ %00000001 mSPI1S_TXFULLF: .equ %00000010 mSPI1S_TNEAREF: .equ %00000100 mSPI1S_RNFULLF: .equ %00001000 mSPI1S_MODF: .equ %00010000 mSPI1S_SPTEF: .equ %00100000 mSPI1S_SPMF: .equ %01000000 mSPI1S_SPRF: .equ %10000000 ;*** SPI1D16 - SPI1 Data Register; 0xFFFF8074 *** SPI1D16: .equ $FFFF8074 ;*** SPI1D16 - SPI1 Data Register; 0xFFFF8074 *** ;*** SPI1DH - SPI1 Data Register High; 0xFFFF8074 *** SPI1DH: .equ $FFFF8074 ;*** SPI1DH - SPI1 Data Register High; 0xFFFF8074 *** ;*** SPI1DL - SPI1 Data Register Low; 0xFFFF8075 *** SPI1DL: .equ $FFFF8075 ;*** SPI1DL - SPI1 Data Register Low; 0xFFFF8075 *** ;*** SPI1D - SPI1 Data Register Low; 0xFFFF8075 *** SPI1D: .equ $FFFF8075 ;*** SPI1D - SPI1 Data Register Low; 0xFFFF8075 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI1D_Bit0: .equ 0 ; SPI Data Bit 0 SPI1D_Bit1: .equ 1 ; SPI Data Bit 1 SPI1D_Bit2: .equ 2 ; SPI Data Bit 2 SPI1D_Bit3: .equ 3 ; SPI Data Bit 3 SPI1D_Bit4: .equ 4 ; SPI Data Bit 4 SPI1D_Bit5: .equ 5 ; SPI Data Bit 5 SPI1D_Bit6: .equ 6 ; SPI Data Bit 6 SPI1D_Bit7: .equ 7 ; SPI Data Bit 7 ; bit position masks mSPI1D_Bit0: .equ %00000001 mSPI1D_Bit1: .equ %00000010 mSPI1D_Bit2: .equ %00000100 mSPI1D_Bit3: .equ %00001000 mSPI1D_Bit4: .equ %00010000 mSPI1D_Bit5: .equ %00100000 mSPI1D_Bit6: .equ %01000000 mSPI1D_Bit7: .equ %10000000 ;*** SPI1M - SPI1 Match Register; 0xFFFF8076 *** SPI1M: .equ $FFFF8076 ;*** SPI1M - SPI1 Match Register; 0xFFFF8076 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI1M_Bit0: .equ 0 ; SPI Match Value Bit 0 SPI1M_Bit1: .equ 1 ; SPI Match Value Bit 1 SPI1M_Bit2: .equ 2 ; SPI Match Value Bit 2 SPI1M_Bit3: .equ 3 ; SPI Match Value Bit 3 SPI1M_Bit4: .equ 4 ; SPI Match Value Bit 4 SPI1M_Bit5: .equ 5 ; SPI Match Value Bit 5 SPI1M_Bit6: .equ 6 ; SPI Match Value Bit 6 SPI1M_Bit7: .equ 7 ; SPI Match Value Bit 7 SPI1M_Bit8: .equ 8 ; SPI Match Value Bit 8 SPI1M_Bit9: .equ 9 ; SPI Match Value Bit 9 SPI1M_Bit10: .equ 10 ; SPI Match Value Bit 10 SPI1M_Bit11: .equ 11 ; SPI Match Value Bit 11 SPI1M_Bit12: .equ 12 ; SPI Match Value Bit 12 SPI1M_Bit13: .equ 13 ; SPI Match Value Bit 13 SPI1M_Bit14: .equ 14 ; SPI Match Value Bit 14 SPI1M_Bit15: .equ 15 ; SPI Match Value Bit 15 ; bit position masks mSPI1M_Bit0: .equ %00000001 mSPI1M_Bit1: .equ %00000010 mSPI1M_Bit2: .equ %00000100 mSPI1M_Bit3: .equ %00001000 mSPI1M_Bit4: .equ %00010000 mSPI1M_Bit5: .equ %00100000 mSPI1M_Bit6: .equ %01000000 mSPI1M_Bit7: .equ %10000000 mSPI1M_Bit8: .equ %100000000 mSPI1M_Bit9: .equ %1000000000 mSPI1M_Bit10: .equ %10000000000 mSPI1M_Bit11: .equ %100000000000 mSPI1M_Bit12: .equ %1000000000000 mSPI1M_Bit13: .equ %10000000000000 mSPI1M_Bit14: .equ %100000000000000 mSPI1M_Bit15: .equ %1000000000000000 ;*** SPI1MH - SPI1 Match Register High; 0xFFFF8076 *** SPI1MH: .equ $FFFF8076 ;*** SPI1MH - SPI1 Match Register High; 0xFFFF8076 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI1MH_Bit8: .equ 0 ; SPI Match Value Bit 8 SPI1MH_Bit9: .equ 1 ; SPI Match Value Bit 9 SPI1MH_Bit10: .equ 2 ; SPI Match Value Bit 10 SPI1MH_Bit11: .equ 3 ; SPI Match Value Bit 11 SPI1MH_Bit12: .equ 4 ; SPI Match Value Bit 12 SPI1MH_Bit13: .equ 5 ; SPI Match Value Bit 13 SPI1MH_Bit14: .equ 6 ; SPI Match Value Bit 14 SPI1MH_Bit15: .equ 7 ; SPI Match Value Bit 15 ; bit position masks mSPI1MH_Bit8: .equ %00000001 mSPI1MH_Bit9: .equ %00000010 mSPI1MH_Bit10: .equ %00000100 mSPI1MH_Bit11: .equ %00001000 mSPI1MH_Bit12: .equ %00010000 mSPI1MH_Bit13: .equ %00100000 mSPI1MH_Bit14: .equ %01000000 mSPI1MH_Bit15: .equ %10000000 ;*** SPI1ML - SPI1 Match Register Low; 0xFFFF8077 *** SPI1ML: .equ $FFFF8077 ;*** SPI1ML - SPI1 Match Register Low; 0xFFFF8077 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI1ML_Bit0: .equ 0 ; SPI Match Value Bit 0 SPI1ML_Bit1: .equ 1 ; SPI Match Value Bit 1 SPI1ML_Bit2: .equ 2 ; SPI Match Value Bit 2 SPI1ML_Bit3: .equ 3 ; SPI Match Value Bit 3 SPI1ML_Bit4: .equ 4 ; SPI Match Value Bit 4 SPI1ML_Bit5: .equ 5 ; SPI Match Value Bit 5 SPI1ML_Bit6: .equ 6 ; SPI Match Value Bit 6 SPI1ML_Bit7: .equ 7 ; SPI Match Value Bit 7 ; bit position masks mSPI1ML_Bit0: .equ %00000001 mSPI1ML_Bit1: .equ %00000010 mSPI1ML_Bit2: .equ %00000100 mSPI1ML_Bit3: .equ %00001000 mSPI1ML_Bit4: .equ %00010000 mSPI1ML_Bit5: .equ %00100000 mSPI1ML_Bit6: .equ %01000000 mSPI1ML_Bit7: .equ %10000000 ;*** SPI1C3 - SPI1 Control Register 3; 0xFFFF8078 *** SPI1C3: .equ $FFFF8078 ;*** SPI1C3 - SPI1 Control Register 3; 0xFFFF8078 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI1C3_FIFOMODE: .equ 0 ; SPI FIFO Mode Enable SPI1C3_RNFULLIEN: .equ 1 ; Receive FIFO Nearly Full Interrupt Enable. This is an additional interrupt on the SPI and will only interrupt the CPU if SPIE in the SPIxC1 register is also set. This bit is ignored and has no function if FIFOMODE=0 SPI1C3_TNEARIEN: .equ 2 ; Transmit FIFO Nearly Empty Interrupt Enable. This is an additional interrupt on the SPI and will only interrupt the CPU if SPTIE in the
SPIxC1 register is also set. This bit is ignored and has no function if FIFOMODE=0 SPI1C3_INTCLR: .equ 3 ; Interrupt Clearing Mechanism Select - This bit selects the mechanism by which SPRF, SPTEF, TNEAREF, RNFULLF interrupts gets cleared SPI1C3_RNFULLF_MARK: .equ 4 ; Receive FIFO Nearly Full Water Mark - This bit selects the mark for which RNFULLF flag is asserted SPI1C3_TNEAREF_MARK: .equ 5 ; Transmit FIFO Nearly Empty Water Mark - This bit selects the mark after which TNEAREF flag is asserted ; bit position masks mSPI1C3_FIFOMODE: .equ %00000001 mSPI1C3_RNFULLIEN: .equ %00000010 mSPI1C3_TNEARIEN: .equ %00000100 mSPI1C3_INTCLR: .equ %00001000 mSPI1C3_RNFULLF_MARK: .equ %00010000 mSPI1C3_TNEAREF_MARK: .equ %00100000 ;*** SPI1CI - SPI1 Clear Interrupt Register; 0xFFFF8079 *** SPI1CI: .equ $FFFF8079 ;*** SPI1CI - SPI1 Clear Interrupt Register; 0xFFFF8079 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI1CI_SPRFCI: .equ 0 ; Receive FIFO Full Flag Clear Interrupt Bit - Write of 1 clears the TNEAREF interrupt provided SPIxC3[3] is set SPI1CI_SPTEFCI: .equ 1 ; Transmit FIFO Empty Flag Clear Interrupt Bit - Write of 1 clears the SPTEF interrupt provided SPIxC3[3] SPTEFCI is set SPI1CI_RNFULLFCI: .equ 2 ; Receive FIFO Nearly Full Flag Clear Interrupt - Write of 1 clears the RNFULLF interrupt provided SPIxC3[3] is set SPI1CI_TNEAREFCI: .equ 3 ; Transmit FIFO Nearly Empty Flag Clear Interrupt Bit - Write of 1 clears the TNEAREF interrupt provided SPIxC3[3] is set SPI1CI_RXFOF: .equ 4 ; RX FIFO Overflow Flag - This Flag indicates that RX FIFO overflow condition has occured SPI1CI_TXFOF: .equ 5 ; TX FIFO Overflow Flag - This Flag indicates that TX FIFO overflow condition has occured SPI1CI_RXFERR: .equ 6 ; Receive FIFO Error Flag - This flag indicates that RX FIFO error occured because entries in fifo goes above 8 SPI1CI_TXFERR: .equ 7 ; Transmit FIFO ErrorFlag - This flag indicates that TX FIFO error occured because entries in fifo goes above 8 ; bit position masks mSPI1CI_SPRFCI: .equ %00000001 mSPI1CI_SPTEFCI: .equ %00000010 mSPI1CI_RNFULLFCI: .equ %00000100 mSPI1CI_TNEAREFCI: .equ %00001000 mSPI1CI_RXFOF: .equ %00010000 mSPI1CI_TXFOF: .equ %00100000 mSPI1CI_RXFERR: .equ %01000000 mSPI1CI_TXFERR: .equ %10000000 ;*** KBI2SC - KBI2 Status and Control Register; 0xFFFF807C *** KBI2SC: .equ $FFFF807C ;*** KBI2SC - KBI2 Status and Control Register; 0xFFFF807C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET KBI2SC_KBI2MOD: .equ 0 ; Keyboard Detection Mode KBI2SC_KB2IE: .equ 1 ; Keyboard Interrupt Enable KBI2SC_KB2ACK: .equ 2 ; Keyboard Interrupt Acknowledge KBI2SC_KB2F: .equ 3 ; Keyboard Interrupt Flag ; bit position masks mKBI2SC_KBI2MOD: .equ %00000001 mKBI2SC_KB2IE: .equ %00000010 mKBI2SC_KB2ACK: .equ %00000100 mKBI2SC_KB2F: .equ %00001000 ;*** KBI2PE - KBI2 Pin Enable Register; 0xFFFF807D *** KBI2PE: .equ $FFFF807D ;*** KBI2PE - KBI2 Pin Enable Register; 0xFFFF807D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET KBI2PE_KBI2PE0: .equ 0 ; Keyboard Pin Enable for KBI Port Bit 0 KBI2PE_KBI2PE1: .equ 1 ; Keyboard Pin Enable for KBI Port Bit 1 KBI2PE_KBI2PE2: .equ 2 ; Keyboard Pin Enable for KBI Port Bit 2 KBI2PE_KBI2PE3: .equ 3 ; Keyboard Pin Enable for KBI Port Bit 3 KBI2PE_KBI2PE4: .equ 4 ; Keyboard Pin Enable for KBI Port Bit 4 KBI2PE_KBI2PE5: .equ 5 ; Keyboard Pin Enable for KBI Port Bit 5 KBI2PE_KBI2PE6: .equ 6 ; Keyboard Pin Enable for KBI Port Bit 6 KBI2PE_KBI2PE7: .equ 7 ; Keyboard Pin Enable for KBI Port Bit 7 ; bit position masks mKBI2PE_KBI2PE0: .equ %00000001 mKBI2PE_KBI2PE1: .equ %00000010 mKBI2PE_KBI2PE2: .equ %00000100 mKBI2PE_KBI2PE3: .equ %00001000 mKBI2PE_KBI2PE4: .equ %00010000 mKBI2PE_KBI2PE5: .equ %00100000 mKBI2PE_KBI2PE6: .equ %01000000 mKBI2PE_KBI2PE7: .equ %10000000 ;*** KBI2ES - KBI2 Edge Select Register; 0xFFFF807E *** KBI2ES: .equ $FFFF807E ;*** KBI2ES - KBI2 Edge Select Register; 0xFFFF807E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET KBI2ES_KB2EDG0: .equ 0 ; Keyboard Edge Select Bit 0 KBI2ES_KB2EDG1: .equ 1 ; Keyboard Edge Select Bit 1 KBI2ES_KB2EDG2: .equ 2 ; Keyboard Edge Select Bit 2 KBI2ES_KB2EDG3: .equ 3 ; Keyboard Edge Select Bit 3 KBI2ES_KB2EDG4: .equ 4 ; Keyboard Edge Select Bit 4 KBI2ES_KB2EDG5: .equ 5 ; Keyboard Edge Select Bit 5 KBI2ES_KB2EDG6: .equ 6 ; Keyboard Edge Select Bit 6 KBI2ES_KB2EDG7: .equ 7 ; Keyboard Edge Select Bit 7 ; bit position masks mKBI2ES_KB2EDG0: .equ %00000001 mKBI2ES_KB2EDG1: .equ %00000010 mKBI2ES_KB2EDG2: .equ %00000100 mKBI2ES_KB2EDG3: .equ %00001000 mKBI2ES_KB2EDG4: .equ %00010000 mKBI2ES_KB2EDG5: .equ %00100000 mKBI2ES_KB2EDG6: .equ %01000000 mKBI2ES_KB2EDG7: .equ %10000000 ;*** SRS - System Reset Status Register; 0xFFFF9800 *** SRS: .equ $FFFF9800 ;*** SRS - System Reset Status Register; 0xFFFF9800 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SRS_LVD: .equ 1 ; Low Voltage Detect SRS_LOC: .equ 2 ; Loss-of-Clock Reset SRS_ILAD: .equ 3 ; Illegal Address SRS_ILOP: .equ 4 ; Illegal Opcode SRS_COP: .equ 5 ; Computer Operating Properly (COP) Watchdog SRS_PIN: .equ 6 ; External Reset Pin SRS_POR: .equ 7 ; Power-On Reset ; bit position masks mSRS_LVD: .equ %00000010 mSRS_LOC: .equ %00000100 mSRS_ILAD: .equ %00001000 mSRS_ILOP: .equ %00010000 mSRS_COP: .equ %00100000 mSRS_PIN: .equ %01000000 mSRS_POR: .equ %10000000 ;*** SOPT1 - System Options Register 1; 0xFFFF9802 *** SOPT1: .equ $FFFF9802 ;*** SOPT1 - System Options Register 1; 0xFFFF9802 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SOPT1_RSTPE: .equ 0 ; RESET Pin Enable SOPT1_BKGDPE: .equ 1 ; Background Debug Mode Pin Enable SOPT1_MBSL: .equ 2 ; MiniFlex Bus Security Level SOPT1_BLMSS: .equ 3 ; Boot Loader Mode Select Status SOPT1_WAITE: .equ 4 ; WAIT Mode Enable SOPT1_STOPE: .equ 5 ; Stop Mode Enable SOPT1_COPT0: .equ 6 ; COP Watchdog Timeout, bit 0 SOPT1_COPT1: .equ 7 ; COP Watchdog Timeout, bit 1 ; bit position masks mSOPT1_RSTPE: .equ %00000001 mSOPT1_BKGDPE: .equ %00000010 mSOPT1_MBSL: .equ %00000100 mSOPT1_BLMSS: .equ %00001000 mSOPT1_WAITE: .equ %00010000 mSOPT1_STOPE: .equ %00100000 mSOPT1_COPT0: .equ %01000000 mSOPT1_COPT1: .equ %10000000 ;*** SOPT2 - System Options Register 2; 0xFFFF9803 *** SOPT2: .equ $FFFF9803 ;*** SOPT2 - System Options Register 2; 0xFFFF9803 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SOPT2_ACIC: .equ 0 ; Analog Comparator to Input Capture Enable SOPT2_CMT_CLK_SEL: .equ 3 ; CMT Clock Select SOPT2_CLKOUT_EN: .equ 4 ; Clock Output Enable SOPT2_USB_BIGEND: .equ 5 ; USB Big Endian SOPT2_COPW: .equ 6 ; COP Window SOPT2_COPCLKS: .equ 7 ; COP Watchdog Clock Select ; bit position masks mSOPT2_ACIC: .equ %00000001 mSOPT2_CMT_CLK_SEL: .equ %00001000 mSOPT2_CLKOUT_EN: .equ %00010000 mSOPT2_USB_BIGEND: .equ %00100000 mSOPT2_COPW: .equ %01000000 mSOPT2_COPCLKS: .equ %10000000 ;*** SDID - System Device Identification Register; 0xFFFF9806 *** SDID: .equ $FFFF9806 ;*** SDID - System Device Identification Register; 0xFFFF9806 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SDID_ID0: .equ 0 ; Part Identification Number, bit 0 SDID_ID1: .equ 1 ; Part Identification Number, bit 1 SDID_ID2: .equ 2 ; Part Identification Number, bit 2 SDID_ID3: .equ 3 ; Part Identification Number, bit 3 SDID_ID4: .equ 4 ; Part Identification Number, bit 4 SDID_ID5: .equ 5 ; Part Identification Number, bit 5 SDID_ID6: .equ 6 ; Part Identification Number, bit 6 SDID_ID7: .equ 7 ; Part Identification Number, bit 7 SDID_ID8: .equ 8 ; Part Identification Number, bit 8 SDID_ID9: .equ 9 ; Part Identification Number, bit 9 SDID_ID10: .equ 10 ; Part Identification Number, bit 10 SDID_ID11: .equ 11 ; Part Identification Number, bit 11 SDID_REV0: .equ 12 ; Revision Number SDID_REV1: .equ 13 ; Revision Number, bit 1 SDID_REV2: .equ 14 ; Revision Number, bit 2 SDID_REV3: .equ 15 ; Revision Number, bit 3 ; bit position masks mSDID_ID0: .equ %00000001 mSDID_ID1: .equ %00000010 mSDID_ID2: .equ %00000100 mSDID_ID3: .equ %00001000 mSDID_ID4: .equ %00010000 mSDID_ID5: .equ %00100000 mSDID_ID6: .equ %01000000 mSDID_ID7: .equ %10000000 mSDID_ID8: .equ %100000000 mSDID_ID9: .equ %1000000000 mSDID_ID10: .equ %10000000000 mSDID_ID11: .equ %100000000000 mSDID_REV0: .equ %1000000000000 mSDID_REV1: .equ %10000000000000 mSDID_REV2: .equ %100000000000000 mSDID_REV3: .equ %1000000000000000 ;*** SDIDH - System Device Identification Register High; 0xFFFF9806 *** SDIDH: .equ $FFFF9806 ;*** SDIDH - System Device Identification Register High; 0xFFFF9806 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SDIDH_ID8: .equ 0 ; Part Identification Number, bit 8 SDIDH_ID9: .equ 1 ; Part Identification Number, bit 9 SDIDH_ID10: .equ 2 ; Part Identification Number, bit 10 SDIDH_ID11: .equ 3 ; Part Identification Number, bit 11 SDIDH_REV0: .equ 4 ; Revision Number, bit 0 SDIDH_REV1: .equ 5 ; Revision Number, bit 1 SDIDH_REV2: .equ 6 ; Revision Number, bit 2 SDIDH_REV3: .equ 7 ; Revision Number, bit 3 ; bit position masks mSDIDH_ID8: .equ %00000001 mSDIDH_ID9: .equ %00000010 mSDIDH_ID10: .equ %00000100 mSDIDH_ID11: .equ %00001000 mSDIDH_REV0: .equ %00010000 mSDIDH_REV1: .equ %00100000 mSDIDH_REV2: .equ %01000000 mSDIDH_REV3: .equ %10000000 ;*** SDIDL - System Device Identification Register Low; 0xFFFF9807 *** SDIDL: .equ $FFFF9807 ;*** SDIDL - System Device Identification Register Low; 0xFFFF9807 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SDIDL_ID0: .equ 0 ; Part Identification Number, bit 0 SDIDL_ID1: .equ 1 ; Part Identification Number, bit 1 SDIDL_ID2: .equ 2 ; Part Identification Number, bit 2 SDIDL_ID3: .equ 3 ; Part Identification Number, bit 3 SDIDL_ID4: .equ 4 ; Part Identification Number, bit 4 SDIDL_ID5: .equ 5 ; Part Identification Number, bit 5 SDIDL_ID6: .equ 6 ; Part Identification Number, bit 6 SDIDL_ID7: .equ 7 ; Part Identification Number, bit 7 ; bit position masks mSDIDL_ID0: .equ %00000001 mSDIDL_ID1: .equ %00000010 mSDIDL_ID2: .equ %00000100 mSDIDL_ID3: .equ %00001000 mSDIDL_ID4: .equ %00010000 mSDIDL_ID5: .equ %00100000 mSDIDL_ID6: .equ %01000000 mSDIDL_ID7: .equ %10000000 ;*** SCGC1 - System Clock Gating Control 1 Register; 0xFFFF9808 *** SCGC1: .equ $FFFF9808 ;*** SCGC1 - System Clock Gating Control 1 Register; 0xFFFF9808 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCGC1_SCI1: .equ 0 ; SCI1 Clock Gate Control SCGC1_SCI2: .equ 1 ; SCI2 Clock Gate Control SCGC1_IIC: .equ 2 ; IIC Clock Gate Control SCGC1_DAC: .equ 3 ; DAC Clock Gate Control SCGC1_ADC: .equ 4 ; ADC Clock Gate Control SCGC1_TPM1: .equ 5 ; TPM1 Clock Gate Control SCGC1_TPM2: .equ 6 ; TPM2 Clock Gate Control SCGC1_CMT: .equ 7 ; CMT Clock Gate Control ; bit position masks mSCGC1_SCI1: .equ %00000001 mSCGC1_SCI2: .equ %00000010 mSCGC1_IIC: .equ %00000100 mSCGC1_DAC: .equ %00001000 mSCGC1_ADC: .equ %00010000 mSCGC1_TPM1: .equ %00100000 mSCGC1_TPM2: .equ %01000000 mSCGC1_CMT: .equ %10000000 ;*** SCGC2 - System Clock Gating Control 2 Register; 0xFFFF9809 *** SCGC2: .equ $FFFF9809 ;*** SCGC2 - System Clock Gating Control 2 Register; 0xFFFF9809 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCGC2_SPI1: .equ 0 ; SPI1 Clock Gate Control SCGC2_SPI2: .equ 1 ; SPI2 Clock Gate Control SCGC2_MFB: .equ 2 ; MFB Clock Gate Control SCGC2_PRACMP: .equ 3 ; PRACMP Clock Gate Control SCGC2_KBI: .equ 4 ; KBI Clock Gate Control SCGC2_IRQ: .equ 5 ; IRQ Clock Gate Control SCGC2_PDB: .equ 6 ; PDB Register Clock Gate Control SCGC2_USB: .equ 7 ; USB Clock Gate Control ; bit position masks mSCGC2_SPI1: .equ %00000001 mSCGC2_SPI2: .equ %00000010 mSCGC2_MFB: .equ %00000100 mSCGC2_PRACMP: .equ %00001000 mSCGC2_KBI: .equ %00010000 mSCGC2_IRQ: .equ %00100000 mSCGC2_PDB: .equ %01000000 mSCGC2_USB: .equ %10000000 ;*** SCGC3 - System Clock Gating Control 3 Register; 0xFFFF980A *** SCGC3: .equ $FFFF980A ;*** SCGC3 - System Clock Gating Control 3 Register; 0xFFFF980A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCGC3_GPOA1: .equ 0 ; GPOA1 Clock Gate Control SCGC3_GPOA2: .equ 1 ; GPOA2 Clock Gate Control SCGC3_TRIAMP1: .equ 2 ; TRIAMP1 Clock Gate Control SCGC3_TRIAMP2: .equ 3 ; TRIAMP2 Clock Gate Control SCGC3_FLS1: .equ 4 ; FLS1 Clock Gate Control SCGC3_FLS2: .equ 5 ; FLS2 Clock Gate Control SCGC3_CRC: .equ 6 ; CRC Clock Gate Control SCGC3_VREF: .equ 7 ; VREF Clock Gate Control ; bit position masks mSCGC3_GPOA1: .equ %00000001 mSCGC3_GPOA2: .equ %00000010 mSCGC3_TRIAMP1: .equ %00000100 mSCGC3_TRIAMP2: .equ %00001000 mSCGC3_FLS1: .equ %00010000 mSCGC3_FLS2: .equ %00100000 mSCGC3_CRC: .equ %01000000 mSCGC3_VREF: .equ %10000000 ;*** SOPT3 - System Options 3 Register; 0xFFFF980B *** SOPT3: .equ $FFFF980B ;*** SOPT3 - System Options 3 Register; 0xFFFF980B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SOPT3_CMT_PAD: .equ 0 ; CMT pad drive strength SOPT3_SCI1_PAD: .equ 1 ; SCI_PAD pad drive strength SOPT3_ARRAYSEL: .equ 2 ; Array Select SOPT3_MB_DATA: .equ 3 ; Mini-FlexBus Data bus configuration SOPT3_USBPS: .equ 4 ; USB Pin Select SOPT3_IICPS: .equ 5 ; IIC Pin Select SOPT3_SCI1PS: .equ 6 ; SCI1 Pin Select SOPT3_SCI2PS: .equ 7 ; SCI2 Pin Select ; bit position masks mSOPT3_CMT_PAD: .equ %00000001 mSOPT3_SCI1_PAD: .equ %00000010 mSOPT3_ARRAYSEL: .equ %00000100 mSOPT3_MB_DATA: .equ %00001000 mSOPT3_USBPS: .equ %00010000 mSOPT3_IICPS: .equ %00100000 mSOPT3_SCI1PS: .equ %01000000 mSOPT3_SCI2PS: .equ %10000000 ;*** SOPT4 - System Options 4 Register; 0xFFFF980C *** SOPT4: .equ $FFFF980C ;*** SOPT4 - System Options 4 Register; 0xFFFF980C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SOPT4_IRODSE: .equ 0 ; Drive Strength Control Enable for IRO pin SOPT4_IROSRE: .equ 1 ; Output Slew Rate Control Enable for IRO pin SOPT4_FBAD12DSE: .equ 2 ; Drive Strength Control Enable for pin where address wire 12 of ?ex bus locate SOPT4_FBAD12SRE: .equ 3 ; Output Slew Rate Control Enable for pin where address wire 12 of ?ex bus locate SOPT4_FBAD12PUE: .equ 4 ; Pull-Up Enable for pin where address wire 12 of ?ex bus locate SOPT4_FBAD12FE: .equ 5 ; Input Filter Enable for pin where address wire 12 of ?ex bus locate SOPT4_FBALEEN: .equ 6 ; Mini-FlexBus Address Latch Enable bit ; bit position masks mSOPT4_IRODSE: .equ %00000001 mSOPT4_IROSRE: .equ %00000010 mSOPT4_FBAD12DSE: .equ %00000100 mSOPT4_FBAD12SRE: .equ %00001000 mSOPT4_FBAD12PUE: .equ %00010000 mSOPT4_FBAD12FE: .equ %00100000 mSOPT4_FBALEEN: .equ %01000000 ;*** SOPT5 - System Options Register 5; 0xFFFF980D *** SOPT5: .equ $FFFF980D ;*** SOPT5 - System Options Register 5; 0xFFFF980D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SOPT5_PMC_LVD_TRIM0: .equ 0 ; PMC LVD TRIM, bit 0 SOPT5_PMC_LVD_TRIM1: .equ 1 ; PMC LVD TRIM, bit 1 SOPT5_PMC_LVD_TRIM2: .equ 2 ; PMC LVD TRIM, bit 2 SOPT5_PMC_LVD_TRIM3: .equ 3 ; PMC LVD TRIM, bit 3 SOPT5_PMC_LVD_TRIM4: .equ 4 ; PMC LVD TRIM, bit 4 ; bit position masks mSOPT5_PMC_LVD_TRIM0: .equ %00000001 mSOPT5_PMC_LVD_TRIM1: .equ %00000010 mSOPT5_PMC_LVD_TRIM2: .equ %00000100 mSOPT5_PMC_LVD_TRIM3: .equ %00001000 mSOPT5_PMC_LVD_TRIM4: .equ %00010000 ;*** SIMIPS - SIM Internal Peripheral Select Register; 0xFFFF980E *** SIMIPS: .equ $FFFF980E ;*** SIMIPS - SIM Internal Peripheral Select Register; 0xFFFF980E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SIMIPS_MODTX1: .equ 0 ; Modulate TX1 SIMIPS_MTBASE10: .equ 2 ; SCI1 TX Modulation Time Base Select, bit 0 SIMIPS_MTBASE11: .equ 3 ; SCI1 TX Modulation Time Base Select, bit 1 SIMIPS_RX1IN: .equ 6 ; SCI1 RX Input Pin Select SIMIPS_ADCTRS: .equ 7 ; ADC HWTRG Select ; bit position masks mSIMIPS_MODTX1: .equ %00000001 mSIMIPS_MTBASE10: .equ %00000100 mSIMIPS_MTBASE11: .equ %00001000 mSIMIPS_RX1IN: .equ %01000000 mSIMIPS_ADCTRS: .equ %10000000 ;*** SIGNATURE - SIGNATURE Register; 0xFFFF980F *** SIGNATURE: .equ $FFFF980F ;*** SIGNATURE - SIGNATURE Register; 0xFFFF980F *** ;*** CCSCTRL - Clock Check & Select Control; 0xFFFF9810 *** CCSCTRL: .equ $FFFF9810 ;*** CCSCTRL - Clock Check & Select Control; 0xFFFF9810 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET CCSCTRL_SEL: .equ 0 ; External Clock Select CCSCTRL_TEST: .equ 1 ; TEST CCSCTRL_EN: .equ 2 ; Enable clock for CCS CCSCTRL_EREFS1: .equ 3 ; External Reference Select CCSCTRL_OSCINIT1: .equ 4 ; Oscillator Initialization CCSCTRL_ERCLKEN1: .equ 5 ; External Clock Enable CCSCTRL_HGO1: .equ 6 ; High-Gain Oscillator Select CCSCTRL_RANGE1: .equ 7 ; Frequency Range Select ; bit position masks mCCSCTRL_SEL: .equ %00000001 mCCSCTRL_TEST: .equ %00000010 mCCSCTRL_EN: .equ %00000100 mCCSCTRL_EREFS1: .equ %00001000 mCCSCTRL_OSCINIT1: .equ %00010000 mCCSCTRL_ERCLKEN1: .equ %00100000 mCCSCTRL_HGO1: .equ %01000000 mCCSCTRL_RANGE1: .equ %10000000 ;*** CCSTMR1 - CCS XOSC1 Timer Register; 0xFFFF9811 *** CCSTMR1: .equ $FFFF9811 ;*** CCSTMR1 - CCS XOSC1 Timer Register; 0xFFFF9811 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET CCSTMR1_CNT10: .equ 0 ; CNT1, bit 0 CCSTMR1_CNT11: .equ 1 ; CNT1, bit 1 CCSTMR1_CNT12: .equ 2 ; CNT1, bit 2 CCSTMR1_CNT13: .equ 3 ; CNT1, bit 3 CCSTMR1_CNT14: .equ 4 ; CNT1, bit 4 CCSTMR1_CNT15: .equ 5 ; CNT1, bit 5 CCSTMR1_CNT16: .equ 6 ; CNT1, bit 6 CCSTMR1_CNT17: .equ 7 ; CNT1, bit 7 ; bit position masks mCCSTMR1_CNT10: .equ %00000001 mCCSTMR1_CNT11: .equ %00000010 mCCSTMR1_CNT12: .equ %00000100 mCCSTMR1_CNT13: .equ %00001000 mCCSTMR1_CNT14: .equ %00010000 mCCSTMR1_CNT15: .equ %00100000 mCCSTMR1_CNT16: .equ %01000000 mCCSTMR1_CNT17: .equ %10000000 ;*** CCSTMR2 - CCS XOSC2 Timer Register; 0xFFFF9812 *** CCSTMR2: .equ $FFFF9812 ;*** CCSTMR2 - CCS XOSC2 Timer Register; 0xFFFF9812 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET CCSTMR2_CNT20: .equ 0 ; CNT2, bit 0 CCSTMR2_CNT21: .equ 1 ; CNT2, bit 1 CCSTMR2_CNT22: .equ 2 ; CNT2, bit 2 CCSTMR2_CNT23: .equ 3 ; CNT2, bit 3 CCSTMR2_CNT24: .equ 4 ; CNT2, bit 4 CCSTMR2_CNT25: .equ 5 ; CNT2, bit 5 CCSTMR2_CNT26: .equ 6 ; CNT2, bit 6 CCSTMR2_CNT27: .equ 7 ; CNT2, bit 7 ; bit position masks mCCSTMR2_CNT20: .equ %00000001 mCCSTMR2_CNT21: .equ %00000010 mCCSTMR2_CNT22: .equ %00000100 mCCSTMR2_CNT23: .equ %00001000 mCCSTMR2_CNT24: .equ %00010000 mCCSTMR2_CNT25: .equ %00100000 mCCSTMR2_CNT26: .equ %01000000 mCCSTMR2_CNT27: .equ %10000000 ;*** CCSTMRIR - CCS Internal Reference Clock Timer Register; 0xFFFF9813 *** CCSTMRIR: .equ $FFFF9813 ;*** CCSTMRIR - CCS Internal Reference Clock Timer Register; 0xFFFF9813 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET CCSTMRIR_CNTIR0: .equ 0 ; CNTIR, bit 0 CCSTMRIR_CNTIR1: .equ 1 ; CNTIR, bit 1 CCSTMRIR_CNTIR2: .equ 2 ; CNTIR, bit 2 CCSTMRIR_CNTIR3: .equ 3 ; CNTIR, bit 3 CCSTMRIR_CNTIR4: .equ 4 ; CNTIR, bit 4 CCSTMRIR_CNTIR5: .equ 5 ; CNTIR, bit 5 CCSTMRIR_CNTIR6: .equ 6 ; CNTIR, bit 6 CCSTMRIR_CNTIR7: .equ 7 ; CNTIR, bit 7 ; bit position masks mCCSTMRIR_CNTIR0: .equ %00000001 mCCSTMRIR_CNTIR1: .equ %00000010 mCCSTMRIR_CNTIR2: .equ %00000100 mCCSTMRIR_CNTIR3: .equ %00001000 mCCSTMRIR_CNTIR4: .equ %00010000 mCCSTMRIR_CNTIR5: .equ %00100000 mCCSTMRIR_CNTIR6: .equ %01000000 mCCSTMRIR_CNTIR7: .equ %10000000 ;*** FPROTD - Flash Protection Disable Register; 0xFFFF9814 *** FPROTD: .equ $FFFF9814 ;*** FPROTD - Flash Protection Disable Register; 0xFFFF9814 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FPROTD_FPDIS: .equ 0 ; Disable Flash protection ; bit position masks mFPROTD_FPDIS: .equ %00000001 ;*** MFBPC1 - Mini-FlexBus Pin Control 1; 0xFFFF9815 *** MFBPC1: .equ $FFFF9815 ;*** MFBPC1 - Mini-FlexBus Pin Control 1; 0xFFFF9815 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET MFBPC1_MFBPEN_AD0: .equ 0 ; MiniFlex bus pin control for FB_AD0 MFBPC1_MFBPEN_AD1: .equ 1 ; MiniFlex bus pin control for FB_AD1 MFBPC1_MFBPEN_AD2: .equ 2 ; MiniFlex bus pin control for FB_AD2 MFBPC1_MFBPEN_AD3: .equ 3 ; MiniFlex bus pin control for FB_AD3 MFBPC1_MFBPEN_AD4: .equ 4 ; MiniFlex bus pin control for FB_AD4 MFBPC1_MFBPEN_AD5: .equ 5 ; MiniFlex bus pin control for FB_AD5 MFBPC1_MFBPEN_AD6: .equ 6 ; MiniFlex bus pin control for FB_AD6 MFBPC1_MFBPEN_AD7: .equ 7 ; MiniFlex bus pin control for FB_AD7 ; bit position masks mMFBPC1_MFBPEN_AD0: .equ %00000001 mMFBPC1_MFBPEN_AD1: .equ %00000010 mMFBPC1_MFBPEN_AD2: .equ %00000100 mMFBPC1_MFBPEN_AD3: .equ %00001000 mMFBPC1_MFBPEN_AD4: .equ %00010000 mMFBPC1_MFBPEN_AD5: .equ %00100000 mMFBPC1_MFBPEN_AD6: .equ %01000000 mMFBPC1_MFBPEN_AD7: .equ %10000000 ;*** MFBPC2 - Mini-FlexBus Pin Control 2; 0xFFFF9816 *** MFBPC2: .equ $FFFF9816 ;*** MFBPC2 - Mini-FlexBus Pin Control 2; 0xFFFF9816 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET MFBPC2_MFBPEN_AD8: .equ 0 ; MiniFlex bus pin control for FB_AD8 MFBPC2_MFBPEN_AD9: .equ 1 ; MiniFlex bus pin control for FB_AD9 MFBPC2_MFBPEN_AD10: .equ 2 ; MiniFlex bus pin control for FB_AD10 MFBPC2_MFBPEN_AD11: .equ 3 ; MiniFlex bus pin control for FB_AD11 MFBPC2_MFBPEN_AD12: .equ 4 ; MiniFlex bus pin control for FB_AD12 MFBPC2_MFBPEN_AD13: .equ 5 ; MiniFlex bus pin control for FB_AD13 MFBPC2_MFBPEN_AD14: .equ 6 ; MiniFlex bus pin control for FB_AD14 MFBPC2_MFBPEN_AD15: .equ 7 ; MiniFlex bus pin control for FB_AD15 ; bit position masks mMFBPC2_MFBPEN_AD8: .equ %00000001 mMFBPC2_MFBPEN_AD9: .equ %00000010 mMFBPC2_MFBPEN_AD10: .equ %00000100 mMFBPC2_MFBPEN_AD11: .equ %00001000 mMFBPC2_MFBPEN_AD12: .equ %00010000 mMFBPC2_MFBPEN_AD13: .equ %00100000 mMFBPC2_MFBPEN_AD14: .equ %01000000 mMFBPC2_MFBPEN_AD15: .equ %10000000 ;*** MFBPC3 - Mini-FlexBus Pin Control 3; 0xFFFF9817 *** MFBPC3: .equ $FFFF9817 ;*** MFBPC3 - Mini-FlexBus Pin Control 3; 0xFFFF9817 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET MFBPC3_MFBPEN_AD16: .equ 0 ; MiniFlex bus pin control for FB_AD16 MFBPC3_MFBPEN_AD17: .equ 1 ; MiniFlex bus pin control for FB_AD17 MFBPC3_MFBPEN_AD18: .equ 2 ; MiniFlex bus pin control for FB_AD18 MFBPC3_MFBPEN_AD19: .equ 3 ; MiniFlex bus pin control for FB_AD19 MFBPC3_MFBPEN_D0: .equ 4 ; MiniFlex bus pin control for FB_D0 MFBPC3_MFBPEN_D1: .equ 5 ; MiniFlex bus pin control for FB_D1 MFBPC3_MFBPEN_D2: .equ 6 ; MiniFlex bus pin control for FB_D2 MFBPC3_MFBPEN_D3: .equ 7 ; MiniFlex bus pin control for FB_D3 ; bit position masks mMFBPC3_MFBPEN_AD16: .equ %00000001 mMFBPC3_MFBPEN_AD17: .equ %00000010 mMFBPC3_MFBPEN_AD18: .equ %00000100 mMFBPC3_MFBPEN_AD19: .equ %00001000 mMFBPC3_MFBPEN_D0: .equ %00010000 mMFBPC3_MFBPEN_D1: .equ %00100000 mMFBPC3_MFBPEN_D2: .equ %01000000 mMFBPC3_MFBPEN_D3: .equ %10000000 ;*** MFBPC4 - Mini-FlexBus Pin Control 4; 0xFFFF9818 *** MFBPC4: .equ $FFFF9818 ;*** MFBPC4 - Mini-FlexBus Pin Control 4; 0xFFFF9818 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET MFBPC4_MFBPEN_D4: .equ 0 ; MiniFlex bus pin control for FB_D4 MFBPC4_MFBPEN_D5: .equ 1 ; MiniFlex bus pin control for FB_D5 MFBPC4_MFBPEN_D6: .equ 2 ; MiniFlex bus pin control for FB_D6 MFBPC4_MFBPEN_D7: .equ 3 ; MiniFlex bus pin control for FB_D7 MFBPC4_EN_RW: .equ 4 ; MiniFlex bus pin control for FB_RW_b MFBPC4_EN_OE: .equ 5 ; MiniFlex bus pin control for FB_OE_b MFBPC4_EN_CS0: .equ 6 ; MiniFlex bus pin control for FB_CS0 MFBPC4_EN_CS1: .equ 7 ; MiniFlex bus pin control for FB_CS1/FB_ALE ; bit position masks mMFBPC4_MFBPEN_D4: .equ %00000001 mMFBPC4_MFBPEN_D5: .equ %00000010 mMFBPC4_MFBPEN_D6: .equ %00000100 mMFBPC4_MFBPEN_D7: .equ %00001000 mMFBPC4_EN_RW: .equ %00010000 mMFBPC4_EN_OE: .equ %00100000 mMFBPC4_EN_CS0: .equ %01000000 mMFBPC4_EN_CS1: .equ %10000000 ;*** SIMCO - SIM Clock Set and Select Register; 0xFFFF9819 *** SIMCO: .equ $FFFF9819 ;*** SIMCO - SIM Clock Set and Select Register; 0xFFFF9819 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SIMCO_CS0: .equ 0 ; CLKOUT Select, bit 0 SIMCO_CS1: .equ 1 ; CLKOUT Select, bit 1 SIMCO_CS2: .equ 2 ; CLKOUT Select, bit 2 ; bit position masks mSIMCO_CS0: .equ %00000001 mSIMCO_CS1: .equ %00000010 mSIMCO_CS2: .equ %00000100 ;*** SPMSC1 - System Power Management Status and Control 1 Register; 0xFFFF981C *** SPMSC1: .equ $FFFF981C ;*** SPMSC1 - System Power Management Status and Control 1 Register; 0xFFFF981C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPMSC1_BGBE: .equ 0 ; Bandgap Buffer Enable SPMSC1_LVDE: .equ 2 ; Low-Voltage Detect Enable SPMSC1_LVDSE: .equ 3 ; Low-Voltage Detect Stop Enable SPMSC1_LVDRE: .equ 4 ; Low-Voltage Detect Reset Enable SPMSC1_LVDIE: .equ 5 ; Low-Voltage Detect Interrupt Enable SPMSC1_LVDACK: .equ 6 ; Low-Voltage Detect Acknowledge SPMSC1_LVDF: .equ 7 ; Low-Voltage Detect Flag ; bit position masks mSPMSC1_BGBE: .equ %00000001 mSPMSC1_LVDE: .equ %00000100 mSPMSC1_LVDSE: .equ %00001000 mSPMSC1_LVDRE: .equ %00010000 mSPMSC1_LVDIE: .equ %00100000 mSPMSC1_LVDACK: .equ %01000000 mSPMSC1_LVDF: .equ %10000000 ;*** SPMSC2 - System Power Management Status and Control 2 Register; 0xFFFF981D *** SPMSC2: .equ $FFFF981D ;*** SPMSC2 - System Power Management Status and Control 2 Register; 0xFFFF981D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPMSC2_PPDC: .equ 0 ; Partial Power Down Control SPMSC2_PPDE: .equ 1 ; Partial Power-Down Enable SPMSC2_PPDACK: .equ 2 ; Partial Power Down Acknowledge SPMSC2_PPDF: .equ 3 ; Partial Power Down Flag SPMSC2_LPWUI: .equ 5 ; Low Power Wake Up on Interrupt SPMSC2_LPRS: .equ 6 ; Low Power Regulator Status SPMSC2_LPR: .equ 7 ; Low Power Regulator Control ; bit position masks mSPMSC2_PPDC: .equ %00000001 mSPMSC2_PPDE: .equ %00000010 mSPMSC2_PPDACK: .equ %00000100 mSPMSC2_PPDF: .equ %00001000 mSPMSC2_LPWUI: .equ %00100000 mSPMSC2_LPRS: .equ %01000000 mSPMSC2_LPR: .equ %10000000 ;*** SPMSC3 - System Power Management Status and Control 3 Register; 0xFFFF981F *** SPMSC3: .equ $FFFF981F ;*** SPMSC3 - System Power Management Status and Control 3 Register; 0xFFFF981F *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPMSC3_LVWIE: .equ 3 ; Low-Voltage Warning Interrupt Enable SPMSC3_LVWV: .equ 4 ; Low-Voltage Warning Voltage Select SPMSC3_LVDV: .equ 5 ; Low-Voltage Detect Voltage Select SPMSC3_LVWACK: .equ 6 ; Low-Voltage Warning Acknowledge SPMSC3_LVWF: .equ 7 ; Low-Voltage Warning Flag ; bit position masks mSPMSC3_LVWIE: .equ %00001000 mSPMSC3_LVWV: .equ %00010000 mSPMSC3_LVDV: .equ %00100000 mSPMSC3_LVWACK: .equ %01000000 mSPMSC3_LVWF: .equ %10000000 ;*** PTED - Port E Data Register; 0xFFFF9830 *** PTED: .equ $FFFF9830 ;*** PTED - Port E Data Register; 0xFFFF9830 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTED_PTED0: .equ 0 ; Port E Data Register Bit 0 PTED_PTED1: .equ 1 ; Port E Data Register Bit 1 PTED_PTED2: .equ 2 ; Port E Data Register Bit 2 PTED_PTED3: .equ 3 ; Port E Data Register Bit 3 PTED_PTED4: .equ 4 ; Port E Data Register Bit 4 PTED_PTED5: .equ 5 ; Port E Data Register Bit 5 PTED_PTED6: .equ 6 ; Port E Data Register Bit 6 PTED_PTED7: .equ 7 ; Port E Data Register Bit 7 ; bit position masks mPTED_PTED0: .equ %00000001 mPTED_PTED1: .equ %00000010 mPTED_PTED2: .equ %00000100 mPTED_PTED3: .equ %00001000 mPTED_PTED4: .equ %00010000 mPTED_PTED5: .equ %00100000 mPTED_PTED6: .equ %01000000 mPTED_PTED7: .equ %10000000 ;*** PTEDD - Port E Data Direction Register; 0xFFFF9831 *** PTEDD: .equ $FFFF9831 ;*** PTEDD - Port E Data Direction Register; 0xFFFF9831 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTEDD_PTEDD0: .equ 0 ; Data Direction for Port E Bit 0 PTEDD_PTEDD1: .equ 1 ; Data Direction for Port E Bit 1 PTEDD_PTEDD2: .equ 2 ; Data Direction for Port E Bit 2 PTEDD_PTEDD3: .equ 3 ; Data Direction for Port E Bit 3 PTEDD_PTEDD5: .equ 5 ; Data Direction for Port E Bit 5 PTEDD_PTEDD6: .equ 6 ; Data Direction for Port E Bit 6 PTEDD_PTEDD7: .equ 7 ; Data Direction for Port E Bit 7 ; bit position masks mPTEDD_PTEDD0: .equ %00000001 mPTEDD_PTEDD1: .equ %00000010 mPTEDD_PTEDD2: .equ %00000100 mPTEDD_PTEDD3: .equ %00001000 mPTEDD_PTEDD5: .equ %00100000 mPTEDD_PTEDD6: .equ %01000000 mPTEDD_PTEDD7: .equ %10000000 ;*** PTFD - Port F Data Register; 0xFFFF9832 *** PTFD: .equ $FFFF9832 ;*** PTFD - Port F Data Register; 0xFFFF9832 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTFD_PTFD0: .equ 0 ; Port F Data Register Bit 0 PTFD_PTFD1: .equ 1 ; Port F Data Register Bit 1 PTFD_PTFD2: .equ 2 ; Port F Data Register Bit 2 PTFD_PTFD3: .equ 3 ; Port F Data Register Bit 3 PTFD_PTFD4: .equ 4 ; Port F Data Register Bit 4 PTFD_PTFD5: .equ 5 ; Port F Data Register Bit 5 PTFD_PTFD6: .equ 6 ; Port F Data Register Bit 6 PTFD_PTFD7: .equ 7 ; Port F Data Register Bit 7 ; bit position masks mPTFD_PTFD0: .equ %00000001 mPTFD_PTFD1: .equ %00000010 mPTFD_PTFD2: .equ %00000100 mPTFD_PTFD3: .equ %00001000 mPTFD_PTFD4: .equ %00010000 mPTFD_PTFD5: .equ %00100000 mPTFD_PTFD6: .equ %01000000 mPTFD_PTFD7: .equ %10000000 ;*** PTFDD - Port F Data Direction Register; 0xFFFF9833 *** PTFDD: .equ $FFFF9833 ;*** PTFDD - Port F Data Direction Register; 0xFFFF9833 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTFDD_PTFDD0: .equ 0 ; Data Direction for Port F Bit 0 PTFDD_PTFDD1: .equ 1 ; Data Direction for Port F Bit 1 PTFDD_PTFDD2: .equ 2 ; Data Direction for Port F Bit 2 PTFDD_PTFDD3: .equ 3 ; Data Direction for Port F Bit 3 PTFDD_PTFDD4: .equ 4 ; Data Direction for Port F Bit 4 PTFDD_PTFDD5: .equ 5 ; Data Direction for Port F Bit 5 PTFDD_PTFDD6: .equ 6 ; Data Direction for Port F Bit 6 PTFDD_PTFDD7: .equ 7 ; Data Direction for Port F Bit 7 ; bit position masks mPTFDD_PTFDD0: .equ %00000001 mPTFDD_PTFDD1: .equ %00000010 mPTFDD_PTFDD2: .equ %00000100 mPTFDD_PTFDD3: .equ %00001000 mPTFDD_PTFDD4: .equ %00010000 mPTFDD_PTFDD5: .equ %00100000 mPTFDD_PTFDD6: .equ %01000000 mPTFDD_PTFDD7: .equ %10000000 ;*** SCI2BD - SCI2 Baud Rate Register; 0xFFFF9838 *** SCI2BD: .equ $FFFF9838 ;*** SCI2BD - SCI2 Baud Rate Register; 0xFFFF9838 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2BD_SBR0: .equ 0 ; Baud Rate Modulo Divisor Bit 0 SCI2BD_SBR1: .equ 1 ; Baud Rate Modulo Divisor Bit 1 SCI2BD_SBR2: .equ 2 ; Baud Rate Modulo Divisor Bit 2 SCI2BD_SBR3: .equ 3 ; Baud Rate Modulo Divisor Bit 3 SCI2BD_SBR4: .equ 4 ; Baud Rate Modulo Divisor Bit 4 SCI2BD_SBR5: .equ 5 ; Baud Rate Modulo Divisor Bit 5 SCI2BD_SBR6: .equ 6 ; Baud Rate Modulo Divisor Bit 6 SCI2BD_SBR7: .equ 7 ; Baud Rate Modulo Divisor Bit 7 SCI2BD_SBR8: .equ 8 ; Baud Rate Modulo Divisor Bit 8 SCI2BD_SBR9: .equ 9 ; Baud Rate Modulo Divisor Bit 9 SCI2BD_SBR10: .equ 10 ; Baud Rate Modulo Divisor Bit 10 SCI2BD_SBR11: .equ 11 ; Baud Rate Modulo Divisor Bit 11 SCI2BD_SBR12: .equ 12 ; Baud Rate Modulo Divisor Bit 12 SCI2BD_RXEDGIE: .equ 14 ; RxD Input Active Edge Interrupt Enable (for RXEDGIF) SCI2BD_LBKDIE: .equ 15 ; LIN Break Detect Interrupt Enable (for LBKDIF) ; bit position masks mSCI2BD_SBR0: .equ %00000001 mSCI2BD_SBR1: .equ %00000010 mSCI2BD_SBR2: .equ %00000100 mSCI2BD_SBR3: .equ %00001000 mSCI2BD_SBR4: .equ %00010000 mSCI2BD_SBR5: .equ %00100000 mSCI2BD_SBR6: .equ %01000000 mSCI2BD_SBR7: .equ %10000000 mSCI2BD_SBR8: .equ %100000000 mSCI2BD_SBR9: .equ %1000000000 mSCI2BD_SBR10: .equ %10000000000 mSCI2BD_SBR11: .equ %100000000000 mSCI2BD_SBR12: .equ %1000000000000 mSCI2BD_RXEDGIE: .equ %100000000000000 mSCI2BD_LBKDIE: .equ %1000000000000000 ;*** SCI2BDH - SCI2 Baud Rate Register High; 0xFFFF9838 *** SCI2BDH: .equ $FFFF9838 ;*** SCI2BDH - SCI2 Baud Rate Register High; 0xFFFF9838 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2BDH_SBR8: .equ 0 ; Baud Rate Modulo Divisor Bit 8 SCI2BDH_SBR9: .equ 1 ; Baud Rate Modulo Divisor Bit 9 SCI2BDH_SBR10: .equ 2 ; Baud Rate Modulo Divisor Bit 10 SCI2BDH_SBR11: .equ 3 ; Baud Rate Modulo Divisor Bit 11 SCI2BDH_SBR12: .equ 4 ; Baud Rate Modulo Divisor Bit 12 SCI2BDH_RXEDGIE: .equ 6 ; RxD Input Active Edge Interrupt Enable (for RXEDGIF) SCI2BDH_LBKDIE: .equ 7 ; LIN Break Detect Interrupt Enable (for LBKDIF) ; bit position masks mSCI2BDH_SBR8: .equ %00000001 mSCI2BDH_SBR9: .equ %00000010 mSCI2BDH_SBR10: .equ %00000100 mSCI2BDH_SBR11: .equ %00001000 mSCI2BDH_SBR12: .equ %00010000 mSCI2BDH_RXEDGIE: .equ %01000000 mSCI2BDH_LBKDIE: .equ %10000000 ;*** SCI2BDL - SCI2 Baud Rate Register Low; 0xFFFF9839 *** SCI2BDL: .equ $FFFF9839 ;*** SCI2BDL - SCI2 Baud Rate Register Low; 0xFFFF9839 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2BDL_SBR0: .equ 0 ; Baud Rate Modulo Divisor Bit 0 SCI2BDL_SBR1: .equ 1 ; Baud Rate Modulo Divisor Bit 1 SCI2BDL_SBR2: .equ 2 ; Baud Rate Modulo Divisor Bit 2 SCI2BDL_SBR3: .equ 3 ; Baud Rate Modulo Divisor Bit 3 SCI2BDL_SBR4: .equ 4 ; Baud Rate Modulo Divisor Bit 4 SCI2BDL_SBR5: .equ 5 ; Baud Rate Modulo Divisor Bit 5 SCI2BDL_SBR6: .equ 6 ; Baud Rate Modulo Divisor Bit 6 SCI2BDL_SBR7: .equ 7 ; Baud Rate Modulo Divisor Bit 7 ; bit position masks mSCI2BDL_SBR0: .equ %00000001 mSCI2BDL_SBR1: .equ %00000010 mSCI2BDL_SBR2: .equ %00000100 mSCI2BDL_SBR3: .equ %00001000 mSCI2BDL_SBR4: .equ %00010000 mSCI2BDL_SBR5: .equ %00100000 mSCI2BDL_SBR6: .equ %01000000 mSCI2BDL_SBR7: .equ %10000000 ;*** SCI2C1 - SCI2 Control Register 1; 0xFFFF983A *** SCI2C1: .equ $FFFF983A ;*** SCI2C1 - SCI2 Control Register 1; 0xFFFF983A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2C1_PT: .equ 0 ; Parity Type SCI2C1_PE: .equ 1 ; Parity Enable SCI2C1_ILT: .equ 2 ; Idle Line Type Select SCI2C1_WAKE: .equ 3 ; Receiver Wakeup Method Select SCI2C1_M: .equ 4 ; 9-Bit or 8-Bit Mode Select SCI2C1_RSRC: .equ 5 ; Receiver Source Select SCI2C1_SCISWAI: .equ 6 ; SCI Stops in Wait Mode SCI2C1_LOOPS: .equ 7 ; Loop Mode Select ; bit position masks mSCI2C1_PT: .equ %00000001 mSCI2C1_PE: .equ %00000010 mSCI2C1_ILT: .equ %00000100 mSCI2C1_WAKE: .equ %00001000 mSCI2C1_M: .equ %00010000 mSCI2C1_RSRC: .equ %00100000 mSCI2C1_SCISWAI: .equ %01000000 mSCI2C1_LOOPS: .equ %10000000 ;*** SCI2C2 - SCI2 Control Register 2; 0xFFFF983B *** SCI2C2: .equ $FFFF983B ;*** SCI2C2 - SCI2 Control Register 2; 0xFFFF983B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2C2_SBK: .equ 0 ; Send Break SCI2C2_RWU: .equ 1 ; Receiver Wakeup Control SCI2C2_RE: .equ 2 ; Receiver Enable SCI2C2_TE: .equ 3 ; Transmitter Enable SCI2C2_ILIE: .equ 4 ; Idle Line Interrupt Enable (for IDLE) SCI2C2_RIE: .equ 5 ; Receiver Interrupt Enable (for RDRF) SCI2C2_TCIE: .equ 6 ; Transmission Complete Interrupt Enable (for TC) SCI2C2_TIE: .equ 7 ; Transmit Interrupt Enable (for TDRE) ; bit position masks mSCI2C2_SBK: .equ %00000001 mSCI2C2_RWU: .equ %00000010 mSCI2C2_RE: .equ %00000100 mSCI2C2_TE: .equ %00001000 mSCI2C2_ILIE: .equ %00010000 mSCI2C2_RIE: .equ %00100000 mSCI2C2_TCIE: .equ %01000000 mSCI2C2_TIE: .equ %10000000 ;*** SCI2S1 - SCI2 Status Register 1; 0xFFFF983C *** SCI2S1: .equ $FFFF983C ;*** SCI2S1 - SCI2 Status Register 1; 0xFFFF983C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2S1_PF: .equ 0 ; Parity Error Flag SCI2S1_FE: .equ 1 ; Framing Error Flag SCI2S1_NF: .equ 2 ; Noise Flag SCI2S1_OR: .equ 3 ; Receiver Overrun Flag SCI2S1_IDLE: .equ 4 ; Idle Line Flag SCI2S1_RDRF: .equ 5 ; Receive Data Register Full Flag SCI2S1_TC: .equ 6 ; Transmission Complete Flag SCI2S1_TDRE: .equ 7 ; Transmit Data Register Empty Flag ; bit position masks mSCI2S1_PF: .equ %00000001 mSCI2S1_FE: .equ %00000010 mSCI2S1_NF: .equ %00000100 mSCI2S1_OR: .equ %00001000 mSCI2S1_IDLE: .equ %00010000 mSCI2S1_RDRF: .equ %00100000 mSCI2S1_TC: .equ %01000000 mSCI2S1_TDRE: .equ %10000000 ;*** SCI2S2 - SCI2 Status Register 2; 0xFFFF983D *** SCI2S2: .equ $FFFF983D ;*** SCI2S2 - SCI2 Status Register 2; 0xFFFF983D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2S2_RAF: .equ 0 ; Receiver Active Flag SCI2S2_LBKDE: .equ 1 ; LIN Break Detection Enable SCI2S2_BRK13: .equ 2 ; Break Character Generation Length SCI2S2_RWUID: .equ 3 ; Receive Wake Up Idle Detect SCI2S2_RXINV: .equ 4 ; Receive Data Inversion SCI2S2_RXEDGIF: .equ 6 ; RxD Pin Active Edge Interrupt Flag SCI2S2_LBKDIF: .equ 7 ; LIN Break Detect Interrupt Flag ; bit position masks mSCI2S2_RAF: .equ %00000001 mSCI2S2_LBKDE: .equ %00000010 mSCI2S2_BRK13: .equ %00000100 mSCI2S2_RWUID: .equ %00001000 mSCI2S2_RXINV: .equ %00010000 mSCI2S2_RXEDGIF: .equ %01000000 mSCI2S2_LBKDIF: .equ %10000000 ;*** SCI2C3 - SCI2 Control Register 3; 0xFFFF983E *** SCI2C3: .equ $FFFF983E ;*** SCI2C3 - SCI2 Control Register 3; 0xFFFF983E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2C3_PEIE: .equ 0 ; Parity Error Interrupt Enable SCI2C3_FEIE: .equ 1 ; Framing Error Interrupt Enable SCI2C3_NEIE: .equ 2 ; Noise Error Interrupt Enable SCI2C3_ORIE: .equ 3 ; Overrun Interrupt Enable SCI2C3_TXINV: .equ 4 ; Transmit Data Inversion SCI2C3_TXDIR: .equ 5 ; TxD Pin Direction in Single-Wire Mode SCI2C3_T8: .equ 6 ; Ninth Data Bit for Transmitter SCI2C3_R8: .equ 7 ; Ninth Data Bit for Receiver ; bit position masks mSCI2C3_PEIE: .equ %00000001 mSCI2C3_FEIE: .equ %00000010 mSCI2C3_NEIE: .equ %00000100 mSCI2C3_ORIE: .equ %00001000 mSCI2C3_TXINV: .equ %00010000 mSCI2C3_TXDIR: .equ %00100000 mSCI2C3_T8: .equ %01000000 mSCI2C3_R8: .equ %10000000 ;*** SCI2D - SCI2 Data Register; 0xFFFF983F *** SCI2D: .equ $FFFF983F ;*** SCI2D - SCI2 Data Register; 0xFFFF983F *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2D_R0_T0: .equ 0 ; Receive/Transmit Data Bit 0 SCI2D_R1_T1: .equ 1 ; Receive/Transmit Data Bit 1 SCI2D_R2_T2: .equ 2 ; Receive/Transmit Data Bit 2 SCI2D_R3_T3: .equ 3 ; Receive/Transmit Data Bit 3 SCI2D_R4_T4: .equ 4 ; Receive/Transmit Data Bit 4 SCI2D_R5_T5: .equ 5 ; Receive/Transmit Data Bit 5 SCI2D_R6_T6: .equ 6 ; Receive/Transmit Data Bit 6 SCI2D_R7_T7: .equ 7 ; Receive/Transmit Data Bit 7 ; bit position masks mSCI2D_R0_T0: .equ %00000001 mSCI2D_R1_T1: .equ %00000010 mSCI2D_R2_T2: .equ %00000100 mSCI2D_R3_T3: .equ %00001000 mSCI2D_R4_T4: .equ %00010000 mSCI2D_R5_T5: .equ %00100000 mSCI2D_R6_T6: .equ %01000000 mSCI2D_R7_T7: .equ %10000000 ;*** SPI2C1 - SPI2 Control Register 1; 0xFFFF9840 *** SPI2C1: .equ $FFFF9840 ;*** SPI2C1 - SPI2 Control Register 1; 0xFFFF9840 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI2C1_LSBFE: .equ 0 ; LSB First (Shifter Direction) SPI2C1_SSOE: .equ 1 ; Slave Select Output Enable SPI2C1_CPHA: .equ 2 ; Clock Phase SPI2C1_CPOL: .equ 3 ; Clock Polarity SPI2C1_MSTR: .equ 4 ; Master/Slave Mode Select SPI2C1_SPTIE: .equ 5 ; SPI Transmit Interrupt Enable SPI2C1_SPE: .equ 6 ; SPI System Enable SPI2C1_SPIE: .equ 7 ; SPI Interrupt Enable (for SPRF and MODF) ; bit position masks mSPI2C1_LSBFE: .equ %00000001 mSPI2C1_SSOE: .equ %00000010 mSPI2C1_CPHA: .equ %00000100 mSPI2C1_CPOL: .equ %00001000 mSPI2C1_MSTR: .equ %00010000 mSPI2C1_SPTIE: .equ %00100000 mSPI2C1_SPE: .equ %01000000 mSPI2C1_SPIE: .equ %10000000 ;*** SPI2C2 - SPI2 Control Register 2; 0xFFFF9841 *** SPI2C2: .equ $FFFF9841 ;*** SPI2C2 - SPI2 Control Register 2; 0xFFFF9841 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI2C2_SPC0: .equ 0 ; SPI Pin Control 0 SPI2C2_SPISWAI: .equ 1 ; SPI Stop in Wait Mode SPI2C2_BIDIROE: .equ 3 ; Bidirectional Mode Output Enable SPI2C2_MODFEN: .equ 4 ; Master Mode-Fault Function Enable SPI2C2_SPMIE: .equ 7 ; SPI Match Interrupt Enable ; bit position masks mSPI2C2_SPC0: .equ %00000001 mSPI2C2_SPISWAI: .equ %00000010 mSPI2C2_BIDIROE: .equ %00001000 mSPI2C2_MODFEN: .equ %00010000 mSPI2C2_SPMIE: .equ %10000000 ;*** SPI2BR - SPI2 Baud Rate Register; 0xFFFF9842 *** SPI2BR: .equ $FFFF9842 ;*** SPI2BR - SPI2 Baud Rate Register; 0xFFFF9842 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI2BR_SPR0: .equ 0 ; SPI Baud Rate Divisor Bit 0 SPI2BR_SPR1: .equ 1 ; SPI Baud Rate Divisor Bit 1 SPI2BR_SPR2: .equ 2 ; SPI Baud Rate Divisor Bit 2 SPI2BR_SPR3: .equ 3 ; SPI Baud Rate Divisor Bit 3 SPI2BR_SPPR0: .equ 4 ; SPI Baud Rate Prescale Divisor Bit 0 SPI2BR_SPPR1: .equ 5 ; SPI Baud Rate Prescale Divisor Bit 1 SPI2BR_SPPR2: .equ 6 ; SPI Baud Rate Prescale Divisor Bit 2 ; bit position masks mSPI2BR_SPR0: .equ %00000001 mSPI2BR_SPR1: .equ %00000010 mSPI2BR_SPR2: .equ %00000100 mSPI2BR_SPR3: .equ %00001000 mSPI2BR_SPPR0: .equ %00010000 mSPI2BR_SPPR1: .equ %00100000 mSPI2BR_SPPR2: .equ %01000000 ;*** SPI2S - SPI2 Status Register; 0xFFFF9843 *** SPI2S: .equ $FFFF9843 ;*** SPI2S - SPI2 Status Register; 0xFFFF9843 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI2S_MODF: .equ 4 ; Master Mode Fault Flag SPI2S_SPTEF: .equ 5 ; SPI Transmit Buffer Empty Flag SPI2S_SPMF: .equ 6 ; SPI Match Flag SPI2S_SPRF: .equ 7 ; SPI Read Buffer Full Flag ; bit position masks mSPI2S_MODF: .equ %00010000 mSPI2S_SPTEF: .equ %00100000 mSPI2S_SPMF: .equ %01000000 mSPI2S_SPRF: .equ %10000000 ;*** SPI2D - SPI2 Data Register; 0xFFFF9845 *** SPI2D: .equ $FFFF9845 ;*** SPI2D - SPI2 Data Register; 0xFFFF9845 *** ;*** SPI2M - SPI2 Match Register; 0xFFFF9847 *** SPI2M: .equ $FFFF9847 ;*** SPI2M - SPI2 Match Register; 0xFFFF9847 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI2M_Bit0: .equ 0 ; SPI Match Value Bit 0 SPI2M_Bit1: .equ 1 ; SPI Match Value Bit 1 SPI2M_Bit2: .equ 2 ; SPI Match Value Bit 2 SPI2M_Bit3: .equ 3 ; SPI Match Value Bit 3 SPI2M_Bit4: .equ 4 ; SPI Match Value Bit 4 SPI2M_Bit5: .equ 5 ; SPI Match Value Bit 5 SPI2M_Bit6: .equ 6 ; SPI Match Value Bit 6 SPI2M_Bit7: .equ 7 ; SPI Match Value Bit 7 ; bit position masks mSPI2M_Bit0: .equ %00000001 mSPI2M_Bit1: .equ %00000010 mSPI2M_Bit2: .equ %00000100 mSPI2M_Bit3: .equ %00001000 mSPI2M_Bit4: .equ %00010000 mSPI2M_Bit5: .equ %00100000 mSPI2M_Bit6: .equ %01000000 mSPI2M_Bit7: .equ %10000000 ;*** PTGD - Port G Data Register; 0xFFFF9848 *** PTGD: .equ $FFFF9848 ;*** PTGD - Port G Data Register; 0xFFFF9848 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTGD_PTGD0: .equ 0 ; Port G Data Register Bit 0 PTGD_PTGD1: .equ 1 ; Port G Data Register Bit 1 PTGD_PTGD2: .equ 2 ; Port G Data Register Bit 2 PTGD_PTGD3: .equ 3 ; Port G Data Register Bit 3 PTGD_PTGD4: .equ 4 ; Port G Data Register Bit 4 PTGD_PTGD5: .equ 5 ; Port G Data Register Bit 5 PTGD_PTGD6: .equ 6 ; Port G Data Register Bit 6 PTGD_PTGD7: .equ 7 ; Port G Data Register Bit 7 ; bit position masks mPTGD_PTGD0: .equ %00000001 mPTGD_PTGD1: .equ %00000010 mPTGD_PTGD2: .equ %00000100 mPTGD_PTGD3: .equ %00001000 mPTGD_PTGD4: .equ %00010000 mPTGD_PTGD5: .equ %00100000 mPTGD_PTGD6: .equ %01000000 mPTGD_PTGD7: .equ %10000000 ;*** PTGDD - Port G Data Direction Register; 0xFFFF9849 *** PTGDD: .equ $FFFF9849 ;*** PTGDD - Port G Data Direction Register; 0xFFFF9849 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTGDD_PTGDD0: .equ 0 ; Data Direction for Port G Bit 0 PTGDD_PTGDD1: .equ 1 ; Data Direction for Port G Bit 1 PTGDD_PTGDD2: .equ 2 ; Data Direction for Port G Bit 2 PTGDD_PTGDD3: .equ 3 ; Data Direction for Port G Bit 3 PTGDD_PTGDD4: .equ 4 ; Data Direction for Port G Bit 4 PTGDD_PTGDD5: .equ 5 ; Data Direction for Port G Bit 5 PTGDD_PTGDD6: .equ 6 ; Data Direction for Port G Bit 6 PTGDD_PTGDD7: .equ 7 ; Data Direction for Port G Bit 7 ; bit position masks mPTGDD_PTGDD0: .equ %00000001 mPTGDD_PTGDD1: .equ %00000010 mPTGDD_PTGDD2: .equ %00000100 mPTGDD_PTGDD3: .equ %00001000 mPTGDD_PTGDD4: .equ %00010000 mPTGDD_PTGDD5: .equ %00100000 mPTGDD_PTGDD6: .equ %01000000 mPTGDD_PTGDD7: .equ %10000000 ;*** PTAPE - Port A Pull Enable Register; 0xFFFF9850 *** PTAPE: .equ $FFFF9850 ;*** PTAPE - Port A Pull Enable Register; 0xFFFF9850 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTAPE_PTAPE0: .equ 0 ; Internal Pull Enable for Port A Bit 0 PTAPE_PTAPE1: .equ 1 ; Internal Pull Enable for Port A Bit 1 PTAPE_PTAPE2: .equ 2 ; Internal Pull Enable for Port A Bit 2 PTAPE_PTAPE3: .equ 3 ; Internal Pull Enable for Port A Bit 3 PTAPE_PTAPE4: .equ 4 ; Internal Pull Enable for Port A Bit 4 PTAPE_PTAPE5: .equ 5 ; Internal Pull Enable for Port A Bit 5 PTAPE_PTAPE6: .equ 6 ; Internal Pull Enable for Port A Bit 6 PTAPE_PTAPE7: .equ 7 ; Internal Pull Enable for Port A Bit 7 ; bit position masks mPTAPE_PTAPE0: .equ %00000001 mPTAPE_PTAPE1: .equ %00000010 mPTAPE_PTAPE2: .equ %00000100 mPTAPE_PTAPE3: .equ %00001000 mPTAPE_PTAPE4: .equ %00010000 mPTAPE_PTAPE5: .equ %00100000 mPTAPE_PTAPE6: .equ %01000000 mPTAPE_PTAPE7: .equ %10000000 ;*** PTASE - Port A Slew Rate Enable Register; 0xFFFF9851 *** PTASE: .equ $FFFF9851 ;*** PTASE - Port A Slew Rate Enable Register; 0xFFFF9851 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTASE_PTASE0: .equ 0 ; Output Slew Rate Enable for Port A Bit 0 PTASE_PTASE1: .equ 1 ; Output Slew Rate Enable for Port A Bit 1 PTASE_PTASE2: .equ 2 ; Output Slew Rate Enable for Port A Bit 2 PTASE_PTASE3: .equ 3 ; Output Slew Rate Enable for Port A Bit 3 PTASE_PTASE4: .equ 4 ; Output Slew Rate Enable for Port A Bit 4 PTASE_PTASE5: .equ 5 ; Output Slew Rate Enable for Port A Bit 5 PTASE_PTASE6: .equ 6 ; Output Slew Rate Enable for Port A Bit 6 PTASE_PTASE7: .equ 7 ; Output Slew Rate Enable for Port A Bit 7 ; bit position masks mPTASE_PTASE0: .equ %00000001 mPTASE_PTASE1: .equ %00000010 mPTASE_PTASE2: .equ %00000100 mPTASE_PTASE3: .equ %00001000 mPTASE_PTASE4: .equ %00010000 mPTASE_PTASE5: .equ %00100000 mPTASE_PTASE6: .equ %01000000 mPTASE_PTASE7: .equ %10000000 ;*** PTADS - Port A Drive Strength Selection Register; 0xFFFF9852 *** PTADS: .equ $FFFF9852 ;*** PTADS - Port A Drive Strength Selection Register; 0xFFFF9852 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTADS_PTADS0: .equ 0 ; Output Drive Strength Selection for Port A Bit 0 PTADS_PTADS1: .equ 1 ; Output Drive Strength Selection for Port A Bit 1 PTADS_PTADS2: .equ 2 ; Output Drive Strength Selection for Port A Bit 2 PTADS_PTADS3: .equ 3 ; Output Drive Strength Selection for Port A Bit 3 PTADS_PTADS4: .equ 4 ; Output Drive Strength Selection for Port A Bit 4 PTADS_PTADS5: .equ 5 ; Output Drive Strength Selection for Port A Bit 5 PTADS_PTADS6: .equ 6 ; Output Drive Strength Selection for Port A Bit 6 PTADS_PTADS7: .equ 7 ; Output Drive Strength Selection for Port A Bit 7 ; bit position masks mPTADS_PTADS0: .equ %00000001 mPTADS_PTADS1: .equ %00000010 mPTADS_PTADS2: .equ %00000100 mPTADS_PTADS3: .equ %00001000 mPTADS_PTADS4: .equ %00010000 mPTADS_PTADS5: .equ %00100000 mPTADS_PTADS6: .equ %01000000 mPTADS_PTADS7: .equ %10000000 ;*** PTAIFE - Port A Input Filter Enable Register; 0xFFFF9853 *** PTAIFE: .equ $FFFF9853 ;*** PTAIFE - Port A Input Filter Enable Register; 0xFFFF9853 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTAIFE_PTAIFE0: .equ 0 ; Port A Input Filter Enable Bit 0 PTAIFE_PTAIFE1: .equ 1 ; Port A Input Filter Enable Bit 1 PTAIFE_PTAIFE2: .equ 2 ; Port A Input Filter Enable Bit 2 PTAIFE_PTAIFE3: .equ 3 ; Port A Input Filter Enable Bit 3 PTAIFE_PTAIFE4: .equ 4 ; Port A Input Filter Enable Bit 4 PTAIFE_PTAIFE5: .equ 5 ; Port A Input Filter Enable Bit 5 PTAIFE_PTAIFE6: .equ 6 ; Port A Input Filter Enable Bit 6 PTAIFE_PTAIFE7: .equ 7 ; Port A Input Filter Enable Bit 7 ; bit position masks mPTAIFE_PTAIFE0: .equ %00000001 mPTAIFE_PTAIFE1: .equ %00000010 mPTAIFE_PTAIFE2: .equ %00000100 mPTAIFE_PTAIFE3: .equ %00001000 mPTAIFE_PTAIFE4: .equ %00010000 mPTAIFE_PTAIFE5: .equ %00100000 mPTAIFE_PTAIFE6: .equ %01000000 mPTAIFE_PTAIFE7: .equ %10000000 ;*** PTBPE - Port B Pull Enable Register; 0xFFFF9854 *** PTBPE: .equ $FFFF9854 ;*** PTBPE - Port B Pull Enable Register; 0xFFFF9854 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTBPE_PTBPE0: .equ 0 ; Internal Pull Enable for Port B Bit 0 PTBPE_PTBPE1: .equ 1 ; Internal Pull Enable for Port B Bit 1 PTBPE_PTBPE2: .equ 2 ; Internal Pull Enable for Port B Bit 2 PTBPE_PTBPE3: .equ 3 ; Internal Pull Enable for Port B Bit 3 PTBPE_PTBPE4: .equ 4 ; Internal Pull Enable for Port B Bit 4 PTBPE_PTBPE5: .equ 5 ; Internal Pull Enable for Port B Bit 5 PTBPE_PTBPE6: .equ 6 ; Internal Pull Enable for Port B Bit 6 PTBPE_PTBPE7: .equ 7 ; Internal Pull Enable for Port B Bit 7 ; bit position masks mPTBPE_PTBPE0: .equ %00000001 mPTBPE_PTBPE1: .equ %00000010 mPTBPE_PTBPE2: .equ %00000100 mPTBPE_PTBPE3: .equ %00001000 mPTBPE_PTBPE4: .equ %00010000 mPTBPE_PTBPE5: .equ %00100000 mPTBPE_PTBPE6: .equ %01000000 mPTBPE_PTBPE7: .equ %10000000 ;*** PTBSE - Port B Slew Rate Enable Register; 0xFFFF9855 *** PTBSE: .equ $FFFF9855 ;*** PTBSE - Port B Slew Rate Enable Register; 0xFFFF9855 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTBSE_PTBSE0: .equ 0 ; Output Slew Rate Enable for Port B Bit 0 PTBSE_PTBSE1: .equ 1 ; Output Slew Rate Enable for Port B Bit 1 PTBSE_PTBSE2: .equ 2 ; Output Slew Rate Enable for Port B Bit 2 PTBSE_PTBSE3: .equ 3 ; Output Slew Rate Enable for Port B Bit 3 PTBSE_PTBSE4: .equ 4 ; Output Slew Rate Enable for Port B Bit 4 PTBSE_PTBSE5: .equ 5 ; Output Slew Rate Enable for Port B Bit 5 PTBSE_PTBSE6: .equ 6 ; Output Slew Rate Enable for Port B Bit 6 PTBSE_PTBSE7: .equ 7 ; Output Slew Rate Enable for Port B Bit 7 ; bit position masks mPTBSE_PTBSE0: .equ %00000001 mPTBSE_PTBSE1: .equ %00000010 mPTBSE_PTBSE2: .equ %00000100 mPTBSE_PTBSE3: .equ %00001000 mPTBSE_PTBSE4: .equ %00010000 mPTBSE_PTBSE5: .equ %00100000 mPTBSE_PTBSE6: .equ %01000000 mPTBSE_PTBSE7: .equ %10000000 ;*** PTBDS - Port B Drive Strength Selection Register; 0xFFFF9856 *** PTBDS: .equ $FFFF9856 ;*** PTBDS - Port B Drive Strength Selection Register; 0xFFFF9856 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTBDS_PTBDS0: .equ 0 ; Output Drive Strength Selection for Port B Bit 0 PTBDS_PTBDS1: .equ 1 ; Output Drive Strength Selection for Port B Bit 1 PTBDS_PTBDS2: .equ 2 ; Output Drive Strength Selection for Port B Bit 2 PTBDS_PTBDS3: .equ 3 ; Output Drive Strength Selection for Port B Bit 3 PTBDS_PTBDS4: .equ 4 ; Output Drive Strength Selection for Port B Bit 4 PTBDS_PTBDS5: .equ 5 ; Output Drive Strength Selection for Port B Bit 5 PTBDS_PTBDS6: .equ 6 ; Output Drive Strength Selection for Port B Bit 6 PTBDS_PTBDS7: .equ 7 ; Output Drive Strength Selection for Port B Bit 7 ; bit position masks mPTBDS_PTBDS0: .equ %00000001 mPTBDS_PTBDS1: .equ %00000010 mPTBDS_PTBDS2: .equ %00000100 mPTBDS_PTBDS3: .equ %00001000 mPTBDS_PTBDS4: .equ %00010000 mPTBDS_PTBDS5: .equ %00100000 mPTBDS_PTBDS6: .equ %01000000 mPTBDS_PTBDS7: .equ %10000000 ;*** PTBIFE - Port B Input Filter Enable Register; 0xFFFF9857 *** PTBIFE: .equ $FFFF9857 ;*** PTBIFE - Port B Input Filter Enable Register; 0xFFFF9857 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTBIFE_PTBIFE0: .equ 0 ; Port B Input Filter Enable Bit 0 PTBIFE_PTBIFE1: .equ 1 ; Port B Input Filter Enable Bit 1 PTBIFE_PTBIFE2: .equ 2 ; Port B Input Filter Enable Bit 2 PTBIFE_PTBIFE3: .equ 3 ; Port B Input Filter Enable Bit 3 PTBIFE_PTBIFE4: .equ 4 ; Port B Input Filter Enable Bit 4 PTBIFE_PTBIFE5: .equ 5 ; Port B Input Filter Enable Bit 5 PTBIFE_PTBIFE6: .equ 6 ; Port B Input Filter Enable Bit 6 PTBIFE_PTBIFE7: .equ 7 ; Port B Input Filter Enable Bit 7 ; bit position masks mPTBIFE_PTBIFE0: .equ %00000001 mPTBIFE_PTBIFE1: .equ %00000010 mPTBIFE_PTBIFE2: .equ %00000100 mPTBIFE_PTBIFE3: .equ %00001000 mPTBIFE_PTBIFE4: .equ %00010000 mPTBIFE_PTBIFE5: .equ %00100000 mPTBIFE_PTBIFE6: .equ %01000000 mPTBIFE_PTBIFE7: .equ %10000000 ;*** PTCPE - Port C Pull Enable Register; 0xFFFF9858 *** PTCPE: .equ $FFFF9858 ;*** PTCPE - Port C Pull Enable Register; 0xFFFF9858 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTCPE_PTCPE0: .equ 0 ; Internal Pull Enable for Port C Bit 0 PTCPE_PTCPE1: .equ 1 ; Internal Pull Enable for Port C Bit 1 PTCPE_PTCPE2: .equ 2 ; Internal Pull Enable for Port C Bit 2 PTCPE_PTCPE3: .equ 3 ; Internal Pull Enable for Port C Bit 3 PTCPE_PTCPE4: .equ 4 ; Internal Pull Enable for Port C Bit 4 PTCPE_PTCPE5: .equ 5 ; Internal Pull Enable for Port C Bit 5 PTCPE_PTCPE6: .equ 6 ; Internal Pull Enable for Port C Bit 6 PTCPE_PTCPE7: .equ 7 ; Internal Pull Enable for Port C Bit 7 ; bit position masks mPTCPE_PTCPE0: .equ %00000001 mPTCPE_PTCPE1: .equ %00000010 mPTCPE_PTCPE2: .equ %00000100 mPTCPE_PTCPE3: .equ %00001000 mPTCPE_PTCPE4: .equ %00010000 mPTCPE_PTCPE5: .equ %00100000 mPTCPE_PTCPE6: .equ %01000000 mPTCPE_PTCPE7: .equ %10000000 ;*** PTCSE - Port C Slew Rate Enable Register; 0xFFFF9859 *** PTCSE: .equ $FFFF9859 ;*** PTCSE - Port C Slew Rate Enable Register; 0xFFFF9859 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTCSE_PTCSE0: .equ 0 ; Output Slew Rate Enable for Port C Bit 0 PTCSE_PTCSE1: .equ 1 ; Output Slew Rate Enable for Port C Bit 1 PTCSE_PTCSE2: .equ 2 ; Output Slew Rate Enable for Port C Bit 2 PTCSE_PTCSE3: .equ 3 ; Output Slew Rate Enable for Port C Bit 3 PTCSE_PTCSE4: .equ 4 ; Output Slew Rate Enable for Port C Bit 4 PTCSE_PTCSE5: .equ 5 ; Output Slew Rate Enable for Port C Bit 5 PTCSE_PTCSE6: .equ 6 ; Output Slew Rate Enable for Port C Bit 6 PTCSE_PTCSE7: .equ 7 ; Output Slew Rate Enable for Port C Bit 7 ; bit position masks mPTCSE_PTCSE0: .equ %00000001 mPTCSE_PTCSE1: .equ %00000010 mPTCSE_PTCSE2: .equ %00000100 mPTCSE_PTCSE3: .equ %00001000 mPTCSE_PTCSE4: .equ %00010000 mPTCSE_PTCSE5: .equ %00100000 mPTCSE_PTCSE6: .equ %01000000 mPTCSE_PTCSE7: .equ %10000000 ;*** PTCDS - Port C Drive Strength Selection Register; 0xFFFF985A *** PTCDS: .equ $FFFF985A ;*** PTCDS - Port C Drive Strength Selection Register; 0xFFFF985A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTCDS_PTCDS0: .equ 0 ; Output Drive Strength Selection for Port C Bit 0 PTCDS_PTCDS1: .equ 1 ; Output Drive Strength Selection for Port C Bit 1 PTCDS_PTCDS2: .equ 2 ; Output Drive Strength Selection for Port C Bit 2 PTCDS_PTCDS3: .equ 3 ; Output Drive Strength Selection for Port C Bit 3 PTCDS_PTCDS4: .equ 4 ; Output Drive Strength Selection for Port C Bit 4 PTCDS_PTCDS5: .equ 5 ; Output Drive Strength Selection for Port C Bit 5 PTCDS_PTCDS6: .equ 6 ; Output Drive Strength Selection for Port C Bit 6 PTCDS_PTCDS7: .equ 7 ; Output Drive Strength Selection for Port C Bit 7 ; bit position masks mPTCDS_PTCDS0: .equ %00000001 mPTCDS_PTCDS1: .equ %00000010 mPTCDS_PTCDS2: .equ %00000100 mPTCDS_PTCDS3: .equ %00001000 mPTCDS_PTCDS4: .equ %00010000 mPTCDS_PTCDS5: .equ %00100000 mPTCDS_PTCDS6: .equ %01000000 mPTCDS_PTCDS7: .equ %10000000 ;*** PTCIFE - Port C Input Filter Enable Register; 0xFFFF985B *** PTCIFE: .equ $FFFF985B ;*** PTCIFE - Port C Input Filter Enable Register; 0xFFFF985B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTCIFE_PTCIFE0: .equ 0 ; Port C Input Filter Enable Bit 0 PTCIFE_PTCIFE1: .equ 1 ; Port C Input Filter Enable Bit 1 PTCIFE_PTCIFE2: .equ 2 ; Port C Input Filter Enable Bit 2 PTCIFE_PTCIFE3: .equ 3 ; Port C Input Filter Enable Bit 3 PTCIFE_PTCIFE4: .equ 4 ; Port C Input Filter Enable Bit 4 PTCIFE_PTCIFE5: .equ 5 ; Port C Input Filter Enable Bit 5 PTCIFE_PTCIFE6: .equ 6 ; Port C Input Filter Enable Bit 6 PTCIFE_PTCIFE7: .equ 7 ; Port C Input Filter Enable Bit 7 ; bit position masks mPTCIFE_PTCIFE0: .equ %00000001 mPTCIFE_PTCIFE1: .equ %00000010 mPTCIFE_PTCIFE2: .equ %00000100 mPTCIFE_PTCIFE3: .equ %00001000 mPTCIFE_PTCIFE4: .equ %00010000 mPTCIFE_PTCIFE5: .equ %00100000 mPTCIFE_PTCIFE6: .equ %01000000 mPTCIFE_PTCIFE7: .equ %10000000 ;*** PTDPE - Port D Pull Enable Register; 0xFFFF985C *** PTDPE: .equ $FFFF985C ;*** PTDPE - Port D Pull Enable Register; 0xFFFF985C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTDPE_PTDPE0: .equ 0 ; Internal Pull Enable for Port D Bit 0 PTDPE_PTDPE1: .equ 1 ; Internal Pull Enable for Port D Bit 1 PTDPE_PTDPE2: .equ 2 ; Internal Pull Enable for Port D Bit 2 PTDPE_PTDPE3: .equ 3 ; Internal Pull Enable for Port D Bit 3 PTDPE_PTDPE4: .equ 4 ; Internal Pull Enable for Port D Bit 4 PTDPE_PTDPE5: .equ 5 ; Internal Pull Enable for Port D Bit 5 PTDPE_PTDPE6: .equ 6 ; Internal Pull Enable for Port D Bit 6 PTDPE_PTDPE7: .equ 7 ; Internal Pull Enable for Port D Bit 7 ; bit position masks mPTDPE_PTDPE0: .equ %00000001 mPTDPE_PTDPE1: .equ %00000010 mPTDPE_PTDPE2: .equ %00000100 mPTDPE_PTDPE3: .equ %00001000 mPTDPE_PTDPE4: .equ %00010000 mPTDPE_PTDPE5: .equ %00100000 mPTDPE_PTDPE6: .equ %01000000 mPTDPE_PTDPE7: .equ %10000000 ;*** PTDSE - Port D Slew Rate Enable Register; 0xFFFF985D *** PTDSE: .equ $FFFF985D ;*** PTDSE - Port D Slew Rate Enable Register; 0xFFFF985D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTDSE_PTDSE0: .equ 0 ; Output Slew Rate Enable for Port D Bit 0 PTDSE_PTDSE1: .equ 1 ; Output Slew Rate Enable for Port D Bit 1 PTDSE_PTDSE2: .equ 2 ; Output Slew Rate Enable for Port D Bit 2 PTDSE_PTDSE3: .equ 3 ; Output Slew Rate Enable for Port D Bit 3 PTDSE_PTDSE4: .equ 4 ; Output Slew Rate Enable for Port D Bit 4 PTDSE_PTDSE5: .equ 5 ; Output Slew Rate Enable for Port D Bit 5 PTDSE_PTDSE6: .equ 6 ; Output Slew Rate Enable for Port D Bit 6 PTDSE_PTDSE7: .equ 7 ; Output Slew Rate Enable for Port D Bit 7 ; bit position masks mPTDSE_PTDSE0: .equ %00000001 mPTDSE_PTDSE1: .equ %00000010 mPTDSE_PTDSE2: .equ %00000100 mPTDSE_PTDSE3: .equ %00001000 mPTDSE_PTDSE4: .equ %00010000 mPTDSE_PTDSE5: .equ %00100000 mPTDSE_PTDSE6: .equ %01000000 mPTDSE_PTDSE7: .equ %10000000 ;*** PTDDS - Port D Drive Strength Selection Register; 0xFFFF985E *** PTDDS: .equ $FFFF985E ;*** PTDDS - Port D Drive Strength Selection Register; 0xFFFF985E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTDDS_PTDDS0: .equ 0 ; Output Drive Strength Selection for Port D Bit 0 PTDDS_PTDDS1: .equ 1 ; Output Drive Strength Selection for Port D Bit 1 PTDDS_PTDDS2: .equ 2 ; Output Drive Strength Selection for Port D Bit 2 PTDDS_PTDDS3: .equ 3 ; Output Drive Strength Selection for Port D Bit 3 PTDDS_PTDDS4: .equ 4 ; Output Drive Strength Selection for Port D Bit 4 PTDDS_PTDDS5: .equ 5 ; Output Drive Strength Selection for Port D Bit 5 PTDDS_PTDDS6: .equ 6 ; Output Drive Strength Selection for Port D Bit 6 PTDDS_PTDDS7: .equ 7 ; Output Drive Strength Selection for Port D Bit 7 ; bit position masks mPTDDS_PTDDS0: .equ %00000001 mPTDDS_PTDDS1: .equ %00000010 mPTDDS_PTDDS2: .equ %00000100 mPTDDS_PTDDS3: .equ %00001000 mPTDDS_PTDDS4: .equ %00010000 mPTDDS_PTDDS5: .equ %00100000 mPTDDS_PTDDS6: .equ %01000000 mPTDDS_PTDDS7: .equ %10000000 ;*** PTDIFE - Port D Input Filter Enable Register; 0xFFFF985F *** PTDIFE: .equ $FFFF985F ;*** PTDIFE - Port D Input Filter Enable Register; 0xFFFF985F *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTDIFE_PTDIFE0: .equ 0 ; Port D Input Filter Enable Bit 0 PTDIFE_PTDIFE1: .equ 1 ; Port D Input Filter Enable Bit 1 PTDIFE_PTDIFE2: .equ 2 ; Port D Input Filter Enable Bit 2 PTDIFE_PTDIFE3: .equ 3 ; Port D Input Filter Enable Bit 3 PTDIFE_PTDIFE4: .equ 4 ; Port D Input Filter Enable Bit 4 PTDIFE_PTDIFE5: .equ 5 ; Port D Input Filter Enable Bit 5 PTDIFE_PTDIFE6: .equ 6 ; Port D Input Filter Enable Bit 6 PTDIFE_PTDIFE7: .equ 7 ; Port D Input Filter Enable Bit 7 ; bit position masks mPTDIFE_PTDIFE0: .equ %00000001 mPTDIFE_PTDIFE1: .equ %00000010 mPTDIFE_PTDIFE2: .equ %00000100 mPTDIFE_PTDIFE3: .equ %00001000 mPTDIFE_PTDIFE4: .equ %00010000 mPTDIFE_PTDIFE5: .equ %00100000 mPTDIFE_PTDIFE6: .equ %01000000 mPTDIFE_PTDIFE7: .equ %10000000 ;*** PTEPE - Port E Pull Enable Register; 0xFFFF9860 *** PTEPE: .equ $FFFF9860 ;*** PTEPE - Port E Pull Enable Register; 0xFFFF9860 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTEPE_PTEPE0: .equ 0 ; Internal Pull Enable for Port E Bit 0 PTEPE_PTEPE1: .equ 1 ; Internal Pull Enable for Port E Bit 1 PTEPE_PTEPE2: .equ 2 ; Internal Pull Enable for Port E Bit 2 PTEPE_PTEPE3: .equ 3 ; Internal Pull Enable for Port E Bit 3 PTEPE_PTEPE4: .equ 4 ; Internal Pull Enable for Port E Bit 4 PTEPE_PTEPE5: .equ 5 ; Internal Pull Enable for Port E Bit 5 PTEPE_PTEPE6: .equ 6 ; Internal Pull Enable for Port E Bit 6 PTEPE_PTEPE7: .equ 7 ; Internal Pull Enable for Port E Bit 7 ; bit position masks mPTEPE_PTEPE0: .equ %00000001 mPTEPE_PTEPE1: .equ %00000010 mPTEPE_PTEPE2: .equ %00000100 mPTEPE_PTEPE3: .equ %00001000 mPTEPE_PTEPE4: .equ %00010000 mPTEPE_PTEPE5: .equ %00100000 mPTEPE_PTEPE6: .equ %01000000 mPTEPE_PTEPE7: .equ %10000000 ;*** PTESE - Port E Slew Rate Enable Register; 0xFFFF9861 *** PTESE: .equ $FFFF9861 ;*** PTESE - Port E Slew Rate Enable Register; 0xFFFF9861 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTESE_PTESE0: .equ 0 ; Output Slew Rate Enable for Port E Bit 0 PTESE_PTESE1: .equ 1 ; Output Slew Rate Enable for Port E Bit 1 PTESE_PTESE2: .equ 2 ; Output Slew Rate Enable for Port E Bit 2 PTESE_PTESE3: .equ 3 ; Output Slew Rate Enable for Port E Bit 3 PTESE_PTESE4: .equ 4 ; Output Slew Rate Enable for Port E Bit 4 PTESE_PTESE5: .equ 5 ; Output Slew Rate Enable for Port E Bit 5 PTESE_PTESE6: .equ 6 ; Output Slew Rate Enable for Port E Bit 6 PTESE_PTESE7: .equ 7 ; Output Slew Rate Enable for Port E Bit 7 ; bit position masks mPTESE_PTESE0: .equ %00000001 mPTESE_PTESE1: .equ %00000010 mPTESE_PTESE2: .equ %00000100 mPTESE_PTESE3: .equ %00001000 mPTESE_PTESE4: .equ %00010000 mPTESE_PTESE5: .equ %00100000 mPTESE_PTESE6: .equ %01000000 mPTESE_PTESE7: .equ %10000000 ;*** PTEDS - Port E Drive Strength Selection Register; 0xFFFF9862 *** PTEDS: .equ $FFFF9862 ;*** PTEDS - Port E Drive Strength Selection Register; 0xFFFF9862 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTEDS_PTEDS0: .equ 0 ; Output Drive Strength Selection for Port E Bit 0 PTEDS_PTEDS1: .equ 1 ; Output Drive Strength Selection for Port E Bit 1 PTEDS_PTEDS2: .equ 2 ; Output Drive Strength Selection for Port E Bit 2 PTEDS_PTEDS3: .equ 3 ; Output Drive Strength Selection for Port E Bit 3 PTEDS_PTEDS4: .equ 4 ; Output Drive Strength Selection for Port E Bit 4 PTEDS_PTEDS5: .equ 5 ; Output Drive Strength Selection for Port E Bit 5 PTEDS_PTEDS6: .equ 6 ; Output Drive Strength Selection for Port E Bit 6 PTEDS_PTEDS7: .equ 7 ; Output Drive Strength Selection for Port E Bit 7 ; bit position masks mPTEDS_PTEDS0: .equ %00000001 mPTEDS_PTEDS1: .equ %00000010 mPTEDS_PTEDS2: .equ %00000100 mPTEDS_PTEDS3: .equ %00001000 mPTEDS_PTEDS4: .equ %00010000 mPTEDS_PTEDS5: .equ %00100000 mPTEDS_PTEDS6: .equ %01000000 mPTEDS_PTEDS7: .equ %10000000 ;*** PTEIFE - Port E Input Filter Enable Register; 0xFFFF9863 *** PTEIFE: .equ $FFFF9863 ;*** PTEIFE - Port E Input Filter Enable Register; 0xFFFF9863 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTEIFE_PTEIFE0: .equ 0 ; Port E Input Filter Enable Bit 0 PTEIFE_PTEIFE1: .equ 1 ; Port E Input Filter Enable Bit 1 PTEIFE_PTEIFE2: .equ 2 ; Port E Input Filter Enable Bit 2 PTEIFE_PTEIFE3: .equ 3 ; Port E Input Filter Enable Bit 3 PTEIFE_PTEIFE4: .equ 4 ; Port E Input Filter Enable Bit 4 PTEIFE_PTEIFE5: .equ 5 ; Port E Input Filter Enable Bit 5 PTEIFE_PTEIFE6: .equ 6 ; Port E Input Filter Enable Bit 6 PTEIFE_PTEIFE7: .equ 7 ; Port E Input Filter Enable Bit 7 ; bit position masks mPTEIFE_PTEIFE0: .equ %00000001 mPTEIFE_PTEIFE1: .equ %00000010 mPTEIFE_PTEIFE2: .equ %00000100 mPTEIFE_PTEIFE3: .equ %00001000 mPTEIFE_PTEIFE4: .equ %00010000 mPTEIFE_PTEIFE5: .equ %00100000 mPTEIFE_PTEIFE6: .equ %01000000 mPTEIFE_PTEIFE7: .equ %10000000 ;*** PTFPE - Port F Pull Enable Register; 0xFFFF9864 *** PTFPE: .equ $FFFF9864 ;*** PTFPE - Port F Pull Enable Register; 0xFFFF9864 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTFPE_PTFPE0: .equ 0 ; Internal Pull Enable for Port F Bit 0 PTFPE_PTFPE1: .equ 1 ; Internal Pull Enable for Port F Bit 1 PTFPE_PTFPE2: .equ 2 ; Internal Pull Enable for Port F Bit 2 PTFPE_PTFPE3: .equ 3 ; Internal Pull Enable for Port F Bit 3 PTFPE_PTFPE4: .equ 4 ; Internal Pull Enable for Port F Bit 4 PTFPE_PTFPE5: .equ 5 ; Internal Pull Enable for Port F Bit 5 PTFPE_PTFPE6: .equ 6 ; Internal Pull Enable for Port F Bit 6 PTFPE_PTFPE7: .equ 7 ; Internal Pull Enable for Port F Bit 7 ; bit position masks mPTFPE_PTFPE0: .equ %00000001 mPTFPE_PTFPE1: .equ %00000010 mPTFPE_PTFPE2: .equ %00000100 mPTFPE_PTFPE3: .equ %00001000 mPTFPE_PTFPE4: .equ %00010000 mPTFPE_PTFPE5: .equ %00100000 mPTFPE_PTFPE6: .equ %01000000 mPTFPE_PTFPE7: .equ %10000000 ;*** PTFSE - Port F Slew Rate Enable Register; 0xFFFF9865 *** PTFSE: .equ $FFFF9865 ;*** PTFSE - Port F Slew Rate Enable Register; 0xFFFF9865 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTFSE_PTFSE0: .equ 0 ; Output Slew Rate Enable for Port F Bit 0 PTFSE_PTFSE1: .equ 1 ; Output Slew Rate Enable for Port F Bit 1 PTFSE_PTFSE2: .equ 2 ; Output Slew Rate Enable for Port F Bit 2 PTFSE_PTFSE3: .equ 3 ; Output Slew Rate Enable for Port F Bit 3 PTFSE_PTFSE4: .equ 4 ; Output Slew Rate Enable for Port F Bit 4 PTFSE_PTFSE5: .equ 5 ; Output Slew Rate Enable for Port F Bit 5 PTFSE_PTFSE6: .equ 6 ; Output Slew Rate Enable for Port F Bit 6 PTFSE_PTFSE7: .equ 7 ; Output Slew Rate Enable for Port F Bit 7 ; bit position masks mPTFSE_PTFSE0: .equ %00000001 mPTFSE_PTFSE1: .equ %00000010 mPTFSE_PTFSE2: .equ %00000100 mPTFSE_PTFSE3: .equ %00001000 mPTFSE_PTFSE4: .equ %00010000 mPTFSE_PTFSE5: .equ %00100000 mPTFSE_PTFSE6: .equ %01000000 mPTFSE_PTFSE7: .equ %10000000 ;*** PTFDS - Port F Drive Strength Selection Register; 0xFFFF9866 *** PTFDS: .equ $FFFF9866 ;*** PTFDS - Port F Drive Strength Selection Register; 0xFFFF9866 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTFDS_PTFDS0: .equ 0 ; Output Drive Strength Selection for Port F Bit 0 PTFDS_PTFDS1: .equ 1 ; Output Drive Strength Selection for Port F Bit 1 PTFDS_PTFDS2: .equ 2 ; Output Drive Strength Selection for Port F Bit 2 PTFDS_PTFDS3: .equ 3 ; Output Drive Strength Selection for Port F Bit 3 PTFDS_PTFDS4: .equ 4 ; Output Drive Strength Selection for Port F Bit 4 PTFDS_PTFDS5: .equ 5 ; Output Drive Strength Selection for Port F Bit 5 PTFDS_PTFDS6: .equ 6 ; Output Drive Strength Selection for Port F Bit 6 PTFDS_PTFDS7: .equ 7 ; Output Drive Strength Selection for Port F Bit 7 ; bit position masks mPTFDS_PTFDS0: .equ %00000001 mPTFDS_PTFDS1: .equ %00000010 mPTFDS_PTFDS2: .equ %00000100 mPTFDS_PTFDS3: .equ %00001000 mPTFDS_PTFDS4: .equ %00010000 mPTFDS_PTFDS5: .equ %00100000 mPTFDS_PTFDS6: .equ %01000000 mPTFDS_PTFDS7: .equ %10000000 ;*** PTFIFE - Port F Input Filter Enable Register; 0xFFFF9867 *** PTFIFE: .equ $FFFF9867 ;*** PTFIFE - Port F Input Filter Enable Register; 0xFFFF9867 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTFIFE_PTFIFE0: .equ 0 ; Port F Input Filter Enable Bit 0 PTFIFE_PTFIFE1: .equ 1 ; Port F Input Filter Enable Bit 1 PTFIFE_PTFIFE2: .equ 2 ; Port F Input Filter Enable Bit 2 PTFIFE_PTFIFE3: .equ 3 ; Port F Input Filter Enable Bit 3 PTFIFE_PTFIFE4: .equ 4 ; Port F Input Filter Enable Bit 4 PTFIFE_PTFIFE5: .equ 5 ; Port F Input Filter Enable Bit 5 PTFIFE_PTFIFE6: .equ 6 ; Port F Input Filter Enable Bit 6 PTFIFE_PTFIFE7: .equ 7 ; Port F Input Filter Enable Bit 7 ; bit position masks mPTFIFE_PTFIFE0: .equ %00000001 mPTFIFE_PTFIFE1: .equ %00000010 mPTFIFE_PTFIFE2: .equ %00000100 mPTFIFE_PTFIFE3: .equ %00001000 mPTFIFE_PTFIFE4: .equ %00010000 mPTFIFE_PTFIFE5: .equ %00100000 mPTFIFE_PTFIFE6: .equ %01000000 mPTFIFE_PTFIFE7: .equ %10000000 ;*** PTGPE - Port G Pull Enable Register; 0xFFFF9868 *** PTGPE: .equ $FFFF9868 ;*** PTGPE - Port G Pull Enable Register; 0xFFFF9868 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTGPE_PTGPE0: .equ 0 ; Internal Pull Enable for Port G Bit 0 PTGPE_PTGPE1: .equ 1 ; Internal Pull Enable for Port G Bit 1 PTGPE_PTGPE2: .equ 2 ; Internal Pull Enable for Port G Bit 2 PTGPE_PTGPE3: .equ 3 ; Internal Pull Enable for Port G Bit 3 PTGPE_PTGPE4: .equ 4 ; Internal Pull Enable for Port G Bit 4 PTGPE_PTGPE5: .equ 5 ; Internal Pull Enable for Port G Bit 5 PTGPE_PTGPE6: .equ 6 ; Internal Pull Enable for Port G Bit 6 PTGPE_PTGPE7: .equ 7 ; Internal Pull Enable for Port G Bit 7 ; bit position masks mPTGPE_PTGPE0: .equ %00000001 mPTGPE_PTGPE1: .equ %00000010 mPTGPE_PTGPE2: .equ %00000100 mPTGPE_PTGPE3: .equ %00001000 mPTGPE_PTGPE4: .equ %00010000 mPTGPE_PTGPE5: .equ %00100000 mPTGPE_PTGPE6: .equ %01000000 mPTGPE_PTGPE7: .equ %10000000 ;*** PTGSE - Port G Slew Rate Enable Register; 0xFFFF9869 *** PTGSE: .equ $FFFF9869 ;*** PTGSE - Port G Slew Rate Enable Register; 0xFFFF9869 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTGSE_PTGSE0: .equ 0 ; Output Slew Rate Enable for Port G Bit 0 PTGSE_PTGSE1: .equ 1 ; Output Slew Rate Enable for Port G Bit 1 PTGSE_PTGSE2: .equ 2 ; Output Slew Rate Enable for Port G Bit 2 PTGSE_PTGSE3: .equ 3 ; Output Slew Rate Enable for Port G Bit 3 PTGSE_PTGSE4: .equ 4 ; Output Slew Rate Enable for Port G Bit 4 PTGSE_PTGSE5: .equ 5 ; Output Slew Rate Enable for Port G Bit 5 PTGSE_PTGSE6: .equ 6 ; Output Slew Rate Enable for Port G Bit 6 PTGSE_PTGSE7: .equ 7 ; Output Slew Rate Enable for Port G Bit 7 ; bit position masks mPTGSE_PTGSE0: .equ %00000001 mPTGSE_PTGSE1: .equ %00000010 mPTGSE_PTGSE2: .equ %00000100 mPTGSE_PTGSE3: .equ %00001000 mPTGSE_PTGSE4: .equ %00010000 mPTGSE_PTGSE5: .equ %00100000 mPTGSE_PTGSE6: .equ %01000000 mPTGSE_PTGSE7: .equ %10000000 ;*** PTGDS - Port G Drive Strength Selection Register; 0xFFFF986A *** PTGDS: .equ $FFFF986A ;*** PTGDS - Port G Drive Strength Selection Register; 0xFFFF986A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTGDS_PTGDS0: .equ 0 ; Output Drive Strength Selection for Port G Bit 0 PTGDS_PTGDS1: .equ 1 ; Output Drive Strength Selection for Port G Bit 1 PTGDS_PTGDS2: .equ 2 ; Output Drive Strength Selection for Port G Bit 2 PTGDS_PTGDS3: .equ 3 ; Output Drive Strength Selection for Port G Bit 3 PTGDS_PTGDS4: .equ 4 ; Output Drive Strength Selection for Port G Bit 4 PTGDS_PTGDS5: .equ 5 ; Output Drive Strength Selection for Port G Bit 5 PTGDS_PTGDS6: .equ 6 ; Output Drive Strength Selection for Port G Bit 6 PTGDS_PTGDS7: .equ 7 ; Output Drive Strength Selection for Port G Bit 7 ; bit position masks mPTGDS_PTGDS0: .equ %00000001 mPTGDS_PTGDS1: .equ %00000010 mPTGDS_PTGDS2: .equ %00000100 mPTGDS_PTGDS3: .equ %00001000 mPTGDS_PTGDS4: .equ %00010000 mPTGDS_PTGDS5: .equ %00100000 mPTGDS_PTGDS6: .equ %01000000 mPTGDS_PTGDS7: .equ %10000000 ;*** PTGIFE - Port G Input Filter Enable Register; 0xFFFF986B *** PTGIFE: .equ $FFFF986B ;*** PTGIFE - Port G Input Filter Enable Register; 0xFFFF986B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTGIFE_PTGIFE0: .equ 0 ; Port G Input Filter Enable Bit 0 PTGIFE_PTGIFE1: .equ 1 ; Port G Input Filter Enable Bit 1 PTGIFE_PTGIFE2: .equ 2 ; Port G Input Filter Enable Bit 2 PTGIFE_PTGIFE3: .equ 3 ; Port G Input Filter Enable Bit 3 PTGIFE_PTGIFE4: .equ 4 ; Port G Input Filter Enable Bit 4 PTGIFE_PTGIFE5: .equ 5 ; Port G Input Filter Enable Bit 5 PTGIFE_PTGIFE6: .equ 6 ; Port G Input Filter Enable Bit 6 PTGIFE_PTGIFE7: .equ 7 ; Port G Input Filter Enable Bit 7 ; bit position masks mPTGIFE_PTGIFE0: .equ %00000001 mPTGIFE_PTGIFE1: .equ %00000010 mPTGIFE_PTGIFE2: .equ %00000100 mPTGIFE_PTGIFE3: .equ %00001000 mPTGIFE_PTGIFE4: .equ %00010000 mPTGIFE_PTGIFE5: .equ %00100000 mPTGIFE_PTGIFE6: .equ %01000000 mPTGIFE_PTGIFE7: .equ %10000000 ;*** CMTCG1 - Carrier Generator Data Register 1; 0xFFFF9870 *** CMTCG1: .equ $FFFF9870 ;*** CMTCG1 - Carrier Generator Data Register 1; 0xFFFF9870 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET CMTCG1_PL0: .equ 0 ; Primary Carrier Low Time Data Value Bit 0 CMTCG1_PL1: .equ 1 ; Primary Carrier Low Time Data Value Bit 1 CMTCG1_PL2: .equ 2 ; Primary Carrier Low Time Data Value Bit 2 CMTCG1_PL3: .equ 3 ; Primary Carrier Low Time Data Value Bit 3 CMTCG1_PL4: .equ 4 ; Primary Carrier Low Time Data Value Bit 4 CMTCG1_PL5: .equ 5 ; Primary Carrier Low Time Data Value Bit 5 CMTCG1_PL6: .equ 6 ; Primary Carrier Low Time Data Value Bit 6 CMTCG1_PL7: .equ 7 ; Primary Carrier Low Time Data Value Bit 0 CMTCG1_PH0: .equ 8 ; Primary Carrier High Time Data Value Bit 0 CMTCG1_PH1: .equ 9 ; Primary Carrier High Time Data Value Bit 1 CMTCG1_PH2: .equ 10 ; Primary Carrier High Time Data Value Bit 2 CMTCG1_PH3: .equ 11 ; Primary Carrier High Time Data Value Bit 3 CMTCG1_PH4: .equ 12 ; Primary Carrier High Time Data Value Bit 4 CMTCG1_PH5: .equ 13 ; Primary Carrier High Time Data Value Bit 5 CMTCG1_PH6: .equ 14 ; Primary Carrier High Time Data Value Bit 6 CMTCG1_PH7: .equ 15 ; Primary Carrier High Time Data Value Bit 7 ; bit position masks mCMTCG1_PL0: .equ %00000001 mCMTCG1_PL1: .equ %00000010 mCMTCG1_PL2: .equ %00000100 mCMTCG1_PL3: .equ %00001000 mCMTCG1_PL4: .equ %00010000 mCMTCG1_PL5: .equ %00100000 mCMTCG1_PL6: .equ %01000000 mCMTCG1_PL7: .equ %10000000 mCMTCG1_PH0: .equ %100000000 mCMTCG1_PH1: .equ %1000000000 mCMTCG1_PH2: .equ %10000000000 mCMTCG1_PH3: .equ %100000000000 mCMTCG1_PH4: .equ %1000000000000 mCMTCG1_PH5: .equ %10000000000000 mCMTCG1_PH6: .equ %100000000000000 mCMTCG1_PH7: .equ %1000000000000000 ;*** CMTCGH1 - CMT Carrier Generator Data Register 1 High Byte; 0xFFFF9870 *** CMTCGH1: .equ $FFFF9870 ;*** CMTCGH1 - CMT Carrier Generator Data Register 1 High Byte; 0xFFFF9870 *** ;*** CMTCGL1 - CMT Carrier Generator Data Register 1 Low Byte; 0xFFFF9871 *** CMTCGL1: .equ $FFFF9871 ;*** CMTCGL1 - CMT Carrier Generator Data Register 1 Low Byte; 0xFFFF9871 *** ;*** CMTCG2 - Carrier Generator Data Register 2; 0xFFFF9872 *** CMTCG2: .equ $FFFF9872 ;*** CMTCG2 - Carrier Generator Data Register 2; 0xFFFF9872 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET CMTCG2_SL0: .equ 0 ; Secondary Carrier Low Time Data Value Bit 0 CMTCG2_SL1: .equ 1 ; Secondary Carrier Low Time Data Value Bit 1 CMTCG2_SL2: .equ 2 ; Secondary Carrier Low Time Data Value Bit 2 CMTCG2_SL3: .equ 3 ; Secondary Carrier Low Time Data Value Bit 3 CMTCG2_SL4: .equ 4 ; Secondary Carrier Low Time Data Value Bit 4 CMTCG2_SL5: .equ 5 ; Secondary Carrier Low Time Data Value Bit 5 CMTCG2_SL6: .equ 6 ; Secondary Carrier Low Time Data Value Bit 6 CMTCG2_SL7: .equ 7 ; Secondary Carrier Low Time Data Value Bit 7 CMTCG2_SH0: .equ 8 ; Secondary Carrier High Time Data Value Bit 0 CMTCG2_SH1: .equ 9 ; Secondary Carrier High Time Data Value Bit 1 CMTCG2_SH2: .equ 10 ; Secondary Carrier High Time Data Value Bit 2 CMTCG2_SH3: .equ 11 ; Secondary Carrier High Time Data Value Bit 3 CMTCG2_SH4: .equ 12 ; Secondary Carrier High Time Data Value Bit 4 CMTCG2_SH5: .equ 13 ; Secondary Carrier High Time Data Value Bit 5 CMTCG2_SH6: .equ 14 ; Secondary Carrier High Time Data Value Bit 6 CMTCG2_SH7: .equ 15 ; Secondary Carrier High Time Data Value Bit 7 ; bit position masks mCMTCG2_SL0: .equ %00000001 mCMTCG2_SL1: .equ %00000010 mCMTCG2_SL2: .equ %00000100 mCMTCG2_SL3: .equ %00001000 mCMTCG2_SL4: .equ %00010000 mCMTCG2_SL5: .equ %00100000 mCMTCG2_SL6: .equ %01000000 mCMTCG2_SL7: .equ %10000000 mCMTCG2_SH0: .equ %100000000 mCMTCG2_SH1: .equ %1000000000 mCMTCG2_SH2: .equ %10000000000 mCMTCG2_SH3: .equ %100000000000 mCMTCG2_SH4: .equ %1000000000000 mCMTCG2_SH5: .equ %10000000000000 mCMTCG2_SH6: .equ %100000000000000 mCMTCG2_SH7: .equ %1000000000000000 ;*** CMTCGH2 - CMT Carrier Generator Data Register 2 High Byte; 0xFFFF9872 *** CMTCGH2: .equ $FFFF9872 ;*** CMTCGH2 - CMT Carrier Generator Data Register 2 High Byte; 0xFFFF9872 *** ;*** CMTCGL2 - CMT Carrier Generator Data Register 2 Low Byte; 0xFFFF9873 *** CMTCGL2: .equ $FFFF9873 ;*** CMTCGL2 - CMT Carrier Generator Data Register 2 Low Byte; 0xFFFF9873 *** ;*** CMTOC - CMT Output Control Register; 0xFFFF9874 *** CMTOC: .equ $FFFF9874 ;*** CMTOC - CMT Output Control Register; 0xFFFF9874 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET CMTOC_IROPEN: .equ 5 ; IRO pin enable CMTOC_CMTPOL: .equ 6 ; CMT output polarity CMTOC_IROL: .equ 7 ; IRO latch control ; bit position masks mCMTOC_IROPEN: .equ %00100000 mCMTOC_CMTPOL: .equ %01000000 mCMTOC_IROL: .equ %10000000 ;*** CMTMSC - CMT Modulator Status and Control Register; 0xFFFF9875 *** CMTMSC: .equ $FFFF9875 ;*** CMTMSC - CMT Modulator Status and Control Register; 0xFFFF9875 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET CMTMSC_MCGEN: .equ 0 ; Modulator and Carrier Generator Enable CMTMSC_EOCIE: .equ 1 ; End of Cycle Interrupt Enable CMTMSC_FSK: .equ 2 ; FSK Mode Select CMTMSC_BASE: .equ 3 ; Baseband Mode Enable CMTMSC_EXSPC: .equ 4 ; Extended Space Enable CMTMSC_CMTDIV0: .equ 5 ; CMT Clock Divide Prescaler Bit 0 CMTMSC_CMTDIV1: .equ 6 ; CMT Clock Divide Prescaler Bit 1 CMTMSC_EOCF: .equ 7 ; End of Cycle Status Flag ; bit position masks mCMTMSC_MCGEN: .equ %00000001 mCMTMSC_EOCIE: .equ %00000010 mCMTMSC_FSK: .equ %00000100 mCMTMSC_BASE: .equ %00001000 mCMTMSC_EXSPC: .equ %00010000 mCMTMSC_CMTDIV0: .equ %00100000 mCMTMSC_CMTDIV1: .equ %01000000 mCMTMSC_EOCF: .equ %10000000 ;*** CMTCMD12 - CMT Modulator Data Register 12; 0xFFFF9876 *** CMTCMD12: .equ $FFFF9876 ;*** CMTCMD12 - CMT Modulator Data Register 12; 0xFFFF9876 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET CMTCMD12_MB0: .equ 0 ; Data Value Bit 0 CMTCMD12_MB1: .equ 1 ; Data Value Bit 1 CMTCMD12_MB2: .equ 2 ; Data Value Bit 2 CMTCMD12_MB3: .equ 3 ; Data Value Bit 3 CMTCMD12_MB4: .equ 4 ; Data Value Bit 4 CMTCMD12_MB5: .equ 5 ; Data Value Bit 5 CMTCMD12_MB6: .equ 6 ; Data Value Bit 6 CMTCMD12_MB7: .equ 7 ; Data Value Bit 7 CMTCMD12_MB8: .equ 8 ; Data Value Bit 8 CMTCMD12_MB9: .equ 9 ; Data Value Bit 9 CMTCMD12_MB10: .equ 10 ; Data Value Bit 10 CMTCMD12_MB11: .equ 11 ; Data Value Bit 11 CMTCMD12_MB12: .equ 12 ; Data Value Bit 12 CMTCMD12_MB13: .equ 13 ; Data Value Bit 13 CMTCMD12_MB14: .equ 14 ; Data Value Bit 14 CMTCMD12_MB15: .equ 15 ; Data Value Bit 15 ; bit position masks mCMTCMD12_MB0: .equ %00000001 mCMTCMD12_MB1: .equ %00000010 mCMTCMD12_MB2: .equ %00000100 mCMTCMD12_MB3: .equ %00001000 mCMTCMD12_MB4: .equ %00010000 mCMTCMD12_MB5: .equ %00100000 mCMTCMD12_MB6: .equ %01000000 mCMTCMD12_MB7: .equ %10000000 mCMTCMD12_MB8: .equ %100000000 mCMTCMD12_MB9: .equ %1000000000 mCMTCMD12_MB10: .equ %10000000000 mCMTCMD12_MB11: .equ %100000000000 mCMTCMD12_MB12: .equ %1000000000000 mCMTCMD12_MB13: .equ %10000000000000 mCMTCMD12_MB14: .equ %100000000000000 mCMTCMD12_MB15: .equ %1000000000000000 ;*** CMTCMD1 - CMT Modulator Data Register 1; 0xFFFF9876 *** CMTCMD1: .equ $FFFF9876 ;*** CMTCMD1 - CMT Modulator Data Register 1; 0xFFFF9876 *** ;*** CMTCMD2 - CMT Modulator Data Register 2; 0xFFFF9877 *** CMTCMD2: .equ $FFFF9877 ;*** CMTCMD2 - CMT Modulator Data Register 2; 0xFFFF9877 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET CMTCMD2_MB0: .equ 0 ; Data Value Bit 0 CMTCMD2_MB1: .equ 1 ; Data Value Bit 1 CMTCMD2_MB2: .equ 2 ; Data Value Bit 2 CMTCMD2_MB3: .equ 3 ; Data Value Bit 3 CMTCMD2_MB4: .equ 4 ; Data Value Bit 4 CMTCMD2_MB5: .equ 5 ; Data Value Bit 5 CMTCMD2_MB6: .equ 6 ; Data Value Bit 6 CMTCMD2_MB7: .equ 7 ; Data Value Bit 7 ; bit position masks mCMTCMD2_MB0: .equ %00000001 mCMTCMD2_MB1: .equ %00000010 mCMTCMD2_MB2: .equ %00000100 mCMTCMD2_MB3: .equ %00001000 mCMTCMD2_MB4: .equ %00010000 mCMTCMD2_MB5: .equ %00100000 mCMTCMD2_MB6: .equ %01000000 mCMTCMD2_MB7: .equ %10000000 ;*** CMTCMD34 - CMT Modulator Data Register 34; 0xFFFF9878 *** CMTCMD34: .equ $FFFF9878 ;*** CMTCMD34 - CMT Modulator Data Register 34; 0xFFFF9878 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET CMTCMD34_SB0: .equ 0 ; Data Value Bit 0 CMTCMD34_SB1: .equ 1 ; Data Value Bit 1 CMTCMD34_SB2: .equ 2 ; Data Value Bit 2 CMTCMD34_SB3: .equ 3 ; Data Value Bit 3 CMTCMD34_SB4: .equ 4 ; Data Value Bit 4 CMTCMD34_SB5: .equ 5 ; Data Value Bit 5 CMTCMD34_SB6: .equ 6 ; Data Value Bit 6 CMTCMD34_SB7: .equ 7 ; Data Value Bit 7 CMTCMD34_SB8: .equ 8 ; Data Value Bit 8 CMTCMD34_SB9: .equ 9 ; Data Value Bit 9 CMTCMD34_SB10: .equ 10 ; Data Value Bit 10 CMTCMD34_SB11: .equ 11 ; Data Value Bit 11 CMTCMD34_SB12: .equ 12 ; Data Value Bit 12 CMTCMD34_SB13: .equ 13 ; Data Value Bit 13 CMTCMD34_SB14: .equ 14 ; Data Value Bit 14 CMTCMD34_SB15: .equ 15 ; Data Value Bit 15 ; bit position masks mCMTCMD34_SB0: .equ %00000001 mCMTCMD34_SB1: .equ %00000010 mCMTCMD34_SB2: .equ %00000100 mCMTCMD34_SB3: .equ %00001000 mCMTCMD34_SB4: .equ %00010000 mCMTCMD34_SB5: .equ %00100000 mCMTCMD34_SB6: .equ %01000000 mCMTCMD34_SB7: .equ %10000000 mCMTCMD34_SB8: .equ %100000000 mCMTCMD34_SB9: .equ %1000000000 mCMTCMD34_SB10: .equ %10000000000 mCMTCMD34_SB11: .equ %100000000000 mCMTCMD34_SB12: .equ %1000000000000 mCMTCMD34_SB13: .equ %10000000000000 mCMTCMD34_SB14: .equ %100000000000000 mCMTCMD34_SB15: .equ %1000000000000000 ;*** CMTCMD3 - CMT Modulator Data Register 3; 0xFFFF9878 *** CMTCMD3: .equ $FFFF9878 ;*** CMTCMD3 - CMT Modulator Data Register 3; 0xFFFF9878 *** ;*** CMTCMD4 - CMT Modulator Data Register 4; 0xFFFF9879 *** CMTCMD4: .equ $FFFF9879 ;*** CMTCMD4 - CMT Modulator Data Register 4; 0xFFFF9879 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET CMTCMD4_SB0: .equ 0 ; Data Value Bit 0 CMTCMD4_SB1: .equ 1 ; Data Value Bit 1 CMTCMD4_SB2: .equ 2 ; Data Value Bit 2 CMTCMD4_SB3: .equ 3 ; Data Value Bit 3 CMTCMD4_SB4: .equ 4 ; Data Value Bit 4 CMTCMD4_SB5: .equ 5 ; Data Value Bit 5 CMTCMD4_SB6: .equ 6 ; Data Value Bit 6 CMTCMD4_SB7: .equ 7 ; Data Value Bit 7 ; bit position masks mCMTCMD4_SB0: .equ %00000001 mCMTCMD4_SB1: .equ %00000010 mCMTCMD4_SB2: .equ %00000100 mCMTCMD4_SB3: .equ %00001000 mCMTCMD4_SB4: .equ %00010000 mCMTCMD4_SB5: .equ %00100000 mCMTCMD4_SB6: .equ %01000000 mCMTCMD4_SB7: .equ %10000000 ;*** CRCH - CRC High Register; 0xFFFF9890 *** CRCH: .equ $FFFF9890 ;*** CRCH - CRC High Register; 0xFFFF9890 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET CRCH_BIT8: .equ 0 ; High byte of CRC register ,bit 8 CRCH_BIT9: .equ 1 ; High byte of CRC register ,bit 9 CRCH_BIT10: .equ 2 ; High byte of CRC register ,bit 10 CRCH_BIT11: .equ 3 ; High byte of CRC register ,bit 11 CRCH_BIT12: .equ 4 ; High byte of CRC register ,bit 12 CRCH_BIT13: .equ 5 ; High byte of CRC register ,bit 13 CRCH_BIT14: .equ 6 ; High byte of CRC register ,bit 14 CRCH_BIT15: .equ 7 ; High byte of CRC register ,bit 15 ; bit position masks mCRCH_BIT8: .equ %00000001 mCRCH_BIT9: .equ %00000010 mCRCH_BIT10: .equ %00000100 mCRCH_BIT11: .equ %00001000 mCRCH_BIT12: .equ %00010000 mCRCH_BIT13: .equ %00100000 mCRCH_BIT14: .equ %01000000 mCRCH_BIT15: .equ %10000000 ;*** CRCL - CRC Low Register; 0xFFFF9891 *** CRCL: .equ $FFFF9891 ;*** CRCL - CRC Low Register; 0xFFFF9891 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET CRCL_BIT0: .equ 0 ; Low byte of CRC register, bit 0 CRCL_BIT1: .equ 1 ; Low byte of CRC register, bit 1 CRCL_BIT2: .equ 2 ; Low byte of CRC register, bit 2 CRCL_BIT3: .equ 3 ; Low byte of CRC register, bit 3 CRCL_BIT4: .equ 4 ; Low byte of CRC register, bit 4 CRCL_BIT5: .equ 5 ; Low byte of CRC register, bit 5 CRCL_BIT6: .equ 6 ; Low byte of CRC register, bit 6 CRCL_BIT7: .equ 7 ; Low byte of CRC register, bit 7 ; bit position masks mCRCL_BIT0: .equ %00000001 mCRCL_BIT1: .equ %00000010 mCRCL_BIT2: .equ %00000100 mCRCL_BIT3: .equ %00001000 mCRCL_BIT4: .equ %00010000 mCRCL_BIT5: .equ %00100000 mCRCL_BIT6: .equ %01000000 mCRCL_BIT7: .equ %10000000 ;*** TRANSPOSE - CRC Transpose Register; 0xFFFF9892 *** TRANSPOSE: .equ $FFFF9892 ;*** TRANSPOSE - CRC Transpose Register; 0xFFFF9892 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TRANSPOSE_BIT0: .equ 0 ; CRC transpose register, bit 0 TRANSPOSE_BIT1: .equ 1 ; CRC transpose register, bit 1 TRANSPOSE_BIT2: .equ 2 ; CRC transpose register, bit 2 TRANSPOSE_BIT3: .equ 3 ; CRC transpose register, bit 3 TRANSPOSE_BIT4: .equ 4 ; CRC transpose register, bit 4 TRANSPOSE_BIT5: .equ 5 ; CRC transpose register, bit 5 TRANSPOSE_BIT6: .equ 6 ; CRC transpose register, bit 6 TRANSPOSE_BIT7: .equ 7 ; CRC transpose register, bit 7 ; bit position masks mTRANSPOSE_BIT0: .equ %00000001 mTRANSPOSE_BIT1: .equ %00000010 mTRANSPOSE_BIT2: .equ %00000100 mTRANSPOSE_BIT3: .equ %00001000 mTRANSPOSE_BIT4: .equ %00010000 mTRANSPOSE_BIT5: .equ %00100000 mTRANSPOSE_BIT6: .equ %01000000 mTRANSPOSE_BIT7: .equ %10000000 ;*** TODC - TOD Control Register; 0xFFFF989C *** TODC: .equ $FFFF989C ;*** TODC - TOD Control Register; 0xFFFF989C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TODC_TODPS0: .equ 0 ; TOD Prescaler Bits, bit 0 TODC_TODPS1: .equ 1 ; TOD Prescaler Bits, bit 1 TODC_TODPS2: .equ 2 ; TOD Prescaler Bits, bit 2 TODC_TODCLKEN: .equ 3 ; TOD Clock Enable TODC_TODR: .equ 4 ; TOD Reset TODC_TODCLKS0: .equ 5 ; TOD Clock Source, bit 0 TODC_TODCLKS1: .equ 6 ; TOD Clock Source, bit 1 TODC_TODEN: .equ 7 ; Time of Day Enable ; bit position masks mTODC_TODPS0: .equ %00000001 mTODC_TODPS1: .equ %00000010 mTODC_TODPS2: .equ %00000100 mTODC_TODCLKEN: .equ %00001000 mTODC_TODR: .equ %00010000 mTODC_TODCLKS0: .equ %00100000 mTODC_TODCLKS1: .equ %01000000 mTODC_TODEN: .equ %10000000 ;*** TODSC - TOD Status and Control Register; 0xFFFF989D *** TODSC: .equ $FFFF989D ;*** TODSC - TOD Status and Control Register; 0xFFFF989D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TODSC_MTCHWC: .equ 0 ; Match Write Complete TODSC_MTCHEN: .equ 1 ; Match Function Enable TODSC_MTCHIE: .equ 2 ; Match Interrupt Enable TODSC_SECIE: .equ 3 ; Second Interrupt Enable TODSC_QSECIE: .equ 4 ; Quarter-Second Interrupt Enable TODSC_MTCHF: .equ 5 ; Match Interrupt Flag TODSC_SECF: .equ 6 ; Second Interrupt Flag TODSC_QSECF: .equ 7 ; Quarter-Second Interrupt Flag ; bit position masks mTODSC_MTCHWC: .equ %00000001 mTODSC_MTCHEN: .equ %00000010 mTODSC_MTCHIE: .equ %00000100 mTODSC_SECIE: .equ %00001000 mTODSC_QSECIE: .equ %00010000 mTODSC_MTCHF: .equ %00100000 mTODSC_SECF: .equ %01000000 mTODSC_QSECF: .equ %10000000 ;*** TODM - TOD Match Register; 0xFFFF989E *** TODM: .equ $FFFF989E ;*** TODM - TOD Match Register; 0xFFFF989E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TODM_MQSEC0: .equ 0 ; Match Quarter-Second Bits, bit 0 TODM_MQSEC1: .equ 1 ; Match Quarter-Second Bits, bit 1 TODM_TODM0: .equ 2 ; TOD Match Value, bit 0 TODM_TODM1: .equ 3 ; TOD Match Value, bit 1 TODM_TODM2: .equ 4 ; TOD Match Value, bit 2 TODM_TODM3: .equ 5 ; TOD Match Value, bit 3 TODM_TODM4: .equ 6 ; TOD Match Value, bit 4 TODM_TODM5: .equ 7 ; TOD Match Value, bit 5 ; bit position masks mTODM_MQSEC0: .equ %00000001 mTODM_MQSEC1: .equ %00000010 mTODM_TODM0: .equ %00000100 mTODM_TODM1: .equ %00001000 mTODM_TODM2: .equ %00010000 mTODM_TODM3: .equ %00100000 mTODM_TODM4: .equ %01000000 mTODM_TODM5: .equ %10000000 ;*** TODCNT - TOD Counter Register; 0xFFFF989F *** TODCNT: .equ $FFFF989F ;*** TODCNT - TOD Counter Register; 0xFFFF989F *** ;*** TPM2SC - TPM2 Status and Control Register; 0xFFFF98A0 *** TPM2SC: .equ $FFFF98A0 ;*** TPM2SC - TPM2 Status and Control Register; 0xFFFF98A0 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPM2SC_PS0: .equ 0 ; Prescale Divisor Select Bit 0 TPM2SC_PS1: .equ 1 ; Prescale Divisor Select Bit 1 TPM2SC_PS2: .equ 2 ; Prescale Divisor Select Bit 2 TPM2SC_CLKSA: .equ 3 ; Clock Source Select A TPM2SC_CLKSB: .equ 4 ; Clock Source Select B TPM2SC_CPWMS: .equ 5 ; Center-Aligned PWM Select TPM2SC_TOIE: .equ 6 ; Timer Overflow Interrupt Enable TPM2SC_TOF: .equ 7 ; Timer Overflow Flag ; bit position masks mTPM2SC_PS0: .equ %00000001 mTPM2SC_PS1: .equ %00000010 mTPM2SC_PS2: .equ %00000100 mTPM2SC_CLKSA: .equ %00001000 mTPM2SC_CLKSB: .equ %00010000 mTPM2SC_CPWMS: .equ %00100000 mTPM2SC_TOIE: .equ %01000000 mTPM2SC_TOF: .equ %10000000 ;*** TPM2CNT - TPM2 Timer Counter Register; 0xFFFF98A1 *** TPM2CNT: .equ $FFFF98A1 ;*** TPM2CNT - TPM2 Timer Counter Register; 0xFFFF98A1 *** ;*** TPM2CNTH - TPM2 Timer Counter Register High; 0xFFFF98A1 *** TPM2CNTH: .equ $FFFF98A1 ;*** TPM2CNTH - TPM2 Timer Counter Register High; 0xFFFF98A1 *** ;*** TPM2CNTL - TPM2 Timer Counter Register Low; 0xFFFF98A2 *** TPM2CNTL: .equ $FFFF98A2 ;*** TPM2CNTL - TPM2 Timer Counter Register Low; 0xFFFF98A2 *** ;*** TPM2MOD - TPM2 Timer Counter Modulo Register; 0xFFFF98A3 *** TPM2MOD: .equ $FFFF98A3 ;*** TPM2MOD - TPM2 Timer Counter Modulo Register; 0xFFFF98A3 *** ;*** TPM2MODH - TPM2 Timer Counter Modulo Register High; 0xFFFF98A3 *** TPM2MODH: .equ $FFFF98A3 ;*** TPM2MODH - TPM2 Timer Counter Modulo Register High; 0xFFFF98A3 *** ;*** TPM2MODL - TPM2 Timer Counter Modulo Register Low; 0xFFFF98A4 *** TPM2MODL: .equ $FFFF98A4 ;*** TPM2MODL - TPM2 Timer Counter Modulo Register Low; 0xFFFF98A4 *** ;*** TPM2C0SC - TPM2 Timer Channel 0 Status and Control Register; 0xFFFF98A5 *** TPM2C0SC: .equ $FFFF98A5 ;*** TPM2C0SC - TPM2 Timer Channel 0 Status and Control Register; 0xFFFF98A5 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPM2C0SC_ELS0A: .equ 2 ; Edge/Level Select Bit A TPM2C0SC_ELS0B: .equ 3 ; Edge/Level Select Bit B TPM2C0SC_MS0A: .equ 4 ; Mode Select A for TPM Channel 0 TPM2C0SC_MS0B: .equ 5 ; Mode Select B for TPM Channel 0 TPM2C0SC_CH0IE: .equ 6 ; Channel 0 Interrupt Enable TPM2C0SC_CH0F: .equ 7 ; Channel 0 Flag ; bit position masks mTPM2C0SC_ELS0A: .equ %00000100 mTPM2C0SC_ELS0B: .equ %00001000 mTPM2C0SC_MS0A: .equ %00010000 mTPM2C0SC_MS0B: .equ %00100000 mTPM2C0SC_CH0IE: .equ %01000000 mTPM2C0SC_CH0F: .equ %10000000 ;*** TPM2C0V - TPM2 Timer Channel 0 Value Register; 0xFFFF98A6 *** TPM2C0V: .equ $FFFF98A6 ;*** TPM2C0V - TPM2 Timer Channel 0 Value Register; 0xFFFF98A6 *** ;*** TPM2C0VH - TPM2 Timer Channel 0 Value Register High; 0xFFFF98A6 *** TPM2C0VH: .equ $FFFF98A6 ;*** TPM2C0VH - TPM2 Timer Channel 0 Value Register High; 0xFFFF98A6 *** ;*** TPM2C0VL - TPM2 Timer Channel 0 Value Register Low; 0xFFFF98A7 *** TPM2C0VL: .equ $FFFF98A7 ;*** TPM2C0VL - TPM2 Timer Channel 0 Value Register Low; 0xFFFF98A7 *** ;*** TPM2C1SC - TPM2 Timer Channel 1 Status and Control Register; 0xFFFF98A8 *** TPM2C1SC: .equ $FFFF98A8 ;*** TPM2C1SC - TPM2 Timer Channel 1 Status and Control Register; 0xFFFF98A8 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPM2C1SC_ELS1A: .equ 2 ; Edge/Level Select Bit A TPM2C1SC_ELS1B: .equ 3 ; Edge/Level Select Bit B TPM2C1SC_MS1A: .equ 4 ; Mode Select A for TPM Channel 1 TPM2C1SC_MS1B: .equ 5 ; Mode Select B for TPM Channel 1 TPM2C1SC_CH1IE: .equ 6 ; Channel 1 Interrupt Enable TPM2C1SC_CH1F: .equ 7 ; Channel 1 Flag ; bit position masks mTPM2C1SC_ELS1A: .equ %00000100 mTPM2C1SC_ELS1B: .equ %00001000 mTPM2C1SC_MS1A: .equ %00010000 mTPM2C1SC_MS1B: .equ %00100000 mTPM2C1SC_CH1IE: .equ %01000000 mTPM2C1SC_CH1F: .equ %10000000 ;*** TPM2C1V - TPM2 Timer Channel 1 Value Register; 0xFFFF98A9 *** TPM2C1V: .equ $FFFF98A9 ;*** TPM2C1V - TPM2 Timer Channel 1 Value Register; 0xFFFF98A9 *** ;*** TPM2C1VH - TPM2 Timer Channel 1 Value Register High; 0xFFFF98A9 *** TPM2C1VH: .equ $FFFF98A9 ;*** TPM2C1VH - TPM2 Timer Channel 1 Value Register High; 0xFFFF98A9 *** ;*** TPM2C1VL - TPM2 Timer Channel 1 Value Register Low; 0xFFFF98AA *** TPM2C1VL: .equ $FFFF98AA ;*** TPM2C1VL - TPM2 Timer Channel 1 Value Register Low; 0xFFFF98AA *** ;*** TPM2C2SC - TPM2 Timer Channel 2 Status and Control Register; 0xFFFF98AB *** TPM2C2SC: .equ $FFFF98AB ;*** TPM2C2SC - TPM2 Timer Channel 2 Status and Control Register; 0xFFFF98AB *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPM2C2SC_ELS2A: .equ 2 ; Edge/Level Select Bit A TPM2C2SC_ELS2B: .equ 3 ; Edge/Level Select Bit B TPM2C2SC_MS2A: .equ 4 ; Mode Select A for TPM Channel 2 TPM2C2SC_MS2B: .equ 5 ; Mode Select B for TPM Channel 2 TPM2C2SC_CH2IE: .equ 6 ; Channel 2 Interrupt Enable TPM2C2SC_CH2F: .equ 7 ; Channel 2 Flag ; bit position masks mTPM2C2SC_ELS2A: .equ %00000100 mTPM2C2SC_ELS2B: .equ %00001000 mTPM2C2SC_MS2A: .equ %00010000 mTPM2C2SC_MS2B: .equ %00100000 mTPM2C2SC_CH2IE: .equ %01000000 mTPM2C2SC_CH2F: .equ %10000000 ;*** TPM2C2V - TPM2 Timer Channel 2 Value Register; 0xFFFF98AC *** TPM2C2V: .equ $FFFF98AC ;*** TPM2C2V - TPM2 Timer Channel 2 Value Register; 0xFFFF98AC *** ;*** TPM2C2VH - TPM2 Timer Channel 2 Value Register High; 0xFFFF98AC *** TPM2C2VH: .equ $FFFF98AC ;*** TPM2C2VH - TPM2 Timer Channel 2 Value Register High; 0xFFFF98AC *** ;*** TPM2C2VL - TPM2 Timer Channel 2 Value Register Low; 0xFFFF98AD *** TPM2C2VL: .equ $FFFF98AD ;*** TPM2C2VL - TPM2 Timer Channel 2 Value Register Low; 0xFFFF98AD *** ;*** TPM2C3SC - TPM2 Timer Channel 3 Status and Control Register; 0xFFFF98AE *** TPM2C3SC: .equ $FFFF98AE ;*** TPM2C3SC - TPM2 Timer Channel 3 Status and Control Register; 0xFFFF98AE *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPM2C3SC_ELS3A: .equ 2 ; Edge/Level Select Bit A TPM2C3SC_ELS3B: .equ 3 ; Edge/Level Select Bit B TPM2C3SC_MS3A: .equ 4 ; Mode Select A for TPM Channel 3 TPM2C3SC_MS3B: .equ 5 ; Mode Select B for TPM Channel 3 TPM2C3SC_CH3IE: .equ 6 ; Channel 3 Interrupt Enable TPM2C3SC_CH3F: .equ 7 ; Channel 3 Flag ; bit position masks mTPM2C3SC_ELS3A: .equ %00000100 mTPM2C3SC_ELS3B: .equ %00001000 mTPM2C3SC_MS3A: .equ %00010000 mTPM2C3SC_MS3B: .equ %00100000 mTPM2C3SC_CH3IE: .equ %01000000 mTPM2C3SC_CH3F: .equ %10000000 ;*** TPM2C3V - TPM2 Timer Channel 3 Value Register; 0xFFFF98AF *** TPM2C3V: .equ $FFFF98AF ;*** TPM2C3V - TPM2 Timer Channel 3 Value Register; 0xFFFF98AF *** ;*** TPM2C3VH - TPM2 Timer Channel 3 Value Register High; 0xFFFF98AF *** TPM2C3VH: .equ $FFFF98AF ;*** TPM2C3VH - TPM2 Timer Channel 3 Value Register High; 0xFFFF98AF *** ;*** TPM2C3VL - TPM2 Timer Channel 3 Value Register Low; 0xFFFF98B0 *** TPM2C3VL: .equ $FFFF98B0 ;*** TPM2C3VL - TPM2 Timer Channel 3 Value Register Low; 0xFFFF98B0 *** ;*** SCI1BD - SCI1 Baud Rate Register; 0xFFFF98B8 *** SCI1BD: .equ $FFFF98B8 ;*** SCI1BD - SCI1 Baud Rate Register; 0xFFFF98B8 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1BD_SBR0: .equ 0 ; Baud Rate Modulo Divisor Bit 0 SCI1BD_SBR1: .equ 1 ; Baud Rate Modulo Divisor Bit 1 SCI1BD_SBR2: .equ 2 ; Baud Rate Modulo Divisor Bit 2 SCI1BD_SBR3: .equ 3 ; Baud Rate Modulo Divisor Bit 3 SCI1BD_SBR4: .equ 4 ; Baud Rate Modulo Divisor Bit 4 SCI1BD_SBR5: .equ 5 ; Baud Rate Modulo Divisor Bit 5 SCI1BD_SBR6: .equ 6 ; Baud Rate Modulo Divisor Bit 6 SCI1BD_SBR7: .equ 7 ; Baud Rate Modulo Divisor Bit 7 SCI1BD_SBR8: .equ 8 ; Baud Rate Modulo Divisor Bit 8 SCI1BD_SBR9: .equ 9 ; Baud Rate Modulo Divisor Bit 9 SCI1BD_SBR10: .equ 10 ; Baud Rate Modulo Divisor Bit 10 SCI1BD_SBR11: .equ 11 ; Baud Rate Modulo Divisor Bit 11 SCI1BD_SBR12: .equ 12 ; Baud Rate Modulo Divisor Bit 12 SCI1BD_RXEDGIE: .equ 14 ; RxD Input Active Edge Interrupt Enable (for RXEDGIF) SCI1BD_LBKDIE: .equ 15 ; LIN Break Detect Interrupt Enable (for LBKDIF) ; bit position masks mSCI1BD_SBR0: .equ %00000001 mSCI1BD_SBR1: .equ %00000010 mSCI1BD_SBR2: .equ %00000100 mSCI1BD_SBR3: .equ %00001000 mSCI1BD_SBR4: .equ %00010000 mSCI1BD_SBR5: .equ %00100000 mSCI1BD_SBR6: .equ %01000000 mSCI1BD_SBR7: .equ %10000000 mSCI1BD_SBR8: .equ %100000000 mSCI1BD_SBR9: .equ %1000000000 mSCI1BD_SBR10: .equ %10000000000 mSCI1BD_SBR11: .equ %100000000000 mSCI1BD_SBR12: .equ %1000000000000 mSCI1BD_RXEDGIE: .equ %100000000000000 mSCI1BD_LBKDIE: .equ %1000000000000000 ;*** SCI1BDH - SCI1 Baud Rate Register High; 0xFFFF98B8 *** SCI1BDH: .equ $FFFF98B8 ;*** SCI1BDH - SCI1 Baud Rate Register High; 0xFFFF98B8 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1BDH_SBR8: .equ 0 ; Baud Rate Modulo Divisor Bit 8 SCI1BDH_SBR9: .equ 1 ; Baud Rate Modulo Divisor Bit 9 SCI1BDH_SBR10: .equ 2 ; Baud Rate Modulo Divisor Bit 10 SCI1BDH_SBR11: .equ 3 ; Baud Rate Modulo Divisor Bit 11 SCI1BDH_SBR12: .equ 4 ; Baud Rate Modulo Divisor Bit 12 SCI1BDH_RXEDGIE: .equ 6 ; RxD Input Active Edge Interrupt Enable (for RXEDGIF) SCI1BDH_LBKDIE: .equ 7 ; LIN Break Detect Interrupt Enable (for LBKDIF) ; bit position masks mSCI1BDH_SBR8: .equ %00000001 mSCI1BDH_SBR9: .equ %00000010 mSCI1BDH_SBR10: .equ %00000100 mSCI1BDH_SBR11: .equ %00001000 mSCI1BDH_SBR12: .equ %00010000 mSCI1BDH_RXEDGIE: .equ %01000000 mSCI1BDH_LBKDIE: .equ %10000000 ;*** SCI1BDL - SCI1 Baud Rate Register Low; 0xFFFF98B9 *** SCI1BDL: .equ $FFFF98B9 ;*** SCI1BDL - SCI1 Baud Rate Register Low; 0xFFFF98B9 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1BDL_SBR0: .equ 0 ; Baud Rate Modulo Divisor Bit 0 SCI1BDL_SBR1: .equ 1 ; Baud Rate Modulo Divisor Bit 1 SCI1BDL_SBR2: .equ 2 ; Baud Rate Modulo Divisor Bit 2 SCI1BDL_SBR3: .equ 3 ; Baud Rate Modulo Divisor Bit 3 SCI1BDL_SBR4: .equ 4 ; Baud Rate Modulo Divisor Bit 4 SCI1BDL_SBR5: .equ 5 ; Baud Rate Modulo Divisor Bit 5 SCI1BDL_SBR6: .equ 6 ; Baud Rate Modulo Divisor Bit 6 SCI1BDL_SBR7: .equ 7 ; Baud Rate Modulo Divisor Bit 7 ; bit position masks mSCI1BDL_SBR0: .equ %00000001 mSCI1BDL_SBR1: .equ %00000010 mSCI1BDL_SBR2: .equ %00000100 mSCI1BDL_SBR3: .equ %00001000 mSCI1BDL_SBR4: .equ %00010000 mSCI1BDL_SBR5: .equ %00100000 mSCI1BDL_SBR6: .equ %01000000 mSCI1BDL_SBR7: .equ %10000000 ;*** SCI1C1 - SCI1 Control Register 1; 0xFFFF98BA *** SCI1C1: .equ $FFFF98BA ;*** SCI1C1 - SCI1 Control Register 1; 0xFFFF98BA *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1C1_PT: .equ 0 ; Parity Type SCI1C1_PE: .equ 1 ; Parity Enable SCI1C1_ILT: .equ 2 ; Idle Line Type Select SCI1C1_WAKE: .equ 3 ; Receiver Wakeup Method Select SCI1C1_M: .equ 4 ; 9-Bit or 8-Bit Mode Select SCI1C1_RSRC: .equ 5 ; Receiver Source Select SCI1C1_SCISWAI: .equ 6 ; SCI Stops in Wait Mode SCI1C1_LOOPS: .equ 7 ; Loop Mode Select ; bit position masks mSCI1C1_PT: .equ %00000001 mSCI1C1_PE: .equ %00000010 mSCI1C1_ILT: .equ %00000100 mSCI1C1_WAKE: .equ %00001000 mSCI1C1_M: .equ %00010000 mSCI1C1_RSRC: .equ %00100000 mSCI1C1_SCISWAI: .equ %01000000 mSCI1C1_LOOPS: .equ %10000000 ;*** SCI1C2 - SCI1 Control Register 2; 0xFFFF98BB *** SCI1C2: .equ $FFFF98BB ;*** SCI1C2 - SCI1 Control Register 2; 0xFFFF98BB *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1C2_SBK: .equ 0 ; Send Break SCI1C2_RWU: .equ 1 ; Receiver Wakeup Control SCI1C2_RE: .equ 2 ; Receiver Enable SCI1C2_TE: .equ 3 ; Transmitter Enable SCI1C2_ILIE: .equ 4 ; Idle Line Interrupt Enable (for IDLE) SCI1C2_RIE: .equ 5 ; Receiver Interrupt Enable (for RDRF) SCI1C2_TCIE: .equ 6 ; Transmission Complete Interrupt Enable (for TC) SCI1C2_TIE: .equ 7 ; Transmit Interrupt Enable (for TDRE) ; bit position masks mSCI1C2_SBK: .equ %00000001 mSCI1C2_RWU: .equ %00000010 mSCI1C2_RE: .equ %00000100 mSCI1C2_TE: .equ %00001000 mSCI1C2_ILIE: .equ %00010000 mSCI1C2_RIE: .equ %00100000 mSCI1C2_TCIE: .equ %01000000 mSCI1C2_TIE: .equ %10000000 ;*** SCI1S1 - SCI1 Status Register 1; 0xFFFF98BC *** SCI1S1: .equ $FFFF98BC ;*** SCI1S1 - SCI1 Status Register 1; 0xFFFF98BC *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1S1_PF: .equ 0 ; Parity Error Flag SCI1S1_FE: .equ 1 ; Framing Error Flag SCI1S1_NF: .equ 2 ; Noise Flag SCI1S1_OR: .equ 3 ; Receiver Overrun Flag SCI1S1_IDLE: .equ 4 ; Idle Line Flag SCI1S1_RDRF: .equ 5 ; Receive Data Register Full Flag SCI1S1_TC: .equ 6 ; Transmission Complete Flag SCI1S1_TDRE: .equ 7 ; Transmit Data Register Empty Flag ; bit position masks mSCI1S1_PF: .equ %00000001 mSCI1S1_FE: .equ %00000010 mSCI1S1_NF: .equ %00000100 mSCI1S1_OR: .equ %00001000 mSCI1S1_IDLE: .equ %00010000 mSCI1S1_RDRF: .equ %00100000 mSCI1S1_TC: .equ %01000000 mSCI1S1_TDRE: .equ %10000000 ;*** SCI1S2 - SCI1 Status Register 2; 0xFFFF98BD *** SCI1S2: .equ $FFFF98BD ;*** SCI1S2 - SCI1 Status Register 2; 0xFFFF98BD *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1S2_RAF: .equ 0 ; Receiver Active Flag SCI1S2_LBKDE: .equ 1 ; LIN Break Detection Enable SCI1S2_BRK13: .equ 2 ; Break Character Generation Length SCI1S2_RWUID: .equ 3 ; Receive Wake Up Idle Detect SCI1S2_RXINV: .equ 4 ; Receive Data Inversion SCI1S2_RXEDGIF: .equ 6 ; RxD Pin Active Edge Interrupt Flag SCI1S2_LBKDIF: .equ 7 ; LIN Break Detect Interrupt Flag ; bit position masks mSCI1S2_RAF: .equ %00000001 mSCI1S2_LBKDE: .equ %00000010 mSCI1S2_BRK13: .equ %00000100 mSCI1S2_RWUID: .equ %00001000 mSCI1S2_RXINV: .equ %00010000 mSCI1S2_RXEDGIF: .equ %01000000 mSCI1S2_LBKDIF: .equ %10000000 ;*** SCI1C3 - SCI1 Control Register 3; 0xFFFF98BE *** SCI1C3: .equ $FFFF98BE ;*** SCI1C3 - SCI1 Control Register 3; 0xFFFF98BE *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1C3_PEIE: .equ 0 ; Parity Error Interrupt Enable SCI1C3_FEIE: .equ 1 ; Framing Error Interrupt Enable SCI1C3_NEIE: .equ 2 ; Noise Error Interrupt Enable SCI1C3_ORIE: .equ 3 ; Overrun Interrupt Enable SCI1C3_TXINV: .equ 4 ; Transmit Data Inversion SCI1C3_TXDIR: .equ 5 ; TxD Pin Direction in Single-Wire Mode SCI1C3_T8: .equ 6 ; Ninth Data Bit for Transmitter SCI1C3_R8: .equ 7 ; Ninth Data Bit for Receiver ; bit position masks mSCI1C3_PEIE: .equ %00000001 mSCI1C3_FEIE: .equ %00000010 mSCI1C3_NEIE: .equ %00000100 mSCI1C3_ORIE: .equ %00001000 mSCI1C3_TXINV: .equ %00010000 mSCI1C3_TXDIR: .equ %00100000 mSCI1C3_T8: .equ %01000000 mSCI1C3_R8: .equ %10000000 ;*** SCI1D - SCI1 Data Register; 0xFFFF98BF *** SCI1D: .equ $FFFF98BF ;*** SCI1D - SCI1 Data Register; 0xFFFF98BF *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1D_R0_T0: .equ 0 ; Receive/Transmit Data Bit 0 SCI1D_R1_T1: .equ 1 ; Receive/Transmit Data Bit 1 SCI1D_R2_T2: .equ 2 ; Receive/Transmit Data Bit 2 SCI1D_R3_T3: .equ 3 ; Receive/Transmit Data Bit 3 SCI1D_R4_T4: .equ 4 ; Receive/Transmit Data Bit 4 SCI1D_R5_T5: .equ 5 ; Receive/Transmit Data Bit 5 SCI1D_R6_T6: .equ 6 ; Receive/Transmit Data Bit 6 SCI1D_R7_T7: .equ 7 ; Receive/Transmit Data Bit 7 ; bit position masks mSCI1D_R0_T0: .equ %00000001 mSCI1D_R1_T1: .equ %00000010 mSCI1D_R2_T2: .equ %00000100 mSCI1D_R3_T3: .equ %00001000 mSCI1D_R4_T4: .equ %00010000 mSCI1D_R5_T5: .equ %00100000 mSCI1D_R6_T6: .equ %01000000 mSCI1D_R7_T7: .equ %10000000 ;*** PDBSC - PDB Status and Control Register; 0xFFFF98C0 *** PDBSC: .equ $FFFF98C0 ;*** PDBSC - PDB Status and Control Register; 0xFFFF98C0 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PDBSC_LDOK: .equ 0 ; Load OK PDBSC_DACTOE: .equ 1 ; DAC Trigger Output Enable PDBSC_TOS0: .equ 2 ; Trigger Output Select, bit 0 PDBSC_TOS1: .equ 3 ; Trigger Output Select, bit 1 PDBSC_LDMOD: .equ 4 ; Load Mode Select PDBSC_PDBIE: .equ 5 ; PDB Interrupt Enable PDBSC_PDBIF: .equ 6 ; PDB Interrupt Flag PDBSC_PDBEN: .equ 7 ; PDB module Enable ; bit position masks mPDBSC_LDOK: .equ %00000001 mPDBSC_DACTOE: .equ %00000010 mPDBSC_TOS0: .equ %00000100 mPDBSC_TOS1: .equ %00001000 mPDBSC_LDMOD: .equ %00010000 mPDBSC_PDBIE: .equ %00100000 mPDBSC_PDBIF: .equ %01000000 mPDBSC_PDBEN: .equ %10000000 ;*** PDBC1 - PDB Control Register 1; 0xFFFF98C1 *** PDBC1: .equ $FFFF98C1 ;*** PDBC1 - PDB Control Register 1; 0xFFFF98C1 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PDBC1_MULT: .equ 0 ; Multiply prescaler bit PDBC1_CONT: .equ 1 ; Continuous Mode Enable PDBC1_TRIGSEL0: .equ 2 ; Input Trigger Select, bit 0 PDBC1_TRIGSEL1: .equ 3 ; Input Trigger Select, bit 1 PDBC1_TRIGSEL2: .equ 4 ; Input Trigger Select, bit 2 PDBC1_PRESCALER0: .equ 5 ; Clock Prescaler Select, bit 0 PDBC1_PRESCALER1: .equ 6 ; Clock Prescaler Select, bit 1 PDBC1_PRESCALER2: .equ 7 ; Clock Prescaler Select, bit 2 ; bit position masks mPDBC1_MULT: .equ %00000001 mPDBC1_CONT: .equ %00000010 mPDBC1_TRIGSEL0: .equ %00000100 mPDBC1_TRIGSEL1: .equ %00001000 mPDBC1_TRIGSEL2: .equ %00010000 mPDBC1_PRESCALER0: .equ %00100000 mPDBC1_PRESCALER1: .equ %01000000 mPDBC1_PRESCALER2: .equ %10000000 ;*** PDBC2 - PDB Control Register 2; 0xFFFF98C2 *** PDBC2: .equ $FFFF98C2 ;*** PDBC2 - PDB Control Register 2; 0xFFFF98C2 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PDBC2_SWTRIG: .equ 0 ; SoftwareTrigger ; bit position masks mPDBC2_SWTRIG: .equ %00000001 ;*** PDBCHEN - PDB Channel Enable; 0xFFFF98C3 *** PDBCHEN: .equ $FFFF98C3 ;*** PDBCHEN - PDB Channel Enable; 0xFFFF98C3 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PDBCHEN_CHEN0: .equ 0 ; PDB channel enable, bit 0 ; bit position masks mPDBCHEN_CHEN0: .equ %00000001 ;*** PDBMOD - PDB Modulus Register; 0xFFFF98C4 *** PDBMOD: .equ $FFFF98C4 ;*** PDBMOD - PDB Modulus Register; 0xFFFF98C4 *** ;*** PDBMODH - PDB Modulus Register High; 0xFFFF98C4 *** PDBMODH: .equ $FFFF98C4 ;*** PDBMODH - PDB Modulus Register High; 0xFFFF98C4 *** ;*** PDBMODL - PDB Modulus Register Low; 0xFFFF98C5 *** PDBMODL: .equ $FFFF98C5 ;*** PDBMODL - PDB Modulus Register Low; 0xFFFF98C5 *** ;*** PDBCNT - PDB Counter Register; 0xFFFF98C6 *** PDBCNT: .equ $FFFF98C6 ;*** PDBCNT - PDB Counter Register; 0xFFFF98C6 *** ;*** PDBCNTH - PDB Counter Register High; 0xFFFF98C6 *** PDBCNTH: .equ $FFFF98C6 ;*** PDBCNTH - PDB Counter Register High; 0xFFFF98C6 *** ;*** PDBCNTL - PDB Counter Register Low; 0xFFFF98C7 *** PDBCNTL: .equ $FFFF98C7 ;*** PDBCNTL - PDB Counter Register Low; 0xFFFF98C7 *** ;*** PDBIDLY - PDB Interrupt Delay Register; 0xFFFF98C8 *** PDBIDLY: .equ $FFFF98C8 ;*** PDBIDLY - PDB Interrupt Delay Register; 0xFFFF98C8 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PDBIDLY_IDELAY0: .equ 0 ; Interrupt Delay, bit 0 PDBIDLY_IDELAY1: .equ 1 ; Interrupt Delay, bit 1 PDBIDLY_IDELAY2: .equ 2 ; Interrupt Delay, bit 2 PDBIDLY_IDELAY3: .equ 3 ; Interrupt Delay, bit 3 PDBIDLY_IDELAY4: .equ 4 ; Interrupt Delay, bit 4 PDBIDLY_IDELAY5: .equ 5 ; Interrupt Delay, bit 5 PDBIDLY_IDELAY6: .equ 6 ; Interrupt Delay, bit 6 PDBIDLY_IDELAY7: .equ 7 ; Interrupt Delay, bit 7 PDBIDLY_IDELAY8: .equ 8 ; Interrupt Delay, bit 8 PDBIDLY_IDELAY9: .equ 9 ; Interrupt Delay, bit 9 PDBIDLY_IDELAY10: .equ 10 ; Interrupt Delay, bit 10 PDBIDLY_IDELAY11: .equ 11 ; Interrupt Delay, bit 11 PDBIDLY_IDELAY12: .equ 12 ; Interrupt Delay, bit 12 PDBIDLY_IDELAY13: .equ 13 ; Interrupt Delay, bit 13 PDBIDLY_IDELAY14: .equ 14 ; Interrupt Delay, bit 14 PDBIDLY_IDELAY15: .equ 15 ; Interrupt Delay, bit 15 ; bit position masks mPDBIDLY_IDELAY0: .equ %00000001 mPDBIDLY_IDELAY1: .equ %00000010 mPDBIDLY_IDELAY2: .equ %00000100 mPDBIDLY_IDELAY3: .equ %00001000 mPDBIDLY_IDELAY4: .equ %00010000 mPDBIDLY_IDELAY5: .equ %00100000 mPDBIDLY_IDELAY6: .equ %01000000 mPDBIDLY_IDELAY7: .equ %10000000 mPDBIDLY_IDELAY8: .equ %100000000 mPDBIDLY_IDELAY9: .equ %1000000000 mPDBIDLY_IDELAY10: .equ %10000000000 mPDBIDLY_IDELAY11: .equ %100000000000 mPDBIDLY_IDELAY12: .equ %1000000000000 mPDBIDLY_IDELAY13: .equ %10000000000000 mPDBIDLY_IDELAY14: .equ %100000000000000 mPDBIDLY_IDELAY15: .equ %1000000000000000 ;*** PDBIDLYH - PDB Interrupt Delay Register High; 0xFFFF98C8 *** PDBIDLYH: .equ $FFFF98C8 ;*** PDBIDLYH - PDB Interrupt Delay Register High; 0xFFFF98C8 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PDBIDLYH_IDELAY8: .equ 0 ; Interrupt Delay, bit 8 PDBIDLYH_IDELAY9: .equ 1 ; Interrupt Delay, bit 9 PDBIDLYH_IDELAY10: .equ 2 ; Interrupt Delay, bit 10 PDBIDLYH_IDELAY11: .equ 3 ; Interrupt Delay, bit 11 PDBIDLYH_IDELAY12: .equ 4 ; Interrupt Delay, bit 12 PDBIDLYH_IDELAY13: .equ 5 ; Interrupt Delay, bit 13 PDBIDLYH_IDELAY14: .equ 6 ; Interrupt Delay, bit 14 PDBIDLYH_IDELAY15: .equ 7 ; Interrupt Delay, bit 15 ; bit position masks mPDBIDLYH_IDELAY8: .equ %00000001 mPDBIDLYH_IDELAY9: .equ %00000010 mPDBIDLYH_IDELAY10: .equ %00000100 mPDBIDLYH_IDELAY11: .equ %00001000 mPDBIDLYH_IDELAY12: .equ %00010000 mPDBIDLYH_IDELAY13: .equ %00100000 mPDBIDLYH_IDELAY14: .equ %01000000 mPDBIDLYH_IDELAY15: .equ %10000000 ;*** PDBIDLYL - PDB Interrupt Delay Register Low; 0xFFFF98C9 *** PDBIDLYL: .equ $FFFF98C9 ;*** PDBIDLYL - PDB Interrupt Delay Register Low; 0xFFFF98C9 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PDBIDLYL_IDELAY0: .equ 0 ; Interrupt Delay, bit 0 PDBIDLYL_IDELAY1: .equ 1 ; Interrupt Delay, bit 1 PDBIDLYL_IDELAY2: .equ 2 ; Interrupt Delay, bit 2 PDBIDLYL_IDELAY3: .equ 3 ; Interrupt Delay, bit 3 PDBIDLYL_IDELAY4: .equ 4 ; Interrupt Delay, bit 4 PDBIDLYL_IDELAY5: .equ 5 ; Interrupt Delay, bit 5 PDBIDLYL_IDELAY6: .equ 6 ; Interrupt Delay, bit 6 PDBIDLYL_IDELAY7: .equ 7 ; Interrupt Delay, bit 7 ; bit position masks mPDBIDLYL_IDELAY0: .equ %00000001 mPDBIDLYL_IDELAY1: .equ %00000010 mPDBIDLYL_IDELAY2: .equ %00000100 mPDBIDLYL_IDELAY3: .equ %00001000 mPDBIDLYL_IDELAY4: .equ %00010000 mPDBIDLYL_IDELAY5: .equ %00100000 mPDBIDLYL_IDELAY6: .equ %01000000 mPDBIDLYL_IDELAY7: .equ %10000000 ;*** DACINT - DAC Trigger Interval Register; 0xFFFF98CA *** DACINT: .equ $FFFF98CA ;*** DACINT - DAC Trigger Interval Register; 0xFFFF98CA *** ;*** DACINTH - DAC Trigger Interval Register High; 0xFFFF98CA *** DACINTH: .equ $FFFF98CA ;*** DACINTH - DAC Trigger Interval Register High; 0xFFFF98CA *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACINTH_DACINT8: .equ 0 ; DAC Interval, bit 8 DACINTH_DACINT9: .equ 1 ; DAC Interval, bit 9 DACINTH_DACINT10: .equ 2 ; DAC Interval, bit 10 DACINTH_DACINT11: .equ 3 ; DAC Interval, bit 11 DACINTH_DACINT12: .equ 4 ; DAC Interval, bit 12 DACINTH_DACINT13: .equ 5 ; DAC Interval, bit 13 DACINTH_DACINT14: .equ 6 ; DAC Interval, bit 14 DACINTH_DACINT15: .equ 7 ; DAC Interval, bit 15 ; bit position masks mDACINTH_DACINT8: .equ %00000001 mDACINTH_DACINT9: .equ %00000010 mDACINTH_DACINT10: .equ %00000100 mDACINTH_DACINT11: .equ %00001000 mDACINTH_DACINT12: .equ %00010000 mDACINTH_DACINT13: .equ %00100000 mDACINTH_DACINT14: .equ %01000000 mDACINTH_DACINT15: .equ %10000000 ;*** DACINTL - DAC Trigger Interval Register Low; 0xFFFF98CB *** DACINTL: .equ $FFFF98CB ;*** DACINTL - DAC Trigger Interval Register Low; 0xFFFF98CB *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DACINTL_DACINT0: .equ 0 ; DAC Interval, bit 0 DACINTL_DACINT1: .equ 1 ; DAC Interval, bit 1 DACINTL_DACINT2: .equ 2 ; DAC Interval, bit 2 DACINTL_DACINT3: .equ 3 ; DAC Interval, bit 3 DACINTL_DACINT4: .equ 4 ; DAC Interval, bit 4 DACINTL_DACINT5: .equ 5 ; DAC Interval, bit 5 DACINTL_DACINT6: .equ 6 ; DAC Interval, bit 6 DACINTL_DACINT7: .equ 7 ; DAC Interval, bit 7 ; bit position masks mDACINTL_DACINT0: .equ %00000001 mDACINTL_DACINT1: .equ %00000010 mDACINTL_DACINT2: .equ %00000100 mDACINTL_DACINT3: .equ %00001000 mDACINTL_DACINT4: .equ %00010000 mDACINTL_DACINT5: .equ %00100000 mDACINTL_DACINT6: .equ %01000000 mDACINTL_DACINT7: .equ %10000000 ;*** PDBDLY - PDB Delay A Register; 0xFFFF98CC *** PDBDLY: .equ $FFFF98CC ;*** PDBDLY - PDB Delay A Register; 0xFFFF98CC *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PDBDLY_DELAY0: .equ 0 ; Delay, bit 0 PDBDLY_DELAY1: .equ 1 ; Delay, bit 1 PDBDLY_DELAY2: .equ 2 ; Delay, bit 2 PDBDLY_DELAY3: .equ 3 ; Delay, bit 3 PDBDLY_DELAY4: .equ 4 ; Delay, bit 4 PDBDLY_DELAY5: .equ 5 ; Delay, bit 5 PDBDLY_DELAY6: .equ 6 ; Delay, bit 6 PDBDLY_DELAY7: .equ 7 ; Delay, bit 7 PDBDLY_DELAY8: .equ 8 ; Delay, bit 8 PDBDLY_DELAY9: .equ 9 ; Delay, bit 9 PDBDLY_DELAY10: .equ 10 ; Delay, bit 10 PDBDLY_DELAY11: .equ 11 ; Delay, bit 11 PDBDLY_DELAY12: .equ 12 ; Delay, bit 12 PDBDLY_DELAY13: .equ 13 ; Delay, bit 13 PDBDLY_DELAY14: .equ 14 ; Delay, bit 14 PDBDLY_DELAY15: .equ 15 ; Delay, bit 15 ; bit position masks mPDBDLY_DELAY0: .equ %00000001 mPDBDLY_DELAY1: .equ %00000010 mPDBDLY_DELAY2: .equ %00000100 mPDBDLY_DELAY3: .equ %00001000 mPDBDLY_DELAY4: .equ %00010000 mPDBDLY_DELAY5: .equ %00100000 mPDBDLY_DELAY6: .equ %01000000 mPDBDLY_DELAY7: .equ %10000000 mPDBDLY_DELAY8: .equ %100000000 mPDBDLY_DELAY9: .equ %1000000000 mPDBDLY_DELAY10: .equ %10000000000 mPDBDLY_DELAY11: .equ %100000000000 mPDBDLY_DELAY12: .equ %1000000000000 mPDBDLY_DELAY13: .equ %10000000000000 mPDBDLY_DELAY14: .equ %100000000000000 mPDBDLY_DELAY15: .equ %1000000000000000 ;*** PDBDLYH - PDB Delay A Register High; 0xFFFF98CC *** PDBDLYH: .equ $FFFF98CC ;*** PDBDLYH - PDB Delay A Register High; 0xFFFF98CC *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PDBDLYH_DELAY8: .equ 0 ; Delay, bit 8 PDBDLYH_DELAY9: .equ 1 ; Delay, bit 9 PDBDLYH_DELAY10: .equ 2 ; Delay, bit 10 PDBDLYH_DELAY11: .equ 3 ; Delay, bit 11 PDBDLYH_DELAY12: .equ 4 ; Delay, bit 12 PDBDLYH_DELAY13: .equ 5 ; Delay, bit 13 PDBDLYH_DELAY14: .equ 6 ; Delay, bit 14 PDBDLYH_DELAY15: .equ 7 ; Delay, bit 15 ; bit position masks mPDBDLYH_DELAY8: .equ %00000001 mPDBDLYH_DELAY9: .equ %00000010 mPDBDLYH_DELAY10: .equ %00000100 mPDBDLYH_DELAY11: .equ %00001000 mPDBDLYH_DELAY12: .equ %00010000 mPDBDLYH_DELAY13: .equ %00100000 mPDBDLYH_DELAY14: .equ %01000000 mPDBDLYH_DELAY15: .equ %10000000 ;*** PDBDLYL - PDB Delay A Register Low; 0xFFFF98CD *** PDBDLYL: .equ $FFFF98CD ;*** PDBDLYL - PDB Delay A Register Low; 0xFFFF98CD *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PDBDLYL_DELAY0: .equ 0 ; Delay, bit 0 PDBDLYL_DELAY1: .equ 1 ; Delay, bit 1 PDBDLYL_DELAY2: .equ 2 ; Delay, bit 2 PDBDLYL_DELAY3: .equ 3 ; Delay, bit 3 PDBDLYL_DELAY4: .equ 4 ; Delay, bit 4 PDBDLYL_DELAY5: .equ 5 ; Delay, bit 5 PDBDLYL_DELAY6: .equ 6 ; Delay, bit 6 PDBDLYL_DELAY7: .equ 7 ; Delay, bit 7 ; bit position masks mPDBDLYL_DELAY0: .equ %00000001 mPDBDLYL_DELAY1: .equ %00000010 mPDBDLYL_DELAY2: .equ %00000100 mPDBDLYL_DELAY3: .equ %00001000 mPDBDLYL_DELAY4: .equ %00010000 mPDBDLYL_DELAY5: .equ %00100000 mPDBDLYL_DELAY6: .equ %01000000 mPDBDLYL_DELAY7: .equ %10000000 ;*** TPM1SC - TPM1 Status and Control Register; 0xFFFF98E0 *** TPM1SC: .equ $FFFF98E0 ;*** TPM1SC - TPM1 Status and Control Register; 0xFFFF98E0 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPM1SC_PS0: .equ 0 ; Prescale Divisor Select Bit 0 TPM1SC_PS1: .equ 1 ; Prescale Divisor Select Bit 1 TPM1SC_PS2: .equ 2 ; Prescale Divisor Select Bit 2 TPM1SC_CLKSA: .equ 3 ; Clock Source Select A TPM1SC_CLKSB: .equ 4 ; Clock Source Select B TPM1SC_CPWMS: .equ 5 ; Center-Aligned PWM Select TPM1SC_TOIE: .equ 6 ; Timer Overflow Interrupt Enable TPM1SC_TOF: .equ 7 ; Timer Overflow Flag ; bit position masks mTPM1SC_PS0: .equ %00000001 mTPM1SC_PS1: .equ %00000010 mTPM1SC_PS2: .equ %00000100 mTPM1SC_CLKSA: .equ %00001000 mTPM1SC_CLKSB: .equ %00010000 mTPM1SC_CPWMS: .equ %00100000 mTPM1SC_TOIE: .equ %01000000 mTPM1SC_TOF: .equ %10000000 ;*** TPM1CNT - TPM1 Timer Counter Register; 0xFFFF98E1 *** TPM1CNT: .equ $FFFF98E1 ;*** TPM1CNT - TPM1 Timer Counter Register; 0xFFFF98E1 *** ;*** TPM1CNTH - TPM1 Timer Counter Register High; 0xFFFF98E1 *** TPM1CNTH: .equ $FFFF98E1 ;*** TPM1CNTH - TPM1 Timer Counter Register High; 0xFFFF98E1 *** ;*** TPM1CNTL - TPM1 Timer Counter Register Low; 0xFFFF98E2 *** TPM1CNTL: .equ $FFFF98E2 ;*** TPM1CNTL - TPM1 Timer Counter Register Low; 0xFFFF98E2 *** ;*** TPM1MOD - TPM1 Timer Counter Modulo Register; 0xFFFF98E3 *** TPM1MOD: .equ $FFFF98E3 ;*** TPM1MOD - TPM1 Timer Counter Modulo Register; 0xFFFF98E3 *** ;*** TPM1MODH - TPM1 Timer Counter Modulo Register High; 0xFFFF98E3 *** TPM1MODH: .equ $FFFF98E3 ;*** TPM1MODH - TPM1 Timer Counter Modulo Register High; 0xFFFF98E3 *** ;*** TPM1MODL - TPM1 Timer Counter Modulo Register Low; 0xFFFF98E4 *** TPM1MODL: .equ $FFFF98E4 ;*** TPM1MODL - TPM1 Timer Counter Modulo Register Low; 0xFFFF98E4 *** ;*** TPM1C0SC - TPM1 Timer Channel 0 Status and Control Register; 0xFFFF98E5 *** TPM1C0SC: .equ $FFFF98E5 ;*** TPM1C0SC - TPM1 Timer Channel 0 Status and Control Register; 0xFFFF98E5 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPM1C0SC_ELS0A: .equ 2 ; Edge/Level Select Bit A TPM1C0SC_ELS0B: .equ 3 ; Edge/Level Select Bit B TPM1C0SC_MS0A: .equ 4 ; Mode Select A for TPM Channel 0 TPM1C0SC_MS0B: .equ 5 ; Mode Select B for TPM Channel 0 TPM1C0SC_CH0IE: .equ 6 ; Channel 0 Interrupt Enable TPM1C0SC_CH0F: .equ 7 ; Channel 0 Flag ; bit position masks mTPM1C0SC_ELS0A: .equ %00000100 mTPM1C0SC_ELS0B: .equ %00001000 mTPM1C0SC_MS0A: .equ %00010000 mTPM1C0SC_MS0B: .equ %00100000 mTPM1C0SC_CH0IE: .equ %01000000 mTPM1C0SC_CH0F: .equ %10000000 ;*** TPM1C0V - TPM1 Timer Channel 0 Value Register; 0xFFFF98E6 *** TPM1C0V: .equ $FFFF98E6 ;*** TPM1C0V - TPM1 Timer Channel 0 Value Register; 0xFFFF98E6 *** ;*** TPM1C0VH - TPM1 Timer Channel 0 Value Register High; 0xFFFF98E6 *** TPM1C0VH: .equ $FFFF98E6 ;*** TPM1C0VH - TPM1 Timer Channel 0 Value Register High; 0xFFFF98E6 *** ;*** TPM1C0VL - TPM1 Timer Channel 0 Value Register Low; 0xFFFF98E7 *** TPM1C0VL: .equ $FFFF98E7 ;*** TPM1C0VL - TPM1 Timer Channel 0 Value Register Low; 0xFFFF98E7 *** ;*** TPM1C1SC - TPM1 Timer Channel 1 Status and Control Register; 0xFFFF98E8 *** TPM1C1SC: .equ $FFFF98E8 ;*** TPM1C1SC - TPM1 Timer Channel 1 Status and Control Register; 0xFFFF98E8 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPM1C1SC_ELS1A: .equ 2 ; Edge/Level Select Bit A TPM1C1SC_ELS1B: .equ 3 ; Edge/Level Select Bit B TPM1C1SC_MS1A: .equ 4 ; Mode Select A for TPM Channel 1 TPM1C1SC_MS1B: .equ 5 ; Mode Select B for TPM Channel 1 TPM1C1SC_CH1IE: .equ 6 ; Channel 1 Interrupt Enable TPM1C1SC_CH1F: .equ 7 ; Channel 1 Flag ; bit position masks mTPM1C1SC_ELS1A: .equ %00000100 mTPM1C1SC_ELS1B: .equ %00001000 mTPM1C1SC_MS1A: .equ %00010000 mTPM1C1SC_MS1B: .equ %00100000 mTPM1C1SC_CH1IE: .equ %01000000 mTPM1C1SC_CH1F: .equ %10000000 ;*** TPM1C1V - TPM1 Timer Channel 1 Value Register; 0xFFFF98E9 *** TPM1C1V: .equ $FFFF98E9 ;*** TPM1C1V - TPM1 Timer Channel 1 Value Register; 0xFFFF98E9 *** ;*** TPM1C1VH - TPM1 Timer Channel 1 Value Register High; 0xFFFF98E9 *** TPM1C1VH: .equ $FFFF98E9 ;*** TPM1C1VH - TPM1 Timer Channel 1 Value Register High; 0xFFFF98E9 *** ;*** TPM1C1VL - TPM1 Timer Channel 1 Value Register Low; 0xFFFF98EA *** TPM1C1VL: .equ $FFFF98EA ;*** TPM1C1VL - TPM1 Timer Channel 1 Value Register Low; 0xFFFF98EA *** ;*** TPM1C2SC - TPM1 Timer Channel 2 Status and Control Register; 0xFFFF98EB *** TPM1C2SC: .equ $FFFF98EB ;*** TPM1C2SC - TPM1 Timer Channel 2 Status and Control Register; 0xFFFF98EB *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPM1C2SC_ELS2A: .equ 2 ; Edge/Level Select Bit A TPM1C2SC_ELS2B: .equ 3 ; Edge/Level Select Bit B TPM1C2SC_MS2A: .equ 4 ; Mode Select A for TPM Channel 2 TPM1C2SC_MS2B: .equ 5 ; Mode Select B for TPM Channel 2 TPM1C2SC_CH2IE: .equ 6 ; Channel 2 Interrupt Enable TPM1C2SC_CH2F: .equ 7 ; Channel 2 Flag ; bit position masks mTPM1C2SC_ELS2A: .equ %00000100 mTPM1C2SC_ELS2B: .equ %00001000 mTPM1C2SC_MS2A: .equ %00010000 mTPM1C2SC_MS2B: .equ %00100000 mTPM1C2SC_CH2IE: .equ %01000000 mTPM1C2SC_CH2F: .equ %10000000 ;*** TPM1C2V - TPM1 Timer Channel 2 Value Register; 0xFFFF98EC *** TPM1C2V: .equ $FFFF98EC ;*** TPM1C2V - TPM1 Timer Channel 2 Value Register; 0xFFFF98EC *** ;*** TPM1C2VH - TPM1 Timer Channel 2 Value Register High; 0xFFFF98EC *** TPM1C2VH: .equ $FFFF98EC ;*** TPM1C2VH - TPM1 Timer Channel 2 Value Register High; 0xFFFF98EC *** ;*** TPM1C2VL - TPM1 Timer Channel 2 Value Register Low; 0xFFFF98ED *** TPM1C2VL: .equ $FFFF98ED ;*** TPM1C2VL - TPM1 Timer Channel 2 Value Register Low; 0xFFFF98ED *** ;*** TPM1C3SC - TPM1 Timer Channel 3 Status and Control Register; 0xFFFF98EE *** TPM1C3SC: .equ $FFFF98EE ;*** TPM1C3SC - TPM1 Timer Channel 3 Status and Control Register; 0xFFFF98EE *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPM1C3SC_ELS3A: .equ 2 ; Edge/Level Select Bit A TPM1C3SC_ELS3B: .equ 3 ; Edge/Level Select Bit B TPM1C3SC_MS3A: .equ 4 ; Mode Select A for TPM Channel 3 TPM1C3SC_MS3B: .equ 5 ; Mode Select B for TPM Channel 3 TPM1C3SC_CH3IE: .equ 6 ; Channel 3 Interrupt Enable TPM1C3SC_CH3F: .equ 7 ; Channel 3 Flag ; bit position masks mTPM1C3SC_ELS3A: .equ %00000100 mTPM1C3SC_ELS3B: .equ %00001000 mTPM1C3SC_MS3A: .equ %00010000 mTPM1C3SC_MS3B: .equ %00100000 mTPM1C3SC_CH3IE: .equ %01000000 mTPM1C3SC_CH3F: .equ %10000000 ;*** TPM1C3V - TPM1 Timer Channel 3 Value Register; 0xFFFF98EF *** TPM1C3V: .equ $FFFF98EF ;*** TPM1C3V - TPM1 Timer Channel 3 Value Register; 0xFFFF98EF *** ;*** TPM1C3VH - TPM1 Timer Channel 3 Value Register High; 0xFFFF98EF *** TPM1C3VH: .equ $FFFF98EF ;*** TPM1C3VH - TPM1 Timer Channel 3 Value Register High; 0xFFFF98EF *** ;*** TPM1C3VL - TPM1 Timer Channel 3 Value Register Low; 0xFFFF98F0 *** TPM1C3VL: .equ $FFFF98F0 ;*** TPM1C3VL - TPM1 Timer Channel 3 Value Register Low; 0xFFFF98F0 *** ;*** ADCCV - Compare Value Register; 0xFFFF98F8 *** ADCCV: .equ $FFFF98F8 ;*** ADCCV - Compare Value Register; 0xFFFF98F8 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADCCV_CV0: .equ 0 ; Compare Function Value Bit 0 ADCCV_CV1: .equ 1 ; Compare Function Value Bit 1 ADCCV_CV2: .equ 2 ; Compare Function Value Bit 2 ADCCV_CV3: .equ 3 ; Compare Function Value Bit 3 ADCCV_CV4: .equ 4 ; Compare Function Value Bit 4 ADCCV_CV5: .equ 5 ; Compare Function Value Bit 5 ADCCV_CV6: .equ 6 ; Compare Function Value Bit 6 ADCCV_CV7: .equ 7 ; Compare Function Value Bit 7 ADCCV_CV8: .equ 8 ; Compare Function Value Bit 8 ADCCV_CV9: .equ 9 ; Compare Function Value Bit 9 ADCCV_CV10: .equ 10 ; Compare Function Value Bit 10 ADCCV_CV11: .equ 11 ; Compare Function Value Bit 11 ; bit position masks mADCCV_CV0: .equ %00000001 mADCCV_CV1: .equ %00000010 mADCCV_CV2: .equ %00000100 mADCCV_CV3: .equ %00001000 mADCCV_CV4: .equ %00010000 mADCCV_CV5: .equ %00100000 mADCCV_CV6: .equ %01000000 mADCCV_CV7: .equ %10000000 mADCCV_CV8: .equ %100000000 mADCCV_CV9: .equ %1000000000 mADCCV_CV10: .equ %10000000000 mADCCV_CV11: .equ %100000000000 ;*** ADCCVH - Compare Value High Register; 0xFFFF98F8 *** ADCCVH: .equ $FFFF98F8 ;*** ADCCVH - Compare Value High Register; 0xFFFF98F8 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADCCVH_CV8: .equ 0 ; Compare Function Value Bit 8 ADCCVH_CV9: .equ 1 ; Compare Function Value Bit 9 ADCCVH_CV10: .equ 2 ; Compare Function Value Bit 10 ADCCVH_CV11: .equ 3 ; Compare Function Value Bit 11 ; bit position masks mADCCVH_CV8: .equ %00000001 mADCCVH_CV9: .equ %00000010 mADCCVH_CV10: .equ %00000100 mADCCVH_CV11: .equ %00001000 ;*** ADCCVL - Compare Value Low Register; 0xFFFF98F9 *** ADCCVL: .equ $FFFF98F9 ;*** ADCCVL - Compare Value Low Register; 0xFFFF98F9 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADCCVL_CV0: .equ 0 ; Compare Function Value 0 ADCCVL_CV1: .equ 1 ; Compare Function Value 1 ADCCVL_CV2: .equ 2 ; Compare Function Value 2 ADCCVL_CV3: .equ 3 ; Compare Function Value 3 ADCCVL_CV4: .equ 4 ; Compare Function Value 4 ADCCVL_CV5: .equ 5 ; Compare Function Value 5 ADCCVL_CV6: .equ 6 ; Compare Function Value 6 ADCCVL_CV7: .equ 7 ; Compare Function Value 7 ; bit position masks mADCCVL_CV0: .equ %00000001 mADCCVL_CV1: .equ %00000010 mADCCVL_CV2: .equ %00000100 mADCCVL_CV3: .equ %00001000 mADCCVL_CV4: .equ %00010000 mADCCVL_CV5: .equ %00100000 mADCCVL_CV6: .equ %01000000 mADCCVL_CV7: .equ %10000000 ;*** ADCSC2 - Status and Control Register 2; 0xFFFF98FC *** ADCSC2: .equ $FFFF98FC ;*** ADCSC2 - Status and Control Register 2; 0xFFFF98FC *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADCSC2_ACFGT: .equ 4 ; Compare Function Greater Than Enable ADCSC2_ACFE: .equ 5 ; Compare Function Enable - ACFE is used to enable the compare function ADCSC2_ADTRG: .equ 6 ; Conversion Trigger Select-ADTRG is used to select the type of trigger to be used for initiating a conversion ADCSC2_ADACT: .equ 7 ; Conversion Active - ADACT indicates that a conversion is in progress. ADACT is set when a conversion is initiated and cleared when a conversion is completed or aborted ; bit position masks mADCSC2_ACFGT: .equ %00010000 mADCSC2_ACFE: .equ %00100000 mADCSC2_ADTRG: .equ %01000000 mADCSC2_ADACT: .equ %10000000 ;*** ADCSC3 - Status and Control Register 3; 0xFFFF98FD *** ADCSC3: .equ $FFFF98FD ;*** ADCSC3 - Status and Control Register 3; 0xFFFF98FD *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADCSC3_ADCO: .equ 3 ; Continuous Conversion Enable - ADCO enables continuous conversions ; bit position masks mADCSC3_ADCO: .equ %00001000 ;*** APCTL1 - Pin Control 1 Register; 0xFFFF9917 *** APCTL1: .equ $FFFF9917 ;*** APCTL1 - Pin Control 1 Register; 0xFFFF9917 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET APCTL1_ADPC0: .equ 0 ; ADC Pin Control 0 - ADPC0 is used to control the pin associated with channel AD0 APCTL1_ADPC1: .equ 1 ; ADC Pin Control 1 - ADPC1 is used to control the pin associated with channel AD1 APCTL1_ADPC2: .equ 2 ; ADC Pin Control 2 - ADPC2 is used to control the pin associated with channel AD2 APCTL1_ADPC3: .equ 3 ; ADC Pin Control 3 - ADPC3 is used to control the pin associated with channel AD3 APCTL1_ADPC4: .equ 4 ; ADC Pin Control 4 - ADPC4 is used to control the pin associated with channel AD4 APCTL1_ADPC5: .equ 5 ; ADC Pin Control 5 - ADPC5 is used to control the pin associated with channel AD5 APCTL1_ADPC6: .equ 6 ; ADC Pin Control 6 - ADPC6 is used to control the pin associated with channel AD6 APCTL1_ADPC7: .equ 7 ; ADC Pin Control 7 - ADPC7 is used to control the pin associated with channel AD7 ; bit position masks mAPCTL1_ADPC0: .equ %00000001 mAPCTL1_ADPC1: .equ %00000010 mAPCTL1_ADPC2: .equ %00000100 mAPCTL1_ADPC3: .equ %00001000 mAPCTL1_ADPC4: .equ %00010000 mAPCTL1_ADPC5: .equ %00100000 mAPCTL1_ADPC6: .equ %01000000 mAPCTL1_ADPC7: .equ %10000000 ;*** APCTL2 - Pin Control 2 Register; 0xFFFF9918 *** APCTL2: .equ $FFFF9918 ;*** APCTL2 - Pin Control 2 Register; 0xFFFF9918 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET APCTL2_ADPC8: .equ 0 ; ADC Pin Control 8 - ADPC8 is used to control the pin associated with channel AD8 APCTL2_ADPC9: .equ 1 ; ADC Pin Control 9 - ADPC9 is used to control the pin associated with channel AD9 APCTL2_ADPC10: .equ 2 ; ADC Pin Control 10 - ADPC10 is used to control the pin associated with channel AD10 APCTL2_ADPC11: .equ 3 ; ADC Pin Control 11 - ADPC11 is used to control the pin associated with channel AD11 ; bit position masks mAPCTL2_ADPC8: .equ %00000001 mAPCTL2_ADPC9: .equ %00000010 mAPCTL2_ADPC10: .equ %00000100 mAPCTL2_ADPC11: .equ %00001000 ;*** F1CDIV - FLASH Clock Divider Register; 0xFFFF9920 *** F1CDIV: .equ $FFFF9920 ;*** F1CDIV - FLASH Clock Divider Register; 0xFFFF9920 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET F1CDIV_FDIV0: .equ 0 ; Divisor for FLASH Clock Divider, bit 0 F1CDIV_FDIV1: .equ 1 ; Divisor for FLASH Clock Divider, bit 1 F1CDIV_FDIV2: .equ 2 ; Divisor for FLASH Clock Divider, bit 2 F1CDIV_FDIV3: .equ 3 ; Divisor for FLASH Clock Divider, bit 3 F1CDIV_FDIV4: .equ 4 ; Divisor for FLASH Clock Divider, bit 4 F1CDIV_FDIV5: .equ 5 ; Divisor for FLASH Clock Divider, bit 5 F1CDIV_PRDIV8: .equ 6 ; Prescale (Divide) FLASH Clock by 8 F1CDIV_FDIVLD: .equ 7 ; Divisor Loaded Status Flag ; bit position masks mF1CDIV_FDIV0: .equ %00000001 mF1CDIV_FDIV1: .equ %00000010 mF1CDIV_FDIV2: .equ %00000100 mF1CDIV_FDIV3: .equ %00001000 mF1CDIV_FDIV4: .equ %00010000 mF1CDIV_FDIV5: .equ %00100000 mF1CDIV_PRDIV8: .equ %01000000 mF1CDIV_FDIVLD: .equ %10000000 ;*** F1OPT - Flash Options Register; 0xFFFF9921 *** F1OPT: .equ $FFFF9921 ;*** F1OPT - Flash Options Register; 0xFFFF9921 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET F1OPT_SEC0: .equ 0 ; Flash Security Bit 0 F1OPT_SEC1: .equ 1 ; Flash Security Bit 1 F1OPT_KEYEN0: .equ 6 ; Backdoor Key Security Enable Bit 0 F1OPT_KEYEN1: .equ 7 ; Backdoor Key Security Enable Bit 1 ; bit position masks mF1OPT_SEC0: .equ %00000001 mF1OPT_SEC1: .equ %00000010 mF1OPT_KEYEN0: .equ %01000000 mF1OPT_KEYEN1: .equ %10000000 ;*** F1CNFG - Flash Configuration Register; 0xFFFF9923 *** F1CNFG: .equ $FFFF9923 ;*** F1CNFG - Flash Configuration Register; 0xFFFF9923 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET F1CNFG_KEYACC: .equ 5 ; Enable Security Key Writing F1CNFG_CCIE: .equ 6 ; Command Complete Interrupt Enable F1CNFG_CBEIE: .equ 7 ; Command Buffer Empty Interrupt Enable ; bit position masks mF1CNFG_KEYACC: .equ %00100000 mF1CNFG_CCIE: .equ %01000000 mF1CNFG_CBEIE: .equ %10000000 ;*** F1PROT - Flash Protection Register; 0xFFFF9924 *** F1PROT: .equ $FFFF9924 ;*** F1PROT - Flash Protection Register; 0xFFFF9924 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET F1PROT_FPOPEN: .equ 0 ; Flash Protection Open F1PROT_FPS0: .equ 1 ; Flash Protection Size, bit 0 F1PROT_FPS1: .equ 2 ; Flash Protection Size, bit 1 F1PROT_FPS2: .equ 3 ; Flash Protection Size, bit 2 F1PROT_FPS3: .equ 4 ; Flash Protection Size, bit 3 F1PROT_FPS4: .equ 5 ; Flash Protection Size, bit 4 F1PROT_FPS5: .equ 6 ; Flash Protection Size, bit 5 F1PROT_FPS6: .equ 7 ; Flash Protection Size, bit 6 ; bit position masks mF1PROT_FPOPEN: .equ %00000001 mF1PROT_FPS0: .equ %00000010 mF1PROT_FPS1: .equ %00000100 mF1PROT_FPS2: .equ %00001000 mF1PROT_FPS3: .equ %00010000 mF1PROT_FPS4: .equ %00100000 mF1PROT_FPS5: .equ %01000000 mF1PROT_FPS6: .equ %10000000 ;*** F1STAT - Flash Status Register; 0xFFFF9925 *** F1STAT: .equ $FFFF9925 ;*** F1STAT - Flash Status Register; 0xFFFF9925 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET F1STAT_FBLANK: .equ 2 ; FLASH Flag Indicating the Erase Verify Operation Status F1STAT_FACCERR: .equ 4 ; FLASH Access Error Flag F1STAT_FPVIOL: .equ 5 ; FLASH Protection Violation Flag F1STAT_FCCF: .equ 6 ; FLASH Command Complete Interrupt Flag F1STAT_FCBEF: .equ 7 ; FLASH Command Buffer Empty Flag ; bit position masks mF1STAT_FBLANK: .equ %00000100 mF1STAT_FACCERR: .equ %00010000 mF1STAT_FPVIOL: .equ %00100000 mF1STAT_FCCF: .equ %01000000 mF1STAT_FCBEF: .equ %10000000 ;*** F1CMD - Flash Command Register; 0xFFFF9926 *** F1CMD: .equ $FFFF9926 ;*** F1CMD - Flash Command Register; 0xFFFF9926 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET F1CMD_FCMD0: .equ 0 ; Flash Command, bit 0 F1CMD_FCMD1: .equ 1 ; Flash Command, bit 1 F1CMD_FCMD2: .equ 2 ; Flash Command, bit 2 F1CMD_FCMD3: .equ 3 ; Flash Command, bit 3 F1CMD_FCMD4: .equ 4 ; Flash Command, bit 4 F1CMD_FCMD5: .equ 5 ; Flash Command, bit 5 F1CMD_FCMD6: .equ 6 ; Flash Command, bit 6 ; bit position masks mF1CMD_FCMD0: .equ %00000001 mF1CMD_FCMD1: .equ %00000010 mF1CMD_FCMD2: .equ %00000100 mF1CMD_FCMD3: .equ %00001000 mF1CMD_FCMD4: .equ %00010000 mF1CMD_FCMD5: .equ %00100000 mF1CMD_FCMD6: .equ %01000000 ;*** F2CDIV - FLASH Clock Divider Register; 0xFFFF9930 *** F2CDIV: .equ $FFFF9930 ;*** F2CDIV - FLASH Clock Divider Register; 0xFFFF9930 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET F2CDIV_FDIV0: .equ 0 ; Divisor for FLASH Clock Divider, bit 0 F2CDIV_FDIV1: .equ 1 ; Divisor for FLASH Clock Divider, bit 1 F2CDIV_FDIV2: .equ 2 ; Divisor for FLASH Clock Divider, bit 2 F2CDIV_FDIV3: .equ 3 ; Divisor for FLASH Clock Divider, bit 3 F2CDIV_FDIV4: .equ 4 ; Divisor for FLASH Clock Divider, bit 4 F2CDIV_FDIV5: .equ 5 ; Divisor for FLASH Clock Divider, bit 5 F2CDIV_PRDIV8: .equ 6 ; Prescale (Divide) FLASH Clock by 8 F2CDIV_FDIVLD: .equ 7 ; Divisor Loaded Status Flag ; bit position masks mF2CDIV_FDIV0: .equ %00000001 mF2CDIV_FDIV1: .equ %00000010 mF2CDIV_FDIV2: .equ %00000100 mF2CDIV_FDIV3: .equ %00001000 mF2CDIV_FDIV4: .equ %00010000 mF2CDIV_FDIV5: .equ %00100000 mF2CDIV_PRDIV8: .equ %01000000 mF2CDIV_FDIVLD: .equ %10000000 ;*** F2OPT - Flash Options Register; 0xFFFF9931 *** F2OPT: .equ $FFFF9931 ;*** F2OPT - Flash Options Register; 0xFFFF9931 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET F2OPT_SEC0: .equ 0 ; Flash Security Bit 0 F2OPT_SEC1: .equ 1 ; Flash Security Bit 1 F2OPT_KEYEN0: .equ 6 ; Backdoor Key Security Enable Bit 0 F2OPT_KEYEN1: .equ 7 ; Backdoor Key Security Enable Bit 1 ; bit position masks mF2OPT_SEC0: .equ %00000001 mF2OPT_SEC1: .equ %00000010 mF2OPT_KEYEN0: .equ %01000000 mF2OPT_KEYEN1: .equ %10000000 ;*** F2CNFG - Flash Configuration Register; 0xFFFF9933 *** F2CNFG: .equ $FFFF9933 ;*** F2CNFG - Flash Configuration Register; 0xFFFF9933 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET F2CNFG_KEYACC: .equ 5 ; Enable Security Key Writing F2CNFG_CCIE: .equ 6 ; Command Complete Interrupt Enable F2CNFG_CBEIE: .equ 7 ; Command Buffer Empty Interrupt Enable ; bit position masks mF2CNFG_KEYACC: .equ %00100000 mF2CNFG_CCIE: .equ %01000000 mF2CNFG_CBEIE: .equ %10000000 ;*** F2PROT - Flash Protection Register; 0xFFFF9934 *** F2PROT: .equ $FFFF9934 ;*** F2PROT - Flash Protection Register; 0xFFFF9934 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET F2PROT_FPOPEN: .equ 0 ; Flash Protection Open F2PROT_FPS0: .equ 1 ; Flash Protection Size, bit 0 F2PROT_FPS1: .equ 2 ; Flash Protection Size, bit 1 F2PROT_FPS2: .equ 3 ; Flash Protection Size, bit 2 F2PROT_FPS3: .equ 4 ; Flash Protection Size, bit 3 F2PROT_FPS4: .equ 5 ; Flash Protection Size, bit 4 F2PROT_FPS5: .equ 6 ; Flash Protection Size, bit 5 F2PROT_FPS6: .equ 7 ; Flash Protection Size, bit 6 ; bit position masks mF2PROT_FPOPEN: .equ %00000001 mF2PROT_FPS0: .equ %00000010 mF2PROT_FPS1: .equ %00000100 mF2PROT_FPS2: .equ %00001000 mF2PROT_FPS3: .equ %00010000 mF2PROT_FPS4: .equ %00100000 mF2PROT_FPS5: .equ %01000000 mF2PROT_FPS6: .equ %10000000 ;*** F2STAT - Flash Status Register; 0xFFFF9935 *** F2STAT: .equ $FFFF9935 ;*** F2STAT - Flash Status Register; 0xFFFF9935 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET F2STAT_FBLANK: .equ 2 ; FLASH Flag Indicating the Erase Verify Operation Status F2STAT_FACCERR: .equ 4 ; FLASH Access Error Flag F2STAT_FPVIOL: .equ 5 ; FLASH Protection Violation Flag F2STAT_FCCF: .equ 6 ; FLASH Command Complete Interrupt Flag F2STAT_FCBEF: .equ 7 ; FLASH Command Buffer Empty Flag ; bit position masks mF2STAT_FBLANK: .equ %00000100 mF2STAT_FACCERR: .equ %00010000 mF2STAT_FPVIOL: .equ %00100000 mF2STAT_FCCF: .equ %01000000 mF2STAT_FCBEF: .equ %10000000 ;*** F2CMD - Flash Command Register; 0xFFFF9936 *** F2CMD: .equ $FFFF9936 ;*** F2CMD - Flash Command Register; 0xFFFF9936 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET F2CMD_FCMD0: .equ 0 ; Flash Command, bit 0 F2CMD_FCMD1: .equ 1 ; Flash Command, bit 1 F2CMD_FCMD2: .equ 2 ; Flash Command, bit 2 F2CMD_FCMD3: .equ 3 ; Flash Command, bit 3 F2CMD_FCMD4: .equ 4 ; Flash Command, bit 4 F2CMD_FCMD5: .equ 5 ; Flash Command, bit 5 F2CMD_FCMD6: .equ 6 ; Flash Command, bit 6 ; bit position masks mF2CMD_FCMD0: .equ %00000001 mF2CMD_FCMD1: .equ %00000010 mF2CMD_FCMD2: .equ %00000100 mF2CMD_FCMD3: .equ %00001000 mF2CMD_FCMD4: .equ %00010000 mF2CMD_FCMD5: .equ %00100000 mF2CMD_FCMD6: .equ %01000000 ;*** PTHD - Port H Data Register; 0xFFFF9940 *** PTHD: .equ $FFFF9940 ;*** PTHD - Port H Data Register; 0xFFFF9940 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTHD_PTHD0: .equ 0 ; Port H Data Register Bit 0 PTHD_PTHD1: .equ 1 ; Port H Data Register Bit 1 PTHD_PTHD2: .equ 2 ; Port H Data Register Bit 2 PTHD_PTHD3: .equ 3 ; Port H Data Register Bit 3 PTHD_PTHD4: .equ 4 ; Port H Data Register Bit 4 PTHD_PTHD5: .equ 5 ; Port H Data Register Bit 5 PTHD_PTHD6: .equ 6 ; Port H Data Register Bit 6 PTHD_PTHD7: .equ 7 ; Port H Data Register Bit 7 ; bit position masks mPTHD_PTHD0: .equ %00000001 mPTHD_PTHD1: .equ %00000010 mPTHD_PTHD2: .equ %00000100 mPTHD_PTHD3: .equ %00001000 mPTHD_PTHD4: .equ %00010000 mPTHD_PTHD5: .equ %00100000 mPTHD_PTHD6: .equ %01000000 mPTHD_PTHD7: .equ %10000000 ;*** PTHDD - Port H Data Direction Register; 0xFFFF9941 *** PTHDD: .equ $FFFF9941 ;*** PTHDD - Port H Data Direction Register; 0xFFFF9941 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTHDD_PTHDD0: .equ 0 ; Data Direction for Port H Bit 0 PTHDD_PTHDD1: .equ 1 ; Data Direction for Port H Bit 1 PTHDD_PTHDD2: .equ 2 ; Data Direction for Port H Bit 2 PTHDD_PTHDD3: .equ 3 ; Data Direction for Port H Bit 3 PTHDD_PTHDD4: .equ 4 ; Data Direction for Port H Bit 4 PTHDD_PTHDD5: .equ 5 ; Data Direction for Port H Bit 5 PTHDD_PTHDD6: .equ 6 ; Data Direction for Port H Bit 6 PTHDD_PTHDD7: .equ 7 ; Data Direction for Port H Bit 7 ; bit position masks mPTHDD_PTHDD0: .equ %00000001 mPTHDD_PTHDD1: .equ %00000010 mPTHDD_PTHDD2: .equ %00000100 mPTHDD_PTHDD3: .equ %00001000 mPTHDD_PTHDD4: .equ %00010000 mPTHDD_PTHDD5: .equ %00100000 mPTHDD_PTHDD6: .equ %01000000 mPTHDD_PTHDD7: .equ %10000000 ;*** PTJD - Port J Data Register; 0xFFFF9942 *** PTJD: .equ $FFFF9942 ;*** PTJD - Port J Data Register; 0xFFFF9942 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTJD_PTJD0: .equ 0 ; Port J Data Register Bit 0 PTJD_PTJD1: .equ 1 ; Port J Data Register Bit 1 PTJD_PTJD2: .equ 2 ; Port J Data Register Bit 2 PTJD_PTJD3: .equ 3 ; Port J Data Register Bit 3 PTJD_PTJD4: .equ 4 ; Port J Data Register Bit 4 PTJD_PTJD5: .equ 5 ; Port J Data Register Bit 5 PTJD_PTJD6: .equ 6 ; Port J Data Register Bit 6 PTJD_PTJD7: .equ 7 ; Port J Data Register Bit 7 ; bit position masks mPTJD_PTJD0: .equ %00000001 mPTJD_PTJD1: .equ %00000010 mPTJD_PTJD2: .equ %00000100 mPTJD_PTJD3: .equ %00001000 mPTJD_PTJD4: .equ %00010000 mPTJD_PTJD5: .equ %00100000 mPTJD_PTJD6: .equ %01000000 mPTJD_PTJD7: .equ %10000000 ;*** PTJDD - Port J Data Direction Register; 0xFFFF9943 *** PTJDD: .equ $FFFF9943 ;*** PTJDD - Port J Data Direction Register; 0xFFFF9943 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTJDD_PTJDD0: .equ 0 ; Data Direction for Port J Bit 0 PTJDD_PTJDD1: .equ 1 ; Data Direction for Port J Bit 1 PTJDD_PTJDD2: .equ 2 ; Data Direction for Port J Bit 2 PTJDD_PTJDD3: .equ 3 ; Data Direction for Port J Bit 3 PTJDD_PTJDD4: .equ 4 ; Data Direction for Port J Bit 4 PTJDD_PTJDD5: .equ 5 ; Data Direction for Port J Bit 5 PTJDD_PTJDD6: .equ 6 ; Data Direction for Port J Bit 6 PTJDD_PTJDD7: .equ 7 ; Data Direction for Port J Bit 7 ; bit position masks mPTJDD_PTJDD0: .equ %00000001 mPTJDD_PTJDD1: .equ %00000010 mPTJDD_PTJDD2: .equ %00000100 mPTJDD_PTJDD3: .equ %00001000 mPTJDD_PTJDD4: .equ %00010000 mPTJDD_PTJDD5: .equ %00100000 mPTJDD_PTJDD6: .equ %01000000 mPTJDD_PTJDD7: .equ %10000000 ;*** PTHPE - Port H Pull Enable Register; 0xFFFF9948 *** PTHPE: .equ $FFFF9948 ;*** PTHPE - Port H Pull Enable Register; 0xFFFF9948 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTHPE_PTHPE0: .equ 0 ; Internal Pull Enable for Port H Bit 0 PTHPE_PTHPE1: .equ 1 ; Internal Pull Enable for Port H Bit 1 PTHPE_PTHPE2: .equ 2 ; Internal Pull Enable for Port H Bit 2 PTHPE_PTHPE3: .equ 3 ; Internal Pull Enable for Port H Bit 3 PTHPE_PTHPE4: .equ 4 ; Internal Pull Enable for Port H Bit 4 PTHPE_PTHPE5: .equ 5 ; Internal Pull Enable for Port H Bit 5 PTHPE_PTHPE6: .equ 6 ; Internal Pull Enable for Port H Bit 6 PTHPE_PTHPE7: .equ 7 ; Internal Pull Enable for Port H Bit 7 ; bit position masks mPTHPE_PTHPE0: .equ %00000001 mPTHPE_PTHPE1: .equ %00000010 mPTHPE_PTHPE2: .equ %00000100 mPTHPE_PTHPE3: .equ %00001000 mPTHPE_PTHPE4: .equ %00010000 mPTHPE_PTHPE5: .equ %00100000 mPTHPE_PTHPE6: .equ %01000000 mPTHPE_PTHPE7: .equ %10000000 ;*** PTHSE - Port H Slew Rate Enable Register; 0xFFFF9949 *** PTHSE: .equ $FFFF9949 ;*** PTHSE - Port H Slew Rate Enable Register; 0xFFFF9949 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTHSE_PTHSE0: .equ 0 ; Output Slew Rate Enable for Port H Bit 0 PTHSE_PTHSE1: .equ 1 ; Output Slew Rate Enable for Port H Bit 1 PTHSE_PTHSE2: .equ 2 ; Output Slew Rate Enable for Port H Bit 2 PTHSE_PTHSE3: .equ 3 ; Output Slew Rate Enable for Port H Bit 3 PTHSE_PTHSE4: .equ 4 ; Output Slew Rate Enable for Port H Bit 4 PTHSE_PTHSE5: .equ 5 ; Output Slew Rate Enable for Port H Bit 5 PTHSE_PTHSE6: .equ 6 ; Output Slew Rate Enable for Port H Bit 6 PTHSE_PTHSE7: .equ 7 ; Output Slew Rate Enable for Port H Bit 7 ; bit position masks mPTHSE_PTHSE0: .equ %00000001 mPTHSE_PTHSE1: .equ %00000010 mPTHSE_PTHSE2: .equ %00000100 mPTHSE_PTHSE3: .equ %00001000 mPTHSE_PTHSE4: .equ %00010000 mPTHSE_PTHSE5: .equ %00100000 mPTHSE_PTHSE6: .equ %01000000 mPTHSE_PTHSE7: .equ %10000000 ;*** PTHDS - Port H Drive Strength Selection Register; 0xFFFF994A *** PTHDS: .equ $FFFF994A ;*** PTHDS - Port H Drive Strength Selection Register; 0xFFFF994A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTHDS_PTHDS0: .equ 0 ; Output Drive Strength Selection for Port H Bit 0 PTHDS_PTHDS1: .equ 1 ; Output Drive Strength Selection for Port H Bit 1 PTHDS_PTHDS2: .equ 2 ; Output Drive Strength Selection for Port H Bit 2 PTHDS_PTHDS3: .equ 3 ; Output Drive Strength Selection for Port H Bit 3 PTHDS_PTHDS4: .equ 4 ; Output Drive Strength Selection for Port H Bit 4 PTHDS_PTHDS5: .equ 5 ; Output Drive Strength Selection for Port H Bit 5 PTHDS_PTHDS6: .equ 6 ; Output Drive Strength Selection for Port H Bit 6 PTHDS_PTHDS7: .equ 7 ; Output Drive Strength Selection for Port H Bit 7 ; bit position masks mPTHDS_PTHDS0: .equ %00000001 mPTHDS_PTHDS1: .equ %00000010 mPTHDS_PTHDS2: .equ %00000100 mPTHDS_PTHDS3: .equ %00001000 mPTHDS_PTHDS4: .equ %00010000 mPTHDS_PTHDS5: .equ %00100000 mPTHDS_PTHDS6: .equ %01000000 mPTHDS_PTHDS7: .equ %10000000 ;*** PTHIFE - Port H Input Filter Enable Register; 0xFFFF994B *** PTHIFE: .equ $FFFF994B ;*** PTHIFE - Port H Input Filter Enable Register; 0xFFFF994B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTHIFE_PTHIFE0: .equ 0 ; Port H Input Filter Enable Bit 0 PTHIFE_PTHIFE1: .equ 1 ; Port H Input Filter Enable Bit 1 PTHIFE_PTHIFE2: .equ 2 ; Port H Input Filter Enable Bit 2 PTHIFE_PTHIFE3: .equ 3 ; Port H Input Filter Enable Bit 3 PTHIFE_PTHIFE4: .equ 4 ; Port H Input Filter Enable Bit 4 PTHIFE_PTHIFE5: .equ 5 ; Port H Input Filter Enable Bit 5 PTHIFE_PTHIFE6: .equ 6 ; Port H Input Filter Enable Bit 6 PTHIFE_PTHIFE7: .equ 7 ; Port H Input Filter Enable Bit 7 ; bit position masks mPTHIFE_PTHIFE0: .equ %00000001 mPTHIFE_PTHIFE1: .equ %00000010 mPTHIFE_PTHIFE2: .equ %00000100 mPTHIFE_PTHIFE3: .equ %00001000 mPTHIFE_PTHIFE4: .equ %00010000 mPTHIFE_PTHIFE5: .equ %00100000 mPTHIFE_PTHIFE6: .equ %01000000 mPTHIFE_PTHIFE7: .equ %10000000 ;*** PTJPE - Port J Pull Enable Register; 0xFFFF994C *** PTJPE: .equ $FFFF994C ;*** PTJPE - Port J Pull Enable Register; 0xFFFF994C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTJPE_PTJPE0: .equ 0 ; Internal Pull Enable for Port J Bit 0 PTJPE_PTJPE1: .equ 1 ; Internal Pull Enable for Port J Bit 1 PTJPE_PTJPE2: .equ 2 ; Internal Pull Enable for Port J Bit 2 PTJPE_PTJPE3: .equ 3 ; Internal Pull Enable for Port J Bit 3 PTJPE_PTJPE4: .equ 4 ; Internal Pull Enable for Port J Bit 4 PTJPE_PTJPE5: .equ 5 ; Internal Pull Enable for Port J Bit 5 PTJPE_PTJPE6: .equ 6 ; Internal Pull Enable for Port J Bit 6 PTJPE_PTJPE7: .equ 7 ; Internal Pull Enable for Port J Bit 7 ; bit position masks mPTJPE_PTJPE0: .equ %00000001 mPTJPE_PTJPE1: .equ %00000010 mPTJPE_PTJPE2: .equ %00000100 mPTJPE_PTJPE3: .equ %00001000 mPTJPE_PTJPE4: .equ %00010000 mPTJPE_PTJPE5: .equ %00100000 mPTJPE_PTJPE6: .equ %01000000 mPTJPE_PTJPE7: .equ %10000000 ;*** PTJSE - Port J Slew Rate Enable Register; 0xFFFF994D *** PTJSE: .equ $FFFF994D ;*** PTJSE - Port J Slew Rate Enable Register; 0xFFFF994D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTJSE_PTJSE0: .equ 0 ; Output Slew Rate Enable for Port J Bit 0 PTJSE_PTJSE1: .equ 1 ; Output Slew Rate Enable for Port J Bit 1 PTJSE_PTJSE2: .equ 2 ; Output Slew Rate Enable for Port J Bit 2 PTJSE_PTJSE3: .equ 3 ; Output Slew Rate Enable for Port J Bit 3 PTJSE_PTJSE4: .equ 4 ; Output Slew Rate Enable for Port J Bit 4 PTJSE_PTJSE5: .equ 5 ; Output Slew Rate Enable for Port J Bit 5 PTJSE_PTJSE6: .equ 6 ; Output Slew Rate Enable for Port J Bit 6 PTJSE_PTJSE7: .equ 7 ; Output Slew Rate Enable for Port J Bit 7 ; bit position masks mPTJSE_PTJSE0: .equ %00000001 mPTJSE_PTJSE1: .equ %00000010 mPTJSE_PTJSE2: .equ %00000100 mPTJSE_PTJSE3: .equ %00001000 mPTJSE_PTJSE4: .equ %00010000 mPTJSE_PTJSE5: .equ %00100000 mPTJSE_PTJSE6: .equ %01000000 mPTJSE_PTJSE7: .equ %10000000 ;*** PTJDS - Port J Drive Strength Selection Register; 0xFFFF994E *** PTJDS: .equ $FFFF994E ;*** PTJDS - Port J Drive Strength Selection Register; 0xFFFF994E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTJDS_PTJDS0: .equ 0 ; Output Drive Strength Selection for Port J Bit 0 PTJDS_PTJDS1: .equ 1 ; Output Drive Strength Selection for Port J Bit 1 PTJDS_PTJDS2: .equ 2 ; Output Drive Strength Selection for Port J Bit 2 PTJDS_PTJDS3: .equ 3 ; Output Drive Strength Selection for Port J Bit 3 PTJDS_PTJDS4: .equ 4 ; Output Drive Strength Selection for Port J Bit 4 PTJDS_PTJDS5: .equ 5 ; Output Drive Strength Selection for Port J Bit 5 PTJDS_PTJDS6: .equ 6 ; Output Drive Strength Selection for Port J Bit 6 PTJDS_PTJDS7: .equ 7 ; Output Drive Strength Selection for Port J Bit 7 ; bit position masks mPTJDS_PTJDS0: .equ %00000001 mPTJDS_PTJDS1: .equ %00000010 mPTJDS_PTJDS2: .equ %00000100 mPTJDS_PTJDS3: .equ %00001000 mPTJDS_PTJDS4: .equ %00010000 mPTJDS_PTJDS5: .equ %00100000 mPTJDS_PTJDS6: .equ %01000000 mPTJDS_PTJDS7: .equ %10000000 ;*** PTJIFE - Port J Input Filter Enable Register; 0xFFFF994F *** PTJIFE: .equ $FFFF994F ;*** PTJIFE - Port J Input Filter Enable Register; 0xFFFF994F *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTJIFE_PTJIFE0: .equ 0 ; Port J Input Filter Enable Bit 0 PTJIFE_PTJIFE1: .equ 1 ; Port J Input Filter Enable Bit 1 PTJIFE_PTJIFE2: .equ 2 ; Port J Input Filter Enable Bit 2 PTJIFE_PTJIFE3: .equ 3 ; Port J Input Filter Enable Bit 3 PTJIFE_PTJIFE4: .equ 4 ; Port J Input Filter Enable Bit 4 PTJIFE_PTJIFE5: .equ 5 ; Port J Input Filter Enable Bit 5 PTJIFE_PTJIFE6: .equ 6 ; Port J Input Filter Enable Bit 6 PTJIFE_PTJIFE7: .equ 7 ; Port J Input Filter Enable Bit 7 ; bit position masks mPTJIFE_PTJIFE0: .equ %00000001 mPTJIFE_PTJIFE1: .equ %00000010 mPTJIFE_PTJIFE2: .equ %00000100 mPTJIFE_PTJIFE3: .equ %00001000 mPTJIFE_PTJIFE4: .equ %00010000 mPTJIFE_PTJIFE5: .equ %00100000 mPTJIFE_PTJIFE6: .equ %01000000 mPTJIFE_PTJIFE7: .equ %10000000 ;*** PER_ID - Peripherial ID Register; 0xFFFF9A00 *** PER_ID: .equ $FFFF9A00 ;*** PER_ID - Peripherial ID Register; 0xFFFF9A00 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PER_ID_ID0: .equ 0 ; Peripheral identification bits. These bits will always read 0x04 (00_0100), bit 0 PER_ID_ID1: .equ 1 ; Peripheral identification bits. These bits will always read 0x04 (00_0100), bit 1 PER_ID_ID2: .equ 2 ; Peripheral identification bits. These bits will always read 0x04 (00_0100), bit 2 PER_ID_ID3: .equ 3 ; Peripheral identification bits. These bits will always read 0x04 (00_0100), bit 3 PER_ID_ID4: .equ 4 ; Peripheral identification bits. These bits will always read 0x04 (00_0100), bit 4 PER_ID_ID5: .equ 5 ; Peripheral identification bits. These bits will always read 0x04 (00_0100), bit 5 ; bit position masks mPER_ID_ID0: .equ %00000001 mPER_ID_ID1: .equ %00000010 mPER_ID_ID2: .equ %00000100 mPER_ID_ID3: .equ %00001000 mPER_ID_ID4: .equ %00010000 mPER_ID_ID5: .equ %00100000 ;*** ID_COMP - Peripheral ID Complement Register; 0xFFFF9A04 *** ID_COMP: .equ $FFFF9A04 ;*** ID_COMP - Peripheral ID Complement Register; 0xFFFF9A04 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ID_COMP_NID0: .equ 0 ; Ones complement of peripheral identification bits, bit 0 ID_COMP_NID1: .equ 1 ; Ones complement of peripheral identification bits, bit 1 ID_COMP_NID2: .equ 2 ; Ones complement of peripheral identification bits, bit 2 ID_COMP_NID3: .equ 3 ; Ones complement of peripheral identification bits, bit 3 ID_COMP_NID4: .equ 4 ; Ones complement of peripheral identification bits, bit 4 ID_COMP_NID5: .equ 5 ; Ones complement of peripheral identification bits, bit 5 ; bit position masks mID_COMP_NID0: .equ %00000001 mID_COMP_NID1: .equ %00000010 mID_COMP_NID2: .equ %00000100 mID_COMP_NID3: .equ %00001000 mID_COMP_NID4: .equ %00010000 mID_COMP_NID5: .equ %00100000 ;*** REV - Peripheral Revision Register; 0xFFFF9A08 *** REV: .equ $FFFF9A08 ;*** REV - Peripheral Revision Register; 0xFFFF9A08 *** ;*** ADD_INFO - Peripheral Additional Info Register; 0xFFFF9A0C *** ADD_INFO: .equ $FFFF9A0C ;*** ADD_INFO - Peripheral Additional Info Register; 0xFFFF9A0C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADD_INFO_IEHOST: .equ 0 ; This bit will be set if host mode is enabled ADD_INFO_IRQ_NUM0: .equ 3 ; Assigned Interrupt Request Number, bit 0 ADD_INFO_IRQ_NUM1: .equ 4 ; Assigned Interrupt Request Number, bit 1 ADD_INFO_IRQ_NUM2: .equ 5 ; Assigned Interrupt Request Number, bit 2 ADD_INFO_IRQ_NUM3: .equ 6 ; Assigned Interrupt Request Number, bit 3 ADD_INFO_IRQ_NUM4: .equ 7 ; Assigned Interrupt Request Number, bit 4 ; bit position masks mADD_INFO_IEHOST: .equ %00000001 mADD_INFO_IRQ_NUM0: .equ %00001000 mADD_INFO_IRQ_NUM1: .equ %00010000 mADD_INFO_IRQ_NUM2: .equ %00100000 mADD_INFO_IRQ_NUM3: .equ %01000000 mADD_INFO_IRQ_NUM4: .equ %10000000 ;*** OTG_INT_STAT - OTG Interrupt Status Register; 0xFFFF9A10 *** OTG_INT_STAT: .equ $FFFF9A10 ;*** OTG_INT_STAT - OTG Interrupt Status Register; 0xFFFF9A10 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET OTG_INT_STAT_A_VBUS_CHG: .equ 0 ; This bit is set when a change in VBUS is detected on an "A" device OTG_INT_STAT_B_SESS_CHG: .equ 2 ; This bit is set when a change in VBUS is detected on a "B" device OTG_INT_STAT_SESS_VLD_CHG: .equ 3 ; This bit is set when a change in VBUS is detected indicating a session valid or a session no longer valid OTG_INT_STAT_LINE_STATE_CHG: .equ 5 ; This bit is set when the USB line state changes. The interrupt associated with this bit can be used to detect Reset, Resume, Connect, and Data Line Pulse signals OTG_INT_STAT_ONE_MSEC: .equ 6 ; This bit is set when the 1 millisecond timer expires. This bit stays asserted until clered by software. The interrupt must be serviced every millisecond to avoid losing 1msec counts OTG_INT_STAT_ID_CHG: .equ 7 ; This bit is set when a change in the ID Signal from the USB connector is sensed ; bit position masks mOTG_INT_STAT_A_VBUS_CHG: .equ %00000001 mOTG_INT_STAT_B_SESS_CHG: .equ %00000100 mOTG_INT_STAT_SESS_VLD_CHG: .equ %00001000 mOTG_INT_STAT_LINE_STATE_CHG: .equ %00100000 mOTG_INT_STAT_ONE_MSEC: .equ %01000000 mOTG_INT_STAT_ID_CHG: .equ %10000000 ;*** OTG_INT_EN - OTG Interrupt Control Register; 0xFFFF9A14 *** OTG_INT_EN: .equ $FFFF9A14 ;*** OTG_INT_EN - OTG Interrupt Control Register; 0xFFFF9A14 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET OTG_INT_EN_A_VBUS_EN: .equ 0 ; "A" VBUS Valid interrupt enable OTG_INT_EN_B_SESS_EN: .equ 2 ; "B" Session END interrupt enable OTG_INT_EN_SESS_VLD_EN: .equ 3 ; Session valid interrupt enable OTG_INT_EN_LINE_STATE_EN: .equ 5 ; Line State change interrupt enable OTG_INT_EN_ONE_MSEC_EN: .equ 6 ; 1 millisecond interrupt enable OTG_INT_EN_ID_EN: .equ 7 ; ID interrupt enable ; bit position masks mOTG_INT_EN_A_VBUS_EN: .equ %00000001 mOTG_INT_EN_B_SESS_EN: .equ %00000100 mOTG_INT_EN_SESS_VLD_EN: .equ %00001000 mOTG_INT_EN_LINE_STATE_EN: .equ %00100000 mOTG_INT_EN_ONE_MSEC_EN: .equ %01000000 mOTG_INT_EN_ID_EN: .equ %10000000 ;*** OTG_STAT - Interrupt Status Register; 0xFFFF9A18 *** OTG_STAT: .equ $FFFF9A18 ;*** OTG_STAT - Interrupt Status Register; 0xFFFF9A18 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET OTG_STAT_A_VBUS_VLD: .equ 0 ; "A" VBUS Valid OTG_STAT_B_SESS_END: .equ 2 ; "B" Session END OTG_STAT_SESS_VLD: .equ 3 ; Session Valid OTG_STAT_LINE_STATE_STABLE: .equ 5 ; This bit indicates that the internal signals which control the LINE_STATE_CHG bit (bit 5) of the OTG_INT_STAT register have been stable for at least 1 millisecond OTG_STAT_ONE_MSEC_EN: .equ 6 ; This bit is reserved for the 1msec count, but it is not useful to software OTG_STAT_ID: .equ 7 ; Indicates the current state of the ID pin on the USB connector ; bit position masks mOTG_STAT_A_VBUS_VLD: .equ %00000001 mOTG_STAT_B_SESS_END: .equ %00000100 mOTG_STAT_SESS_VLD: .equ %00001000 mOTG_STAT_LINE_STATE_STABLE: .equ %00100000 mOTG_STAT_ONE_MSEC_EN: .equ %01000000 mOTG_STAT_ID: .equ %10000000 ;*** OTG_CTRL - OTG Control Register; 0xFFFF9A1C *** OTG_CTRL: .equ $FFFF9A1C ;*** OTG_CTRL - OTG Control Register; 0xFFFF9A1C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET OTG_CTRL_OTG_EN: .equ 2 ; On-The-Go pull-up/pull-down resistor enable OTG_CTRL_DM_LOW: .equ 4 ; D- Data Line pull-down resistor enable. This bit should always be enabled together with bit 5 (DP_LOW) OTG_CTRL_DP_LOW: .equ 5 ; D+ Data Line pull-down resistor enable. This bit should always be enabled together with bit 4 (DM_LOW) OTG_CTRL_DP_HIGH: .equ 7 ; D+ Data Line pull-up resistor enable ; bit position masks mOTG_CTRL_OTG_EN: .equ %00000100 mOTG_CTRL_DM_LOW: .equ %00010000 mOTG_CTRL_DP_LOW: .equ %00100000 mOTG_CTRL_DP_HIGH: .equ %10000000 ;*** INT_STAT - Interrupt Status Register; 0xFFFF9A80 *** INT_STAT: .equ $FFFF9A80 ;*** INT_STAT - Interrupt Status Register; 0xFFFF9A80 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INT_STAT_USB_RST: .equ 0 ; This bit is set when the USB Module has decoded a valid USB reset INT_STAT_ERROR: .equ 1 ; This bit is set when any of the error conditions within the ERR_STAT register occur. The ColdFire core must then read the ERR_STAT register to determine the source of the error INT_STAT_SOF_TOK: .equ 2 ; This bit is set when the USB Module receives a Start Of Frame (SOF) token. In Host mode this bit is set when the SOF threshold is reached, so that software can prepare for the next SOF INT_STAT_TOK_DNE: .equ 3 ; This bit is set when the current token being processed has completed INT_STAT_SLEEP: .equ 4 ; This bit is set when the USB Module detects a constant idle on the USB bus for 3 milliseconds. The sleep timer is reset by activity on the USB bus INT_STAT_RESUME: .equ 5 ; This bit is set depending upon the DP/DM signals, and can be used to signal remote wake-up signaling on the USB bus. When not in suspend mode this interrupt should be disabled INT_STAT_ATTACH: .equ 6 ; Attach Interrupt. This bit is set when the USB Module detects an attach of a USB device. This signal is only valid if HOST_MODE_EN is true. This interrupt signifies that a peripheral is now present and must be configured INT_STAT_STALL: .equ 7 ; Stall Interrupt. In Target mode this bit is asserted when a STALL handshake is sent by the SIE. In Host mode this bit is set when the USB Module detects a STALL acknowledge during the handshake phase of a USB transaction ; bit position masks mINT_STAT_USB_RST: .equ %00000001 mINT_STAT_ERROR: .equ %00000010 mINT_STAT_SOF_TOK: .equ %00000100 mINT_STAT_TOK_DNE: .equ %00001000 mINT_STAT_SLEEP: .equ %00010000 mINT_STAT_RESUME: .equ %00100000 mINT_STAT_ATTACH: .equ %01000000 mINT_STAT_STALL: .equ %10000000 ;*** INT_ENB - Interrupt Enable Register; 0xFFFF9A84 *** INT_ENB: .equ $FFFF9A84 ;*** INT_ENB - Interrupt Enable Register; 0xFFFF9A84 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INT_ENB_USB_RST_EN: .equ 0 ; USB_RST Interrupt Enable INT_ENB_ERROR_EN: .equ 1 ; ERROR Interrupt Enable INT_ENB_SOF_TOK_EN: .equ 2 ; SOF_TOK Interrupt Enable INT_ENB_TOK_DNE_EN: .equ 3 ; TOK_DNE Interrupt Enable INT_ENB_SLEEP_EN: .equ 4 ; SLEEP Interrupt Enable INT_ENB_RESUME_EN: .equ 5 ; RESUME Interrupt Enable INT_ENB_ATTACH_EN: .equ 6 ; ATTACH Interrupt Enable INT_ENB_STALL_EN: .equ 7 ; STALL Interrupt Enable ; bit position masks mINT_ENB_USB_RST_EN: .equ %00000001 mINT_ENB_ERROR_EN: .equ %00000010 mINT_ENB_SOF_TOK_EN: .equ %00000100 mINT_ENB_TOK_DNE_EN: .equ %00001000 mINT_ENB_SLEEP_EN: .equ %00010000 mINT_ENB_RESUME_EN: .equ %00100000 mINT_ENB_ATTACH_EN: .equ %01000000 mINT_ENB_STALL_EN: .equ %10000000 ;*** ERR_STAT - Error Interrupt Status Register; 0xFFFF9A88 *** ERR_STAT: .equ $FFFF9A88 ;*** ERR_STAT - Error Interrupt Status Register; 0xFFFF9A88 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ERR_STAT_PID_ERR: .equ 0 ; This bit is set when the PID check field fails ERR_STAT_CRC5_EOF: .equ 1 ; When the USB Module is operating in Peripheral mode (HOST_MODE_EN=0) this interrupt will detect CRC5 errors in the token packets generated by the host. When the USB Module is operating in Host mode (HOST_MODE_EN=1) this interupt will detect End Of Frame... ERR_STAT_CRC16: .equ 2 ; This bit is set when a data packet is rejected due to a CRC16 error ERR_STAT_DFN8: .equ 3 ; This bit is set if the dta field received was not 8 bits in length. USB Specification 1.0 requires that data fields be an integral number of bytes. If the data field was not an integral number of bytes this bit will be set ERR_STAT_BTO_ERR: .equ 4 ; This bit is set when a bus turnaround timeout error occurs ERR_STAT_DMA_ERR: .equ 5 ; This bit is set if the USB Module has requested a DMA access to read a new BDT but has not been given the bus before it needs to receive or transmit data ERR_STAT_BTS_ERR: .equ 7 ; This bit is set when a bit stuff error is detected. If set the corresponding packet will be rejected due to the error ; bit position masks mERR_STAT_PID_ERR: .equ %00000001 mERR_STAT_CRC5_EOF: .equ %00000010 mERR_STAT_CRC16: .equ %00000100 mERR_STAT_DFN8: .equ %00001000 mERR_STAT_BTO_ERR: .equ %00010000 mERR_STAT_DMA_ERR: .equ %00100000 mERR_STAT_BTS_ERR: .equ %10000000 ;*** ERR_ENB - Error Interrupt Enable Register; 0xFFFF9A8C *** ERR_ENB: .equ $FFFF9A8C ;*** ERR_ENB - Error Interrupt Enable Register; 0xFFFF9A8C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ERR_ENB_PID_ERR_EN: .equ 0 ; PID_ERR Interrupt Enable ERR_ENB_CRC5_EOF_EN: .equ 1 ; CRC5/EOF Interrupt Enable ERR_ENB_CRC16_EN: .equ 2 ; CRC16 Interrupt Enable ERR_ENB_DFN8_EN: .equ 3 ; DFN8 Interrupt Enable ERR_ENB_BTO_ERR_EN: .equ 4 ; BTO_ERR Interrupt Enable ERR_ENB_DMA_ERR_EN: .equ 5 ; DMA_ERR Interrupt Enable ERR_ENB_BTS_ERR_EN: .equ 7 ; BTS_ERR Interrupt Enable ; bit position masks mERR_ENB_PID_ERR_EN: .equ %00000001 mERR_ENB_CRC5_EOF_EN: .equ %00000010 mERR_ENB_CRC16_EN: .equ %00000100 mERR_ENB_DFN8_EN: .equ %00001000 mERR_ENB_BTO_ERR_EN: .equ %00010000 mERR_ENB_DMA_ERR_EN: .equ %00100000 mERR_ENB_BTS_ERR_EN: .equ %10000000 ;*** STAT - Status Register; 0xFFFF9A90 *** STAT: .equ $FFFF9A90 ;*** STAT - Status Register; 0xFFFF9A90 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET STAT_ODD: .equ 2 ; This bit is set if the last Buffer Descriptor updated was in the odd bank of the BDT STAT_TX: .equ 3 ; Transmit Indicator STAT_ENDP0: .equ 4 ; ENDP field, bit 0 STAT_ENDP1: .equ 5 ; ENDP field, bit 1 STAT_ENDP2: .equ 6 ; ENDP field, bit 2 STAT_ENDP3: .equ 7 ; ENDP field, bit 3 ; bit position masks mSTAT_ODD: .equ %00000100 mSTAT_TX: .equ %00001000 mSTAT_ENDP0: .equ %00010000 mSTAT_ENDP1: .equ %00100000 mSTAT_ENDP2: .equ %01000000 mSTAT_ENDP3: .equ %10000000 ;*** CTL - Control Register; 0xFFFF9A94 *** CTL: .equ $FFFF9A94 ;*** CTL - Control Register; 0xFFFF9A94 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET CTL_USB_EN_SOF_EN: .equ 0 ; USB Enable. Setting this bit causes the SIE to reset all of its ODD bits to the BDTs. Thus, setting this bit will reset much of the logic in the SIE. when host mode is enabled clearing this bit will cause the SIE to stop sending SOF tokens CTL_ODD_RST: .equ 1 ; Setting this bit to 1 will reset all the BDT ODD ping/pong bits to 0, which then specifies the EVEN BDT bank CTL_RESUME: .equ 2 ; When set to 1 this bit enables the USB Module to execute resume signaling CTL_HOST_MODE_EN: .equ 3 ; When set to 1, this bit enables the USB Module to operate in Host mode. In Host mode the USB Module will perform USB transactions under the programmed control of the host processor CTL_RESET: .equ 4 ; Setting this bit enables the USB Module to generate USB reset signaling CTL_TXSUSPEND_TOKENBUSY: .equ 5 ; When the USB Module is in Host mode TOKEN_BUSY is set when the USB Module is busy executing a USB token and no more token commands should be written to the Token Register. In Target mode TXD_SUSPEND is set when the SIE has disabled packet transmission a... CTL_SE0: .equ 6 ; Live USB Single Ended Zero signal CTL_JSTATE: .equ 7 ; Live USB differential receiver JSTATE signal. The polarity of this signal is affected bythe current state of LS_EN ; bit position masks mCTL_USB_EN_SOF_EN: .equ %00000001 mCTL_ODD_RST: .equ %00000010 mCTL_RESUME: .equ %00000100 mCTL_HOST_MODE_EN: .equ %00001000 mCTL_RESET: .equ %00010000 mCTL_TXSUSPEND_TOKENBUSY: .equ %00100000 mCTL_SE0: .equ %01000000 mCTL_JSTATE: .equ %10000000 ;*** ADDR - Address Register; 0xFFFF9A98 *** ADDR: .equ $FFFF9A98 ;*** ADDR - Address Register; 0xFFFF9A98 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADDR_ADDR0: .equ 0 ; USB address. This 7-bit value defines the USB address that the USB Module will decode in peripheral mode, or transmit when in host mode, bit 0 ADDR_ADDR1: .equ 1 ; USB address. This 7-bit value defines the USB address that the USB Module will decode in peripheral mode, or transmit when in host mode, bit 1 ADDR_ADDR2: .equ 2 ; USB address. This 7-bit value defines the USB address that the USB Module will decode in peripheral mode, or transmit when in host mode, bit 2 ADDR_ADDR3: .equ 3 ; USB address. This 7-bit value defines the USB address that the USB Module will decode in peripheral mode, or transmit when in host mode, bit 3 ADDR_ADDR4: .equ 4 ; USB address. This 7-bit value defines the USB address that the USB Module will decode in peripheral mode, or transmit when in host mode, bit 4 ADDR_ADDR5: .equ 5 ; USB address. This 7-bit value defines the USB address that the USB Module will decode in peripheral mode, or transmit when in host mode, bit 5 ADDR_ADDR6: .equ 6 ; USB address. This 7-bit value defines the USB address that the USB Module will decode in peripheral mode, or transmit when in host mode, bit 6 ADDR_LS_EN: .equ 7 ; Low Speed Enable bit. This bit uniforms the USB Module that the next token command written to the token register must be performed at low speed. This will enable the USB Module to perform the necessary preamble required for low-speed data transmissions ; bit position masks mADDR_ADDR0: .equ %00000001 mADDR_ADDR1: .equ %00000010 mADDR_ADDR2: .equ %00000100 mADDR_ADDR3: .equ %00001000 mADDR_ADDR4: .equ %00010000 mADDR_ADDR5: .equ %00100000 mADDR_ADDR6: .equ %01000000 mADDR_LS_EN: .equ %10000000 ;*** BDT_PAGE_01 - BDT Page Register 1; 0xFFFF9A9C *** BDT_PAGE_01: .equ $FFFF9A9C ;*** BDT_PAGE_01 - BDT Page Register 1; 0xFFFF9A9C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET BDT_PAGE_01_BDT_BA9: .equ 1 ; BDT base address bit 9 BDT_PAGE_01_BDT_BA10: .equ 2 ; BDT base address bit 10 BDT_PAGE_01_BDT_BA11: .equ 3 ; BDT base address bit 11 BDT_PAGE_01_BDT_BA12: .equ 4 ; BDT base address bit 12 BDT_PAGE_01_BDT_BA13: .equ 5 ; BDT base address bit 13 BDT_PAGE_01_BDT_BA14: .equ 6 ; BDT base address bit 14 BDT_PAGE_01_BDT_BA15: .equ 7 ; BDT base address bit 15 ; bit position masks mBDT_PAGE_01_BDT_BA9: .equ %00000010 mBDT_PAGE_01_BDT_BA10: .equ %00000100 mBDT_PAGE_01_BDT_BA11: .equ %00001000 mBDT_PAGE_01_BDT_BA12: .equ %00010000 mBDT_PAGE_01_BDT_BA13: .equ %00100000 mBDT_PAGE_01_BDT_BA14: .equ %01000000 mBDT_PAGE_01_BDT_BA15: .equ %10000000 ;*** FRM_NUML - Frame Number Register Low; 0xFFFF9AA0 *** FRM_NUML: .equ $FFFF9AA0 ;*** FRM_NUML - Frame Number Register Low; 0xFFFF9AA0 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FRM_NUML_FRM0: .equ 0 ; Frame number bit 0 FRM_NUML_FRM1: .equ 1 ; Frame number bit 1 FRM_NUML_FRM2: .equ 2 ; Frame number bit 2 FRM_NUML_FRM3: .equ 3 ; Frame number bit 3 FRM_NUML_FRM4: .equ 4 ; Frame number bit 4 FRM_NUML_FRM5: .equ 5 ; Frame number bit 5 FRM_NUML_FRM6: .equ 6 ; Frame number bit 6 FRM_NUML_FRM7: .equ 7 ; Frame number bit 7 ; bit position masks mFRM_NUML_FRM0: .equ %00000001 mFRM_NUML_FRM1: .equ %00000010 mFRM_NUML_FRM2: .equ %00000100 mFRM_NUML_FRM3: .equ %00001000 mFRM_NUML_FRM4: .equ %00010000 mFRM_NUML_FRM5: .equ %00100000 mFRM_NUML_FRM6: .equ %01000000 mFRM_NUML_FRM7: .equ %10000000 ;*** FRM_NUMH - Frame Number Register High; 0xFFFF9AA4 *** FRM_NUMH: .equ $FFFF9AA4 ;*** FRM_NUMH - Frame Number Register High; 0xFFFF9AA4 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FRM_NUMH_FRM8: .equ 0 ; Frame number bit 8 FRM_NUMH_FRM9: .equ 1 ; Frame number bit 9 FRM_NUMH_FRM10: .equ 2 ; Frame number bit 10 ; bit position masks mFRM_NUMH_FRM8: .equ %00000001 mFRM_NUMH_FRM9: .equ %00000010 mFRM_NUMH_FRM10: .equ %00000100 ;*** TOKEN - Token Register; 0xFFFF9AA8 *** TOKEN: .equ $FFFF9AA8 ;*** TOKEN - Token Register; 0xFFFF9AA8 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TOKEN_TOKEN_ENDPT0: .equ 0 ; Endpoint address for the token command, bit 0 TOKEN_TOKEN_ENDPT1: .equ 1 ; Endpoint address for the token command, bit 1 TOKEN_TOKEN_ENDPT2: .equ 2 ; Endpoint address for the token command, bit 2 TOKEN_TOKEN_ENDPT3: .equ 3 ; Endpoint address for the token command, bit 3 TOKEN_TOKEN_PID0: .equ 4 ; Token type, bit 0 TOKEN_TOKEN_PID1: .equ 5 ; Token type, bit 1 TOKEN_TOKEN_PID2: .equ 6 ; Token type, bit 2 TOKEN_TOKEN_PID3: .equ 7 ; Token type, bit 3 ; bit position masks mTOKEN_TOKEN_ENDPT0: .equ %00000001 mTOKEN_TOKEN_ENDPT1: .equ %00000010 mTOKEN_TOKEN_ENDPT2: .equ %00000100 mTOKEN_TOKEN_ENDPT3: .equ %00001000 mTOKEN_TOKEN_PID0: .equ %00010000 mTOKEN_TOKEN_PID1: .equ %00100000 mTOKEN_TOKEN_PID2: .equ %01000000 mTOKEN_TOKEN_PID3: .equ %10000000 ;*** SOF_THLD - SOF Threshold Register; 0xFFFF9AAC *** SOF_THLD: .equ $FFFF9AAC ;*** SOF_THLD - SOF Threshold Register; 0xFFFF9AAC *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SOF_THLD_CNT0: .equ 0 ; SOF count threshold, bit 0 SOF_THLD_CNT1: .equ 1 ; SOF count threshold, bit 1 SOF_THLD_CNT2: .equ 2 ; SOF count threshold, bit 2 SOF_THLD_CNT3: .equ 3 ; SOF count threshold, bit 3 SOF_THLD_CNT4: .equ 4 ; SOF count threshold, bit 4 SOF_THLD_CNT5: .equ 5 ; SOF count threshold, bit 5 SOF_THLD_CNT6: .equ 6 ; SOF count threshold, bit 6 SOF_THLD_CNT7: .equ 7 ; SOF count threshold, bit 7 ; bit position masks mSOF_THLD_CNT0: .equ %00000001 mSOF_THLD_CNT1: .equ %00000010 mSOF_THLD_CNT2: .equ %00000100 mSOF_THLD_CNT3: .equ %00001000 mSOF_THLD_CNT4: .equ %00010000 mSOF_THLD_CNT5: .equ %00100000 mSOF_THLD_CNT6: .equ %01000000 mSOF_THLD_CNT7: .equ %10000000 ;*** BDT_PAGE_02 - BDT Page Register 2; 0xFFFF9AB0 *** BDT_PAGE_02: .equ $FFFF9AB0 ;*** BDT_PAGE_02 - BDT Page Register 2; 0xFFFF9AB0 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET BDT_PAGE_02_BDT_BA16: .equ 0 ; BDT base address bit 16 BDT_PAGE_02_BDT_BA17: .equ 1 ; BDT base address bit 17 BDT_PAGE_02_BDT_BA18: .equ 2 ; BDT base address bit 18 BDT_PAGE_02_BDT_BA19: .equ 3 ; BDT base address bit 19 BDT_PAGE_02_BDT_BA20: .equ 4 ; BDT base address bit 20 BDT_PAGE_02_BDT_BA21: .equ 5 ; BDT base address bit 21 BDT_PAGE_02_BDT_BA22: .equ 6 ; BDT base address bit 22 BDT_PAGE_02_BDT_BA23: .equ 7 ; BDT base address bit 23 ; bit position masks mBDT_PAGE_02_BDT_BA16: .equ %00000001 mBDT_PAGE_02_BDT_BA17: .equ %00000010 mBDT_PAGE_02_BDT_BA18: .equ %00000100 mBDT_PAGE_02_BDT_BA19: .equ %00001000 mBDT_PAGE_02_BDT_BA20: .equ %00010000 mBDT_PAGE_02_BDT_BA21: .equ %00100000 mBDT_PAGE_02_BDT_BA22: .equ %01000000 mBDT_PAGE_02_BDT_BA23: .equ %10000000 ;*** BDT_PAGE_03 - BDT Page Register 3; 0xFFFF9AB4 *** BDT_PAGE_03: .equ $FFFF9AB4 ;*** BDT_PAGE_03 - BDT Page Register 3; 0xFFFF9AB4 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET BDT_PAGE_03_BDT_BA24: .equ 0 ; BDT base address bit 24 BDT_PAGE_03_BDT_BA25: .equ 1 ; BDT base address bit 25 BDT_PAGE_03_BDT_BA26: .equ 2 ; BDT base address bit 26 BDT_PAGE_03_BDT_BA27: .equ 3 ; BDT base address bit 27 BDT_PAGE_03_BDT_BA28: .equ 4 ; BDT base address bit 28 BDT_PAGE_03_BDT_BA29: .equ 5 ; BDT base address bit 29 BDT_PAGE_03_BDT_BA30: .equ 6 ; BDT base address bit 30 BDT_PAGE_03_BDT_BA31: .equ 7 ; BDT base address bit 31 ; bit position masks mBDT_PAGE_03_BDT_BA24: .equ %00000001 mBDT_PAGE_03_BDT_BA25: .equ %00000010 mBDT_PAGE_03_BDT_BA26: .equ %00000100 mBDT_PAGE_03_BDT_BA27: .equ %00001000 mBDT_PAGE_03_BDT_BA28: .equ %00010000 mBDT_PAGE_03_BDT_BA29: .equ %00100000 mBDT_PAGE_03_BDT_BA30: .equ %01000000 mBDT_PAGE_03_BDT_BA31: .equ %10000000 ;*** ENDPT0 - Endpoint Control Register 0; 0xFFFF9AC0 *** ENDPT0: .equ $FFFF9AC0 ;*** ENDPT0 - Endpoint Control Register 0; 0xFFFF9AC0 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ENDPT0_EP_HSHK: .equ 0 ; When set this bet enables an endpoint to perform handshaking during a transaction to this endpoint. This bit will generally be set unless the endpoint is Isochronous ENDPT0_EP_STALL: .equ 1 ; When set this bit indicates that the endpoint is stalled ENDPT0_EP_TX_EN: .equ 2 ; This bit, when set, enables the endpoint for TX transfers ENDPT0_EP_RX_EN: .equ 3 ; This bit, when set, enables the endpoint for RX transfers ENDPT0_EP_CTL_DIS: .equ 4 ; This bit, when set, disables control (SETUP) transfers. When cleared, control transfers are enabled. This applies if and only if the EP_RX_EN and EP_TX_EN bits are also set ENDPT0_RETRY_DIS: .equ 6 ; This is a Host mode only bit and is only present in the control register for endpoint 0 (ENDPT0) ENDPT0_HOST_WO_HUB: .equ 7 ; This is a Host mode only bit and is only present in the control register for endpoint 0 (ENDPT0) ; bit position masks mENDPT0_EP_HSHK: .equ %00000001 mENDPT0_EP_STALL: .equ %00000010 mENDPT0_EP_TX_EN: .equ %00000100 mENDPT0_EP_RX_EN: .equ %00001000 mENDPT0_EP_CTL_DIS: .equ %00010000 mENDPT0_RETRY_DIS: .equ %01000000 mENDPT0_HOST_WO_HUB: .equ %10000000 ;*** ENDPT1 - Endpoint Control Register 1; 0xFFFF9AC4 *** ENDPT1: .equ $FFFF9AC4 ;*** ENDPT1 - Endpoint Control Register 1; 0xFFFF9AC4 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ENDPT1_EP_HSHK: .equ 0 ; When set this bet enables an endpoint to perform handshaking during a transaction to this endpoint. This bit will generally be set unless the endpoint is Isochronous ENDPT1_EP_STALL: .equ 1 ; When set this bit indicates that the endpoint is stalled ENDPT1_EP_TX_EN: .equ 2 ; This bit, when set, enables the endpoint for TX transfers ENDPT1_EP_RX_EN: .equ 3 ; This bit, when set, enables the endpoint for RX transfers ENDPT1_EP_CTL_DIS: .equ 4 ; This bit, when set, disables control (SETUP) transfers. When cleared, control transfers are enabled. This applies if and only if the EP_RX_EN and EP_TX_EN bits are also set ENDPT1_RETRY_DIS: .equ 6 ; Not available. Present only in endpoint 0 control register (ENDPT0) ENDPT1_HOST_WO_HUB: .equ 7 ; Not available. Present only in endpoint 0 control register (ENDPT0) ; bit position masks mENDPT1_EP_HSHK: .equ %00000001 mENDPT1_EP_STALL: .equ %00000010 mENDPT1_EP_TX_EN: .equ %00000100 mENDPT1_EP_RX_EN: .equ %00001000 mENDPT1_EP_CTL_DIS: .equ %00010000 mENDPT1_RETRY_DIS: .equ %01000000 mENDPT1_HOST_WO_HUB: .equ %10000000 ;*** ENDPT2 - Endpoint Control Register 2; 0xFFFF9AC8 *** ENDPT2: .equ $FFFF9AC8 ;*** ENDPT2 - Endpoint Control Register 2; 0xFFFF9AC8 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ENDPT2_EP_HSHK: .equ 0 ; When set this bet enables an endpoint to perform handshaking during a transaction to this endpoint. This bit will generally be set unless the endpoint is Isochronous ENDPT2_EP_STALL: .equ 1 ; When set this bit indicates that the endpoint is stalled ENDPT2_EP_TX_EN: .equ 2 ; This bit, when set, enables the endpoint for TX transfers ENDPT2_EP_RX_EN: .equ 3 ; This bit, when set, enables the endpoint for RX transfers ENDPT2_EP_CTL_DIS: .equ 4 ; This bit, when set, disables control (SETUP) transfers. When cleared, control transfers are enabled. This applies if and only if the EP_RX_EN and EP_TX_EN bits are also set ENDPT2_RETRY_DIS: .equ 6 ; Not available. Present only in endpoint 0 control register (ENDPT0) ENDPT2_HOST_WO_HUB: .equ 7 ; Not available. Present only in endpoint 0 control register (ENDPT0) ; bit position masks mENDPT2_EP_HSHK: .equ %00000001 mENDPT2_EP_STALL: .equ %00000010 mENDPT2_EP_TX_EN: .equ %00000100 mENDPT2_EP_RX_EN: .equ %00001000 mENDPT2_EP_CTL_DIS: .equ %00010000 mENDPT2_RETRY_DIS: .equ %01000000 mENDPT2_HOST_WO_HUB: .equ %10000000 ;*** ENDPT3 - Endpoint Control Register 3; 0xFFFF9ACC *** ENDPT3: .equ $FFFF9ACC ;*** ENDPT3 - Endpoint Control Register 3; 0xFFFF9ACC *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ENDPT3_EP_HSHK: .equ 0 ; When set this bet enables an endpoint to perform handshaking during a transaction to this endpoint. This bit will generally be set unless the endpoint is Isochronous ENDPT3_EP_STALL: .equ 1 ; When set this bit indicates that the endpoint is stalled ENDPT3_EP_TX_EN: .equ 2 ; This bit, when set, enables the endpoint for TX transfers ENDPT3_EP_RX_EN: .equ 3 ; This bit, when set, enables the endpoint for RX transfers ENDPT3_EP_CTL_DIS: .equ 4 ; This bit, when set, disables control (SETUP) transfers. When cleared, control transfers are enabled. This applies if and only if the EP_RX_EN and EP_TX_EN bits are also set ENDPT3_RETRY_DIS: .equ 6 ; Not available. Present only in endpoint 0 control register (ENDPT0) ENDPT3_HOST_WO_HUB: .equ 7 ; Not available. Present only in endpoint 0 control register (ENDPT0) ; bit position masks mENDPT3_EP_HSHK: .equ %00000001 mENDPT3_EP_STALL: .equ %00000010 mENDPT3_EP_TX_EN: .equ %00000100 mENDPT3_EP_RX_EN: .equ %00001000 mENDPT3_EP_CTL_DIS: .equ %00010000 mENDPT3_RETRY_DIS: .equ %01000000 mENDPT3_HOST_WO_HUB: .equ %10000000 ;*** ENDPT4 - Endpoint Control Register 4; 0xFFFF9AD0 *** ENDPT4: .equ $FFFF9AD0 ;*** ENDPT4 - Endpoint Control Register 4; 0xFFFF9AD0 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ENDPT4_EP_HSHK: .equ 0 ; When set this bet enables an endpoint to perform handshaking during a transaction to this endpoint. This bit will generally be set unless the endpoint is Isochronous ENDPT4_EP_STALL: .equ 1 ; When set this bit indicates that the endpoint is stalled ENDPT4_EP_TX_EN: .equ 2 ; This bit, when set, enables the endpoint for TX transfers ENDPT4_EP_RX_EN: .equ 3 ; This bit, when set, enables the endpoint for RX transfers ENDPT4_EP_CTL_DIS: .equ 4 ; This bit, when set, disables control (SETUP) transfers. When cleared, control transfers are enabled. This applies if and only if the EP_RX_EN and EP_TX_EN bits are also set ENDPT4_RETRY_DIS: .equ 6 ; Not available. Present only in endpoint 0 control register (ENDPT0) ENDPT4_HOST_WO_HUB: .equ 7 ; Not available. Present only in endpoint 0 control register (ENDPT0) ; bit position masks mENDPT4_EP_HSHK: .equ %00000001 mENDPT4_EP_STALL: .equ %00000010 mENDPT4_EP_TX_EN: .equ %00000100 mENDPT4_EP_RX_EN: .equ %00001000 mENDPT4_EP_CTL_DIS: .equ %00010000 mENDPT4_RETRY_DIS: .equ %01000000 mENDPT4_HOST_WO_HUB: .equ %10000000 ;*** ENDPT5 - Endpoint Control Register 5; 0xFFFF9AD4 *** ENDPT5: .equ $FFFF9AD4 ;*** ENDPT5 - Endpoint Control Register 5; 0xFFFF9AD4 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ENDPT5_EP_HSHK: .equ 0 ; When set this bet enables an endpoint to perform handshaking during a transaction to this endpoint. This bit will generally be set unless the endpoint is Isochronous ENDPT5_EP_STALL: .equ 1 ; When set this bit indicates that the endpoint is stalled ENDPT5_EP_TX_EN: .equ 2 ; This bit, when set, enables the endpoint for TX transfers ENDPT5_EP_RX_EN: .equ 3 ; This bit, when set, enables the endpoint for RX transfers ENDPT5_EP_CTL_DIS: .equ 4 ; This bit, when set, disables control (SETUP) transfers. When cleared, control transfers are enabled. This applies if and only if the EP_RX_EN and EP_TX_EN bits are also set ENDPT5_RETRY_DIS: .equ 6 ; Not available. Present only in endpoint 0 control register (ENDPT0) ENDPT5_HOST_WO_HUB: .equ 7 ; Not available. Present only in endpoint 0 control register (ENDPT0) ; bit position masks mENDPT5_EP_HSHK: .equ %00000001 mENDPT5_EP_STALL: .equ %00000010 mENDPT5_EP_TX_EN: .equ %00000100 mENDPT5_EP_RX_EN: .equ %00001000 mENDPT5_EP_CTL_DIS: .equ %00010000 mENDPT5_RETRY_DIS: .equ %01000000 mENDPT5_HOST_WO_HUB: .equ %10000000 ;*** ENDPT6 - Endpoint Control Register 6; 0xFFFF9AD8 *** ENDPT6: .equ $FFFF9AD8 ;*** ENDPT6 - Endpoint Control Register 6; 0xFFFF9AD8 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ENDPT6_EP_HSHK: .equ 0 ; When set this bet enables an endpoint to perform handshaking during a transaction to this endpoint. This bit will generally be set unless the endpoint is Isochronous ENDPT6_EP_STALL: .equ 1 ; When set this bit indicates that the endpoint is stalled ENDPT6_EP_TX_EN: .equ 2 ; This bit, when set, enables the endpoint for TX transfers ENDPT6_EP_RX_EN: .equ 3 ; This bit, when set, enables the endpoint for RX transfers ENDPT6_EP_CTL_DIS: .equ 4 ; This bit, when set, disables control (SETUP) transfers. When cleared, control transfers are enabled. This applies if and only if the EP_RX_EN and EP_TX_EN bits are also set ENDPT6_RETRY_DIS: .equ 6 ; Not available. Present only in endpoint 0 control register (ENDPT0) ENDPT6_HOST_WO_HUB: .equ 7 ; Not available. Present only in endpoint 0 control register (ENDPT0) ; bit position masks mENDPT6_EP_HSHK: .equ %00000001 mENDPT6_EP_STALL: .equ %00000010 mENDPT6_EP_TX_EN: .equ %00000100 mENDPT6_EP_RX_EN: .equ %00001000 mENDPT6_EP_CTL_DIS: .equ %00010000 mENDPT6_RETRY_DIS: .equ %01000000 mENDPT6_HOST_WO_HUB: .equ %10000000 ;*** ENDPT7 - Endpoint Control Register 7; 0xFFFF9ADC *** ENDPT7: .equ $FFFF9ADC ;*** ENDPT7 - Endpoint Control Register 7; 0xFFFF9ADC *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ENDPT7_EP_HSHK: .equ 0 ; When set this bet enables an endpoint to perform handshaking during a transaction to this endpoint. This bit will generally be set unless the endpoint is Isochronous ENDPT7_EP_STALL: .equ 1 ; When set this bit indicates that the endpoint is stalled ENDPT7_EP_TX_EN: .equ 2 ; This bit, when set, enables the endpoint for TX transfers ENDPT7_EP_RX_EN: .equ 3 ; This bit, when set, enables the endpoint for RX transfers ENDPT7_EP_CTL_DIS: .equ 4 ; This bit, when set, disables control (SETUP) transfers. When cleared, control transfers are enabled. This applies if and only if the EP_RX_EN and EP_TX_EN bits are also set ENDPT7_RETRY_DIS: .equ 6 ; Not available. Present only in endpoint 0 control register (ENDPT0) ENDPT7_HOST_WO_HUB: .equ 7 ; Not available. Present only in endpoint 0 control register (ENDPT0) ; bit position masks mENDPT7_EP_HSHK: .equ %00000001 mENDPT7_EP_STALL: .equ %00000010 mENDPT7_EP_TX_EN: .equ %00000100 mENDPT7_EP_RX_EN: .equ %00001000 mENDPT7_EP_CTL_DIS: .equ %00010000 mENDPT7_RETRY_DIS: .equ %01000000 mENDPT7_HOST_WO_HUB: .equ %10000000 ;*** ENDPT8 - Endpoint Control Register 8; 0xFFFF9AE0 *** ENDPT8: .equ $FFFF9AE0 ;*** ENDPT8 - Endpoint Control Register 8; 0xFFFF9AE0 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ENDPT8_EP_HSHK: .equ 0 ; When set this bet enables an endpoint to perform handshaking during a transaction to this endpoint. This bit will generally be set unless the endpoint is Isochronous ENDPT8_EP_STALL: .equ 1 ; When set this bit indicates that the endpoint is stalled ENDPT8_EP_TX_EN: .equ 2 ; This bit, when set, enables the endpoint for TX transfers ENDPT8_EP_RX_EN: .equ 3 ; This bit, when set, enables the endpoint for RX transfers ENDPT8_EP_CTL_DIS: .equ 4 ; This bit, when set, disables control (SETUP) transfers. When cleared, control transfers are enabled. This applies if and only if the EP_RX_EN and EP_TX_EN bits are also set ENDPT8_RETRY_DIS: .equ 6 ; Not available. Present only in endpoint 0 control register (ENDPT0) ENDPT8_HOST_WO_HUB: .equ 7 ; Not available. Present only in endpoint 0 control register (ENDPT0) ; bit position masks mENDPT8_EP_HSHK: .equ %00000001 mENDPT8_EP_STALL: .equ %00000010 mENDPT8_EP_TX_EN: .equ %00000100 mENDPT8_EP_RX_EN: .equ %00001000 mENDPT8_EP_CTL_DIS: .equ %00010000 mENDPT8_RETRY_DIS: .equ %01000000 mENDPT8_HOST_WO_HUB: .equ %10000000 ;*** ENDPT9 - Endpoint Control Register 9; 0xFFFF9AE4 *** ENDPT9: .equ $FFFF9AE4 ;*** ENDPT9 - Endpoint Control Register 9; 0xFFFF9AE4 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ENDPT9_EP_HSHK: .equ 0 ; When set this bet enables an endpoint to perform handshaking during a transaction to this endpoint. This bit will generally be set unless the endpoint is Isochronous ENDPT9_EP_STALL: .equ 1 ; When set this bit indicates that the endpoint is stalled ENDPT9_EP_TX_EN: .equ 2 ; This bit, when set, enables the endpoint for TX transfers ENDPT9_EP_RX_EN: .equ 3 ; This bit, when set, enables the endpoint for RX transfers ENDPT9_EP_CTL_DIS: .equ 4 ; This bit, when set, disables control (SETUP) transfers. When cleared, control transfers are enabled. This applies if and only if the EP_RX_EN and EP_TX_EN bits are also set ENDPT9_RETRY_DIS: .equ 6 ; Not available. Present only in endpoint 0 control register (ENDPT0) ENDPT9_HOST_WO_HUB: .equ 7 ; Not available. Present only in endpoint 0 control register (ENDPT0) ; bit position masks mENDPT9_EP_HSHK: .equ %00000001 mENDPT9_EP_STALL: .equ %00000010 mENDPT9_EP_TX_EN: .equ %00000100 mENDPT9_EP_RX_EN: .equ %00001000 mENDPT9_EP_CTL_DIS: .equ %00010000 mENDPT9_RETRY_DIS: .equ %01000000 mENDPT9_HOST_WO_HUB: .equ %10000000 ;*** ENDPT10 - Endpoint Control Register 10; 0xFFFF9AE8 *** ENDPT10: .equ $FFFF9AE8 ;*** ENDPT10 - Endpoint Control Register 10; 0xFFFF9AE8 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ENDPT10_EP_HSHK: .equ 0 ; When set this bet enables an endpoint to perform handshaking during a transaction to this endpoint. This bit will generally be set unless the endpoint is Isochronous ENDPT10_EP_STALL: .equ 1 ; When set this bit indicates that the endpoint is stalled ENDPT10_EP_TX_EN: .equ 2 ; This bit, when set, enables the endpoint for TX transfers ENDPT10_EP_RX_EN: .equ 3 ; This bit, when set, enables the endpoint for RX transfers ENDPT10_EP_CTL_DIS: .equ 4 ; This bit, when set, disables control (SETUP) transfers. When cleared, control transfers are enabled. This applies if and only if the EP_RX_EN and EP_TX_EN bits are also set ENDPT10_RETRY_DIS: .equ 6 ; Not available. Present only in endpoint 0 control register (ENDPT0) ENDPT10_HOST_WO_HUB: .equ 7 ; Not available. Present only in endpoint 0 control register (ENDPT0) ; bit position masks mENDPT10_EP_HSHK: .equ %00000001 mENDPT10_EP_STALL: .equ %00000010 mENDPT10_EP_TX_EN: .equ %00000100 mENDPT10_EP_RX_EN: .equ %00001000 mENDPT10_EP_CTL_DIS: .equ %00010000 mENDPT10_RETRY_DIS: .equ %01000000 mENDPT10_HOST_WO_HUB: .equ %10000000 ;*** ENDPT11 - Endpoint Control Register 11; 0xFFFF9AEC *** ENDPT11: .equ $FFFF9AEC ;*** ENDPT11 - Endpoint Control Register 11; 0xFFFF9AEC *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ENDPT11_EP_HSHK: .equ 0 ; When set this bet enables an endpoint to perform handshaking during a transaction to this endpoint. This bit will generally be set unless the endpoint is Isochronous ENDPT11_EP_STALL: .equ 1 ; When set this bit indicates that the endpoint is stalled ENDPT11_EP_TX_EN: .equ 2 ; This bit, when set, enables the endpoint for TX transfers ENDPT11_EP_RX_EN: .equ 3 ; This bit, when set, enables the endpoint for RX transfers ENDPT11_EP_CTL_DIS: .equ 4 ; This bit, when set, disables control (SETUP) transfers. When cleared, control transfers are enabled. This applies if and only if the EP_RX_EN and EP_TX_EN bits are also set ENDPT11_RETRY_DIS: .equ 6 ; Not available. Present only in endpoint 0 control register (ENDPT0) ENDPT11_HOST_WO_HUB: .equ 7 ; Not available. Present only in endpoint 0 control register (ENDPT0) ; bit position masks mENDPT11_EP_HSHK: .equ %00000001 mENDPT11_EP_STALL: .equ %00000010 mENDPT11_EP_TX_EN: .equ %00000100 mENDPT11_EP_RX_EN: .equ %00001000 mENDPT11_EP_CTL_DIS: .equ %00010000 mENDPT11_RETRY_DIS: .equ %01000000 mENDPT11_HOST_WO_HUB: .equ %10000000 ;*** ENDPT12 - Endpoint Control Register 12; 0xFFFF9AF0 *** ENDPT12: .equ $FFFF9AF0 ;*** ENDPT12 - Endpoint Control Register 12; 0xFFFF9AF0 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ENDPT12_EP_HSHK: .equ 0 ; When set this bet enables an endpoint to perform handshaking during a transaction to this endpoint. This bit will generally be set unless the endpoint is Isochronous ENDPT12_EP_STALL: .equ 1 ; When set this bit indicates that the endpoint is stalled ENDPT12_EP_TX_EN: .equ 2 ; This bit, when set, enables the endpoint for TX transfers ENDPT12_EP_RX_EN: .equ 3 ; This bit, when set, enables the endpoint for RX transfers ENDPT12_EP_CTL_DIS: .equ 4 ; This bit, when set, disables control (SETUP) transfers. When cleared, control transfers are enabled. This applies if and only if the EP_RX_EN and EP_TX_EN bits are also set ENDPT12_RETRY_DIS: .equ 6 ; Not available. Present only in endpoint 0 control register (ENDPT0) ENDPT12_HOST_WO_HUB: .equ 7 ; Not available. Present only in endpoint 0 control register (ENDPT0) ; bit position masks mENDPT12_EP_HSHK: .equ %00000001 mENDPT12_EP_STALL: .equ %00000010 mENDPT12_EP_TX_EN: .equ %00000100 mENDPT12_EP_RX_EN: .equ %00001000 mENDPT12_EP_CTL_DIS: .equ %00010000 mENDPT12_RETRY_DIS: .equ %01000000 mENDPT12_HOST_WO_HUB: .equ %10000000 ;*** ENDPT13 - Endpoint Control Register 13; 0xFFFF9AF4 *** ENDPT13: .equ $FFFF9AF4 ;*** ENDPT13 - Endpoint Control Register 13; 0xFFFF9AF4 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ENDPT13_EP_HSHK: .equ 0 ; When set this bet enables an endpoint to perform handshaking during a transaction to this endpoint. This bit will generally be set unless the endpoint is Isochronous ENDPT13_EP_STALL: .equ 1 ; When set this bit indicates that the endpoint is stalled ENDPT13_EP_TX_EN: .equ 2 ; This bit, when set, enables the endpoint for TX transfers ENDPT13_EP_RX_EN: .equ 3 ; This bit, when set, enables the endpoint for RX transfers ENDPT13_EP_CTL_DIS: .equ 4 ; This bit, when set, disables control (SETUP) transfers. When cleared, control transfers are enabled. This applies if and only if the EP_RX_EN and EP_TX_EN bits are also set ENDPT13_RETRY_DIS: .equ 6 ; Not available. Present only in endpoint 0 control register (ENDPT0) ENDPT13_HOST_WO_HUB: .equ 7 ; Not available. Present only in endpoint 0 control register (ENDPT0) ; bit position masks mENDPT13_EP_HSHK: .equ %00000001 mENDPT13_EP_STALL: .equ %00000010 mENDPT13_EP_TX_EN: .equ %00000100 mENDPT13_EP_RX_EN: .equ %00001000 mENDPT13_EP_CTL_DIS: .equ %00010000 mENDPT13_RETRY_DIS: .equ %01000000 mENDPT13_HOST_WO_HUB: .equ %10000000 ;*** ENDPT14 - Endpoint Control Register 14; 0xFFFF9AF8 *** ENDPT14: .equ $FFFF9AF8 ;*** ENDPT14 - Endpoint Control Register 14; 0xFFFF9AF8 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ENDPT14_EP_HSHK: .equ 0 ; When set this bet enables an endpoint to perform handshaking during a transaction to this endpoint. This bit will generally be set unless the endpoint is Isochronous ENDPT14_EP_STALL: .equ 1 ; When set this bit indicates that the endpoint is stalled ENDPT14_EP_TX_EN: .equ 2 ; This bit, when set, enables the endpoint for TX transfers ENDPT14_EP_RX_EN: .equ 3 ; This bit, when set, enables the endpoint for RX transfers ENDPT14_EP_CTL_DIS: .equ 4 ; This bit, when set, disables control (SETUP) transfers. When cleared, control transfers are enabled. This applies if and only if the EP_RX_EN and EP_TX_EN bits are also set ENDPT14_RETRY_DIS: .equ 6 ; Not available. Present only in endpoint 0 control register (ENDPT0) ENDPT14_HOST_WO_HUB: .equ 7 ; Not available. Present only in endpoint 0 control register (ENDPT0) ; bit position masks mENDPT14_EP_HSHK: .equ %00000001 mENDPT14_EP_STALL: .equ %00000010 mENDPT14_EP_TX_EN: .equ %00000100 mENDPT14_EP_RX_EN: .equ %00001000 mENDPT14_EP_CTL_DIS: .equ %00010000 mENDPT14_RETRY_DIS: .equ %01000000 mENDPT14_HOST_WO_HUB: .equ %10000000 ;*** ENDPT15 - Endpoint Control Register 15; 0xFFFF9AFC *** ENDPT15: .equ $FFFF9AFC ;*** ENDPT15 - Endpoint Control Register 15; 0xFFFF9AFC *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ENDPT15_EP_HSHK: .equ 0 ; When set this bet enables an endpoint to perform handshaking during a transaction to this endpoint. This bit will generally be set unless the endpoint is Isochronous ENDPT15_EP_STALL: .equ 1 ; When set this bit indicates that the endpoint is stalled ENDPT15_EP_TX_EN: .equ 2 ; This bit, when set, enables the endpoint for TX transfers ENDPT15_EP_RX_EN: .equ 3 ; This bit, when set, enables the endpoint for RX transfers ENDPT15_EP_CTL_DIS: .equ 4 ; This bit, when set, disables control (SETUP) transfers. When cleared, control transfers are enabled. This applies if and only if the EP_RX_EN and EP_TX_EN bits are also set ENDPT15_RETRY_DIS: .equ 6 ; Not available. Present only in endpoint 0 control register (ENDPT0) ENDPT15_HOST_WO_HUB: .equ 7 ; Not available. Present only in endpoint 0 control register (ENDPT0) ; bit position masks mENDPT15_EP_HSHK: .equ %00000001 mENDPT15_EP_STALL: .equ %00000010 mENDPT15_EP_TX_EN: .equ %00000100 mENDPT15_EP_RX_EN: .equ %00001000 mENDPT15_EP_CTL_DIS: .equ %00010000 mENDPT15_RETRY_DIS: .equ %01000000 mENDPT15_HOST_WO_HUB: .equ %10000000 ;*** USB_CTRL - USB Control Register; 0xFFFF9B00 *** USB_CTRL: .equ $FFFF9B00 ;*** USB_CTRL - USB Control Register; 0xFFFF9B00 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET USB_CTRL_CLK_SRC0: .equ 0 ; Determines the clock source for the USB 48 MHZ clock, bit 0 USB_CTRL_CLK_SRC1: .equ 1 ; Determines the clock source for the USB 48 MHZ clock, bit 1 USB_CTRL_PDE: .equ 6 ; Enables the non-functional weak pulldowns on the USB transceiver USB_CTRL_SUSP: .equ 7 ; Places the USB transceiver into the suspend state ; bit position masks mUSB_CTRL_CLK_SRC0: .equ %00000001 mUSB_CTRL_CLK_SRC1: .equ %00000010 mUSB_CTRL_PDE: .equ %01000000 mUSB_CTRL_SUSP: .equ %10000000 ;*** USB_OTG_OBSERVE - USB OTG Observe Register; 0xFFFF9B04 *** USB_OTG_OBSERVE: .equ $FFFF9B04 ;*** USB_OTG_OBSERVE - USB OTG Observe Register; 0xFFFF9B04 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET USB_OTG_OBSERVE_DM_PD: .equ 4 ; Provides observability of the D- Pull Down signal output from the USB OTG module. Useful when interfacing to an external OTG control module via a serial interface USB_OTG_OBSERVE_DP_PD: .equ 6 ; Provides observability of the D+ Pull Down signal output from the USB OTG module. Useful when interfacing to an external OTG control module via a serial interface USB_OTG_OBSERVE_DP_PU: .equ 7 ; Provides observability of the D+ Pull Up signal output from the USB OTG module. This bit is useful when interfacing to anexternal OTG control module via a serial interface. Useful when interfacing to an external OTG control module via a serial interface ; bit position masks mUSB_OTG_OBSERVE_DM_PD: .equ %00010000 mUSB_OTG_OBSERVE_DP_PD: .equ %01000000 mUSB_OTG_OBSERVE_DP_PU: .equ %10000000 ;*** USB_OTG_CONTROL - USB OTG Control Register; 0xFFFF9B08 *** USB_OTG_CONTROL: .equ $FFFF9B08 ;*** USB_OTG_CONTROL - USB OTG Control Register; 0xFFFF9B08 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET USB_OTG_CONTROL_SESSEND: .equ 0 ; Provides observability of the Session End signal output from the USB OTG module. Useful when interfacing to an external OTG control module via a serial interface USB_OTG_CONTROL_SESSVLD: .equ 1 ; Provides observability of the Session Valid signal output from the USB OTG module. Useful when interfacing to an external OTG control module via a serial interface USB_OTG_CONTROL_VBUSVLD: .equ 2 ; Provides control of the VBUS Valid signal into the USB OTG module if a pin has not been configured for this function. Useful when interfacing to an external OTG control module via a serial interface USB_OTG_CONTROL_ID: .equ 3 ; Provides control of the USB ID signal into the USB OTG module if a pin has not been configured for this function. Useful when interfacing to an external OTG control module via a serial interface USB_OTG_CONTROL_DPPULLUP_NONOTG: .equ 4 ; Provides control of the DP PULLUP in the USB OTG module, if USB is configured in non-OTG device mode ; bit position masks mUSB_OTG_CONTROL_SESSEND: .equ %00000001 mUSB_OTG_CONTROL_SESSVLD: .equ %00000010 mUSB_OTG_CONTROL_VBUSVLD: .equ %00000100 mUSB_OTG_CONTROL_ID: .equ %00001000 mUSB_OTG_CONTROL_DPPULLUP_NONOTG: .equ %00010000 ;*** USBTRC0 - USB Transceiver and Regulator Control Register 0; 0xFFFF9B0C *** USBTRC0: .equ $FFFF9B0C ;*** USBTRC0 - USB Transceiver and Regulator Control Register 0; 0xFFFF9B0C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET USBTRC0_USB_RESUME_INT: .equ 0 ; USB Asynchronous Interrupt USBTRC0_USBVREN: .equ 2 ; USB voltage regulator enable USBTRC0_USBRESMEN: .equ 5 ; Allows the USB module to send an asynchronous wakeup event upon detection of resume signaling on the USB bus USBTRC0_USBPU: .equ 6 ; Pull-up resistor on the USBDP line USBTRC0_USBRESET: .equ 7 ; Generates a hard reset to the USB module ; bit position masks mUSBTRC0_USB_RESUME_INT: .equ %00000001 mUSBTRC0_USBVREN: .equ %00000100 mUSBTRC0_USBRESMEN: .equ %00100000 mUSBTRC0_USBPU: .equ %01000000 mUSBTRC0_USBRESET: .equ %10000000 ;*** OTGPIN - USB OTG Pin Control Register; 0xFFFF9B10 *** OTGPIN: .equ $FFFF9B10 ;*** OTGPIN - USB OTG Pin Control Register; 0xFFFF9B10 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET OTGPIN_SESSVLD: .equ 0 ; Session Valid Pin Enable OTGPIN_SESSEND: .equ 1 ; Session End Pin Enable OTGPIN_VBUSVLD: .equ 2 ; Valid Pin Enable OTGPIN_PULLUP: .equ 3 ; Pull-up Pin Enable OTGPIN_DPDOWN: .equ 4 ; DPDOWN Pin Enable OTGPIN_DMDOWN: .equ 5 ; DMDOWN Pin Enable OTGPIN_USBID: .equ 6 ; USB_ID Pin Enable ; bit position masks mOTGPIN_SESSVLD: .equ %00000001 mOTGPIN_SESSEND: .equ %00000010 mOTGPIN_VBUSVLD: .equ %00000100 mOTGPIN_PULLUP: .equ %00001000 mOTGPIN_DPDOWN: .equ %00010000 mOTGPIN_DMDOWN: .equ %00100000 mOTGPIN_USBID: .equ %01000000 ;*** MBCSAR0 - Chip Select Address Register 0; 0xFFFFE800 *** MBCSAR0: .equ $FFFFE800 ;*** MBCSAR0 - Chip Select Address Register 0; 0xFFFFE800 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET MBCSAR0_BA0: .equ 16 ; Base address. Defines the base address for memory dedicated to chip select CS0. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 0 MBCSAR0_BA1: .equ 17 ; Base address. Defines the base address for memory dedicated to chip select CS0. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 1 MBCSAR0_BA2: .equ 18 ; Base address. Defines the base address for memory dedicated to chip select CS0. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 2 MBCSAR0_BA3: .equ 19 ; Base address. Defines the base address for memory dedicated to chip select CS0. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 3 MBCSAR0_BA4: .equ 20 ; Base address. Defines the base address for memory dedicated to chip select CS0. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 4 MBCSAR0_BA5: .equ 21 ; Base address. Defines the base address for memory dedicated to chip select CS0. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 5 MBCSAR0_BA6: .equ 22 ; Base address. Defines the base address for memory dedicated to chip select CS0. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 6 MBCSAR0_BA7: .equ 23 ; Base address. Defines the base address for memory dedicated to chip select CS0. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 7 MBCSAR0_BA8: .equ 24 ; Base address. Defines the base address for memory dedicated to chip select CS0. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 8 MBCSAR0_BA9: .equ 25 ; Base address. Defines the base address for memory dedicated to chip select CS0. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 9 MBCSAR0_BA10: .equ 26 ; Base address. Defines the base address for memory dedicated to chip select CS0. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 10 MBCSAR0_BA11: .equ 27 ; Base address. Defines the base address for memory dedicated to chip select CS0. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 11 MBCSAR0_BA12: .equ 28 ; Base address. Defines the base address for memory dedicated to chip select CS0. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 12 MBCSAR0_BA13: .equ 29 ; Base address. Defines the base address for memory dedicated to chip select CS0. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 13 MBCSAR0_BA14: .equ 30 ; Base address. Defines the base address for memory dedicated to chip select CS0. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 14 MBCSAR0_BA15: .equ 31 ; Base address. Defines the base address for memory dedicated to chip select CS0. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 15 ; bit position masks mMBCSAR0_BA0: .equ %10000000000000000 mMBCSAR0_BA1: .equ %100000000000000000 mMBCSAR0_BA2: .equ %1000000000000000000 mMBCSAR0_BA3: .equ %10000000000000000000 mMBCSAR0_BA4: .equ %100000000000000000000 mMBCSAR0_BA5: .equ %1000000000000000000000 mMBCSAR0_BA6: .equ %10000000000000000000000 mMBCSAR0_BA7: .equ %100000000000000000000000 mMBCSAR0_BA8: .equ %1000000000000000000000000 mMBCSAR0_BA9: .equ %10000000000000000000000000 mMBCSAR0_BA10: .equ %100000000000000000000000000 mMBCSAR0_BA11: .equ %1000000000000000000000000000 mMBCSAR0_BA12: .equ %10000000000000000000000000000 mMBCSAR0_BA13: .equ %100000000000000000000000000000 mMBCSAR0_BA14: .equ %1000000000000000000000000000000 mMBCSAR0_BA15: .equ %10000000000000000000000000000000 ;*** MBCSMR0 - Chip Select Mask Register 0; 0xFFFFE804 *** MBCSMR0: .equ $FFFFE804 ;*** MBCSMR0 - Chip Select Mask Register 0; 0xFFFFE804 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET MBCSMR0_V: .equ 0 ; Valid bit. Indicates whether the corresponding CSAR, CSMR, and CSCR contents are valid. Programmed chip selects do not assert until V is set (except for CS0, which acts as the global chip select). Reset clears each CSMRn[V] MBCSMR0_WP: .equ 8 ; Write protect. Controls write accesses to the address range in the corresponding CSAR. Attempting to write to the range of addresses for which CSAR0[WP] = 1 results in the appropriate chip select not being selected. No exception occurs MBCSMR0_BAM0: .equ 16 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 0 MBCSMR0_BAM1: .equ 17 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 1 MBCSMR0_BAM2: .equ 18 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 2 MBCSMR0_BAM3: .equ 19 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 3 MBCSMR0_BAM4: .equ 20 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 4 MBCSMR0_BAM5: .equ 21 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 5 MBCSMR0_BAM6: .equ 22 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 6 MBCSMR0_BAM7: .equ 23 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 7 MBCSMR0_BAM8: .equ 24 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 8 MBCSMR0_BAM9: .equ 25 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 9 MBCSMR0_BAM10: .equ 26 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 10 MBCSMR0_BAM11: .equ 27 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 11 MBCSMR0_BAM12: .equ 28 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 12 MBCSMR0_BAM13: .equ 29 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 13 MBCSMR0_BAM14: .equ 30 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 14 MBCSMR0_BAM15: .equ 31 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 15 ; bit position masks mMBCSMR0_V: .equ %00000001 mMBCSMR0_WP: .equ %100000000 mMBCSMR0_BAM0: .equ %10000000000000000 mMBCSMR0_BAM1: .equ %100000000000000000 mMBCSMR0_BAM2: .equ %1000000000000000000 mMBCSMR0_BAM3: .equ %10000000000000000000 mMBCSMR0_BAM4: .equ %100000000000000000000 mMBCSMR0_BAM5: .equ %1000000000000000000000 mMBCSMR0_BAM6: .equ %10000000000000000000000 mMBCSMR0_BAM7: .equ %100000000000000000000000 mMBCSMR0_BAM8: .equ %1000000000000000000000000 mMBCSMR0_BAM9: .equ %10000000000000000000000000 mMBCSMR0_BAM10: .equ %100000000000000000000000000 mMBCSMR0_BAM11: .equ %1000000000000000000000000000 mMBCSMR0_BAM12: .equ %10000000000000000000000000000 mMBCSMR0_BAM13: .equ %100000000000000000000000000000 mMBCSMR0_BAM14: .equ %1000000000000000000000000000000 mMBCSMR0_BAM15: .equ %10000000000000000000000000000000 ;*** MBCSCR0 - Chip Select Control Register 0; 0xFFFFE808 *** MBCSCR0: .equ $FFFFE808 ;*** MBCSCR0 - Chip Select Control Register 0; 0xFFFFE808 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET MBCSCR0_PS0: .equ 6 ; Port size. Specifies the width of the data associated with each chip select. It determines where data is driven during write cycles and where data is sampled during read cycles, bit 0 MBCSCR0_PS1: .equ 7 ; Port size. Specifies the width of the data associated with each chip select. It determines where data is driven during write cycles and where data is sampled during read cycles, bit 1 MBCSCR0_AA: .equ 8 ; Auto-acknowledge enable. Determines the assertion of the internal transfer acknowledge for accesses specified by the chip select address. Note that if AA = 1 for a corresponding CSn and the external system asserts an external TA before the wait-state co... MBCSCR0_MUX: .equ 9 ; Multiplexed mode MBCSCR0_WS0: .equ 10 ; Wait states. The number of wait states inserted after FB_CSn asserts and before an internal transfer acknowledge
is generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63 wait states), bit 0 MBCSCR0_WS1: .equ 11 ; Wait states. The number of wait states inserted after FB_CSn asserts and before an internal transfer acknowledge
is generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63 wait states), bit 1 MBCSCR0_WS2: .equ 12 ; Wait states. The number of wait states inserted after FB_CSn asserts and before an internal transfer acknowledge
is generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63 wait states), bit 2 MBCSCR0_WS3: .equ 13 ; Wait states. The number of wait states inserted after FB_CSn asserts and before an internal transfer acknowledge
is generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63 wait states), bit 3 MBCSCR0_WS4: .equ 14 ; Wait states. The number of wait states inserted after FB_CSn asserts and before an internal transfer acknowledge
is generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63 wait states), bit 4 MBCSCR0_WS5: .equ 15 ; Wait states. The number of wait states inserted after FB_CSn asserts and before an internal transfer acknowledge
is generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63 wait states), bit 5 MBCSCR0_WRAH0: .equ 16 ; Write address hold or deselect, bit 0 MBCSCR0_WRAH1: .equ 17 ; Write address hold or deselect, bit 1 MBCSCR0_RDAH0: .equ 18 ; Read address hold or deselect, bit 0 MBCSCR0_RDAH1: .equ 19 ; Read address hold or deselect, bit 1 MBCSCR0_ASET0: .equ 20 ; Address setup, bit 0 MBCSCR0_ASET1: .equ 21 ; Address setup, bit 1 ; bit position masks mMBCSCR0_PS0: .equ %01000000 mMBCSCR0_PS1: .equ %10000000 mMBCSCR0_AA: .equ %100000000 mMBCSCR0_MUX: .equ %1000000000 mMBCSCR0_WS0: .equ %10000000000 mMBCSCR0_WS1: .equ %100000000000 mMBCSCR0_WS2: .equ %1000000000000 mMBCSCR0_WS3: .equ %10000000000000 mMBCSCR0_WS4: .equ %100000000000000 mMBCSCR0_WS5: .equ %1000000000000000 mMBCSCR0_WRAH0: .equ %10000000000000000 mMBCSCR0_WRAH1: .equ %100000000000000000 mMBCSCR0_RDAH0: .equ %1000000000000000000 mMBCSCR0_RDAH1: .equ %10000000000000000000 mMBCSCR0_ASET0: .equ %100000000000000000000 mMBCSCR0_ASET1: .equ %1000000000000000000000 ;*** MBCSAR1 - Chip Select Address Register 1; 0xFFFFE80C *** MBCSAR1: .equ $FFFFE80C ;*** MBCSAR1 - Chip Select Address Register 1; 0xFFFFE80C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET MBCSAR1_BA0: .equ 16 ; Base address. Defines the base address for memory dedicated to chip select CS1. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 0 MBCSAR1_BA1: .equ 17 ; Base address. Defines the base address for memory dedicated to chip select CS1. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 1 MBCSAR1_BA2: .equ 18 ; Base address. Defines the base address for memory dedicated to chip select CS1. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 2 MBCSAR1_BA3: .equ 19 ; Base address. Defines the base address for memory dedicated to chip select CS1. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 3 MBCSAR1_BA4: .equ 20 ; Base address. Defines the base address for memory dedicated to chip select CS1. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 4 MBCSAR1_BA5: .equ 21 ; Base address. Defines the base address for memory dedicated to chip select CS1. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 5 MBCSAR1_BA6: .equ 22 ; Base address. Defines the base address for memory dedicated to chip select CS1. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 6 MBCSAR1_BA7: .equ 23 ; Base address. Defines the base address for memory dedicated to chip select CS1. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 7 MBCSAR1_BA8: .equ 24 ; Base address. Defines the base address for memory dedicated to chip select CS1. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 8 MBCSAR1_BA9: .equ 25 ; Base address. Defines the base address for memory dedicated to chip select CS1. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 9 MBCSAR1_BA10: .equ 26 ; Base address. Defines the base address for memory dedicated to chip select CS1. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 10 MBCSAR1_BA11: .equ 27 ; Base address. Defines the base address for memory dedicated to chip select CS1. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 11 MBCSAR1_BA12: .equ 28 ; Base address. Defines the base address for memory dedicated to chip select CS1. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 12 MBCSAR1_BA13: .equ 29 ; Base address. Defines the base address for memory dedicated to chip select CS1. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 13 MBCSAR1_BA14: .equ 30 ; Base address. Defines the base address for memory dedicated to chip select CS1. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 14 MBCSAR1_BA15: .equ 31 ; Base address. Defines the base address for memory dedicated to chip select CS1. BA is compared to bits 31-16 on the internal address bus to determine if chip select memory is being accessed, bit 15 ; bit position masks mMBCSAR1_BA0: .equ %10000000000000000 mMBCSAR1_BA1: .equ %100000000000000000 mMBCSAR1_BA2: .equ %1000000000000000000 mMBCSAR1_BA3: .equ %10000000000000000000 mMBCSAR1_BA4: .equ %100000000000000000000 mMBCSAR1_BA5: .equ %1000000000000000000000 mMBCSAR1_BA6: .equ %10000000000000000000000 mMBCSAR1_BA7: .equ %100000000000000000000000 mMBCSAR1_BA8: .equ %1000000000000000000000000 mMBCSAR1_BA9: .equ %10000000000000000000000000 mMBCSAR1_BA10: .equ %100000000000000000000000000 mMBCSAR1_BA11: .equ %1000000000000000000000000000 mMBCSAR1_BA12: .equ %10000000000000000000000000000 mMBCSAR1_BA13: .equ %100000000000000000000000000000 mMBCSAR1_BA14: .equ %1000000000000000000000000000000 mMBCSAR1_BA15: .equ %10000000000000000000000000000000 ;*** MBCSMR1 - Chip Select Mask Register 1; 0xFFFFE810 *** MBCSMR1: .equ $FFFFE810 ;*** MBCSMR1 - Chip Select Mask Register 1; 0xFFFFE810 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET MBCSMR1_V: .equ 0 ; Valid bit. Indicates whether the corresponding CSAR, CSMR, and CSCR contents are valid. Programmed chip selects do not assert until V is set. Reset clears each CSMRn[V] MBCSMR1_WP: .equ 8 ; Write protect. Controls write accesses to the address range in the corresponding CSAR. Attempting to write to the range of addresses for which CSAR0[WP] = 1 results results in a bus error termination of the internal cycle and no external
cycle MBCSMR1_BAM0: .equ 16 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 0 MBCSMR1_BAM1: .equ 17 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 1 MBCSMR1_BAM2: .equ 18 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 2 MBCSMR1_BAM3: .equ 19 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 3 MBCSMR1_BAM4: .equ 20 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 4 MBCSMR1_BAM5: .equ 21 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 5 MBCSMR1_BAM6: .equ 22 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 6 MBCSMR1_BAM7: .equ 23 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 7 MBCSMR1_BAM8: .equ 24 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 8 MBCSMR1_BAM9: .equ 25 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 9 MBCSMR1_BAM10: .equ 26 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 10 MBCSMR1_BAM11: .equ 27 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 11 MBCSMR1_BAM12: .equ 28 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 12 MBCSMR1_BAM13: .equ 29 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 13 MBCSMR1_BAM14: .equ 30 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 14 MBCSMR1_BAM15: .equ 31 ; Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode, bit 15 ; bit position masks mMBCSMR1_V: .equ %00000001 mMBCSMR1_WP: .equ %100000000 mMBCSMR1_BAM0: .equ %10000000000000000 mMBCSMR1_BAM1: .equ %100000000000000000 mMBCSMR1_BAM2: .equ %1000000000000000000 mMBCSMR1_BAM3: .equ %10000000000000000000 mMBCSMR1_BAM4: .equ %100000000000000000000 mMBCSMR1_BAM5: .equ %1000000000000000000000 mMBCSMR1_BAM6: .equ %10000000000000000000000 mMBCSMR1_BAM7: .equ %100000000000000000000000 mMBCSMR1_BAM8: .equ %1000000000000000000000000 mMBCSMR1_BAM9: .equ %10000000000000000000000000 mMBCSMR1_BAM10: .equ %100000000000000000000000000 mMBCSMR1_BAM11: .equ %1000000000000000000000000000 mMBCSMR1_BAM12: .equ %10000000000000000000000000000 mMBCSMR1_BAM13: .equ %100000000000000000000000000000 mMBCSMR1_BAM14: .equ %1000000000000000000000000000000 mMBCSMR1_BAM15: .equ %10000000000000000000000000000000 ;*** MBCSCR1 - Chip Select Control Register 1; 0xFFFFE814 *** MBCSCR1: .equ $FFFFE814 ;*** MBCSCR1 - Chip Select Control Register 1; 0xFFFFE814 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET MBCSCR1_PS0: .equ 6 ; Port size. Specifies the width of the data associated with each chip select. It determines where data is driven during write cycles and where data is sampled during read cycles, bit 0 MBCSCR1_PS1: .equ 7 ; Port size. Specifies the width of the data associated with each chip select. It determines where data is driven during write cycles and where data is sampled during read cycles, bit 1 MBCSCR1_AA: .equ 8 ; Auto-acknowledge enable. Determines the assertion of the internal transfer acknowledge for accesses specified by the chip select address. Note that if AA = 1 for a corresponding CSn and the external system asserts an external TA before the wait-state co... MBCSCR1_MUX: .equ 9 ; Multiplexed mode MBCSCR1_WS0: .equ 10 ; Wait states. The number of wait states inserted after FB_CSn asserts and before an internal transfer acknowledge
is generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63 wait states), bit 0 MBCSCR1_WS1: .equ 11 ; Wait states. The number of wait states inserted after FB_CSn asserts and before an internal transfer acknowledge
is generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63 wait states), bit 1 MBCSCR1_WS2: .equ 12 ; Wait states. The number of wait states inserted after FB_CSn asserts and before an internal transfer acknowledge
is generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63 wait states), bit 2 MBCSCR1_WS3: .equ 13 ; Wait states. The number of wait states inserted after FB_CSn asserts and before an internal transfer acknowledge
is generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63 wait states), bit 3 MBCSCR1_WS4: .equ 14 ; Wait states. The number of wait states inserted after FB_CSn asserts and before an internal transfer acknowledge
is generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63 wait states), bit 4 MBCSCR1_WS5: .equ 15 ; Wait states. The number of wait states inserted after FB_CSn asserts and before an internal transfer acknowledge
is generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63 wait states), bit 5 MBCSCR1_WRAH0: .equ 16 ; Write address hold or deselect, bit 0 MBCSCR1_WRAH1: .equ 17 ; Write address hold or deselect, bit 1 MBCSCR1_RDAH0: .equ 18 ; Read address hold or deselect, bit 0 MBCSCR1_RDAH1: .equ 19 ; Read address hold or deselect, bit 1 MBCSCR1_ASET0: .equ 20 ; Address setup, bit 0 MBCSCR1_ASET1: .equ 21 ; Address setup, bit 1 ; bit position masks mMBCSCR1_PS0: .equ %01000000 mMBCSCR1_PS1: .equ %10000000 mMBCSCR1_AA: .equ %100000000 mMBCSCR1_MUX: .equ %1000000000 mMBCSCR1_WS0: .equ %10000000000 mMBCSCR1_WS1: .equ %100000000000 mMBCSCR1_WS2: .equ %1000000000000 mMBCSCR1_WS3: .equ %10000000000000 mMBCSCR1_WS4: .equ %100000000000000 mMBCSCR1_WS5: .equ %1000000000000000 mMBCSCR1_WRAH0: .equ %10000000000000000 mMBCSCR1_WRAH1: .equ %100000000000000000 mMBCSCR1_RDAH0: .equ %1000000000000000000 mMBCSCR1_RDAH1: .equ %10000000000000000000 mMBCSCR1_ASET0: .equ %100000000000000000000 mMBCSCR1_ASET1: .equ %1000000000000000000000 ;*** INTC_FRC - INTC Force Interrupt Register; 0xFFFFFFD0 *** INTC_FRC: .equ $FFFFFFD0 ;*** INTC_FRC - INTC Force Interrupt Register; 0xFFFFFFD0 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_FRC_LVL7: .equ 0 ; Force Level 7 interrupt INTC_FRC_LVL6: .equ 1 ; Force Level 6 interrupt INTC_FRC_LVL5: .equ 2 ; Force Level 5 interrupt INTC_FRC_LVL4: .equ 3 ; Force Level 4 interrupt INTC_FRC_LVL3: .equ 4 ; Force Level 3 interrupt INTC_FRC_LVL2: .equ 5 ; Force Level 2 interrupt INTC_FRC_LVL1: .equ 6 ; Force Level 1 interrupt ; bit position masks mINTC_FRC_LVL7: .equ %00000001 mINTC_FRC_LVL6: .equ %00000010 mINTC_FRC_LVL5: .equ %00000100 mINTC_FRC_LVL4: .equ %00001000 mINTC_FRC_LVL3: .equ %00010000 mINTC_FRC_LVL2: .equ %00100000 mINTC_FRC_LVL1: .equ %01000000 ;*** INTC_PL6P7 - INTC Programmable Level 6, Priority 7 Register; 0xFFFFFFD8 *** INTC_PL6P7: .equ $FFFFFFD8 ;*** INTC_PL6P7 - INTC Programmable Level 6, Priority 7 Register; 0xFFFFFFD8 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_PL6P7_REQN0: .equ 0 ; Request number, bit 0 INTC_PL6P7_REQN1: .equ 1 ; Request number, bit 1 INTC_PL6P7_REQN2: .equ 2 ; Request number, bit 2 INTC_PL6P7_REQN3: .equ 3 ; Request number, bit 3 INTC_PL6P7_REQN4: .equ 4 ; Request number, bit 4 INTC_PL6P7_REQN5: .equ 5 ; Request number, bit 5 ; bit position masks mINTC_PL6P7_REQN0: .equ %00000001 mINTC_PL6P7_REQN1: .equ %00000010 mINTC_PL6P7_REQN2: .equ %00000100 mINTC_PL6P7_REQN3: .equ %00001000 mINTC_PL6P7_REQN4: .equ %00010000 mINTC_PL6P7_REQN5: .equ %00100000 ;*** INTC_PL6P6 - INTC Programmable Level 6, Priority 6 Register; 0xFFFFFFD9 *** INTC_PL6P6: .equ $FFFFFFD9 ;*** INTC_PL6P6 - INTC Programmable Level 6, Priority 6 Register; 0xFFFFFFD9 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_PL6P6_REQN0: .equ 0 ; Request number, bit 0 INTC_PL6P6_REQN1: .equ 1 ; Request number, bit 1 INTC_PL6P6_REQN2: .equ 2 ; Request number, bit 2 INTC_PL6P6_REQN3: .equ 3 ; Request number, bit 3 INTC_PL6P6_REQN4: .equ 4 ; Request number, bit 4 INTC_PL6P6_REQN5: .equ 5 ; Request number, bit 5 ; bit position masks mINTC_PL6P6_REQN0: .equ %00000001 mINTC_PL6P6_REQN1: .equ %00000010 mINTC_PL6P6_REQN2: .equ %00000100 mINTC_PL6P6_REQN3: .equ %00001000 mINTC_PL6P6_REQN4: .equ %00010000 mINTC_PL6P6_REQN5: .equ %00100000 ;*** INTC_WCR - INTC Wake-up Control Register; 0xFFFFFFDB *** INTC_WCR: .equ $FFFFFFDB ;*** INTC_WCR - INTC Wake-up Control Register; 0xFFFFFFDB *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_WCR_MASK0: .equ 0 ; Interrupt mask level, bit 0 INTC_WCR_MASK1: .equ 1 ; Interrupt mask level, bit 1 INTC_WCR_MASK2: .equ 2 ; Interrupt mask level, bit 2 INTC_WCR_ENB: .equ 7 ; Enable ; bit position masks mINTC_WCR_MASK0: .equ %00000001 mINTC_WCR_MASK1: .equ %00000010 mINTC_WCR_MASK2: .equ %00000100 mINTC_WCR_ENB: .equ %10000000 ;*** INTC_SFRC - INTC Set Interrupt Force Register; 0xFFFFFFDE *** INTC_SFRC: .equ $FFFFFFDE ;*** INTC_SFRC - INTC Set Interrupt Force Register; 0xFFFFFFDE *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_SFRC_SET0: .equ 0 ; Sets corresponding bits in the INTC_FRC register, bit 0 INTC_SFRC_SET1: .equ 1 ; Sets corresponding bits in the INTC_FRC register, bit 1 INTC_SFRC_SET2: .equ 2 ; Sets corresponding bits in the INTC_FRC register, bit 2 INTC_SFRC_SET3: .equ 3 ; Sets corresponding bits in the INTC_FRC register, bit 3 INTC_SFRC_SET4: .equ 4 ; Sets corresponding bits in the INTC_FRC register, bit 4 INTC_SFRC_SET5: .equ 5 ; Sets corresponding bits in the INTC_FRC register, bit 5 ; bit position masks mINTC_SFRC_SET0: .equ %00000001 mINTC_SFRC_SET1: .equ %00000010 mINTC_SFRC_SET2: .equ %00000100 mINTC_SFRC_SET3: .equ %00001000 mINTC_SFRC_SET4: .equ %00010000 mINTC_SFRC_SET5: .equ %00100000 ;*** INTC_CFRC - INTC Clear Interrupt Force Register; 0xFFFFFFDF *** INTC_CFRC: .equ $FFFFFFDF ;*** INTC_CFRC - INTC Clear Interrupt Force Register; 0xFFFFFFDF *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_CFRC_CLR0: .equ 0 ; Clears corresponding bits in the INTC_FRC register, bit 0 INTC_CFRC_CLR1: .equ 1 ; Clears corresponding bits in the INTC_FRC register, bit 1 INTC_CFRC_CLR2: .equ 2 ; Clears corresponding bits in the INTC_FRC register, bit 2 INTC_CFRC_CLR3: .equ 3 ; Clears corresponding bits in the INTC_FRC register, bit 3 INTC_CFRC_CLR4: .equ 4 ; Clears corresponding bits in the INTC_FRC register, bit 4 INTC_CFRC_CLR5: .equ 5 ; Clears corresponding bits in the INTC_FRC register, bit 5 ; bit position masks mINTC_CFRC_CLR0: .equ %00000001 mINTC_CFRC_CLR1: .equ %00000010 mINTC_CFRC_CLR2: .equ %00000100 mINTC_CFRC_CLR3: .equ %00001000 mINTC_CFRC_CLR4: .equ %00010000 mINTC_CFRC_CLR5: .equ %00100000 ;*** INTC_SWIACK - INTC Software IACK Register; 0xFFFFFFE0 *** INTC_SWIACK: .equ $FFFFFFE0 ;*** INTC_SWIACK - INTC Software IACK Register; 0xFFFFFFE0 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_SWIACK_VECN0: .equ 0 ; Vector number, bit 0 INTC_SWIACK_VECN1: .equ 1 ; Vector number, bit 1 INTC_SWIACK_VECN2: .equ 2 ; Vector number, bit 2 INTC_SWIACK_VECN3: .equ 3 ; Vector number, bit 3 INTC_SWIACK_VECN4: .equ 4 ; Vector number, bit 4 INTC_SWIACK_VECN5: .equ 5 ; Vector number, bit 5 INTC_SWIACK_VECN6: .equ 6 ; Vector number, bit 6 ; bit position masks mINTC_SWIACK_VECN0: .equ %00000001 mINTC_SWIACK_VECN1: .equ %00000010 mINTC_SWIACK_VECN2: .equ %00000100 mINTC_SWIACK_VECN3: .equ %00001000 mINTC_SWIACK_VECN4: .equ %00010000 mINTC_SWIACK_VECN5: .equ %00100000 mINTC_SWIACK_VECN6: .equ %01000000 ;*** INTC_LVL1IACK - INTC Level 1 IACK Register; 0xFFFFFFE4 *** INTC_LVL1IACK: .equ $FFFFFFE4 ;*** INTC_LVL1IACK - INTC Level 1 IACK Register; 0xFFFFFFE4 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_LVL1IACK_VECN0: .equ 0 ; Vector number, bit 0 INTC_LVL1IACK_VECN1: .equ 1 ; Vector number, bit 1 INTC_LVL1IACK_VECN2: .equ 2 ; Vector number, bit 2 INTC_LVL1IACK_VECN3: .equ 3 ; Vector number, bit 3 INTC_LVL1IACK_VECN4: .equ 4 ; Vector number, bit 4 INTC_LVL1IACK_VECN5: .equ 5 ; Vector number, bit 5 INTC_LVL1IACK_VECN6: .equ 6 ; Vector number, bit 6 ; bit position masks mINTC_LVL1IACK_VECN0: .equ %00000001 mINTC_LVL1IACK_VECN1: .equ %00000010 mINTC_LVL1IACK_VECN2: .equ %00000100 mINTC_LVL1IACK_VECN3: .equ %00001000 mINTC_LVL1IACK_VECN4: .equ %00010000 mINTC_LVL1IACK_VECN5: .equ %00100000 mINTC_LVL1IACK_VECN6: .equ %01000000 ;*** INTC_LVL2IACK - INTC Level 2 IACK Register; 0xFFFFFFE8 *** INTC_LVL2IACK: .equ $FFFFFFE8 ;*** INTC_LVL2IACK - INTC Level 2 IACK Register; 0xFFFFFFE8 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_LVL2IACK_VECN0: .equ 0 ; Vector number, bit 0 INTC_LVL2IACK_VECN1: .equ 1 ; Vector number, bit 1 INTC_LVL2IACK_VECN2: .equ 2 ; Vector number, bit 2 INTC_LVL2IACK_VECN3: .equ 3 ; Vector number, bit 3 INTC_LVL2IACK_VECN4: .equ 4 ; Vector number, bit 4 INTC_LVL2IACK_VECN5: .equ 5 ; Vector number, bit 5 INTC_LVL2IACK_VECN6: .equ 6 ; Vector number, bit 6 ; bit position masks mINTC_LVL2IACK_VECN0: .equ %00000001 mINTC_LVL2IACK_VECN1: .equ %00000010 mINTC_LVL2IACK_VECN2: .equ %00000100 mINTC_LVL2IACK_VECN3: .equ %00001000 mINTC_LVL2IACK_VECN4: .equ %00010000 mINTC_LVL2IACK_VECN5: .equ %00100000 mINTC_LVL2IACK_VECN6: .equ %01000000 ;*** INTC_LVL3IACK - INTC Level 3 IACK Register; 0xFFFFFFEC *** INTC_LVL3IACK: .equ $FFFFFFEC ;*** INTC_LVL3IACK - INTC Level 3 IACK Register; 0xFFFFFFEC *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_LVL3IACK_VECN0: .equ 0 ; Vector number, bit 0 INTC_LVL3IACK_VECN1: .equ 1 ; Vector number, bit 1 INTC_LVL3IACK_VECN2: .equ 2 ; Vector number, bit 2 INTC_LVL3IACK_VECN3: .equ 3 ; Vector number, bit 3 INTC_LVL3IACK_VECN4: .equ 4 ; Vector number, bit 4 INTC_LVL3IACK_VECN5: .equ 5 ; Vector number, bit 5 INTC_LVL3IACK_VECN6: .equ 6 ; Vector number, bit 6 ; bit position masks mINTC_LVL3IACK_VECN0: .equ %00000001 mINTC_LVL3IACK_VECN1: .equ %00000010 mINTC_LVL3IACK_VECN2: .equ %00000100 mINTC_LVL3IACK_VECN3: .equ %00001000 mINTC_LVL3IACK_VECN4: .equ %00010000 mINTC_LVL3IACK_VECN5: .equ %00100000 mINTC_LVL3IACK_VECN6: .equ %01000000 ;*** INTC_LVL4IACK - INTC Level 4 IACK Register; 0xFFFFFFF0 *** INTC_LVL4IACK: .equ $FFFFFFF0 ;*** INTC_LVL4IACK - INTC Level 4 IACK Register; 0xFFFFFFF0 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_LVL4IACK_VECN0: .equ 0 ; Vector number, bit 0 INTC_LVL4IACK_VECN1: .equ 1 ; Vector number, bit 1 INTC_LVL4IACK_VECN2: .equ 2 ; Vector number, bit 2 INTC_LVL4IACK_VECN3: .equ 3 ; Vector number, bit 3 INTC_LVL4IACK_VECN4: .equ 4 ; Vector number, bit 4 INTC_LVL4IACK_VECN5: .equ 5 ; Vector number, bit 5 INTC_LVL4IACK_VECN6: .equ 6 ; Vector number, bit 6 ; bit position masks mINTC_LVL4IACK_VECN0: .equ %00000001 mINTC_LVL4IACK_VECN1: .equ %00000010 mINTC_LVL4IACK_VECN2: .equ %00000100 mINTC_LVL4IACK_VECN3: .equ %00001000 mINTC_LVL4IACK_VECN4: .equ %00010000 mINTC_LVL4IACK_VECN5: .equ %00100000 mINTC_LVL4IACK_VECN6: .equ %01000000 ;*** INTC_LVL5IACK - INTC Level 5 IACK Register; 0xFFFFFFF4 *** INTC_LVL5IACK: .equ $FFFFFFF4 ;*** INTC_LVL5IACK - INTC Level 5 IACK Register; 0xFFFFFFF4 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_LVL5IACK_VECN0: .equ 0 ; Vector number, bit 0 INTC_LVL5IACK_VECN1: .equ 1 ; Vector number, bit 1 INTC_LVL5IACK_VECN2: .equ 2 ; Vector number, bit 2 INTC_LVL5IACK_VECN3: .equ 3 ; Vector number, bit 3 INTC_LVL5IACK_VECN4: .equ 4 ; Vector number, bit 4 INTC_LVL5IACK_VECN5: .equ 5 ; Vector number, bit 5 INTC_LVL5IACK_VECN6: .equ 6 ; Vector number, bit 6 ; bit position masks mINTC_LVL5IACK_VECN0: .equ %00000001 mINTC_LVL5IACK_VECN1: .equ %00000010 mINTC_LVL5IACK_VECN2: .equ %00000100 mINTC_LVL5IACK_VECN3: .equ %00001000 mINTC_LVL5IACK_VECN4: .equ %00010000 mINTC_LVL5IACK_VECN5: .equ %00100000 mINTC_LVL5IACK_VECN6: .equ %01000000 ;*** INTC_LVL6IACK - INTC Level 6 IACK Register; 0xFFFFFFF8 *** INTC_LVL6IACK: .equ $FFFFFFF8 ;*** INTC_LVL6IACK - INTC Level 6 IACK Register; 0xFFFFFFF8 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_LVL6IACK_VECN0: .equ 0 ; Vector number, bit 0 INTC_LVL6IACK_VECN1: .equ 1 ; Vector number, bit 1 INTC_LVL6IACK_VECN2: .equ 2 ; Vector number, bit 2 INTC_LVL6IACK_VECN3: .equ 3 ; Vector number, bit 3 INTC_LVL6IACK_VECN4: .equ 4 ; Vector number, bit 4 INTC_LVL6IACK_VECN5: .equ 5 ; Vector number, bit 5 INTC_LVL6IACK_VECN6: .equ 6 ; Vector number, bit 6 ; bit position masks mINTC_LVL6IACK_VECN0: .equ %00000001 mINTC_LVL6IACK_VECN1: .equ %00000010 mINTC_LVL6IACK_VECN2: .equ %00000100 mINTC_LVL6IACK_VECN3: .equ %00001000 mINTC_LVL6IACK_VECN4: .equ %00010000 mINTC_LVL6IACK_VECN5: .equ %00100000 mINTC_LVL6IACK_VECN6: .equ %01000000 ;*** INTC_LVL7IACK - INTC Level 7 IACK Register; 0xFFFFFFFC *** INTC_LVL7IACK: .equ $FFFFFFFC ;*** INTC_LVL7IACK - INTC Level 7 IACK Register; 0xFFFFFFFC *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_LVL7IACK_VECN0: .equ 0 ; Vector number, bit 0 INTC_LVL7IACK_VECN1: .equ 1 ; Vector number, bit 1 INTC_LVL7IACK_VECN2: .equ 2 ; Vector number, bit 2 INTC_LVL7IACK_VECN3: .equ 3 ; Vector number, bit 3 INTC_LVL7IACK_VECN4: .equ 4 ; Vector number, bit 4 INTC_LVL7IACK_VECN5: .equ 5 ; Vector number, bit 5 INTC_LVL7IACK_VECN6: .equ 6 ; Vector number, bit 6 ; bit position masks mINTC_LVL7IACK_VECN0: .equ %00000001 mINTC_LVL7IACK_VECN1: .equ %00000010 mINTC_LVL7IACK_VECN2: .equ %00000100 mINTC_LVL7IACK_VECN3: .equ %00001000 mINTC_LVL7IACK_VECN4: .equ %00010000 mINTC_LVL7IACK_VECN5: .equ %00100000 mINTC_LVL7IACK_VECN6: .equ %01000000 ;*********************************************** ;** D E P R E C I A T E D S Y M B O L S ** ;*********************************************** .IFNDEF __GENERATE_APPLICATION__ ; not supported for absolute assembler .XREF This_symb_has_been_depreciated .ENDIF ; EOF