; Based on CPU DB MCF51AG128_80, version 3.00.011 (RegistersPrg V2.31) ; ################################################################### ; Filename : mcf51ag128.inc ; Processor : MCF51AG128VLK ; FileFormat: V2.31 ; DataSheet : MCF51AG128RM Rev. 3 5/2009 ; Compiler : CodeWarrior compiler ; Date/Time : 13.11.2009, 15:06 ; Abstract : ; This header implements the mapping of I/O devices. ; ; Copyright : 1997 - 2009 Freescale Semiconductor, Inc. All Rights Reserved. ; ; http : www.freescale.com ; mail : support@freescale.com ; ; CPU Registers Revisions: ; - 13.11.2009, V3.00.0: ; - Removed empty Bits structures from definitions of EWM and WDOG registers. ; ; File-Format-Revisions: ; - 10.9.2009, V2.30 : ; - Fixed generation of registers arrays. ; - 15.10.2009, V2.31 : ; - Changes have not affected this file (because they are related to another family) ; ; Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific ; derivative device. To avoid extra current drain from floating input pins, the user’s reset ; initialization routine in the application program must either enable on-chip pull-up devices ; or change the direction of unconnected pins to outputs so the pins do not float. ; ################################################################### ;*** Interrupt Vectors ;****************************************** INITSP: .equ $00000000 INITPC: .equ $00000004 Vaccerr: .equ $00000008 Vadderr: .equ $0000000C Viinstr: .equ $00000010 VReserved5: .equ $00000014 VReserved6: .equ $00000018 VReserved7: .equ $0000001C Vprviol: .equ $00000020 Vtrace: .equ $00000024 Vunilaop: .equ $00000028 Vunilfop: .equ $0000002C Vdbgi: .equ $00000030 VReserved13: .equ $00000034 Vferror: .equ $00000038 VReserved15: .equ $0000003C VReserved16: .equ $00000040 VReserved17: .equ $00000044 VReserved18: .equ $00000048 VReserved19: .equ $0000004C VReserved20: .equ $00000050 VReserved21: .equ $00000054 VReserved22: .equ $00000058 VReserved23: .equ $0000005C Vspuri: .equ $00000060 VReserved25: .equ $00000064 VReserved26: .equ $00000068 VReserved27: .equ $0000006C VReserved28: .equ $00000070 VReserved29: .equ $00000074 VReserved30: .equ $00000078 VReserved31: .equ $0000007C Vtrap0: .equ $00000080 Vtrap1: .equ $00000084 Vtrap2: .equ $00000088 Vtrap3: .equ $0000008C Vtrap4: .equ $00000090 Vtrap5: .equ $00000094 Vtrap6: .equ $00000098 Vtrap7: .equ $0000009C Vtrap8: .equ $000000A0 Vtrap9: .equ $000000A4 Vtrap10: .equ $000000A8 Vtrap11: .equ $000000AC Vtrap12: .equ $000000B0 Vtrap13: .equ $000000B4 Vtrap14: .equ $000000B8 Vtrap15: .equ $000000BC VReserved48: .equ $000000C0 VReserved49: .equ $000000C4 VReserved50: .equ $000000C8 VReserved51: .equ $000000CC VReserved52: .equ $000000D0 VReserved53: .equ $000000D4 VReserved54: .equ $000000D8 VReserved55: .equ $000000DC VReserved56: .equ $000000E0 VReserved57: .equ $000000E4 VReserved58: .equ $000000E8 VReserved59: .equ $000000EC VReserved60: .equ $000000F0 Vunsinstr: .equ $000000F4 VReserved62: .equ $000000F8 VReserved63: .equ $000000FC Virq: .equ $00000100 Vlvd: .equ $00000104 VReserved66: .equ $00000108 VReserved67: .equ $0000010C Vdmach0: .equ $00000110 Vdmach1: .equ $00000114 Vdmach2: .equ $00000118 Vdmach3: .equ $0000011C Vieventch0: .equ $00000120 Vftm1fault_ovf: .equ $00000124 Vftm1ch0: .equ $00000128 Vftm1ch1: .equ $0000012C Vftm1ch2: .equ $00000130 Vftm1ch3: .equ $00000134 Vftm1ch4: .equ $00000138 Vftm1ch5: .equ $0000013C Vftm2fault_ovf: .equ $00000140 Vftm2ch0: .equ $00000144 Vftm2ch1: .equ $00000148 Vftm2ch2: .equ $0000014C Vftm2ch3: .equ $00000150 Vftm2ch4: .equ $00000154 Vftm2ch5: .equ $00000158 Vtpm3ovf: .equ $0000015C Vtpm3ch0: .equ $00000160 Vtpm3ch1: .equ $00000164 Vadc: .equ $00000168 Vhscmp1: .equ $0000016C Vhscmp2: .equ $00000170 Vieventch1: .equ $00000174 Vspi1: .equ $00000178 Vspi2: .equ $0000017C Vsci1err: .equ $00000180 Vsci1rx: .equ $00000184 Vsci1tx: .equ $00000188 Viic: .equ $0000018C Vieventch2: .equ $00000190 Vsci2err: .equ $00000194 Vsci2rx: .equ $00000198 VL7swi: .equ $0000019C VL6swi: .equ $000001A0 VL5swi: .equ $000001A4 VL4swi: .equ $000001A8 VL3swi: .equ $000001AC VL2swi: .equ $000001B0 VL1swi: .equ $000001B4 Vsci2tx: .equ $000001B8 Vportae: .equ $000001BC Vportfj: .equ $000001C0 Vrtc_wdg: .equ $000001C4 Vieventch3: .equ $000001C8 ; ;*** NVFTRIM - Nonvolatile ICS Fine Trim; 0x000003FE *** NVFTRIM: .equ $000003FE ;*** NVFTRIM - Nonvolatile ICS Fine Trim; 0x000003FE *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVFTRIM_FTRIM: .equ 0 ; ICS Fine Trim ; bit position masks mNVFTRIM_FTRIM: .equ %00000001 ;*** NVICSTRM - Nonvolatile ICS Trim Register; 0x000003FF *** NVICSTRM: .equ $000003FF ;*** NVICSTRM - Nonvolatile ICS Trim Register; 0x000003FF *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVICSTRM_TRIM0: .equ 0 ; ICS Trim Setting, bit 0 NVICSTRM_TRIM1: .equ 1 ; ICS Trim Setting, bit 1 NVICSTRM_TRIM2: .equ 2 ; ICS Trim Setting, bit 2 NVICSTRM_TRIM3: .equ 3 ; ICS Trim Setting, bit 3 NVICSTRM_TRIM4: .equ 4 ; ICS Trim Setting, bit 4 NVICSTRM_TRIM5: .equ 5 ; ICS Trim Setting, bit 5 NVICSTRM_TRIM6: .equ 6 ; ICS Trim Setting, bit 6 NVICSTRM_TRIM7: .equ 7 ; ICS Trim Setting, bit 7 ; bit position masks mNVICSTRM_TRIM0: .equ %00000001 mNVICSTRM_TRIM1: .equ %00000010 mNVICSTRM_TRIM2: .equ %00000100 mNVICSTRM_TRIM3: .equ %00001000 mNVICSTRM_TRIM4: .equ %00010000 mNVICSTRM_TRIM5: .equ %00100000 mNVICSTRM_TRIM6: .equ %01000000 mNVICSTRM_TRIM7: .equ %10000000 ;*** NVBACKKEY0 - Backdoor Comparison Key 0; 0x00000400 *** NVBACKKEY0: .equ $00000400 ;*** NVBACKKEY0 - Backdoor Comparison Key 0; 0x00000400 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVBACKKEY0_KEY0: .equ 0 ; Backdoor Comparison Key 0 Bits, bit 0 NVBACKKEY0_KEY1: .equ 1 ; Backdoor Comparison Key 0 Bits, bit 1 NVBACKKEY0_KEY2: .equ 2 ; Backdoor Comparison Key 0 Bits, bit 2 NVBACKKEY0_KEY3: .equ 3 ; Backdoor Comparison Key 0 Bits, bit 3 NVBACKKEY0_KEY4: .equ 4 ; Backdoor Comparison Key 0 Bits, bit 4 NVBACKKEY0_KEY5: .equ 5 ; Backdoor Comparison Key 0 Bits, bit 5 NVBACKKEY0_KEY6: .equ 6 ; Backdoor Comparison Key 0 Bits, bit 6 NVBACKKEY0_KEY7: .equ 7 ; Backdoor Comparison Key 0 Bits, bit 7 ; bit position masks mNVBACKKEY0_KEY0: .equ %00000001 mNVBACKKEY0_KEY1: .equ %00000010 mNVBACKKEY0_KEY2: .equ %00000100 mNVBACKKEY0_KEY3: .equ %00001000 mNVBACKKEY0_KEY4: .equ %00010000 mNVBACKKEY0_KEY5: .equ %00100000 mNVBACKKEY0_KEY6: .equ %01000000 mNVBACKKEY0_KEY7: .equ %10000000 ;*** NVBACKKEY1 - Backdoor Comparison Key 1; 0x00000401 *** NVBACKKEY1: .equ $00000401 ;*** NVBACKKEY1 - Backdoor Comparison Key 1; 0x00000401 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVBACKKEY1_KEY0: .equ 0 ; Backdoor Comparison Key 1 Bits, bit 0 NVBACKKEY1_KEY1: .equ 1 ; Backdoor Comparison Key 1 Bits, bit 1 NVBACKKEY1_KEY2: .equ 2 ; Backdoor Comparison Key 1 Bits, bit 2 NVBACKKEY1_KEY3: .equ 3 ; Backdoor Comparison Key 1 Bits, bit 3 NVBACKKEY1_KEY4: .equ 4 ; Backdoor Comparison Key 1 Bits, bit 4 NVBACKKEY1_KEY5: .equ 5 ; Backdoor Comparison Key 1 Bits, bit 5 NVBACKKEY1_KEY6: .equ 6 ; Backdoor Comparison Key 1 Bits, bit 6 NVBACKKEY1_KEY7: .equ 7 ; Backdoor Comparison Key 1 Bits, bit 7 ; bit position masks mNVBACKKEY1_KEY0: .equ %00000001 mNVBACKKEY1_KEY1: .equ %00000010 mNVBACKKEY1_KEY2: .equ %00000100 mNVBACKKEY1_KEY3: .equ %00001000 mNVBACKKEY1_KEY4: .equ %00010000 mNVBACKKEY1_KEY5: .equ %00100000 mNVBACKKEY1_KEY6: .equ %01000000 mNVBACKKEY1_KEY7: .equ %10000000 ;*** NVBACKKEY2 - Backdoor Comparison Key 2; 0x00000402 *** NVBACKKEY2: .equ $00000402 ;*** NVBACKKEY2 - Backdoor Comparison Key 2; 0x00000402 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVBACKKEY2_KEY0: .equ 0 ; Backdoor Comparison Key 2 Bits, bit 0 NVBACKKEY2_KEY1: .equ 1 ; Backdoor Comparison Key 2 Bits, bit 1 NVBACKKEY2_KEY2: .equ 2 ; Backdoor Comparison Key 2 Bits, bit 2 NVBACKKEY2_KEY3: .equ 3 ; Backdoor Comparison Key 2 Bits, bit 3 NVBACKKEY2_KEY4: .equ 4 ; Backdoor Comparison Key 2 Bits, bit 4 NVBACKKEY2_KEY5: .equ 5 ; Backdoor Comparison Key 2 Bits, bit 5 NVBACKKEY2_KEY6: .equ 6 ; Backdoor Comparison Key 2 Bits, bit 6 NVBACKKEY2_KEY7: .equ 7 ; Backdoor Comparison Key 2 Bits, bit 7 ; bit position masks mNVBACKKEY2_KEY0: .equ %00000001 mNVBACKKEY2_KEY1: .equ %00000010 mNVBACKKEY2_KEY2: .equ %00000100 mNVBACKKEY2_KEY3: .equ %00001000 mNVBACKKEY2_KEY4: .equ %00010000 mNVBACKKEY2_KEY5: .equ %00100000 mNVBACKKEY2_KEY6: .equ %01000000 mNVBACKKEY2_KEY7: .equ %10000000 ;*** NVBACKKEY3 - Backdoor Comparison Key 3; 0x00000403 *** NVBACKKEY3: .equ $00000403 ;*** NVBACKKEY3 - Backdoor Comparison Key 3; 0x00000403 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVBACKKEY3_KEY0: .equ 0 ; Backdoor Comparison Key 3 Bits, bit 0 NVBACKKEY3_KEY1: .equ 1 ; Backdoor Comparison Key 3 Bits, bit 1 NVBACKKEY3_KEY2: .equ 2 ; Backdoor Comparison Key 3 Bits, bit 2 NVBACKKEY3_KEY3: .equ 3 ; Backdoor Comparison Key 3 Bits, bit 3 NVBACKKEY3_KEY4: .equ 4 ; Backdoor Comparison Key 3 Bits, bit 4 NVBACKKEY3_KEY5: .equ 5 ; Backdoor Comparison Key 3 Bits, bit 5 NVBACKKEY3_KEY6: .equ 6 ; Backdoor Comparison Key 3 Bits, bit 6 NVBACKKEY3_KEY7: .equ 7 ; Backdoor Comparison Key 3 Bits, bit 7 ; bit position masks mNVBACKKEY3_KEY0: .equ %00000001 mNVBACKKEY3_KEY1: .equ %00000010 mNVBACKKEY3_KEY2: .equ %00000100 mNVBACKKEY3_KEY3: .equ %00001000 mNVBACKKEY3_KEY4: .equ %00010000 mNVBACKKEY3_KEY5: .equ %00100000 mNVBACKKEY3_KEY6: .equ %01000000 mNVBACKKEY3_KEY7: .equ %10000000 ;*** NVBACKKEY4 - Backdoor Comparison Key 4; 0x00000404 *** NVBACKKEY4: .equ $00000404 ;*** NVBACKKEY4 - Backdoor Comparison Key 4; 0x00000404 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVBACKKEY4_KEY0: .equ 0 ; Backdoor Comparison Key 4 Bits, bit 0 NVBACKKEY4_KEY1: .equ 1 ; Backdoor Comparison Key 4 Bits, bit 1 NVBACKKEY4_KEY2: .equ 2 ; Backdoor Comparison Key 4 Bits, bit 2 NVBACKKEY4_KEY3: .equ 3 ; Backdoor Comparison Key 4 Bits, bit 3 NVBACKKEY4_KEY4: .equ 4 ; Backdoor Comparison Key 4 Bits, bit 4 NVBACKKEY4_KEY5: .equ 5 ; Backdoor Comparison Key 4 Bits, bit 5 NVBACKKEY4_KEY6: .equ 6 ; Backdoor Comparison Key 4 Bits, bit 6 NVBACKKEY4_KEY7: .equ 7 ; Backdoor Comparison Key 4 Bits, bit 7 ; bit position masks mNVBACKKEY4_KEY0: .equ %00000001 mNVBACKKEY4_KEY1: .equ %00000010 mNVBACKKEY4_KEY2: .equ %00000100 mNVBACKKEY4_KEY3: .equ %00001000 mNVBACKKEY4_KEY4: .equ %00010000 mNVBACKKEY4_KEY5: .equ %00100000 mNVBACKKEY4_KEY6: .equ %01000000 mNVBACKKEY4_KEY7: .equ %10000000 ;*** NVBACKKEY5 - Backdoor Comparison Key 5; 0x00000405 *** NVBACKKEY5: .equ $00000405 ;*** NVBACKKEY5 - Backdoor Comparison Key 5; 0x00000405 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVBACKKEY5_KEY0: .equ 0 ; Backdoor Comparison Key 5 Bits, bit 0 NVBACKKEY5_KEY1: .equ 1 ; Backdoor Comparison Key 5 Bits, bit 1 NVBACKKEY5_KEY2: .equ 2 ; Backdoor Comparison Key 5 Bits, bit 2 NVBACKKEY5_KEY3: .equ 3 ; Backdoor Comparison Key 5 Bits, bit 3 NVBACKKEY5_KEY4: .equ 4 ; Backdoor Comparison Key 5 Bits, bit 4 NVBACKKEY5_KEY5: .equ 5 ; Backdoor Comparison Key 5 Bits, bit 5 NVBACKKEY5_KEY6: .equ 6 ; Backdoor Comparison Key 5 Bits, bit 6 NVBACKKEY5_KEY7: .equ 7 ; Backdoor Comparison Key 5 Bits, bit 7 ; bit position masks mNVBACKKEY5_KEY0: .equ %00000001 mNVBACKKEY5_KEY1: .equ %00000010 mNVBACKKEY5_KEY2: .equ %00000100 mNVBACKKEY5_KEY3: .equ %00001000 mNVBACKKEY5_KEY4: .equ %00010000 mNVBACKKEY5_KEY5: .equ %00100000 mNVBACKKEY5_KEY6: .equ %01000000 mNVBACKKEY5_KEY7: .equ %10000000 ;*** NVBACKKEY6 - Backdoor Comparison Key 6; 0x00000406 *** NVBACKKEY6: .equ $00000406 ;*** NVBACKKEY6 - Backdoor Comparison Key 6; 0x00000406 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVBACKKEY6_KEY0: .equ 0 ; Backdoor Comparison Key 6 Bits, bit 0 NVBACKKEY6_KEY1: .equ 1 ; Backdoor Comparison Key 6 Bits, bit 1 NVBACKKEY6_KEY2: .equ 2 ; Backdoor Comparison Key 6 Bits, bit 2 NVBACKKEY6_KEY3: .equ 3 ; Backdoor Comparison Key 6 Bits, bit 3 NVBACKKEY6_KEY4: .equ 4 ; Backdoor Comparison Key 6 Bits, bit 4 NVBACKKEY6_KEY5: .equ 5 ; Backdoor Comparison Key 6 Bits, bit 5 NVBACKKEY6_KEY6: .equ 6 ; Backdoor Comparison Key 6 Bits, bit 6 NVBACKKEY6_KEY7: .equ 7 ; Backdoor Comparison Key 6 Bits, bit 7 ; bit position masks mNVBACKKEY6_KEY0: .equ %00000001 mNVBACKKEY6_KEY1: .equ %00000010 mNVBACKKEY6_KEY2: .equ %00000100 mNVBACKKEY6_KEY3: .equ %00001000 mNVBACKKEY6_KEY4: .equ %00010000 mNVBACKKEY6_KEY5: .equ %00100000 mNVBACKKEY6_KEY6: .equ %01000000 mNVBACKKEY6_KEY7: .equ %10000000 ;*** NVBACKKEY7 - Backdoor Comparison Key 7; 0x00000407 *** NVBACKKEY7: .equ $00000407 ;*** NVBACKKEY7 - Backdoor Comparison Key 7; 0x00000407 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVBACKKEY7_KEY0: .equ 0 ; Backdoor Comparison Key 7 Bits, bit 0 NVBACKKEY7_KEY1: .equ 1 ; Backdoor Comparison Key 7 Bits, bit 1 NVBACKKEY7_KEY2: .equ 2 ; Backdoor Comparison Key 7 Bits, bit 2 NVBACKKEY7_KEY3: .equ 3 ; Backdoor Comparison Key 7 Bits, bit 3 NVBACKKEY7_KEY4: .equ 4 ; Backdoor Comparison Key 7 Bits, bit 4 NVBACKKEY7_KEY5: .equ 5 ; Backdoor Comparison Key 7 Bits, bit 5 NVBACKKEY7_KEY6: .equ 6 ; Backdoor Comparison Key 7 Bits, bit 6 NVBACKKEY7_KEY7: .equ 7 ; Backdoor Comparison Key 7 Bits, bit 7 ; bit position masks mNVBACKKEY7_KEY0: .equ %00000001 mNVBACKKEY7_KEY1: .equ %00000010 mNVBACKKEY7_KEY2: .equ %00000100 mNVBACKKEY7_KEY3: .equ %00001000 mNVBACKKEY7_KEY4: .equ %00010000 mNVBACKKEY7_KEY5: .equ %00100000 mNVBACKKEY7_KEY6: .equ %01000000 mNVBACKKEY7_KEY7: .equ %10000000 ;*** NVPROT - Nonvolatile Flash Protection Register; 0x0000040D *** NVPROT: .equ $0000040D ;*** NVPROT - Nonvolatile Flash Protection Register; 0x0000040D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVPROT_FPOPEN: .equ 0 ; Flash Protection Open NVPROT_FPS0: .equ 1 ; Flash Protection Size, bit 0 NVPROT_FPS1: .equ 2 ; Flash Protection Size, bit 1 NVPROT_FPS2: .equ 3 ; Flash Protection Size, bit 2 NVPROT_FPS3: .equ 4 ; Flash Protection Size, bit 3 NVPROT_FPS4: .equ 5 ; Flash Protection Size, bit 4 NVPROT_FPS5: .equ 6 ; Flash Protection Size, bit 5 NVPROT_FPS6: .equ 7 ; Flash Protection Size, bit 6 ; bit position masks mNVPROT_FPOPEN: .equ %00000001 mNVPROT_FPS0: .equ %00000010 mNVPROT_FPS1: .equ %00000100 mNVPROT_FPS2: .equ %00001000 mNVPROT_FPS3: .equ %00010000 mNVPROT_FPS4: .equ %00100000 mNVPROT_FPS5: .equ %01000000 mNVPROT_FPS6: .equ %10000000 ;*** NVOPT - Nonvolatile Flash Options Register; 0x0000040F *** NVOPT: .equ $0000040F ;*** NVOPT - Nonvolatile Flash Options Register; 0x0000040F *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET NVOPT_SEC0: .equ 0 ; Flash Security Bit 0 NVOPT_SEC1: .equ 1 ; Flash Security Bit 1 NVOPT_KEYEN0: .equ 6 ; Backdoor Key Security Enable Bit 0 NVOPT_KEYEN1: .equ 7 ; Backdoor Key Security Enable Bit 1 ; bit position masks mNVOPT_SEC0: .equ %00000001 mNVOPT_SEC1: .equ %00000010 mNVOPT_KEYEN0: .equ %01000000 mNVOPT_KEYEN1: .equ %10000000 ;*** RGPIO_DIR - RGPIO Data Direction Register; 0x00C00000 *** RGPIO_DIR: .equ $00C00000 ;*** RGPIO_DIR - RGPIO Data Direction Register; 0x00C00000 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET RGPIO_DIR_DIR0: .equ 0 ; RGPIO data direction bit 0 RGPIO_DIR_DIR1: .equ 1 ; RGPIO data direction bit 1 RGPIO_DIR_DIR2: .equ 2 ; RGPIO data direction bit 2 RGPIO_DIR_DIR3: .equ 3 ; RGPIO data direction bit 3 RGPIO_DIR_DIR4: .equ 4 ; RGPIO data direction bit 4 RGPIO_DIR_DIR5: .equ 5 ; RGPIO data direction bit 5 RGPIO_DIR_DIR6: .equ 6 ; RGPIO data direction bit 6 RGPIO_DIR_DIR7: .equ 7 ; RGPIO data direction bit 7 RGPIO_DIR_DIR8: .equ 8 ; RGPIO data direction bit 8 RGPIO_DIR_DIR9: .equ 9 ; RGPIO data direction bit 9 RGPIO_DIR_DIR10: .equ 10 ; RGPIO data direction bit 10 RGPIO_DIR_DIR11: .equ 11 ; RGPIO data direction bit 11 RGPIO_DIR_DIR12: .equ 12 ; RGPIO data direction bit 12 RGPIO_DIR_DIR13: .equ 13 ; RGPIO data direction bit 13 RGPIO_DIR_DIR14: .equ 14 ; RGPIO data direction bit 14 RGPIO_DIR_DIR15: .equ 15 ; RGPIO data direction bit 15 ; bit position masks mRGPIO_DIR_DIR0: .equ %00000001 mRGPIO_DIR_DIR1: .equ %00000010 mRGPIO_DIR_DIR2: .equ %00000100 mRGPIO_DIR_DIR3: .equ %00001000 mRGPIO_DIR_DIR4: .equ %00010000 mRGPIO_DIR_DIR5: .equ %00100000 mRGPIO_DIR_DIR6: .equ %01000000 mRGPIO_DIR_DIR7: .equ %10000000 mRGPIO_DIR_DIR8: .equ %100000000 mRGPIO_DIR_DIR9: .equ %1000000000 mRGPIO_DIR_DIR10: .equ %10000000000 mRGPIO_DIR_DIR11: .equ %100000000000 mRGPIO_DIR_DIR12: .equ %1000000000000 mRGPIO_DIR_DIR13: .equ %10000000000000 mRGPIO_DIR_DIR14: .equ %100000000000000 mRGPIO_DIR_DIR15: .equ %1000000000000000 ;*** RGPIO_DATA - RGPIO Data Register; 0x00C00002 *** RGPIO_DATA: .equ $00C00002 ;*** RGPIO_DATA - RGPIO Data Register; 0x00C00002 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET RGPIO_DATA_DATA0: .equ 0 ; RGPIO data bit 0 RGPIO_DATA_DATA1: .equ 1 ; RGPIO data bit 1 RGPIO_DATA_DATA2: .equ 2 ; RGPIO data bit 2 RGPIO_DATA_DATA3: .equ 3 ; RGPIO data bit 3 RGPIO_DATA_DATA4: .equ 4 ; RGPIO data bit 4 RGPIO_DATA_DATA5: .equ 5 ; RGPIO data bit 5 RGPIO_DATA_DATA6: .equ 6 ; RGPIO data bit 6 RGPIO_DATA_DATA7: .equ 7 ; RGPIO data bit 7 RGPIO_DATA_DATA8: .equ 8 ; RGPIO data bit 8 RGPIO_DATA_DATA9: .equ 9 ; RGPIO data bit 9 RGPIO_DATA_DATA10: .equ 10 ; RGPIO data bit 10 RGPIO_DATA_DATA11: .equ 11 ; RGPIO data bit 11 RGPIO_DATA_DATA12: .equ 12 ; RGPIO data bit 12 RGPIO_DATA_DATA13: .equ 13 ; RGPIO data bit 13 RGPIO_DATA_DATA14: .equ 14 ; RGPIO data bit 14 RGPIO_DATA_DATA15: .equ 15 ; RGPIO data bit 15 ; bit position masks mRGPIO_DATA_DATA0: .equ %00000001 mRGPIO_DATA_DATA1: .equ %00000010 mRGPIO_DATA_DATA2: .equ %00000100 mRGPIO_DATA_DATA3: .equ %00001000 mRGPIO_DATA_DATA4: .equ %00010000 mRGPIO_DATA_DATA5: .equ %00100000 mRGPIO_DATA_DATA6: .equ %01000000 mRGPIO_DATA_DATA7: .equ %10000000 mRGPIO_DATA_DATA8: .equ %100000000 mRGPIO_DATA_DATA9: .equ %1000000000 mRGPIO_DATA_DATA10: .equ %10000000000 mRGPIO_DATA_DATA11: .equ %100000000000 mRGPIO_DATA_DATA12: .equ %1000000000000 mRGPIO_DATA_DATA13: .equ %10000000000000 mRGPIO_DATA_DATA14: .equ %100000000000000 mRGPIO_DATA_DATA15: .equ %1000000000000000 ;*** RGPIO_ENB - RGPIO Pin Enable Register; 0x00C00004 *** RGPIO_ENB: .equ $00C00004 ;*** RGPIO_ENB - RGPIO Pin Enable Register; 0x00C00004 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET RGPIO_ENB_ENB0: .equ 0 ; RGPIO enable bit 0 RGPIO_ENB_ENB1: .equ 1 ; RGPIO enable bit 1 RGPIO_ENB_ENB2: .equ 2 ; RGPIO enable bit 2 RGPIO_ENB_ENB3: .equ 3 ; RGPIO enable bit 3 RGPIO_ENB_ENB4: .equ 4 ; RGPIO enable bit 4 RGPIO_ENB_ENB5: .equ 5 ; RGPIO enable bit 5 RGPIO_ENB_ENB6: .equ 6 ; RGPIO enable bit 6 RGPIO_ENB_ENB7: .equ 7 ; RGPIO enable bit 7 RGPIO_ENB_ENB8: .equ 8 ; RGPIO enable bit 8 RGPIO_ENB_ENB9: .equ 9 ; RGPIO enable bit 9 RGPIO_ENB_ENB10: .equ 10 ; RGPIO enable bit 10 RGPIO_ENB_ENB11: .equ 11 ; RGPIO enable bit 11 RGPIO_ENB_ENB12: .equ 12 ; RGPIO enable bit 12 RGPIO_ENB_ENB13: .equ 13 ; RGPIO enable bit 13 RGPIO_ENB_ENB14: .equ 14 ; RGPIO enable bit 14 RGPIO_ENB_ENB15: .equ 15 ; RGPIO enable bit 15 ; bit position masks mRGPIO_ENB_ENB0: .equ %00000001 mRGPIO_ENB_ENB1: .equ %00000010 mRGPIO_ENB_ENB2: .equ %00000100 mRGPIO_ENB_ENB3: .equ %00001000 mRGPIO_ENB_ENB4: .equ %00010000 mRGPIO_ENB_ENB5: .equ %00100000 mRGPIO_ENB_ENB6: .equ %01000000 mRGPIO_ENB_ENB7: .equ %10000000 mRGPIO_ENB_ENB8: .equ %100000000 mRGPIO_ENB_ENB9: .equ %1000000000 mRGPIO_ENB_ENB10: .equ %10000000000 mRGPIO_ENB_ENB11: .equ %100000000000 mRGPIO_ENB_ENB12: .equ %1000000000000 mRGPIO_ENB_ENB13: .equ %10000000000000 mRGPIO_ENB_ENB14: .equ %100000000000000 mRGPIO_ENB_ENB15: .equ %1000000000000000 ;*** RGPIO_CLR - RGPIO Clear Data Register; 0x00C00006 *** RGPIO_CLR: .equ $00C00006 ;*** RGPIO_CLR - RGPIO Clear Data Register; 0x00C00006 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET RGPIO_CLR_CLR0: .equ 0 ; RGPIO clear data bit 0 RGPIO_CLR_CLR1: .equ 1 ; RGPIO clear data bit 1 RGPIO_CLR_CLR2: .equ 2 ; RGPIO clear data bit 2 RGPIO_CLR_CLR3: .equ 3 ; RGPIO clear data bit 3 RGPIO_CLR_CLR4: .equ 4 ; RGPIO clear data bit 4 RGPIO_CLR_CLR5: .equ 5 ; RGPIO clear data bit 5 RGPIO_CLR_CLR6: .equ 6 ; RGPIO clear data bit 6 RGPIO_CLR_CLR7: .equ 7 ; RGPIO clear data bit 7 RGPIO_CLR_CLR8: .equ 8 ; RGPIO clear data bit 8 RGPIO_CLR_CLR9: .equ 9 ; RGPIO clear data bit 9 RGPIO_CLR_CLR10: .equ 10 ; RGPIO clear data bit 10 RGPIO_CLR_CLR11: .equ 11 ; RGPIO clear data bit 11 RGPIO_CLR_CLR12: .equ 12 ; RGPIO clear data bit 12 RGPIO_CLR_CLR13: .equ 13 ; RGPIO clear data bit 13 RGPIO_CLR_CLR14: .equ 14 ; RGPIO clear data bit 14 RGPIO_CLR_CLR15: .equ 15 ; RGPIO clear data bit 15 ; bit position masks mRGPIO_CLR_CLR0: .equ %00000001 mRGPIO_CLR_CLR1: .equ %00000010 mRGPIO_CLR_CLR2: .equ %00000100 mRGPIO_CLR_CLR3: .equ %00001000 mRGPIO_CLR_CLR4: .equ %00010000 mRGPIO_CLR_CLR5: .equ %00100000 mRGPIO_CLR_CLR6: .equ %01000000 mRGPIO_CLR_CLR7: .equ %10000000 mRGPIO_CLR_CLR8: .equ %100000000 mRGPIO_CLR_CLR9: .equ %1000000000 mRGPIO_CLR_CLR10: .equ %10000000000 mRGPIO_CLR_CLR11: .equ %100000000000 mRGPIO_CLR_CLR12: .equ %1000000000000 mRGPIO_CLR_CLR13: .equ %10000000000000 mRGPIO_CLR_CLR14: .equ %100000000000000 mRGPIO_CLR_CLR15: .equ %1000000000000000 ;*** RGPIO_SET - RGPIO Set Data Register; 0x00C0000A *** RGPIO_SET: .equ $00C0000A ;*** RGPIO_SET - RGPIO Set Data Register; 0x00C0000A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET RGPIO_SET_SET0: .equ 0 ; RGPIO set data bit 0 RGPIO_SET_SET1: .equ 1 ; RGPIO set data bit 1 RGPIO_SET_SET2: .equ 2 ; RGPIO set data bit 2 RGPIO_SET_SET3: .equ 3 ; RGPIO set data bit 3 RGPIO_SET_SET4: .equ 4 ; RGPIO set data bit 4 RGPIO_SET_SET5: .equ 5 ; RGPIO set data bit 5 RGPIO_SET_SET6: .equ 6 ; RGPIO set data bit 6 RGPIO_SET_SET7: .equ 7 ; RGPIO set data bit 7 RGPIO_SET_SET8: .equ 8 ; RGPIO set data bit 8 RGPIO_SET_SET9: .equ 9 ; RGPIO set data bit 9 RGPIO_SET_SET10: .equ 10 ; RGPIO set data bit 10 RGPIO_SET_SET11: .equ 11 ; RGPIO set data bit 11 RGPIO_SET_SET12: .equ 12 ; RGPIO set data bit 12 RGPIO_SET_SET13: .equ 13 ; RGPIO set data bit 13 RGPIO_SET_SET14: .equ 14 ; RGPIO set data bit 14 RGPIO_SET_SET15: .equ 15 ; RGPIO set data bit 15 ; bit position masks mRGPIO_SET_SET0: .equ %00000001 mRGPIO_SET_SET1: .equ %00000010 mRGPIO_SET_SET2: .equ %00000100 mRGPIO_SET_SET3: .equ %00001000 mRGPIO_SET_SET4: .equ %00010000 mRGPIO_SET_SET5: .equ %00100000 mRGPIO_SET_SET6: .equ %01000000 mRGPIO_SET_SET7: .equ %10000000 mRGPIO_SET_SET8: .equ %100000000 mRGPIO_SET_SET9: .equ %1000000000 mRGPIO_SET_SET10: .equ %10000000000 mRGPIO_SET_SET11: .equ %100000000000 mRGPIO_SET_SET12: .equ %1000000000000 mRGPIO_SET_SET13: .equ %10000000000000 mRGPIO_SET_SET14: .equ %100000000000000 mRGPIO_SET_SET15: .equ %1000000000000000 ;*** RGPIO_TOG - RGPIO Toggle Data Register; 0x00C0000E *** RGPIO_TOG: .equ $00C0000E ;*** RGPIO_TOG - RGPIO Toggle Data Register; 0x00C0000E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET RGPIO_TOG_TOG0: .equ 0 ; RGPIO toggle data bit 0 RGPIO_TOG_TOG1: .equ 1 ; RGPIO toggle data bit 1 RGPIO_TOG_TOG2: .equ 2 ; RGPIO toggle data bit 2 RGPIO_TOG_TOG3: .equ 3 ; RGPIO toggle data bit 3 RGPIO_TOG_TOG4: .equ 4 ; RGPIO toggle data bit 4 RGPIO_TOG_TOG5: .equ 5 ; RGPIO toggle data bit 5 RGPIO_TOG_TOG6: .equ 6 ; RGPIO toggle data bit 6 RGPIO_TOG_TOG7: .equ 7 ; RGPIO toggle data bit 7 RGPIO_TOG_TOG8: .equ 8 ; RGPIO toggle data bit 8 RGPIO_TOG_TOG9: .equ 9 ; RGPIO toggle data bit 9 RGPIO_TOG_TOG10: .equ 10 ; RGPIO toggle data bit 10 RGPIO_TOG_TOG11: .equ 11 ; RGPIO toggle data bit 11 RGPIO_TOG_TOG12: .equ 12 ; RGPIO toggle data bit 12 RGPIO_TOG_TOG13: .equ 13 ; RGPIO toggle data bit 13 RGPIO_TOG_TOG14: .equ 14 ; RGPIO toggle data bit 14 RGPIO_TOG_TOG15: .equ 15 ; RGPIO toggle data bit 15 ; bit position masks mRGPIO_TOG_TOG0: .equ %00000001 mRGPIO_TOG_TOG1: .equ %00000010 mRGPIO_TOG_TOG2: .equ %00000100 mRGPIO_TOG_TOG3: .equ %00001000 mRGPIO_TOG_TOG4: .equ %00010000 mRGPIO_TOG_TOG5: .equ %00100000 mRGPIO_TOG_TOG6: .equ %01000000 mRGPIO_TOG_TOG7: .equ %10000000 mRGPIO_TOG_TOG8: .equ %100000000 mRGPIO_TOG_TOG9: .equ %1000000000 mRGPIO_TOG_TOG10: .equ %10000000000 mRGPIO_TOG_TOG11: .equ %100000000000 mRGPIO_TOG_TOG12: .equ %1000000000000 mRGPIO_TOG_TOG13: .equ %10000000000000 mRGPIO_TOG_TOG14: .equ %100000000000000 mRGPIO_TOG_TOG15: .equ %1000000000000000 ;*** PTAD - Port A Data Register; 0xFFFF8000 *** PTAD: .equ $FFFF8000 ;*** PTAD - Port A Data Register; 0xFFFF8000 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTAD_PTAD0: .equ 0 ; Port A Data Register Bit 0 PTAD_PTAD1: .equ 1 ; Port A Data Register Bit 1 PTAD_PTAD2: .equ 2 ; Port A Data Register Bit 2 PTAD_PTAD3: .equ 3 ; Port A Data Register Bit 3 PTAD_PTAD4: .equ 4 ; Port A Data Register Bit 4 PTAD_PTAD5: .equ 5 ; Port A Data Register Bit 5 PTAD_PTAD6: .equ 6 ; Port A Data Register Bit 6 PTAD_PTAD7: .equ 7 ; Port A Data Register Bit 7 ; bit position masks mPTAD_PTAD0: .equ %00000001 mPTAD_PTAD1: .equ %00000010 mPTAD_PTAD2: .equ %00000100 mPTAD_PTAD3: .equ %00001000 mPTAD_PTAD4: .equ %00010000 mPTAD_PTAD5: .equ %00100000 mPTAD_PTAD6: .equ %01000000 mPTAD_PTAD7: .equ %10000000 ;*** PTADD - Port A Data Direction Register; 0xFFFF8001 *** PTADD: .equ $FFFF8001 ;*** PTADD - Port A Data Direction Register; 0xFFFF8001 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTADD_PTADD0: .equ 0 ; Data Direction for Port A Bit 0 PTADD_PTADD1: .equ 1 ; Data Direction for Port A Bit 1 PTADD_PTADD2: .equ 2 ; Data Direction for Port A Bit 2 PTADD_PTADD3: .equ 3 ; Data Direction for Port A Bit 3 PTADD_PTADD4: .equ 4 ; Data Direction for Port A Bit 4 PTADD_PTADD5: .equ 5 ; Data Direction for Port A Bit 5 PTADD_PTADD6: .equ 6 ; Data Direction for Port A Bit 6 PTADD_PTADD7: .equ 7 ; Data Direction for Port A Bit 7 ; bit position masks mPTADD_PTADD0: .equ %00000001 mPTADD_PTADD1: .equ %00000010 mPTADD_PTADD2: .equ %00000100 mPTADD_PTADD3: .equ %00001000 mPTADD_PTADD4: .equ %00010000 mPTADD_PTADD5: .equ %00100000 mPTADD_PTADD6: .equ %01000000 mPTADD_PTADD7: .equ %10000000 ;*** PTAPV - Port A Pin Value Register; 0xFFFF8002 *** PTAPV: .equ $FFFF8002 ;*** PTAPV - Port A Pin Value Register; 0xFFFF8002 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTAPV_PTAPV0: .equ 0 ; Pin Value Bit 0 PTAPV_PTAPV1: .equ 1 ; Pin Value Bit 1 PTAPV_PTAPV2: .equ 2 ; Pin Value Bit 2 PTAPV_PTAPV3: .equ 3 ; Pin Value Bit 3 PTAPV_PTAPV4: .equ 4 ; Pin Value Bit 4 PTAPV_PTAPV5: .equ 5 ; Pin Value Bit 5 PTAPV_PTAPV6: .equ 6 ; Pin Value Bit 6 PTAPV_PTAPV7: .equ 7 ; Pin Value Bit 7 ; bit position masks mPTAPV_PTAPV0: .equ %00000001 mPTAPV_PTAPV1: .equ %00000010 mPTAPV_PTAPV2: .equ %00000100 mPTAPV_PTAPV3: .equ %00001000 mPTAPV_PTAPV4: .equ %00010000 mPTAPV_PTAPV5: .equ %00100000 mPTAPV_PTAPV6: .equ %01000000 mPTAPV_PTAPV7: .equ %10000000 ;*** PTBD - Port B Data Register; 0xFFFF8004 *** PTBD: .equ $FFFF8004 ;*** PTBD - Port B Data Register; 0xFFFF8004 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTBD_PTBD0: .equ 0 ; Port B Data Register Bit 0 PTBD_PTBD1: .equ 1 ; Port B Data Register Bit 1 PTBD_PTBD2: .equ 2 ; Port B Data Register Bit 2 PTBD_PTBD3: .equ 3 ; Port B Data Register Bit 3 PTBD_PTBD4: .equ 4 ; Port B Data Register Bit 4 PTBD_PTBD5: .equ 5 ; Port B Data Register Bit 5 PTBD_PTBD6: .equ 6 ; Port B Data Register Bit 6 PTBD_PTBD7: .equ 7 ; Port B Data Register Bit 7 ; bit position masks mPTBD_PTBD0: .equ %00000001 mPTBD_PTBD1: .equ %00000010 mPTBD_PTBD2: .equ %00000100 mPTBD_PTBD3: .equ %00001000 mPTBD_PTBD4: .equ %00010000 mPTBD_PTBD5: .equ %00100000 mPTBD_PTBD6: .equ %01000000 mPTBD_PTBD7: .equ %10000000 ;*** PTBDD - Port B Data Direction Register; 0xFFFF8005 *** PTBDD: .equ $FFFF8005 ;*** PTBDD - Port B Data Direction Register; 0xFFFF8005 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTBDD_PTBDD0: .equ 0 ; Data Direction for Port B Bit 0 PTBDD_PTBDD1: .equ 1 ; Data Direction for Port B Bit 1 PTBDD_PTBDD2: .equ 2 ; Data Direction for Port B Bit 2 PTBDD_PTBDD3: .equ 3 ; Data Direction for Port B Bit 3 PTBDD_PTBDD4: .equ 4 ; Data Direction for Port B Bit 4 PTBDD_PTBDD5: .equ 5 ; Data Direction for Port B Bit 5 PTBDD_PTBDD6: .equ 6 ; Data Direction for Port B Bit 6 PTBDD_PTBDD7: .equ 7 ; Data Direction for Port B Bit 7 ; bit position masks mPTBDD_PTBDD0: .equ %00000001 mPTBDD_PTBDD1: .equ %00000010 mPTBDD_PTBDD2: .equ %00000100 mPTBDD_PTBDD3: .equ %00001000 mPTBDD_PTBDD4: .equ %00010000 mPTBDD_PTBDD5: .equ %00100000 mPTBDD_PTBDD6: .equ %01000000 mPTBDD_PTBDD7: .equ %10000000 ;*** PTBPV - Port B Pin Value Register; 0xFFFF8006 *** PTBPV: .equ $FFFF8006 ;*** PTBPV - Port B Pin Value Register; 0xFFFF8006 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTBPV_PTBPV0: .equ 0 ; Pin Value Bit 0 PTBPV_PTBPV1: .equ 1 ; Pin Value Bit 1 PTBPV_PTBPV2: .equ 2 ; Pin Value Bit 2 PTBPV_PTBPV3: .equ 3 ; Pin Value Bit 3 PTBPV_PTBPV4: .equ 4 ; Pin Value Bit 4 PTBPV_PTBPV5: .equ 5 ; Pin Value Bit 5 PTBPV_PTBPV6: .equ 6 ; Pin Value Bit 6 PTBPV_PTBPV7: .equ 7 ; Pin Value Bit 7 ; bit position masks mPTBPV_PTBPV0: .equ %00000001 mPTBPV_PTBPV1: .equ %00000010 mPTBPV_PTBPV2: .equ %00000100 mPTBPV_PTBPV3: .equ %00001000 mPTBPV_PTBPV4: .equ %00010000 mPTBPV_PTBPV5: .equ %00100000 mPTBPV_PTBPV6: .equ %01000000 mPTBPV_PTBPV7: .equ %10000000 ;*** PTCD - Port C Data Register; 0xFFFF8008 *** PTCD: .equ $FFFF8008 ;*** PTCD - Port C Data Register; 0xFFFF8008 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTCD_PTCD0: .equ 0 ; Port C Data Register Bit 0 PTCD_PTCD1: .equ 1 ; Port C Data Register Bit 1 PTCD_PTCD2: .equ 2 ; Port C Data Register Bit 2 PTCD_PTCD3: .equ 3 ; Port C Data Register Bit 3 PTCD_PTCD4: .equ 4 ; Port C Data Register Bit 4 PTCD_PTCD5: .equ 5 ; Port C Data Register Bit 5 PTCD_PTCD6: .equ 6 ; Port C Data Register Bit 6 ; bit position masks mPTCD_PTCD0: .equ %00000001 mPTCD_PTCD1: .equ %00000010 mPTCD_PTCD2: .equ %00000100 mPTCD_PTCD3: .equ %00001000 mPTCD_PTCD4: .equ %00010000 mPTCD_PTCD5: .equ %00100000 mPTCD_PTCD6: .equ %01000000 ;*** PTCDD - Port C Data Direction Register; 0xFFFF8009 *** PTCDD: .equ $FFFF8009 ;*** PTCDD - Port C Data Direction Register; 0xFFFF8009 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTCDD_PTCDD0: .equ 0 ; Data Direction for Port C Bit 0 PTCDD_PTCDD1: .equ 1 ; Data Direction for Port C Bit 1 PTCDD_PTCDD2: .equ 2 ; Data Direction for Port C Bit 2 PTCDD_PTCDD3: .equ 3 ; Data Direction for Port C Bit 3 PTCDD_PTCDD4: .equ 4 ; Data Direction for Port C Bit 4 PTCDD_PTCDD5: .equ 5 ; Data Direction for Port C Bit 5 PTCDD_PTCDD6: .equ 6 ; Data Direction for Port C Bit 6 ; bit position masks mPTCDD_PTCDD0: .equ %00000001 mPTCDD_PTCDD1: .equ %00000010 mPTCDD_PTCDD2: .equ %00000100 mPTCDD_PTCDD3: .equ %00001000 mPTCDD_PTCDD4: .equ %00010000 mPTCDD_PTCDD5: .equ %00100000 mPTCDD_PTCDD6: .equ %01000000 ;*** PTCPV - Port C Pin Value Register; 0xFFFF800A *** PTCPV: .equ $FFFF800A ;*** PTCPV - Port C Pin Value Register; 0xFFFF800A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTCPV_PTCPV0: .equ 0 ; Pin Value Bit 0 PTCPV_PTCPV1: .equ 1 ; Pin Value Bit 1 PTCPV_PTCPV2: .equ 2 ; Pin Value Bit 2 PTCPV_PTCPV3: .equ 3 ; Pin Value Bit 3 PTCPV_PTCPV4: .equ 4 ; Pin Value Bit 4 PTCPV_PTCPV5: .equ 5 ; Pin Value Bit 5 PTCPV_PTCPV6: .equ 6 ; Pin Value Bit 6 ; bit position masks mPTCPV_PTCPV0: .equ %00000001 mPTCPV_PTCPV1: .equ %00000010 mPTCPV_PTCPV2: .equ %00000100 mPTCPV_PTCPV3: .equ %00001000 mPTCPV_PTCPV4: .equ %00010000 mPTCPV_PTCPV5: .equ %00100000 mPTCPV_PTCPV6: .equ %01000000 ;*** PTDD - Port D Data Register; 0xFFFF800C *** PTDD: .equ $FFFF800C ;*** PTDD - Port D Data Register; 0xFFFF800C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTDD_PTDD0: .equ 0 ; Port D Data Register Bit 0 PTDD_PTDD1: .equ 1 ; Port D Data Register Bit 1 PTDD_PTDD2: .equ 2 ; Port D Data Register Bit 2 PTDD_PTDD3: .equ 3 ; Port D Data Register Bit 3 PTDD_PTDD4: .equ 4 ; Port D Data Register Bit 4 PTDD_PTDD5: .equ 5 ; Port D Data Register Bit 5 PTDD_PTDD6: .equ 6 ; Port D Data Register Bit 6 PTDD_PTDD7: .equ 7 ; Port D Data Register Bit 7 ; bit position masks mPTDD_PTDD0: .equ %00000001 mPTDD_PTDD1: .equ %00000010 mPTDD_PTDD2: .equ %00000100 mPTDD_PTDD3: .equ %00001000 mPTDD_PTDD4: .equ %00010000 mPTDD_PTDD5: .equ %00100000 mPTDD_PTDD6: .equ %01000000 mPTDD_PTDD7: .equ %10000000 ;*** PTDDD - Port D Data Direction Register; 0xFFFF800D *** PTDDD: .equ $FFFF800D ;*** PTDDD - Port D Data Direction Register; 0xFFFF800D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTDDD_PTDDD0: .equ 0 ; Data Direction for Port D Bit 0 PTDDD_PTDDD1: .equ 1 ; Data Direction for Port D Bit 1 PTDDD_PTDDD2: .equ 2 ; Data Direction for Port D Bit 2 PTDDD_PTDDD3: .equ 3 ; Data Direction for Port D Bit 3 PTDDD_PTDDD4: .equ 4 ; Data Direction for Port D Bit 4 PTDDD_PTDDD5: .equ 5 ; Data Direction for Port D Bit 5 PTDDD_PTDDD6: .equ 6 ; Data Direction for Port D Bit 6 PTDDD_PTDDD7: .equ 7 ; Data Direction for Port D Bit 7 ; bit position masks mPTDDD_PTDDD0: .equ %00000001 mPTDDD_PTDDD1: .equ %00000010 mPTDDD_PTDDD2: .equ %00000100 mPTDDD_PTDDD3: .equ %00001000 mPTDDD_PTDDD4: .equ %00010000 mPTDDD_PTDDD5: .equ %00100000 mPTDDD_PTDDD6: .equ %01000000 mPTDDD_PTDDD7: .equ %10000000 ;*** PTDPV - Port D Pin Value Register; 0xFFFF800E *** PTDPV: .equ $FFFF800E ;*** PTDPV - Port D Pin Value Register; 0xFFFF800E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTDPV_PTDPV0: .equ 0 ; Pin Value Bit 0 PTDPV_PTDPV1: .equ 1 ; Pin Value Bit 1 PTDPV_PTDPV2: .equ 2 ; Pin Value Bit 2 PTDPV_PTDPV3: .equ 3 ; Pin Value Bit 3 PTDPV_PTDPV4: .equ 4 ; Pin Value Bit 4 PTDPV_PTDPV5: .equ 5 ; Pin Value Bit 5 PTDPV_PTDPV6: .equ 6 ; Pin Value Bit 6 PTDPV_PTDPV7: .equ 7 ; Pin Value Bit 7 ; bit position masks mPTDPV_PTDPV0: .equ %00000001 mPTDPV_PTDPV1: .equ %00000010 mPTDPV_PTDPV2: .equ %00000100 mPTDPV_PTDPV3: .equ %00001000 mPTDPV_PTDPV4: .equ %00010000 mPTDPV_PTDPV5: .equ %00100000 mPTDPV_PTDPV6: .equ %01000000 mPTDPV_PTDPV7: .equ %10000000 ;*** PTED - Port E Data Register; 0xFFFF8010 *** PTED: .equ $FFFF8010 ;*** PTED - Port E Data Register; 0xFFFF8010 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTED_PTED0: .equ 0 ; Port E Data Register Bit 0 PTED_PTED1: .equ 1 ; Port E Data Register Bit 1 PTED_PTED2: .equ 2 ; Port E Data Register Bit 2 PTED_PTED3: .equ 3 ; Port E Data Register Bit 3 PTED_PTED4: .equ 4 ; Port E Data Register Bit 4 PTED_PTED5: .equ 5 ; Port E Data Register Bit 5 PTED_PTED6: .equ 6 ; Port E Data Register Bit 6 PTED_PTED7: .equ 7 ; Port E Data Register Bit 7 ; bit position masks mPTED_PTED0: .equ %00000001 mPTED_PTED1: .equ %00000010 mPTED_PTED2: .equ %00000100 mPTED_PTED3: .equ %00001000 mPTED_PTED4: .equ %00010000 mPTED_PTED5: .equ %00100000 mPTED_PTED6: .equ %01000000 mPTED_PTED7: .equ %10000000 ;*** PTEDD - Port E Data Direction Register; 0xFFFF8011 *** PTEDD: .equ $FFFF8011 ;*** PTEDD - Port E Data Direction Register; 0xFFFF8011 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTEDD_PTEDD0: .equ 0 ; Data Direction for Port E Bit 0 PTEDD_PTEDD1: .equ 1 ; Data Direction for Port E Bit 1 PTEDD_PTEDD2: .equ 2 ; Data Direction for Port E Bit 2 PTEDD_PTEDD3: .equ 3 ; Data Direction for Port E Bit 3 PTEDD_PTEDD4: .equ 4 ; Data Direction for Port E Bit 4 PTEDD_PTEDD5: .equ 5 ; Data Direction for Port E Bit 5 PTEDD_PTEDD6: .equ 6 ; Data Direction for Port E Bit 6 PTEDD_PTEDD7: .equ 7 ; Data Direction for Port E Bit 7 ; bit position masks mPTEDD_PTEDD0: .equ %00000001 mPTEDD_PTEDD1: .equ %00000010 mPTEDD_PTEDD2: .equ %00000100 mPTEDD_PTEDD3: .equ %00001000 mPTEDD_PTEDD4: .equ %00010000 mPTEDD_PTEDD5: .equ %00100000 mPTEDD_PTEDD6: .equ %01000000 mPTEDD_PTEDD7: .equ %10000000 ;*** PTEPV - Port E Pin Value Register; 0xFFFF8012 *** PTEPV: .equ $FFFF8012 ;*** PTEPV - Port E Pin Value Register; 0xFFFF8012 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTEPV_PTEPV0: .equ 0 ; Pin Value Bit 0 PTEPV_PTEPV1: .equ 1 ; Pin Value Bit 1 PTEPV_PTEPV2: .equ 2 ; Pin Value Bit 2 PTEPV_PTEPV3: .equ 3 ; Pin Value Bit 3 PTEPV_PTEPV4: .equ 4 ; Pin Value Bit 4 PTEPV_PTEPV5: .equ 5 ; Pin Value Bit 5 PTEPV_PTEPV6: .equ 6 ; Pin Value Bit 6 PTEPV_PTEPV7: .equ 7 ; Pin Value Bit 7 ; bit position masks mPTEPV_PTEPV0: .equ %00000001 mPTEPV_PTEPV1: .equ %00000010 mPTEPV_PTEPV2: .equ %00000100 mPTEPV_PTEPV3: .equ %00001000 mPTEPV_PTEPV4: .equ %00010000 mPTEPV_PTEPV5: .equ %00100000 mPTEPV_PTEPV6: .equ %01000000 mPTEPV_PTEPV7: .equ %10000000 ;*** PTFD - Port F Data Register; 0xFFFF8014 *** PTFD: .equ $FFFF8014 ;*** PTFD - Port F Data Register; 0xFFFF8014 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTFD_PTFD0: .equ 0 ; Port F Data Register Bit 0 PTFD_PTFD1: .equ 1 ; Port F Data Register Bit 1 PTFD_PTFD2: .equ 2 ; Port F Data Register Bit 2 PTFD_PTFD3: .equ 3 ; Port F Data Register Bit 3 PTFD_PTFD4: .equ 4 ; Port F Data Register Bit 4 PTFD_PTFD5: .equ 5 ; Port F Data Register Bit 5 PTFD_PTFD6: .equ 6 ; Port F Data Register Bit 6 PTFD_PTFD7: .equ 7 ; Port F Data Register Bit 7 ; bit position masks mPTFD_PTFD0: .equ %00000001 mPTFD_PTFD1: .equ %00000010 mPTFD_PTFD2: .equ %00000100 mPTFD_PTFD3: .equ %00001000 mPTFD_PTFD4: .equ %00010000 mPTFD_PTFD5: .equ %00100000 mPTFD_PTFD6: .equ %01000000 mPTFD_PTFD7: .equ %10000000 ;*** PTFDD - Port F Data Direction Register; 0xFFFF8015 *** PTFDD: .equ $FFFF8015 ;*** PTFDD - Port F Data Direction Register; 0xFFFF8015 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTFDD_PTFDD0: .equ 0 ; Data Direction for Port F Bit 0 PTFDD_PTFDD1: .equ 1 ; Data Direction for Port F Bit 1 PTFDD_PTFDD2: .equ 2 ; Data Direction for Port F Bit 2 PTFDD_PTFDD3: .equ 3 ; Data Direction for Port F Bit 3 PTFDD_PTFDD4: .equ 4 ; Data Direction for Port F Bit 4 PTFDD_PTFDD5: .equ 5 ; Data Direction for Port F Bit 5 PTFDD_PTFDD6: .equ 6 ; Data Direction for Port F Bit 6 PTFDD_PTFDD7: .equ 7 ; Data Direction for Port F Bit 7 ; bit position masks mPTFDD_PTFDD0: .equ %00000001 mPTFDD_PTFDD1: .equ %00000010 mPTFDD_PTFDD2: .equ %00000100 mPTFDD_PTFDD3: .equ %00001000 mPTFDD_PTFDD4: .equ %00010000 mPTFDD_PTFDD5: .equ %00100000 mPTFDD_PTFDD6: .equ %01000000 mPTFDD_PTFDD7: .equ %10000000 ;*** PTFPV - Port F Pin Value Register; 0xFFFF8016 *** PTFPV: .equ $FFFF8016 ;*** PTFPV - Port F Pin Value Register; 0xFFFF8016 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTFPV_PTFPV0: .equ 0 ; Pin Value Bit 0 PTFPV_PTFPV1: .equ 1 ; Pin Value Bit 1 PTFPV_PTFPV2: .equ 2 ; Pin Value Bit 2 PTFPV_PTFPV3: .equ 3 ; Pin Value Bit 3 PTFPV_PTFPV4: .equ 4 ; Pin Value Bit 4 PTFPV_PTFPV5: .equ 5 ; Pin Value Bit 5 PTFPV_PTFPV6: .equ 6 ; Pin Value Bit 6 PTFPV_PTFPV7: .equ 7 ; Pin Value Bit 7 ; bit position masks mPTFPV_PTFPV0: .equ %00000001 mPTFPV_PTFPV1: .equ %00000010 mPTFPV_PTFPV2: .equ %00000100 mPTFPV_PTFPV3: .equ %00001000 mPTFPV_PTFPV4: .equ %00010000 mPTFPV_PTFPV5: .equ %00100000 mPTFPV_PTFPV6: .equ %01000000 mPTFPV_PTFPV7: .equ %10000000 ;*** PTGD - Port G Data Register; 0xFFFF8018 *** PTGD: .equ $FFFF8018 ;*** PTGD - Port G Data Register; 0xFFFF8018 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTGD_PTGD0: .equ 0 ; Port G Data Register Bit 0 PTGD_PTGD1: .equ 1 ; Port G Data Register Bit 1 PTGD_PTGD2: .equ 2 ; Port G Data Register Bit 2 PTGD_PTGD3: .equ 3 ; Port G Data Register Bit 3 PTGD_PTGD4: .equ 4 ; Port G Data Register Bit 4 PTGD_PTGD5: .equ 5 ; Port G Data Register Bit 5 PTGD_PTGD6: .equ 6 ; Port G Data Register Bit 6 ; bit position masks mPTGD_PTGD0: .equ %00000001 mPTGD_PTGD1: .equ %00000010 mPTGD_PTGD2: .equ %00000100 mPTGD_PTGD3: .equ %00001000 mPTGD_PTGD4: .equ %00010000 mPTGD_PTGD5: .equ %00100000 mPTGD_PTGD6: .equ %01000000 ;*** PTGDD - Port G Data Direction Register; 0xFFFF8019 *** PTGDD: .equ $FFFF8019 ;*** PTGDD - Port G Data Direction Register; 0xFFFF8019 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTGDD_PTGDD0: .equ 0 ; Data Direction for Port G Bit 0 PTGDD_PTGDD1: .equ 1 ; Data Direction for Port G Bit 1 PTGDD_PTGDD2: .equ 2 ; Data Direction for Port G Bit 2 PTGDD_PTGDD3: .equ 3 ; Data Direction for Port G Bit 3 PTGDD_PTGDD4: .equ 4 ; Data Direction for Port G Bit 4 PTGDD_PTGDD5: .equ 5 ; Data Direction for Port G Bit 5 PTGDD_PTGDD6: .equ 6 ; Data Direction for Port G Bit 6 ; bit position masks mPTGDD_PTGDD0: .equ %00000001 mPTGDD_PTGDD1: .equ %00000010 mPTGDD_PTGDD2: .equ %00000100 mPTGDD_PTGDD3: .equ %00001000 mPTGDD_PTGDD4: .equ %00010000 mPTGDD_PTGDD5: .equ %00100000 mPTGDD_PTGDD6: .equ %01000000 ;*** PTGPV - Port G Pin Value Register; 0xFFFF801A *** PTGPV: .equ $FFFF801A ;*** PTGPV - Port G Pin Value Register; 0xFFFF801A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTGPV_PTGPV0: .equ 0 ; Pin Value Bit 0 PTGPV_PTGPV1: .equ 1 ; Pin Value Bit 1 PTGPV_PTGPV2: .equ 2 ; Pin Value Bit 2 PTGPV_PTGPV3: .equ 3 ; Pin Value Bit 3 PTGPV_PTGPV4: .equ 4 ; Pin Value Bit 4 PTGPV_PTGPV5: .equ 5 ; Pin Value Bit 5 PTGPV_PTGPV6: .equ 6 ; Pin Value Bit 6 ; bit position masks mPTGPV_PTGPV0: .equ %00000001 mPTGPV_PTGPV1: .equ %00000010 mPTGPV_PTGPV2: .equ %00000100 mPTGPV_PTGPV3: .equ %00001000 mPTGPV_PTGPV4: .equ %00010000 mPTGPV_PTGPV5: .equ %00100000 mPTGPV_PTGPV6: .equ %01000000 ;*** PTHD - Port H Data Register; 0xFFFF801C *** PTHD: .equ $FFFF801C ;*** PTHD - Port H Data Register; 0xFFFF801C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTHD_PTHD0: .equ 0 ; Port H Data Register Bit 0 PTHD_PTHD1: .equ 1 ; Port H Data Register Bit 1 PTHD_PTHD2: .equ 2 ; Port H Data Register Bit 2 PTHD_PTHD3: .equ 3 ; Port H Data Register Bit 3 PTHD_PTHD4: .equ 4 ; Port H Data Register Bit 4 PTHD_PTHD5: .equ 5 ; Port H Data Register Bit 5 PTHD_PTHD6: .equ 6 ; Port H Data Register Bit 6 ; bit position masks mPTHD_PTHD0: .equ %00000001 mPTHD_PTHD1: .equ %00000010 mPTHD_PTHD2: .equ %00000100 mPTHD_PTHD3: .equ %00001000 mPTHD_PTHD4: .equ %00010000 mPTHD_PTHD5: .equ %00100000 mPTHD_PTHD6: .equ %01000000 ;*** PTHDD - Port H Data Direction Register; 0xFFFF801D *** PTHDD: .equ $FFFF801D ;*** PTHDD - Port H Data Direction Register; 0xFFFF801D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTHDD_PTHDD0: .equ 0 ; Data Direction for Port H Bit 0 PTHDD_PTHDD1: .equ 1 ; Data Direction for Port H Bit 1 PTHDD_PTHDD2: .equ 2 ; Data Direction for Port H Bit 2 PTHDD_PTHDD3: .equ 3 ; Data Direction for Port H Bit 3 PTHDD_PTHDD4: .equ 4 ; Data Direction for Port H Bit 4 PTHDD_PTHDD5: .equ 5 ; Data Direction for Port H Bit 5 PTHDD_PTHDD6: .equ 6 ; Data Direction for Port H Bit 6 ; bit position masks mPTHDD_PTHDD0: .equ %00000001 mPTHDD_PTHDD1: .equ %00000010 mPTHDD_PTHDD2: .equ %00000100 mPTHDD_PTHDD3: .equ %00001000 mPTHDD_PTHDD4: .equ %00010000 mPTHDD_PTHDD5: .equ %00100000 mPTHDD_PTHDD6: .equ %01000000 ;*** PTHPV - Port H Pin Value Register; 0xFFFF801E *** PTHPV: .equ $FFFF801E ;*** PTHPV - Port H Pin Value Register; 0xFFFF801E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTHPV_PTHPV0: .equ 0 ; Pin Value Bit 0 PTHPV_PTHPV1: .equ 1 ; Pin Value Bit 1 PTHPV_PTHPV2: .equ 2 ; Pin Value Bit 2 PTHPV_PTHPV3: .equ 3 ; Pin Value Bit 3 PTHPV_PTHPV4: .equ 4 ; Pin Value Bit 4 PTHPV_PTHPV5: .equ 5 ; Pin Value Bit 5 PTHPV_PTHPV6: .equ 6 ; Pin Value Bit 6 ; bit position masks mPTHPV_PTHPV0: .equ %00000001 mPTHPV_PTHPV1: .equ %00000010 mPTHPV_PTHPV2: .equ %00000100 mPTHPV_PTHPV3: .equ %00001000 mPTHPV_PTHPV4: .equ %00010000 mPTHPV_PTHPV5: .equ %00100000 mPTHPV_PTHPV6: .equ %01000000 ;*** PTJD - Port J Data Register; 0xFFFF8020 *** PTJD: .equ $FFFF8020 ;*** PTJD - Port J Data Register; 0xFFFF8020 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTJD_PTJD0: .equ 0 ; Port J Data Register Bit 0 PTJD_PTJD1: .equ 1 ; Port J Data Register Bit 1 PTJD_PTJD2: .equ 2 ; Port J Data Register Bit 2 PTJD_PTJD3: .equ 3 ; Port J Data Register Bit 3 PTJD_PTJD4: .equ 4 ; Port J Data Register Bit 4 PTJD_PTJD5: .equ 5 ; Port J Data Register Bit 5 PTJD_PTJD6: .equ 6 ; Port J Data Register Bit 6 PTJD_PTJD7: .equ 7 ; Port J Data Register Bit 7 ; bit position masks mPTJD_PTJD0: .equ %00000001 mPTJD_PTJD1: .equ %00000010 mPTJD_PTJD2: .equ %00000100 mPTJD_PTJD3: .equ %00001000 mPTJD_PTJD4: .equ %00010000 mPTJD_PTJD5: .equ %00100000 mPTJD_PTJD6: .equ %01000000 mPTJD_PTJD7: .equ %10000000 ;*** PTJDD - Port J Data Direction Register; 0xFFFF8021 *** PTJDD: .equ $FFFF8021 ;*** PTJDD - Port J Data Direction Register; 0xFFFF8021 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTJDD_PTJDD0: .equ 0 ; Data Direction for Port J Bit 0 PTJDD_PTJDD1: .equ 1 ; Data Direction for Port J Bit 1 PTJDD_PTJDD2: .equ 2 ; Data Direction for Port J Bit 2 PTJDD_PTJDD3: .equ 3 ; Data Direction for Port J Bit 3 PTJDD_PTJDD4: .equ 4 ; Data Direction for Port J Bit 4 PTJDD_PTJDD5: .equ 5 ; Data Direction for Port J Bit 5 PTJDD_PTJDD6: .equ 6 ; Data Direction for Port J Bit 6 PTJDD_PTJDD7: .equ 7 ; Data Direction for Port J Bit 7 ; bit position masks mPTJDD_PTJDD0: .equ %00000001 mPTJDD_PTJDD1: .equ %00000010 mPTJDD_PTJDD2: .equ %00000100 mPTJDD_PTJDD3: .equ %00001000 mPTJDD_PTJDD4: .equ %00010000 mPTJDD_PTJDD5: .equ %00100000 mPTJDD_PTJDD6: .equ %01000000 mPTJDD_PTJDD7: .equ %10000000 ;*** PTJPV - Port J Pin Value Register; 0xFFFF8022 *** PTJPV: .equ $FFFF8022 ;*** PTJPV - Port J Pin Value Register; 0xFFFF8022 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTJPV_PTJPV0: .equ 0 ; Pin Value Bit 0 PTJPV_PTJPV1: .equ 1 ; Pin Value Bit 1 PTJPV_PTJPV2: .equ 2 ; Pin Value Bit 2 PTJPV_PTJPV3: .equ 3 ; Pin Value Bit 3 PTJPV_PTJPV4: .equ 4 ; Pin Value Bit 4 PTJPV_PTJPV5: .equ 5 ; Pin Value Bit 5 PTJPV_PTJPV6: .equ 6 ; Pin Value Bit 6 PTJPV_PTJPV7: .equ 7 ; Pin Value Bit 7 ; bit position masks mPTJPV_PTJPV0: .equ %00000001 mPTJPV_PTJPV1: .equ %00000010 mPTJPV_PTJPV2: .equ %00000100 mPTJPV_PTJPV3: .equ %00001000 mPTJPV_PTJPV4: .equ %00010000 mPTJPV_PTJPV5: .equ %00100000 mPTJPV_PTJPV6: .equ %01000000 mPTJPV_PTJPV7: .equ %10000000 ;*** ICSC1 - ICS Control Register 1; 0xFFFF8024 *** ICSC1: .equ $FFFF8024 ;*** ICSC1 - ICS Control Register 1; 0xFFFF8024 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ICSC1_IREFSTEN: .equ 0 ; Internal Reference Stop Enable ICSC1_IRCLKEN: .equ 1 ; Internal Reference Clock Enable ICSC1_IREFS: .equ 2 ; Internal Reference Select ICSC1_RDIV0: .equ 3 ; Reference Divider, bit 0 ICSC1_RDIV1: .equ 4 ; Reference Divider, bit 1 ICSC1_RDIV2: .equ 5 ; Reference Divider, bit 2 ICSC1_CLKS0: .equ 6 ; Clock Source Select, bit 0 ICSC1_CLKS1: .equ 7 ; Clock Source Select, bit 1 ; bit position masks mICSC1_IREFSTEN: .equ %00000001 mICSC1_IRCLKEN: .equ %00000010 mICSC1_IREFS: .equ %00000100 mICSC1_RDIV0: .equ %00001000 mICSC1_RDIV1: .equ %00010000 mICSC1_RDIV2: .equ %00100000 mICSC1_CLKS0: .equ %01000000 mICSC1_CLKS1: .equ %10000000 ;*** ICSC2 - ICS Control Register 2; 0xFFFF8025 *** ICSC2: .equ $FFFF8025 ;*** ICSC2 - ICS Control Register 2; 0xFFFF8025 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ICSC2_EREFSTEN: .equ 0 ; External Reference Stop Enable ICSC2_ERCLKEN: .equ 1 ; External Reference Enable ICSC2_EREFS: .equ 2 ; External Reference Select ICSC2_LP: .equ 3 ; Low Power Select ICSC2_HGO: .equ 4 ; High Gain Oscillator Select ICSC2_RANGE: .equ 5 ; Frequency Range Select ICSC2_BDIV0: .equ 6 ; Bus Frequency Divider, bit 0 ICSC2_BDIV1: .equ 7 ; Bus Frequency Divider, bit 1 ; bit position masks mICSC2_EREFSTEN: .equ %00000001 mICSC2_ERCLKEN: .equ %00000010 mICSC2_EREFS: .equ %00000100 mICSC2_LP: .equ %00001000 mICSC2_HGO: .equ %00010000 mICSC2_RANGE: .equ %00100000 mICSC2_BDIV0: .equ %01000000 mICSC2_BDIV1: .equ %10000000 ;*** ICSTRM - ICS Trim Register; 0xFFFF8026 *** ICSTRM: .equ $FFFF8026 ;*** ICSTRM - ICS Trim Register; 0xFFFF8026 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ICSTRM_TRIM0: .equ 0 ; ICS Trim Setting, bit 0 ICSTRM_TRIM1: .equ 1 ; ICS Trim Setting, bit 1 ICSTRM_TRIM2: .equ 2 ; ICS Trim Setting, bit 2 ICSTRM_TRIM3: .equ 3 ; ICS Trim Setting, bit 3 ICSTRM_TRIM4: .equ 4 ; ICS Trim Setting, bit 4 ICSTRM_TRIM5: .equ 5 ; ICS Trim Setting, bit 5 ICSTRM_TRIM6: .equ 6 ; ICS Trim Setting, bit 6 ICSTRM_TRIM7: .equ 7 ; ICS Trim Setting, bit 7 ; bit position masks mICSTRM_TRIM0: .equ %00000001 mICSTRM_TRIM1: .equ %00000010 mICSTRM_TRIM2: .equ %00000100 mICSTRM_TRIM3: .equ %00001000 mICSTRM_TRIM4: .equ %00010000 mICSTRM_TRIM5: .equ %00100000 mICSTRM_TRIM6: .equ %01000000 mICSTRM_TRIM7: .equ %10000000 ;*** ICSSC - ICS Status and Control Register; 0xFFFF8027 *** ICSSC: .equ $FFFF8027 ;*** ICSSC - ICS Status and Control Register; 0xFFFF8027 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ICSSC_FTRIM: .equ 0 ; ICS Fine Trim ICSSC_OSCINIT: .equ 1 ; OSC Initialization ICSSC_CLKST0: .equ 2 ; Clock Mode Status, bit 0 ICSSC_CLKST1: .equ 3 ; Clock Mode Status, bit 1 ICSSC_IREFST: .equ 4 ; Internal Reference Status ICSSC_DMX32: .equ 5 ; DCO Maximum frequency with 32.768 kHz reference ICSSC_DRST_DRS0: .equ 6 ; DCO Range Status/Range Select, bit 0 ICSSC_DRST_DRS1: .equ 7 ; DCO Range Status/Range Select, bit 1 ; bit position masks mICSSC_FTRIM: .equ %00000001 mICSSC_OSCINIT: .equ %00000010 mICSSC_CLKST0: .equ %00000100 mICSSC_CLKST1: .equ %00001000 mICSSC_IREFST: .equ %00010000 mICSSC_DMX32: .equ %00100000 mICSSC_DRST_DRS0: .equ %01000000 mICSSC_DRST_DRS1: .equ %10000000 ;*** RTCSC - RTC Status and Control Register; 0xFFFF8028 *** RTCSC: .equ $FFFF8028 ;*** RTCSC - RTC Status and Control Register; 0xFFFF8028 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET RTCSC_RTCPS0: .equ 0 ; Real-Time Clock Prescaler Select, bit 0 RTCSC_RTCPS1: .equ 1 ; Real-Time Clock Prescaler Select, bit 1 RTCSC_RTCPS2: .equ 2 ; Real-Time Clock Prescaler Select, bit 2 RTCSC_RTCPS3: .equ 3 ; Real-Time Clock Prescaler Select, bit 3 RTCSC_RTIE: .equ 4 ; Real-Time Interrupt Enable RTCSC_RTCLKS0: .equ 5 ; Real-Time Clock Source Select, bit 0 RTCSC_RTCLKS1: .equ 6 ; Real-Time Clock Source Select, bit 1 RTCSC_RTIF: .equ 7 ; Real-Time Interrupt Flag ; bit position masks mRTCSC_RTCPS0: .equ %00000001 mRTCSC_RTCPS1: .equ %00000010 mRTCSC_RTCPS2: .equ %00000100 mRTCSC_RTCPS3: .equ %00001000 mRTCSC_RTIE: .equ %00010000 mRTCSC_RTCLKS0: .equ %00100000 mRTCSC_RTCLKS1: .equ %01000000 mRTCSC_RTIF: .equ %10000000 ;*** RTCCNT - RTC Counter Register; 0xFFFF8029 *** RTCCNT: .equ $FFFF8029 ;*** RTCCNT - RTC Counter Register; 0xFFFF8029 *** ;*** RTCMOD - RTC Modulo Register; 0xFFFF802A *** RTCMOD: .equ $FFFF802A ;*** RTCMOD - RTC Modulo Register; 0xFFFF802A *** ;*** RTCSC1 - RTC DMA Enable Register; 0xFFFF802B *** RTCSC1: .equ $FFFF802B ;*** RTCSC1 - RTC DMA Enable Register; 0xFFFF802B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET RTCSC1_DMAEN: .equ 7 ; RTC DMA Enable ; bit position masks mRTCSC1_DMAEN: .equ %10000000 ;*** DAC1CTRL - DAC Control Register; 0xFFFF802D *** DAC1CTRL: .equ $FFFF802D ;*** DAC1CTRL - DAC Control Register; 0xFFFF802D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DAC1CTRL_VOSEL0: .equ 0 ; DAC output voltage select, bit 0 DAC1CTRL_VOSEL1: .equ 1 ; DAC output voltage select, bit 1 DAC1CTRL_VOSEL2: .equ 2 ; DAC output voltage select, bit 2 DAC1CTRL_VOSEL3: .equ 3 ; DAC output voltage select, bit 3 DAC1CTRL_VOSEL4: .equ 4 ; DAC output voltage select, bit 4 DAC1CTRL_VRSEL: .equ 6 ; Supply voltage reference source select. This bit selects the supply reference source DAC1CTRL_DACEN: .equ 7 ; DAC enable. When the module is disabled, the DAC is powered down to conserve power ; bit position masks mDAC1CTRL_VOSEL0: .equ %00000001 mDAC1CTRL_VOSEL1: .equ %00000010 mDAC1CTRL_VOSEL2: .equ %00000100 mDAC1CTRL_VOSEL3: .equ %00001000 mDAC1CTRL_VOSEL4: .equ %00010000 mDAC1CTRL_VRSEL: .equ %01000000 mDAC1CTRL_DACEN: .equ %10000000 ;*** DAC2CTRL - DAC Control Register; 0xFFFF802E *** DAC2CTRL: .equ $FFFF802E ;*** DAC2CTRL - DAC Control Register; 0xFFFF802E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DAC2CTRL_VOSEL0: .equ 0 ; DAC output voltage select, bit 0 DAC2CTRL_VOSEL1: .equ 1 ; DAC output voltage select, bit 1 DAC2CTRL_VOSEL2: .equ 2 ; DAC output voltage select, bit 2 DAC2CTRL_VOSEL3: .equ 3 ; DAC output voltage select, bit 3 DAC2CTRL_VOSEL4: .equ 4 ; DAC output voltage select, bit 4 DAC2CTRL_VRSEL: .equ 6 ; Supply voltage reference source select. This bit selects the supply reference source DAC2CTRL_DACEN: .equ 7 ; DAC enable. When the module is disabled, the DAC is powered down to conserve power ; bit position masks mDAC2CTRL_VOSEL0: .equ %00000001 mDAC2CTRL_VOSEL1: .equ %00000010 mDAC2CTRL_VOSEL2: .equ %00000100 mDAC2CTRL_VOSEL3: .equ %00001000 mDAC2CTRL_VOSEL4: .equ %00010000 mDAC2CTRL_VRSEL: .equ %01000000 mDAC2CTRL_DACEN: .equ %10000000 ;*** ADCSC1A - ADC Status and control register 1A; 0xFFFF8030 *** ADCSC1A: .equ $FFFF8030 ;*** ADCSC1A - ADC Status and control register 1A; 0xFFFF8030 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADCSC1A_ADCH0: .equ 0 ; Input Channel Select, bit 0 ADCSC1A_ADCH1: .equ 1 ; Input Channel Select, bit 1 ADCSC1A_ADCH2: .equ 2 ; Input Channel Select, bit 2 ADCSC1A_ADCH3: .equ 3 ; Input Channel Select, bit 3 ADCSC1A_ADCH4: .equ 4 ; Input Channel Select, bit 4 ADCSC1A_ADCO: .equ 5 ; Continuous Conversion Enable ADCSC1A_AIEN: .equ 6 ; Interrupt Enable ADCSC1A_COCO: .equ 7 ; Conversion Complete Flag ; bit position masks mADCSC1A_ADCH0: .equ %00000001 mADCSC1A_ADCH1: .equ %00000010 mADCSC1A_ADCH2: .equ %00000100 mADCSC1A_ADCH3: .equ %00001000 mADCSC1A_ADCH4: .equ %00010000 mADCSC1A_ADCO: .equ %00100000 mADCSC1A_AIEN: .equ %01000000 mADCSC1A_COCO: .equ %10000000 ;*** ADCSC2 - ADC Status and control register 2; 0xFFFF8032 *** ADCSC2: .equ $FFFF8032 ;*** ADCSC2 - ADC Status and control register 2; 0xFFFF8032 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADCSC2_REFSEL0: .equ 0 ; REFSEL, bit 0 ADCSC2_REFSEL1: .equ 1 ; REFSEL, bit 1 ADCSC2_DMAEN: .equ 3 ; DMA Enable ADCSC2_BB: .equ 4 ; Back-to-back Conversion Enable ADCSC2_ADTRG: .equ 6 ; Conversion Trigger Select ADCSC2_ADACT: .equ 7 ; Conversion Active ; bit position masks mADCSC2_REFSEL0: .equ %00000001 mADCSC2_REFSEL1: .equ %00000010 mADCSC2_DMAEN: .equ %00001000 mADCSC2_BB: .equ %00010000 mADCSC2_ADTRG: .equ %01000000 mADCSC2_ADACT: .equ %10000000 ;*** ADCCFG - ADC Configuration register; 0xFFFF803C *** ADCCFG: .equ $FFFF803C ;*** ADCCFG - ADC Configuration register; 0xFFFF803C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADCCFG_ADICLK0: .equ 0 ; Input Clock Select, bit 0 ADCCFG_ADICLK1: .equ 1 ; Input Clock Select, bit 1 ADCCFG_MODE0: .equ 2 ; Conversion Mode Selection, bit 0 ADCCFG_MODE1: .equ 3 ; Conversion Mode Selection, bit 1 ADCCFG_ADLSMP: .equ 4 ; Long Sample Time Configuration ADCCFG_ADIV0: .equ 5 ; Clock Divide Select, bit 0 ADCCFG_ADIV1: .equ 6 ; Clock Divide Select, bit 1 ADCCFG_ADLPC: .equ 7 ; Low Power Configuration ; bit position masks mADCCFG_ADICLK0: .equ %00000001 mADCCFG_ADICLK1: .equ %00000010 mADCCFG_MODE0: .equ %00000100 mADCCFG_MODE1: .equ %00001000 mADCCFG_ADLSMP: .equ %00010000 mADCCFG_ADIV0: .equ %00100000 mADCCFG_ADIV1: .equ %01000000 mADCCFG_ADLPC: .equ %10000000 ;*** ADCSC1B - ADC Status and control register 1B; 0xFFFF8044 *** ADCSC1B: .equ $FFFF8044 ;*** ADCSC1B - ADC Status and control register 1B; 0xFFFF8044 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADCSC1B_ADCH0: .equ 0 ; Input Channel Select, bit 0 ADCSC1B_ADCH1: .equ 1 ; Input Channel Select, bit 1 ADCSC1B_ADCH2: .equ 2 ; Input Channel Select, bit 2 ADCSC1B_ADCH3: .equ 3 ; Input Channel Select, bit 3 ADCSC1B_ADCH4: .equ 4 ; Input Channel Select, bit 4 ADCSC1B_ADCO: .equ 5 ; Continuous Conversion Enable ADCSC1B_AIEN: .equ 6 ; Interrupt Enable ADCSC1B_COCO: .equ 7 ; Conversion Complete Flag ; bit position masks mADCSC1B_ADCH0: .equ %00000001 mADCSC1B_ADCH1: .equ %00000010 mADCSC1B_ADCH2: .equ %00000100 mADCSC1B_ADCH3: .equ %00001000 mADCSC1B_ADCH4: .equ %00010000 mADCSC1B_ADCO: .equ %00100000 mADCSC1B_AIEN: .equ %01000000 mADCSC1B_COCO: .equ %10000000 ;*** ADCRA - ADC Data Result Registers A; 0xFFFF8046 *** ADCRA: .equ $FFFF8046 ;*** ADCRA - ADC Data Result Registers A; 0xFFFF8046 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADCRA_ADR0: .equ 3 ; Digital Result of the Conversion, bit 0 ADCRA_ADR1: .equ 4 ; Digital Result of the Conversion, bit 1 ADCRA_ADR2: .equ 5 ; Digital Result of the Conversion, bit 2 ADCRA_ADR3: .equ 6 ; Digital Result of the Conversion, bit 3 ADCRA_ADR4: .equ 7 ; Digital Result of the Conversion, bit 4 ADCRA_ADR5: .equ 8 ; Digital Result of the Conversion, bit 5 ADCRA_ADR6: .equ 9 ; Digital Result of the Conversion, bit 6 ADCRA_ADR7: .equ 10 ; Digital Result of the Conversion, bit 7 ADCRA_ADR8: .equ 11 ; Digital Result of the Conversion, bit 8 ADCRA_ADR9: .equ 12 ; Digital Result of the Conversion, bit 9 ADCRA_ADR10: .equ 13 ; Digital Result of the Conversion, bit 10 ADCRA_ADR11: .equ 14 ; Digital Result of the Conversion, bit 11 ; bit position masks mADCRA_ADR0: .equ %00001000 mADCRA_ADR1: .equ %00010000 mADCRA_ADR2: .equ %00100000 mADCRA_ADR3: .equ %01000000 mADCRA_ADR4: .equ %10000000 mADCRA_ADR5: .equ %100000000 mADCRA_ADR6: .equ %1000000000 mADCRA_ADR7: .equ %10000000000 mADCRA_ADR8: .equ %100000000000 mADCRA_ADR9: .equ %1000000000000 mADCRA_ADR10: .equ %10000000000000 mADCRA_ADR11: .equ %100000000000000 ;*** ADCRB - ADC Data Result Registers B; 0xFFFF8048 *** ADCRB: .equ $FFFF8048 ;*** ADCRB - ADC Data Result Registers B; 0xFFFF8048 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET ADCRB_ADR0: .equ 3 ; Digital Result of the Conversion, bit 0 ADCRB_ADR1: .equ 4 ; Digital Result of the Conversion, bit 1 ADCRB_ADR2: .equ 5 ; Digital Result of the Conversion, bit 2 ADCRB_ADR3: .equ 6 ; Digital Result of the Conversion, bit 3 ADCRB_ADR4: .equ 7 ; Digital Result of the Conversion, bit 4 ADCRB_ADR5: .equ 8 ; Digital Result of the Conversion, bit 5 ADCRB_ADR6: .equ 9 ; Digital Result of the Conversion, bit 6 ADCRB_ADR7: .equ 10 ; Digital Result of the Conversion, bit 7 ADCRB_ADR8: .equ 11 ; Digital Result of the Conversion, bit 8 ADCRB_ADR9: .equ 12 ; Digital Result of the Conversion, bit 9 ADCRB_ADR10: .equ 13 ; Digital Result of the Conversion, bit 10 ADCRB_ADR11: .equ 14 ; Digital Result of the Conversion, bit 11 ; bit position masks mADCRB_ADR0: .equ %00001000 mADCRB_ADR1: .equ %00010000 mADCRB_ADR2: .equ %00100000 mADCRB_ADR3: .equ %01000000 mADCRB_ADR4: .equ %10000000 mADCRB_ADR5: .equ %100000000 mADCRB_ADR6: .equ %1000000000 mADCRB_ADR7: .equ %10000000000 mADCRB_ADR8: .equ %100000000000 mADCRB_ADR9: .equ %1000000000000 mADCRB_ADR10: .equ %10000000000000 mADCRB_ADR11: .equ %100000000000000 ;*** SCI1BD - SCI1 Baud Rate Register; 0xFFFF8050 *** SCI1BD: .equ $FFFF8050 ;*** SCI1BD - SCI1 Baud Rate Register; 0xFFFF8050 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1BD_SBR0: .equ 0 ; Baud Rate Modulo Divisor Bit 0 SCI1BD_SBR1: .equ 1 ; Baud Rate Modulo Divisor Bit 1 SCI1BD_SBR2: .equ 2 ; Baud Rate Modulo Divisor Bit 2 SCI1BD_SBR3: .equ 3 ; Baud Rate Modulo Divisor Bit 3 SCI1BD_SBR4: .equ 4 ; Baud Rate Modulo Divisor Bit 4 SCI1BD_SBR5: .equ 5 ; Baud Rate Modulo Divisor Bit 5 SCI1BD_SBR6: .equ 6 ; Baud Rate Modulo Divisor Bit 6 SCI1BD_SBR7: .equ 7 ; Baud Rate Modulo Divisor Bit 7 SCI1BD_SBR8: .equ 8 ; Baud Rate Modulo Divisor Bit 8 SCI1BD_SBR9: .equ 9 ; Baud Rate Modulo Divisor Bit 9 SCI1BD_SBR10: .equ 10 ; Baud Rate Modulo Divisor Bit 10 SCI1BD_SBR11: .equ 11 ; Baud Rate Modulo Divisor Bit 11 SCI1BD_SBR12: .equ 12 ; Baud Rate Modulo Divisor Bit 12 SCI1BD_RXEDGIE: .equ 14 ; RxD Input Active Edge Interrupt Enable (for RXEDGIF) SCI1BD_LBKDIE: .equ 15 ; LIN Break Detect Interrupt Enable (for LBKDIF) ; bit position masks mSCI1BD_SBR0: .equ %00000001 mSCI1BD_SBR1: .equ %00000010 mSCI1BD_SBR2: .equ %00000100 mSCI1BD_SBR3: .equ %00001000 mSCI1BD_SBR4: .equ %00010000 mSCI1BD_SBR5: .equ %00100000 mSCI1BD_SBR6: .equ %01000000 mSCI1BD_SBR7: .equ %10000000 mSCI1BD_SBR8: .equ %100000000 mSCI1BD_SBR9: .equ %1000000000 mSCI1BD_SBR10: .equ %10000000000 mSCI1BD_SBR11: .equ %100000000000 mSCI1BD_SBR12: .equ %1000000000000 mSCI1BD_RXEDGIE: .equ %100000000000000 mSCI1BD_LBKDIE: .equ %1000000000000000 ;*** SCI1BDH - SCI1 Baud Rate Register High; 0xFFFF8050 *** SCI1BDH: .equ $FFFF8050 ;*** SCI1BDH - SCI1 Baud Rate Register High; 0xFFFF8050 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1BDH_SBR8: .equ 0 ; Baud Rate Modulo Divisor Bit 8 SCI1BDH_SBR9: .equ 1 ; Baud Rate Modulo Divisor Bit 9 SCI1BDH_SBR10: .equ 2 ; Baud Rate Modulo Divisor Bit 10 SCI1BDH_SBR11: .equ 3 ; Baud Rate Modulo Divisor Bit 11 SCI1BDH_SBR12: .equ 4 ; Baud Rate Modulo Divisor Bit 12 SCI1BDH_RXEDGIE: .equ 6 ; RxD Input Active Edge Interrupt Enable (for RXEDGIF) SCI1BDH_LBKDIE: .equ 7 ; LIN Break Detect Interrupt Enable (for LBKDIF) ; bit position masks mSCI1BDH_SBR8: .equ %00000001 mSCI1BDH_SBR9: .equ %00000010 mSCI1BDH_SBR10: .equ %00000100 mSCI1BDH_SBR11: .equ %00001000 mSCI1BDH_SBR12: .equ %00010000 mSCI1BDH_RXEDGIE: .equ %01000000 mSCI1BDH_LBKDIE: .equ %10000000 ;*** SCI1BDL - SCI1 Baud Rate Register Low; 0xFFFF8051 *** SCI1BDL: .equ $FFFF8051 ;*** SCI1BDL - SCI1 Baud Rate Register Low; 0xFFFF8051 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1BDL_SBR0: .equ 0 ; Baud Rate Modulo Divisor Bit 0 SCI1BDL_SBR1: .equ 1 ; Baud Rate Modulo Divisor Bit 1 SCI1BDL_SBR2: .equ 2 ; Baud Rate Modulo Divisor Bit 2 SCI1BDL_SBR3: .equ 3 ; Baud Rate Modulo Divisor Bit 3 SCI1BDL_SBR4: .equ 4 ; Baud Rate Modulo Divisor Bit 4 SCI1BDL_SBR5: .equ 5 ; Baud Rate Modulo Divisor Bit 5 SCI1BDL_SBR6: .equ 6 ; Baud Rate Modulo Divisor Bit 6 SCI1BDL_SBR7: .equ 7 ; Baud Rate Modulo Divisor Bit 7 ; bit position masks mSCI1BDL_SBR0: .equ %00000001 mSCI1BDL_SBR1: .equ %00000010 mSCI1BDL_SBR2: .equ %00000100 mSCI1BDL_SBR3: .equ %00001000 mSCI1BDL_SBR4: .equ %00010000 mSCI1BDL_SBR5: .equ %00100000 mSCI1BDL_SBR6: .equ %01000000 mSCI1BDL_SBR7: .equ %10000000 ;*** SCI1C1 - SCI1 Control Register 1; 0xFFFF8052 *** SCI1C1: .equ $FFFF8052 ;*** SCI1C1 - SCI1 Control Register 1; 0xFFFF8052 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1C1_PT: .equ 0 ; Parity Type SCI1C1_PE: .equ 1 ; Parity Enable SCI1C1_ILT: .equ 2 ; Idle Line Type Select SCI1C1_WAKE: .equ 3 ; Receiver Wakeup Method Select SCI1C1_M: .equ 4 ; 9-Bit or 8-Bit Mode Select SCI1C1_RSRC: .equ 5 ; Receiver Source Select SCI1C1_SCISWAI: .equ 6 ; SCI Stops in Wait Mode SCI1C1_LOOPS: .equ 7 ; Loop Mode Select ; bit position masks mSCI1C1_PT: .equ %00000001 mSCI1C1_PE: .equ %00000010 mSCI1C1_ILT: .equ %00000100 mSCI1C1_WAKE: .equ %00001000 mSCI1C1_M: .equ %00010000 mSCI1C1_RSRC: .equ %00100000 mSCI1C1_SCISWAI: .equ %01000000 mSCI1C1_LOOPS: .equ %10000000 ;*** SCI1C2 - SCI1 Control Register 2; 0xFFFF8053 *** SCI1C2: .equ $FFFF8053 ;*** SCI1C2 - SCI1 Control Register 2; 0xFFFF8053 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1C2_SBK: .equ 0 ; Send Break SCI1C2_RWU: .equ 1 ; Receiver Wakeup Control SCI1C2_RE: .equ 2 ; Receiver Enable SCI1C2_TE: .equ 3 ; Transmitter Enable SCI1C2_ILIE: .equ 4 ; Idle Line Interrupt Enable (for IDLE) SCI1C2_RIE: .equ 5 ; Receiver Interrupt Enable (for RDRF) SCI1C2_TCIE: .equ 6 ; Transmission Complete Interrupt Enable (for TC) SCI1C2_TIE: .equ 7 ; Transmit Interrupt Enable (for TDRE) ; bit position masks mSCI1C2_SBK: .equ %00000001 mSCI1C2_RWU: .equ %00000010 mSCI1C2_RE: .equ %00000100 mSCI1C2_TE: .equ %00001000 mSCI1C2_ILIE: .equ %00010000 mSCI1C2_RIE: .equ %00100000 mSCI1C2_TCIE: .equ %01000000 mSCI1C2_TIE: .equ %10000000 ;*** SCI1S1 - SCI1 Status Register 1; 0xFFFF8054 *** SCI1S1: .equ $FFFF8054 ;*** SCI1S1 - SCI1 Status Register 1; 0xFFFF8054 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1S1_PF: .equ 0 ; Parity Error Flag SCI1S1_FE: .equ 1 ; Framing Error Flag SCI1S1_NF: .equ 2 ; Noise Flag SCI1S1_OR: .equ 3 ; Receiver Overrun Flag SCI1S1_IDLE: .equ 4 ; Idle Line Flag SCI1S1_RDRF: .equ 5 ; Receive Data Register Full Flag SCI1S1_TC: .equ 6 ; Transmission Complete Flag SCI1S1_TDRE: .equ 7 ; Transmit Data Register Empty Flag ; bit position masks mSCI1S1_PF: .equ %00000001 mSCI1S1_FE: .equ %00000010 mSCI1S1_NF: .equ %00000100 mSCI1S1_OR: .equ %00001000 mSCI1S1_IDLE: .equ %00010000 mSCI1S1_RDRF: .equ %00100000 mSCI1S1_TC: .equ %01000000 mSCI1S1_TDRE: .equ %10000000 ;*** SCI1S2 - SCI1 Status Register 2; 0xFFFF8055 *** SCI1S2: .equ $FFFF8055 ;*** SCI1S2 - SCI1 Status Register 2; 0xFFFF8055 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1S2_RAF: .equ 0 ; Receiver Active Flag SCI1S2_LBKDE: .equ 1 ; LIN Break Detection Enable SCI1S2_BRK13: .equ 2 ; Break Character Generation Length SCI1S2_RWUID: .equ 3 ; Receive Wake Up Idle Detect SCI1S2_RXINV: .equ 4 ; Receive Data Inversion SCI1S2_RXEDGIF: .equ 6 ; RxD Pin Active Edge Interrupt Flag SCI1S2_LBKDIF: .equ 7 ; LIN Break Detect Interrupt Flag ; bit position masks mSCI1S2_RAF: .equ %00000001 mSCI1S2_LBKDE: .equ %00000010 mSCI1S2_BRK13: .equ %00000100 mSCI1S2_RWUID: .equ %00001000 mSCI1S2_RXINV: .equ %00010000 mSCI1S2_RXEDGIF: .equ %01000000 mSCI1S2_LBKDIF: .equ %10000000 ;*** SCI1C3 - SCI1 Control Register 3; 0xFFFF8056 *** SCI1C3: .equ $FFFF8056 ;*** SCI1C3 - SCI1 Control Register 3; 0xFFFF8056 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1C3_PEIE: .equ 0 ; Parity Error Interrupt Enable SCI1C3_FEIE: .equ 1 ; Framing Error Interrupt Enable SCI1C3_NEIE: .equ 2 ; Noise Error Interrupt Enable SCI1C3_ORIE: .equ 3 ; Overrun Interrupt Enable SCI1C3_TXINV: .equ 4 ; Transmit Data Inversion SCI1C3_TXDIR: .equ 5 ; TxD Pin Direction in Single-Wire Mode SCI1C3_T8: .equ 6 ; Ninth Data Bit for Transmitter SCI1C3_R8: .equ 7 ; Ninth Data Bit for Receiver ; bit position masks mSCI1C3_PEIE: .equ %00000001 mSCI1C3_FEIE: .equ %00000010 mSCI1C3_NEIE: .equ %00000100 mSCI1C3_ORIE: .equ %00001000 mSCI1C3_TXINV: .equ %00010000 mSCI1C3_TXDIR: .equ %00100000 mSCI1C3_T8: .equ %01000000 mSCI1C3_R8: .equ %10000000 ;*** SCI1D - SCI1 Data Register; 0xFFFF8057 *** SCI1D: .equ $FFFF8057 ;*** SCI1D - SCI1 Data Register; 0xFFFF8057 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1D_R0_T0: .equ 0 ; Receive/Transmit Data Bit 0 SCI1D_R1_T1: .equ 1 ; Receive/Transmit Data Bit 1 SCI1D_R2_T2: .equ 2 ; Receive/Transmit Data Bit 2 SCI1D_R3_T3: .equ 3 ; Receive/Transmit Data Bit 3 SCI1D_R4_T4: .equ 4 ; Receive/Transmit Data Bit 4 SCI1D_R5_T5: .equ 5 ; Receive/Transmit Data Bit 5 SCI1D_R6_T6: .equ 6 ; Receive/Transmit Data Bit 6 SCI1D_R7_T7: .equ 7 ; Receive/Transmit Data Bit 7 ; bit position masks mSCI1D_R0_T0: .equ %00000001 mSCI1D_R1_T1: .equ %00000010 mSCI1D_R2_T2: .equ %00000100 mSCI1D_R3_T3: .equ %00001000 mSCI1D_R4_T4: .equ %00010000 mSCI1D_R5_T5: .equ %00100000 mSCI1D_R6_T6: .equ %01000000 mSCI1D_R7_T7: .equ %10000000 ;*** SCI1MA1 - SCI1 Match Address Registers 1; 0xFFFF8058 *** SCI1MA1: .equ $FFFF8058 ;*** SCI1MA1 - SCI1 Match Address Registers 1; 0xFFFF8058 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1MA1_MA0: .equ 0 ; Match address value, bit 0 SCI1MA1_MA1: .equ 1 ; Match address value, bit 1 SCI1MA1_MA2: .equ 2 ; Match address value, bit 2 SCI1MA1_MA3: .equ 3 ; Match address value, bit 3 SCI1MA1_MA4: .equ 4 ; Match address value, bit 4 SCI1MA1_MA5: .equ 5 ; Match address value, bit 5 SCI1MA1_MA6: .equ 6 ; Match address value, bit 6 SCI1MA1_MA7: .equ 7 ; Match address value, bit 7 ; bit position masks mSCI1MA1_MA0: .equ %00000001 mSCI1MA1_MA1: .equ %00000010 mSCI1MA1_MA2: .equ %00000100 mSCI1MA1_MA3: .equ %00001000 mSCI1MA1_MA4: .equ %00010000 mSCI1MA1_MA5: .equ %00100000 mSCI1MA1_MA6: .equ %01000000 mSCI1MA1_MA7: .equ %10000000 ;*** SCI1MA2 - SCI1 Match Address Registers 2; 0xFFFF8059 *** SCI1MA2: .equ $FFFF8059 ;*** SCI1MA2 - SCI1 Match Address Registers 2; 0xFFFF8059 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1MA2_MA0: .equ 0 ; Match address value, bit 0 SCI1MA2_MA1: .equ 1 ; Match address value, bit 1 SCI1MA2_MA2: .equ 2 ; Match address value, bit 2 SCI1MA2_MA3: .equ 3 ; Match address value, bit 3 SCI1MA2_MA4: .equ 4 ; Match address value, bit 4 SCI1MA2_MA5: .equ 5 ; Match address value, bit 5 SCI1MA2_MA6: .equ 6 ; Match address value, bit 6 SCI1MA2_MA7: .equ 7 ; Match address value, bit 7 ; bit position masks mSCI1MA2_MA0: .equ %00000001 mSCI1MA2_MA1: .equ %00000010 mSCI1MA2_MA2: .equ %00000100 mSCI1MA2_MA3: .equ %00001000 mSCI1MA2_MA4: .equ %00010000 mSCI1MA2_MA5: .equ %00100000 mSCI1MA2_MA6: .equ %01000000 mSCI1MA2_MA7: .equ %10000000 ;*** SCI1C4 - SCI1 Control Register 4; 0xFFFF805A *** SCI1C4: .equ $FFFF805A ;*** SCI1C4 - SCI1 Control Register 4; 0xFFFF805A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1C4_BRFA0: .equ 0 ; Baud rate fine adjust, bit 0 SCI1C4_BRFA1: .equ 1 ; Baud rate fine adjust, bit 1 SCI1C4_BRFA2: .equ 2 ; Baud rate fine adjust, bit 2 SCI1C4_BRFA3: .equ 3 ; Baud rate fine adjust, bit 3 SCI1C4_BRFA4: .equ 4 ; Baud rate fine adjust, bit 4 SCI1C4_MAEN2: .equ 6 ; Match Address Mode Enable 2 SCI1C4_MAEN1: .equ 7 ; Match Address Mode Enable 1 ; bit position masks mSCI1C4_BRFA0: .equ %00000001 mSCI1C4_BRFA1: .equ %00000010 mSCI1C4_BRFA2: .equ %00000100 mSCI1C4_BRFA3: .equ %00001000 mSCI1C4_BRFA4: .equ %00010000 mSCI1C4_MAEN2: .equ %01000000 mSCI1C4_MAEN1: .equ %10000000 ;*** SCI1C5 - SCI1 Control Register 5; 0xFFFF805B *** SCI1C5: .equ $FFFF805B ;*** SCI1C5 - SCI1 Control Register 5; 0xFFFF805B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI1C5_RDMAS: .equ 5 ; Receiver Full DMA Select SCI1C5_TDMAS: .equ 7 ; Transmitter DMA Select ; bit position masks mSCI1C5_RDMAS: .equ %00100000 mSCI1C5_TDMAS: .equ %10000000 ;*** SCI2BD - SCI2 Baud Rate Register; 0xFFFF8060 *** SCI2BD: .equ $FFFF8060 ;*** SCI2BD - SCI2 Baud Rate Register; 0xFFFF8060 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2BD_SBR0: .equ 0 ; Baud Rate Modulo Divisor Bit 0 SCI2BD_SBR1: .equ 1 ; Baud Rate Modulo Divisor Bit 1 SCI2BD_SBR2: .equ 2 ; Baud Rate Modulo Divisor Bit 2 SCI2BD_SBR3: .equ 3 ; Baud Rate Modulo Divisor Bit 3 SCI2BD_SBR4: .equ 4 ; Baud Rate Modulo Divisor Bit 4 SCI2BD_SBR5: .equ 5 ; Baud Rate Modulo Divisor Bit 5 SCI2BD_SBR6: .equ 6 ; Baud Rate Modulo Divisor Bit 6 SCI2BD_SBR7: .equ 7 ; Baud Rate Modulo Divisor Bit 7 SCI2BD_SBR8: .equ 8 ; Baud Rate Modulo Divisor Bit 8 SCI2BD_SBR9: .equ 9 ; Baud Rate Modulo Divisor Bit 9 SCI2BD_SBR10: .equ 10 ; Baud Rate Modulo Divisor Bit 10 SCI2BD_SBR11: .equ 11 ; Baud Rate Modulo Divisor Bit 11 SCI2BD_SBR12: .equ 12 ; Baud Rate Modulo Divisor Bit 12 SCI2BD_RXEDGIE: .equ 14 ; RxD Input Active Edge Interrupt Enable (for RXEDGIF) SCI2BD_LBKDIE: .equ 15 ; LIN Break Detect Interrupt Enable (for LBKDIF) ; bit position masks mSCI2BD_SBR0: .equ %00000001 mSCI2BD_SBR1: .equ %00000010 mSCI2BD_SBR2: .equ %00000100 mSCI2BD_SBR3: .equ %00001000 mSCI2BD_SBR4: .equ %00010000 mSCI2BD_SBR5: .equ %00100000 mSCI2BD_SBR6: .equ %01000000 mSCI2BD_SBR7: .equ %10000000 mSCI2BD_SBR8: .equ %100000000 mSCI2BD_SBR9: .equ %1000000000 mSCI2BD_SBR10: .equ %10000000000 mSCI2BD_SBR11: .equ %100000000000 mSCI2BD_SBR12: .equ %1000000000000 mSCI2BD_RXEDGIE: .equ %100000000000000 mSCI2BD_LBKDIE: .equ %1000000000000000 ;*** SCI2BDH - SCI2 Baud Rate Register High; 0xFFFF8060 *** SCI2BDH: .equ $FFFF8060 ;*** SCI2BDH - SCI2 Baud Rate Register High; 0xFFFF8060 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2BDH_SBR8: .equ 0 ; Baud Rate Modulo Divisor Bit 8 SCI2BDH_SBR9: .equ 1 ; Baud Rate Modulo Divisor Bit 9 SCI2BDH_SBR10: .equ 2 ; Baud Rate Modulo Divisor Bit 10 SCI2BDH_SBR11: .equ 3 ; Baud Rate Modulo Divisor Bit 11 SCI2BDH_SBR12: .equ 4 ; Baud Rate Modulo Divisor Bit 12 SCI2BDH_RXEDGIE: .equ 6 ; RxD Input Active Edge Interrupt Enable (for RXEDGIF) SCI2BDH_LBKDIE: .equ 7 ; LIN Break Detect Interrupt Enable (for LBKDIF) ; bit position masks mSCI2BDH_SBR8: .equ %00000001 mSCI2BDH_SBR9: .equ %00000010 mSCI2BDH_SBR10: .equ %00000100 mSCI2BDH_SBR11: .equ %00001000 mSCI2BDH_SBR12: .equ %00010000 mSCI2BDH_RXEDGIE: .equ %01000000 mSCI2BDH_LBKDIE: .equ %10000000 ;*** SCI2BDL - SCI2 Baud Rate Register Low; 0xFFFF8061 *** SCI2BDL: .equ $FFFF8061 ;*** SCI2BDL - SCI2 Baud Rate Register Low; 0xFFFF8061 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2BDL_SBR0: .equ 0 ; Baud Rate Modulo Divisor Bit 0 SCI2BDL_SBR1: .equ 1 ; Baud Rate Modulo Divisor Bit 1 SCI2BDL_SBR2: .equ 2 ; Baud Rate Modulo Divisor Bit 2 SCI2BDL_SBR3: .equ 3 ; Baud Rate Modulo Divisor Bit 3 SCI2BDL_SBR4: .equ 4 ; Baud Rate Modulo Divisor Bit 4 SCI2BDL_SBR5: .equ 5 ; Baud Rate Modulo Divisor Bit 5 SCI2BDL_SBR6: .equ 6 ; Baud Rate Modulo Divisor Bit 6 SCI2BDL_SBR7: .equ 7 ; Baud Rate Modulo Divisor Bit 7 ; bit position masks mSCI2BDL_SBR0: .equ %00000001 mSCI2BDL_SBR1: .equ %00000010 mSCI2BDL_SBR2: .equ %00000100 mSCI2BDL_SBR3: .equ %00001000 mSCI2BDL_SBR4: .equ %00010000 mSCI2BDL_SBR5: .equ %00100000 mSCI2BDL_SBR6: .equ %01000000 mSCI2BDL_SBR7: .equ %10000000 ;*** SCI2C1 - SCI2 Control Register 1; 0xFFFF8062 *** SCI2C1: .equ $FFFF8062 ;*** SCI2C1 - SCI2 Control Register 1; 0xFFFF8062 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2C1_PT: .equ 0 ; Parity Type SCI2C1_PE: .equ 1 ; Parity Enable SCI2C1_ILT: .equ 2 ; Idle Line Type Select SCI2C1_WAKE: .equ 3 ; Receiver Wakeup Method Select SCI2C1_M: .equ 4 ; 9-Bit or 8-Bit Mode Select SCI2C1_RSRC: .equ 5 ; Receiver Source Select SCI2C1_SCISWAI: .equ 6 ; SCI Stops in Wait Mode SCI2C1_LOOPS: .equ 7 ; Loop Mode Select ; bit position masks mSCI2C1_PT: .equ %00000001 mSCI2C1_PE: .equ %00000010 mSCI2C1_ILT: .equ %00000100 mSCI2C1_WAKE: .equ %00001000 mSCI2C1_M: .equ %00010000 mSCI2C1_RSRC: .equ %00100000 mSCI2C1_SCISWAI: .equ %01000000 mSCI2C1_LOOPS: .equ %10000000 ;*** SCI2C2 - SCI2 Control Register 2; 0xFFFF8063 *** SCI2C2: .equ $FFFF8063 ;*** SCI2C2 - SCI2 Control Register 2; 0xFFFF8063 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2C2_SBK: .equ 0 ; Send Break SCI2C2_RWU: .equ 1 ; Receiver Wakeup Control SCI2C2_RE: .equ 2 ; Receiver Enable SCI2C2_TE: .equ 3 ; Transmitter Enable SCI2C2_ILIE: .equ 4 ; Idle Line Interrupt Enable (for IDLE) SCI2C2_RIE: .equ 5 ; Receiver Interrupt Enable (for RDRF) SCI2C2_TCIE: .equ 6 ; Transmission Complete Interrupt Enable (for TC) SCI2C2_TIE: .equ 7 ; Transmit Interrupt Enable (for TDRE) ; bit position masks mSCI2C2_SBK: .equ %00000001 mSCI2C2_RWU: .equ %00000010 mSCI2C2_RE: .equ %00000100 mSCI2C2_TE: .equ %00001000 mSCI2C2_ILIE: .equ %00010000 mSCI2C2_RIE: .equ %00100000 mSCI2C2_TCIE: .equ %01000000 mSCI2C2_TIE: .equ %10000000 ;*** SCI2S1 - SCI2 Status Register 1; 0xFFFF8064 *** SCI2S1: .equ $FFFF8064 ;*** SCI2S1 - SCI2 Status Register 1; 0xFFFF8064 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2S1_PF: .equ 0 ; Parity Error Flag SCI2S1_FE: .equ 1 ; Framing Error Flag SCI2S1_NF: .equ 2 ; Noise Flag SCI2S1_OR: .equ 3 ; Receiver Overrun Flag SCI2S1_IDLE: .equ 4 ; Idle Line Flag SCI2S1_RDRF: .equ 5 ; Receive Data Register Full Flag SCI2S1_TC: .equ 6 ; Transmission Complete Flag SCI2S1_TDRE: .equ 7 ; Transmit Data Register Empty Flag ; bit position masks mSCI2S1_PF: .equ %00000001 mSCI2S1_FE: .equ %00000010 mSCI2S1_NF: .equ %00000100 mSCI2S1_OR: .equ %00001000 mSCI2S1_IDLE: .equ %00010000 mSCI2S1_RDRF: .equ %00100000 mSCI2S1_TC: .equ %01000000 mSCI2S1_TDRE: .equ %10000000 ;*** SCI2S2 - SCI2 Status Register 2; 0xFFFF8065 *** SCI2S2: .equ $FFFF8065 ;*** SCI2S2 - SCI2 Status Register 2; 0xFFFF8065 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2S2_RAF: .equ 0 ; Receiver Active Flag SCI2S2_LBKDE: .equ 1 ; LIN Break Detection Enable SCI2S2_BRK13: .equ 2 ; Break Character Generation Length SCI2S2_RWUID: .equ 3 ; Receive Wake Up Idle Detect SCI2S2_RXINV: .equ 4 ; Receive Data Inversion SCI2S2_RXEDGIF: .equ 6 ; RxD Pin Active Edge Interrupt Flag SCI2S2_LBKDIF: .equ 7 ; LIN Break Detect Interrupt Flag ; bit position masks mSCI2S2_RAF: .equ %00000001 mSCI2S2_LBKDE: .equ %00000010 mSCI2S2_BRK13: .equ %00000100 mSCI2S2_RWUID: .equ %00001000 mSCI2S2_RXINV: .equ %00010000 mSCI2S2_RXEDGIF: .equ %01000000 mSCI2S2_LBKDIF: .equ %10000000 ;*** SCI2C3 - SCI2 Control Register 3; 0xFFFF8066 *** SCI2C3: .equ $FFFF8066 ;*** SCI2C3 - SCI2 Control Register 3; 0xFFFF8066 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2C3_PEIE: .equ 0 ; Parity Error Interrupt Enable SCI2C3_FEIE: .equ 1 ; Framing Error Interrupt Enable SCI2C3_NEIE: .equ 2 ; Noise Error Interrupt Enable SCI2C3_ORIE: .equ 3 ; Overrun Interrupt Enable SCI2C3_TXINV: .equ 4 ; Transmit Data Inversion SCI2C3_TXDIR: .equ 5 ; TxD Pin Direction in Single-Wire Mode SCI2C3_T8: .equ 6 ; Ninth Data Bit for Transmitter SCI2C3_R8: .equ 7 ; Ninth Data Bit for Receiver ; bit position masks mSCI2C3_PEIE: .equ %00000001 mSCI2C3_FEIE: .equ %00000010 mSCI2C3_NEIE: .equ %00000100 mSCI2C3_ORIE: .equ %00001000 mSCI2C3_TXINV: .equ %00010000 mSCI2C3_TXDIR: .equ %00100000 mSCI2C3_T8: .equ %01000000 mSCI2C3_R8: .equ %10000000 ;*** SCI2D - SCI2 Data Register; 0xFFFF8067 *** SCI2D: .equ $FFFF8067 ;*** SCI2D - SCI2 Data Register; 0xFFFF8067 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2D_R0_T0: .equ 0 ; Receive/Transmit Data Bit 0 SCI2D_R1_T1: .equ 1 ; Receive/Transmit Data Bit 1 SCI2D_R2_T2: .equ 2 ; Receive/Transmit Data Bit 2 SCI2D_R3_T3: .equ 3 ; Receive/Transmit Data Bit 3 SCI2D_R4_T4: .equ 4 ; Receive/Transmit Data Bit 4 SCI2D_R5_T5: .equ 5 ; Receive/Transmit Data Bit 5 SCI2D_R6_T6: .equ 6 ; Receive/Transmit Data Bit 6 SCI2D_R7_T7: .equ 7 ; Receive/Transmit Data Bit 7 ; bit position masks mSCI2D_R0_T0: .equ %00000001 mSCI2D_R1_T1: .equ %00000010 mSCI2D_R2_T2: .equ %00000100 mSCI2D_R3_T3: .equ %00001000 mSCI2D_R4_T4: .equ %00010000 mSCI2D_R5_T5: .equ %00100000 mSCI2D_R6_T6: .equ %01000000 mSCI2D_R7_T7: .equ %10000000 ;*** SCI2MA1 - SCI2 Match Address Registers 1; 0xFFFF8068 *** SCI2MA1: .equ $FFFF8068 ;*** SCI2MA1 - SCI2 Match Address Registers 1; 0xFFFF8068 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2MA1_MA0: .equ 0 ; Match address value, bit 0 SCI2MA1_MA1: .equ 1 ; Match address value, bit 1 SCI2MA1_MA2: .equ 2 ; Match address value, bit 2 SCI2MA1_MA3: .equ 3 ; Match address value, bit 3 SCI2MA1_MA4: .equ 4 ; Match address value, bit 4 SCI2MA1_MA5: .equ 5 ; Match address value, bit 5 SCI2MA1_MA6: .equ 6 ; Match address value, bit 6 SCI2MA1_MA7: .equ 7 ; Match address value, bit 7 ; bit position masks mSCI2MA1_MA0: .equ %00000001 mSCI2MA1_MA1: .equ %00000010 mSCI2MA1_MA2: .equ %00000100 mSCI2MA1_MA3: .equ %00001000 mSCI2MA1_MA4: .equ %00010000 mSCI2MA1_MA5: .equ %00100000 mSCI2MA1_MA6: .equ %01000000 mSCI2MA1_MA7: .equ %10000000 ;*** SCI2MA2 - SCI2 Match Address Registers 2; 0xFFFF8069 *** SCI2MA2: .equ $FFFF8069 ;*** SCI2MA2 - SCI2 Match Address Registers 2; 0xFFFF8069 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2MA2_MA0: .equ 0 ; Match address value, bit 0 SCI2MA2_MA1: .equ 1 ; Match address value, bit 1 SCI2MA2_MA2: .equ 2 ; Match address value, bit 2 SCI2MA2_MA3: .equ 3 ; Match address value, bit 3 SCI2MA2_MA4: .equ 4 ; Match address value, bit 4 SCI2MA2_MA5: .equ 5 ; Match address value, bit 5 SCI2MA2_MA6: .equ 6 ; Match address value, bit 6 SCI2MA2_MA7: .equ 7 ; Match address value, bit 7 ; bit position masks mSCI2MA2_MA0: .equ %00000001 mSCI2MA2_MA1: .equ %00000010 mSCI2MA2_MA2: .equ %00000100 mSCI2MA2_MA3: .equ %00001000 mSCI2MA2_MA4: .equ %00010000 mSCI2MA2_MA5: .equ %00100000 mSCI2MA2_MA6: .equ %01000000 mSCI2MA2_MA7: .equ %10000000 ;*** SCI2C4 - SCI2 Control Register 4; 0xFFFF806A *** SCI2C4: .equ $FFFF806A ;*** SCI2C4 - SCI2 Control Register 4; 0xFFFF806A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2C4_BRFA0: .equ 0 ; Baud rate fine adjust, bit 0 SCI2C4_BRFA1: .equ 1 ; Baud rate fine adjust, bit 1 SCI2C4_BRFA2: .equ 2 ; Baud rate fine adjust, bit 2 SCI2C4_BRFA3: .equ 3 ; Baud rate fine adjust, bit 3 SCI2C4_BRFA4: .equ 4 ; Baud rate fine adjust, bit 4 SCI2C4_MAEN2: .equ 6 ; Match Address Mode Enable 2 SCI2C4_MAEN1: .equ 7 ; Match Address Mode Enable 1 ; bit position masks mSCI2C4_BRFA0: .equ %00000001 mSCI2C4_BRFA1: .equ %00000010 mSCI2C4_BRFA2: .equ %00000100 mSCI2C4_BRFA3: .equ %00001000 mSCI2C4_BRFA4: .equ %00010000 mSCI2C4_MAEN2: .equ %01000000 mSCI2C4_MAEN1: .equ %10000000 ;*** SCI2C5 - SCI2 Control Register 5; 0xFFFF806B *** SCI2C5: .equ $FFFF806B ;*** SCI2C5 - SCI2 Control Register 5; 0xFFFF806B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCI2C5_RDMAS: .equ 5 ; Receiver Full DMA Select SCI2C5_TDMAS: .equ 7 ; Transmitter DMA Select ; bit position masks mSCI2C5_RDMAS: .equ %00100000 mSCI2C5_TDMAS: .equ %10000000 ;*** TPM3SC - TPM3 Status and Control Register; 0xFFFF8070 *** TPM3SC: .equ $FFFF8070 ;*** TPM3SC - TPM3 Status and Control Register; 0xFFFF8070 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPM3SC_PS0: .equ 0 ; Prescale Divisor Select Bit 0 TPM3SC_PS1: .equ 1 ; Prescale Divisor Select Bit 1 TPM3SC_PS2: .equ 2 ; Prescale Divisor Select Bit 2 TPM3SC_CLKSA: .equ 3 ; Clock Source Select A TPM3SC_CLKSB: .equ 4 ; Clock Source Select B TPM3SC_CPWMS: .equ 5 ; Center-Aligned PWM Select TPM3SC_TOIE: .equ 6 ; Timer Overflow Interrupt Enable TPM3SC_TOF: .equ 7 ; Timer Overflow Flag ; bit position masks mTPM3SC_PS0: .equ %00000001 mTPM3SC_PS1: .equ %00000010 mTPM3SC_PS2: .equ %00000100 mTPM3SC_CLKSA: .equ %00001000 mTPM3SC_CLKSB: .equ %00010000 mTPM3SC_CPWMS: .equ %00100000 mTPM3SC_TOIE: .equ %01000000 mTPM3SC_TOF: .equ %10000000 ;*** TPM3CNT - TPM3 Timer Counter Register; 0xFFFF8071 *** TPM3CNT: .equ $FFFF8071 ;*** TPM3CNT - TPM3 Timer Counter Register; 0xFFFF8071 *** ;*** TPM3CNTH - TPM3 Timer Counter Register High; 0xFFFF8071 *** TPM3CNTH: .equ $FFFF8071 ;*** TPM3CNTH - TPM3 Timer Counter Register High; 0xFFFF8071 *** ;*** TPM3CNTL - TPM3 Timer Counter Register Low; 0xFFFF8072 *** TPM3CNTL: .equ $FFFF8072 ;*** TPM3CNTL - TPM3 Timer Counter Register Low; 0xFFFF8072 *** ;*** TPM3MOD - TPM3 Timer Counter Modulo Register; 0xFFFF8073 *** TPM3MOD: .equ $FFFF8073 ;*** TPM3MOD - TPM3 Timer Counter Modulo Register; 0xFFFF8073 *** ;*** TPM3MODH - TPM3 Timer Counter Modulo Register High; 0xFFFF8073 *** TPM3MODH: .equ $FFFF8073 ;*** TPM3MODH - TPM3 Timer Counter Modulo Register High; 0xFFFF8073 *** ;*** TPM3MODL - TPM3 Timer Counter Modulo Register Low; 0xFFFF8074 *** TPM3MODL: .equ $FFFF8074 ;*** TPM3MODL - TPM3 Timer Counter Modulo Register Low; 0xFFFF8074 *** ;*** TPM3C0SC - TPM3 Timer Channel 0 Status and Control Register; 0xFFFF8075 *** TPM3C0SC: .equ $FFFF8075 ;*** TPM3C0SC - TPM3 Timer Channel 0 Status and Control Register; 0xFFFF8075 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPM3C0SC_ELS0A: .equ 2 ; Edge/Level Select Bit A TPM3C0SC_ELS0B: .equ 3 ; Edge/Level Select Bit B TPM3C0SC_MS0A: .equ 4 ; Mode Select A for TPM Channel 0 TPM3C0SC_MS0B: .equ 5 ; Mode Select B for TPM Channel 0 TPM3C0SC_CH0IE: .equ 6 ; Channel 0 Interrupt Enable TPM3C0SC_CH0F: .equ 7 ; Channel 0 Flag ; bit position masks mTPM3C0SC_ELS0A: .equ %00000100 mTPM3C0SC_ELS0B: .equ %00001000 mTPM3C0SC_MS0A: .equ %00010000 mTPM3C0SC_MS0B: .equ %00100000 mTPM3C0SC_CH0IE: .equ %01000000 mTPM3C0SC_CH0F: .equ %10000000 ;*** TPM3C0V - TPM3 Timer Channel 0 Value Register; 0xFFFF8076 *** TPM3C0V: .equ $FFFF8076 ;*** TPM3C0V - TPM3 Timer Channel 0 Value Register; 0xFFFF8076 *** ;*** TPM3C0VH - TPM3 Timer Channel 0 Value Register High; 0xFFFF8076 *** TPM3C0VH: .equ $FFFF8076 ;*** TPM3C0VH - TPM3 Timer Channel 0 Value Register High; 0xFFFF8076 *** ;*** TPM3C0VL - TPM3 Timer Channel 0 Value Register Low; 0xFFFF8077 *** TPM3C0VL: .equ $FFFF8077 ;*** TPM3C0VL - TPM3 Timer Channel 0 Value Register Low; 0xFFFF8077 *** ;*** TPM3C1SC - TPM3 Timer Channel 1 Status and Control Register; 0xFFFF8078 *** TPM3C1SC: .equ $FFFF8078 ;*** TPM3C1SC - TPM3 Timer Channel 1 Status and Control Register; 0xFFFF8078 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TPM3C1SC_ELS1A: .equ 2 ; Edge/Level Select Bit A TPM3C1SC_ELS1B: .equ 3 ; Edge/Level Select Bit B TPM3C1SC_MS1A: .equ 4 ; Mode Select A for TPM Channel 1 TPM3C1SC_MS1B: .equ 5 ; Mode Select B for TPM Channel 1 TPM3C1SC_CH1IE: .equ 6 ; Channel 1 Interrupt Enable TPM3C1SC_CH1F: .equ 7 ; Channel 1 Flag ; bit position masks mTPM3C1SC_ELS1A: .equ %00000100 mTPM3C1SC_ELS1B: .equ %00001000 mTPM3C1SC_MS1A: .equ %00010000 mTPM3C1SC_MS1B: .equ %00100000 mTPM3C1SC_CH1IE: .equ %01000000 mTPM3C1SC_CH1F: .equ %10000000 ;*** TPM3C1V - TPM3 Timer Channel 1 Value Register; 0xFFFF8079 *** TPM3C1V: .equ $FFFF8079 ;*** TPM3C1V - TPM3 Timer Channel 1 Value Register; 0xFFFF8079 *** ;*** TPM3C1VH - TPM3 Timer Channel 1 Value Register High; 0xFFFF8079 *** TPM3C1VH: .equ $FFFF8079 ;*** TPM3C1VH - TPM3 Timer Channel 1 Value Register High; 0xFFFF8079 *** ;*** TPM3C1VL - TPM3 Timer Channel 1 Value Register Low; 0xFFFF807A *** TPM3C1VL: .equ $FFFF807A ;*** TPM3C1VL - TPM3 Timer Channel 1 Value Register Low; 0xFFFF807A *** ;*** FTM1SC - FTM1 Status and Control Register; 0xFFFF8080 *** FTM1SC: .equ $FFFF8080 ;*** FTM1SC - FTM1 Status and Control Register; 0xFFFF8080 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM1SC_PS0: .equ 0 ; Prescale Divisor Select Bit 0 FTM1SC_PS1: .equ 1 ; Prescale Divisor Select Bit 1 FTM1SC_PS2: .equ 2 ; Prescale Divisor Select Bit 2 FTM1SC_CLKSA: .equ 3 ; Clock Source Select A FTM1SC_CLKSB: .equ 4 ; Clock Source Select B FTM1SC_CPWMS: .equ 5 ; Center-Aligned PWM Select FTM1SC_TOIE: .equ 6 ; Timer Overflow Interrupt Enable FTM1SC_TOF: .equ 7 ; Timer Overflow Flag ; bit position masks mFTM1SC_PS0: .equ %00000001 mFTM1SC_PS1: .equ %00000010 mFTM1SC_PS2: .equ %00000100 mFTM1SC_CLKSA: .equ %00001000 mFTM1SC_CLKSB: .equ %00010000 mFTM1SC_CPWMS: .equ %00100000 mFTM1SC_TOIE: .equ %01000000 mFTM1SC_TOF: .equ %10000000 ;*** FTM1CNT - FTM1 Timer Counter Register; 0xFFFF8081 *** FTM1CNT: .equ $FFFF8081 ;*** FTM1CNT - FTM1 Timer Counter Register; 0xFFFF8081 *** ;*** FTM1CNTH - FTM1 Timer Counter Register High; 0xFFFF8081 *** FTM1CNTH: .equ $FFFF8081 ;*** FTM1CNTH - FTM1 Timer Counter Register High; 0xFFFF8081 *** ;*** FTM1CNTL - FTM1 Timer Counter Register Low; 0xFFFF8082 *** FTM1CNTL: .equ $FFFF8082 ;*** FTM1CNTL - FTM1 Timer Counter Register Low; 0xFFFF8082 *** ;*** FTM1MOD - FTM1 Timer Counter Modulo Register; 0xFFFF8083 *** FTM1MOD: .equ $FFFF8083 ;*** FTM1MOD - FTM1 Timer Counter Modulo Register; 0xFFFF8083 *** ;*** FTM1MODH - FTM1 Timer Counter Modulo Register High; 0xFFFF8083 *** FTM1MODH: .equ $FFFF8083 ;*** FTM1MODH - FTM1 Timer Counter Modulo Register High; 0xFFFF8083 *** ;*** FTM1MODL - FTM1 Timer Counter Modulo Register Low; 0xFFFF8084 *** FTM1MODL: .equ $FFFF8084 ;*** FTM1MODL - FTM1 Timer Counter Modulo Register Low; 0xFFFF8084 *** ;*** FTM1C0SC - FTM1 Timer Channel 0 Status and Control Register; 0xFFFF8085 *** FTM1C0SC: .equ $FFFF8085 ;*** FTM1C0SC - FTM1 Timer Channel 0 Status and Control Register; 0xFFFF8085 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM1C0SC_DMA: .equ 0 ; The DMA bit enables DMA requests on CH0F flag being set rather than issuing a CPU interrupt request FTM1C0SC_ELS0A: .equ 2 ; Edge/Level Select Bit A FTM1C0SC_ELS0B: .equ 3 ; Edge/Level Select Bit B FTM1C0SC_MS0A: .equ 4 ; Mode Select A for FTM1 Channel 0 FTM1C0SC_MS0B: .equ 5 ; Mode Select B for FTM1 Channel 0 FTM1C0SC_CH0IE: .equ 6 ; Channel 0 Interrupt Enable FTM1C0SC_CH0F: .equ 7 ; Channel 0 Flag ; bit position masks mFTM1C0SC_DMA: .equ %00000001 mFTM1C0SC_ELS0A: .equ %00000100 mFTM1C0SC_ELS0B: .equ %00001000 mFTM1C0SC_MS0A: .equ %00010000 mFTM1C0SC_MS0B: .equ %00100000 mFTM1C0SC_CH0IE: .equ %01000000 mFTM1C0SC_CH0F: .equ %10000000 ;*** FTM1C0V - FTM1 Timer Channel 0 Value Register; 0xFFFF8086 *** FTM1C0V: .equ $FFFF8086 ;*** FTM1C0V - FTM1 Timer Channel 0 Value Register; 0xFFFF8086 *** ;*** FTM1C0VH - FTM1 Timer Channel 0 Value Register High; 0xFFFF8086 *** FTM1C0VH: .equ $FFFF8086 ;*** FTM1C0VH - FTM1 Timer Channel 0 Value Register High; 0xFFFF8086 *** ;*** FTM1C0VL - FTM1 Timer Channel 0 Value Register Low; 0xFFFF8087 *** FTM1C0VL: .equ $FFFF8087 ;*** FTM1C0VL - FTM1 Timer Channel 0 Value Register Low; 0xFFFF8087 *** ;*** FTM1C1SC - FTM1 Timer Channel 1 Status and Control Register; 0xFFFF8088 *** FTM1C1SC: .equ $FFFF8088 ;*** FTM1C1SC - FTM1 Timer Channel 1 Status and Control Register; 0xFFFF8088 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM1C1SC_DMA: .equ 0 ; The DMA bit enables DMA requests on CH1F flag being set rather than issuing a CPU interrupt request FTM1C1SC_ELS1A: .equ 2 ; Edge/Level Select Bit A FTM1C1SC_ELS1B: .equ 3 ; Edge/Level Select Bit B FTM1C1SC_MS1A: .equ 4 ; Mode Select A for FTM1 Channel 1 FTM1C1SC_MS1B: .equ 5 ; Mode Select B for FTM1 Channel 1 FTM1C1SC_CH1IE: .equ 6 ; Channel 1 Interrupt Enable FTM1C1SC_CH1F: .equ 7 ; Channel 1 Flag ; bit position masks mFTM1C1SC_DMA: .equ %00000001 mFTM1C1SC_ELS1A: .equ %00000100 mFTM1C1SC_ELS1B: .equ %00001000 mFTM1C1SC_MS1A: .equ %00010000 mFTM1C1SC_MS1B: .equ %00100000 mFTM1C1SC_CH1IE: .equ %01000000 mFTM1C1SC_CH1F: .equ %10000000 ;*** FTM1C1V - FTM1 Timer Channel 1 Value Register; 0xFFFF8089 *** FTM1C1V: .equ $FFFF8089 ;*** FTM1C1V - FTM1 Timer Channel 1 Value Register; 0xFFFF8089 *** ;*** FTM1C1VH - FTM1 Timer Channel 1 Value Register High; 0xFFFF8089 *** FTM1C1VH: .equ $FFFF8089 ;*** FTM1C1VH - FTM1 Timer Channel 1 Value Register High; 0xFFFF8089 *** ;*** FTM1C1VL - FTM1 Timer Channel 1 Value Register Low; 0xFFFF808A *** FTM1C1VL: .equ $FFFF808A ;*** FTM1C1VL - FTM1 Timer Channel 1 Value Register Low; 0xFFFF808A *** ;*** FTM1C2SC - FTM1 Timer Channel 2 Status and Control Register; 0xFFFF808B *** FTM1C2SC: .equ $FFFF808B ;*** FTM1C2SC - FTM1 Timer Channel 2 Status and Control Register; 0xFFFF808B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM1C2SC_DMA: .equ 0 ; The DMA bit enables DMA requests on CH2F flag being set rather than issuing a CPU interrupt request FTM1C2SC_ELS2A: .equ 2 ; Edge/Level Select Bit A FTM1C2SC_ELS2B: .equ 3 ; Edge/Level Select Bit B FTM1C2SC_MS2A: .equ 4 ; Mode Select A for FTM1 Channel 2 FTM1C2SC_MS2B: .equ 5 ; Mode Select B for FTM1 Channel 2 FTM1C2SC_CH2IE: .equ 6 ; Channel 2 Interrupt Enable FTM1C2SC_CH2F: .equ 7 ; Channel 2 Flag ; bit position masks mFTM1C2SC_DMA: .equ %00000001 mFTM1C2SC_ELS2A: .equ %00000100 mFTM1C2SC_ELS2B: .equ %00001000 mFTM1C2SC_MS2A: .equ %00010000 mFTM1C2SC_MS2B: .equ %00100000 mFTM1C2SC_CH2IE: .equ %01000000 mFTM1C2SC_CH2F: .equ %10000000 ;*** FTM1C2V - FTM1 Timer Channel 2 Value Register; 0xFFFF808C *** FTM1C2V: .equ $FFFF808C ;*** FTM1C2V - FTM1 Timer Channel 2 Value Register; 0xFFFF808C *** ;*** FTM1C2VH - FTM1 Timer Channel 2 Value Register High; 0xFFFF808C *** FTM1C2VH: .equ $FFFF808C ;*** FTM1C2VH - FTM1 Timer Channel 2 Value Register High; 0xFFFF808C *** ;*** FTM1C2VL - FTM1 Timer Channel 2 Value Register Low; 0xFFFF808D *** FTM1C2VL: .equ $FFFF808D ;*** FTM1C2VL - FTM1 Timer Channel 2 Value Register Low; 0xFFFF808D *** ;*** FTM1C3SC - FTM1 Timer Channel 3 Status and Control Register; 0xFFFF808E *** FTM1C3SC: .equ $FFFF808E ;*** FTM1C3SC - FTM1 Timer Channel 3 Status and Control Register; 0xFFFF808E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM1C3SC_DMA: .equ 0 ; The DMA bit enables DMA requests on CH3F flag being set rather than issuing a CPU interrupt request FTM1C3SC_ELS3A: .equ 2 ; Edge/Level Select Bit A FTM1C3SC_ELS3B: .equ 3 ; Edge/Level Select Bit B FTM1C3SC_MS3A: .equ 4 ; Mode Select A for FTM1 Channel 3 FTM1C3SC_MS3B: .equ 5 ; Mode Select B for FTM1 Channel 3 FTM1C3SC_CH3IE: .equ 6 ; Channel 3 Interrupt Enable FTM1C3SC_CH3F: .equ 7 ; Channel 3 Flag ; bit position masks mFTM1C3SC_DMA: .equ %00000001 mFTM1C3SC_ELS3A: .equ %00000100 mFTM1C3SC_ELS3B: .equ %00001000 mFTM1C3SC_MS3A: .equ %00010000 mFTM1C3SC_MS3B: .equ %00100000 mFTM1C3SC_CH3IE: .equ %01000000 mFTM1C3SC_CH3F: .equ %10000000 ;*** FTM1C3V - FTM1 Timer Channel 3 Value Register; 0xFFFF808F *** FTM1C3V: .equ $FFFF808F ;*** FTM1C3V - FTM1 Timer Channel 3 Value Register; 0xFFFF808F *** ;*** FTM1C3VH - FTM1 Timer Channel 3 Value Register High; 0xFFFF808F *** FTM1C3VH: .equ $FFFF808F ;*** FTM1C3VH - FTM1 Timer Channel 3 Value Register High; 0xFFFF808F *** ;*** FTM1C3VL - FTM1 Timer Channel 3 Value Register Low; 0xFFFF8090 *** FTM1C3VL: .equ $FFFF8090 ;*** FTM1C3VL - FTM1 Timer Channel 3 Value Register Low; 0xFFFF8090 *** ;*** FTM1C4SC - FTM1 Timer Channel 4 Status and Control Register; 0xFFFF8091 *** FTM1C4SC: .equ $FFFF8091 ;*** FTM1C4SC - FTM1 Timer Channel 4 Status and Control Register; 0xFFFF8091 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM1C4SC_DMA: .equ 0 ; The DMA bit enables DMA requests on CH4F flag being set rather than issuing a CPU interrupt request FTM1C4SC_ELS4A: .equ 2 ; Edge/Level Select Bit A FTM1C4SC_ELS4B: .equ 3 ; Edge/Level Select Bit B FTM1C4SC_MS4A: .equ 4 ; Mode Select A for FTM1 Channel 4 FTM1C4SC_MS4B: .equ 5 ; Mode Select B for FTM1 Channel 4 FTM1C4SC_CH4IE: .equ 6 ; Channel 4 Interrupt Enable FTM1C4SC_CH4F: .equ 7 ; Channel 4 Flag ; bit position masks mFTM1C4SC_DMA: .equ %00000001 mFTM1C4SC_ELS4A: .equ %00000100 mFTM1C4SC_ELS4B: .equ %00001000 mFTM1C4SC_MS4A: .equ %00010000 mFTM1C4SC_MS4B: .equ %00100000 mFTM1C4SC_CH4IE: .equ %01000000 mFTM1C4SC_CH4F: .equ %10000000 ;*** FTM1C4V - FTM1 Timer Channel 4 Value Register; 0xFFFF8092 *** FTM1C4V: .equ $FFFF8092 ;*** FTM1C4V - FTM1 Timer Channel 4 Value Register; 0xFFFF8092 *** ;*** FTM1C4VH - FTM1 Timer Channel 4 Value Register High; 0xFFFF8092 *** FTM1C4VH: .equ $FFFF8092 ;*** FTM1C4VH - FTM1 Timer Channel 4 Value Register High; 0xFFFF8092 *** ;*** FTM1C4VL - FTM1 Timer Channel 4 Value Register Low; 0xFFFF8093 *** FTM1C4VL: .equ $FFFF8093 ;*** FTM1C4VL - FTM1 Timer Channel 4 Value Register Low; 0xFFFF8093 *** ;*** FTM1C5SC - FTM1 Timer Channel 5 Status and Control Register; 0xFFFF8094 *** FTM1C5SC: .equ $FFFF8094 ;*** FTM1C5SC - FTM1 Timer Channel 5 Status and Control Register; 0xFFFF8094 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM1C5SC_DMA: .equ 0 ; The DMA bit enables DMA requests on CH5F flag being set rather than issuing a CPU interrupt request FTM1C5SC_ELS5A: .equ 2 ; Edge/Level Select Bit A FTM1C5SC_ELS5B: .equ 3 ; Edge/Level Select Bit B FTM1C5SC_MS5A: .equ 4 ; Mode Select A for FTM1 Channel 5 FTM1C5SC_MS5B: .equ 5 ; Mode Select B for FTM1 Channel 5 FTM1C5SC_CH5IE: .equ 6 ; Channel 5 Interrupt Enable FTM1C5SC_CH5F: .equ 7 ; Channel 5 Flag ; bit position masks mFTM1C5SC_DMA: .equ %00000001 mFTM1C5SC_ELS5A: .equ %00000100 mFTM1C5SC_ELS5B: .equ %00001000 mFTM1C5SC_MS5A: .equ %00010000 mFTM1C5SC_MS5B: .equ %00100000 mFTM1C5SC_CH5IE: .equ %01000000 mFTM1C5SC_CH5F: .equ %10000000 ;*** FTM1C5V - FTM1 Timer Channel 5 Value Register; 0xFFFF8095 *** FTM1C5V: .equ $FFFF8095 ;*** FTM1C5V - FTM1 Timer Channel 5 Value Register; 0xFFFF8095 *** ;*** FTM1C5VH - FTM1 Timer Channel 5 Value Register High; 0xFFFF8095 *** FTM1C5VH: .equ $FFFF8095 ;*** FTM1C5VH - FTM1 Timer Channel 5 Value Register High; 0xFFFF8095 *** ;*** FTM1C5VL - FTM1 Timer Channel 5 Value Register Low; 0xFFFF8096 *** FTM1C5VL: .equ $FFFF8096 ;*** FTM1C5VL - FTM1 Timer Channel 5 Value Register Low; 0xFFFF8096 *** ;*** FTM1CNTIN - FTM1 Counter Initial Value Registers; 0xFFFF80A0 *** FTM1CNTIN: .equ $FFFF80A0 ;*** FTM1CNTIN - FTM1 Counter Initial Value Registers; 0xFFFF80A0 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM1CNTIN_BIT0: .equ 0 ; FTM1 Counter Initial Value Bit 0 FTM1CNTIN_BIT1: .equ 1 ; FTM1 Counter Initial Value Bit 1 FTM1CNTIN_BIT2: .equ 2 ; FTM1 Counter Initial Value Bit 2 FTM1CNTIN_BIT3: .equ 3 ; FTM1 Counter Initial Value Bit 3 FTM1CNTIN_BIT4: .equ 4 ; FTM1 Counter Initial Value Bit 4 FTM1CNTIN_BIT5: .equ 5 ; FTM1 Counter Initial Value Bit 5 FTM1CNTIN_BIT6: .equ 6 ; FTM1 Counter Initial Value Bit 6 FTM1CNTIN_BIT7: .equ 7 ; FTM1 Counter Initial Value Bit 7 FTM1CNTIN_BIT8: .equ 8 ; FTM1 Counter Initial Value Bit 8 FTM1CNTIN_BIT9: .equ 9 ; FTM1 Counter Initial Value Bit 9 FTM1CNTIN_BIT10: .equ 10 ; FTM1 Counter Initial Value Bit 10 FTM1CNTIN_BIT11: .equ 11 ; FTM1 Counter Initial Value Bit 11 FTM1CNTIN_BIT12: .equ 12 ; FTM1 Counter Initial Value Bit 12 FTM1CNTIN_BIT13: .equ 13 ; FTM1 Counter Initial Value Bit 13 FTM1CNTIN_BIT14: .equ 14 ; FTM1 Counter Initial Value Bit 14 FTM1CNTIN_BIT15: .equ 15 ; FTM1 Counter Initial Value Bit 15 ; bit position masks mFTM1CNTIN_BIT0: .equ %00000001 mFTM1CNTIN_BIT1: .equ %00000010 mFTM1CNTIN_BIT2: .equ %00000100 mFTM1CNTIN_BIT3: .equ %00001000 mFTM1CNTIN_BIT4: .equ %00010000 mFTM1CNTIN_BIT5: .equ %00100000 mFTM1CNTIN_BIT6: .equ %01000000 mFTM1CNTIN_BIT7: .equ %10000000 mFTM1CNTIN_BIT8: .equ %100000000 mFTM1CNTIN_BIT9: .equ %1000000000 mFTM1CNTIN_BIT10: .equ %10000000000 mFTM1CNTIN_BIT11: .equ %100000000000 mFTM1CNTIN_BIT12: .equ %1000000000000 mFTM1CNTIN_BIT13: .equ %10000000000000 mFTM1CNTIN_BIT14: .equ %100000000000000 mFTM1CNTIN_BIT15: .equ %1000000000000000 ;*** FTM1CNTINH - FTM1 Counter Initial Value Registers High; 0xFFFF80A0 *** FTM1CNTINH: .equ $FFFF80A0 ;*** FTM1CNTINH - FTM1 Counter Initial Value Registers High; 0xFFFF80A0 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM1CNTINH_BIT8: .equ 0 ; FTM1 Counter Initial Value Bit 8 FTM1CNTINH_BIT9: .equ 1 ; FTM1 Counter Initial Value Bit 9 FTM1CNTINH_BIT10: .equ 2 ; FTM1 Counter Initial Value Bit 10 FTM1CNTINH_BIT11: .equ 3 ; FTM1 Counter Initial Value Bit 11 FTM1CNTINH_BIT12: .equ 4 ; FTM1 Counter Initial Value Bit 12 FTM1CNTINH_BIT13: .equ 5 ; FTM1 Counter Initial Value Bit 13 FTM1CNTINH_BIT14: .equ 6 ; FTM1 Counter Initial Value Bit 14 FTM1CNTINH_BIT15: .equ 7 ; FTM1 Counter Initial Value Bit 15 ; bit position masks mFTM1CNTINH_BIT8: .equ %00000001 mFTM1CNTINH_BIT9: .equ %00000010 mFTM1CNTINH_BIT10: .equ %00000100 mFTM1CNTINH_BIT11: .equ %00001000 mFTM1CNTINH_BIT12: .equ %00010000 mFTM1CNTINH_BIT13: .equ %00100000 mFTM1CNTINH_BIT14: .equ %01000000 mFTM1CNTINH_BIT15: .equ %10000000 ;*** FTM1CNTINL - FTM1 Counter Initial Value Registers Low; 0xFFFF80A1 *** FTM1CNTINL: .equ $FFFF80A1 ;*** FTM1CNTINL - FTM1 Counter Initial Value Registers Low; 0xFFFF80A1 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM1CNTINL_BIT0: .equ 0 ; FTM1 Counter Initial Value Bit 0 FTM1CNTINL_BIT1: .equ 1 ; FTM1 Counter Initial Value Bit 1 FTM1CNTINL_BIT2: .equ 2 ; FTM1 Counter Initial Value Bit 2 FTM1CNTINL_BIT3: .equ 3 ; FTM1 Counter Initial Value Bit 3 FTM1CNTINL_BIT4: .equ 4 ; FTM1 Counter Initial Value Bit 4 FTM1CNTINL_BIT5: .equ 5 ; FTM1 Counter Initial Value Bit 5 FTM1CNTINL_BIT6: .equ 6 ; FTM1 Counter Initial Value Bit 6 FTM1CNTINL_BIT7: .equ 7 ; FTM1 Counter Initial Value Bit 7 ; bit position masks mFTM1CNTINL_BIT0: .equ %00000001 mFTM1CNTINL_BIT1: .equ %00000010 mFTM1CNTINL_BIT2: .equ %00000100 mFTM1CNTINL_BIT3: .equ %00001000 mFTM1CNTINL_BIT4: .equ %00010000 mFTM1CNTINL_BIT5: .equ %00100000 mFTM1CNTINL_BIT6: .equ %01000000 mFTM1CNTINL_BIT7: .equ %10000000 ;*** FTM1STATUS - FTM1 Capture and Compare Status Register; 0xFFFF80A2 *** FTM1STATUS: .equ $FFFF80A2 ;*** FTM1STATUS - FTM1 Capture and Compare Status Register; 0xFFFF80A2 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM1STATUS_CH0F: .equ 0 ; Channel 0 Flag FTM1STATUS_CH1F: .equ 1 ; Channel 1 Flag FTM1STATUS_CH2F: .equ 2 ; Channel 2 Flag FTM1STATUS_CH3F: .equ 3 ; Channel 3 Flag FTM1STATUS_CH4F: .equ 4 ; Channel 4 Flag FTM1STATUS_CH5F: .equ 5 ; Channel 5 Flag ; bit position masks mFTM1STATUS_CH0F: .equ %00000001 mFTM1STATUS_CH1F: .equ %00000010 mFTM1STATUS_CH2F: .equ %00000100 mFTM1STATUS_CH3F: .equ %00001000 mFTM1STATUS_CH4F: .equ %00010000 mFTM1STATUS_CH5F: .equ %00100000 ;*** FTM1MODE - FTM1 Features Mode Selection Register; 0xFFFF80A3 *** FTM1MODE: .equ $FFFF80A3 ;*** FTM1MODE - FTM1 Features Mode Selection Register; 0xFFFF80A3 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM1MODE_FTMEN: .equ 0 ; FTM1 Enable FTM1MODE_INIT: .equ 1 ; Initialize the Channels Output FTM1MODE_WPDIS: .equ 2 ; Write Protected Disable FTM1MODE_PWMSYNC: .equ 3 ; PWM synchronization mode FTM1MODE_CAPTTEST: .equ 4 ; Capture test mode enable FTM1MODE_FAULTM0: .equ 5 ; Fault Control Mode Bits, bit 0 FTM1MODE_FAULTM1: .equ 6 ; Fault Control Mode Bits, bit 1 FTM1MODE_FAULTIE: .equ 7 ; Fault Interrupt Enable ; bit position masks mFTM1MODE_FTMEN: .equ %00000001 mFTM1MODE_INIT: .equ %00000010 mFTM1MODE_WPDIS: .equ %00000100 mFTM1MODE_PWMSYNC: .equ %00001000 mFTM1MODE_CAPTTEST: .equ %00010000 mFTM1MODE_FAULTM0: .equ %00100000 mFTM1MODE_FAULTM1: .equ %01000000 mFTM1MODE_FAULTIE: .equ %10000000 ;*** FTM1SYNC - FTM1 Synchronization Register; 0xFFFF80A4 *** FTM1SYNC: .equ $FFFF80A4 ;*** FTM1SYNC - FTM1 Synchronization Register; 0xFFFF80A4 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM1SYNC_CNTMIN: .equ 0 ; FTM1 Counter is Minimum FTM1SYNC_CNTMAX: .equ 1 ; FTM1 Counter is Maximum FTM1SYNC_REINIT: .equ 2 ; Reinitialization of FTM1 Counter by Synchronization FTM1SYNC_SYNCHOM: .equ 3 ; Output Mask by Synchronization FTM1SYNC_TRIG0: .equ 4 ; External Trigger Bit 0 for Synchronization FTM1SYNC_TRIG1: .equ 5 ; External Trigger Bit 1 for Synchronization FTM1SYNC_TRIG2: .equ 6 ; External Trigger Bit 2 for Synchronization FTM1SYNC_SWSYNC: .equ 7 ; Software Trigger for Synchronization ; bit position masks mFTM1SYNC_CNTMIN: .equ %00000001 mFTM1SYNC_CNTMAX: .equ %00000010 mFTM1SYNC_REINIT: .equ %00000100 mFTM1SYNC_SYNCHOM: .equ %00001000 mFTM1SYNC_TRIG0: .equ %00010000 mFTM1SYNC_TRIG1: .equ %00100000 mFTM1SYNC_TRIG2: .equ %01000000 mFTM1SYNC_SWSYNC: .equ %10000000 ;*** FTM1OUTINIT - FTM1 Initial State for Channels Output Register; 0xFFFF80A5 *** FTM1OUTINIT: .equ $FFFF80A5 ;*** FTM1OUTINIT - FTM1 Initial State for Channels Output Register; 0xFFFF80A5 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM1OUTINIT_CH0OI: .equ 0 ; Initial State for Channel 0 Output FTM1OUTINIT_CH1OI: .equ 1 ; Initial State for Channel 1 Output FTM1OUTINIT_CH2OI: .equ 2 ; Initial State for Channel 2 Output FTM1OUTINIT_CH3OI: .equ 3 ; Initial State for Channel 3 Output FTM1OUTINIT_CH4OI: .equ 4 ; Initial State for Channel 4 Output FTM1OUTINIT_CH5OI: .equ 5 ; Initial State for Channel 5 Output ; bit position masks mFTM1OUTINIT_CH0OI: .equ %00000001 mFTM1OUTINIT_CH1OI: .equ %00000010 mFTM1OUTINIT_CH2OI: .equ %00000100 mFTM1OUTINIT_CH3OI: .equ %00001000 mFTM1OUTINIT_CH4OI: .equ %00010000 mFTM1OUTINIT_CH5OI: .equ %00100000 ;*** FTM1OUTMASK - FTM1 Output Mask Register; 0xFFFF80A6 *** FTM1OUTMASK: .equ $FFFF80A6 ;*** FTM1OUTMASK - FTM1 Output Mask Register; 0xFFFF80A6 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM1OUTMASK_CH0OM: .equ 0 ; Channel 0 Output Mask FTM1OUTMASK_CH1OM: .equ 1 ; Channel 1 Output Mask FTM1OUTMASK_CH2OM: .equ 2 ; Channel 2 Output Mask FTM1OUTMASK_CH3OM: .equ 3 ; Channel 3 Output Mask FTM1OUTMASK_CH4OM: .equ 4 ; Channel 4 Output Mask FTM1OUTMASK_CH5OM: .equ 5 ; Channel 5 Output Mask ; bit position masks mFTM1OUTMASK_CH0OM: .equ %00000001 mFTM1OUTMASK_CH1OM: .equ %00000010 mFTM1OUTMASK_CH2OM: .equ %00000100 mFTM1OUTMASK_CH3OM: .equ %00001000 mFTM1OUTMASK_CH4OM: .equ %00010000 mFTM1OUTMASK_CH5OM: .equ %00100000 ;*** FTM1COMBINE0 - FTM1 Function For Linked Channel 0 Register; 0xFFFF80A7 *** FTM1COMBINE0: .equ $FFFF80A7 ;*** FTM1COMBINE0 - FTM1 Function For Linked Channel 0 Register; 0xFFFF80A7 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM1COMBINE0_COMBINE: .equ 0 ; Enables the Combine of the Channels 0 and 1 FTM1COMBINE0_COMP: .equ 1 ; Complementary of Channel 0 FTM1COMBINE0_DTEN: .equ 4 ; Deadtime Enable FTM1COMBINE0_SYNCEN: .equ 5 ; Synchronization Enable FTM1COMBINE0_FAULTEN: .equ 6 ; Fault Control Enable ; bit position masks mFTM1COMBINE0_COMBINE: .equ %00000001 mFTM1COMBINE0_COMP: .equ %00000010 mFTM1COMBINE0_DTEN: .equ %00010000 mFTM1COMBINE0_SYNCEN: .equ %00100000 mFTM1COMBINE0_FAULTEN: .equ %01000000 ;*** FTM1COMBINE1 - FTM1 Function For Linked Channel 1 Register; 0xFFFF80A8 *** FTM1COMBINE1: .equ $FFFF80A8 ;*** FTM1COMBINE1 - FTM1 Function For Linked Channel 1 Register; 0xFFFF80A8 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM1COMBINE1_COMBINE: .equ 0 ; Enables the Combine of the Channels 2 and 3 FTM1COMBINE1_COMP: .equ 1 ; Complementary of Channel 2 FTM1COMBINE1_DTEN: .equ 4 ; Deadtime Enable FTM1COMBINE1_SYNCEN: .equ 5 ; Synchronization Enable FTM1COMBINE1_FAULTEN: .equ 6 ; Fault Control Enable ; bit position masks mFTM1COMBINE1_COMBINE: .equ %00000001 mFTM1COMBINE1_COMP: .equ %00000010 mFTM1COMBINE1_DTEN: .equ %00010000 mFTM1COMBINE1_SYNCEN: .equ %00100000 mFTM1COMBINE1_FAULTEN: .equ %01000000 ;*** FTM1COMBINE2 - FTM1 Function For Linked Channel 2 Register; 0xFFFF80A9 *** FTM1COMBINE2: .equ $FFFF80A9 ;*** FTM1COMBINE2 - FTM1 Function For Linked Channel 2 Register; 0xFFFF80A9 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM1COMBINE2_COMBINE: .equ 0 ; Enables the Combine of the Channels 4 and 5 FTM1COMBINE2_COMP: .equ 1 ; Complementary of Channel 4 FTM1COMBINE2_DTEN: .equ 4 ; Deadtime Enable FTM1COMBINE2_SYNCEN: .equ 5 ; Synchronization Enable FTM1COMBINE2_FAULTEN: .equ 6 ; Fault Control Enable ; bit position masks mFTM1COMBINE2_COMBINE: .equ %00000001 mFTM1COMBINE2_COMP: .equ %00000010 mFTM1COMBINE2_DTEN: .equ %00010000 mFTM1COMBINE2_SYNCEN: .equ %00100000 mFTM1COMBINE2_FAULTEN: .equ %01000000 ;*** FTM1DEADTIME - FTM1 Deadtime Insertion Control Register; 0xFFFF80AB *** FTM1DEADTIME: .equ $FFFF80AB ;*** FTM1DEADTIME - FTM1 Deadtime Insertion Control Register; 0xFFFF80AB *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM1DEADTIME_DTVAL0: .equ 0 ; Deadtime Value Bits, bit 0 FTM1DEADTIME_DTVAL1: .equ 1 ; Deadtime Value Bits, bit 1 FTM1DEADTIME_DTVAL2: .equ 2 ; Deadtime Value Bits, bit 2 FTM1DEADTIME_DTVAL3: .equ 3 ; Deadtime Value Bits, bit 3 FTM1DEADTIME_DTVAL4: .equ 4 ; Deadtime Value Bits, bit 4 FTM1DEADTIME_DTVAL5: .equ 5 ; Deadtime Value Bits, bit 5 FTM1DEADTIME_DTPS0: .equ 6 ; Deadtime Prescaler Value Bits, bit 0 FTM1DEADTIME_DTPS1: .equ 7 ; Deadtime Prescaler Value Bits, bit 1 ; bit position masks mFTM1DEADTIME_DTVAL0: .equ %00000001 mFTM1DEADTIME_DTVAL1: .equ %00000010 mFTM1DEADTIME_DTVAL2: .equ %00000100 mFTM1DEADTIME_DTVAL3: .equ %00001000 mFTM1DEADTIME_DTVAL4: .equ %00010000 mFTM1DEADTIME_DTVAL5: .equ %00100000 mFTM1DEADTIME_DTPS0: .equ %01000000 mFTM1DEADTIME_DTPS1: .equ %10000000 ;*** FTM1EXTTRIG - FTM1 ExternalTrigger Register; 0xFFFF80AC *** FTM1EXTTRIG: .equ $FFFF80AC ;*** FTM1EXTTRIG - FTM1 ExternalTrigger Register; 0xFFFF80AC *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM1EXTTRIG_CH2TRIG: .equ 0 ; Channel 2 trigger enable FTM1EXTTRIG_CH3TRIG: .equ 1 ; Channel 3 trigger enable FTM1EXTTRIG_CH4TRIG: .equ 2 ; Channel 4 trigger enable FTM1EXTTRIG_CH5TRIG: .equ 3 ; Channel 5 trigger enable FTM1EXTTRIG_CH0TRIG: .equ 4 ; Channel 0 trigger enable FTM1EXTTRIG_CH1TRIG: .equ 5 ; Channel 1 trigger enable FTM1EXTTRIG_INITTRIGEN: .equ 6 ; Enables the Generation of a Trigger Signal FTM1EXTTRIG_TRIGF: .equ 7 ; Channel trigger flag ; bit position masks mFTM1EXTTRIG_CH2TRIG: .equ %00000001 mFTM1EXTTRIG_CH3TRIG: .equ %00000010 mFTM1EXTTRIG_CH4TRIG: .equ %00000100 mFTM1EXTTRIG_CH5TRIG: .equ %00001000 mFTM1EXTTRIG_CH0TRIG: .equ %00010000 mFTM1EXTTRIG_CH1TRIG: .equ %00100000 mFTM1EXTTRIG_INITTRIGEN: .equ %01000000 mFTM1EXTTRIG_TRIGF: .equ %10000000 ;*** FTM1POL - FTM1 Channels Polarity Register; 0xFFFF80AD *** FTM1POL: .equ $FFFF80AD ;*** FTM1POL - FTM1 Channels Polarity Register; 0xFFFF80AD *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM1POL_POL0: .equ 0 ; Channel 0 Polarity FTM1POL_POL1: .equ 1 ; Channel 1 Polarity FTM1POL_POL2: .equ 2 ; Channel 2 Polarity FTM1POL_POL3: .equ 3 ; Channel 3 Polarity FTM1POL_POL4: .equ 4 ; Channel 4 Polarity FTM1POL_POL5: .equ 5 ; Channel 5 Polarity ; bit position masks mFTM1POL_POL0: .equ %00000001 mFTM1POL_POL1: .equ %00000010 mFTM1POL_POL2: .equ %00000100 mFTM1POL_POL3: .equ %00001000 mFTM1POL_POL4: .equ %00010000 mFTM1POL_POL5: .equ %00100000 ;*** FTM1FMS - FTM1 Fault Mode Status Register; 0xFFFF80AE *** FTM1FMS: .equ $FFFF80AE ;*** FTM1FMS - FTM1 Fault Mode Status Register; 0xFFFF80AE *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM1FMS_FAULTF0: .equ 0 ; Fault detection flag 0 FTM1FMS_FAULTF1: .equ 1 ; Fault detection flag 1 FTM1FMS_FAULTF2: .equ 2 ; Fault detection flag 2 FTM1FMS_FAULTF3: .equ 3 ; Fault detection flag 3 FTM1FMS_FAULTIN: .equ 5 ; Fault Input FTM1FMS_WPEN: .equ 6 ; Write Protected Enable FTM1FMS_FAULTF: .equ 7 ; Fault Detection Flag ; bit position masks mFTM1FMS_FAULTF0: .equ %00000001 mFTM1FMS_FAULTF1: .equ %00000010 mFTM1FMS_FAULTF2: .equ %00000100 mFTM1FMS_FAULTF3: .equ %00001000 mFTM1FMS_FAULTIN: .equ %00100000 mFTM1FMS_WPEN: .equ %01000000 mFTM1FMS_FAULTF: .equ %10000000 ;*** FTM1FILTER0 - FTM1 Input Capture Filter Control Register 0; 0xFFFF80AF *** FTM1FILTER0: .equ $FFFF80AF ;*** FTM1FILTER0 - FTM1 Input Capture Filter Control Register 0; 0xFFFF80AF *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM1FILTER0_CH0FVAL0: .equ 0 ; Channel 0 Input Filter Bits, bit 0 FTM1FILTER0_CH0FVAL1: .equ 1 ; Channel 0 Input Filter Bits, bit 1 FTM1FILTER0_CH0FVAL2: .equ 2 ; Channel 0 Input Filter Bits, bit 2 FTM1FILTER0_CH0FVAL3: .equ 3 ; Channel 0 Input Filter Bits, bit 3 FTM1FILTER0_CH1FVAL0: .equ 4 ; Channel 1 Input Filter Bits, bit 0 FTM1FILTER0_CH1FVAL1: .equ 5 ; Channel 1 Input Filter Bits, bit 1 FTM1FILTER0_CH1FVAL2: .equ 6 ; Channel 1 Input Filter Bits, bit 2 FTM1FILTER0_CH1FVAL3: .equ 7 ; Channel 1 Input Filter Bits, bit 3 ; bit position masks mFTM1FILTER0_CH0FVAL0: .equ %00000001 mFTM1FILTER0_CH0FVAL1: .equ %00000010 mFTM1FILTER0_CH0FVAL2: .equ %00000100 mFTM1FILTER0_CH0FVAL3: .equ %00001000 mFTM1FILTER0_CH1FVAL0: .equ %00010000 mFTM1FILTER0_CH1FVAL1: .equ %00100000 mFTM1FILTER0_CH1FVAL2: .equ %01000000 mFTM1FILTER0_CH1FVAL3: .equ %10000000 ;*** FTM1FILTER1 - FTM1 Input Capture Filter Control Register 1; 0xFFFF80B0 *** FTM1FILTER1: .equ $FFFF80B0 ;*** FTM1FILTER1 - FTM1 Input Capture Filter Control Register 1; 0xFFFF80B0 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM1FILTER1_CH2FVAL0: .equ 0 ; Channel 2 Input Filter Bits, bit 0 FTM1FILTER1_CH2FVAL1: .equ 1 ; Channel 2 Input Filter Bits, bit 1 FTM1FILTER1_CH2FVAL2: .equ 2 ; Channel 2 Input Filter Bits, bit 2 FTM1FILTER1_CH2FVAL3: .equ 3 ; Channel 2 Input Filter Bits, bit 3 FTM1FILTER1_CH3FVAL0: .equ 4 ; Channel 3 Input Filter Bits, bit 0 FTM1FILTER1_CH3FVAL1: .equ 5 ; Channel 3 Input Filter Bits, bit 1 FTM1FILTER1_CH3FVAL2: .equ 6 ; Channel 3 Input Filter Bits, bit 2 FTM1FILTER1_CH3FVAL3: .equ 7 ; Channel 3 Input Filter Bits, bit 3 ; bit position masks mFTM1FILTER1_CH2FVAL0: .equ %00000001 mFTM1FILTER1_CH2FVAL1: .equ %00000010 mFTM1FILTER1_CH2FVAL2: .equ %00000100 mFTM1FILTER1_CH2FVAL3: .equ %00001000 mFTM1FILTER1_CH3FVAL0: .equ %00010000 mFTM1FILTER1_CH3FVAL1: .equ %00100000 mFTM1FILTER1_CH3FVAL2: .equ %01000000 mFTM1FILTER1_CH3FVAL3: .equ %10000000 ;*** FTM1FLTFILTER - FTM1 Fault Input Filter Control Register; 0xFFFF80B1 *** FTM1FLTFILTER: .equ $FFFF80B1 ;*** FTM1FLTFILTER - FTM1 Fault Input Filter Control Register; 0xFFFF80B1 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM1FLTFILTER_FFVAL0: .equ 0 ; Fault Input Filter Bits, bit 0 FTM1FLTFILTER_FFVAL1: .equ 1 ; Fault Input Filter Bits, bit 1 FTM1FLTFILTER_FFVAL2: .equ 2 ; Fault Input Filter Bits, bit 2 FTM1FLTFILTER_FFVAL3: .equ 3 ; Fault Input Filter Bits, bit 3 ; bit position masks mFTM1FLTFILTER_FFVAL0: .equ %00000001 mFTM1FLTFILTER_FFVAL1: .equ %00000010 mFTM1FLTFILTER_FFVAL2: .equ %00000100 mFTM1FLTFILTER_FFVAL3: .equ %00001000 ;*** FTM1FLTCTRL - FTM1 Fault Control Register; 0xFFFF80B2 *** FTM1FLTCTRL: .equ $FFFF80B2 ;*** FTM1FLTCTRL - FTM1 Fault Control Register; 0xFFFF80B2 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM1FLTCTRL_FAULT0EN: .equ 0 ; Fault input 0 enable FTM1FLTCTRL_FAULT1EN: .equ 1 ; Fault input 1 enable FTM1FLTCTRL_FFLTR0EN: .equ 4 ; Fault input 0 filter enable ; bit position masks mFTM1FLTCTRL_FAULT0EN: .equ %00000001 mFTM1FLTCTRL_FAULT1EN: .equ %00000010 mFTM1FLTCTRL_FFLTR0EN: .equ %00010000 ;*** FTM2SC - FTM2 Status and Control Register; 0xFFFF80C0 *** FTM2SC: .equ $FFFF80C0 ;*** FTM2SC - FTM2 Status and Control Register; 0xFFFF80C0 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM2SC_PS0: .equ 0 ; Prescale Divisor Select Bit 0 FTM2SC_PS1: .equ 1 ; Prescale Divisor Select Bit 1 FTM2SC_PS2: .equ 2 ; Prescale Divisor Select Bit 2 FTM2SC_CLKSA: .equ 3 ; Clock Source Select A FTM2SC_CLKSB: .equ 4 ; Clock Source Select B FTM2SC_CPWMS: .equ 5 ; Center-Aligned PWM Select FTM2SC_TOIE: .equ 6 ; Timer Overflow Interrupt Enable FTM2SC_TOF: .equ 7 ; Timer Overflow Flag ; bit position masks mFTM2SC_PS0: .equ %00000001 mFTM2SC_PS1: .equ %00000010 mFTM2SC_PS2: .equ %00000100 mFTM2SC_CLKSA: .equ %00001000 mFTM2SC_CLKSB: .equ %00010000 mFTM2SC_CPWMS: .equ %00100000 mFTM2SC_TOIE: .equ %01000000 mFTM2SC_TOF: .equ %10000000 ;*** FTM2CNT - FTM2 Timer Counter Register; 0xFFFF80C1 *** FTM2CNT: .equ $FFFF80C1 ;*** FTM2CNT - FTM2 Timer Counter Register; 0xFFFF80C1 *** ;*** FTM2CNTH - FTM2 Timer Counter Register High; 0xFFFF80C1 *** FTM2CNTH: .equ $FFFF80C1 ;*** FTM2CNTH - FTM2 Timer Counter Register High; 0xFFFF80C1 *** ;*** FTM2CNTL - FTM2 Timer Counter Register Low; 0xFFFF80C2 *** FTM2CNTL: .equ $FFFF80C2 ;*** FTM2CNTL - FTM2 Timer Counter Register Low; 0xFFFF80C2 *** ;*** FTM2MOD - FTM2 Timer Counter Modulo Register; 0xFFFF80C3 *** FTM2MOD: .equ $FFFF80C3 ;*** FTM2MOD - FTM2 Timer Counter Modulo Register; 0xFFFF80C3 *** ;*** FTM2MODH - FTM2 Timer Counter Modulo Register High; 0xFFFF80C3 *** FTM2MODH: .equ $FFFF80C3 ;*** FTM2MODH - FTM2 Timer Counter Modulo Register High; 0xFFFF80C3 *** ;*** FTM2MODL - FTM2 Timer Counter Modulo Register Low; 0xFFFF80C4 *** FTM2MODL: .equ $FFFF80C4 ;*** FTM2MODL - FTM2 Timer Counter Modulo Register Low; 0xFFFF80C4 *** ;*** FTM2C0SC - FTM2 Timer Channel 0 Status and Control Register; 0xFFFF80C5 *** FTM2C0SC: .equ $FFFF80C5 ;*** FTM2C0SC - FTM2 Timer Channel 0 Status and Control Register; 0xFFFF80C5 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM2C0SC_DMA: .equ 0 ; The DMA bit enables DMA requests on CH0F flag being set rather than issuing a CPU interrupt request FTM2C0SC_ELS0A: .equ 2 ; Edge/Level Select Bit A FTM2C0SC_ELS0B: .equ 3 ; Edge/Level Select Bit B FTM2C0SC_MS0A: .equ 4 ; Mode Select A for FTM2 Channel 0 FTM2C0SC_MS0B: .equ 5 ; Mode Select B for FTM2 Channel 0 FTM2C0SC_CH0IE: .equ 6 ; Channel 0 Interrupt Enable FTM2C0SC_CH0F: .equ 7 ; Channel 0 Flag ; bit position masks mFTM2C0SC_DMA: .equ %00000001 mFTM2C0SC_ELS0A: .equ %00000100 mFTM2C0SC_ELS0B: .equ %00001000 mFTM2C0SC_MS0A: .equ %00010000 mFTM2C0SC_MS0B: .equ %00100000 mFTM2C0SC_CH0IE: .equ %01000000 mFTM2C0SC_CH0F: .equ %10000000 ;*** FTM2C0V - FTM2 Timer Channel 0 Value Register; 0xFFFF80C6 *** FTM2C0V: .equ $FFFF80C6 ;*** FTM2C0V - FTM2 Timer Channel 0 Value Register; 0xFFFF80C6 *** ;*** FTM2C0VH - FTM2 Timer Channel 0 Value Register High; 0xFFFF80C6 *** FTM2C0VH: .equ $FFFF80C6 ;*** FTM2C0VH - FTM2 Timer Channel 0 Value Register High; 0xFFFF80C6 *** ;*** FTM2C0VL - FTM2 Timer Channel 0 Value Register Low; 0xFFFF80C7 *** FTM2C0VL: .equ $FFFF80C7 ;*** FTM2C0VL - FTM2 Timer Channel 0 Value Register Low; 0xFFFF80C7 *** ;*** FTM2C1SC - FTM2 Timer Channel 1 Status and Control Register; 0xFFFF80C8 *** FTM2C1SC: .equ $FFFF80C8 ;*** FTM2C1SC - FTM2 Timer Channel 1 Status and Control Register; 0xFFFF80C8 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM2C1SC_DMA: .equ 0 ; The DMA bit enables DMA requests on CH1F flag being set rather than issuing a CPU interrupt request FTM2C1SC_ELS1A: .equ 2 ; Edge/Level Select Bit A FTM2C1SC_ELS1B: .equ 3 ; Edge/Level Select Bit B FTM2C1SC_MS1A: .equ 4 ; Mode Select A for FTM2 Channel 1 FTM2C1SC_MS1B: .equ 5 ; Mode Select B for FTM2 Channel 1 FTM2C1SC_CH1IE: .equ 6 ; Channel 1 Interrupt Enable FTM2C1SC_CH1F: .equ 7 ; Channel 1 Flag ; bit position masks mFTM2C1SC_DMA: .equ %00000001 mFTM2C1SC_ELS1A: .equ %00000100 mFTM2C1SC_ELS1B: .equ %00001000 mFTM2C1SC_MS1A: .equ %00010000 mFTM2C1SC_MS1B: .equ %00100000 mFTM2C1SC_CH1IE: .equ %01000000 mFTM2C1SC_CH1F: .equ %10000000 ;*** FTM2C1V - FTM2 Timer Channel 1 Value Register; 0xFFFF80C9 *** FTM2C1V: .equ $FFFF80C9 ;*** FTM2C1V - FTM2 Timer Channel 1 Value Register; 0xFFFF80C9 *** ;*** FTM2C1VH - FTM2 Timer Channel 1 Value Register High; 0xFFFF80C9 *** FTM2C1VH: .equ $FFFF80C9 ;*** FTM2C1VH - FTM2 Timer Channel 1 Value Register High; 0xFFFF80C9 *** ;*** FTM2C1VL - FTM2 Timer Channel 1 Value Register Low; 0xFFFF80CA *** FTM2C1VL: .equ $FFFF80CA ;*** FTM2C1VL - FTM2 Timer Channel 1 Value Register Low; 0xFFFF80CA *** ;*** FTM2C2SC - FTM2 Timer Channel 2 Status and Control Register; 0xFFFF80CB *** FTM2C2SC: .equ $FFFF80CB ;*** FTM2C2SC - FTM2 Timer Channel 2 Status and Control Register; 0xFFFF80CB *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM2C2SC_DMA: .equ 0 ; The DMA bit enables DMA requests on CH2F flag being set rather than issuing a CPU interrupt request FTM2C2SC_ELS2A: .equ 2 ; Edge/Level Select Bit A FTM2C2SC_ELS2B: .equ 3 ; Edge/Level Select Bit B FTM2C2SC_MS2A: .equ 4 ; Mode Select A for FTM2 Channel 2 FTM2C2SC_MS2B: .equ 5 ; Mode Select B for FTM2 Channel 2 FTM2C2SC_CH2IE: .equ 6 ; Channel 2 Interrupt Enable FTM2C2SC_CH2F: .equ 7 ; Channel 2 Flag ; bit position masks mFTM2C2SC_DMA: .equ %00000001 mFTM2C2SC_ELS2A: .equ %00000100 mFTM2C2SC_ELS2B: .equ %00001000 mFTM2C2SC_MS2A: .equ %00010000 mFTM2C2SC_MS2B: .equ %00100000 mFTM2C2SC_CH2IE: .equ %01000000 mFTM2C2SC_CH2F: .equ %10000000 ;*** FTM2C2V - FTM2 Timer Channel 2 Value Register; 0xFFFF80CC *** FTM2C2V: .equ $FFFF80CC ;*** FTM2C2V - FTM2 Timer Channel 2 Value Register; 0xFFFF80CC *** ;*** FTM2C2VH - FTM2 Timer Channel 2 Value Register High; 0xFFFF80CC *** FTM2C2VH: .equ $FFFF80CC ;*** FTM2C2VH - FTM2 Timer Channel 2 Value Register High; 0xFFFF80CC *** ;*** FTM2C2VL - FTM2 Timer Channel 2 Value Register Low; 0xFFFF80CD *** FTM2C2VL: .equ $FFFF80CD ;*** FTM2C2VL - FTM2 Timer Channel 2 Value Register Low; 0xFFFF80CD *** ;*** FTM2C3SC - FTM2 Timer Channel 3 Status and Control Register; 0xFFFF80CE *** FTM2C3SC: .equ $FFFF80CE ;*** FTM2C3SC - FTM2 Timer Channel 3 Status and Control Register; 0xFFFF80CE *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM2C3SC_DMA: .equ 0 ; The DMA bit enables DMA requests on CH3F flag being set rather than issuing a CPU interrupt request FTM2C3SC_ELS3A: .equ 2 ; Edge/Level Select Bit A FTM2C3SC_ELS3B: .equ 3 ; Edge/Level Select Bit B FTM2C3SC_MS3A: .equ 4 ; Mode Select A for FTM2 Channel 3 FTM2C3SC_MS3B: .equ 5 ; Mode Select B for FTM2 Channel 3 FTM2C3SC_CH3IE: .equ 6 ; Channel 3 Interrupt Enable FTM2C3SC_CH3F: .equ 7 ; Channel 3 Flag ; bit position masks mFTM2C3SC_DMA: .equ %00000001 mFTM2C3SC_ELS3A: .equ %00000100 mFTM2C3SC_ELS3B: .equ %00001000 mFTM2C3SC_MS3A: .equ %00010000 mFTM2C3SC_MS3B: .equ %00100000 mFTM2C3SC_CH3IE: .equ %01000000 mFTM2C3SC_CH3F: .equ %10000000 ;*** FTM2C3V - FTM2 Timer Channel 3 Value Register; 0xFFFF80CF *** FTM2C3V: .equ $FFFF80CF ;*** FTM2C3V - FTM2 Timer Channel 3 Value Register; 0xFFFF80CF *** ;*** FTM2C3VH - FTM2 Timer Channel 3 Value Register High; 0xFFFF80CF *** FTM2C3VH: .equ $FFFF80CF ;*** FTM2C3VH - FTM2 Timer Channel 3 Value Register High; 0xFFFF80CF *** ;*** FTM2C3VL - FTM2 Timer Channel 3 Value Register Low; 0xFFFF80D0 *** FTM2C3VL: .equ $FFFF80D0 ;*** FTM2C3VL - FTM2 Timer Channel 3 Value Register Low; 0xFFFF80D0 *** ;*** FTM2C4SC - FTM2 Timer Channel 4 Status and Control Register; 0xFFFF80D1 *** FTM2C4SC: .equ $FFFF80D1 ;*** FTM2C4SC - FTM2 Timer Channel 4 Status and Control Register; 0xFFFF80D1 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM2C4SC_DMA: .equ 0 ; The DMA bit enables DMA requests on CH4F flag being set rather than issuing a CPU interrupt request FTM2C4SC_ELS4A: .equ 2 ; Edge/Level Select Bit A FTM2C4SC_ELS4B: .equ 3 ; Edge/Level Select Bit B FTM2C4SC_MS4A: .equ 4 ; Mode Select A for FTM2 Channel 4 FTM2C4SC_MS4B: .equ 5 ; Mode Select B for FTM2 Channel 4 FTM2C4SC_CH4IE: .equ 6 ; Channel 4 Interrupt Enable FTM2C4SC_CH4F: .equ 7 ; Channel 4 Flag ; bit position masks mFTM2C4SC_DMA: .equ %00000001 mFTM2C4SC_ELS4A: .equ %00000100 mFTM2C4SC_ELS4B: .equ %00001000 mFTM2C4SC_MS4A: .equ %00010000 mFTM2C4SC_MS4B: .equ %00100000 mFTM2C4SC_CH4IE: .equ %01000000 mFTM2C4SC_CH4F: .equ %10000000 ;*** FTM2C4V - FTM2 Timer Channel 4 Value Register; 0xFFFF80D2 *** FTM2C4V: .equ $FFFF80D2 ;*** FTM2C4V - FTM2 Timer Channel 4 Value Register; 0xFFFF80D2 *** ;*** FTM2C4VH - FTM2 Timer Channel 4 Value Register High; 0xFFFF80D2 *** FTM2C4VH: .equ $FFFF80D2 ;*** FTM2C4VH - FTM2 Timer Channel 4 Value Register High; 0xFFFF80D2 *** ;*** FTM2C4VL - FTM2 Timer Channel 4 Value Register Low; 0xFFFF80D3 *** FTM2C4VL: .equ $FFFF80D3 ;*** FTM2C4VL - FTM2 Timer Channel 4 Value Register Low; 0xFFFF80D3 *** ;*** FTM2C5SC - FTM2 Timer Channel 5 Status and Control Register; 0xFFFF80D4 *** FTM2C5SC: .equ $FFFF80D4 ;*** FTM2C5SC - FTM2 Timer Channel 5 Status and Control Register; 0xFFFF80D4 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM2C5SC_DMA: .equ 0 ; The DMA bit enables DMA requests on CH5F flag being set rather than issuing a CPU interrupt request FTM2C5SC_ELS5A: .equ 2 ; Edge/Level Select Bit A FTM2C5SC_ELS5B: .equ 3 ; Edge/Level Select Bit B FTM2C5SC_MS5A: .equ 4 ; Mode Select A for FTM2 Channel 5 FTM2C5SC_MS5B: .equ 5 ; Mode Select B for FTM2 Channel 5 FTM2C5SC_CH5IE: .equ 6 ; Channel 5 Interrupt Enable FTM2C5SC_CH5F: .equ 7 ; Channel 5 Flag ; bit position masks mFTM2C5SC_DMA: .equ %00000001 mFTM2C5SC_ELS5A: .equ %00000100 mFTM2C5SC_ELS5B: .equ %00001000 mFTM2C5SC_MS5A: .equ %00010000 mFTM2C5SC_MS5B: .equ %00100000 mFTM2C5SC_CH5IE: .equ %01000000 mFTM2C5SC_CH5F: .equ %10000000 ;*** FTM2C5V - FTM2 Timer Channel 5 Value Register; 0xFFFF80D5 *** FTM2C5V: .equ $FFFF80D5 ;*** FTM2C5V - FTM2 Timer Channel 5 Value Register; 0xFFFF80D5 *** ;*** FTM2C5VH - FTM2 Timer Channel 5 Value Register High; 0xFFFF80D5 *** FTM2C5VH: .equ $FFFF80D5 ;*** FTM2C5VH - FTM2 Timer Channel 5 Value Register High; 0xFFFF80D5 *** ;*** FTM2C5VL - FTM2 Timer Channel 5 Value Register Low; 0xFFFF80D6 *** FTM2C5VL: .equ $FFFF80D6 ;*** FTM2C5VL - FTM2 Timer Channel 5 Value Register Low; 0xFFFF80D6 *** ;*** FTM2CNTIN - FTM2 Counter Initial Value Registers; 0xFFFF80E0 *** FTM2CNTIN: .equ $FFFF80E0 ;*** FTM2CNTIN - FTM2 Counter Initial Value Registers; 0xFFFF80E0 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM2CNTIN_BIT0: .equ 0 ; FTM2 Counter Initial Value Bit 0 FTM2CNTIN_BIT1: .equ 1 ; FTM2 Counter Initial Value Bit 1 FTM2CNTIN_BIT2: .equ 2 ; FTM2 Counter Initial Value Bit 2 FTM2CNTIN_BIT3: .equ 3 ; FTM2 Counter Initial Value Bit 3 FTM2CNTIN_BIT4: .equ 4 ; FTM2 Counter Initial Value Bit 4 FTM2CNTIN_BIT5: .equ 5 ; FTM2 Counter Initial Value Bit 5 FTM2CNTIN_BIT6: .equ 6 ; FTM2 Counter Initial Value Bit 6 FTM2CNTIN_BIT7: .equ 7 ; FTM2 Counter Initial Value Bit 7 FTM2CNTIN_BIT8: .equ 8 ; FTM2 Counter Initial Value Bit 8 FTM2CNTIN_BIT9: .equ 9 ; FTM2 Counter Initial Value Bit 9 FTM2CNTIN_BIT10: .equ 10 ; FTM2 Counter Initial Value Bit 10 FTM2CNTIN_BIT11: .equ 11 ; FTM2 Counter Initial Value Bit 11 FTM2CNTIN_BIT12: .equ 12 ; FTM2 Counter Initial Value Bit 12 FTM2CNTIN_BIT13: .equ 13 ; FTM2 Counter Initial Value Bit 13 FTM2CNTIN_BIT14: .equ 14 ; FTM2 Counter Initial Value Bit 14 FTM2CNTIN_BIT15: .equ 15 ; FTM2 Counter Initial Value Bit 15 ; bit position masks mFTM2CNTIN_BIT0: .equ %00000001 mFTM2CNTIN_BIT1: .equ %00000010 mFTM2CNTIN_BIT2: .equ %00000100 mFTM2CNTIN_BIT3: .equ %00001000 mFTM2CNTIN_BIT4: .equ %00010000 mFTM2CNTIN_BIT5: .equ %00100000 mFTM2CNTIN_BIT6: .equ %01000000 mFTM2CNTIN_BIT7: .equ %10000000 mFTM2CNTIN_BIT8: .equ %100000000 mFTM2CNTIN_BIT9: .equ %1000000000 mFTM2CNTIN_BIT10: .equ %10000000000 mFTM2CNTIN_BIT11: .equ %100000000000 mFTM2CNTIN_BIT12: .equ %1000000000000 mFTM2CNTIN_BIT13: .equ %10000000000000 mFTM2CNTIN_BIT14: .equ %100000000000000 mFTM2CNTIN_BIT15: .equ %1000000000000000 ;*** FTM2CNTINH - FTM2 Counter Initial Value Registers High; 0xFFFF80E0 *** FTM2CNTINH: .equ $FFFF80E0 ;*** FTM2CNTINH - FTM2 Counter Initial Value Registers High; 0xFFFF80E0 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM2CNTINH_BIT8: .equ 0 ; FTM2 Counter Initial Value Bit 8 FTM2CNTINH_BIT9: .equ 1 ; FTM2 Counter Initial Value Bit 9 FTM2CNTINH_BIT10: .equ 2 ; FTM2 Counter Initial Value Bit 10 FTM2CNTINH_BIT11: .equ 3 ; FTM2 Counter Initial Value Bit 11 FTM2CNTINH_BIT12: .equ 4 ; FTM2 Counter Initial Value Bit 12 FTM2CNTINH_BIT13: .equ 5 ; FTM2 Counter Initial Value Bit 13 FTM2CNTINH_BIT14: .equ 6 ; FTM2 Counter Initial Value Bit 14 FTM2CNTINH_BIT15: .equ 7 ; FTM2 Counter Initial Value Bit 15 ; bit position masks mFTM2CNTINH_BIT8: .equ %00000001 mFTM2CNTINH_BIT9: .equ %00000010 mFTM2CNTINH_BIT10: .equ %00000100 mFTM2CNTINH_BIT11: .equ %00001000 mFTM2CNTINH_BIT12: .equ %00010000 mFTM2CNTINH_BIT13: .equ %00100000 mFTM2CNTINH_BIT14: .equ %01000000 mFTM2CNTINH_BIT15: .equ %10000000 ;*** FTM2CNTINL - FTM2 Counter Initial Value Registers Low; 0xFFFF80E1 *** FTM2CNTINL: .equ $FFFF80E1 ;*** FTM2CNTINL - FTM2 Counter Initial Value Registers Low; 0xFFFF80E1 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM2CNTINL_BIT0: .equ 0 ; FTM2 Counter Initial Value Bit 0 FTM2CNTINL_BIT1: .equ 1 ; FTM2 Counter Initial Value Bit 1 FTM2CNTINL_BIT2: .equ 2 ; FTM2 Counter Initial Value Bit 2 FTM2CNTINL_BIT3: .equ 3 ; FTM2 Counter Initial Value Bit 3 FTM2CNTINL_BIT4: .equ 4 ; FTM2 Counter Initial Value Bit 4 FTM2CNTINL_BIT5: .equ 5 ; FTM2 Counter Initial Value Bit 5 FTM2CNTINL_BIT6: .equ 6 ; FTM2 Counter Initial Value Bit 6 FTM2CNTINL_BIT7: .equ 7 ; FTM2 Counter Initial Value Bit 7 ; bit position masks mFTM2CNTINL_BIT0: .equ %00000001 mFTM2CNTINL_BIT1: .equ %00000010 mFTM2CNTINL_BIT2: .equ %00000100 mFTM2CNTINL_BIT3: .equ %00001000 mFTM2CNTINL_BIT4: .equ %00010000 mFTM2CNTINL_BIT5: .equ %00100000 mFTM2CNTINL_BIT6: .equ %01000000 mFTM2CNTINL_BIT7: .equ %10000000 ;*** FTM2STATUS - FTM2 Capture and Compare Status Register; 0xFFFF80E2 *** FTM2STATUS: .equ $FFFF80E2 ;*** FTM2STATUS - FTM2 Capture and Compare Status Register; 0xFFFF80E2 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM2STATUS_CH0F: .equ 0 ; Channel 0 Flag FTM2STATUS_CH1F: .equ 1 ; Channel 1 Flag FTM2STATUS_CH2F: .equ 2 ; Channel 2 Flag FTM2STATUS_CH3F: .equ 3 ; Channel 3 Flag FTM2STATUS_CH4F: .equ 4 ; Channel 4 Flag FTM2STATUS_CH5F: .equ 5 ; Channel 5 Flag ; bit position masks mFTM2STATUS_CH0F: .equ %00000001 mFTM2STATUS_CH1F: .equ %00000010 mFTM2STATUS_CH2F: .equ %00000100 mFTM2STATUS_CH3F: .equ %00001000 mFTM2STATUS_CH4F: .equ %00010000 mFTM2STATUS_CH5F: .equ %00100000 ;*** FTM2MODE - FTM2 Features Mode Selection Register; 0xFFFF80E3 *** FTM2MODE: .equ $FFFF80E3 ;*** FTM2MODE - FTM2 Features Mode Selection Register; 0xFFFF80E3 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM2MODE_FTMEN: .equ 0 ; FTM2 Enable FTM2MODE_INIT: .equ 1 ; Initialize the Channels Output FTM2MODE_WPDIS: .equ 2 ; Write Protected Disable FTM2MODE_PWMSYNC: .equ 3 ; PWM synchronization mode FTM2MODE_CAPTTEST: .equ 4 ; Capture test mode enable FTM2MODE_FAULTM0: .equ 5 ; Fault Control Mode Bits, bit 0 FTM2MODE_FAULTM1: .equ 6 ; Fault Control Mode Bits, bit 1 FTM2MODE_FAULTIE: .equ 7 ; Fault Interrupt Enable ; bit position masks mFTM2MODE_FTMEN: .equ %00000001 mFTM2MODE_INIT: .equ %00000010 mFTM2MODE_WPDIS: .equ %00000100 mFTM2MODE_PWMSYNC: .equ %00001000 mFTM2MODE_CAPTTEST: .equ %00010000 mFTM2MODE_FAULTM0: .equ %00100000 mFTM2MODE_FAULTM1: .equ %01000000 mFTM2MODE_FAULTIE: .equ %10000000 ;*** FTM2SYNC - FTM2 Synchronization Register; 0xFFFF80E4 *** FTM2SYNC: .equ $FFFF80E4 ;*** FTM2SYNC - FTM2 Synchronization Register; 0xFFFF80E4 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM2SYNC_CNTMIN: .equ 0 ; FTM2 Counter is Minimum FTM2SYNC_CNTMAX: .equ 1 ; FTM2 Counter is Maximum FTM2SYNC_REINIT: .equ 2 ; Reinitialization of FTM2 Counter by Synchronization FTM2SYNC_SYNCHOM: .equ 3 ; Output Mask by Synchronization FTM2SYNC_TRIG0: .equ 4 ; External Trigger Bit 0 for Synchronization FTM2SYNC_TRIG1: .equ 5 ; External Trigger Bit 1 for Synchronization FTM2SYNC_TRIG2: .equ 6 ; External Trigger Bit 2 for Synchronization FTM2SYNC_SWSYNC: .equ 7 ; Software Trigger for Synchronization ; bit position masks mFTM2SYNC_CNTMIN: .equ %00000001 mFTM2SYNC_CNTMAX: .equ %00000010 mFTM2SYNC_REINIT: .equ %00000100 mFTM2SYNC_SYNCHOM: .equ %00001000 mFTM2SYNC_TRIG0: .equ %00010000 mFTM2SYNC_TRIG1: .equ %00100000 mFTM2SYNC_TRIG2: .equ %01000000 mFTM2SYNC_SWSYNC: .equ %10000000 ;*** FTM2OUTINIT - FTM2 Initial State for Channels Output Register; 0xFFFF80E5 *** FTM2OUTINIT: .equ $FFFF80E5 ;*** FTM2OUTINIT - FTM2 Initial State for Channels Output Register; 0xFFFF80E5 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM2OUTINIT_CH0OI: .equ 0 ; Initial State for Channel 0 Output FTM2OUTINIT_CH1OI: .equ 1 ; Initial State for Channel 1 Output FTM2OUTINIT_CH2OI: .equ 2 ; Initial State for Channel 2 Output FTM2OUTINIT_CH3OI: .equ 3 ; Initial State for Channel 3 Output FTM2OUTINIT_CH4OI: .equ 4 ; Initial State for Channel 4 Output FTM2OUTINIT_CH5OI: .equ 5 ; Initial State for Channel 5 Output ; bit position masks mFTM2OUTINIT_CH0OI: .equ %00000001 mFTM2OUTINIT_CH1OI: .equ %00000010 mFTM2OUTINIT_CH2OI: .equ %00000100 mFTM2OUTINIT_CH3OI: .equ %00001000 mFTM2OUTINIT_CH4OI: .equ %00010000 mFTM2OUTINIT_CH5OI: .equ %00100000 ;*** FTM2OUTMASK - FTM2 Output Mask Register; 0xFFFF80E6 *** FTM2OUTMASK: .equ $FFFF80E6 ;*** FTM2OUTMASK - FTM2 Output Mask Register; 0xFFFF80E6 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM2OUTMASK_CH0OM: .equ 0 ; Channel 0 Output Mask FTM2OUTMASK_CH1OM: .equ 1 ; Channel 1 Output Mask FTM2OUTMASK_CH2OM: .equ 2 ; Channel 2 Output Mask FTM2OUTMASK_CH3OM: .equ 3 ; Channel 3 Output Mask FTM2OUTMASK_CH4OM: .equ 4 ; Channel 4 Output Mask FTM2OUTMASK_CH5OM: .equ 5 ; Channel 5 Output Mask ; bit position masks mFTM2OUTMASK_CH0OM: .equ %00000001 mFTM2OUTMASK_CH1OM: .equ %00000010 mFTM2OUTMASK_CH2OM: .equ %00000100 mFTM2OUTMASK_CH3OM: .equ %00001000 mFTM2OUTMASK_CH4OM: .equ %00010000 mFTM2OUTMASK_CH5OM: .equ %00100000 ;*** FTM2COMBINE0 - FTM2 Function For Linked Channel 0 Register; 0xFFFF80E7 *** FTM2COMBINE0: .equ $FFFF80E7 ;*** FTM2COMBINE0 - FTM2 Function For Linked Channel 0 Register; 0xFFFF80E7 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM2COMBINE0_COMBINE: .equ 0 ; Enables the Combine of the Channels 0 and 1 FTM2COMBINE0_COMP: .equ 1 ; Complementary of Channel 0 FTM2COMBINE0_DTEN: .equ 4 ; Deadtime Enable FTM2COMBINE0_SYNCEN: .equ 5 ; Synchronization Enable FTM2COMBINE0_FAULTEN: .equ 6 ; Fault Control Enable ; bit position masks mFTM2COMBINE0_COMBINE: .equ %00000001 mFTM2COMBINE0_COMP: .equ %00000010 mFTM2COMBINE0_DTEN: .equ %00010000 mFTM2COMBINE0_SYNCEN: .equ %00100000 mFTM2COMBINE0_FAULTEN: .equ %01000000 ;*** FTM2COMBINE1 - FTM2 Function For Linked Channel 1 Register; 0xFFFF80E8 *** FTM2COMBINE1: .equ $FFFF80E8 ;*** FTM2COMBINE1 - FTM2 Function For Linked Channel 1 Register; 0xFFFF80E8 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM2COMBINE1_COMBINE: .equ 0 ; Enables the Combine of the Channels 2 and 3 FTM2COMBINE1_COMP: .equ 1 ; Complementary of Channel 2 FTM2COMBINE1_DTEN: .equ 4 ; Deadtime Enable FTM2COMBINE1_SYNCEN: .equ 5 ; Synchronization Enable FTM2COMBINE1_FAULTEN: .equ 6 ; Fault Control Enable ; bit position masks mFTM2COMBINE1_COMBINE: .equ %00000001 mFTM2COMBINE1_COMP: .equ %00000010 mFTM2COMBINE1_DTEN: .equ %00010000 mFTM2COMBINE1_SYNCEN: .equ %00100000 mFTM2COMBINE1_FAULTEN: .equ %01000000 ;*** FTM2COMBINE2 - FTM2 Function For Linked Channel 2 Register; 0xFFFF80E9 *** FTM2COMBINE2: .equ $FFFF80E9 ;*** FTM2COMBINE2 - FTM2 Function For Linked Channel 2 Register; 0xFFFF80E9 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM2COMBINE2_COMBINE: .equ 0 ; Enables the Combine of the Channels 4 and 5 FTM2COMBINE2_COMP: .equ 1 ; Complementary of Channel 4 FTM2COMBINE2_DTEN: .equ 4 ; Deadtime Enable FTM2COMBINE2_SYNCEN: .equ 5 ; Synchronization Enable FTM2COMBINE2_FAULTEN: .equ 6 ; Fault Control Enable ; bit position masks mFTM2COMBINE2_COMBINE: .equ %00000001 mFTM2COMBINE2_COMP: .equ %00000010 mFTM2COMBINE2_DTEN: .equ %00010000 mFTM2COMBINE2_SYNCEN: .equ %00100000 mFTM2COMBINE2_FAULTEN: .equ %01000000 ;*** FTM2DEADTIME - FTM2 Deadtime Insertion Control Register; 0xFFFF80EB *** FTM2DEADTIME: .equ $FFFF80EB ;*** FTM2DEADTIME - FTM2 Deadtime Insertion Control Register; 0xFFFF80EB *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM2DEADTIME_DTVAL0: .equ 0 ; Deadtime Value Bits, bit 0 FTM2DEADTIME_DTVAL1: .equ 1 ; Deadtime Value Bits, bit 1 FTM2DEADTIME_DTVAL2: .equ 2 ; Deadtime Value Bits, bit 2 FTM2DEADTIME_DTVAL3: .equ 3 ; Deadtime Value Bits, bit 3 FTM2DEADTIME_DTVAL4: .equ 4 ; Deadtime Value Bits, bit 4 FTM2DEADTIME_DTVAL5: .equ 5 ; Deadtime Value Bits, bit 5 FTM2DEADTIME_DTPS0: .equ 6 ; Deadtime Prescaler Value Bits, bit 0 FTM2DEADTIME_DTPS1: .equ 7 ; Deadtime Prescaler Value Bits, bit 1 ; bit position masks mFTM2DEADTIME_DTVAL0: .equ %00000001 mFTM2DEADTIME_DTVAL1: .equ %00000010 mFTM2DEADTIME_DTVAL2: .equ %00000100 mFTM2DEADTIME_DTVAL3: .equ %00001000 mFTM2DEADTIME_DTVAL4: .equ %00010000 mFTM2DEADTIME_DTVAL5: .equ %00100000 mFTM2DEADTIME_DTPS0: .equ %01000000 mFTM2DEADTIME_DTPS1: .equ %10000000 ;*** FTM2EXTTRIG - FTM2 ExternalTrigger Register; 0xFFFF80EC *** FTM2EXTTRIG: .equ $FFFF80EC ;*** FTM2EXTTRIG - FTM2 ExternalTrigger Register; 0xFFFF80EC *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM2EXTTRIG_CH2TRIG: .equ 0 ; Channel 2 trigger enable FTM2EXTTRIG_CH3TRIG: .equ 1 ; Channel 3 trigger enable FTM2EXTTRIG_CH4TRIG: .equ 2 ; Channel 4 trigger enable FTM2EXTTRIG_CH5TRIG: .equ 3 ; Channel 5 trigger enable FTM2EXTTRIG_CH0TRIG: .equ 4 ; Channel 0 trigger enable FTM2EXTTRIG_CH1TRIG: .equ 5 ; Channel 1 trigger enable FTM2EXTTRIG_INITTRIGEN: .equ 6 ; Enables the Generation of a Trigger Signal FTM2EXTTRIG_TRIGF: .equ 7 ; Channel trigger flag ; bit position masks mFTM2EXTTRIG_CH2TRIG: .equ %00000001 mFTM2EXTTRIG_CH3TRIG: .equ %00000010 mFTM2EXTTRIG_CH4TRIG: .equ %00000100 mFTM2EXTTRIG_CH5TRIG: .equ %00001000 mFTM2EXTTRIG_CH0TRIG: .equ %00010000 mFTM2EXTTRIG_CH1TRIG: .equ %00100000 mFTM2EXTTRIG_INITTRIGEN: .equ %01000000 mFTM2EXTTRIG_TRIGF: .equ %10000000 ;*** FTM2POL - FTM2 Channels Polarity Register; 0xFFFF80ED *** FTM2POL: .equ $FFFF80ED ;*** FTM2POL - FTM2 Channels Polarity Register; 0xFFFF80ED *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM2POL_POL0: .equ 0 ; Channel 0 Polarity FTM2POL_POL1: .equ 1 ; Channel 1 Polarity FTM2POL_POL2: .equ 2 ; Channel 2 Polarity FTM2POL_POL3: .equ 3 ; Channel 3 Polarity FTM2POL_POL4: .equ 4 ; Channel 4 Polarity FTM2POL_POL5: .equ 5 ; Channel 5 Polarity ; bit position masks mFTM2POL_POL0: .equ %00000001 mFTM2POL_POL1: .equ %00000010 mFTM2POL_POL2: .equ %00000100 mFTM2POL_POL3: .equ %00001000 mFTM2POL_POL4: .equ %00010000 mFTM2POL_POL5: .equ %00100000 ;*** FTM2FMS - FTM2 Fault Mode Status Register; 0xFFFF80EE *** FTM2FMS: .equ $FFFF80EE ;*** FTM2FMS - FTM2 Fault Mode Status Register; 0xFFFF80EE *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM2FMS_FAULTF0: .equ 0 ; Fault detection flag 0 FTM2FMS_FAULTF1: .equ 1 ; Fault detection flag 1 FTM2FMS_FAULTF2: .equ 2 ; Fault detection flag 2 FTM2FMS_FAULTF3: .equ 3 ; Fault detection flag 3 FTM2FMS_FAULTIN: .equ 5 ; Fault Input FTM2FMS_WPEN: .equ 6 ; Write Protected Enable FTM2FMS_FAULTF: .equ 7 ; Fault Detection Flag ; bit position masks mFTM2FMS_FAULTF0: .equ %00000001 mFTM2FMS_FAULTF1: .equ %00000010 mFTM2FMS_FAULTF2: .equ %00000100 mFTM2FMS_FAULTF3: .equ %00001000 mFTM2FMS_FAULTIN: .equ %00100000 mFTM2FMS_WPEN: .equ %01000000 mFTM2FMS_FAULTF: .equ %10000000 ;*** FTM2FILTER0 - FTM2 Input Capture Filter Control Register 0; 0xFFFF80EF *** FTM2FILTER0: .equ $FFFF80EF ;*** FTM2FILTER0 - FTM2 Input Capture Filter Control Register 0; 0xFFFF80EF *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM2FILTER0_CH0FVAL0: .equ 0 ; Channel 0 Input Filter Bits, bit 0 FTM2FILTER0_CH0FVAL1: .equ 1 ; Channel 0 Input Filter Bits, bit 1 FTM2FILTER0_CH0FVAL2: .equ 2 ; Channel 0 Input Filter Bits, bit 2 FTM2FILTER0_CH0FVAL3: .equ 3 ; Channel 0 Input Filter Bits, bit 3 FTM2FILTER0_CH1FVAL0: .equ 4 ; Channel 1 Input Filter Bits, bit 0 FTM2FILTER0_CH1FVAL1: .equ 5 ; Channel 1 Input Filter Bits, bit 1 FTM2FILTER0_CH1FVAL2: .equ 6 ; Channel 1 Input Filter Bits, bit 2 FTM2FILTER0_CH1FVAL3: .equ 7 ; Channel 1 Input Filter Bits, bit 3 ; bit position masks mFTM2FILTER0_CH0FVAL0: .equ %00000001 mFTM2FILTER0_CH0FVAL1: .equ %00000010 mFTM2FILTER0_CH0FVAL2: .equ %00000100 mFTM2FILTER0_CH0FVAL3: .equ %00001000 mFTM2FILTER0_CH1FVAL0: .equ %00010000 mFTM2FILTER0_CH1FVAL1: .equ %00100000 mFTM2FILTER0_CH1FVAL2: .equ %01000000 mFTM2FILTER0_CH1FVAL3: .equ %10000000 ;*** FTM2FILTER1 - FTM2 Input Capture Filter Control Register 1; 0xFFFF80F0 *** FTM2FILTER1: .equ $FFFF80F0 ;*** FTM2FILTER1 - FTM2 Input Capture Filter Control Register 1; 0xFFFF80F0 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM2FILTER1_CH2FVAL0: .equ 0 ; Channel 2 Input Filter Bits, bit 0 FTM2FILTER1_CH2FVAL1: .equ 1 ; Channel 2 Input Filter Bits, bit 1 FTM2FILTER1_CH2FVAL2: .equ 2 ; Channel 2 Input Filter Bits, bit 2 FTM2FILTER1_CH2FVAL3: .equ 3 ; Channel 2 Input Filter Bits, bit 3 FTM2FILTER1_CH3FVAL0: .equ 4 ; Channel 3 Input Filter Bits, bit 0 FTM2FILTER1_CH3FVAL1: .equ 5 ; Channel 3 Input Filter Bits, bit 1 FTM2FILTER1_CH3FVAL2: .equ 6 ; Channel 3 Input Filter Bits, bit 2 FTM2FILTER1_CH3FVAL3: .equ 7 ; Channel 3 Input Filter Bits, bit 3 ; bit position masks mFTM2FILTER1_CH2FVAL0: .equ %00000001 mFTM2FILTER1_CH2FVAL1: .equ %00000010 mFTM2FILTER1_CH2FVAL2: .equ %00000100 mFTM2FILTER1_CH2FVAL3: .equ %00001000 mFTM2FILTER1_CH3FVAL0: .equ %00010000 mFTM2FILTER1_CH3FVAL1: .equ %00100000 mFTM2FILTER1_CH3FVAL2: .equ %01000000 mFTM2FILTER1_CH3FVAL3: .equ %10000000 ;*** FTM2FLTFILTER - FTM2 Fault Input Filter Control Register; 0xFFFF80F1 *** FTM2FLTFILTER: .equ $FFFF80F1 ;*** FTM2FLTFILTER - FTM2 Fault Input Filter Control Register; 0xFFFF80F1 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM2FLTFILTER_FFVAL0: .equ 0 ; Fault Input Filter Bits, bit 0 FTM2FLTFILTER_FFVAL1: .equ 1 ; Fault Input Filter Bits, bit 1 FTM2FLTFILTER_FFVAL2: .equ 2 ; Fault Input Filter Bits, bit 2 FTM2FLTFILTER_FFVAL3: .equ 3 ; Fault Input Filter Bits, bit 3 ; bit position masks mFTM2FLTFILTER_FFVAL0: .equ %00000001 mFTM2FLTFILTER_FFVAL1: .equ %00000010 mFTM2FLTFILTER_FFVAL2: .equ %00000100 mFTM2FLTFILTER_FFVAL3: .equ %00001000 ;*** FTM2FLTCTRL - FTM2 Fault Control Register; 0xFFFF80F2 *** FTM2FLTCTRL: .equ $FFFF80F2 ;*** FTM2FLTCTRL - FTM2 Fault Control Register; 0xFFFF80F2 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FTM2FLTCTRL_FAULT0EN: .equ 0 ; Fault input 0 enable FTM2FLTCTRL_FAULT1EN: .equ 1 ; Fault input 1 enable FTM2FLTCTRL_FFLTR0EN: .equ 4 ; Fault input 0 filter enable ; bit position masks mFTM2FLTCTRL_FAULT0EN: .equ %00000001 mFTM2FLTCTRL_FAULT1EN: .equ %00000010 mFTM2FLTCTRL_FFLTR0EN: .equ %00010000 ;*** PTAPUE - Port A Pulling Enable Register; 0xFFFF8100 *** PTAPUE: .equ $FFFF8100 ;*** PTAPUE - Port A Pulling Enable Register; 0xFFFF8100 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTAPUE_PTAPUE0: .equ 0 ; Internal Pulling Enable for Port A Bit 0 PTAPUE_PTAPUE1: .equ 1 ; Internal Pulling Enable for Port A Bit 1 PTAPUE_PTAPUE2: .equ 2 ; Internal Pulling Enable for Port A Bit 2 PTAPUE_PTAPUE3: .equ 3 ; Internal Pulling Enable for Port A Bit 3 PTAPUE_PTAPUE4: .equ 4 ; Internal Pulling Enable for Port A Bit 4 PTAPUE_PTAPUE5: .equ 5 ; Internal Pulling Enable for Port A Bit 5 PTAPUE_PTAPUE6: .equ 6 ; Internal Pulling Enable for Port A Bit 6 PTAPUE_PTAPUE7: .equ 7 ; Internal Pulling Enable for Port A Bit 7 ; bit position masks mPTAPUE_PTAPUE0: .equ %00000001 mPTAPUE_PTAPUE1: .equ %00000010 mPTAPUE_PTAPUE2: .equ %00000100 mPTAPUE_PTAPUE3: .equ %00001000 mPTAPUE_PTAPUE4: .equ %00010000 mPTAPUE_PTAPUE5: .equ %00100000 mPTAPUE_PTAPUE6: .equ %01000000 mPTAPUE_PTAPUE7: .equ %10000000 ;*** PTAPUS - Port A Pullup/Pulldown Select Register; 0xFFFF8101 *** PTAPUS: .equ $FFFF8101 ;*** PTAPUS - Port A Pullup/Pulldown Select Register; 0xFFFF8101 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTAPUS_PTAPUS0: .equ 0 ; Pullup/Pulldown Select Bit 0 PTAPUS_PTAPUS1: .equ 1 ; Pullup/Pulldown Select Bit 1 PTAPUS_PTAPUS2: .equ 2 ; Pullup/Pulldown Select Bit 2 PTAPUS_PTAPUS3: .equ 3 ; Pullup/Pulldown Select Bit 3 PTAPUS_PTAPUS4: .equ 4 ; Pullup/Pulldown Select Bit 4 PTAPUS_PTAPUS5: .equ 5 ; Pullup/Pulldown Select Bit 5 PTAPUS_PTAPUS6: .equ 6 ; Pullup/Pulldown Select Bit 6 PTAPUS_PTAPUS7: .equ 7 ; Pullup/Pulldown Select Bit 7 ; bit position masks mPTAPUS_PTAPUS0: .equ %00000001 mPTAPUS_PTAPUS1: .equ %00000010 mPTAPUS_PTAPUS2: .equ %00000100 mPTAPUS_PTAPUS3: .equ %00001000 mPTAPUS_PTAPUS4: .equ %00010000 mPTAPUS_PTAPUS5: .equ %00100000 mPTAPUS_PTAPUS6: .equ %01000000 mPTAPUS_PTAPUS7: .equ %10000000 ;*** PTADS - Port A Drive Strength Selection Register; 0xFFFF8102 *** PTADS: .equ $FFFF8102 ;*** PTADS - Port A Drive Strength Selection Register; 0xFFFF8102 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTADS_PTADS0: .equ 0 ; Output Drive Strength Selection for Port A Bit 0 PTADS_PTADS1: .equ 1 ; Output Drive Strength Selection for Port A Bit 1 PTADS_PTADS2: .equ 2 ; Output Drive Strength Selection for Port A Bit 2 PTADS_PTADS3: .equ 3 ; Output Drive Strength Selection for Port A Bit 3 PTADS_PTADS4: .equ 4 ; Output Drive Strength Selection for Port A Bit 4 PTADS_PTADS5: .equ 5 ; Output Drive Strength Selection for Port A Bit 5 PTADS_PTADS6: .equ 6 ; Output Drive Strength Selection for Port A Bit 6 PTADS_PTADS7: .equ 7 ; Output Drive Strength Selection for Port A Bit 7 ; bit position masks mPTADS_PTADS0: .equ %00000001 mPTADS_PTADS1: .equ %00000010 mPTADS_PTADS2: .equ %00000100 mPTADS_PTADS3: .equ %00001000 mPTADS_PTADS4: .equ %00010000 mPTADS_PTADS5: .equ %00100000 mPTADS_PTADS6: .equ %01000000 mPTADS_PTADS7: .equ %10000000 ;*** PTASRE - Port A Slew Rate Enable Register; 0xFFFF8103 *** PTASRE: .equ $FFFF8103 ;*** PTASRE - Port A Slew Rate Enable Register; 0xFFFF8103 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTASRE_PTASRE0: .equ 0 ; Output Slew Rate Enable for Port A Bit 0 PTASRE_PTASRE1: .equ 1 ; Output Slew Rate Enable for Port A Bit 1 PTASRE_PTASRE2: .equ 2 ; Output Slew Rate Enable for Port A Bit 2 PTASRE_PTASRE3: .equ 3 ; Output Slew Rate Enable for Port A Bit 3 PTASRE_PTASRE4: .equ 4 ; Output Slew Rate Enable for Port A Bit 4 PTASRE_PTASRE5: .equ 5 ; Output Slew Rate Enable for Port A Bit 5 PTASRE_PTASRE6: .equ 6 ; Output Slew Rate Enable for Port A Bit 6 PTASRE_PTASRE7: .equ 7 ; Output Slew Rate Enable for Port A Bit 7 ; bit position masks mPTASRE_PTASRE0: .equ %00000001 mPTASRE_PTASRE1: .equ %00000010 mPTASRE_PTASRE2: .equ %00000100 mPTASRE_PTASRE3: .equ %00001000 mPTASRE_PTASRE4: .equ %00010000 mPTASRE_PTASRE5: .equ %00100000 mPTASRE_PTASRE6: .equ %01000000 mPTASRE_PTASRE7: .equ %10000000 ;*** PTAPFE - Port A Passive Filter Enable Register; 0xFFFF8104 *** PTAPFE: .equ $FFFF8104 ;*** PTAPFE - Port A Passive Filter Enable Register; 0xFFFF8104 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTAPFE_PTAPFE0: .equ 0 ; Port A Input Filter Enable Bit 0 PTAPFE_PTAPFE1: .equ 1 ; Port A Input Filter Enable Bit 1 PTAPFE_PTAPFE2: .equ 2 ; Port A Input Filter Enable Bit 2 PTAPFE_PTAPFE3: .equ 3 ; Port A Input Filter Enable Bit 3 PTAPFE_PTAPFE4: .equ 4 ; Port A Input Filter Enable Bit 4 PTAPFE_PTAPFE5: .equ 5 ; Port A Input Filter Enable Bit 5 PTAPFE_PTAPFE6: .equ 6 ; Port A Input Filter Enable Bit 6 PTAPFE_PTAPFE7: .equ 7 ; Port A Input Filter Enable Bit 7 ; bit position masks mPTAPFE_PTAPFE0: .equ %00000001 mPTAPFE_PTAPFE1: .equ %00000010 mPTAPFE_PTAPFE2: .equ %00000100 mPTAPFE_PTAPFE3: .equ %00001000 mPTAPFE_PTAPFE4: .equ %00010000 mPTAPFE_PTAPFE5: .equ %00100000 mPTAPFE_PTAPFE6: .equ %01000000 mPTAPFE_PTAPFE7: .equ %10000000 ;*** PTAIC - Port A Interrupt Control Register; 0xFFFF8105 *** PTAIC: .equ $FFFF8105 ;*** PTAIC - Port A Interrupt Control Register; 0xFFFF8105 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTAIC_PTAMOD: .equ 0 ; Detection Mode for Pin Interrupt PTAIC_PTAIE: .equ 1 ; Interrupt Enable PTAIC_PTADMAEN: .equ 7 ; DMA Enable bit ; bit position masks mPTAIC_PTAMOD: .equ %00000001 mPTAIC_PTAIE: .equ %00000010 mPTAIC_PTADMAEN: .equ %10000000 ;*** PTAIPE - Port A Interrupt Pin Enable Register; 0xFFFF8106 *** PTAIPE: .equ $FFFF8106 ;*** PTAIPE - Port A Interrupt Pin Enable Register; 0xFFFF8106 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTAIPE_PTAIPE0: .equ 0 ; Interrupt Pin Enable Bit 0 PTAIPE_PTAIPE1: .equ 1 ; Interrupt Pin Enable Bit 1 PTAIPE_PTAIPE2: .equ 2 ; Interrupt Pin Enable Bit 2 PTAIPE_PTAIPE3: .equ 3 ; Interrupt Pin Enable Bit 3 PTAIPE_PTAIPE4: .equ 4 ; Interrupt Pin Enable Bit 4 PTAIPE_PTAIPE5: .equ 5 ; Interrupt Pin Enable Bit 5 PTAIPE_PTAIPE6: .equ 6 ; Interrupt Pin Enable Bit 6 PTAIPE_PTAIPE7: .equ 7 ; Interrupt Pin Enable Bit 7 ; bit position masks mPTAIPE_PTAIPE0: .equ %00000001 mPTAIPE_PTAIPE1: .equ %00000010 mPTAIPE_PTAIPE2: .equ %00000100 mPTAIPE_PTAIPE3: .equ %00001000 mPTAIPE_PTAIPE4: .equ %00010000 mPTAIPE_PTAIPE5: .equ %00100000 mPTAIPE_PTAIPE6: .equ %01000000 mPTAIPE_PTAIPE7: .equ %10000000 ;*** PTAIF - Port A Interrupt Flag Register; 0xFFFF8107 *** PTAIF: .equ $FFFF8107 ;*** PTAIF - Port A Interrupt Flag Register; 0xFFFF8107 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTAIF_PTAIF0: .equ 0 ; Interrupt Flag Bit 0 PTAIF_PTAIF1: .equ 1 ; Interrupt Flag Bit 1 PTAIF_PTAIF2: .equ 2 ; Interrupt Flag Bit 2 PTAIF_PTAIF3: .equ 3 ; Interrupt Flag Bit 3 PTAIF_PTAIF4: .equ 4 ; Interrupt Flag Bit 4 PTAIF_PTAIF5: .equ 5 ; Interrupt Flag Bit 5 PTAIF_PTAIF6: .equ 6 ; Interrupt Flag Bit 6 PTAIF_PTAIF7: .equ 7 ; Interrupt Flag Bit 7 ; bit position masks mPTAIF_PTAIF0: .equ %00000001 mPTAIF_PTAIF1: .equ %00000010 mPTAIF_PTAIF2: .equ %00000100 mPTAIF_PTAIF3: .equ %00001000 mPTAIF_PTAIF4: .equ %00010000 mPTAIF_PTAIF5: .equ %00100000 mPTAIF_PTAIF6: .equ %01000000 mPTAIF_PTAIF7: .equ %10000000 ;*** PTAIES - Port A Interrupt Edge Select Register; 0xFFFF8108 *** PTAIES: .equ $FFFF8108 ;*** PTAIES - Port A Interrupt Edge Select Register; 0xFFFF8108 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTAIES_PTAEDG0: .equ 0 ; Edge Selects of Pin Interrupt Bit 0 PTAIES_PTAEDG1: .equ 1 ; Edge Selects of Pin Interrupt Bit 1 PTAIES_PTAEDG2: .equ 2 ; Edge Selects of Pin Interrupt Bit 2 PTAIES_PTAEDG3: .equ 3 ; Edge Selects of Pin Interrupt Bit 3 PTAIES_PTAEDG4: .equ 4 ; Edge Selects of Pin Interrupt Bit 4 PTAIES_PTAEDG5: .equ 5 ; Edge Selects of Pin Interrupt Bit 5 PTAIES_PTAEDG6: .equ 6 ; Edge Selects of Pin Interrupt Bit 6 PTAIES_PTAEDG7: .equ 7 ; Edge Selects of Pin Interrupt Bit 7 ; bit position masks mPTAIES_PTAEDG0: .equ %00000001 mPTAIES_PTAEDG1: .equ %00000010 mPTAIES_PTAEDG2: .equ %00000100 mPTAIES_PTAEDG3: .equ %00001000 mPTAIES_PTAEDG4: .equ %00010000 mPTAIES_PTAEDG5: .equ %00100000 mPTAIES_PTAEDG6: .equ %01000000 mPTAIES_PTAEDG7: .equ %10000000 ;*** PTADFE - Port A Digital Filter Enable Register; 0xFFFF8109 *** PTADFE: .equ $FFFF8109 ;*** PTADFE - Port A Digital Filter Enable Register; 0xFFFF8109 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTADFE_PTADFE0: .equ 0 ; Digital Filter Enable Bit 0 PTADFE_PTADFE1: .equ 1 ; Digital Filter Enable Bit 1 PTADFE_PTADFE2: .equ 2 ; Digital Filter Enable Bit 2 PTADFE_PTADFE3: .equ 3 ; Digital Filter Enable Bit 3 PTADFE_PTADFE4: .equ 4 ; Digital Filter Enable Bit 4 PTADFE_PTADFE5: .equ 5 ; Digital Filter Enable Bit 5 PTADFE_PTADFE6: .equ 6 ; Digital Filter Enable Bit 6 PTADFE_PTADFE7: .equ 7 ; Digital Filter Enable Bit 7 ; bit position masks mPTADFE_PTADFE0: .equ %00000001 mPTADFE_PTADFE1: .equ %00000010 mPTADFE_PTADFE2: .equ %00000100 mPTADFE_PTADFE3: .equ %00001000 mPTADFE_PTADFE4: .equ %00010000 mPTADFE_PTADFE5: .equ %00100000 mPTADFE_PTADFE6: .equ %01000000 mPTADFE_PTADFE7: .equ %10000000 ;*** PTADFC - Port A Digital Filter Control Register; 0xFFFF810A *** PTADFC: .equ $FFFF810A ;*** PTADFC - Port A Digital Filter Control Register; 0xFFFF810A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTADFC_PTAFF0: .equ 0 ; Filter Factor Bits, bit 0 PTADFC_PTAFF1: .equ 1 ; Filter Factor Bits, bit 1 PTADFC_PTAFF2: .equ 2 ; Filter Factor Bits, bit 2 PTADFC_PTAFF3: .equ 3 ; Filter Factor Bits, bit 3 PTADFC_PTAFF4: .equ 4 ; Filter Factor Bits, bit 4 PTADFC_PTACLKS: .equ 7 ; Clok Select Bit ; bit position masks mPTADFC_PTAFF0: .equ %00000001 mPTADFC_PTAFF1: .equ %00000010 mPTADFC_PTAFF2: .equ %00000100 mPTADFC_PTAFF3: .equ %00001000 mPTADFC_PTAFF4: .equ %00010000 mPTADFC_PTACLKS: .equ %10000000 ;*** PTBPUE - Port B Pulling Enable Register; 0xFFFF8110 *** PTBPUE: .equ $FFFF8110 ;*** PTBPUE - Port B Pulling Enable Register; 0xFFFF8110 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTBPUE_PTBPUE0: .equ 0 ; Internal Pulling Enable for Port B Bit 0 PTBPUE_PTBPUE1: .equ 1 ; Internal Pulling Enable for Port B Bit 1 PTBPUE_PTBPUE2: .equ 2 ; Internal Pulling Enable for Port B Bit 2 PTBPUE_PTBPUE3: .equ 3 ; Internal Pulling Enable for Port B Bit 3 PTBPUE_PTBPUE4: .equ 4 ; Internal Pulling Enable for Port B Bit 4 PTBPUE_PTBPUE5: .equ 5 ; Internal Pulling Enable for Port B Bit 5 PTBPUE_PTBPUE6: .equ 6 ; Internal Pulling Enable for Port B Bit 6 PTBPUE_PTBPUE7: .equ 7 ; Internal Pulling Enable for Port B Bit 7 ; bit position masks mPTBPUE_PTBPUE0: .equ %00000001 mPTBPUE_PTBPUE1: .equ %00000010 mPTBPUE_PTBPUE2: .equ %00000100 mPTBPUE_PTBPUE3: .equ %00001000 mPTBPUE_PTBPUE4: .equ %00010000 mPTBPUE_PTBPUE5: .equ %00100000 mPTBPUE_PTBPUE6: .equ %01000000 mPTBPUE_PTBPUE7: .equ %10000000 ;*** PTBPUS - Port B Pullup/Pulldown Select Register; 0xFFFF8111 *** PTBPUS: .equ $FFFF8111 ;*** PTBPUS - Port B Pullup/Pulldown Select Register; 0xFFFF8111 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTBPUS_PTBPUS0: .equ 0 ; Pullup/Pulldown Select Bit 0 PTBPUS_PTBPUS1: .equ 1 ; Pullup/Pulldown Select Bit 1 PTBPUS_PTBPUS2: .equ 2 ; Pullup/Pulldown Select Bit 2 PTBPUS_PTBPUS3: .equ 3 ; Pullup/Pulldown Select Bit 3 PTBPUS_PTBPUS4: .equ 4 ; Pullup/Pulldown Select Bit 4 PTBPUS_PTBPUS5: .equ 5 ; Pullup/Pulldown Select Bit 5 PTBPUS_PTBPUS6: .equ 6 ; Pullup/Pulldown Select Bit 6 PTBPUS_PTBPUS7: .equ 7 ; Pullup/Pulldown Select Bit 7 ; bit position masks mPTBPUS_PTBPUS0: .equ %00000001 mPTBPUS_PTBPUS1: .equ %00000010 mPTBPUS_PTBPUS2: .equ %00000100 mPTBPUS_PTBPUS3: .equ %00001000 mPTBPUS_PTBPUS4: .equ %00010000 mPTBPUS_PTBPUS5: .equ %00100000 mPTBPUS_PTBPUS6: .equ %01000000 mPTBPUS_PTBPUS7: .equ %10000000 ;*** PTBDS - Port B Drive Strength Selection Register; 0xFFFF8112 *** PTBDS: .equ $FFFF8112 ;*** PTBDS - Port B Drive Strength Selection Register; 0xFFFF8112 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTBDS_PTBDS0: .equ 0 ; Output Drive Strength Selection for Port B Bit 0 PTBDS_PTBDS1: .equ 1 ; Output Drive Strength Selection for Port B Bit 1 PTBDS_PTBDS2: .equ 2 ; Output Drive Strength Selection for Port B Bit 2 PTBDS_PTBDS3: .equ 3 ; Output Drive Strength Selection for Port B Bit 3 PTBDS_PTBDS4: .equ 4 ; Output Drive Strength Selection for Port B Bit 4 PTBDS_PTBDS5: .equ 5 ; Output Drive Strength Selection for Port B Bit 5 PTBDS_PTBDS6: .equ 6 ; Output Drive Strength Selection for Port B Bit 6 PTBDS_PTBDS7: .equ 7 ; Output Drive Strength Selection for Port B Bit 7 ; bit position masks mPTBDS_PTBDS0: .equ %00000001 mPTBDS_PTBDS1: .equ %00000010 mPTBDS_PTBDS2: .equ %00000100 mPTBDS_PTBDS3: .equ %00001000 mPTBDS_PTBDS4: .equ %00010000 mPTBDS_PTBDS5: .equ %00100000 mPTBDS_PTBDS6: .equ %01000000 mPTBDS_PTBDS7: .equ %10000000 ;*** PTBSRE - Port B Slew Rate Enable Register; 0xFFFF8113 *** PTBSRE: .equ $FFFF8113 ;*** PTBSRE - Port B Slew Rate Enable Register; 0xFFFF8113 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTBSRE_PTBSRE0: .equ 0 ; Output Slew Rate Enable for Port B Bit 0 PTBSRE_PTBSRE1: .equ 1 ; Output Slew Rate Enable for Port B Bit 1 PTBSRE_PTBSRE2: .equ 2 ; Output Slew Rate Enable for Port B Bit 2 PTBSRE_PTBSRE3: .equ 3 ; Output Slew Rate Enable for Port B Bit 3 PTBSRE_PTBSRE4: .equ 4 ; Output Slew Rate Enable for Port B Bit 4 PTBSRE_PTBSRE5: .equ 5 ; Output Slew Rate Enable for Port B Bit 5 PTBSRE_PTBSRE6: .equ 6 ; Output Slew Rate Enable for Port B Bit 6 PTBSRE_PTBSRE7: .equ 7 ; Output Slew Rate Enable for Port B Bit 7 ; bit position masks mPTBSRE_PTBSRE0: .equ %00000001 mPTBSRE_PTBSRE1: .equ %00000010 mPTBSRE_PTBSRE2: .equ %00000100 mPTBSRE_PTBSRE3: .equ %00001000 mPTBSRE_PTBSRE4: .equ %00010000 mPTBSRE_PTBSRE5: .equ %00100000 mPTBSRE_PTBSRE6: .equ %01000000 mPTBSRE_PTBSRE7: .equ %10000000 ;*** PTBPFE - Port B Passive Filter Enable Register; 0xFFFF8114 *** PTBPFE: .equ $FFFF8114 ;*** PTBPFE - Port B Passive Filter Enable Register; 0xFFFF8114 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTBPFE_PTBPFE0: .equ 0 ; Port A Input Filter Enable Bit 0 PTBPFE_PTBPFE1: .equ 1 ; Port A Input Filter Enable Bit 1 PTBPFE_PTBPFE2: .equ 2 ; Port A Input Filter Enable Bit 2 PTBPFE_PTBPFE3: .equ 3 ; Port A Input Filter Enable Bit 3 PTBPFE_PTBPFE4: .equ 4 ; Port A Input Filter Enable Bit 4 PTBPFE_PTBPFE5: .equ 5 ; Port A Input Filter Enable Bit 5 PTBPFE_PTBPFE6: .equ 6 ; Port A Input Filter Enable Bit 6 PTBPFE_PTBPFE7: .equ 7 ; Port A Input Filter Enable Bit 7 ; bit position masks mPTBPFE_PTBPFE0: .equ %00000001 mPTBPFE_PTBPFE1: .equ %00000010 mPTBPFE_PTBPFE2: .equ %00000100 mPTBPFE_PTBPFE3: .equ %00001000 mPTBPFE_PTBPFE4: .equ %00010000 mPTBPFE_PTBPFE5: .equ %00100000 mPTBPFE_PTBPFE6: .equ %01000000 mPTBPFE_PTBPFE7: .equ %10000000 ;*** PTBIC - Port B Interrupt Control Register; 0xFFFF8115 *** PTBIC: .equ $FFFF8115 ;*** PTBIC - Port B Interrupt Control Register; 0xFFFF8115 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTBIC_PTBMOD: .equ 0 ; Detection Mode for Pin Interrupt PTBIC_PTBIE: .equ 1 ; Interrupt Enable PTBIC_PTBDMAEN: .equ 7 ; DMA Enable bit ; bit position masks mPTBIC_PTBMOD: .equ %00000001 mPTBIC_PTBIE: .equ %00000010 mPTBIC_PTBDMAEN: .equ %10000000 ;*** PTBIPE - Port B Interrupt Pin Enable Register; 0xFFFF8116 *** PTBIPE: .equ $FFFF8116 ;*** PTBIPE - Port B Interrupt Pin Enable Register; 0xFFFF8116 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTBIPE_PTBIPE0: .equ 0 ; Interrupt Pin Enable Bit 0 PTBIPE_PTBIPE1: .equ 1 ; Interrupt Pin Enable Bit 1 PTBIPE_PTBIPE2: .equ 2 ; Interrupt Pin Enable Bit 2 PTBIPE_PTBIPE3: .equ 3 ; Interrupt Pin Enable Bit 3 PTBIPE_PTBIPE4: .equ 4 ; Interrupt Pin Enable Bit 4 PTBIPE_PTBIPE5: .equ 5 ; Interrupt Pin Enable Bit 5 PTBIPE_PTBIPE6: .equ 6 ; Interrupt Pin Enable Bit 6 PTBIPE_PTBIPE7: .equ 7 ; Interrupt Pin Enable Bit 7 ; bit position masks mPTBIPE_PTBIPE0: .equ %00000001 mPTBIPE_PTBIPE1: .equ %00000010 mPTBIPE_PTBIPE2: .equ %00000100 mPTBIPE_PTBIPE3: .equ %00001000 mPTBIPE_PTBIPE4: .equ %00010000 mPTBIPE_PTBIPE5: .equ %00100000 mPTBIPE_PTBIPE6: .equ %01000000 mPTBIPE_PTBIPE7: .equ %10000000 ;*** PTBIF - Port B Interrupt Flag Register; 0xFFFF8117 *** PTBIF: .equ $FFFF8117 ;*** PTBIF - Port B Interrupt Flag Register; 0xFFFF8117 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTBIF_PTBIF0: .equ 0 ; Interrupt Flag Bit 0 PTBIF_PTBIF1: .equ 1 ; Interrupt Flag Bit 1 PTBIF_PTBIF2: .equ 2 ; Interrupt Flag Bit 2 PTBIF_PTBIF3: .equ 3 ; Interrupt Flag Bit 3 PTBIF_PTBIF4: .equ 4 ; Interrupt Flag Bit 4 PTBIF_PTBIF5: .equ 5 ; Interrupt Flag Bit 5 PTBIF_PTBIF6: .equ 6 ; Interrupt Flag Bit 6 PTBIF_PTBIF7: .equ 7 ; Interrupt Flag Bit 7 ; bit position masks mPTBIF_PTBIF0: .equ %00000001 mPTBIF_PTBIF1: .equ %00000010 mPTBIF_PTBIF2: .equ %00000100 mPTBIF_PTBIF3: .equ %00001000 mPTBIF_PTBIF4: .equ %00010000 mPTBIF_PTBIF5: .equ %00100000 mPTBIF_PTBIF6: .equ %01000000 mPTBIF_PTBIF7: .equ %10000000 ;*** PTBIES - Port B Interrupt Edge Select Register; 0xFFFF8118 *** PTBIES: .equ $FFFF8118 ;*** PTBIES - Port B Interrupt Edge Select Register; 0xFFFF8118 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTBIES_PTBEDG0: .equ 0 ; Edge Selects of Pin Interrupt Bit 0 PTBIES_PTBEDG1: .equ 1 ; Edge Selects of Pin Interrupt Bit 1 PTBIES_PTBEDG2: .equ 2 ; Edge Selects of Pin Interrupt Bit 2 PTBIES_PTBEDG3: .equ 3 ; Edge Selects of Pin Interrupt Bit 3 PTBIES_PTBEDG4: .equ 4 ; Edge Selects of Pin Interrupt Bit 4 PTBIES_PTBEDG5: .equ 5 ; Edge Selects of Pin Interrupt Bit 5 PTBIES_PTBEDG6: .equ 6 ; Edge Selects of Pin Interrupt Bit 6 PTBIES_PTBEDG7: .equ 7 ; Edge Selects of Pin Interrupt Bit 7 ; bit position masks mPTBIES_PTBEDG0: .equ %00000001 mPTBIES_PTBEDG1: .equ %00000010 mPTBIES_PTBEDG2: .equ %00000100 mPTBIES_PTBEDG3: .equ %00001000 mPTBIES_PTBEDG4: .equ %00010000 mPTBIES_PTBEDG5: .equ %00100000 mPTBIES_PTBEDG6: .equ %01000000 mPTBIES_PTBEDG7: .equ %10000000 ;*** PTBDFE - Port B Digital Filter Enable Register; 0xFFFF8119 *** PTBDFE: .equ $FFFF8119 ;*** PTBDFE - Port B Digital Filter Enable Register; 0xFFFF8119 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTBDFE_PTBDFE0: .equ 0 ; Digital Filter Enable Bit 0 PTBDFE_PTBDFE1: .equ 1 ; Digital Filter Enable Bit 1 PTBDFE_PTBDFE2: .equ 2 ; Digital Filter Enable Bit 2 PTBDFE_PTBDFE3: .equ 3 ; Digital Filter Enable Bit 3 PTBDFE_PTBDFE4: .equ 4 ; Digital Filter Enable Bit 4 PTBDFE_PTBDFE5: .equ 5 ; Digital Filter Enable Bit 5 PTBDFE_PTBDFE6: .equ 6 ; Digital Filter Enable Bit 6 PTBDFE_PTBDFE7: .equ 7 ; Digital Filter Enable Bit 7 ; bit position masks mPTBDFE_PTBDFE0: .equ %00000001 mPTBDFE_PTBDFE1: .equ %00000010 mPTBDFE_PTBDFE2: .equ %00000100 mPTBDFE_PTBDFE3: .equ %00001000 mPTBDFE_PTBDFE4: .equ %00010000 mPTBDFE_PTBDFE5: .equ %00100000 mPTBDFE_PTBDFE6: .equ %01000000 mPTBDFE_PTBDFE7: .equ %10000000 ;*** PTBDFC - Port B Digital Filter Control Register; 0xFFFF811A *** PTBDFC: .equ $FFFF811A ;*** PTBDFC - Port B Digital Filter Control Register; 0xFFFF811A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTBDFC_PTBFF0: .equ 0 ; Filter Factor Bits, bit 0 PTBDFC_PTBFF1: .equ 1 ; Filter Factor Bits, bit 1 PTBDFC_PTBFF2: .equ 2 ; Filter Factor Bits, bit 2 PTBDFC_PTBFF3: .equ 3 ; Filter Factor Bits, bit 3 PTBDFC_PTBFF4: .equ 4 ; Filter Factor Bits, bit 4 PTBDFC_PTBCLKS: .equ 7 ; Clok Select Bit ; bit position masks mPTBDFC_PTBFF0: .equ %00000001 mPTBDFC_PTBFF1: .equ %00000010 mPTBDFC_PTBFF2: .equ %00000100 mPTBDFC_PTBFF3: .equ %00001000 mPTBDFC_PTBFF4: .equ %00010000 mPTBDFC_PTBCLKS: .equ %10000000 ;*** PTCPUE - Port C Pulling Enable Register; 0xFFFF8120 *** PTCPUE: .equ $FFFF8120 ;*** PTCPUE - Port C Pulling Enable Register; 0xFFFF8120 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTCPUE_PTCPUE0: .equ 0 ; Internal Pulling Enable for Port C Bit 0 PTCPUE_PTCPUE1: .equ 1 ; Internal Pulling Enable for Port C Bit 1 PTCPUE_PTCPUE2: .equ 2 ; Internal Pulling Enable for Port C Bit 2 PTCPUE_PTCPUE3: .equ 3 ; Internal Pulling Enable for Port C Bit 3 PTCPUE_PTCPUE4: .equ 4 ; Internal Pulling Enable for Port C Bit 4 PTCPUE_PTCPUE5: .equ 5 ; Internal Pulling Enable for Port C Bit 5 PTCPUE_PTCPUE6: .equ 6 ; Internal Pulling Enable for Port C Bit 6 ; bit position masks mPTCPUE_PTCPUE0: .equ %00000001 mPTCPUE_PTCPUE1: .equ %00000010 mPTCPUE_PTCPUE2: .equ %00000100 mPTCPUE_PTCPUE3: .equ %00001000 mPTCPUE_PTCPUE4: .equ %00010000 mPTCPUE_PTCPUE5: .equ %00100000 mPTCPUE_PTCPUE6: .equ %01000000 ;*** PTCPUS - Port C Pullup/Pulldown Select Register; 0xFFFF8121 *** PTCPUS: .equ $FFFF8121 ;*** PTCPUS - Port C Pullup/Pulldown Select Register; 0xFFFF8121 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTCPUS_PTCPUS0: .equ 0 ; Pullup/Pulldown Select Bit 0 PTCPUS_PTCPUS1: .equ 1 ; Pullup/Pulldown Select Bit 1 PTCPUS_PTCPUS2: .equ 2 ; Pullup/Pulldown Select Bit 2 PTCPUS_PTCPUS3: .equ 3 ; Pullup/Pulldown Select Bit 3 PTCPUS_PTCPUS4: .equ 4 ; Pullup/Pulldown Select Bit 4 PTCPUS_PTCPUS5: .equ 5 ; Pullup/Pulldown Select Bit 5 PTCPUS_PTCPUS6: .equ 6 ; Pullup/Pulldown Select Bit 6 ; bit position masks mPTCPUS_PTCPUS0: .equ %00000001 mPTCPUS_PTCPUS1: .equ %00000010 mPTCPUS_PTCPUS2: .equ %00000100 mPTCPUS_PTCPUS3: .equ %00001000 mPTCPUS_PTCPUS4: .equ %00010000 mPTCPUS_PTCPUS5: .equ %00100000 mPTCPUS_PTCPUS6: .equ %01000000 ;*** PTCDS - Port C Drive Strength Selection Register; 0xFFFF8122 *** PTCDS: .equ $FFFF8122 ;*** PTCDS - Port C Drive Strength Selection Register; 0xFFFF8122 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTCDS_PTCDS0: .equ 0 ; Output Drive Strength Selection for Port C Bit 0 PTCDS_PTCDS1: .equ 1 ; Output Drive Strength Selection for Port C Bit 1 PTCDS_PTCDS2: .equ 2 ; Output Drive Strength Selection for Port C Bit 2 PTCDS_PTCDS3: .equ 3 ; Output Drive Strength Selection for Port C Bit 3 PTCDS_PTCDS4: .equ 4 ; Output Drive Strength Selection for Port C Bit 4 PTCDS_PTCDS5: .equ 5 ; Output Drive Strength Selection for Port C Bit 5 PTCDS_PTCDS6: .equ 6 ; Output Drive Strength Selection for Port C Bit 6 ; bit position masks mPTCDS_PTCDS0: .equ %00000001 mPTCDS_PTCDS1: .equ %00000010 mPTCDS_PTCDS2: .equ %00000100 mPTCDS_PTCDS3: .equ %00001000 mPTCDS_PTCDS4: .equ %00010000 mPTCDS_PTCDS5: .equ %00100000 mPTCDS_PTCDS6: .equ %01000000 ;*** PTCSRE - Port C Slew Rate Enable Register; 0xFFFF8123 *** PTCSRE: .equ $FFFF8123 ;*** PTCSRE - Port C Slew Rate Enable Register; 0xFFFF8123 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTCSRE_PTCSRE0: .equ 0 ; Output Slew Rate Enable for Port C Bit 0 PTCSRE_PTCSRE1: .equ 1 ; Output Slew Rate Enable for Port C Bit 1 PTCSRE_PTCSRE2: .equ 2 ; Output Slew Rate Enable for Port C Bit 2 PTCSRE_PTCSRE3: .equ 3 ; Output Slew Rate Enable for Port C Bit 3 PTCSRE_PTCSRE4: .equ 4 ; Output Slew Rate Enable for Port C Bit 4 PTCSRE_PTCSRE5: .equ 5 ; Output Slew Rate Enable for Port C Bit 5 PTCSRE_PTCSRE6: .equ 6 ; Output Slew Rate Enable for Port C Bit 6 ; bit position masks mPTCSRE_PTCSRE0: .equ %00000001 mPTCSRE_PTCSRE1: .equ %00000010 mPTCSRE_PTCSRE2: .equ %00000100 mPTCSRE_PTCSRE3: .equ %00001000 mPTCSRE_PTCSRE4: .equ %00010000 mPTCSRE_PTCSRE5: .equ %00100000 mPTCSRE_PTCSRE6: .equ %01000000 ;*** PTCPFE - Port C Passive Filter Enable Register; 0xFFFF8124 *** PTCPFE: .equ $FFFF8124 ;*** PTCPFE - Port C Passive Filter Enable Register; 0xFFFF8124 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTCPFE_PTCPFE0: .equ 0 ; Port A Input Filter Enable Bit 0 PTCPFE_PTCPFE1: .equ 1 ; Port A Input Filter Enable Bit 1 PTCPFE_PTCPFE2: .equ 2 ; Port A Input Filter Enable Bit 2 PTCPFE_PTCPFE3: .equ 3 ; Port A Input Filter Enable Bit 3 PTCPFE_PTCPFE4: .equ 4 ; Port A Input Filter Enable Bit 4 PTCPFE_PTCPFE5: .equ 5 ; Port A Input Filter Enable Bit 5 PTCPFE_PTCPFE6: .equ 6 ; Port A Input Filter Enable Bit 6 ; bit position masks mPTCPFE_PTCPFE0: .equ %00000001 mPTCPFE_PTCPFE1: .equ %00000010 mPTCPFE_PTCPFE2: .equ %00000100 mPTCPFE_PTCPFE3: .equ %00001000 mPTCPFE_PTCPFE4: .equ %00010000 mPTCPFE_PTCPFE5: .equ %00100000 mPTCPFE_PTCPFE6: .equ %01000000 ;*** PTCIC - Port C Interrupt Control Register; 0xFFFF8125 *** PTCIC: .equ $FFFF8125 ;*** PTCIC - Port C Interrupt Control Register; 0xFFFF8125 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTCIC_PTCMOD: .equ 0 ; Detection Mode for Pin Interrupt PTCIC_PTCIE: .equ 1 ; Interrupt Enable PTCIC_PTCDMAEN: .equ 7 ; DMA Enable bit ; bit position masks mPTCIC_PTCMOD: .equ %00000001 mPTCIC_PTCIE: .equ %00000010 mPTCIC_PTCDMAEN: .equ %10000000 ;*** PTCIPE - Port C Interrupt Pin Enable Register; 0xFFFF8126 *** PTCIPE: .equ $FFFF8126 ;*** PTCIPE - Port C Interrupt Pin Enable Register; 0xFFFF8126 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTCIPE_PTCIPE0: .equ 0 ; Interrupt Pin Enable Bit 0 PTCIPE_PTCIPE1: .equ 1 ; Interrupt Pin Enable Bit 1 PTCIPE_PTCIPE2: .equ 2 ; Interrupt Pin Enable Bit 2 PTCIPE_PTCIPE3: .equ 3 ; Interrupt Pin Enable Bit 3 PTCIPE_PTCIPE4: .equ 4 ; Interrupt Pin Enable Bit 4 PTCIPE_PTCIPE5: .equ 5 ; Interrupt Pin Enable Bit 5 PTCIPE_PTCIPE6: .equ 6 ; Interrupt Pin Enable Bit 6 ; bit position masks mPTCIPE_PTCIPE0: .equ %00000001 mPTCIPE_PTCIPE1: .equ %00000010 mPTCIPE_PTCIPE2: .equ %00000100 mPTCIPE_PTCIPE3: .equ %00001000 mPTCIPE_PTCIPE4: .equ %00010000 mPTCIPE_PTCIPE5: .equ %00100000 mPTCIPE_PTCIPE6: .equ %01000000 ;*** PTCIF - Port C Interrupt Flag Register; 0xFFFF8127 *** PTCIF: .equ $FFFF8127 ;*** PTCIF - Port C Interrupt Flag Register; 0xFFFF8127 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTCIF_PTCIF0: .equ 0 ; Interrupt Flag Bit 0 PTCIF_PTCIF1: .equ 1 ; Interrupt Flag Bit 1 PTCIF_PTCIF2: .equ 2 ; Interrupt Flag Bit 2 PTCIF_PTCIF3: .equ 3 ; Interrupt Flag Bit 3 PTCIF_PTCIF4: .equ 4 ; Interrupt Flag Bit 4 PTCIF_PTCIF5: .equ 5 ; Interrupt Flag Bit 5 PTCIF_PTCIF6: .equ 6 ; Interrupt Flag Bit 6 ; bit position masks mPTCIF_PTCIF0: .equ %00000001 mPTCIF_PTCIF1: .equ %00000010 mPTCIF_PTCIF2: .equ %00000100 mPTCIF_PTCIF3: .equ %00001000 mPTCIF_PTCIF4: .equ %00010000 mPTCIF_PTCIF5: .equ %00100000 mPTCIF_PTCIF6: .equ %01000000 ;*** PTCIES - Port C Interrupt Edge Select Register; 0xFFFF8128 *** PTCIES: .equ $FFFF8128 ;*** PTCIES - Port C Interrupt Edge Select Register; 0xFFFF8128 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTCIES_PTCEDG0: .equ 0 ; Edge Selects of Pin Interrupt Bit 0 PTCIES_PTCEDG1: .equ 1 ; Edge Selects of Pin Interrupt Bit 1 PTCIES_PTCEDG2: .equ 2 ; Edge Selects of Pin Interrupt Bit 2 PTCIES_PTCEDG3: .equ 3 ; Edge Selects of Pin Interrupt Bit 3 PTCIES_PTCEDG4: .equ 4 ; Edge Selects of Pin Interrupt Bit 4 PTCIES_PTCEDG5: .equ 5 ; Edge Selects of Pin Interrupt Bit 5 PTCIES_PTCEDG6: .equ 6 ; Edge Selects of Pin Interrupt Bit 6 ; bit position masks mPTCIES_PTCEDG0: .equ %00000001 mPTCIES_PTCEDG1: .equ %00000010 mPTCIES_PTCEDG2: .equ %00000100 mPTCIES_PTCEDG3: .equ %00001000 mPTCIES_PTCEDG4: .equ %00010000 mPTCIES_PTCEDG5: .equ %00100000 mPTCIES_PTCEDG6: .equ %01000000 ;*** PTCDFE - Port C Digital Filter Enable Register; 0xFFFF8129 *** PTCDFE: .equ $FFFF8129 ;*** PTCDFE - Port C Digital Filter Enable Register; 0xFFFF8129 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTCDFE_PTCDFE0: .equ 0 ; Digital Filter Enable Bit 0 PTCDFE_PTCDFE1: .equ 1 ; Digital Filter Enable Bit 1 PTCDFE_PTCDFE2: .equ 2 ; Digital Filter Enable Bit 2 PTCDFE_PTCDFE3: .equ 3 ; Digital Filter Enable Bit 3 PTCDFE_PTCDFE4: .equ 4 ; Digital Filter Enable Bit 4 PTCDFE_PTCDFE5: .equ 5 ; Digital Filter Enable Bit 5 PTCDFE_PTCDFE6: .equ 6 ; Digital Filter Enable Bit 6 ; bit position masks mPTCDFE_PTCDFE0: .equ %00000001 mPTCDFE_PTCDFE1: .equ %00000010 mPTCDFE_PTCDFE2: .equ %00000100 mPTCDFE_PTCDFE3: .equ %00001000 mPTCDFE_PTCDFE4: .equ %00010000 mPTCDFE_PTCDFE5: .equ %00100000 mPTCDFE_PTCDFE6: .equ %01000000 ;*** PTCDFC - Port C Digital Filter Control Register; 0xFFFF812A *** PTCDFC: .equ $FFFF812A ;*** PTCDFC - Port C Digital Filter Control Register; 0xFFFF812A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTCDFC_PTCFF0: .equ 0 ; Filter Factor Bits, bit 0 PTCDFC_PTCFF1: .equ 1 ; Filter Factor Bits, bit 1 PTCDFC_PTCFF2: .equ 2 ; Filter Factor Bits, bit 2 PTCDFC_PTCFF3: .equ 3 ; Filter Factor Bits, bit 3 PTCDFC_PTCFF4: .equ 4 ; Filter Factor Bits, bit 4 PTCDFC_PTCCLKS: .equ 7 ; Clok Select Bit ; bit position masks mPTCDFC_PTCFF0: .equ %00000001 mPTCDFC_PTCFF1: .equ %00000010 mPTCDFC_PTCFF2: .equ %00000100 mPTCDFC_PTCFF3: .equ %00001000 mPTCDFC_PTCFF4: .equ %00010000 mPTCDFC_PTCCLKS: .equ %10000000 ;*** PTDPUE - Port D Pulling Enable Register; 0xFFFF8130 *** PTDPUE: .equ $FFFF8130 ;*** PTDPUE - Port D Pulling Enable Register; 0xFFFF8130 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTDPUE_PTDPUE0: .equ 0 ; Internal Pulling Enable for Port D Bit 0 PTDPUE_PTDPUE1: .equ 1 ; Internal Pulling Enable for Port D Bit 1 PTDPUE_PTDPUE2: .equ 2 ; Internal Pulling Enable for Port D Bit 2 PTDPUE_PTDPUE3: .equ 3 ; Internal Pulling Enable for Port D Bit 3 PTDPUE_PTDPUE4: .equ 4 ; Internal Pulling Enable for Port D Bit 4 PTDPUE_PTDPUE5: .equ 5 ; Internal Pulling Enable for Port D Bit 5 PTDPUE_PTDPUE6: .equ 6 ; Internal Pulling Enable for Port D Bit 6 PTDPUE_PTDPUE7: .equ 7 ; Internal Pulling Enable for Port D Bit 7 ; bit position masks mPTDPUE_PTDPUE0: .equ %00000001 mPTDPUE_PTDPUE1: .equ %00000010 mPTDPUE_PTDPUE2: .equ %00000100 mPTDPUE_PTDPUE3: .equ %00001000 mPTDPUE_PTDPUE4: .equ %00010000 mPTDPUE_PTDPUE5: .equ %00100000 mPTDPUE_PTDPUE6: .equ %01000000 mPTDPUE_PTDPUE7: .equ %10000000 ;*** PTDPUS - Port D Pullup/Pulldown Select Register; 0xFFFF8131 *** PTDPUS: .equ $FFFF8131 ;*** PTDPUS - Port D Pullup/Pulldown Select Register; 0xFFFF8131 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTDPUS_PTDPUS0: .equ 0 ; Pullup/Pulldown Select Bit 0 PTDPUS_PTDPUS1: .equ 1 ; Pullup/Pulldown Select Bit 1 PTDPUS_PTDPUS2: .equ 2 ; Pullup/Pulldown Select Bit 2 PTDPUS_PTDPUS3: .equ 3 ; Pullup/Pulldown Select Bit 3 PTDPUS_PTDPUS4: .equ 4 ; Pullup/Pulldown Select Bit 4 PTDPUS_PTDPUS5: .equ 5 ; Pullup/Pulldown Select Bit 5 PTDPUS_PTDPUS6: .equ 6 ; Pullup/Pulldown Select Bit 6 PTDPUS_PTDPUS7: .equ 7 ; Pullup/Pulldown Select Bit 7 ; bit position masks mPTDPUS_PTDPUS0: .equ %00000001 mPTDPUS_PTDPUS1: .equ %00000010 mPTDPUS_PTDPUS2: .equ %00000100 mPTDPUS_PTDPUS3: .equ %00001000 mPTDPUS_PTDPUS4: .equ %00010000 mPTDPUS_PTDPUS5: .equ %00100000 mPTDPUS_PTDPUS6: .equ %01000000 mPTDPUS_PTDPUS7: .equ %10000000 ;*** PTDDS - Port D Drive Strength Selection Register; 0xFFFF8132 *** PTDDS: .equ $FFFF8132 ;*** PTDDS - Port D Drive Strength Selection Register; 0xFFFF8132 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTDDS_PTDDS0: .equ 0 ; Output Drive Strength Selection for Port D Bit 0 PTDDS_PTDDS1: .equ 1 ; Output Drive Strength Selection for Port D Bit 1 PTDDS_PTDDS2: .equ 2 ; Output Drive Strength Selection for Port D Bit 2 PTDDS_PTDDS3: .equ 3 ; Output Drive Strength Selection for Port D Bit 3 PTDDS_PTDDS4: .equ 4 ; Output Drive Strength Selection for Port D Bit 4 PTDDS_PTDDS5: .equ 5 ; Output Drive Strength Selection for Port D Bit 5 PTDDS_PTDDS6: .equ 6 ; Output Drive Strength Selection for Port D Bit 6 PTDDS_PTDDS7: .equ 7 ; Output Drive Strength Selection for Port D Bit 7 ; bit position masks mPTDDS_PTDDS0: .equ %00000001 mPTDDS_PTDDS1: .equ %00000010 mPTDDS_PTDDS2: .equ %00000100 mPTDDS_PTDDS3: .equ %00001000 mPTDDS_PTDDS4: .equ %00010000 mPTDDS_PTDDS5: .equ %00100000 mPTDDS_PTDDS6: .equ %01000000 mPTDDS_PTDDS7: .equ %10000000 ;*** PTDSRE - Port D Slew Rate Enable Register; 0xFFFF8133 *** PTDSRE: .equ $FFFF8133 ;*** PTDSRE - Port D Slew Rate Enable Register; 0xFFFF8133 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTDSRE_PTDSRE0: .equ 0 ; Output Slew Rate Enable for Port D Bit 0 PTDSRE_PTDSRE1: .equ 1 ; Output Slew Rate Enable for Port D Bit 1 PTDSRE_PTDSRE2: .equ 2 ; Output Slew Rate Enable for Port D Bit 2 PTDSRE_PTDSRE3: .equ 3 ; Output Slew Rate Enable for Port D Bit 3 PTDSRE_PTDSRE4: .equ 4 ; Output Slew Rate Enable for Port D Bit 4 PTDSRE_PTDSRE5: .equ 5 ; Output Slew Rate Enable for Port D Bit 5 PTDSRE_PTDSRE6: .equ 6 ; Output Slew Rate Enable for Port D Bit 6 PTDSRE_PTDSRE7: .equ 7 ; Output Slew Rate Enable for Port D Bit 7 ; bit position masks mPTDSRE_PTDSRE0: .equ %00000001 mPTDSRE_PTDSRE1: .equ %00000010 mPTDSRE_PTDSRE2: .equ %00000100 mPTDSRE_PTDSRE3: .equ %00001000 mPTDSRE_PTDSRE4: .equ %00010000 mPTDSRE_PTDSRE5: .equ %00100000 mPTDSRE_PTDSRE6: .equ %01000000 mPTDSRE_PTDSRE7: .equ %10000000 ;*** PTDPFE - Port D Passive Filter Enable Register; 0xFFFF8134 *** PTDPFE: .equ $FFFF8134 ;*** PTDPFE - Port D Passive Filter Enable Register; 0xFFFF8134 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTDPFE_PTDPFE0: .equ 0 ; Port A Input Filter Enable Bit 0 PTDPFE_PTDPFE1: .equ 1 ; Port A Input Filter Enable Bit 1 PTDPFE_PTDPFE2: .equ 2 ; Port A Input Filter Enable Bit 2 PTDPFE_PTDPFE3: .equ 3 ; Port A Input Filter Enable Bit 3 PTDPFE_PTDPFE4: .equ 4 ; Port A Input Filter Enable Bit 4 PTDPFE_PTDPFE5: .equ 5 ; Port A Input Filter Enable Bit 5 PTDPFE_PTDPFE6: .equ 6 ; Port A Input Filter Enable Bit 6 PTDPFE_PTDPFE7: .equ 7 ; Port A Input Filter Enable Bit 7 ; bit position masks mPTDPFE_PTDPFE0: .equ %00000001 mPTDPFE_PTDPFE1: .equ %00000010 mPTDPFE_PTDPFE2: .equ %00000100 mPTDPFE_PTDPFE3: .equ %00001000 mPTDPFE_PTDPFE4: .equ %00010000 mPTDPFE_PTDPFE5: .equ %00100000 mPTDPFE_PTDPFE6: .equ %01000000 mPTDPFE_PTDPFE7: .equ %10000000 ;*** PTDIC - Port D Interrupt Control Register; 0xFFFF8135 *** PTDIC: .equ $FFFF8135 ;*** PTDIC - Port D Interrupt Control Register; 0xFFFF8135 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTDIC_PTDMOD: .equ 0 ; Detection Mode for Pin Interrupt PTDIC_PTDIE: .equ 1 ; Interrupt Enable PTDIC_PTDDMAEN: .equ 7 ; DMA Enable bit ; bit position masks mPTDIC_PTDMOD: .equ %00000001 mPTDIC_PTDIE: .equ %00000010 mPTDIC_PTDDMAEN: .equ %10000000 ;*** PTDIPE - Port D Interrupt Pin Enable Register; 0xFFFF8136 *** PTDIPE: .equ $FFFF8136 ;*** PTDIPE - Port D Interrupt Pin Enable Register; 0xFFFF8136 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTDIPE_PTDIPE0: .equ 0 ; Interrupt Pin Enable Bit 0 PTDIPE_PTDIPE1: .equ 1 ; Interrupt Pin Enable Bit 1 PTDIPE_PTDIPE2: .equ 2 ; Interrupt Pin Enable Bit 2 PTDIPE_PTDIPE3: .equ 3 ; Interrupt Pin Enable Bit 3 PTDIPE_PTDIPE4: .equ 4 ; Interrupt Pin Enable Bit 4 PTDIPE_PTDIPE5: .equ 5 ; Interrupt Pin Enable Bit 5 PTDIPE_PTDIPE6: .equ 6 ; Interrupt Pin Enable Bit 6 PTDIPE_PTDIPE7: .equ 7 ; Interrupt Pin Enable Bit 7 ; bit position masks mPTDIPE_PTDIPE0: .equ %00000001 mPTDIPE_PTDIPE1: .equ %00000010 mPTDIPE_PTDIPE2: .equ %00000100 mPTDIPE_PTDIPE3: .equ %00001000 mPTDIPE_PTDIPE4: .equ %00010000 mPTDIPE_PTDIPE5: .equ %00100000 mPTDIPE_PTDIPE6: .equ %01000000 mPTDIPE_PTDIPE7: .equ %10000000 ;*** PTDIF - Port D Interrupt Flag Register; 0xFFFF8137 *** PTDIF: .equ $FFFF8137 ;*** PTDIF - Port D Interrupt Flag Register; 0xFFFF8137 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTDIF_PTDIF0: .equ 0 ; Interrupt Flag Bit 0 PTDIF_PTDIF1: .equ 1 ; Interrupt Flag Bit 1 PTDIF_PTDIF2: .equ 2 ; Interrupt Flag Bit 2 PTDIF_PTDIF3: .equ 3 ; Interrupt Flag Bit 3 PTDIF_PTDIF4: .equ 4 ; Interrupt Flag Bit 4 PTDIF_PTDIF5: .equ 5 ; Interrupt Flag Bit 5 PTDIF_PTDIF6: .equ 6 ; Interrupt Flag Bit 6 PTDIF_PTDIF7: .equ 7 ; Interrupt Flag Bit 7 ; bit position masks mPTDIF_PTDIF0: .equ %00000001 mPTDIF_PTDIF1: .equ %00000010 mPTDIF_PTDIF2: .equ %00000100 mPTDIF_PTDIF3: .equ %00001000 mPTDIF_PTDIF4: .equ %00010000 mPTDIF_PTDIF5: .equ %00100000 mPTDIF_PTDIF6: .equ %01000000 mPTDIF_PTDIF7: .equ %10000000 ;*** PTDIES - Port D Interrupt Edge Select Register; 0xFFFF8138 *** PTDIES: .equ $FFFF8138 ;*** PTDIES - Port D Interrupt Edge Select Register; 0xFFFF8138 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTDIES_PTDEDG0: .equ 0 ; Edge Selects of Pin Interrupt Bit 0 PTDIES_PTDEDG1: .equ 1 ; Edge Selects of Pin Interrupt Bit 1 PTDIES_PTDEDG2: .equ 2 ; Edge Selects of Pin Interrupt Bit 2 PTDIES_PTDEDG3: .equ 3 ; Edge Selects of Pin Interrupt Bit 3 PTDIES_PTDEDG4: .equ 4 ; Edge Selects of Pin Interrupt Bit 4 PTDIES_PTDEDG5: .equ 5 ; Edge Selects of Pin Interrupt Bit 5 PTDIES_PTDEDG6: .equ 6 ; Edge Selects of Pin Interrupt Bit 6 PTDIES_PTDEDG7: .equ 7 ; Edge Selects of Pin Interrupt Bit 7 ; bit position masks mPTDIES_PTDEDG0: .equ %00000001 mPTDIES_PTDEDG1: .equ %00000010 mPTDIES_PTDEDG2: .equ %00000100 mPTDIES_PTDEDG3: .equ %00001000 mPTDIES_PTDEDG4: .equ %00010000 mPTDIES_PTDEDG5: .equ %00100000 mPTDIES_PTDEDG6: .equ %01000000 mPTDIES_PTDEDG7: .equ %10000000 ;*** PTDDFE - Port D Digital Filter Enable Register; 0xFFFF8139 *** PTDDFE: .equ $FFFF8139 ;*** PTDDFE - Port D Digital Filter Enable Register; 0xFFFF8139 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTDDFE_PTDDFE0: .equ 0 ; Digital Filter Enable Bit 0 PTDDFE_PTDDFE1: .equ 1 ; Digital Filter Enable Bit 1 PTDDFE_PTDDFE2: .equ 2 ; Digital Filter Enable Bit 2 PTDDFE_PTDDFE3: .equ 3 ; Digital Filter Enable Bit 3 PTDDFE_PTDDFE4: .equ 4 ; Digital Filter Enable Bit 4 PTDDFE_PTDDFE5: .equ 5 ; Digital Filter Enable Bit 5 PTDDFE_PTDDFE6: .equ 6 ; Digital Filter Enable Bit 6 PTDDFE_PTDDFE7: .equ 7 ; Digital Filter Enable Bit 7 ; bit position masks mPTDDFE_PTDDFE0: .equ %00000001 mPTDDFE_PTDDFE1: .equ %00000010 mPTDDFE_PTDDFE2: .equ %00000100 mPTDDFE_PTDDFE3: .equ %00001000 mPTDDFE_PTDDFE4: .equ %00010000 mPTDDFE_PTDDFE5: .equ %00100000 mPTDDFE_PTDDFE6: .equ %01000000 mPTDDFE_PTDDFE7: .equ %10000000 ;*** PTDDFC - Port D Digital Filter Control Register; 0xFFFF813A *** PTDDFC: .equ $FFFF813A ;*** PTDDFC - Port D Digital Filter Control Register; 0xFFFF813A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTDDFC_PTDFF0: .equ 0 ; Filter Factor Bits, bit 0 PTDDFC_PTDFF1: .equ 1 ; Filter Factor Bits, bit 1 PTDDFC_PTDFF2: .equ 2 ; Filter Factor Bits, bit 2 PTDDFC_PTDFF3: .equ 3 ; Filter Factor Bits, bit 3 PTDDFC_PTDFF4: .equ 4 ; Filter Factor Bits, bit 4 PTDDFC_PTDCLKS: .equ 7 ; Clok Select Bit ; bit position masks mPTDDFC_PTDFF0: .equ %00000001 mPTDDFC_PTDFF1: .equ %00000010 mPTDDFC_PTDFF2: .equ %00000100 mPTDDFC_PTDFF3: .equ %00001000 mPTDDFC_PTDFF4: .equ %00010000 mPTDDFC_PTDCLKS: .equ %10000000 ;*** PTEPUE - Port E Pulling Enable Register; 0xFFFF8140 *** PTEPUE: .equ $FFFF8140 ;*** PTEPUE - Port E Pulling Enable Register; 0xFFFF8140 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTEPUE_PTEPUE0: .equ 0 ; Internal Pulling Enable for Port E Bit 0 PTEPUE_PTEPUE1: .equ 1 ; Internal Pulling Enable for Port E Bit 1 PTEPUE_PTEPUE2: .equ 2 ; Internal Pulling Enable for Port E Bit 2 PTEPUE_PTEPUE3: .equ 3 ; Internal Pulling Enable for Port E Bit 3 PTEPUE_PTEPUE4: .equ 4 ; Internal Pulling Enable for Port E Bit 4 PTEPUE_PTEPUE5: .equ 5 ; Internal Pulling Enable for Port E Bit 5 PTEPUE_PTEPUE6: .equ 6 ; Internal Pulling Enable for Port E Bit 6 PTEPUE_PTEPUE7: .equ 7 ; Internal Pulling Enable for Port E Bit 7 ; bit position masks mPTEPUE_PTEPUE0: .equ %00000001 mPTEPUE_PTEPUE1: .equ %00000010 mPTEPUE_PTEPUE2: .equ %00000100 mPTEPUE_PTEPUE3: .equ %00001000 mPTEPUE_PTEPUE4: .equ %00010000 mPTEPUE_PTEPUE5: .equ %00100000 mPTEPUE_PTEPUE6: .equ %01000000 mPTEPUE_PTEPUE7: .equ %10000000 ;*** PTEPUS - Port E Pullup/Pulldown Select Register; 0xFFFF8141 *** PTEPUS: .equ $FFFF8141 ;*** PTEPUS - Port E Pullup/Pulldown Select Register; 0xFFFF8141 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTEPUS_PTEPUS0: .equ 0 ; Pullup/Pulldown Select Bit 0 PTEPUS_PTEPUS1: .equ 1 ; Pullup/Pulldown Select Bit 1 PTEPUS_PTEPUS2: .equ 2 ; Pullup/Pulldown Select Bit 2 PTEPUS_PTEPUS3: .equ 3 ; Pullup/Pulldown Select Bit 3 PTEPUS_PTEPUS4: .equ 4 ; Pullup/Pulldown Select Bit 4 PTEPUS_PTEPUS5: .equ 5 ; Pullup/Pulldown Select Bit 5 PTEPUS_PTEPUS6: .equ 6 ; Pullup/Pulldown Select Bit 6 PTEPUS_PTEPUS7: .equ 7 ; Pullup/Pulldown Select Bit 7 ; bit position masks mPTEPUS_PTEPUS0: .equ %00000001 mPTEPUS_PTEPUS1: .equ %00000010 mPTEPUS_PTEPUS2: .equ %00000100 mPTEPUS_PTEPUS3: .equ %00001000 mPTEPUS_PTEPUS4: .equ %00010000 mPTEPUS_PTEPUS5: .equ %00100000 mPTEPUS_PTEPUS6: .equ %01000000 mPTEPUS_PTEPUS7: .equ %10000000 ;*** PTEDS - Port E Drive Strength Selection Register; 0xFFFF8142 *** PTEDS: .equ $FFFF8142 ;*** PTEDS - Port E Drive Strength Selection Register; 0xFFFF8142 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTEDS_PTEDS0: .equ 0 ; Output Drive Strength Selection for Port E Bit 0 PTEDS_PTEDS1: .equ 1 ; Output Drive Strength Selection for Port E Bit 1 PTEDS_PTEDS2: .equ 2 ; Output Drive Strength Selection for Port E Bit 2 PTEDS_PTEDS3: .equ 3 ; Output Drive Strength Selection for Port E Bit 3 PTEDS_PTEDS4: .equ 4 ; Output Drive Strength Selection for Port E Bit 4 PTEDS_PTEDS5: .equ 5 ; Output Drive Strength Selection for Port E Bit 5 PTEDS_PTEDS6: .equ 6 ; Output Drive Strength Selection for Port E Bit 6 PTEDS_PTEDS7: .equ 7 ; Output Drive Strength Selection for Port E Bit 7 ; bit position masks mPTEDS_PTEDS0: .equ %00000001 mPTEDS_PTEDS1: .equ %00000010 mPTEDS_PTEDS2: .equ %00000100 mPTEDS_PTEDS3: .equ %00001000 mPTEDS_PTEDS4: .equ %00010000 mPTEDS_PTEDS5: .equ %00100000 mPTEDS_PTEDS6: .equ %01000000 mPTEDS_PTEDS7: .equ %10000000 ;*** PTESRE - Port E Slew Rate Enable Register; 0xFFFF8143 *** PTESRE: .equ $FFFF8143 ;*** PTESRE - Port E Slew Rate Enable Register; 0xFFFF8143 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTESRE_PTESRE0: .equ 0 ; Output Slew Rate Enable for Port E Bit 0 PTESRE_PTESRE1: .equ 1 ; Output Slew Rate Enable for Port E Bit 1 PTESRE_PTESRE2: .equ 2 ; Output Slew Rate Enable for Port E Bit 2 PTESRE_PTESRE3: .equ 3 ; Output Slew Rate Enable for Port E Bit 3 PTESRE_PTESRE4: .equ 4 ; Output Slew Rate Enable for Port E Bit 4 PTESRE_PTESRE5: .equ 5 ; Output Slew Rate Enable for Port E Bit 5 PTESRE_PTESRE6: .equ 6 ; Output Slew Rate Enable for Port E Bit 6 PTESRE_PTESRE7: .equ 7 ; Output Slew Rate Enable for Port E Bit 7 ; bit position masks mPTESRE_PTESRE0: .equ %00000001 mPTESRE_PTESRE1: .equ %00000010 mPTESRE_PTESRE2: .equ %00000100 mPTESRE_PTESRE3: .equ %00001000 mPTESRE_PTESRE4: .equ %00010000 mPTESRE_PTESRE5: .equ %00100000 mPTESRE_PTESRE6: .equ %01000000 mPTESRE_PTESRE7: .equ %10000000 ;*** PTEPFE - Port E Passive Filter Enable Register; 0xFFFF8144 *** PTEPFE: .equ $FFFF8144 ;*** PTEPFE - Port E Passive Filter Enable Register; 0xFFFF8144 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTEPFE_PTEPFE0: .equ 0 ; Port A Input Filter Enable Bit 0 PTEPFE_PTEPFE1: .equ 1 ; Port A Input Filter Enable Bit 1 PTEPFE_PTEPFE2: .equ 2 ; Port A Input Filter Enable Bit 2 PTEPFE_PTEPFE3: .equ 3 ; Port A Input Filter Enable Bit 3 PTEPFE_PTEPFE4: .equ 4 ; Port A Input Filter Enable Bit 4 PTEPFE_PTEPFE5: .equ 5 ; Port A Input Filter Enable Bit 5 PTEPFE_PTEPFE6: .equ 6 ; Port A Input Filter Enable Bit 6 PTEPFE_PTEPFE7: .equ 7 ; Port A Input Filter Enable Bit 7 ; bit position masks mPTEPFE_PTEPFE0: .equ %00000001 mPTEPFE_PTEPFE1: .equ %00000010 mPTEPFE_PTEPFE2: .equ %00000100 mPTEPFE_PTEPFE3: .equ %00001000 mPTEPFE_PTEPFE4: .equ %00010000 mPTEPFE_PTEPFE5: .equ %00100000 mPTEPFE_PTEPFE6: .equ %01000000 mPTEPFE_PTEPFE7: .equ %10000000 ;*** PTEIC - Port E Interrupt Control Register; 0xFFFF8145 *** PTEIC: .equ $FFFF8145 ;*** PTEIC - Port E Interrupt Control Register; 0xFFFF8145 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTEIC_PTEMOD: .equ 0 ; Detection Mode for Pin Interrupt PTEIC_PTEIE: .equ 1 ; Interrupt Enable PTEIC_PTEDMAEN: .equ 7 ; DMA Enable bit ; bit position masks mPTEIC_PTEMOD: .equ %00000001 mPTEIC_PTEIE: .equ %00000010 mPTEIC_PTEDMAEN: .equ %10000000 ;*** PTEIPE - Port E Interrupt Pin Enable Register; 0xFFFF8146 *** PTEIPE: .equ $FFFF8146 ;*** PTEIPE - Port E Interrupt Pin Enable Register; 0xFFFF8146 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTEIPE_PTEIPE0: .equ 0 ; Interrupt Pin Enable Bit 0 PTEIPE_PTEIPE1: .equ 1 ; Interrupt Pin Enable Bit 1 PTEIPE_PTEIPE2: .equ 2 ; Interrupt Pin Enable Bit 2 PTEIPE_PTEIPE3: .equ 3 ; Interrupt Pin Enable Bit 3 PTEIPE_PTEIPE4: .equ 4 ; Interrupt Pin Enable Bit 4 PTEIPE_PTEIPE5: .equ 5 ; Interrupt Pin Enable Bit 5 PTEIPE_PTEIPE6: .equ 6 ; Interrupt Pin Enable Bit 6 PTEIPE_PTEIPE7: .equ 7 ; Interrupt Pin Enable Bit 7 ; bit position masks mPTEIPE_PTEIPE0: .equ %00000001 mPTEIPE_PTEIPE1: .equ %00000010 mPTEIPE_PTEIPE2: .equ %00000100 mPTEIPE_PTEIPE3: .equ %00001000 mPTEIPE_PTEIPE4: .equ %00010000 mPTEIPE_PTEIPE5: .equ %00100000 mPTEIPE_PTEIPE6: .equ %01000000 mPTEIPE_PTEIPE7: .equ %10000000 ;*** PTEIF - Port E Interrupt Flag Register; 0xFFFF8147 *** PTEIF: .equ $FFFF8147 ;*** PTEIF - Port E Interrupt Flag Register; 0xFFFF8147 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTEIF_PTEIF0: .equ 0 ; Interrupt Flag Bit 0 PTEIF_PTEIF1: .equ 1 ; Interrupt Flag Bit 1 PTEIF_PTEIF2: .equ 2 ; Interrupt Flag Bit 2 PTEIF_PTEIF3: .equ 3 ; Interrupt Flag Bit 3 PTEIF_PTEIF4: .equ 4 ; Interrupt Flag Bit 4 PTEIF_PTEIF5: .equ 5 ; Interrupt Flag Bit 5 PTEIF_PTEIF6: .equ 6 ; Interrupt Flag Bit 6 PTEIF_PTEIF7: .equ 7 ; Interrupt Flag Bit 7 ; bit position masks mPTEIF_PTEIF0: .equ %00000001 mPTEIF_PTEIF1: .equ %00000010 mPTEIF_PTEIF2: .equ %00000100 mPTEIF_PTEIF3: .equ %00001000 mPTEIF_PTEIF4: .equ %00010000 mPTEIF_PTEIF5: .equ %00100000 mPTEIF_PTEIF6: .equ %01000000 mPTEIF_PTEIF7: .equ %10000000 ;*** PTEIES - Port E Interrupt Edge Select Register; 0xFFFF8148 *** PTEIES: .equ $FFFF8148 ;*** PTEIES - Port E Interrupt Edge Select Register; 0xFFFF8148 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTEIES_PTEEDG0: .equ 0 ; Edge Selects of Pin Interrupt Bit 0 PTEIES_PTEEDG1: .equ 1 ; Edge Selects of Pin Interrupt Bit 1 PTEIES_PTEEDG2: .equ 2 ; Edge Selects of Pin Interrupt Bit 2 PTEIES_PTEEDG3: .equ 3 ; Edge Selects of Pin Interrupt Bit 3 PTEIES_PTEEDG4: .equ 4 ; Edge Selects of Pin Interrupt Bit 4 PTEIES_PTEEDG5: .equ 5 ; Edge Selects of Pin Interrupt Bit 5 PTEIES_PTEEDG6: .equ 6 ; Edge Selects of Pin Interrupt Bit 6 PTEIES_PTEEDG7: .equ 7 ; Edge Selects of Pin Interrupt Bit 7 ; bit position masks mPTEIES_PTEEDG0: .equ %00000001 mPTEIES_PTEEDG1: .equ %00000010 mPTEIES_PTEEDG2: .equ %00000100 mPTEIES_PTEEDG3: .equ %00001000 mPTEIES_PTEEDG4: .equ %00010000 mPTEIES_PTEEDG5: .equ %00100000 mPTEIES_PTEEDG6: .equ %01000000 mPTEIES_PTEEDG7: .equ %10000000 ;*** PTEDFE - Port E Digital Filter Enable Register; 0xFFFF8149 *** PTEDFE: .equ $FFFF8149 ;*** PTEDFE - Port E Digital Filter Enable Register; 0xFFFF8149 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTEDFE_PTEDFE0: .equ 0 ; Digital Filter Enable Bit 0 PTEDFE_PTEDFE1: .equ 1 ; Digital Filter Enable Bit 1 PTEDFE_PTEDFE2: .equ 2 ; Digital Filter Enable Bit 2 PTEDFE_PTEDFE3: .equ 3 ; Digital Filter Enable Bit 3 PTEDFE_PTEDFE4: .equ 4 ; Digital Filter Enable Bit 4 PTEDFE_PTEDFE5: .equ 5 ; Digital Filter Enable Bit 5 PTEDFE_PTEDFE6: .equ 6 ; Digital Filter Enable Bit 6 PTEDFE_PTEDFE7: .equ 7 ; Digital Filter Enable Bit 7 ; bit position masks mPTEDFE_PTEDFE0: .equ %00000001 mPTEDFE_PTEDFE1: .equ %00000010 mPTEDFE_PTEDFE2: .equ %00000100 mPTEDFE_PTEDFE3: .equ %00001000 mPTEDFE_PTEDFE4: .equ %00010000 mPTEDFE_PTEDFE5: .equ %00100000 mPTEDFE_PTEDFE6: .equ %01000000 mPTEDFE_PTEDFE7: .equ %10000000 ;*** PTEDFC - Port E Digital Filter Control Register; 0xFFFF814A *** PTEDFC: .equ $FFFF814A ;*** PTEDFC - Port E Digital Filter Control Register; 0xFFFF814A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTEDFC_PTEFF0: .equ 0 ; Filter Factor Bits, bit 0 PTEDFC_PTEFF1: .equ 1 ; Filter Factor Bits, bit 1 PTEDFC_PTEFF2: .equ 2 ; Filter Factor Bits, bit 2 PTEDFC_PTEFF3: .equ 3 ; Filter Factor Bits, bit 3 PTEDFC_PTEFF4: .equ 4 ; Filter Factor Bits, bit 4 PTEDFC_PTECLKS: .equ 7 ; Clok Select Bit ; bit position masks mPTEDFC_PTEFF0: .equ %00000001 mPTEDFC_PTEFF1: .equ %00000010 mPTEDFC_PTEFF2: .equ %00000100 mPTEDFC_PTEFF3: .equ %00001000 mPTEDFC_PTEFF4: .equ %00010000 mPTEDFC_PTECLKS: .equ %10000000 ;*** PTFPUE - Port F Pulling Enable Register; 0xFFFF8150 *** PTFPUE: .equ $FFFF8150 ;*** PTFPUE - Port F Pulling Enable Register; 0xFFFF8150 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTFPUE_PTFPUE0: .equ 0 ; Internal Pulling Enable for Port F Bit 0 PTFPUE_PTFPUE1: .equ 1 ; Internal Pulling Enable for Port F Bit 1 PTFPUE_PTFPUE2: .equ 2 ; Internal Pulling Enable for Port F Bit 2 PTFPUE_PTFPUE3: .equ 3 ; Internal Pulling Enable for Port F Bit 3 PTFPUE_PTFPUE4: .equ 4 ; Internal Pulling Enable for Port F Bit 4 PTFPUE_PTFPUE5: .equ 5 ; Internal Pulling Enable for Port F Bit 5 PTFPUE_PTFPUE6: .equ 6 ; Internal Pulling Enable for Port F Bit 6 PTFPUE_PTFPUE7: .equ 7 ; Internal Pulling Enable for Port F Bit 7 ; bit position masks mPTFPUE_PTFPUE0: .equ %00000001 mPTFPUE_PTFPUE1: .equ %00000010 mPTFPUE_PTFPUE2: .equ %00000100 mPTFPUE_PTFPUE3: .equ %00001000 mPTFPUE_PTFPUE4: .equ %00010000 mPTFPUE_PTFPUE5: .equ %00100000 mPTFPUE_PTFPUE6: .equ %01000000 mPTFPUE_PTFPUE7: .equ %10000000 ;*** PTFPUS - Port F Pullup/Pulldown Select Register; 0xFFFF8151 *** PTFPUS: .equ $FFFF8151 ;*** PTFPUS - Port F Pullup/Pulldown Select Register; 0xFFFF8151 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTFPUS_PTFPUS0: .equ 0 ; Pullup/Pulldown Select Bit 0 PTFPUS_PTFPUS1: .equ 1 ; Pullup/Pulldown Select Bit 1 PTFPUS_PTFPUS2: .equ 2 ; Pullup/Pulldown Select Bit 2 PTFPUS_PTFPUS3: .equ 3 ; Pullup/Pulldown Select Bit 3 PTFPUS_PTFPUS4: .equ 4 ; Pullup/Pulldown Select Bit 4 PTFPUS_PTFPUS5: .equ 5 ; Pullup/Pulldown Select Bit 5 PTFPUS_PTFPUS6: .equ 6 ; Pullup/Pulldown Select Bit 6 PTFPUS_PTFPUS7: .equ 7 ; Pullup/Pulldown Select Bit 7 ; bit position masks mPTFPUS_PTFPUS0: .equ %00000001 mPTFPUS_PTFPUS1: .equ %00000010 mPTFPUS_PTFPUS2: .equ %00000100 mPTFPUS_PTFPUS3: .equ %00001000 mPTFPUS_PTFPUS4: .equ %00010000 mPTFPUS_PTFPUS5: .equ %00100000 mPTFPUS_PTFPUS6: .equ %01000000 mPTFPUS_PTFPUS7: .equ %10000000 ;*** PTFDS - Port F Drive Strength Selection Register; 0xFFFF8152 *** PTFDS: .equ $FFFF8152 ;*** PTFDS - Port F Drive Strength Selection Register; 0xFFFF8152 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTFDS_PTFDS0: .equ 0 ; Output Drive Strength Selection for Port F Bit 0 PTFDS_PTFDS1: .equ 1 ; Output Drive Strength Selection for Port F Bit 1 PTFDS_PTFDS2: .equ 2 ; Output Drive Strength Selection for Port F Bit 2 PTFDS_PTFDS3: .equ 3 ; Output Drive Strength Selection for Port F Bit 3 PTFDS_PTFDS4: .equ 4 ; Output Drive Strength Selection for Port F Bit 4 PTFDS_PTFDS5: .equ 5 ; Output Drive Strength Selection for Port F Bit 5 PTFDS_PTFDS6: .equ 6 ; Output Drive Strength Selection for Port F Bit 6 PTFDS_PTFDS7: .equ 7 ; Output Drive Strength Selection for Port F Bit 7 ; bit position masks mPTFDS_PTFDS0: .equ %00000001 mPTFDS_PTFDS1: .equ %00000010 mPTFDS_PTFDS2: .equ %00000100 mPTFDS_PTFDS3: .equ %00001000 mPTFDS_PTFDS4: .equ %00010000 mPTFDS_PTFDS5: .equ %00100000 mPTFDS_PTFDS6: .equ %01000000 mPTFDS_PTFDS7: .equ %10000000 ;*** PTFSRE - Port F Slew Rate Enable Register; 0xFFFF8153 *** PTFSRE: .equ $FFFF8153 ;*** PTFSRE - Port F Slew Rate Enable Register; 0xFFFF8153 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTFSRE_PTFSRE0: .equ 0 ; Output Slew Rate Enable for Port F Bit 0 PTFSRE_PTFSRE1: .equ 1 ; Output Slew Rate Enable for Port F Bit 1 PTFSRE_PTFSRE2: .equ 2 ; Output Slew Rate Enable for Port F Bit 2 PTFSRE_PTFSRE3: .equ 3 ; Output Slew Rate Enable for Port F Bit 3 PTFSRE_PTFSRE4: .equ 4 ; Output Slew Rate Enable for Port F Bit 4 PTFSRE_PTFSRE5: .equ 5 ; Output Slew Rate Enable for Port F Bit 5 PTFSRE_PTFSRE6: .equ 6 ; Output Slew Rate Enable for Port F Bit 6 PTFSRE_PTFSRE7: .equ 7 ; Output Slew Rate Enable for Port F Bit 7 ; bit position masks mPTFSRE_PTFSRE0: .equ %00000001 mPTFSRE_PTFSRE1: .equ %00000010 mPTFSRE_PTFSRE2: .equ %00000100 mPTFSRE_PTFSRE3: .equ %00001000 mPTFSRE_PTFSRE4: .equ %00010000 mPTFSRE_PTFSRE5: .equ %00100000 mPTFSRE_PTFSRE6: .equ %01000000 mPTFSRE_PTFSRE7: .equ %10000000 ;*** PTFPFE - Port F Passive Filter Enable Register; 0xFFFF8154 *** PTFPFE: .equ $FFFF8154 ;*** PTFPFE - Port F Passive Filter Enable Register; 0xFFFF8154 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTFPFE_PTFPFE0: .equ 0 ; Port A Input Filter Enable Bit 0 PTFPFE_PTFPFE1: .equ 1 ; Port A Input Filter Enable Bit 1 PTFPFE_PTFPFE2: .equ 2 ; Port A Input Filter Enable Bit 2 PTFPFE_PTFPFE3: .equ 3 ; Port A Input Filter Enable Bit 3 PTFPFE_PTFPFE4: .equ 4 ; Port A Input Filter Enable Bit 4 PTFPFE_PTFPFE5: .equ 5 ; Port A Input Filter Enable Bit 5 PTFPFE_PTFPFE6: .equ 6 ; Port A Input Filter Enable Bit 6 PTFPFE_PTFPFE7: .equ 7 ; Port A Input Filter Enable Bit 7 ; bit position masks mPTFPFE_PTFPFE0: .equ %00000001 mPTFPFE_PTFPFE1: .equ %00000010 mPTFPFE_PTFPFE2: .equ %00000100 mPTFPFE_PTFPFE3: .equ %00001000 mPTFPFE_PTFPFE4: .equ %00010000 mPTFPFE_PTFPFE5: .equ %00100000 mPTFPFE_PTFPFE6: .equ %01000000 mPTFPFE_PTFPFE7: .equ %10000000 ;*** PTFIC - Port F Interrupt Control Register; 0xFFFF8155 *** PTFIC: .equ $FFFF8155 ;*** PTFIC - Port F Interrupt Control Register; 0xFFFF8155 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTFIC_PTFMOD: .equ 0 ; Detection Mode for Pin Interrupt PTFIC_PTFIE: .equ 1 ; Interrupt Enable PTFIC_PTFDMAEN: .equ 7 ; DMA Enable bit ; bit position masks mPTFIC_PTFMOD: .equ %00000001 mPTFIC_PTFIE: .equ %00000010 mPTFIC_PTFDMAEN: .equ %10000000 ;*** PTFIPE - Port F Interrupt Pin Enable Register; 0xFFFF8156 *** PTFIPE: .equ $FFFF8156 ;*** PTFIPE - Port F Interrupt Pin Enable Register; 0xFFFF8156 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTFIPE_PTFIPE0: .equ 0 ; Interrupt Pin Enable Bit 0 PTFIPE_PTFIPE1: .equ 1 ; Interrupt Pin Enable Bit 1 PTFIPE_PTFIPE2: .equ 2 ; Interrupt Pin Enable Bit 2 PTFIPE_PTFIPE3: .equ 3 ; Interrupt Pin Enable Bit 3 PTFIPE_PTFIPE4: .equ 4 ; Interrupt Pin Enable Bit 4 PTFIPE_PTFIPE5: .equ 5 ; Interrupt Pin Enable Bit 5 PTFIPE_PTFIPE6: .equ 6 ; Interrupt Pin Enable Bit 6 PTFIPE_PTFIPE7: .equ 7 ; Interrupt Pin Enable Bit 7 ; bit position masks mPTFIPE_PTFIPE0: .equ %00000001 mPTFIPE_PTFIPE1: .equ %00000010 mPTFIPE_PTFIPE2: .equ %00000100 mPTFIPE_PTFIPE3: .equ %00001000 mPTFIPE_PTFIPE4: .equ %00010000 mPTFIPE_PTFIPE5: .equ %00100000 mPTFIPE_PTFIPE6: .equ %01000000 mPTFIPE_PTFIPE7: .equ %10000000 ;*** PTFIF - Port F Interrupt Flag Register; 0xFFFF8157 *** PTFIF: .equ $FFFF8157 ;*** PTFIF - Port F Interrupt Flag Register; 0xFFFF8157 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTFIF_PTFIF0: .equ 0 ; Interrupt Flag Bit 0 PTFIF_PTFIF1: .equ 1 ; Interrupt Flag Bit 1 PTFIF_PTFIF2: .equ 2 ; Interrupt Flag Bit 2 PTFIF_PTFIF3: .equ 3 ; Interrupt Flag Bit 3 PTFIF_PTFIF4: .equ 4 ; Interrupt Flag Bit 4 PTFIF_PTFIF5: .equ 5 ; Interrupt Flag Bit 5 PTFIF_PTFIF6: .equ 6 ; Interrupt Flag Bit 6 PTFIF_PTFIF7: .equ 7 ; Interrupt Flag Bit 7 ; bit position masks mPTFIF_PTFIF0: .equ %00000001 mPTFIF_PTFIF1: .equ %00000010 mPTFIF_PTFIF2: .equ %00000100 mPTFIF_PTFIF3: .equ %00001000 mPTFIF_PTFIF4: .equ %00010000 mPTFIF_PTFIF5: .equ %00100000 mPTFIF_PTFIF6: .equ %01000000 mPTFIF_PTFIF7: .equ %10000000 ;*** PTFIES - Port F Interrupt Edge Select Register; 0xFFFF8158 *** PTFIES: .equ $FFFF8158 ;*** PTFIES - Port F Interrupt Edge Select Register; 0xFFFF8158 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTFIES_PTFEDG0: .equ 0 ; Edge Selects of Pin Interrupt Bit 0 PTFIES_PTFEDG1: .equ 1 ; Edge Selects of Pin Interrupt Bit 1 PTFIES_PTFEDG2: .equ 2 ; Edge Selects of Pin Interrupt Bit 2 PTFIES_PTFEDG3: .equ 3 ; Edge Selects of Pin Interrupt Bit 3 PTFIES_PTFEDG4: .equ 4 ; Edge Selects of Pin Interrupt Bit 4 PTFIES_PTFEDG5: .equ 5 ; Edge Selects of Pin Interrupt Bit 5 PTFIES_PTFEDG6: .equ 6 ; Edge Selects of Pin Interrupt Bit 6 PTFIES_PTFEDG7: .equ 7 ; Edge Selects of Pin Interrupt Bit 7 ; bit position masks mPTFIES_PTFEDG0: .equ %00000001 mPTFIES_PTFEDG1: .equ %00000010 mPTFIES_PTFEDG2: .equ %00000100 mPTFIES_PTFEDG3: .equ %00001000 mPTFIES_PTFEDG4: .equ %00010000 mPTFIES_PTFEDG5: .equ %00100000 mPTFIES_PTFEDG6: .equ %01000000 mPTFIES_PTFEDG7: .equ %10000000 ;*** PTFDFE - Port F Digital Filter Enable Register; 0xFFFF8159 *** PTFDFE: .equ $FFFF8159 ;*** PTFDFE - Port F Digital Filter Enable Register; 0xFFFF8159 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTFDFE_PTFDFE0: .equ 0 ; Digital Filter Enable Bit 0 PTFDFE_PTFDFE1: .equ 1 ; Digital Filter Enable Bit 1 PTFDFE_PTFDFE2: .equ 2 ; Digital Filter Enable Bit 2 PTFDFE_PTFDFE3: .equ 3 ; Digital Filter Enable Bit 3 PTFDFE_PTFDFE4: .equ 4 ; Digital Filter Enable Bit 4 PTFDFE_PTFDFE5: .equ 5 ; Digital Filter Enable Bit 5 PTFDFE_PTFDFE6: .equ 6 ; Digital Filter Enable Bit 6 PTFDFE_PTFDFE7: .equ 7 ; Digital Filter Enable Bit 7 ; bit position masks mPTFDFE_PTFDFE0: .equ %00000001 mPTFDFE_PTFDFE1: .equ %00000010 mPTFDFE_PTFDFE2: .equ %00000100 mPTFDFE_PTFDFE3: .equ %00001000 mPTFDFE_PTFDFE4: .equ %00010000 mPTFDFE_PTFDFE5: .equ %00100000 mPTFDFE_PTFDFE6: .equ %01000000 mPTFDFE_PTFDFE7: .equ %10000000 ;*** PTFDFC - Port F Digital Filter Control Register; 0xFFFF815A *** PTFDFC: .equ $FFFF815A ;*** PTFDFC - Port F Digital Filter Control Register; 0xFFFF815A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTFDFC_PTFFF0: .equ 0 ; Filter Factor Bits, bit 0 PTFDFC_PTFFF1: .equ 1 ; Filter Factor Bits, bit 1 PTFDFC_PTFFF2: .equ 2 ; Filter Factor Bits, bit 2 PTFDFC_PTFFF3: .equ 3 ; Filter Factor Bits, bit 3 PTFDFC_PTFFF4: .equ 4 ; Filter Factor Bits, bit 4 PTFDFC_PTFCLKS: .equ 7 ; Clok Select Bit ; bit position masks mPTFDFC_PTFFF0: .equ %00000001 mPTFDFC_PTFFF1: .equ %00000010 mPTFDFC_PTFFF2: .equ %00000100 mPTFDFC_PTFFF3: .equ %00001000 mPTFDFC_PTFFF4: .equ %00010000 mPTFDFC_PTFCLKS: .equ %10000000 ;*** PTGPUE - Port G Pulling Enable Register; 0xFFFF8160 *** PTGPUE: .equ $FFFF8160 ;*** PTGPUE - Port G Pulling Enable Register; 0xFFFF8160 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTGPUE_PTGPUE0: .equ 0 ; Internal Pulling Enable for Port G Bit 0 PTGPUE_PTGPUE1: .equ 1 ; Internal Pulling Enable for Port G Bit 1 PTGPUE_PTGPUE2: .equ 2 ; Internal Pulling Enable for Port G Bit 2 PTGPUE_PTGPUE3: .equ 3 ; Internal Pulling Enable for Port G Bit 3 PTGPUE_PTGPUE4: .equ 4 ; Internal Pulling Enable for Port G Bit 4 PTGPUE_PTGPUE5: .equ 5 ; Internal Pulling Enable for Port G Bit 5 PTGPUE_PTGPUE6: .equ 6 ; Internal Pulling Enable for Port G Bit 6 ; bit position masks mPTGPUE_PTGPUE0: .equ %00000001 mPTGPUE_PTGPUE1: .equ %00000010 mPTGPUE_PTGPUE2: .equ %00000100 mPTGPUE_PTGPUE3: .equ %00001000 mPTGPUE_PTGPUE4: .equ %00010000 mPTGPUE_PTGPUE5: .equ %00100000 mPTGPUE_PTGPUE6: .equ %01000000 ;*** PTGPUS - Port G Pullup/Pulldown Select Register; 0xFFFF8161 *** PTGPUS: .equ $FFFF8161 ;*** PTGPUS - Port G Pullup/Pulldown Select Register; 0xFFFF8161 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTGPUS_PTGPUS0: .equ 0 ; Pullup/Pulldown Select Bit 0 PTGPUS_PTGPUS1: .equ 1 ; Pullup/Pulldown Select Bit 1 PTGPUS_PTGPUS2: .equ 2 ; Pullup/Pulldown Select Bit 2 PTGPUS_PTGPUS3: .equ 3 ; Pullup/Pulldown Select Bit 3 PTGPUS_PTGPUS4: .equ 4 ; Pullup/Pulldown Select Bit 4 PTGPUS_PTGPUS5: .equ 5 ; Pullup/Pulldown Select Bit 5 PTGPUS_PTGPUS6: .equ 6 ; Pullup/Pulldown Select Bit 6 ; bit position masks mPTGPUS_PTGPUS0: .equ %00000001 mPTGPUS_PTGPUS1: .equ %00000010 mPTGPUS_PTGPUS2: .equ %00000100 mPTGPUS_PTGPUS3: .equ %00001000 mPTGPUS_PTGPUS4: .equ %00010000 mPTGPUS_PTGPUS5: .equ %00100000 mPTGPUS_PTGPUS6: .equ %01000000 ;*** PTGDS - Port G Drive Strength Selection Register; 0xFFFF8162 *** PTGDS: .equ $FFFF8162 ;*** PTGDS - Port G Drive Strength Selection Register; 0xFFFF8162 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTGDS_PTGDS0: .equ 0 ; Output Drive Strength Selection for Port G Bit 0 PTGDS_PTGDS1: .equ 1 ; Output Drive Strength Selection for Port G Bit 1 PTGDS_PTGDS2: .equ 2 ; Output Drive Strength Selection for Port G Bit 2 PTGDS_PTGDS3: .equ 3 ; Output Drive Strength Selection for Port G Bit 3 PTGDS_PTGDS4: .equ 4 ; Output Drive Strength Selection for Port G Bit 4 PTGDS_PTGDS5: .equ 5 ; Output Drive Strength Selection for Port G Bit 5 PTGDS_PTGDS6: .equ 6 ; Output Drive Strength Selection for Port G Bit 6 ; bit position masks mPTGDS_PTGDS0: .equ %00000001 mPTGDS_PTGDS1: .equ %00000010 mPTGDS_PTGDS2: .equ %00000100 mPTGDS_PTGDS3: .equ %00001000 mPTGDS_PTGDS4: .equ %00010000 mPTGDS_PTGDS5: .equ %00100000 mPTGDS_PTGDS6: .equ %01000000 ;*** PTGSRE - Port G Slew Rate Enable Register; 0xFFFF8163 *** PTGSRE: .equ $FFFF8163 ;*** PTGSRE - Port G Slew Rate Enable Register; 0xFFFF8163 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTGSRE_PTGSRE0: .equ 0 ; Output Slew Rate Enable for Port G Bit 0 PTGSRE_PTGSRE1: .equ 1 ; Output Slew Rate Enable for Port G Bit 1 PTGSRE_PTGSRE2: .equ 2 ; Output Slew Rate Enable for Port G Bit 2 PTGSRE_PTGSRE3: .equ 3 ; Output Slew Rate Enable for Port G Bit 3 PTGSRE_PTGSRE4: .equ 4 ; Output Slew Rate Enable for Port G Bit 4 PTGSRE_PTGSRE5: .equ 5 ; Output Slew Rate Enable for Port G Bit 5 PTGSRE_PTGSRE6: .equ 6 ; Output Slew Rate Enable for Port G Bit 6 ; bit position masks mPTGSRE_PTGSRE0: .equ %00000001 mPTGSRE_PTGSRE1: .equ %00000010 mPTGSRE_PTGSRE2: .equ %00000100 mPTGSRE_PTGSRE3: .equ %00001000 mPTGSRE_PTGSRE4: .equ %00010000 mPTGSRE_PTGSRE5: .equ %00100000 mPTGSRE_PTGSRE6: .equ %01000000 ;*** PTGPFE - Port G Passive Filter Enable Register; 0xFFFF8164 *** PTGPFE: .equ $FFFF8164 ;*** PTGPFE - Port G Passive Filter Enable Register; 0xFFFF8164 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTGPFE_PTGPFE0: .equ 0 ; Port A Input Filter Enable Bit 0 PTGPFE_PTGPFE1: .equ 1 ; Port A Input Filter Enable Bit 1 PTGPFE_PTGPFE2: .equ 2 ; Port A Input Filter Enable Bit 2 PTGPFE_PTGPFE3: .equ 3 ; Port A Input Filter Enable Bit 3 PTGPFE_PTGPFE4: .equ 4 ; Port A Input Filter Enable Bit 4 PTGPFE_PTGPFE5: .equ 5 ; Port A Input Filter Enable Bit 5 PTGPFE_PTGPFE6: .equ 6 ; Port A Input Filter Enable Bit 6 ; bit position masks mPTGPFE_PTGPFE0: .equ %00000001 mPTGPFE_PTGPFE1: .equ %00000010 mPTGPFE_PTGPFE2: .equ %00000100 mPTGPFE_PTGPFE3: .equ %00001000 mPTGPFE_PTGPFE4: .equ %00010000 mPTGPFE_PTGPFE5: .equ %00100000 mPTGPFE_PTGPFE6: .equ %01000000 ;*** PTGIC - Port G Interrupt Control Register; 0xFFFF8165 *** PTGIC: .equ $FFFF8165 ;*** PTGIC - Port G Interrupt Control Register; 0xFFFF8165 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTGIC_PTGMOD: .equ 0 ; Detection Mode for Pin Interrupt PTGIC_PTGIE: .equ 1 ; Interrupt Enable PTGIC_PTGDMAEN: .equ 7 ; DMA Enable bit ; bit position masks mPTGIC_PTGMOD: .equ %00000001 mPTGIC_PTGIE: .equ %00000010 mPTGIC_PTGDMAEN: .equ %10000000 ;*** PTGIPE - Port G Interrupt Pin Enable Register; 0xFFFF8166 *** PTGIPE: .equ $FFFF8166 ;*** PTGIPE - Port G Interrupt Pin Enable Register; 0xFFFF8166 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTGIPE_PTGIPE0: .equ 0 ; Interrupt Pin Enable Bit 0 PTGIPE_PTGIPE1: .equ 1 ; Interrupt Pin Enable Bit 1 PTGIPE_PTGIPE2: .equ 2 ; Interrupt Pin Enable Bit 2 PTGIPE_PTGIPE3: .equ 3 ; Interrupt Pin Enable Bit 3 PTGIPE_PTGIPE4: .equ 4 ; Interrupt Pin Enable Bit 4 PTGIPE_PTGIPE5: .equ 5 ; Interrupt Pin Enable Bit 5 PTGIPE_PTGIPE6: .equ 6 ; Interrupt Pin Enable Bit 6 ; bit position masks mPTGIPE_PTGIPE0: .equ %00000001 mPTGIPE_PTGIPE1: .equ %00000010 mPTGIPE_PTGIPE2: .equ %00000100 mPTGIPE_PTGIPE3: .equ %00001000 mPTGIPE_PTGIPE4: .equ %00010000 mPTGIPE_PTGIPE5: .equ %00100000 mPTGIPE_PTGIPE6: .equ %01000000 ;*** PTGIF - Port G Interrupt Flag Register; 0xFFFF8167 *** PTGIF: .equ $FFFF8167 ;*** PTGIF - Port G Interrupt Flag Register; 0xFFFF8167 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTGIF_PTGIF0: .equ 0 ; Interrupt Flag Bit 0 PTGIF_PTGIF1: .equ 1 ; Interrupt Flag Bit 1 PTGIF_PTGIF2: .equ 2 ; Interrupt Flag Bit 2 PTGIF_PTGIF3: .equ 3 ; Interrupt Flag Bit 3 PTGIF_PTGIF4: .equ 4 ; Interrupt Flag Bit 4 PTGIF_PTGIF5: .equ 5 ; Interrupt Flag Bit 5 PTGIF_PTGIF6: .equ 6 ; Interrupt Flag Bit 6 ; bit position masks mPTGIF_PTGIF0: .equ %00000001 mPTGIF_PTGIF1: .equ %00000010 mPTGIF_PTGIF2: .equ %00000100 mPTGIF_PTGIF3: .equ %00001000 mPTGIF_PTGIF4: .equ %00010000 mPTGIF_PTGIF5: .equ %00100000 mPTGIF_PTGIF6: .equ %01000000 ;*** PTGIES - Port G Interrupt Edge Select Register; 0xFFFF8168 *** PTGIES: .equ $FFFF8168 ;*** PTGIES - Port G Interrupt Edge Select Register; 0xFFFF8168 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTGIES_PTGEDG0: .equ 0 ; Edge Selects of Pin Interrupt Bit 0 PTGIES_PTGEDG1: .equ 1 ; Edge Selects of Pin Interrupt Bit 1 PTGIES_PTGEDG2: .equ 2 ; Edge Selects of Pin Interrupt Bit 2 PTGIES_PTGEDG3: .equ 3 ; Edge Selects of Pin Interrupt Bit 3 PTGIES_PTGEDG4: .equ 4 ; Edge Selects of Pin Interrupt Bit 4 PTGIES_PTGEDG5: .equ 5 ; Edge Selects of Pin Interrupt Bit 5 PTGIES_PTGEDG6: .equ 6 ; Edge Selects of Pin Interrupt Bit 6 ; bit position masks mPTGIES_PTGEDG0: .equ %00000001 mPTGIES_PTGEDG1: .equ %00000010 mPTGIES_PTGEDG2: .equ %00000100 mPTGIES_PTGEDG3: .equ %00001000 mPTGIES_PTGEDG4: .equ %00010000 mPTGIES_PTGEDG5: .equ %00100000 mPTGIES_PTGEDG6: .equ %01000000 ;*** PTGDFE - Port G Digital Filter Enable Register; 0xFFFF8169 *** PTGDFE: .equ $FFFF8169 ;*** PTGDFE - Port G Digital Filter Enable Register; 0xFFFF8169 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTGDFE_PTGDFE0: .equ 0 ; Digital Filter Enable Bit 0 PTGDFE_PTGDFE1: .equ 1 ; Digital Filter Enable Bit 1 PTGDFE_PTGDFE2: .equ 2 ; Digital Filter Enable Bit 2 PTGDFE_PTGDFE3: .equ 3 ; Digital Filter Enable Bit 3 PTGDFE_PTGDFE4: .equ 4 ; Digital Filter Enable Bit 4 PTGDFE_PTGDFE5: .equ 5 ; Digital Filter Enable Bit 5 PTGDFE_PTGDFE6: .equ 6 ; Digital Filter Enable Bit 6 ; bit position masks mPTGDFE_PTGDFE0: .equ %00000001 mPTGDFE_PTGDFE1: .equ %00000010 mPTGDFE_PTGDFE2: .equ %00000100 mPTGDFE_PTGDFE3: .equ %00001000 mPTGDFE_PTGDFE4: .equ %00010000 mPTGDFE_PTGDFE5: .equ %00100000 mPTGDFE_PTGDFE6: .equ %01000000 ;*** PTGDFC - Port G Digital Filter Control Register; 0xFFFF816A *** PTGDFC: .equ $FFFF816A ;*** PTGDFC - Port G Digital Filter Control Register; 0xFFFF816A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTGDFC_PTGFF0: .equ 0 ; Filter Factor Bits, bit 0 PTGDFC_PTGFF1: .equ 1 ; Filter Factor Bits, bit 1 PTGDFC_PTGFF2: .equ 2 ; Filter Factor Bits, bit 2 PTGDFC_PTGFF3: .equ 3 ; Filter Factor Bits, bit 3 PTGDFC_PTGFF4: .equ 4 ; Filter Factor Bits, bit 4 PTGDFC_PTGCLKS: .equ 7 ; Clok Select Bit ; bit position masks mPTGDFC_PTGFF0: .equ %00000001 mPTGDFC_PTGFF1: .equ %00000010 mPTGDFC_PTGFF2: .equ %00000100 mPTGDFC_PTGFF3: .equ %00001000 mPTGDFC_PTGFF4: .equ %00010000 mPTGDFC_PTGCLKS: .equ %10000000 ;*** PTHPUE - Port H Pulling Enable Register; 0xFFFF8170 *** PTHPUE: .equ $FFFF8170 ;*** PTHPUE - Port H Pulling Enable Register; 0xFFFF8170 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTHPUE_PTHPUE0: .equ 0 ; Internal Pulling Enable for Port H Bit 0 PTHPUE_PTHPUE1: .equ 1 ; Internal Pulling Enable for Port H Bit 1 PTHPUE_PTHPUE2: .equ 2 ; Internal Pulling Enable for Port H Bit 2 PTHPUE_PTHPUE3: .equ 3 ; Internal Pulling Enable for Port H Bit 3 PTHPUE_PTHPUE4: .equ 4 ; Internal Pulling Enable for Port H Bit 4 PTHPUE_PTHPUE5: .equ 5 ; Internal Pulling Enable for Port H Bit 5 PTHPUE_PTHPUE6: .equ 6 ; Internal Pulling Enable for Port H Bit 6 ; bit position masks mPTHPUE_PTHPUE0: .equ %00000001 mPTHPUE_PTHPUE1: .equ %00000010 mPTHPUE_PTHPUE2: .equ %00000100 mPTHPUE_PTHPUE3: .equ %00001000 mPTHPUE_PTHPUE4: .equ %00010000 mPTHPUE_PTHPUE5: .equ %00100000 mPTHPUE_PTHPUE6: .equ %01000000 ;*** PTHPUS - Port H Pullup/Pulldown Select Register; 0xFFFF8171 *** PTHPUS: .equ $FFFF8171 ;*** PTHPUS - Port H Pullup/Pulldown Select Register; 0xFFFF8171 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTHPUS_PTHPUS0: .equ 0 ; Pullup/Pulldown Select Bit 0 PTHPUS_PTHPUS1: .equ 1 ; Pullup/Pulldown Select Bit 1 PTHPUS_PTHPUS2: .equ 2 ; Pullup/Pulldown Select Bit 2 PTHPUS_PTHPUS3: .equ 3 ; Pullup/Pulldown Select Bit 3 PTHPUS_PTHPUS4: .equ 4 ; Pullup/Pulldown Select Bit 4 PTHPUS_PTHPUS5: .equ 5 ; Pullup/Pulldown Select Bit 5 PTHPUS_PTHPUS6: .equ 6 ; Pullup/Pulldown Select Bit 6 ; bit position masks mPTHPUS_PTHPUS0: .equ %00000001 mPTHPUS_PTHPUS1: .equ %00000010 mPTHPUS_PTHPUS2: .equ %00000100 mPTHPUS_PTHPUS3: .equ %00001000 mPTHPUS_PTHPUS4: .equ %00010000 mPTHPUS_PTHPUS5: .equ %00100000 mPTHPUS_PTHPUS6: .equ %01000000 ;*** PTHDS - Port H Drive Strength Selection Register; 0xFFFF8172 *** PTHDS: .equ $FFFF8172 ;*** PTHDS - Port H Drive Strength Selection Register; 0xFFFF8172 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTHDS_PTHDS0: .equ 0 ; Output Drive Strength Selection for Port H Bit 0 PTHDS_PTHDS1: .equ 1 ; Output Drive Strength Selection for Port H Bit 1 PTHDS_PTHDS2: .equ 2 ; Output Drive Strength Selection for Port H Bit 2 PTHDS_PTHDS3: .equ 3 ; Output Drive Strength Selection for Port H Bit 3 PTHDS_PTHDS4: .equ 4 ; Output Drive Strength Selection for Port H Bit 4 PTHDS_PTHDS5: .equ 5 ; Output Drive Strength Selection for Port H Bit 5 PTHDS_PTHDS6: .equ 6 ; Output Drive Strength Selection for Port H Bit 6 ; bit position masks mPTHDS_PTHDS0: .equ %00000001 mPTHDS_PTHDS1: .equ %00000010 mPTHDS_PTHDS2: .equ %00000100 mPTHDS_PTHDS3: .equ %00001000 mPTHDS_PTHDS4: .equ %00010000 mPTHDS_PTHDS5: .equ %00100000 mPTHDS_PTHDS6: .equ %01000000 ;*** PTHSRE - Port H Slew Rate Enable Register; 0xFFFF8173 *** PTHSRE: .equ $FFFF8173 ;*** PTHSRE - Port H Slew Rate Enable Register; 0xFFFF8173 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTHSRE_PTHSRE0: .equ 0 ; Output Slew Rate Enable for Port H Bit 0 PTHSRE_PTHSRE1: .equ 1 ; Output Slew Rate Enable for Port H Bit 1 PTHSRE_PTHSRE2: .equ 2 ; Output Slew Rate Enable for Port H Bit 2 PTHSRE_PTHSRE3: .equ 3 ; Output Slew Rate Enable for Port H Bit 3 PTHSRE_PTHSRE4: .equ 4 ; Output Slew Rate Enable for Port H Bit 4 PTHSRE_PTHSRE5: .equ 5 ; Output Slew Rate Enable for Port H Bit 5 PTHSRE_PTHSRE6: .equ 6 ; Output Slew Rate Enable for Port H Bit 6 ; bit position masks mPTHSRE_PTHSRE0: .equ %00000001 mPTHSRE_PTHSRE1: .equ %00000010 mPTHSRE_PTHSRE2: .equ %00000100 mPTHSRE_PTHSRE3: .equ %00001000 mPTHSRE_PTHSRE4: .equ %00010000 mPTHSRE_PTHSRE5: .equ %00100000 mPTHSRE_PTHSRE6: .equ %01000000 ;*** PTHPFE - Port H Passive Filter Enable Register; 0xFFFF8174 *** PTHPFE: .equ $FFFF8174 ;*** PTHPFE - Port H Passive Filter Enable Register; 0xFFFF8174 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTHPFE_PTHPFE0: .equ 0 ; Port A Input Filter Enable Bit 0 PTHPFE_PTHPFE1: .equ 1 ; Port A Input Filter Enable Bit 1 PTHPFE_PTHPFE2: .equ 2 ; Port A Input Filter Enable Bit 2 PTHPFE_PTHPFE3: .equ 3 ; Port A Input Filter Enable Bit 3 PTHPFE_PTHPFE4: .equ 4 ; Port A Input Filter Enable Bit 4 PTHPFE_PTHPFE5: .equ 5 ; Port A Input Filter Enable Bit 5 PTHPFE_PTHPFE6: .equ 6 ; Port A Input Filter Enable Bit 6 ; bit position masks mPTHPFE_PTHPFE0: .equ %00000001 mPTHPFE_PTHPFE1: .equ %00000010 mPTHPFE_PTHPFE2: .equ %00000100 mPTHPFE_PTHPFE3: .equ %00001000 mPTHPFE_PTHPFE4: .equ %00010000 mPTHPFE_PTHPFE5: .equ %00100000 mPTHPFE_PTHPFE6: .equ %01000000 ;*** PTHIC - Port H Interrupt Control Register; 0xFFFF8175 *** PTHIC: .equ $FFFF8175 ;*** PTHIC - Port H Interrupt Control Register; 0xFFFF8175 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTHIC_PTHMOD: .equ 0 ; Detection Mode for Pin Interrupt PTHIC_PTHIE: .equ 1 ; Interrupt Enable PTHIC_PTHDMAEN: .equ 7 ; DMA Enable bit ; bit position masks mPTHIC_PTHMOD: .equ %00000001 mPTHIC_PTHIE: .equ %00000010 mPTHIC_PTHDMAEN: .equ %10000000 ;*** PTHIPE - Port H Interrupt Pin Enable Register; 0xFFFF8176 *** PTHIPE: .equ $FFFF8176 ;*** PTHIPE - Port H Interrupt Pin Enable Register; 0xFFFF8176 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTHIPE_PTHIPE0: .equ 0 ; Interrupt Pin Enable Bit 0 PTHIPE_PTHIPE1: .equ 1 ; Interrupt Pin Enable Bit 1 PTHIPE_PTHIPE2: .equ 2 ; Interrupt Pin Enable Bit 2 PTHIPE_PTHIPE3: .equ 3 ; Interrupt Pin Enable Bit 3 PTHIPE_PTHIPE4: .equ 4 ; Interrupt Pin Enable Bit 4 PTHIPE_PTHIPE5: .equ 5 ; Interrupt Pin Enable Bit 5 PTHIPE_PTHIPE6: .equ 6 ; Interrupt Pin Enable Bit 6 ; bit position masks mPTHIPE_PTHIPE0: .equ %00000001 mPTHIPE_PTHIPE1: .equ %00000010 mPTHIPE_PTHIPE2: .equ %00000100 mPTHIPE_PTHIPE3: .equ %00001000 mPTHIPE_PTHIPE4: .equ %00010000 mPTHIPE_PTHIPE5: .equ %00100000 mPTHIPE_PTHIPE6: .equ %01000000 ;*** PTHIF - Port H Interrupt Flag Register; 0xFFFF8177 *** PTHIF: .equ $FFFF8177 ;*** PTHIF - Port H Interrupt Flag Register; 0xFFFF8177 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTHIF_PTHIF0: .equ 0 ; Interrupt Flag Bit 0 PTHIF_PTHIF1: .equ 1 ; Interrupt Flag Bit 1 PTHIF_PTHIF2: .equ 2 ; Interrupt Flag Bit 2 PTHIF_PTHIF3: .equ 3 ; Interrupt Flag Bit 3 PTHIF_PTHIF4: .equ 4 ; Interrupt Flag Bit 4 PTHIF_PTHIF5: .equ 5 ; Interrupt Flag Bit 5 PTHIF_PTHIF6: .equ 6 ; Interrupt Flag Bit 6 ; bit position masks mPTHIF_PTHIF0: .equ %00000001 mPTHIF_PTHIF1: .equ %00000010 mPTHIF_PTHIF2: .equ %00000100 mPTHIF_PTHIF3: .equ %00001000 mPTHIF_PTHIF4: .equ %00010000 mPTHIF_PTHIF5: .equ %00100000 mPTHIF_PTHIF6: .equ %01000000 ;*** PTHIES - Port H Interrupt Edge Select Register; 0xFFFF8178 *** PTHIES: .equ $FFFF8178 ;*** PTHIES - Port H Interrupt Edge Select Register; 0xFFFF8178 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTHIES_PTHEDG0: .equ 0 ; Edge Selects of Pin Interrupt Bit 0 PTHIES_PTHEDG1: .equ 1 ; Edge Selects of Pin Interrupt Bit 1 PTHIES_PTHEDG2: .equ 2 ; Edge Selects of Pin Interrupt Bit 2 PTHIES_PTHEDG3: .equ 3 ; Edge Selects of Pin Interrupt Bit 3 PTHIES_PTHEDG4: .equ 4 ; Edge Selects of Pin Interrupt Bit 4 PTHIES_PTHEDG5: .equ 5 ; Edge Selects of Pin Interrupt Bit 5 PTHIES_PTHEDG6: .equ 6 ; Edge Selects of Pin Interrupt Bit 6 ; bit position masks mPTHIES_PTHEDG0: .equ %00000001 mPTHIES_PTHEDG1: .equ %00000010 mPTHIES_PTHEDG2: .equ %00000100 mPTHIES_PTHEDG3: .equ %00001000 mPTHIES_PTHEDG4: .equ %00010000 mPTHIES_PTHEDG5: .equ %00100000 mPTHIES_PTHEDG6: .equ %01000000 ;*** PTHDFE - Port H Digital Filter Enable Register; 0xFFFF8179 *** PTHDFE: .equ $FFFF8179 ;*** PTHDFE - Port H Digital Filter Enable Register; 0xFFFF8179 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTHDFE_PTHDFE0: .equ 0 ; Digital Filter Enable Bit 0 PTHDFE_PTHDFE1: .equ 1 ; Digital Filter Enable Bit 1 PTHDFE_PTHDFE2: .equ 2 ; Digital Filter Enable Bit 2 PTHDFE_PTHDFE3: .equ 3 ; Digital Filter Enable Bit 3 PTHDFE_PTHDFE4: .equ 4 ; Digital Filter Enable Bit 4 PTHDFE_PTHDFE5: .equ 5 ; Digital Filter Enable Bit 5 PTHDFE_PTHDFE6: .equ 6 ; Digital Filter Enable Bit 6 ; bit position masks mPTHDFE_PTHDFE0: .equ %00000001 mPTHDFE_PTHDFE1: .equ %00000010 mPTHDFE_PTHDFE2: .equ %00000100 mPTHDFE_PTHDFE3: .equ %00001000 mPTHDFE_PTHDFE4: .equ %00010000 mPTHDFE_PTHDFE5: .equ %00100000 mPTHDFE_PTHDFE6: .equ %01000000 ;*** PTHDFC - Port H Digital Filter Control Register; 0xFFFF817A *** PTHDFC: .equ $FFFF817A ;*** PTHDFC - Port H Digital Filter Control Register; 0xFFFF817A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTHDFC_PTHFF0: .equ 0 ; Filter Factor Bits, bit 0 PTHDFC_PTHFF1: .equ 1 ; Filter Factor Bits, bit 1 PTHDFC_PTHFF2: .equ 2 ; Filter Factor Bits, bit 2 PTHDFC_PTHFF3: .equ 3 ; Filter Factor Bits, bit 3 PTHDFC_PTHFF4: .equ 4 ; Filter Factor Bits, bit 4 PTHDFC_PTHCLKS: .equ 7 ; Clok Select Bit ; bit position masks mPTHDFC_PTHFF0: .equ %00000001 mPTHDFC_PTHFF1: .equ %00000010 mPTHDFC_PTHFF2: .equ %00000100 mPTHDFC_PTHFF3: .equ %00001000 mPTHDFC_PTHFF4: .equ %00010000 mPTHDFC_PTHCLKS: .equ %10000000 ;*** PTJPUE - Port J Pulling Enable Register; 0xFFFF8180 *** PTJPUE: .equ $FFFF8180 ;*** PTJPUE - Port J Pulling Enable Register; 0xFFFF8180 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTJPUE_PTJPUE0: .equ 0 ; Internal Pulling Enable for Port J Bit 0 PTJPUE_PTJPUE1: .equ 1 ; Internal Pulling Enable for Port J Bit 1 PTJPUE_PTJPUE2: .equ 2 ; Internal Pulling Enable for Port J Bit 2 PTJPUE_PTJPUE3: .equ 3 ; Internal Pulling Enable for Port J Bit 3 PTJPUE_PTJPUE4: .equ 4 ; Internal Pulling Enable for Port J Bit 4 PTJPUE_PTJPUE5: .equ 5 ; Internal Pulling Enable for Port J Bit 5 PTJPUE_PTJPUE6: .equ 6 ; Internal Pulling Enable for Port J Bit 6 PTJPUE_PTJPUE7: .equ 7 ; Internal Pulling Enable for Port J Bit 7 ; bit position masks mPTJPUE_PTJPUE0: .equ %00000001 mPTJPUE_PTJPUE1: .equ %00000010 mPTJPUE_PTJPUE2: .equ %00000100 mPTJPUE_PTJPUE3: .equ %00001000 mPTJPUE_PTJPUE4: .equ %00010000 mPTJPUE_PTJPUE5: .equ %00100000 mPTJPUE_PTJPUE6: .equ %01000000 mPTJPUE_PTJPUE7: .equ %10000000 ;*** PTJPUS - Port J Pullup/Pulldown Select Register; 0xFFFF8181 *** PTJPUS: .equ $FFFF8181 ;*** PTJPUS - Port J Pullup/Pulldown Select Register; 0xFFFF8181 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTJPUS_PTJPUS0: .equ 0 ; Pullup/Pulldown Select Bit 0 PTJPUS_PTJPUS1: .equ 1 ; Pullup/Pulldown Select Bit 1 PTJPUS_PTJPUS2: .equ 2 ; Pullup/Pulldown Select Bit 2 PTJPUS_PTJPUS3: .equ 3 ; Pullup/Pulldown Select Bit 3 PTJPUS_PTJPUS4: .equ 4 ; Pullup/Pulldown Select Bit 4 PTJPUS_PTJPUS5: .equ 5 ; Pullup/Pulldown Select Bit 5 PTJPUS_PTJPUS6: .equ 6 ; Pullup/Pulldown Select Bit 6 PTJPUS_PTJPUS7: .equ 7 ; Pullup/Pulldown Select Bit 7 ; bit position masks mPTJPUS_PTJPUS0: .equ %00000001 mPTJPUS_PTJPUS1: .equ %00000010 mPTJPUS_PTJPUS2: .equ %00000100 mPTJPUS_PTJPUS3: .equ %00001000 mPTJPUS_PTJPUS4: .equ %00010000 mPTJPUS_PTJPUS5: .equ %00100000 mPTJPUS_PTJPUS6: .equ %01000000 mPTJPUS_PTJPUS7: .equ %10000000 ;*** PTJDS - Port J Drive Strength Selection Register; 0xFFFF8182 *** PTJDS: .equ $FFFF8182 ;*** PTJDS - Port J Drive Strength Selection Register; 0xFFFF8182 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTJDS_PTJDS0: .equ 0 ; Output Drive Strength Selection for Port J Bit 0 PTJDS_PTJDS1: .equ 1 ; Output Drive Strength Selection for Port J Bit 1 PTJDS_PTJDS2: .equ 2 ; Output Drive Strength Selection for Port J Bit 2 PTJDS_PTJDS3: .equ 3 ; Output Drive Strength Selection for Port J Bit 3 PTJDS_PTJDS4: .equ 4 ; Output Drive Strength Selection for Port J Bit 4 PTJDS_PTJDS5: .equ 5 ; Output Drive Strength Selection for Port J Bit 5 PTJDS_PTJDS6: .equ 6 ; Output Drive Strength Selection for Port J Bit 6 PTJDS_PTJDS7: .equ 7 ; Output Drive Strength Selection for Port J Bit 7 ; bit position masks mPTJDS_PTJDS0: .equ %00000001 mPTJDS_PTJDS1: .equ %00000010 mPTJDS_PTJDS2: .equ %00000100 mPTJDS_PTJDS3: .equ %00001000 mPTJDS_PTJDS4: .equ %00010000 mPTJDS_PTJDS5: .equ %00100000 mPTJDS_PTJDS6: .equ %01000000 mPTJDS_PTJDS7: .equ %10000000 ;*** PTJSRE - Port J Slew Rate Enable Register; 0xFFFF8183 *** PTJSRE: .equ $FFFF8183 ;*** PTJSRE - Port J Slew Rate Enable Register; 0xFFFF8183 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTJSRE_PTJSRE0: .equ 0 ; Output Slew Rate Enable for Port J Bit 0 PTJSRE_PTJSRE1: .equ 1 ; Output Slew Rate Enable for Port J Bit 1 PTJSRE_PTJSRE2: .equ 2 ; Output Slew Rate Enable for Port J Bit 2 PTJSRE_PTJSRE3: .equ 3 ; Output Slew Rate Enable for Port J Bit 3 PTJSRE_PTJSRE4: .equ 4 ; Output Slew Rate Enable for Port J Bit 4 PTJSRE_PTJSRE5: .equ 5 ; Output Slew Rate Enable for Port J Bit 5 PTJSRE_PTJSRE6: .equ 6 ; Output Slew Rate Enable for Port J Bit 6 PTJSRE_PTJSRE7: .equ 7 ; Output Slew Rate Enable for Port J Bit 7 ; bit position masks mPTJSRE_PTJSRE0: .equ %00000001 mPTJSRE_PTJSRE1: .equ %00000010 mPTJSRE_PTJSRE2: .equ %00000100 mPTJSRE_PTJSRE3: .equ %00001000 mPTJSRE_PTJSRE4: .equ %00010000 mPTJSRE_PTJSRE5: .equ %00100000 mPTJSRE_PTJSRE6: .equ %01000000 mPTJSRE_PTJSRE7: .equ %10000000 ;*** PTJPFE - Port J Passive Filter Enable Register; 0xFFFF8184 *** PTJPFE: .equ $FFFF8184 ;*** PTJPFE - Port J Passive Filter Enable Register; 0xFFFF8184 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTJPFE_PTJPFE0: .equ 0 ; Port A Input Filter Enable Bit 0 PTJPFE_PTJPFE1: .equ 1 ; Port A Input Filter Enable Bit 1 PTJPFE_PTJPFE2: .equ 2 ; Port A Input Filter Enable Bit 2 PTJPFE_PTJPFE3: .equ 3 ; Port A Input Filter Enable Bit 3 PTJPFE_PTJPFE4: .equ 4 ; Port A Input Filter Enable Bit 4 PTJPFE_PTJPFE5: .equ 5 ; Port A Input Filter Enable Bit 5 PTJPFE_PTJPFE6: .equ 6 ; Port A Input Filter Enable Bit 6 PTJPFE_PTJPFE7: .equ 7 ; Port A Input Filter Enable Bit 7 ; bit position masks mPTJPFE_PTJPFE0: .equ %00000001 mPTJPFE_PTJPFE1: .equ %00000010 mPTJPFE_PTJPFE2: .equ %00000100 mPTJPFE_PTJPFE3: .equ %00001000 mPTJPFE_PTJPFE4: .equ %00010000 mPTJPFE_PTJPFE5: .equ %00100000 mPTJPFE_PTJPFE6: .equ %01000000 mPTJPFE_PTJPFE7: .equ %10000000 ;*** PTJIC - Port J Interrupt Control Register; 0xFFFF8185 *** PTJIC: .equ $FFFF8185 ;*** PTJIC - Port J Interrupt Control Register; 0xFFFF8185 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTJIC_PTJMOD: .equ 0 ; Detection Mode for Pin Interrupt PTJIC_PTJIE: .equ 1 ; Interrupt Enable PTJIC_PTJDMAEN: .equ 7 ; DMA Enable bit ; bit position masks mPTJIC_PTJMOD: .equ %00000001 mPTJIC_PTJIE: .equ %00000010 mPTJIC_PTJDMAEN: .equ %10000000 ;*** PTJIPE - Port J Interrupt Pin Enable Register; 0xFFFF8186 *** PTJIPE: .equ $FFFF8186 ;*** PTJIPE - Port J Interrupt Pin Enable Register; 0xFFFF8186 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTJIPE_PTJIPE0: .equ 0 ; Interrupt Pin Enable Bit 0 PTJIPE_PTJIPE1: .equ 1 ; Interrupt Pin Enable Bit 1 PTJIPE_PTJIPE2: .equ 2 ; Interrupt Pin Enable Bit 2 PTJIPE_PTJIPE3: .equ 3 ; Interrupt Pin Enable Bit 3 PTJIPE_PTJIPE4: .equ 4 ; Interrupt Pin Enable Bit 4 PTJIPE_PTJIPE5: .equ 5 ; Interrupt Pin Enable Bit 5 PTJIPE_PTJIPE6: .equ 6 ; Interrupt Pin Enable Bit 6 PTJIPE_PTJIPE7: .equ 7 ; Interrupt Pin Enable Bit 7 ; bit position masks mPTJIPE_PTJIPE0: .equ %00000001 mPTJIPE_PTJIPE1: .equ %00000010 mPTJIPE_PTJIPE2: .equ %00000100 mPTJIPE_PTJIPE3: .equ %00001000 mPTJIPE_PTJIPE4: .equ %00010000 mPTJIPE_PTJIPE5: .equ %00100000 mPTJIPE_PTJIPE6: .equ %01000000 mPTJIPE_PTJIPE7: .equ %10000000 ;*** PTJIF - Port J Interrupt Flag Register; 0xFFFF8187 *** PTJIF: .equ $FFFF8187 ;*** PTJIF - Port J Interrupt Flag Register; 0xFFFF8187 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTJIF_PTJIF0: .equ 0 ; Interrupt Flag Bit 0 PTJIF_PTJIF1: .equ 1 ; Interrupt Flag Bit 1 PTJIF_PTJIF2: .equ 2 ; Interrupt Flag Bit 2 PTJIF_PTJIF3: .equ 3 ; Interrupt Flag Bit 3 PTJIF_PTJIF4: .equ 4 ; Interrupt Flag Bit 4 PTJIF_PTJIF5: .equ 5 ; Interrupt Flag Bit 5 PTJIF_PTJIF6: .equ 6 ; Interrupt Flag Bit 6 PTJIF_PTJIF7: .equ 7 ; Interrupt Flag Bit 7 ; bit position masks mPTJIF_PTJIF0: .equ %00000001 mPTJIF_PTJIF1: .equ %00000010 mPTJIF_PTJIF2: .equ %00000100 mPTJIF_PTJIF3: .equ %00001000 mPTJIF_PTJIF4: .equ %00010000 mPTJIF_PTJIF5: .equ %00100000 mPTJIF_PTJIF6: .equ %01000000 mPTJIF_PTJIF7: .equ %10000000 ;*** PTJIES - Port J Interrupt Edge Select Register; 0xFFFF8188 *** PTJIES: .equ $FFFF8188 ;*** PTJIES - Port J Interrupt Edge Select Register; 0xFFFF8188 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTJIES_PTJEDG0: .equ 0 ; Edge Selects of Pin Interrupt Bit 0 PTJIES_PTJEDG1: .equ 1 ; Edge Selects of Pin Interrupt Bit 1 PTJIES_PTJEDG2: .equ 2 ; Edge Selects of Pin Interrupt Bit 2 PTJIES_PTJEDG3: .equ 3 ; Edge Selects of Pin Interrupt Bit 3 PTJIES_PTJEDG4: .equ 4 ; Edge Selects of Pin Interrupt Bit 4 PTJIES_PTJEDG5: .equ 5 ; Edge Selects of Pin Interrupt Bit 5 PTJIES_PTJEDG6: .equ 6 ; Edge Selects of Pin Interrupt Bit 6 PTJIES_PTJEDG7: .equ 7 ; Edge Selects of Pin Interrupt Bit 7 ; bit position masks mPTJIES_PTJEDG0: .equ %00000001 mPTJIES_PTJEDG1: .equ %00000010 mPTJIES_PTJEDG2: .equ %00000100 mPTJIES_PTJEDG3: .equ %00001000 mPTJIES_PTJEDG4: .equ %00010000 mPTJIES_PTJEDG5: .equ %00100000 mPTJIES_PTJEDG6: .equ %01000000 mPTJIES_PTJEDG7: .equ %10000000 ;*** PTJDFE - Port J Digital Filter Enable Register; 0xFFFF8189 *** PTJDFE: .equ $FFFF8189 ;*** PTJDFE - Port J Digital Filter Enable Register; 0xFFFF8189 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTJDFE_PTJDFE0: .equ 0 ; Digital Filter Enable Bit 0 PTJDFE_PTJDFE1: .equ 1 ; Digital Filter Enable Bit 1 PTJDFE_PTJDFE2: .equ 2 ; Digital Filter Enable Bit 2 PTJDFE_PTJDFE3: .equ 3 ; Digital Filter Enable Bit 3 PTJDFE_PTJDFE4: .equ 4 ; Digital Filter Enable Bit 4 PTJDFE_PTJDFE5: .equ 5 ; Digital Filter Enable Bit 5 PTJDFE_PTJDFE6: .equ 6 ; Digital Filter Enable Bit 6 PTJDFE_PTJDFE7: .equ 7 ; Digital Filter Enable Bit 7 ; bit position masks mPTJDFE_PTJDFE0: .equ %00000001 mPTJDFE_PTJDFE1: .equ %00000010 mPTJDFE_PTJDFE2: .equ %00000100 mPTJDFE_PTJDFE3: .equ %00001000 mPTJDFE_PTJDFE4: .equ %00010000 mPTJDFE_PTJDFE5: .equ %00100000 mPTJDFE_PTJDFE6: .equ %01000000 mPTJDFE_PTJDFE7: .equ %10000000 ;*** PTJDFC - Port J Digital Filter Control Register; 0xFFFF818A *** PTJDFC: .equ $FFFF818A ;*** PTJDFC - Port J Digital Filter Control Register; 0xFFFF818A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PTJDFC_PTJFF0: .equ 0 ; Filter Factor Bits, bit 0 PTJDFC_PTJFF1: .equ 1 ; Filter Factor Bits, bit 1 PTJDFC_PTJFF2: .equ 2 ; Filter Factor Bits, bit 2 PTJDFC_PTJFF3: .equ 3 ; Filter Factor Bits, bit 3 PTJDFC_PTJFF4: .equ 4 ; Filter Factor Bits, bit 4 PTJDFC_PTJCLKS: .equ 7 ; Clok Select Bit ; bit position masks mPTJDFC_PTJFF0: .equ %00000001 mPTJDFC_PTJFF1: .equ %00000010 mPTJDFC_PTJFF2: .equ %00000100 mPTJDFC_PTJFF3: .equ %00001000 mPTJDFC_PTJFF4: .equ %00010000 mPTJDFC_PTJCLKS: .equ %10000000 ;*** IICA1 - IIC Address Register; 0xFFFF8190 *** IICA1: .equ $FFFF8190 ;*** IICA1 - IIC Address Register; 0xFFFF8190 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICA1_AD1: .equ 1 ; Slave Address Bit 1 IICA1_AD2: .equ 2 ; Slave Address Bit 2 IICA1_AD3: .equ 3 ; Slave Address Bit 3 IICA1_AD4: .equ 4 ; Slave Address Bit 4 IICA1_AD5: .equ 5 ; Slave Address Bit 5 IICA1_AD6: .equ 6 ; Slave Address Bit 6 IICA1_AD7: .equ 7 ; Slave Address Bit 7 ; bit position masks mIICA1_AD1: .equ %00000010 mIICA1_AD2: .equ %00000100 mIICA1_AD3: .equ %00001000 mIICA1_AD4: .equ %00010000 mIICA1_AD5: .equ %00100000 mIICA1_AD6: .equ %01000000 mIICA1_AD7: .equ %10000000 ;*** IICA - IIC Address Register; 0xFFFF8190 *** IICA: .equ $FFFF8190 ;*** IICA - IIC Address Register; 0xFFFF8190 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICA_AD1: .equ 1 ; Slave Address Bit 1 IICA_AD2: .equ 2 ; Slave Address Bit 2 IICA_AD3: .equ 3 ; Slave Address Bit 3 IICA_AD4: .equ 4 ; Slave Address Bit 4 IICA_AD5: .equ 5 ; Slave Address Bit 5 IICA_AD6: .equ 6 ; Slave Address Bit 6 IICA_AD7: .equ 7 ; Slave Address Bit 7 ; bit position masks mIICA_AD1: .equ %00000010 mIICA_AD2: .equ %00000100 mIICA_AD3: .equ %00001000 mIICA_AD4: .equ %00010000 mIICA_AD5: .equ %00100000 mIICA_AD6: .equ %01000000 mIICA_AD7: .equ %10000000 ;*** IICF - IIC Frequency Divider Register; 0xFFFF8191 *** IICF: .equ $FFFF8191 ;*** IICF - IIC Frequency Divider Register; 0xFFFF8191 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICF_ICR0: .equ 0 ; IIC Clock Rate Bit 0 IICF_ICR1: .equ 1 ; IIC Clock Rate Bit 1 IICF_ICR2: .equ 2 ; IIC Clock Rate Bit 2 IICF_ICR3: .equ 3 ; IIC Clock Rate Bit 3 IICF_ICR4: .equ 4 ; IIC Clock Rate Bit 4 IICF_ICR5: .equ 5 ; IIC Clock Rate Bit 5 IICF_MULT0: .equ 6 ; Multiplier Factor Bit 0 IICF_MULT1: .equ 7 ; Multiplier Factor Bit 1 ; bit position masks mIICF_ICR0: .equ %00000001 mIICF_ICR1: .equ %00000010 mIICF_ICR2: .equ %00000100 mIICF_ICR3: .equ %00001000 mIICF_ICR4: .equ %00010000 mIICF_ICR5: .equ %00100000 mIICF_MULT0: .equ %01000000 mIICF_MULT1: .equ %10000000 ;*** IICC1 - IIC Control Register 1; 0xFFFF8192 *** IICC1: .equ $FFFF8192 ;*** IICC1 - IIC Control Register 1; 0xFFFF8192 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICC1_DMAEN: .equ 0 ; DMA Enable IICC1_WUEN: .equ 1 ; Wake-up Enable IICC1_RSTA: .equ 2 ; Repeat START IICC1_TXAK: .equ 3 ; Transmit Acknowledge Enable IICC1_TX: .equ 4 ; Transmit Mode Select IICC1_MST: .equ 5 ; Master Mode Select IICC1_IICIE: .equ 6 ; IIC Interrupt Enable IICC1_IICEN: .equ 7 ; IIC Enable ; bit position masks mIICC1_DMAEN: .equ %00000001 mIICC1_WUEN: .equ %00000010 mIICC1_RSTA: .equ %00000100 mIICC1_TXAK: .equ %00001000 mIICC1_TX: .equ %00010000 mIICC1_MST: .equ %00100000 mIICC1_IICIE: .equ %01000000 mIICC1_IICEN: .equ %10000000 ;*** IICC - IIC Control Register; 0xFFFF8192 *** IICC: .equ $FFFF8192 ;*** IICC - IIC Control Register; 0xFFFF8192 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICC_DMAEN: .equ 0 ; DMA Enable IICC_WUEN: .equ 1 ; Wake-up Enable IICC_RSTA: .equ 2 ; Repeat START IICC_TXAK: .equ 3 ; Transmit Acknowledge Enable IICC_TX: .equ 4 ; Transmit Mode Select IICC_MST: .equ 5 ; Master Mode Select IICC_IICIE: .equ 6 ; IIC Interrupt Enable IICC_IICEN: .equ 7 ; IIC Enable ; bit position masks mIICC_DMAEN: .equ %00000001 mIICC_WUEN: .equ %00000010 mIICC_RSTA: .equ %00000100 mIICC_TXAK: .equ %00001000 mIICC_TX: .equ %00010000 mIICC_MST: .equ %00100000 mIICC_IICIE: .equ %01000000 mIICC_IICEN: .equ %10000000 ;*** IICS - IIC Status Register; 0xFFFF8193 *** IICS: .equ $FFFF8193 ;*** IICS - IIC Status Register; 0xFFFF8193 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICS_RXAK: .equ 0 ; Receive Acknowledge IICS_IICIF: .equ 1 ; IIC Interrupt Flag IICS_SRW: .equ 2 ; Slave Read/Write IICS_ARBL: .equ 4 ; Arbitration Lost IICS_BUSY: .equ 5 ; Bus Busy IICS_IAAS: .equ 6 ; Addressed as a Slave IICS_TCF: .equ 7 ; Transfer Complete Flag ; bit position masks mIICS_RXAK: .equ %00000001 mIICS_IICIF: .equ %00000010 mIICS_SRW: .equ %00000100 mIICS_ARBL: .equ %00010000 mIICS_BUSY: .equ %00100000 mIICS_IAAS: .equ %01000000 mIICS_TCF: .equ %10000000 ;*** IICD - IIC Data I/O Register; 0xFFFF8194 *** IICD: .equ $FFFF8194 ;*** IICD - IIC Data I/O Register; 0xFFFF8194 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICD_DATA0: .equ 0 ; IIC Data Bit 0 IICD_DATA1: .equ 1 ; IIC Data Bit 1 IICD_DATA2: .equ 2 ; IIC Data Bit 2 IICD_DATA3: .equ 3 ; IIC Data Bit 3 IICD_DATA4: .equ 4 ; IIC Data Bit 4 IICD_DATA5: .equ 5 ; IIC Data Bit 5 IICD_DATA6: .equ 6 ; IIC Data Bit 6 IICD_DATA7: .equ 7 ; IIC Data Bit 7 ; bit position masks mIICD_DATA0: .equ %00000001 mIICD_DATA1: .equ %00000010 mIICD_DATA2: .equ %00000100 mIICD_DATA3: .equ %00001000 mIICD_DATA4: .equ %00010000 mIICD_DATA5: .equ %00100000 mIICD_DATA6: .equ %01000000 mIICD_DATA7: .equ %10000000 ;*** IICC2 - IIC Control Register 2; 0xFFFF8195 *** IICC2: .equ $FFFF8195 ;*** IICC2 - IIC Control Register 2; 0xFFFF8195 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICC2_AD8: .equ 0 ; Slave Address Bit 8 IICC2_AD9: .equ 1 ; Slave Address Bit 9 IICC2_AD10: .equ 2 ; Slave Address Bit 10 IICC2_SBRC: .equ 4 ; Slave Baud Rate Control IICC2_HDRS: .equ 5 ; High drive select IICC2_ADEXT: .equ 6 ; Address Extension IICC2_GCAEN: .equ 7 ; General Call Address Enable ; bit position masks mIICC2_AD8: .equ %00000001 mIICC2_AD9: .equ %00000010 mIICC2_AD10: .equ %00000100 mIICC2_SBRC: .equ %00010000 mIICC2_HDRS: .equ %00100000 mIICC2_ADEXT: .equ %01000000 mIICC2_GCAEN: .equ %10000000 ;*** IICFLT - IIC Filter register; 0xFFFF8196 *** IICFLT: .equ $FFFF8196 ;*** IICFLT - IIC Filter register; 0xFFFF8196 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICFLT_FLT0: .equ 0 ; Filter value bit 0 IICFLT_FLT1: .equ 1 ; Filter value bit 1 IICFLT_FLT2: .equ 2 ; Filter value bit 2 IICFLT_FLT3: .equ 3 ; Filter value bit 3 IICFLT_FLT4: .equ 4 ; Filter value bit 4 ; bit position masks mIICFLT_FLT0: .equ %00000001 mIICFLT_FLT1: .equ %00000010 mIICFLT_FLT2: .equ %00000100 mIICFLT_FLT3: .equ %00001000 mIICFLT_FLT4: .equ %00010000 ;*** IICSMB - SMBus Control and Status Register; 0xFFFF8197 *** IICSMB: .equ $FFFF8197 ;*** IICSMB - SMBus Control and Status Register; 0xFFFF8197 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICSMB_SHTF2IE: .equ 0 ; SHTF2 Interrupt Enable IICSMB_SHTF2: .equ 1 ; SCL High Timeout Flag 2 IICSMB_SHTF1: .equ 2 ; SCL High Timeout Flag 1 IICSMB_SLTF: .equ 3 ; SCL Low Timeout Flag IICSMB_TCKSEL: .equ 4 ; Time Out Counter Clock Select IICSMB_SIICAEN: .equ 5 ; Second IIC Address Enable IICSMB_ALERTEN: .equ 6 ; SMBus Alert Response Address Enable IICSMB_FACK: .equ 7 ; Fast NACK/ACK enable ; bit position masks mIICSMB_SHTF2IE: .equ %00000001 mIICSMB_SHTF2: .equ %00000010 mIICSMB_SHTF1: .equ %00000100 mIICSMB_SLTF: .equ %00001000 mIICSMB_TCKSEL: .equ %00010000 mIICSMB_SIICAEN: .equ %00100000 mIICSMB_ALERTEN: .equ %01000000 mIICSMB_FACK: .equ %10000000 ;*** IICA2 - IIC Address Register 2; 0xFFFF8198 *** IICA2: .equ $FFFF8198 ;*** IICA2 - IIC Address Register 2; 0xFFFF8198 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICA2_SAD1: .equ 1 ; SMBus Address Bit 1 IICA2_SAD2: .equ 2 ; SMBus Address Bit 2 IICA2_SAD3: .equ 3 ; SMBus Address Bit 3 IICA2_SAD4: .equ 4 ; SMBus Address Bit 4 IICA2_SAD5: .equ 5 ; SMBus Address Bit 5 IICA2_SAD6: .equ 6 ; SMBus Address Bit 6 IICA2_SAD7: .equ 7 ; SMBus Address Bit 7 ; bit position masks mIICA2_SAD1: .equ %00000010 mIICA2_SAD2: .equ %00000100 mIICA2_SAD3: .equ %00001000 mIICA2_SAD4: .equ %00010000 mIICA2_SAD5: .equ %00100000 mIICA2_SAD6: .equ %01000000 mIICA2_SAD7: .equ %10000000 ;*** IICSLT - IIC SCL Low Time Out register; 0xFFFF8199 *** IICSLT: .equ $FFFF8199 ;*** IICSLT - IIC SCL Low Time Out register; 0xFFFF8199 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICSLT_SSLT0: .equ 0 ; SCL Low Time Out Bits, bit 0 IICSLT_SSLT1: .equ 1 ; SCL Low Time Out Bits, bit 1 IICSLT_SSLT2: .equ 2 ; SCL Low Time Out Bits, bit 2 IICSLT_SSLT3: .equ 3 ; SCL Low Time Out Bits, bit 3 IICSLT_SSLT4: .equ 4 ; SCL Low Time Out Bits, bit 4 IICSLT_SSLT5: .equ 5 ; SCL Low Time Out Bits, bit 5 IICSLT_SSLT6: .equ 6 ; SCL Low Time Out Bits, bit 6 IICSLT_SSLT7: .equ 7 ; SCL Low Time Out Bits, bit 7 IICSLT_SSLT8: .equ 8 ; SCL Low Time Out Bits, bit 8 IICSLT_SSLT9: .equ 9 ; SCL Low Time Out Bits, bit 9 IICSLT_SSLT10: .equ 10 ; SCL Low Time Out Bits, bit 10 IICSLT_SSLT11: .equ 11 ; SCL Low Time Out Bits, bit 11 IICSLT_SSLT12: .equ 12 ; SCL Low Time Out Bits, bit 12 IICSLT_SSLT13: .equ 13 ; SCL Low Time Out Bits, bit 13 IICSLT_SSLT14: .equ 14 ; SCL Low Time Out Bits, bit 14 IICSLT_SSLT15: .equ 15 ; SCL Low Time Out Bits, bit 15 ; bit position masks mIICSLT_SSLT0: .equ %00000001 mIICSLT_SSLT1: .equ %00000010 mIICSLT_SSLT2: .equ %00000100 mIICSLT_SSLT3: .equ %00001000 mIICSLT_SSLT4: .equ %00010000 mIICSLT_SSLT5: .equ %00100000 mIICSLT_SSLT6: .equ %01000000 mIICSLT_SSLT7: .equ %10000000 mIICSLT_SSLT8: .equ %100000000 mIICSLT_SSLT9: .equ %1000000000 mIICSLT_SSLT10: .equ %10000000000 mIICSLT_SSLT11: .equ %100000000000 mIICSLT_SSLT12: .equ %1000000000000 mIICSLT_SSLT13: .equ %10000000000000 mIICSLT_SSLT14: .equ %100000000000000 mIICSLT_SSLT15: .equ %1000000000000000 ;*** IICSLTH - IIC SCL Low Time Out register - High byte; 0xFFFF8199 *** IICSLTH: .equ $FFFF8199 ;*** IICSLTH - IIC SCL Low Time Out register - High byte; 0xFFFF8199 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICSLTH_SSLT8: .equ 0 ; SCL Low Time Out Bit 8 IICSLTH_SSLT9: .equ 1 ; SCL Low Time Out Bit 9 IICSLTH_SSLT10: .equ 2 ; SCL Low Time Out Bit 10 IICSLTH_SSLT11: .equ 3 ; SCL Low Time Out Bit 11 IICSLTH_SSLT12: .equ 4 ; SCL Low Time Out Bit 12 IICSLTH_SSLT13: .equ 5 ; SCL Low Time Out Bit 13 IICSLTH_SSLT14: .equ 6 ; SCL Low Time Out Bit 14 IICSLTH_SSLT15: .equ 7 ; SCL Low Time Out Bit 15 ; bit position masks mIICSLTH_SSLT8: .equ %00000001 mIICSLTH_SSLT9: .equ %00000010 mIICSLTH_SSLT10: .equ %00000100 mIICSLTH_SSLT11: .equ %00001000 mIICSLTH_SSLT12: .equ %00010000 mIICSLTH_SSLT13: .equ %00100000 mIICSLTH_SSLT14: .equ %01000000 mIICSLTH_SSLT15: .equ %10000000 ;*** IICSLTL - IIC SCL Low Time Out register - Low byte; 0xFFFF819A *** IICSLTL: .equ $FFFF819A ;*** IICSLTL - IIC SCL Low Time Out register - Low byte; 0xFFFF819A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IICSLTL_SSLT0: .equ 0 ; SCL Low Time Out Bits, bit 0 IICSLTL_SSLT1: .equ 1 ; SCL Low Time Out Bits, bit 1 IICSLTL_SSLT2: .equ 2 ; SCL Low Time Out Bits, bit 2 IICSLTL_SSLT3: .equ 3 ; SCL Low Time Out Bits, bit 3 IICSLTL_SSLT4: .equ 4 ; SCL Low Time Out Bits, bit 4 IICSLTL_SSLT5: .equ 5 ; SCL Low Time Out Bits, bit 5 IICSLTL_SSLT6: .equ 6 ; SCL Low Time Out Bits, bit 6 IICSLTL_SSLT7: .equ 7 ; SCL Low Time Out Bits, bit 7 ; bit position masks mIICSLTL_SSLT0: .equ %00000001 mIICSLTL_SSLT1: .equ %00000010 mIICSLTL_SSLT2: .equ %00000100 mIICSLTL_SSLT3: .equ %00001000 mIICSLTL_SSLT4: .equ %00010000 mIICSLTL_SSLT5: .equ %00100000 mIICSLTL_SSLT6: .equ %01000000 mIICSLTL_SSLT7: .equ %10000000 ;*** SPI1C1 - SPI1 Control Register 1; 0xFFFF81A0 *** SPI1C1: .equ $FFFF81A0 ;*** SPI1C1 - SPI1 Control Register 1; 0xFFFF81A0 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI1C1_LSBFE: .equ 0 ; LSB First (Shifter Direction) SPI1C1_SSOE: .equ 1 ; Slave Select Output Enable SPI1C1_CPHA: .equ 2 ; Clock Phase SPI1C1_CPOL: .equ 3 ; Clock Polarity SPI1C1_MSTR: .equ 4 ; Master/Slave Mode Select SPI1C1_SPTIE: .equ 5 ; SPI Transmit Interrupt Enable SPI1C1_SPE: .equ 6 ; SPI System Enable SPI1C1_SPIE: .equ 7 ; SPI Interrupt Enable (for SPRF and MODF) ; bit position masks mSPI1C1_LSBFE: .equ %00000001 mSPI1C1_SSOE: .equ %00000010 mSPI1C1_CPHA: .equ %00000100 mSPI1C1_CPOL: .equ %00001000 mSPI1C1_MSTR: .equ %00010000 mSPI1C1_SPTIE: .equ %00100000 mSPI1C1_SPE: .equ %01000000 mSPI1C1_SPIE: .equ %10000000 ;*** SPI1C2 - SPI1 Control Register 2; 0xFFFF81A1 *** SPI1C2: .equ $FFFF81A1 ;*** SPI1C2 - SPI1 Control Register 2; 0xFFFF81A1 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI1C2_SPC0: .equ 0 ; SPI Pin Control 0 SPI1C2_SPISWAI: .equ 1 ; SPI Stop in Wait Mode SPI1C2_RXDMAE: .equ 2 ; Receive DMA Enable SPI1C2_BIDIROE: .equ 3 ; Bidirectional Mode Output Enable SPI1C2_MODFEN: .equ 4 ; Master Mode-Fault Function Enable SPI1C2_TXDMAE: .equ 5 ; Transmit DMA Enable SPI1C2_SPIMODE: .equ 6 ; SPI 8- or 16-bit Mode Select SPI1C2_SPMIE: .equ 7 ; SPI Match Interrupt Enable ; bit position masks mSPI1C2_SPC0: .equ %00000001 mSPI1C2_SPISWAI: .equ %00000010 mSPI1C2_RXDMAE: .equ %00000100 mSPI1C2_BIDIROE: .equ %00001000 mSPI1C2_MODFEN: .equ %00010000 mSPI1C2_TXDMAE: .equ %00100000 mSPI1C2_SPIMODE: .equ %01000000 mSPI1C2_SPMIE: .equ %10000000 ;*** SPI1BR - SPI1 Baud Rate Register; 0xFFFF81A2 *** SPI1BR: .equ $FFFF81A2 ;*** SPI1BR - SPI1 Baud Rate Register; 0xFFFF81A2 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI1BR_SPR0: .equ 0 ; SPI Baud Rate Divisor Bit 0 SPI1BR_SPR1: .equ 1 ; SPI Baud Rate Divisor Bit 1 SPI1BR_SPR2: .equ 2 ; SPI Baud Rate Divisor Bit 2 SPI1BR_SPR3: .equ 3 ; SPI Baud Rate Divisor Bit 3 SPI1BR_SPPR0: .equ 4 ; SPI Baud Rate Prescale Divisor Bit 0 SPI1BR_SPPR1: .equ 5 ; SPI Baud Rate Prescale Divisor Bit 1 SPI1BR_SPPR2: .equ 6 ; SPI Baud Rate Prescale Divisor Bit 2 ; bit position masks mSPI1BR_SPR0: .equ %00000001 mSPI1BR_SPR1: .equ %00000010 mSPI1BR_SPR2: .equ %00000100 mSPI1BR_SPR3: .equ %00001000 mSPI1BR_SPPR0: .equ %00010000 mSPI1BR_SPPR1: .equ %00100000 mSPI1BR_SPPR2: .equ %01000000 ;*** SPI1S - SPI1 Status Register; 0xFFFF81A3 *** SPI1S: .equ $FFFF81A3 ;*** SPI1S - SPI1 Status Register; 0xFFFF81A3 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI1S_MODF: .equ 4 ; Master Mode Fault Flag SPI1S_SPTEF: .equ 5 ; SPI Transmit Buffer Empty Flag SPI1S_SPMF: .equ 6 ; SPI Match Flag SPI1S_SPRF: .equ 7 ; SPI Read Buffer Full Flag ; bit position masks mSPI1S_MODF: .equ %00010000 mSPI1S_SPTEF: .equ %00100000 mSPI1S_SPMF: .equ %01000000 mSPI1S_SPRF: .equ %10000000 ;*** SPI1D16 - SPI1 Data Register; 0xFFFF81A4 *** SPI1D16: .equ $FFFF81A4 ;*** SPI1D16 - SPI1 Data Register; 0xFFFF81A4 *** ;*** SPI1DH - SPI1 Data Register High; 0xFFFF81A4 *** SPI1DH: .equ $FFFF81A4 ;*** SPI1DH - SPI1 Data Register High; 0xFFFF81A4 *** ;*** SPI1DL - SPI1 Data Register Low; 0xFFFF81A5 *** SPI1DL: .equ $FFFF81A5 ;*** SPI1DL - SPI1 Data Register Low; 0xFFFF81A5 *** ;*** SPI1D - SPI1 Data Register Low; 0xFFFF81A5 *** SPI1D: .equ $FFFF81A5 ;*** SPI1D - SPI1 Data Register Low; 0xFFFF81A5 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI1D_Bit0: .equ 0 ; SPI Data Bit 0 SPI1D_Bit1: .equ 1 ; SPI Data Bit 1 SPI1D_Bit2: .equ 2 ; SPI Data Bit 2 SPI1D_Bit3: .equ 3 ; SPI Data Bit 3 SPI1D_Bit4: .equ 4 ; SPI Data Bit 4 SPI1D_Bit5: .equ 5 ; SPI Data Bit 5 SPI1D_Bit6: .equ 6 ; SPI Data Bit 6 SPI1D_Bit7: .equ 7 ; SPI Data Bit 7 ; bit position masks mSPI1D_Bit0: .equ %00000001 mSPI1D_Bit1: .equ %00000010 mSPI1D_Bit2: .equ %00000100 mSPI1D_Bit3: .equ %00001000 mSPI1D_Bit4: .equ %00010000 mSPI1D_Bit5: .equ %00100000 mSPI1D_Bit6: .equ %01000000 mSPI1D_Bit7: .equ %10000000 ;*** SPI1M - SPI1 Match Register; 0xFFFF81A6 *** SPI1M: .equ $FFFF81A6 ;*** SPI1M - SPI1 Match Register; 0xFFFF81A6 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI1M_Bit0: .equ 0 ; SPI Match Value Bit 0 SPI1M_Bit1: .equ 1 ; SPI Match Value Bit 1 SPI1M_Bit2: .equ 2 ; SPI Match Value Bit 2 SPI1M_Bit3: .equ 3 ; SPI Match Value Bit 3 SPI1M_Bit4: .equ 4 ; SPI Match Value Bit 4 SPI1M_Bit5: .equ 5 ; SPI Match Value Bit 5 SPI1M_Bit6: .equ 6 ; SPI Match Value Bit 6 SPI1M_Bit7: .equ 7 ; SPI Match Value Bit 7 SPI1M_Bit8: .equ 8 ; SPI Match Value Bit 8 SPI1M_Bit9: .equ 9 ; SPI Match Value Bit 9 SPI1M_Bit10: .equ 10 ; SPI Match Value Bit 10 SPI1M_Bit11: .equ 11 ; SPI Match Value Bit 11 SPI1M_Bit12: .equ 12 ; SPI Match Value Bit 12 SPI1M_Bit13: .equ 13 ; SPI Match Value Bit 13 SPI1M_Bit14: .equ 14 ; SPI Match Value Bit 14 SPI1M_Bit15: .equ 15 ; SPI Match Value Bit 15 ; bit position masks mSPI1M_Bit0: .equ %00000001 mSPI1M_Bit1: .equ %00000010 mSPI1M_Bit2: .equ %00000100 mSPI1M_Bit3: .equ %00001000 mSPI1M_Bit4: .equ %00010000 mSPI1M_Bit5: .equ %00100000 mSPI1M_Bit6: .equ %01000000 mSPI1M_Bit7: .equ %10000000 mSPI1M_Bit8: .equ %100000000 mSPI1M_Bit9: .equ %1000000000 mSPI1M_Bit10: .equ %10000000000 mSPI1M_Bit11: .equ %100000000000 mSPI1M_Bit12: .equ %1000000000000 mSPI1M_Bit13: .equ %10000000000000 mSPI1M_Bit14: .equ %100000000000000 mSPI1M_Bit15: .equ %1000000000000000 ;*** SPI1MH - SPI1 Match Register High; 0xFFFF81A6 *** SPI1MH: .equ $FFFF81A6 ;*** SPI1MH - SPI1 Match Register High; 0xFFFF81A6 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI1MH_Bit8: .equ 0 ; SPI Match Value Bit 8 SPI1MH_Bit9: .equ 1 ; SPI Match Value Bit 9 SPI1MH_Bit10: .equ 2 ; SPI Match Value Bit 10 SPI1MH_Bit11: .equ 3 ; SPI Match Value Bit 11 SPI1MH_Bit12: .equ 4 ; SPI Match Value Bit 12 SPI1MH_Bit13: .equ 5 ; SPI Match Value Bit 13 SPI1MH_Bit14: .equ 6 ; SPI Match Value Bit 14 SPI1MH_Bit15: .equ 7 ; SPI Match Value Bit 15 ; bit position masks mSPI1MH_Bit8: .equ %00000001 mSPI1MH_Bit9: .equ %00000010 mSPI1MH_Bit10: .equ %00000100 mSPI1MH_Bit11: .equ %00001000 mSPI1MH_Bit12: .equ %00010000 mSPI1MH_Bit13: .equ %00100000 mSPI1MH_Bit14: .equ %01000000 mSPI1MH_Bit15: .equ %10000000 ;*** SPI1ML - SPI1 Match Register Low; 0xFFFF81A7 *** SPI1ML: .equ $FFFF81A7 ;*** SPI1ML - SPI1 Match Register Low; 0xFFFF81A7 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI1ML_Bit0: .equ 0 ; SPI Match Value Bit 0 SPI1ML_Bit1: .equ 1 ; SPI Match Value Bit 1 SPI1ML_Bit2: .equ 2 ; SPI Match Value Bit 2 SPI1ML_Bit3: .equ 3 ; SPI Match Value Bit 3 SPI1ML_Bit4: .equ 4 ; SPI Match Value Bit 4 SPI1ML_Bit5: .equ 5 ; SPI Match Value Bit 5 SPI1ML_Bit6: .equ 6 ; SPI Match Value Bit 6 SPI1ML_Bit7: .equ 7 ; SPI Match Value Bit 7 ; bit position masks mSPI1ML_Bit0: .equ %00000001 mSPI1ML_Bit1: .equ %00000010 mSPI1ML_Bit2: .equ %00000100 mSPI1ML_Bit3: .equ %00001000 mSPI1ML_Bit4: .equ %00010000 mSPI1ML_Bit5: .equ %00100000 mSPI1ML_Bit6: .equ %01000000 mSPI1ML_Bit7: .equ %10000000 ;*** SPI2C1 - SPI2 Control Register 1; 0xFFFF81A8 *** SPI2C1: .equ $FFFF81A8 ;*** SPI2C1 - SPI2 Control Register 1; 0xFFFF81A8 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI2C1_LSBFE: .equ 0 ; LSB First (Shifter Direction) SPI2C1_SSOE: .equ 1 ; Slave Select Output Enable SPI2C1_CPHA: .equ 2 ; Clock Phase SPI2C1_CPOL: .equ 3 ; Clock Polarity SPI2C1_MSTR: .equ 4 ; Master/Slave Mode Select SPI2C1_SPTIE: .equ 5 ; SPI Transmit Interrupt Enable SPI2C1_SPE: .equ 6 ; SPI System Enable SPI2C1_SPIE: .equ 7 ; SPI Interrupt Enable (for SPRF and MODF) ; bit position masks mSPI2C1_LSBFE: .equ %00000001 mSPI2C1_SSOE: .equ %00000010 mSPI2C1_CPHA: .equ %00000100 mSPI2C1_CPOL: .equ %00001000 mSPI2C1_MSTR: .equ %00010000 mSPI2C1_SPTIE: .equ %00100000 mSPI2C1_SPE: .equ %01000000 mSPI2C1_SPIE: .equ %10000000 ;*** SPI2C2 - SPI2 Control Register 2; 0xFFFF81A9 *** SPI2C2: .equ $FFFF81A9 ;*** SPI2C2 - SPI2 Control Register 2; 0xFFFF81A9 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI2C2_SPC0: .equ 0 ; SPI Pin Control 0 SPI2C2_SPISWAI: .equ 1 ; SPI Stop in Wait Mode SPI2C2_RXDMAE: .equ 2 ; Receive DMA Enable SPI2C2_BIDIROE: .equ 3 ; Bidirectional Mode Output Enable SPI2C2_MODFEN: .equ 4 ; Master Mode-Fault Function Enable SPI2C2_TXDMAE: .equ 5 ; Transmit DMA Enable SPI2C2_SPIMODE: .equ 6 ; SPI 8- or 16-bit Mode Select SPI2C2_SPMIE: .equ 7 ; SPI Match Interrupt Enable ; bit position masks mSPI2C2_SPC0: .equ %00000001 mSPI2C2_SPISWAI: .equ %00000010 mSPI2C2_RXDMAE: .equ %00000100 mSPI2C2_BIDIROE: .equ %00001000 mSPI2C2_MODFEN: .equ %00010000 mSPI2C2_TXDMAE: .equ %00100000 mSPI2C2_SPIMODE: .equ %01000000 mSPI2C2_SPMIE: .equ %10000000 ;*** SPI2BR - SPI2 Baud Rate Register; 0xFFFF81AA *** SPI2BR: .equ $FFFF81AA ;*** SPI2BR - SPI2 Baud Rate Register; 0xFFFF81AA *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI2BR_SPR0: .equ 0 ; SPI Baud Rate Divisor Bit 0 SPI2BR_SPR1: .equ 1 ; SPI Baud Rate Divisor Bit 1 SPI2BR_SPR2: .equ 2 ; SPI Baud Rate Divisor Bit 2 SPI2BR_SPR3: .equ 3 ; SPI Baud Rate Divisor Bit 3 SPI2BR_SPPR0: .equ 4 ; SPI Baud Rate Prescale Divisor Bit 0 SPI2BR_SPPR1: .equ 5 ; SPI Baud Rate Prescale Divisor Bit 1 SPI2BR_SPPR2: .equ 6 ; SPI Baud Rate Prescale Divisor Bit 2 ; bit position masks mSPI2BR_SPR0: .equ %00000001 mSPI2BR_SPR1: .equ %00000010 mSPI2BR_SPR2: .equ %00000100 mSPI2BR_SPR3: .equ %00001000 mSPI2BR_SPPR0: .equ %00010000 mSPI2BR_SPPR1: .equ %00100000 mSPI2BR_SPPR2: .equ %01000000 ;*** SPI2S - SPI2 Status Register; 0xFFFF81AB *** SPI2S: .equ $FFFF81AB ;*** SPI2S - SPI2 Status Register; 0xFFFF81AB *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI2S_MODF: .equ 4 ; Master Mode Fault Flag SPI2S_SPTEF: .equ 5 ; SPI Transmit Buffer Empty Flag SPI2S_SPMF: .equ 6 ; SPI Match Flag SPI2S_SPRF: .equ 7 ; SPI Read Buffer Full Flag ; bit position masks mSPI2S_MODF: .equ %00010000 mSPI2S_SPTEF: .equ %00100000 mSPI2S_SPMF: .equ %01000000 mSPI2S_SPRF: .equ %10000000 ;*** SPI2D16 - SPI2 Data Register; 0xFFFF81AC *** SPI2D16: .equ $FFFF81AC ;*** SPI2D16 - SPI2 Data Register; 0xFFFF81AC *** ;*** SPI2DH - SPI2 Data Register High; 0xFFFF81AC *** SPI2DH: .equ $FFFF81AC ;*** SPI2DH - SPI2 Data Register High; 0xFFFF81AC *** ;*** SPI2DL - SPI2 Data Register Low; 0xFFFF81AD *** SPI2DL: .equ $FFFF81AD ;*** SPI2DL - SPI2 Data Register Low; 0xFFFF81AD *** ;*** SPI2D - SPI2 Data Register Low; 0xFFFF81AD *** SPI2D: .equ $FFFF81AD ;*** SPI2D - SPI2 Data Register Low; 0xFFFF81AD *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI2D_Bit0: .equ 0 ; SPI Data Bit 0 SPI2D_Bit1: .equ 1 ; SPI Data Bit 1 SPI2D_Bit2: .equ 2 ; SPI Data Bit 2 SPI2D_Bit3: .equ 3 ; SPI Data Bit 3 SPI2D_Bit4: .equ 4 ; SPI Data Bit 4 SPI2D_Bit5: .equ 5 ; SPI Data Bit 5 SPI2D_Bit6: .equ 6 ; SPI Data Bit 6 SPI2D_Bit7: .equ 7 ; SPI Data Bit 7 ; bit position masks mSPI2D_Bit0: .equ %00000001 mSPI2D_Bit1: .equ %00000010 mSPI2D_Bit2: .equ %00000100 mSPI2D_Bit3: .equ %00001000 mSPI2D_Bit4: .equ %00010000 mSPI2D_Bit5: .equ %00100000 mSPI2D_Bit6: .equ %01000000 mSPI2D_Bit7: .equ %10000000 ;*** SPI2M - SPI2 Match Register; 0xFFFF81AE *** SPI2M: .equ $FFFF81AE ;*** SPI2M - SPI2 Match Register; 0xFFFF81AE *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI2M_Bit0: .equ 0 ; SPI Match Value Bit 0 SPI2M_Bit1: .equ 1 ; SPI Match Value Bit 1 SPI2M_Bit2: .equ 2 ; SPI Match Value Bit 2 SPI2M_Bit3: .equ 3 ; SPI Match Value Bit 3 SPI2M_Bit4: .equ 4 ; SPI Match Value Bit 4 SPI2M_Bit5: .equ 5 ; SPI Match Value Bit 5 SPI2M_Bit6: .equ 6 ; SPI Match Value Bit 6 SPI2M_Bit7: .equ 7 ; SPI Match Value Bit 7 SPI2M_Bit8: .equ 8 ; SPI Match Value Bit 8 SPI2M_Bit9: .equ 9 ; SPI Match Value Bit 9 SPI2M_Bit10: .equ 10 ; SPI Match Value Bit 10 SPI2M_Bit11: .equ 11 ; SPI Match Value Bit 11 SPI2M_Bit12: .equ 12 ; SPI Match Value Bit 12 SPI2M_Bit13: .equ 13 ; SPI Match Value Bit 13 SPI2M_Bit14: .equ 14 ; SPI Match Value Bit 14 SPI2M_Bit15: .equ 15 ; SPI Match Value Bit 15 ; bit position masks mSPI2M_Bit0: .equ %00000001 mSPI2M_Bit1: .equ %00000010 mSPI2M_Bit2: .equ %00000100 mSPI2M_Bit3: .equ %00001000 mSPI2M_Bit4: .equ %00010000 mSPI2M_Bit5: .equ %00100000 mSPI2M_Bit6: .equ %01000000 mSPI2M_Bit7: .equ %10000000 mSPI2M_Bit8: .equ %100000000 mSPI2M_Bit9: .equ %1000000000 mSPI2M_Bit10: .equ %10000000000 mSPI2M_Bit11: .equ %100000000000 mSPI2M_Bit12: .equ %1000000000000 mSPI2M_Bit13: .equ %10000000000000 mSPI2M_Bit14: .equ %100000000000000 mSPI2M_Bit15: .equ %1000000000000000 ;*** SPI2MH - SPI2 Match Register High; 0xFFFF81AE *** SPI2MH: .equ $FFFF81AE ;*** SPI2MH - SPI2 Match Register High; 0xFFFF81AE *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI2MH_Bit8: .equ 0 ; SPI Match Value Bit 8 SPI2MH_Bit9: .equ 1 ; SPI Match Value Bit 9 SPI2MH_Bit10: .equ 2 ; SPI Match Value Bit 10 SPI2MH_Bit11: .equ 3 ; SPI Match Value Bit 11 SPI2MH_Bit12: .equ 4 ; SPI Match Value Bit 12 SPI2MH_Bit13: .equ 5 ; SPI Match Value Bit 13 SPI2MH_Bit14: .equ 6 ; SPI Match Value Bit 14 SPI2MH_Bit15: .equ 7 ; SPI Match Value Bit 15 ; bit position masks mSPI2MH_Bit8: .equ %00000001 mSPI2MH_Bit9: .equ %00000010 mSPI2MH_Bit10: .equ %00000100 mSPI2MH_Bit11: .equ %00001000 mSPI2MH_Bit12: .equ %00010000 mSPI2MH_Bit13: .equ %00100000 mSPI2MH_Bit14: .equ %01000000 mSPI2MH_Bit15: .equ %10000000 ;*** SPI2ML - SPI2 Match Register Low; 0xFFFF81AF *** SPI2ML: .equ $FFFF81AF ;*** SPI2ML - SPI2 Match Register Low; 0xFFFF81AF *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPI2ML_Bit0: .equ 0 ; SPI Match Value Bit 0 SPI2ML_Bit1: .equ 1 ; SPI Match Value Bit 1 SPI2ML_Bit2: .equ 2 ; SPI Match Value Bit 2 SPI2ML_Bit3: .equ 3 ; SPI Match Value Bit 3 SPI2ML_Bit4: .equ 4 ; SPI Match Value Bit 4 SPI2ML_Bit5: .equ 5 ; SPI Match Value Bit 5 SPI2ML_Bit6: .equ 6 ; SPI Match Value Bit 6 SPI2ML_Bit7: .equ 7 ; SPI Match Value Bit 7 ; bit position masks mSPI2ML_Bit0: .equ %00000001 mSPI2ML_Bit1: .equ %00000010 mSPI2ML_Bit2: .equ %00000100 mSPI2ML_Bit3: .equ %00001000 mSPI2ML_Bit4: .equ %00010000 mSPI2ML_Bit5: .equ %00100000 mSPI2ML_Bit6: .equ %01000000 mSPI2ML_Bit7: .equ %10000000 ;*** HSCMP1CR0 - HSCMP1 Control Register 0; 0xFFFF81B0 *** HSCMP1CR0: .equ $FFFF81B0 ;*** HSCMP1CR0 - HSCMP1 Control Register 0; 0xFFFF81B0 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET HSCMP1CR0_MMC0: .equ 0 ; Minus Input Mux Control, bit 0 HSCMP1CR0_MMC1: .equ 1 ; Minus Input Mux Control, bit 1 HSCMP1CR0_PMC0: .equ 2 ; Positive Input Mux Control, bit 0 HSCMP1CR0_PMC1: .equ 3 ; Positive Input Mux Control, bit 1 HSCMP1CR0_FILTER_CNT0: .equ 4 ; Filter Sample Count, bit 0 HSCMP1CR0_FILTER_CNT1: .equ 5 ; Filter Sample Count, bit 1 HSCMP1CR0_FILTER_CNT2: .equ 6 ; Filter Sample Count, bit 2 ; bit position masks mHSCMP1CR0_MMC0: .equ %00000001 mHSCMP1CR0_MMC1: .equ %00000010 mHSCMP1CR0_PMC0: .equ %00000100 mHSCMP1CR0_PMC1: .equ %00001000 mHSCMP1CR0_FILTER_CNT0: .equ %00010000 mHSCMP1CR0_FILTER_CNT1: .equ %00100000 mHSCMP1CR0_FILTER_CNT2: .equ %01000000 ;*** HSCMP1CR1 - HSCMP1 Control Register 1; 0xFFFF81B1 *** HSCMP1CR1: .equ $FFFF81B1 ;*** HSCMP1CR1 - HSCMP1 Control Register 1; 0xFFFF81B1 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET HSCMP1CR1_EN: .equ 0 ; Comparator Module Enable HSCMP1CR1_OPE: .equ 1 ; Comparator Output Pin Enable HSCMP1CR1_COS: .equ 2 ; Comparator Output Select HSCMP1CR1_INV: .equ 3 ; Comparator INVERT HSCMP1CR1_PMODE: .equ 4 ; Power Mode Select HSCMP1CR1_WE: .equ 6 ; Windowing Enable HSCMP1CR1_SE: .equ 7 ; Sample Enable ; bit position masks mHSCMP1CR1_EN: .equ %00000001 mHSCMP1CR1_OPE: .equ %00000010 mHSCMP1CR1_COS: .equ %00000100 mHSCMP1CR1_INV: .equ %00001000 mHSCMP1CR1_PMODE: .equ %00010000 mHSCMP1CR1_WE: .equ %01000000 mHSCMP1CR1_SE: .equ %10000000 ;*** HSCMP1FPR - HSCMP1 Filter Period Register; 0xFFFF81B2 *** HSCMP1FPR: .equ $FFFF81B2 ;*** HSCMP1FPR - HSCMP1 Filter Period Register; 0xFFFF81B2 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET HSCMP1FPR_FILT_PER0: .equ 0 ; Filter Period, bit 0 HSCMP1FPR_FILT_PER1: .equ 1 ; Filter Period, bit 1 HSCMP1FPR_FILT_PER2: .equ 2 ; Filter Period, bit 2 HSCMP1FPR_FILT_PER3: .equ 3 ; Filter Period, bit 3 HSCMP1FPR_FILT_PER4: .equ 4 ; Filter Period, bit 4 HSCMP1FPR_FILT_PER5: .equ 5 ; Filter Period, bit 5 HSCMP1FPR_FILT_PER6: .equ 6 ; Filter Period, bit 6 HSCMP1FPR_FILT_PER7: .equ 7 ; Filter Period, bit 7 ; bit position masks mHSCMP1FPR_FILT_PER0: .equ %00000001 mHSCMP1FPR_FILT_PER1: .equ %00000010 mHSCMP1FPR_FILT_PER2: .equ %00000100 mHSCMP1FPR_FILT_PER3: .equ %00001000 mHSCMP1FPR_FILT_PER4: .equ %00010000 mHSCMP1FPR_FILT_PER5: .equ %00100000 mHSCMP1FPR_FILT_PER6: .equ %01000000 mHSCMP1FPR_FILT_PER7: .equ %10000000 ;*** HSCMP1SCR - HSCMP1 Status & Control Register; 0xFFFF81B3 *** HSCMP1SCR: .equ $FFFF81B3 ;*** HSCMP1SCR - HSCMP1 Status & Control Register; 0xFFFF81B3 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET HSCMP1SCR_COUT: .equ 0 ; Analog Comparator Output HSCMP1SCR_CFF: .equ 1 ; Analog Comparator Flag Falling HSCMP1SCR_CFR: .equ 2 ; Analog Comparator Flag Rising HSCMP1SCR_IEF: .equ 3 ; Comparator Interrupt Enable Falling HSCMP1SCR_IER: .equ 4 ; Comparator Interrupt Enable Rising HSCMP1SCR_SMLEB: .equ 5 ; Stop Mode Edge / Level Interrupt Control HSCMP1SCR_DMAEN: .equ 6 ; DMA enable control ; bit position masks mHSCMP1SCR_COUT: .equ %00000001 mHSCMP1SCR_CFF: .equ %00000010 mHSCMP1SCR_CFR: .equ %00000100 mHSCMP1SCR_IEF: .equ %00001000 mHSCMP1SCR_IER: .equ %00010000 mHSCMP1SCR_SMLEB: .equ %00100000 mHSCMP1SCR_DMAEN: .equ %01000000 ;*** HSCMP1PCR - Pin Control Register; 0xFFFF81B4 *** HSCMP1PCR: .equ $FFFF81B4 ;*** HSCMP1PCR - Pin Control Register; 0xFFFF81B4 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET HSCMP1PCR_INMPE1: .equ 0 ; Minus Input Pin 1 Enable HSCMP1PCR_INMPE2: .equ 1 ; Minus Input Pin 2 Enable HSCMP1PCR_INMPE3: .equ 2 ; Minus Input Pin 3 Enable HSCMP1PCR_INMPE4: .equ 3 ; Minus Input Pin 4 Enable HSCMP1PCR_INPPE1: .equ 4 ; Positive Input Pin 1 Enable HSCMP1PCR_INPPE2: .equ 5 ; Positive Input Pin 2 Enable HSCMP1PCR_INPPE3: .equ 6 ; Positive Input Pin 3 Enable HSCMP1PCR_INPPE4: .equ 7 ; Positive Input Pin 4 Enable ; bit position masks mHSCMP1PCR_INMPE1: .equ %00000001 mHSCMP1PCR_INMPE2: .equ %00000010 mHSCMP1PCR_INMPE3: .equ %00000100 mHSCMP1PCR_INMPE4: .equ %00001000 mHSCMP1PCR_INPPE1: .equ %00010000 mHSCMP1PCR_INPPE2: .equ %00100000 mHSCMP1PCR_INPPE3: .equ %01000000 mHSCMP1PCR_INPPE4: .equ %10000000 ;*** HSCMP2CR0 - HSCMP2 Control Register 0; 0xFFFF81B8 *** HSCMP2CR0: .equ $FFFF81B8 ;*** HSCMP2CR0 - HSCMP2 Control Register 0; 0xFFFF81B8 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET HSCMP2CR0_MMC0: .equ 0 ; Minus Input Mux Control, bit 0 HSCMP2CR0_MMC1: .equ 1 ; Minus Input Mux Control, bit 1 HSCMP2CR0_PMC0: .equ 2 ; Positive Input Mux Control, bit 0 HSCMP2CR0_PMC1: .equ 3 ; Positive Input Mux Control, bit 1 HSCMP2CR0_FILTER_CNT0: .equ 4 ; Filter Sample Count, bit 0 HSCMP2CR0_FILTER_CNT1: .equ 5 ; Filter Sample Count, bit 1 HSCMP2CR0_FILTER_CNT2: .equ 6 ; Filter Sample Count, bit 2 ; bit position masks mHSCMP2CR0_MMC0: .equ %00000001 mHSCMP2CR0_MMC1: .equ %00000010 mHSCMP2CR0_PMC0: .equ %00000100 mHSCMP2CR0_PMC1: .equ %00001000 mHSCMP2CR0_FILTER_CNT0: .equ %00010000 mHSCMP2CR0_FILTER_CNT1: .equ %00100000 mHSCMP2CR0_FILTER_CNT2: .equ %01000000 ;*** HSCMP2CR1 - HSCMP2 Control Register 1; 0xFFFF81B9 *** HSCMP2CR1: .equ $FFFF81B9 ;*** HSCMP2CR1 - HSCMP2 Control Register 1; 0xFFFF81B9 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET HSCMP2CR1_EN: .equ 0 ; Comparator Module Enable HSCMP2CR1_OPE: .equ 1 ; Comparator Output Pin Enable HSCMP2CR1_COS: .equ 2 ; Comparator Output Select HSCMP2CR1_INV: .equ 3 ; Comparator INVERT HSCMP2CR1_PMODE: .equ 4 ; Power Mode Select HSCMP2CR1_WE: .equ 6 ; Windowing Enable HSCMP2CR1_SE: .equ 7 ; Sample Enable ; bit position masks mHSCMP2CR1_EN: .equ %00000001 mHSCMP2CR1_OPE: .equ %00000010 mHSCMP2CR1_COS: .equ %00000100 mHSCMP2CR1_INV: .equ %00001000 mHSCMP2CR1_PMODE: .equ %00010000 mHSCMP2CR1_WE: .equ %01000000 mHSCMP2CR1_SE: .equ %10000000 ;*** HSCMP2FPR - HSCMP2 Filter Period Register; 0xFFFF81BA *** HSCMP2FPR: .equ $FFFF81BA ;*** HSCMP2FPR - HSCMP2 Filter Period Register; 0xFFFF81BA *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET HSCMP2FPR_FILT_PER0: .equ 0 ; Filter Period, bit 0 HSCMP2FPR_FILT_PER1: .equ 1 ; Filter Period, bit 1 HSCMP2FPR_FILT_PER2: .equ 2 ; Filter Period, bit 2 HSCMP2FPR_FILT_PER3: .equ 3 ; Filter Period, bit 3 HSCMP2FPR_FILT_PER4: .equ 4 ; Filter Period, bit 4 HSCMP2FPR_FILT_PER5: .equ 5 ; Filter Period, bit 5 HSCMP2FPR_FILT_PER6: .equ 6 ; Filter Period, bit 6 HSCMP2FPR_FILT_PER7: .equ 7 ; Filter Period, bit 7 ; bit position masks mHSCMP2FPR_FILT_PER0: .equ %00000001 mHSCMP2FPR_FILT_PER1: .equ %00000010 mHSCMP2FPR_FILT_PER2: .equ %00000100 mHSCMP2FPR_FILT_PER3: .equ %00001000 mHSCMP2FPR_FILT_PER4: .equ %00010000 mHSCMP2FPR_FILT_PER5: .equ %00100000 mHSCMP2FPR_FILT_PER6: .equ %01000000 mHSCMP2FPR_FILT_PER7: .equ %10000000 ;*** HSCMP2SCR - HSCMP2 Status & Control Register; 0xFFFF81BB *** HSCMP2SCR: .equ $FFFF81BB ;*** HSCMP2SCR - HSCMP2 Status & Control Register; 0xFFFF81BB *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET HSCMP2SCR_COUT: .equ 0 ; Analog Comparator Output HSCMP2SCR_CFF: .equ 1 ; Analog Comparator Flag Falling HSCMP2SCR_CFR: .equ 2 ; Analog Comparator Flag Rising HSCMP2SCR_IEF: .equ 3 ; Comparator Interrupt Enable Falling HSCMP2SCR_IER: .equ 4 ; Comparator Interrupt Enable Rising HSCMP2SCR_SMLEB: .equ 5 ; Stop Mode Edge / Level Interrupt Control HSCMP2SCR_DMAEN: .equ 6 ; DMA enable control ; bit position masks mHSCMP2SCR_COUT: .equ %00000001 mHSCMP2SCR_CFF: .equ %00000010 mHSCMP2SCR_CFR: .equ %00000100 mHSCMP2SCR_IEF: .equ %00001000 mHSCMP2SCR_IER: .equ %00010000 mHSCMP2SCR_SMLEB: .equ %00100000 mHSCMP2SCR_DMAEN: .equ %01000000 ;*** HSCMP2PCR - Pin Control Register; 0xFFFF81BC *** HSCMP2PCR: .equ $FFFF81BC ;*** HSCMP2PCR - Pin Control Register; 0xFFFF81BC *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET HSCMP2PCR_INMPE1: .equ 0 ; Minus Input Pin 1 Enable HSCMP2PCR_INMPE2: .equ 1 ; Minus Input Pin 2 Enable HSCMP2PCR_INMPE3: .equ 2 ; Minus Input Pin 3 Enable HSCMP2PCR_INMPE4: .equ 3 ; Minus Input Pin 4 Enable HSCMP2PCR_INPPE1: .equ 4 ; Positive Input Pin 1 Enable HSCMP2PCR_INPPE2: .equ 5 ; Positive Input Pin 2 Enable HSCMP2PCR_INPPE3: .equ 6 ; Positive Input Pin 3 Enable HSCMP2PCR_INPPE4: .equ 7 ; Positive Input Pin 4 Enable ; bit position masks mHSCMP2PCR_INMPE1: .equ %00000001 mHSCMP2PCR_INMPE2: .equ %00000010 mHSCMP2PCR_INMPE3: .equ %00000100 mHSCMP2PCR_INMPE4: .equ %00001000 mHSCMP2PCR_INPPE1: .equ %00010000 mHSCMP2PCR_INPPE2: .equ %00100000 mHSCMP2PCR_INPPE3: .equ %01000000 mHSCMP2PCR_INPPE4: .equ %10000000 ;*** SRS - System Reset Status Register; 0xFFFF9800 *** SRS: .equ $FFFF9800 ;*** SRS - System Reset Status Register; 0xFFFF9800 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SRS_LVD: .equ 1 ; Low Voltage Detect SRS_WDOG: .equ 2 ; Watchdog timer reset SRS_ILAD: .equ 3 ; Illegal Address SRS_ILOP: .equ 4 ; Illegal Opcode SRS_LOC: .equ 5 ; Lose-the-clock Reset SRS_PIN: .equ 6 ; External Reset Pin SRS_POR: .equ 7 ; Power-On Reset ; bit position masks mSRS_LVD: .equ %00000010 mSRS_WDOG: .equ %00000100 mSRS_ILAD: .equ %00001000 mSRS_ILOP: .equ %00010000 mSRS_LOC: .equ %00100000 mSRS_PIN: .equ %01000000 mSRS_POR: .equ %10000000 ;*** SOPT1 - System Options Register 1; 0xFFFF9802 *** SOPT1: .equ $FFFF9802 ;*** SOPT1 - System Options Register 1; 0xFFFF9802 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SOPT1_WAITE: .equ 4 ; WAIT Mode Enable SOPT1_STOPE: .equ 5 ; Stop Mode Enable ; bit position masks mSOPT1_WAITE: .equ %00010000 mSOPT1_STOPE: .equ %00100000 ;*** SMCLK - System MCLK Control Register; 0xFFFF9803 *** SMCLK: .equ $FFFF9803 ;*** SMCLK - System MCLK Control Register; 0xFFFF9803 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SMCLK_MCSEL0: .equ 0 ; MCLK Divide Select, bit 0 SMCLK_MCSEL1: .equ 1 ; MCLK Divide Select, bit 1 SMCLK_MCSEL2: .equ 2 ; MCLK Divide Select, bit 2 SMCLK_MPE: .equ 4 ; MCLK Pin Enable ; bit position masks mSMCLK_MCSEL0: .equ %00000001 mSMCLK_MCSEL1: .equ %00000010 mSMCLK_MCSEL2: .equ %00000100 mSMCLK_MPE: .equ %00010000 ;*** SDID - System Device Identification Register; 0xFFFF9806 *** SDID: .equ $FFFF9806 ;*** SDID - System Device Identification Register; 0xFFFF9806 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SDID_ID0: .equ 0 ; Part Identification Number, bit 0 SDID_ID1: .equ 1 ; Part Identification Number, bit 1 SDID_ID2: .equ 2 ; Part Identification Number, bit 2 SDID_ID3: .equ 3 ; Part Identification Number, bit 3 SDID_ID4: .equ 4 ; Part Identification Number, bit 4 SDID_ID5: .equ 5 ; Part Identification Number, bit 5 SDID_ID6: .equ 6 ; Part Identification Number, bit 6 SDID_ID7: .equ 7 ; Part Identification Number, bit 7 SDID_ID8: .equ 8 ; Part Identification Number, bit 8 SDID_ID9: .equ 9 ; Part Identification Number, bit 9 SDID_ID10: .equ 10 ; Part Identification Number, bit 10 SDID_ID11: .equ 11 ; Part Identification Number, bit 11 ; bit position masks mSDID_ID0: .equ %00000001 mSDID_ID1: .equ %00000010 mSDID_ID2: .equ %00000100 mSDID_ID3: .equ %00001000 mSDID_ID4: .equ %00010000 mSDID_ID5: .equ %00100000 mSDID_ID6: .equ %01000000 mSDID_ID7: .equ %10000000 mSDID_ID8: .equ %100000000 mSDID_ID9: .equ %1000000000 mSDID_ID10: .equ %10000000000 mSDID_ID11: .equ %100000000000 ;*** SDIDH - System Device Identification Register High; 0xFFFF9806 *** SDIDH: .equ $FFFF9806 ;*** SDIDH - System Device Identification Register High; 0xFFFF9806 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SDIDH_ID8: .equ 0 ; Part Identification Number, bit 8 SDIDH_ID9: .equ 1 ; Part Identification Number, bit 9 SDIDH_ID10: .equ 2 ; Part Identification Number, bit 10 SDIDH_ID11: .equ 3 ; Part Identification Number, bit 11 ; bit position masks mSDIDH_ID8: .equ %00000001 mSDIDH_ID9: .equ %00000010 mSDIDH_ID10: .equ %00000100 mSDIDH_ID11: .equ %00001000 ;*** SDIDL - System Device Identification Register Low; 0xFFFF9807 *** SDIDL: .equ $FFFF9807 ;*** SDIDL - System Device Identification Register Low; 0xFFFF9807 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SDIDL_ID0: .equ 0 ; Part Identification Number, bit 0 SDIDL_ID1: .equ 1 ; Part Identification Number, bit 1 SDIDL_ID2: .equ 2 ; Part Identification Number, bit 2 SDIDL_ID3: .equ 3 ; Part Identification Number, bit 3 SDIDL_ID4: .equ 4 ; Part Identification Number, bit 4 SDIDL_ID5: .equ 5 ; Part Identification Number, bit 5 SDIDL_ID6: .equ 6 ; Part Identification Number, bit 6 SDIDL_ID7: .equ 7 ; Part Identification Number, bit 7 ; bit position masks mSDIDL_ID0: .equ %00000001 mSDIDL_ID1: .equ %00000010 mSDIDL_ID2: .equ %00000100 mSDIDL_ID3: .equ %00001000 mSDIDL_ID4: .equ %00010000 mSDIDL_ID5: .equ %00100000 mSDIDL_ID6: .equ %01000000 mSDIDL_ID7: .equ %10000000 ;*** SPMSC1 - System Power Management Status and Control 1 Register; 0xFFFF9809 *** SPMSC1: .equ $FFFF9809 ;*** SPMSC1 - System Power Management Status and Control 1 Register; 0xFFFF9809 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPMSC1_BGBE: .equ 0 ; Bandgap Buffer Enable SPMSC1_LVDE: .equ 2 ; Low-Voltage Detect Enable SPMSC1_LVDSE: .equ 3 ; Low-Voltage Detect Stop Enable SPMSC1_LVDRE: .equ 4 ; Low-Voltage Detect Reset Enable SPMSC1_LVWIE: .equ 5 ; Low-Voltage Warning Interrupt Enable SPMSC1_LVWACK: .equ 6 ; Low-Voltage Warning Acknowledge SPMSC1_LVWF: .equ 7 ; Low-Voltage Warning status ; bit position masks mSPMSC1_BGBE: .equ %00000001 mSPMSC1_LVDE: .equ %00000100 mSPMSC1_LVDSE: .equ %00001000 mSPMSC1_LVDRE: .equ %00010000 mSPMSC1_LVWIE: .equ %00100000 mSPMSC1_LVWACK: .equ %01000000 mSPMSC1_LVWF: .equ %10000000 ;*** SPMSC2 - System Power Management Status and Control 2 Register; 0xFFFF980A *** SPMSC2: .equ $FFFF980A ;*** SPMSC2 - System Power Management Status and Control 2 Register; 0xFFFF980A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPMSC2_PPDC: .equ 0 ; Partial Power Down Control SPMSC2_PPDACK: .equ 2 ; Partial Power Down Acknowledge SPMSC2_PPDF: .equ 3 ; Partial Power Down Flag SPMSC2_LVWV: .equ 4 ; Low-Voltage Warning Voltage Select SPMSC2_LVDV: .equ 5 ; Low-Voltage Detect Voltage Select ; bit position masks mSPMSC2_PPDC: .equ %00000001 mSPMSC2_PPDACK: .equ %00000100 mSPMSC2_PPDF: .equ %00001000 mSPMSC2_LVWV: .equ %00010000 mSPMSC2_LVDV: .equ %00100000 ;*** SOPT2 - System Options Register 2; 0xFFFF980C *** SOPT2: .equ $FFFF980C ;*** SOPT2 - System Options Register 2; 0xFFFF980C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SOPT2_ADHWTS0: .equ 0 ; ADC Hardware Trigger Source, bit 0 SOPT2_ADHWTS1: .equ 1 ; ADC Hardware Trigger Source, bit 1 SOPT2_ACIC1: .equ 2 ; Analog Comparator 1 to Input Capture Enable SOPT2_TPMCCFG: .equ 3 ; TPM Clock Configuration SOPT2_ACIC2: .equ 4 ; Analog Comparator 2 to Input Capture Enable SOPT2_FTM1SYNC: .equ 5 ; FTM1 synchronization trigger SOPT2_FTM2SYNC: .equ 6 ; FTM2 synchronization trigger SOPT2_CME: .equ 7 ; ICS External reference clock monitor ; bit position masks mSOPT2_ADHWTS0: .equ %00000001 mSOPT2_ADHWTS1: .equ %00000010 mSOPT2_ACIC1: .equ %00000100 mSOPT2_TPMCCFG: .equ %00001000 mSOPT2_ACIC2: .equ %00010000 mSOPT2_FTM1SYNC: .equ %00100000 mSOPT2_FTM2SYNC: .equ %01000000 mSOPT2_CME: .equ %10000000 ;*** SCGC1 - System Clock Gating Control 1 Register; 0xFFFF980D *** SCGC1: .equ $FFFF980D ;*** SCGC1 - System Clock Gating Control 1 Register; 0xFFFF980D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCGC1_SCI1: .equ 0 ; SCI1 Clock Gate Control SCGC1_SCI2: .equ 1 ; SCI2 Clock Gate Control SCGC1_IIC: .equ 2 ; IIC Clock Gate Control SCGC1_DMA: .equ 3 ; DMA Clock Gate Control SCGC1_ADC: .equ 4 ; ADC Clock Gate Control SCGC1_FTM1: .equ 5 ; FTM1 Clock Gate Control SCGC1_FTM2: .equ 6 ; FTM2 Clock Gate Control SCGC1_TPM3: .equ 7 ; TPM3 Clock Gate Control ; bit position masks mSCGC1_SCI1: .equ %00000001 mSCGC1_SCI2: .equ %00000010 mSCGC1_IIC: .equ %00000100 mSCGC1_DMA: .equ %00001000 mSCGC1_ADC: .equ %00010000 mSCGC1_FTM1: .equ %00100000 mSCGC1_FTM2: .equ %01000000 mSCGC1_TPM3: .equ %10000000 ;*** SCGC2 - System Clock Gating Control 2 Register; 0xFFFF980E *** SCGC2: .equ $FFFF980E ;*** SCGC2 - System Clock Gating Control 2 Register; 0xFFFF980E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCGC2_SPI1: .equ 0 ; SPI1 Clock Gate Control SCGC2_SPI2: .equ 1 ; SPI2 Clock Gate Control SCGC2_RTC: .equ 2 ; RTC Clock Gate Control SCGC2_iEVT: .equ 3 ; iEVENT Clock Gate Control SCGC2_PDB: .equ 4 ; PDB Clock Gate Control SCGC2_IRQ: .equ 5 ; IRQ Clock Gate Control SCGC2_FLS: .equ 6 ; FTSR Clock Gate Control SCGC2_CRC: .equ 7 ; CRC Clock Gate Control ; bit position masks mSCGC2_SPI1: .equ %00000001 mSCGC2_SPI2: .equ %00000010 mSCGC2_RTC: .equ %00000100 mSCGC2_iEVT: .equ %00001000 mSCGC2_PDB: .equ %00010000 mSCGC2_IRQ: .equ %00100000 mSCGC2_FLS: .equ %01000000 mSCGC2_CRC: .equ %10000000 ;*** SCGC3 - System Clock Gating Control 3 Register; 0xFFFF980F *** SCGC3: .equ $FFFF980F ;*** SCGC3 - System Clock Gating Control 3 Register; 0xFFFF980F *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SCGC3_EWM: .equ 0 ; EWM Clock Gate Control SCGC3_DAC1: .equ 1 ; DAC1 Clock Gate Control SCGC3_DAC2: .equ 2 ; DAC2 Clock Gate Control SCGC3_HSCMP1: .equ 3 ; HSCMP1 Clock Gate Control SCGC3_HSCMP2: .equ 4 ; HSCMP2 Clock Gate Control ; bit position masks mSCGC3_EWM: .equ %00000001 mSCGC3_DAC1: .equ %00000010 mSCGC3_DAC2: .equ %00000100 mSCGC3_HSCMP1: .equ %00001000 mSCGC3_HSCMP2: .equ %00010000 ;*** FCDIV - FLASH Clock Divider Register; 0xFFFF9820 *** FCDIV: .equ $FFFF9820 ;*** FCDIV - FLASH Clock Divider Register; 0xFFFF9820 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FCDIV_FDIV0: .equ 0 ; Divisor for FLASH Clock Divider, bit 0 FCDIV_FDIV1: .equ 1 ; Divisor for FLASH Clock Divider, bit 1 FCDIV_FDIV2: .equ 2 ; Divisor for FLASH Clock Divider, bit 2 FCDIV_FDIV3: .equ 3 ; Divisor for FLASH Clock Divider, bit 3 FCDIV_FDIV4: .equ 4 ; Divisor for FLASH Clock Divider, bit 4 FCDIV_FDIV5: .equ 5 ; Divisor for FLASH Clock Divider, bit 5 FCDIV_PRDIV8: .equ 6 ; Prescale (Divide) FLASH Clock by 8 FCDIV_FDIVLD: .equ 7 ; Divisor Loaded Status Flag ; bit position masks mFCDIV_FDIV0: .equ %00000001 mFCDIV_FDIV1: .equ %00000010 mFCDIV_FDIV2: .equ %00000100 mFCDIV_FDIV3: .equ %00001000 mFCDIV_FDIV4: .equ %00010000 mFCDIV_FDIV5: .equ %00100000 mFCDIV_PRDIV8: .equ %01000000 mFCDIV_FDIVLD: .equ %10000000 ;*** FOPT - Flash Options Register; 0xFFFF9821 *** FOPT: .equ $FFFF9821 ;*** FOPT - Flash Options Register; 0xFFFF9821 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FOPT_SEC0: .equ 0 ; Flash Security Bit 0 FOPT_SEC1: .equ 1 ; Flash Security Bit 1 FOPT_KEYEN0: .equ 6 ; Backdoor Key Security Enable Bit 0 FOPT_KEYEN1: .equ 7 ; Backdoor Key Security Enable Bit 1 ; bit position masks mFOPT_SEC0: .equ %00000001 mFOPT_SEC1: .equ %00000010 mFOPT_KEYEN0: .equ %01000000 mFOPT_KEYEN1: .equ %10000000 ;*** FCNFG - Flash Configuration Register; 0xFFFF9823 *** FCNFG: .equ $FFFF9823 ;*** FCNFG - Flash Configuration Register; 0xFFFF9823 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FCNFG_KEYACC: .equ 5 ; Enable Security Key Writing ; bit position masks mFCNFG_KEYACC: .equ %00100000 ;*** FPROT - Flash Protection Register; 0xFFFF9824 *** FPROT: .equ $FFFF9824 ;*** FPROT - Flash Protection Register; 0xFFFF9824 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FPROT_FPOPEN: .equ 0 ; Flash Protection Open FPROT_FPS0: .equ 1 ; Flash Protection Size, bit 0 FPROT_FPS1: .equ 2 ; Flash Protection Size, bit 1 FPROT_FPS2: .equ 3 ; Flash Protection Size, bit 2 FPROT_FPS3: .equ 4 ; Flash Protection Size, bit 3 FPROT_FPS4: .equ 5 ; Flash Protection Size, bit 4 FPROT_FPS5: .equ 6 ; Flash Protection Size, bit 5 FPROT_FPS6: .equ 7 ; Flash Protection Size, bit 6 ; bit position masks mFPROT_FPOPEN: .equ %00000001 mFPROT_FPS0: .equ %00000010 mFPROT_FPS1: .equ %00000100 mFPROT_FPS2: .equ %00001000 mFPROT_FPS3: .equ %00010000 mFPROT_FPS4: .equ %00100000 mFPROT_FPS5: .equ %01000000 mFPROT_FPS6: .equ %10000000 ;*** FSTAT - Flash Status Register; 0xFFFF9825 *** FSTAT: .equ $FFFF9825 ;*** FSTAT - Flash Status Register; 0xFFFF9825 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FSTAT_FBLANK: .equ 2 ; FLASH Flag Indicating the Erase Verify Operation Status FSTAT_FACCERR: .equ 4 ; FLASH Access Error Flag FSTAT_FPVIOL: .equ 5 ; FLASH Protection Violation Flag FSTAT_FCCF: .equ 6 ; FLASH Command Complete Interrupt Flag FSTAT_FCBEF: .equ 7 ; FLASH Command Buffer Empty Flag ; bit position masks mFSTAT_FBLANK: .equ %00000100 mFSTAT_FACCERR: .equ %00010000 mFSTAT_FPVIOL: .equ %00100000 mFSTAT_FCCF: .equ %01000000 mFSTAT_FCBEF: .equ %10000000 ;*** FCMD - Flash Command Register; 0xFFFF9826 *** FCMD: .equ $FFFF9826 ;*** FCMD - Flash Command Register; 0xFFFF9826 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET FCMD_FCMD0: .equ 0 ; Flash Command, bit 0 FCMD_FCMD1: .equ 1 ; Flash Command, bit 1 FCMD_FCMD2: .equ 2 ; Flash Command, bit 2 FCMD_FCMD3: .equ 3 ; Flash Command, bit 3 FCMD_FCMD4: .equ 4 ; Flash Command, bit 4 FCMD_FCMD5: .equ 5 ; Flash Command, bit 5 FCMD_FCMD6: .equ 6 ; Flash Command, bit 6 ; bit position masks mFCMD_FCMD0: .equ %00000001 mFCMD_FCMD1: .equ %00000010 mFCMD_FCMD2: .equ %00000100 mFCMD_FCMD3: .equ %00001000 mFCMD_FCMD4: .equ %00010000 mFCMD_FCMD5: .equ %00100000 mFCMD_FCMD6: .equ %01000000 ;*** SAPE1 - System ADC Pin Enable 1 Register; 0xFFFF9831 *** SAPE1: .equ $FFFF9831 ;*** SAPE1 - System ADC Pin Enable 1 Register; 0xFFFF9831 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SAPE1_ADPC0: .equ 0 ; ADC Pin Control 0 SAPE1_ADPC1: .equ 1 ; ADC Pin Control 1 SAPE1_ADPC2: .equ 2 ; ADC Pin Control 2 SAPE1_ADPC3: .equ 3 ; ADC Pin Control 3 SAPE1_ADPC4: .equ 4 ; ADC Pin Control 4 SAPE1_ADPC5: .equ 5 ; ADC Pin Control 5 SAPE1_ADPC6: .equ 6 ; ADC Pin Control 6 SAPE1_ADPC7: .equ 7 ; ADC Pin Control 7 ; bit position masks mSAPE1_ADPC0: .equ %00000001 mSAPE1_ADPC1: .equ %00000010 mSAPE1_ADPC2: .equ %00000100 mSAPE1_ADPC3: .equ %00001000 mSAPE1_ADPC4: .equ %00010000 mSAPE1_ADPC5: .equ %00100000 mSAPE1_ADPC6: .equ %01000000 mSAPE1_ADPC7: .equ %10000000 ;*** SAPE2 - System ADC Pin Enable 2 Register; 0xFFFF9832 *** SAPE2: .equ $FFFF9832 ;*** SAPE2 - System ADC Pin Enable 2 Register; 0xFFFF9832 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SAPE2_ADPC8: .equ 0 ; ADC Pin Control 8 SAPE2_ADPC9: .equ 1 ; ADC Pin Control 9 SAPE2_ADPC10: .equ 2 ; ADC Pin Control 10 SAPE2_ADPC11: .equ 3 ; ADC Pin Control 11 SAPE2_ADPC12: .equ 4 ; ADC Pin Control 12 SAPE2_ADPC13: .equ 5 ; ADC Pin Control 13 SAPE2_ADPC14: .equ 6 ; ADC Pin Control 14 SAPE2_ADPC15: .equ 7 ; ADC Pin Control 15 ; bit position masks mSAPE2_ADPC8: .equ %00000001 mSAPE2_ADPC9: .equ %00000010 mSAPE2_ADPC10: .equ %00000100 mSAPE2_ADPC11: .equ %00001000 mSAPE2_ADPC12: .equ %00010000 mSAPE2_ADPC13: .equ %00100000 mSAPE2_ADPC14: .equ %01000000 mSAPE2_ADPC15: .equ %10000000 ;*** SAPE3 - System ADC Pin Enable 3 Register; 0xFFFF9833 *** SAPE3: .equ $FFFF9833 ;*** SAPE3 - System ADC Pin Enable 3 Register; 0xFFFF9833 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SAPE3_ADPC16: .equ 0 ; ADC Pin Control 16 SAPE3_ADPC17: .equ 1 ; ADC Pin Control 17 SAPE3_ADPC18: .equ 2 ; ADC Pin Control 18 SAPE3_ADPC19: .equ 3 ; ADC Pin Control 19 SAPE3_ADPC20: .equ 4 ; ADC Pin Control 20 SAPE3_ADPC21: .equ 5 ; ADC Pin Control 21 SAPE3_ADPC22: .equ 6 ; ADC Pin Control 22 SAPE3_ADPC23: .equ 7 ; ADC Pin Control 23 ; bit position masks mSAPE3_ADPC16: .equ %00000001 mSAPE3_ADPC17: .equ %00000010 mSAPE3_ADPC18: .equ %00000100 mSAPE3_ADPC19: .equ %00001000 mSAPE3_ADPC20: .equ %00010000 mSAPE3_ADPC21: .equ %00100000 mSAPE3_ADPC22: .equ %01000000 mSAPE3_ADPC23: .equ %10000000 ;*** SEIS1 - System eGPIO Interrupt Status 1 Register; 0xFFFF9834 *** SEIS1: .equ $FFFF9834 ;*** SEIS1 - System eGPIO Interrupt Status 1 Register; 0xFFFF9834 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SEIS1_PTA: .equ 0 ; PORT A Interrupt Status SEIS1_PTB: .equ 1 ; PORT B Interrupt Status SEIS1_PTC: .equ 2 ; PORT C Interrupt Status SEIS1_PTD: .equ 3 ; PORT D Interrupt Status SEIS1_PTE: .equ 4 ; PORT E Interrupt Status ; bit position masks mSEIS1_PTA: .equ %00000001 mSEIS1_PTB: .equ %00000010 mSEIS1_PTC: .equ %00000100 mSEIS1_PTD: .equ %00001000 mSEIS1_PTE: .equ %00010000 ;*** SEIS2 - System eGPIO Interrupt Status 2 Register; 0xFFFF9835 *** SEIS2: .equ $FFFF9835 ;*** SEIS2 - System eGPIO Interrupt Status 2 Register; 0xFFFF9835 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SEIS2_PTF: .equ 0 ; PORTF Interrupt Status SEIS2_PTG: .equ 1 ; PORTG Interrupt Status SEIS2_PTH: .equ 2 ; PORTH Interrupt Status SEIS2_PTJ: .equ 3 ; PORTJ Interrupt Status ; bit position masks mSEIS2_PTF: .equ %00000001 mSEIS2_PTG: .equ %00000010 mSEIS2_PTH: .equ %00000100 mSEIS2_PTJ: .equ %00001000 ;*** SPINPS - System Pin Positioning Register; 0xFFFF9836 *** SPINPS: .equ $FFFF9836 ;*** SPINPS - System Pin Positioning Register; 0xFFFF9836 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SPINPS_TPM3CH0: .equ 0 ; TPM3 Channel 0 Pin Control SPINPS_TPM3CH1: .equ 1 ; TPM3 Channel 1 Pin Control SPINPS_FTM2CH2: .equ 2 ; FTM2 Channel 2 Pin Control SPINPS_FTM2CH3: .equ 3 ; FTM2 Channel 3 Pin Control SPINPS_FTM2CH4: .equ 4 ; FTM2 Channel 4 Pin Control SPINPS_FTM2CH5: .equ 5 ; FTM2 Channel 5 Pin Control ; bit position masks mSPINPS_TPM3CH0: .equ %00000001 mSPINPS_TPM3CH1: .equ %00000010 mSPINPS_FTM2CH2: .equ %00000100 mSPINPS_FTM2CH3: .equ %00001000 mSPINPS_FTM2CH4: .equ %00010000 mSPINPS_FTM2CH5: .equ %00100000 ;*** SIMPTA - System Port A Input Buffer Enable Register; 0xFFFF9837 *** SIMPTA: .equ $FFFF9837 ;*** SIMPTA - System Port A Input Buffer Enable Register; 0xFFFF9837 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SIMPTA_SIMPTA0: .equ 0 ; PTA0 Input Buffer Control SIMPTA_SIMPTA1: .equ 1 ; PTA1 Input Buffer Control SIMPTA_SIMPTA2: .equ 2 ; PTA2 Input Buffer Control SIMPTA_SIMPTA3: .equ 3 ; PTA3 Input Buffer Control SIMPTA_SIMPTA4: .equ 4 ; PTA4 Input Buffer Control SIMPTA_SIMPTA5: .equ 5 ; PTA5 Input Buffer Control SIMPTA_SIMPTA6: .equ 6 ; PTA6 Input Buffer Control SIMPTA_SIMPTA7: .equ 7 ; PTA7 Input Buffer Control ; bit position masks mSIMPTA_SIMPTA0: .equ %00000001 mSIMPTA_SIMPTA1: .equ %00000010 mSIMPTA_SIMPTA2: .equ %00000100 mSIMPTA_SIMPTA3: .equ %00001000 mSIMPTA_SIMPTA4: .equ %00010000 mSIMPTA_SIMPTA5: .equ %00100000 mSIMPTA_SIMPTA6: .equ %01000000 mSIMPTA_SIMPTA7: .equ %10000000 ;*** SIMPTB - System Port B Input Buffer Enable Register; 0xFFFF9838 *** SIMPTB: .equ $FFFF9838 ;*** SIMPTB - System Port B Input Buffer Enable Register; 0xFFFF9838 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SIMPTB_SIMPTB0: .equ 0 ; PTB0 Input Buffer Control SIMPTB_SIMPTB1: .equ 1 ; PTB1 Input Buffer Control SIMPTB_SIMPTB2: .equ 2 ; PTB2 Input Buffer Control SIMPTB_SIMPTB3: .equ 3 ; PTB3 Input Buffer Control SIMPTB_SIMPTB4: .equ 4 ; PTB4 Input Buffer Control SIMPTB_SIMPTB5: .equ 5 ; PTB5 Input Buffer Control SIMPTB_SIMPTB6: .equ 6 ; PTB6 Input Buffer Control SIMPTB_SIMPTB7: .equ 7 ; PTB7 Input Buffer Control ; bit position masks mSIMPTB_SIMPTB0: .equ %00000001 mSIMPTB_SIMPTB1: .equ %00000010 mSIMPTB_SIMPTB2: .equ %00000100 mSIMPTB_SIMPTB3: .equ %00001000 mSIMPTB_SIMPTB4: .equ %00010000 mSIMPTB_SIMPTB5: .equ %00100000 mSIMPTB_SIMPTB6: .equ %01000000 mSIMPTB_SIMPTB7: .equ %10000000 ;*** SIMPTC - System Port C Input Buffer Enable Register; 0xFFFF9839 *** SIMPTC: .equ $FFFF9839 ;*** SIMPTC - System Port C Input Buffer Enable Register; 0xFFFF9839 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SIMPTC_SIMPTC0: .equ 0 ; PTC0 Input Buffer Control SIMPTC_SIMPTC1: .equ 1 ; PTC1 Input Buffer Control SIMPTC_SIMPTC2: .equ 2 ; PTC2 Input Buffer Control SIMPTC_SIMPTC3: .equ 3 ; PTC3 Input Buffer Control SIMPTC_SIMPTC4: .equ 4 ; PTC4 Input Buffer Control SIMPTC_SIMPTC5: .equ 5 ; PTC5 Input Buffer Control SIMPTC_SIMPTC6: .equ 6 ; PTC6 Input Buffer Control ; bit position masks mSIMPTC_SIMPTC0: .equ %00000001 mSIMPTC_SIMPTC1: .equ %00000010 mSIMPTC_SIMPTC2: .equ %00000100 mSIMPTC_SIMPTC3: .equ %00001000 mSIMPTC_SIMPTC4: .equ %00010000 mSIMPTC_SIMPTC5: .equ %00100000 mSIMPTC_SIMPTC6: .equ %01000000 ;*** SIMPTD - System Port D Input Buffer Enable Register; 0xFFFF983A *** SIMPTD: .equ $FFFF983A ;*** SIMPTD - System Port D Input Buffer Enable Register; 0xFFFF983A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SIMPTD_SIMPTD0: .equ 0 ; PTD0 Input Buffer Control SIMPTD_SIMPTD1: .equ 1 ; PTD1 Input Buffer Control SIMPTD_SIMPTD2: .equ 2 ; PTD2 Input Buffer Control SIMPTD_SIMPTD3: .equ 3 ; PTD3 Input Buffer Control SIMPTD_SIMPTD4: .equ 4 ; PTD4 Input Buffer Control SIMPTD_SIMPTD5: .equ 5 ; PTD5 Input Buffer Control SIMPTD_SIMPTD6: .equ 6 ; PTD6 Input Buffer Control SIMPTD_SIMPTD7: .equ 7 ; PTD7 Input Buffer Control ; bit position masks mSIMPTD_SIMPTD0: .equ %00000001 mSIMPTD_SIMPTD1: .equ %00000010 mSIMPTD_SIMPTD2: .equ %00000100 mSIMPTD_SIMPTD3: .equ %00001000 mSIMPTD_SIMPTD4: .equ %00010000 mSIMPTD_SIMPTD5: .equ %00100000 mSIMPTD_SIMPTD6: .equ %01000000 mSIMPTD_SIMPTD7: .equ %10000000 ;*** SIMPTE - System Port E Input Buffer Enable Register; 0xFFFF983B *** SIMPTE: .equ $FFFF983B ;*** SIMPTE - System Port E Input Buffer Enable Register; 0xFFFF983B *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SIMPTE_SIMPTE0: .equ 0 ; PTE0 Input Buffer Control SIMPTE_SIMPTE1: .equ 1 ; PTE1 Input Buffer Control SIMPTE_SIMPTE2: .equ 2 ; PTE2 Input Buffer Control SIMPTE_SIMPTE3: .equ 3 ; PTE3 Input Buffer Control SIMPTE_SIMPTE4: .equ 4 ; PTE4 Input Buffer Control SIMPTE_SIMPTE5: .equ 5 ; PTE5 Input Buffer Control SIMPTE_SIMPTE6: .equ 6 ; PTE6 Input Buffer Control SIMPTE_SIMPTE7: .equ 7 ; PTE7 Input Buffer Control ; bit position masks mSIMPTE_SIMPTE0: .equ %00000001 mSIMPTE_SIMPTE1: .equ %00000010 mSIMPTE_SIMPTE2: .equ %00000100 mSIMPTE_SIMPTE3: .equ %00001000 mSIMPTE_SIMPTE4: .equ %00010000 mSIMPTE_SIMPTE5: .equ %00100000 mSIMPTE_SIMPTE6: .equ %01000000 mSIMPTE_SIMPTE7: .equ %10000000 ;*** SIMPTF - System Port F Input Buffer Enable Register; 0xFFFF983C *** SIMPTF: .equ $FFFF983C ;*** SIMPTF - System Port F Input Buffer Enable Register; 0xFFFF983C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SIMPTF_SIMPTF0: .equ 0 ; PTF0 Input Buffer Control SIMPTF_SIMPTF1: .equ 1 ; PTF1 Input Buffer Control SIMPTF_SIMPTF2: .equ 2 ; PTF2 Input Buffer Control SIMPTF_SIMPTF3: .equ 3 ; PTF3 Input Buffer Control SIMPTF_SIMPTF4: .equ 4 ; PTF4 Input Buffer Control SIMPTF_SIMPTF5: .equ 5 ; PTF5 Input Buffer Control SIMPTF_SIMPTF6: .equ 6 ; PTF6 Input Buffer Control SIMPTF_SIMPTF7: .equ 7 ; PTF7 Input Buffer Control ; bit position masks mSIMPTF_SIMPTF0: .equ %00000001 mSIMPTF_SIMPTF1: .equ %00000010 mSIMPTF_SIMPTF2: .equ %00000100 mSIMPTF_SIMPTF3: .equ %00001000 mSIMPTF_SIMPTF4: .equ %00010000 mSIMPTF_SIMPTF5: .equ %00100000 mSIMPTF_SIMPTF6: .equ %01000000 mSIMPTF_SIMPTF7: .equ %10000000 ;*** SIMPTG - System Port G Input Buffer Enable Register; 0xFFFF983D *** SIMPTG: .equ $FFFF983D ;*** SIMPTG - System Port G Input Buffer Enable Register; 0xFFFF983D *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SIMPTG_SIMPTG0: .equ 0 ; PTG0 Input Buffer Control SIMPTG_SIMPTG1: .equ 1 ; PTG1 Input Buffer Control SIMPTG_SIMPTG2: .equ 2 ; PTG2 Input Buffer Control SIMPTG_SIMPTG3: .equ 3 ; PTG3 Input Buffer Control SIMPTG_SIMPTG4: .equ 4 ; PTG4 Input Buffer Control SIMPTG_SIMPTG5: .equ 5 ; PTG5 Input Buffer Control SIMPTG_SIMPTG6: .equ 6 ; PTG6 Input Buffer Control ; bit position masks mSIMPTG_SIMPTG0: .equ %00000001 mSIMPTG_SIMPTG1: .equ %00000010 mSIMPTG_SIMPTG2: .equ %00000100 mSIMPTG_SIMPTG3: .equ %00001000 mSIMPTG_SIMPTG4: .equ %00010000 mSIMPTG_SIMPTG5: .equ %00100000 mSIMPTG_SIMPTG6: .equ %01000000 ;*** SIMPTH - System Port H Input Buffer Enable Register; 0xFFFF983E *** SIMPTH: .equ $FFFF983E ;*** SIMPTH - System Port H Input Buffer Enable Register; 0xFFFF983E *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SIMPTH_SIMPTH0: .equ 0 ; PTH0 Input Buffer Control SIMPTH_SIMPTH1: .equ 1 ; PTH1 Input Buffer Control SIMPTH_SIMPTH2: .equ 2 ; PTH2 Input Buffer Control SIMPTH_SIMPTH3: .equ 3 ; PTH3 Input Buffer Control SIMPTH_SIMPTH4: .equ 4 ; PTH4 Input Buffer Control SIMPTH_SIMPTH5: .equ 5 ; PTH5 Input Buffer Control SIMPTH_SIMPTH6: .equ 6 ; PTH6 Input Buffer Control ; bit position masks mSIMPTH_SIMPTH0: .equ %00000001 mSIMPTH_SIMPTH1: .equ %00000010 mSIMPTH_SIMPTH2: .equ %00000100 mSIMPTH_SIMPTH3: .equ %00001000 mSIMPTH_SIMPTH4: .equ %00010000 mSIMPTH_SIMPTH5: .equ %00100000 mSIMPTH_SIMPTH6: .equ %01000000 ;*** SIMPTJ - System Port J Input Buffer Enable Register; 0xFFFF983F *** SIMPTJ: .equ $FFFF983F ;*** SIMPTJ - System Port J Input Buffer Enable Register; 0xFFFF983F *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SIMPTJ_SIMPTJ0: .equ 0 ; PTJ0 Input Buffer Control SIMPTJ_SIMPTJ1: .equ 1 ; PTJ1 Input Buffer Control SIMPTJ_SIMPTJ2: .equ 2 ; PTJ2 Input Buffer Control SIMPTJ_SIMPTJ3: .equ 3 ; PTJ3 Input Buffer Control SIMPTJ_SIMPTJ4: .equ 4 ; PTJ4 Input Buffer Control SIMPTJ_SIMPTJ5: .equ 5 ; PTJ5 Input Buffer Control SIMPTJ_SIMPTJ6: .equ 6 ; PTJ6 Input Buffer Control SIMPTJ_SIMPTJ7: .equ 7 ; PTJ7 Input Buffer Control ; bit position masks mSIMPTJ_SIMPTJ0: .equ %00000001 mSIMPTJ_SIMPTJ1: .equ %00000010 mSIMPTJ_SIMPTJ2: .equ %00000100 mSIMPTJ_SIMPTJ3: .equ %00001000 mSIMPTJ_SIMPTJ4: .equ %00010000 mSIMPTJ_SIMPTJ5: .equ %00100000 mSIMPTJ_SIMPTJ6: .equ %01000000 mSIMPTJ_SIMPTJ7: .equ %10000000 ;*** EWMCTRL - EWM Control Register; 0xFFFF9840 *** EWMCTRL: .equ $FFFF9840 ;*** EWMCTRL - EWM Control Register; 0xFFFF9840 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET EWMCTRL_EWMEN: .equ 0 ; Module enable EWMCTRL_ASSIN: .equ 1 ; EWM_in assert state invert EWMCTRL_INEN: .equ 2 ; EWM_in enable ; bit position masks mEWMCTRL_EWMEN: .equ %00000001 mEWMCTRL_ASSIN: .equ %00000010 mEWMCTRL_INEN: .equ %00000100 ;*** EWMSERV - EWM Service Register; 0xFFFF9841 *** EWMSERV: .equ $FFFF9841 ;*** EWMSERV - EWM Service Register; 0xFFFF9841 *** ;*** EWMCMPL - EWM Compare Low Register; 0xFFFF9842 *** EWMCMPL: .equ $FFFF9842 ;*** EWMCMPL - EWM Compare Low Register; 0xFFFF9842 *** ;*** EWMCMPH - EWM Compare High Register; 0xFFFF9843 *** EWMCMPH: .equ $FFFF9843 ;*** EWMCMPH - EWM Compare High Register; 0xFFFF9843 *** ;*** IRQSC - Interrupt request status and control register; 0xFFFF9844 *** IRQSC: .equ $FFFF9844 ;*** IRQSC - Interrupt request status and control register; 0xFFFF9844 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IRQSC_IRQMOD: .equ 0 ; IRQ Detection Mode IRQSC_IRQIE: .equ 1 ; IRQ Interrupt Enable IRQSC_IRQACK: .equ 2 ; IRQ Acknowledge IRQSC_IRQF: .equ 3 ; IRQ Flag IRQSC_IRQPE: .equ 4 ; IRQ Pin Enable IRQSC_IRQEDG: .equ 5 ; IRQ Edge Select IRQSC_IRQPDD: .equ 6 ; IRQ Pull Device Disable ; bit position masks mIRQSC_IRQMOD: .equ %00000001 mIRQSC_IRQIE: .equ %00000010 mIRQSC_IRQACK: .equ %00000100 mIRQSC_IRQF: .equ %00001000 mIRQSC_IRQPE: .equ %00010000 mIRQSC_IRQEDG: .equ %00100000 mIRQSC_IRQPDD: .equ %01000000 ;*** CRCH - CRC High Register; 0xFFFF9850 *** CRCH: .equ $FFFF9850 ;*** CRCH - CRC High Register; 0xFFFF9850 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET CRCH_BIT8: .equ 0 ; High byte of CRC register ,bit 8 CRCH_BIT9: .equ 1 ; High byte of CRC register ,bit 9 CRCH_BIT10: .equ 2 ; High byte of CRC register ,bit 10 CRCH_BIT11: .equ 3 ; High byte of CRC register ,bit 11 CRCH_BIT12: .equ 4 ; High byte of CRC register ,bit 12 CRCH_BIT13: .equ 5 ; High byte of CRC register ,bit 13 CRCH_BIT14: .equ 6 ; High byte of CRC register ,bit 14 CRCH_BIT15: .equ 7 ; High byte of CRC register ,bit 15 ; bit position masks mCRCH_BIT8: .equ %00000001 mCRCH_BIT9: .equ %00000010 mCRCH_BIT10: .equ %00000100 mCRCH_BIT11: .equ %00001000 mCRCH_BIT12: .equ %00010000 mCRCH_BIT13: .equ %00100000 mCRCH_BIT14: .equ %01000000 mCRCH_BIT15: .equ %10000000 ;*** CRCL - CRC Low Register; 0xFFFF9851 *** CRCL: .equ $FFFF9851 ;*** CRCL - CRC Low Register; 0xFFFF9851 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET CRCL_BIT0: .equ 0 ; Low byte of CRC register, bit 0 CRCL_BIT1: .equ 1 ; Low byte of CRC register, bit 1 CRCL_BIT2: .equ 2 ; Low byte of CRC register, bit 2 CRCL_BIT3: .equ 3 ; Low byte of CRC register, bit 3 CRCL_BIT4: .equ 4 ; Low byte of CRC register, bit 4 CRCL_BIT5: .equ 5 ; Low byte of CRC register, bit 5 CRCL_BIT6: .equ 6 ; Low byte of CRC register, bit 6 CRCL_BIT7: .equ 7 ; Low byte of CRC register, bit 7 ; bit position masks mCRCL_BIT0: .equ %00000001 mCRCL_BIT1: .equ %00000010 mCRCL_BIT2: .equ %00000100 mCRCL_BIT3: .equ %00001000 mCRCL_BIT4: .equ %00010000 mCRCL_BIT5: .equ %00100000 mCRCL_BIT6: .equ %01000000 mCRCL_BIT7: .equ %10000000 ;*** TRANSPOSE - CRC Transpose Register; 0xFFFF9852 *** TRANSPOSE: .equ $FFFF9852 ;*** TRANSPOSE - CRC Transpose Register; 0xFFFF9852 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET TRANSPOSE_BIT0: .equ 0 ; CRC transpose register, bit 0 TRANSPOSE_BIT1: .equ 1 ; CRC transpose register, bit 1 TRANSPOSE_BIT2: .equ 2 ; CRC transpose register, bit 2 TRANSPOSE_BIT3: .equ 3 ; CRC transpose register, bit 3 TRANSPOSE_BIT4: .equ 4 ; CRC transpose register, bit 4 TRANSPOSE_BIT5: .equ 5 ; CRC transpose register, bit 5 TRANSPOSE_BIT6: .equ 6 ; CRC transpose register, bit 6 TRANSPOSE_BIT7: .equ 7 ; CRC transpose register, bit 7 ; bit position masks mTRANSPOSE_BIT0: .equ %00000001 mTRANSPOSE_BIT1: .equ %00000010 mTRANSPOSE_BIT2: .equ %00000100 mTRANSPOSE_BIT3: .equ %00001000 mTRANSPOSE_BIT4: .equ %00010000 mTRANSPOSE_BIT5: .equ %00100000 mTRANSPOSE_BIT6: .equ %01000000 mTRANSPOSE_BIT7: .equ %10000000 ;*** CRCL0 - CRC Low Register 0; 0xFFFF9854 *** CRCL0: .equ $FFFF9854 ;*** CRCL0 - CRC Low Register 0; 0xFFFF9854 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET CRCL0_BIT0: .equ 0 ; Low byte of CRC register, bit 0 CRCL0_BIT1: .equ 1 ; Low byte of CRC register, bit 1 CRCL0_BIT2: .equ 2 ; Low byte of CRC register, bit 2 CRCL0_BIT3: .equ 3 ; Low byte of CRC register, bit 3 CRCL0_BIT4: .equ 4 ; Low byte of CRC register, bit 4 CRCL0_BIT5: .equ 5 ; Low byte of CRC register, bit 5 CRCL0_BIT6: .equ 6 ; Low byte of CRC register, bit 6 CRCL0_BIT7: .equ 7 ; Low byte of CRC register, bit 7 ; bit position masks mCRCL0_BIT0: .equ %00000001 mCRCL0_BIT1: .equ %00000010 mCRCL0_BIT2: .equ %00000100 mCRCL0_BIT3: .equ %00001000 mCRCL0_BIT4: .equ %00010000 mCRCL0_BIT5: .equ %00100000 mCRCL0_BIT6: .equ %01000000 mCRCL0_BIT7: .equ %10000000 ;*** CRCL1 - CRC Low Register 1; 0xFFFF9855 *** CRCL1: .equ $FFFF9855 ;*** CRCL1 - CRC Low Register 1; 0xFFFF9855 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET CRCL1_BIT0: .equ 0 ; Low byte of CRC register, bit 0 CRCL1_BIT1: .equ 1 ; Low byte of CRC register, bit 1 CRCL1_BIT2: .equ 2 ; Low byte of CRC register, bit 2 CRCL1_BIT3: .equ 3 ; Low byte of CRC register, bit 3 CRCL1_BIT4: .equ 4 ; Low byte of CRC register, bit 4 CRCL1_BIT5: .equ 5 ; Low byte of CRC register, bit 5 CRCL1_BIT6: .equ 6 ; Low byte of CRC register, bit 6 CRCL1_BIT7: .equ 7 ; Low byte of CRC register, bit 7 ; bit position masks mCRCL1_BIT0: .equ %00000001 mCRCL1_BIT1: .equ %00000010 mCRCL1_BIT2: .equ %00000100 mCRCL1_BIT3: .equ %00001000 mCRCL1_BIT4: .equ %00010000 mCRCL1_BIT5: .equ %00100000 mCRCL1_BIT6: .equ %01000000 mCRCL1_BIT7: .equ %10000000 ;*** CRCL2 - CRC Low Register 2; 0xFFFF9856 *** CRCL2: .equ $FFFF9856 ;*** CRCL2 - CRC Low Register 2; 0xFFFF9856 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET CRCL2_BIT0: .equ 0 ; Low byte of CRC register, bit 0 CRCL2_BIT1: .equ 1 ; Low byte of CRC register, bit 1 CRCL2_BIT2: .equ 2 ; Low byte of CRC register, bit 2 CRCL2_BIT3: .equ 3 ; Low byte of CRC register, bit 3 CRCL2_BIT4: .equ 4 ; Low byte of CRC register, bit 4 CRCL2_BIT5: .equ 5 ; Low byte of CRC register, bit 5 CRCL2_BIT6: .equ 6 ; Low byte of CRC register, bit 6 CRCL2_BIT7: .equ 7 ; Low byte of CRC register, bit 7 ; bit position masks mCRCL2_BIT0: .equ %00000001 mCRCL2_BIT1: .equ %00000010 mCRCL2_BIT2: .equ %00000100 mCRCL2_BIT3: .equ %00001000 mCRCL2_BIT4: .equ %00010000 mCRCL2_BIT5: .equ %00100000 mCRCL2_BIT6: .equ %01000000 mCRCL2_BIT7: .equ %10000000 ;*** CRCL3 - CRC Low Register 3; 0xFFFF9857 *** CRCL3: .equ $FFFF9857 ;*** CRCL3 - CRC Low Register 3; 0xFFFF9857 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET CRCL3_BIT0: .equ 0 ; Low byte of CRC register, bit 0 CRCL3_BIT1: .equ 1 ; Low byte of CRC register, bit 1 CRCL3_BIT2: .equ 2 ; Low byte of CRC register, bit 2 CRCL3_BIT3: .equ 3 ; Low byte of CRC register, bit 3 CRCL3_BIT4: .equ 4 ; Low byte of CRC register, bit 4 CRCL3_BIT5: .equ 5 ; Low byte of CRC register, bit 5 CRCL3_BIT6: .equ 6 ; Low byte of CRC register, bit 6 CRCL3_BIT7: .equ 7 ; Low byte of CRC register, bit 7 ; bit position masks mCRCL3_BIT0: .equ %00000001 mCRCL3_BIT1: .equ %00000010 mCRCL3_BIT2: .equ %00000100 mCRCL3_BIT3: .equ %00001000 mCRCL3_BIT4: .equ %00010000 mCRCL3_BIT5: .equ %00100000 mCRCL3_BIT6: .equ %01000000 mCRCL3_BIT7: .equ %10000000 ;*** PDBCTRL1 - PDB Control 1 Register; 0xFFFF9860 *** PDBCTRL1: .equ $FFFF9860 ;*** PDBCTRL1 - PDB Control 1 Register; 0xFFFF9860 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PDBCTRL1_LDOK: .equ 0 ; Load OK PDBCTRL1_ENA: .equ 1 ; Trigger A Enable PDBCTRL1_AOS0: .equ 2 ; Trigger A Output Select, bit 0 PDBCTRL1_AOS1: .equ 3 ; Trigger A Output Select, bit 1 PDBCTRL1_ENB: .equ 4 ; Trigger B Enable PDBCTRL1_BOS0: .equ 5 ; Trigger B Output Select, bit 0 PDBCTRL1_BOS1: .equ 6 ; Trigger B Output Select, bit 1 PDBCTRL1_LDMOD: .equ 7 ; Load mode select ; bit position masks mPDBCTRL1_LDOK: .equ %00000001 mPDBCTRL1_ENA: .equ %00000010 mPDBCTRL1_AOS0: .equ %00000100 mPDBCTRL1_AOS1: .equ %00001000 mPDBCTRL1_ENB: .equ %00010000 mPDBCTRL1_BOS0: .equ %00100000 mPDBCTRL1_BOS1: .equ %01000000 mPDBCTRL1_LDMOD: .equ %10000000 ;*** PDBCTRL2 - PDB Control 2 Register; 0xFFFF9861 *** PDBCTRL2: .equ $FFFF9861 ;*** PDBCTRL2 - PDB Control 2 Register; 0xFFFF9861 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PDBCTRL2_SWTRIG: .equ 0 ; Software Trigger PDBCTRL2_CONT: .equ 1 ; Continuous Mode Enable PDBCTRL2_TRIGSEL0: .equ 2 ; Input Trigger, bit 0 PDBCTRL2_TRIGSEL1: .equ 3 ; Input Trigger, bit 1 PDBCTRL2_TRIGSEL2: .equ 4 ; Input Trigger, bit 2 PDBCTRL2_PRESCALER0: .equ 5 ; Clock Prescaler, bit 0 PDBCTRL2_PRESCALER1: .equ 6 ; Clock Prescaler, bit 1 PDBCTRL2_PRESCALER2: .equ 7 ; Clock Prescaler, bit 2 ; bit position masks mPDBCTRL2_SWTRIG: .equ %00000001 mPDBCTRL2_CONT: .equ %00000010 mPDBCTRL2_TRIGSEL0: .equ %00000100 mPDBCTRL2_TRIGSEL1: .equ %00001000 mPDBCTRL2_TRIGSEL2: .equ %00010000 mPDBCTRL2_PRESCALER0: .equ %00100000 mPDBCTRL2_PRESCALER1: .equ %01000000 mPDBCTRL2_PRESCALER2: .equ %10000000 ;*** PDBDLYA - PDB Delay A Register; 0xFFFF9862 *** PDBDLYA: .equ $FFFF9862 ;*** PDBDLYA - PDB Delay A Register; 0xFFFF9862 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PDBDLYA_DELAYA0: .equ 0 ; Delay A, bit 0 PDBDLYA_DELAYA1: .equ 1 ; Delay A, bit 1 PDBDLYA_DELAYA2: .equ 2 ; Delay A, bit 2 PDBDLYA_DELAYA3: .equ 3 ; Delay A, bit 3 PDBDLYA_DELAYA4: .equ 4 ; Delay A, bit 4 PDBDLYA_DELAYA5: .equ 5 ; Delay A, bit 5 PDBDLYA_DELAYA6: .equ 6 ; Delay A, bit 6 PDBDLYA_DELAYA7: .equ 7 ; Delay A, bit 7 PDBDLYA_DELAYA8: .equ 8 ; Delay A, bit 8 PDBDLYA_DELAYA9: .equ 9 ; Delay A, bit 9 PDBDLYA_DELAYA10: .equ 10 ; Delay A, bit 10 PDBDLYA_DELAYA11: .equ 11 ; Delay A, bit 11 PDBDLYA_DELAYA12: .equ 12 ; Delay A, bit 12 PDBDLYA_DELAYA13: .equ 13 ; Delay A, bit 13 PDBDLYA_DELAYA14: .equ 14 ; Delay A, bit 14 PDBDLYA_DELAYA15: .equ 15 ; Delay A, bit 15 ; bit position masks mPDBDLYA_DELAYA0: .equ %00000001 mPDBDLYA_DELAYA1: .equ %00000010 mPDBDLYA_DELAYA2: .equ %00000100 mPDBDLYA_DELAYA3: .equ %00001000 mPDBDLYA_DELAYA4: .equ %00010000 mPDBDLYA_DELAYA5: .equ %00100000 mPDBDLYA_DELAYA6: .equ %01000000 mPDBDLYA_DELAYA7: .equ %10000000 mPDBDLYA_DELAYA8: .equ %100000000 mPDBDLYA_DELAYA9: .equ %1000000000 mPDBDLYA_DELAYA10: .equ %10000000000 mPDBDLYA_DELAYA11: .equ %100000000000 mPDBDLYA_DELAYA12: .equ %1000000000000 mPDBDLYA_DELAYA13: .equ %10000000000000 mPDBDLYA_DELAYA14: .equ %100000000000000 mPDBDLYA_DELAYA15: .equ %1000000000000000 ;*** PDBDLYAH - PDB Delay A High Register; 0xFFFF9862 *** PDBDLYAH: .equ $FFFF9862 ;*** PDBDLYAH - PDB Delay A High Register; 0xFFFF9862 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PDBDLYAH_DELAYA8: .equ 0 ; Delay A, bit 8 PDBDLYAH_DELAYA9: .equ 1 ; Delay A, bit 9 PDBDLYAH_DELAYA10: .equ 2 ; Delay A, bit 10 PDBDLYAH_DELAYA11: .equ 3 ; Delay A, bit 11 PDBDLYAH_DELAYA12: .equ 4 ; Delay A, bit 12 PDBDLYAH_DELAYA13: .equ 5 ; Delay A, bit 13 PDBDLYAH_DELAYA14: .equ 6 ; Delay A, bit 14 PDBDLYAH_DELAYA15: .equ 7 ; Delay A, bit 15 ; bit position masks mPDBDLYAH_DELAYA8: .equ %00000001 mPDBDLYAH_DELAYA9: .equ %00000010 mPDBDLYAH_DELAYA10: .equ %00000100 mPDBDLYAH_DELAYA11: .equ %00001000 mPDBDLYAH_DELAYA12: .equ %00010000 mPDBDLYAH_DELAYA13: .equ %00100000 mPDBDLYAH_DELAYA14: .equ %01000000 mPDBDLYAH_DELAYA15: .equ %10000000 ;*** PDBDLYAL - PDB Delay A Low Register; 0xFFFF9863 *** PDBDLYAL: .equ $FFFF9863 ;*** PDBDLYAL - PDB Delay A Low Register; 0xFFFF9863 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PDBDLYAL_DELAYA0: .equ 0 ; Delay A, bit 0 PDBDLYAL_DELAYA1: .equ 1 ; Delay A, bit 1 PDBDLYAL_DELAYA2: .equ 2 ; Delay A, bit 2 PDBDLYAL_DELAYA3: .equ 3 ; Delay A, bit 3 PDBDLYAL_DELAYA4: .equ 4 ; Delay A, bit 4 PDBDLYAL_DELAYA5: .equ 5 ; Delay A, bit 5 PDBDLYAL_DELAYA6: .equ 6 ; Delay A, bit 6 PDBDLYAL_DELAYA7: .equ 7 ; Delay A, bit 7 ; bit position masks mPDBDLYAL_DELAYA0: .equ %00000001 mPDBDLYAL_DELAYA1: .equ %00000010 mPDBDLYAL_DELAYA2: .equ %00000100 mPDBDLYAL_DELAYA3: .equ %00001000 mPDBDLYAL_DELAYA4: .equ %00010000 mPDBDLYAL_DELAYA5: .equ %00100000 mPDBDLYAL_DELAYA6: .equ %01000000 mPDBDLYAL_DELAYA7: .equ %10000000 ;*** PDBDLYB - PDB Delay B Register; 0xFFFF9864 *** PDBDLYB: .equ $FFFF9864 ;*** PDBDLYB - PDB Delay B Register; 0xFFFF9864 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PDBDLYB_DELAYB0: .equ 0 ; Delay B, bit 0 PDBDLYB_DELAYB1: .equ 1 ; Delay B, bit 1 PDBDLYB_DELAYB2: .equ 2 ; Delay B, bit 2 PDBDLYB_DELAYB3: .equ 3 ; Delay B, bit 3 PDBDLYB_DELAYB4: .equ 4 ; Delay B, bit 4 PDBDLYB_DELAYB5: .equ 5 ; Delay B, bit 5 PDBDLYB_DELAYB6: .equ 6 ; Delay B, bit 6 PDBDLYB_DELAYB7: .equ 7 ; Delay B, bit 7 PDBDLYB_DELAYB8: .equ 8 ; Delay B, bit 8 PDBDLYB_DELAYB9: .equ 9 ; Delay B, bit 9 PDBDLYB_DELAYB10: .equ 10 ; Delay B, bit 10 PDBDLYB_DELAYB11: .equ 11 ; Delay B, bit 11 PDBDLYB_DELAYB12: .equ 12 ; Delay B, bit 12 PDBDLYB_DELAYB13: .equ 13 ; Delay B, bit 13 PDBDLYB_DELAYB14: .equ 14 ; Delay B, bit 14 PDBDLYB_DELAYB15: .equ 15 ; Delay B, bit 15 ; bit position masks mPDBDLYB_DELAYB0: .equ %00000001 mPDBDLYB_DELAYB1: .equ %00000010 mPDBDLYB_DELAYB2: .equ %00000100 mPDBDLYB_DELAYB3: .equ %00001000 mPDBDLYB_DELAYB4: .equ %00010000 mPDBDLYB_DELAYB5: .equ %00100000 mPDBDLYB_DELAYB6: .equ %01000000 mPDBDLYB_DELAYB7: .equ %10000000 mPDBDLYB_DELAYB8: .equ %100000000 mPDBDLYB_DELAYB9: .equ %1000000000 mPDBDLYB_DELAYB10: .equ %10000000000 mPDBDLYB_DELAYB11: .equ %100000000000 mPDBDLYB_DELAYB12: .equ %1000000000000 mPDBDLYB_DELAYB13: .equ %10000000000000 mPDBDLYB_DELAYB14: .equ %100000000000000 mPDBDLYB_DELAYB15: .equ %1000000000000000 ;*** PDBDLYBH - PDB Delay B High Register; 0xFFFF9864 *** PDBDLYBH: .equ $FFFF9864 ;*** PDBDLYBH - PDB Delay B High Register; 0xFFFF9864 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PDBDLYBH_DELAYB8: .equ 0 ; Delay B, bit 8 PDBDLYBH_DELAYB9: .equ 1 ; Delay B, bit 9 PDBDLYBH_DELAYB10: .equ 2 ; Delay B, bit 10 PDBDLYBH_DELAYB11: .equ 3 ; Delay B, bit 11 PDBDLYBH_DELAYB12: .equ 4 ; Delay B, bit 12 PDBDLYBH_DELAYB13: .equ 5 ; Delay B, bit 13 PDBDLYBH_DELAYB14: .equ 6 ; Delay B, bit 14 PDBDLYBH_DELAYB15: .equ 7 ; Delay B, bit 15 ; bit position masks mPDBDLYBH_DELAYB8: .equ %00000001 mPDBDLYBH_DELAYB9: .equ %00000010 mPDBDLYBH_DELAYB10: .equ %00000100 mPDBDLYBH_DELAYB11: .equ %00001000 mPDBDLYBH_DELAYB12: .equ %00010000 mPDBDLYBH_DELAYB13: .equ %00100000 mPDBDLYBH_DELAYB14: .equ %01000000 mPDBDLYBH_DELAYB15: .equ %10000000 ;*** PDBDLYBL - PDB Delay B Low Register; 0xFFFF9865 *** PDBDLYBL: .equ $FFFF9865 ;*** PDBDLYBL - PDB Delay B Low Register; 0xFFFF9865 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PDBDLYBL_DELAYB0: .equ 0 ; Delay B, bit 0 PDBDLYBL_DELAYB1: .equ 1 ; Delay B, bit 1 PDBDLYBL_DELAYB2: .equ 2 ; Delay B, bit 2 PDBDLYBL_DELAYB3: .equ 3 ; Delay B, bit 3 PDBDLYBL_DELAYB4: .equ 4 ; Delay B, bit 4 PDBDLYBL_DELAYB5: .equ 5 ; Delay B, bit 5 PDBDLYBL_DELAYB6: .equ 6 ; Delay B, bit 6 PDBDLYBL_DELAYB7: .equ 7 ; Delay B, bit 7 ; bit position masks mPDBDLYBL_DELAYB0: .equ %00000001 mPDBDLYBL_DELAYB1: .equ %00000010 mPDBDLYBL_DELAYB2: .equ %00000100 mPDBDLYBL_DELAYB3: .equ %00001000 mPDBDLYBL_DELAYB4: .equ %00010000 mPDBDLYBL_DELAYB5: .equ %00100000 mPDBDLYBL_DELAYB6: .equ %01000000 mPDBDLYBL_DELAYB7: .equ %10000000 ;*** PDBMOD - PDB Counter Modulus Register; 0xFFFF9866 *** PDBMOD: .equ $FFFF9866 ;*** PDBMOD - PDB Counter Modulus Register; 0xFFFF9866 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PDBMOD_MOD0: .equ 0 ; Counter Modulus, bit 0 PDBMOD_MOD1: .equ 1 ; Counter Modulus, bit 1 PDBMOD_MOD2: .equ 2 ; Counter Modulus, bit 2 PDBMOD_MOD3: .equ 3 ; Counter Modulus, bit 3 PDBMOD_MOD4: .equ 4 ; Counter Modulus, bit 4 PDBMOD_MOD5: .equ 5 ; Counter Modulus, bit 5 PDBMOD_MOD6: .equ 6 ; Counter Modulus, bit 6 PDBMOD_MOD7: .equ 7 ; Counter Modulus, bit 7 PDBMOD_MOD8: .equ 8 ; Counter Modulus, bit 8 PDBMOD_MOD9: .equ 9 ; Counter Modulus, bit 9 PDBMOD_MOD10: .equ 10 ; Counter Modulus, bit 10 PDBMOD_MOD11: .equ 11 ; Counter Modulus, bit 11 PDBMOD_MOD12: .equ 12 ; Counter Modulus, bit 12 PDBMOD_MOD13: .equ 13 ; Counter Modulus, bit 13 PDBMOD_MOD14: .equ 14 ; Counter Modulus, bit 14 PDBMOD_MOD15: .equ 15 ; Counter Modulus, bit 15 ; bit position masks mPDBMOD_MOD0: .equ %00000001 mPDBMOD_MOD1: .equ %00000010 mPDBMOD_MOD2: .equ %00000100 mPDBMOD_MOD3: .equ %00001000 mPDBMOD_MOD4: .equ %00010000 mPDBMOD_MOD5: .equ %00100000 mPDBMOD_MOD6: .equ %01000000 mPDBMOD_MOD7: .equ %10000000 mPDBMOD_MOD8: .equ %100000000 mPDBMOD_MOD9: .equ %1000000000 mPDBMOD_MOD10: .equ %10000000000 mPDBMOD_MOD11: .equ %100000000000 mPDBMOD_MOD12: .equ %1000000000000 mPDBMOD_MOD13: .equ %10000000000000 mPDBMOD_MOD14: .equ %100000000000000 mPDBMOD_MOD15: .equ %1000000000000000 ;*** PDBMODH - PDB Counter Modulus High Register; 0xFFFF9866 *** PDBMODH: .equ $FFFF9866 ;*** PDBMODH - PDB Counter Modulus High Register; 0xFFFF9866 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PDBMODH_MOD8: .equ 0 ; Counter Modulus, bit 8 PDBMODH_MOD9: .equ 1 ; Counter Modulus, bit 9 PDBMODH_MOD10: .equ 2 ; Counter Modulus, bit 10 PDBMODH_MOD11: .equ 3 ; Counter Modulus, bit 11 PDBMODH_MOD12: .equ 4 ; Counter Modulus, bit 12 PDBMODH_MOD13: .equ 5 ; Counter Modulus, bit 13 PDBMODH_MOD14: .equ 6 ; Counter Modulus, bit 14 PDBMODH_MOD15: .equ 7 ; Counter Modulus, bit 15 ; bit position masks mPDBMODH_MOD8: .equ %00000001 mPDBMODH_MOD9: .equ %00000010 mPDBMODH_MOD10: .equ %00000100 mPDBMODH_MOD11: .equ %00001000 mPDBMODH_MOD12: .equ %00010000 mPDBMODH_MOD13: .equ %00100000 mPDBMODH_MOD14: .equ %01000000 mPDBMODH_MOD15: .equ %10000000 ;*** PDBMODL - PDB Counter Modulus Low Register; 0xFFFF9867 *** PDBMODL: .equ $FFFF9867 ;*** PDBMODL - PDB Counter Modulus Low Register; 0xFFFF9867 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PDBMODL_MOD0: .equ 0 ; Counter Modulus, bit 0 PDBMODL_MOD1: .equ 1 ; Counter Modulus, bit 1 PDBMODL_MOD2: .equ 2 ; Counter Modulus, bit 2 PDBMODL_MOD3: .equ 3 ; Counter Modulus, bit 3 PDBMODL_MOD4: .equ 4 ; Counter Modulus, bit 4 PDBMODL_MOD5: .equ 5 ; Counter Modulus, bit 5 PDBMODL_MOD6: .equ 6 ; Counter Modulus, bit 6 PDBMODL_MOD7: .equ 7 ; Counter Modulus, bit 7 ; bit position masks mPDBMODL_MOD0: .equ %00000001 mPDBMODL_MOD1: .equ %00000010 mPDBMODL_MOD2: .equ %00000100 mPDBMODL_MOD3: .equ %00001000 mPDBMODL_MOD4: .equ %00010000 mPDBMODL_MOD5: .equ %00100000 mPDBMODL_MOD6: .equ %01000000 mPDBMODL_MOD7: .equ %10000000 ;*** PDBCNT - PDB Counter Value Register; 0xFFFF9868 *** PDBCNT: .equ $FFFF9868 ;*** PDBCNT - PDB Counter Value Register; 0xFFFF9868 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PDBCNT_COUNT0: .equ 0 ; Counter Value, bit 0 PDBCNT_COUNT1: .equ 1 ; Counter Value, bit 1 PDBCNT_COUNT2: .equ 2 ; Counter Value, bit 2 PDBCNT_COUNT3: .equ 3 ; Counter Value, bit 3 PDBCNT_COUNT4: .equ 4 ; Counter Value, bit 4 PDBCNT_COUNT5: .equ 5 ; Counter Value, bit 5 PDBCNT_COUNT6: .equ 6 ; Counter Value, bit 6 PDBCNT_COUNT7: .equ 7 ; Counter Value, bit 7 PDBCNT_COUNT8: .equ 8 ; Counter Value, bit 8 PDBCNT_COUNT9: .equ 9 ; Counter Value, bit 9 PDBCNT_COUNT10: .equ 10 ; Counter Value, bit 10 PDBCNT_COUNT11: .equ 11 ; Counter Value, bit 11 PDBCNT_COUNT12: .equ 12 ; Counter Value, bit 12 PDBCNT_COUNT13: .equ 13 ; Counter Value, bit 13 PDBCNT_COUNT14: .equ 14 ; Counter Value, bit 14 PDBCNT_COUNT15: .equ 15 ; Counter Value, bit 15 ; bit position masks mPDBCNT_COUNT0: .equ %00000001 mPDBCNT_COUNT1: .equ %00000010 mPDBCNT_COUNT2: .equ %00000100 mPDBCNT_COUNT3: .equ %00001000 mPDBCNT_COUNT4: .equ %00010000 mPDBCNT_COUNT5: .equ %00100000 mPDBCNT_COUNT6: .equ %01000000 mPDBCNT_COUNT7: .equ %10000000 mPDBCNT_COUNT8: .equ %100000000 mPDBCNT_COUNT9: .equ %1000000000 mPDBCNT_COUNT10: .equ %10000000000 mPDBCNT_COUNT11: .equ %100000000000 mPDBCNT_COUNT12: .equ %1000000000000 mPDBCNT_COUNT13: .equ %10000000000000 mPDBCNT_COUNT14: .equ %100000000000000 mPDBCNT_COUNT15: .equ %1000000000000000 ;*** PDBCNTH - PDB Counter Value High Register; 0xFFFF9868 *** PDBCNTH: .equ $FFFF9868 ;*** PDBCNTH - PDB Counter Value High Register; 0xFFFF9868 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PDBCNTH_COUNT8: .equ 0 ; Counter Value, bit 8 PDBCNTH_COUNT9: .equ 1 ; Counter Value, bit 9 PDBCNTH_COUNT10: .equ 2 ; Counter Value, bit 10 PDBCNTH_COUNT11: .equ 3 ; Counter Value, bit 11 PDBCNTH_COUNT12: .equ 4 ; Counter Value, bit 12 PDBCNTH_COUNT13: .equ 5 ; Counter Value, bit 13 PDBCNTH_COUNT14: .equ 6 ; Counter Value, bit 14 PDBCNTH_COUNT15: .equ 7 ; Counter Value, bit 15 ; bit position masks mPDBCNTH_COUNT8: .equ %00000001 mPDBCNTH_COUNT9: .equ %00000010 mPDBCNTH_COUNT10: .equ %00000100 mPDBCNTH_COUNT11: .equ %00001000 mPDBCNTH_COUNT12: .equ %00010000 mPDBCNTH_COUNT13: .equ %00100000 mPDBCNTH_COUNT14: .equ %01000000 mPDBCNTH_COUNT15: .equ %10000000 ;*** PDBCNTL - PDB Counter Value Low Register; 0xFFFF9869 *** PDBCNTL: .equ $FFFF9869 ;*** PDBCNTL - PDB Counter Value Low Register; 0xFFFF9869 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PDBCNTL_COUNT0: .equ 0 ; Counter Value, bit 0 PDBCNTL_COUNT1: .equ 1 ; Counter Value, bit 1 PDBCNTL_COUNT2: .equ 2 ; Counter Value, bit 2 PDBCNTL_COUNT3: .equ 3 ; Counter Value, bit 3 PDBCNTL_COUNT4: .equ 4 ; Counter Value, bit 4 PDBCNTL_COUNT5: .equ 5 ; Counter Value, bit 5 PDBCNTL_COUNT6: .equ 6 ; Counter Value, bit 6 PDBCNTL_COUNT7: .equ 7 ; Counter Value, bit 7 ; bit position masks mPDBCNTL_COUNT0: .equ %00000001 mPDBCNTL_COUNT1: .equ %00000010 mPDBCNTL_COUNT2: .equ %00000100 mPDBCNTL_COUNT3: .equ %00001000 mPDBCNTL_COUNT4: .equ %00010000 mPDBCNTL_COUNT5: .equ %00100000 mPDBCNTL_COUNT6: .equ %01000000 mPDBCNTL_COUNT7: .equ %10000000 ;*** PDBSCR - PDB Status Register; 0xFFFF986A *** PDBSCR: .equ $FFFF986A ;*** PDBSCR - PDB Status Register; 0xFFFF986A *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET PDBSCR_DAF: .equ 1 ; Delay A flag PDBSCR_DBF: .equ 3 ; Delay B flag PDBSCR_COF: .equ 5 ; Counter overflow flag PDBSCR_PDBEN: .equ 6 ; PDB module enable ; bit position masks mPDBSCR_DAF: .equ %00000010 mPDBSCR_DBF: .equ %00001000 mPDBSCR_COF: .equ %00100000 mPDBSCR_PDBEN: .equ %01000000 ;*** WDOG_ST_CTRL - Watchdog Status and Control Register; 0xFFFF9880 *** WDOG_ST_CTRL: .equ $FFFF9880 ;*** WDOG_ST_CTRL - Watchdog Status and Control Register; 0xFFFF9880 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET WDOG_ST_CTRL_INT_FLG: .equ 15 ; Interrupt Flag WDOG_ST_CTRL_WDOG_EN: .equ 16 ; Watchdog Enable WDOG_ST_CTRL_CLK_SRC: .equ 17 ; Clock Source Select WDOG_ST_CTRL_IRQ_RST_EN: .equ 18 ; Interrupt Enable WDOG_ST_CTRL_WIN_EN: .equ 19 ; Window mode WDOG_ST_CTRL_ALLOW_UPDATE: .equ 20 ; Write once registers update WDOG_ST_CTRL_DBG_EN: .equ 21 ; Debug mode enable WDOG_ST_CTRL_STOP_EN: .equ 22 ; Stop mode enable WDOG_ST_CTRL_WAIT_EN: .equ 23 ; Wait mode enable WDOG_ST_CTRL_TESTWDOG: .equ 26 ; Test watchdog WDOG_ST_CTRL_TESTSEL: .equ 27 ; Test Selection WDOG_ST_CTRL_BYTESEL0: .equ 28 ; Byte Test Selection, bit 0 WDOG_ST_CTRL_BYTESEL1: .equ 29 ; Byte Test Selection, bit 1 WDOG_ST_CTRL_DISABLE_TESTWDOG: .equ 30 ; Test Mode Disable ; bit position masks mWDOG_ST_CTRL_INT_FLG: .equ %1000000000000000 mWDOG_ST_CTRL_WDOG_EN: .equ %10000000000000000 mWDOG_ST_CTRL_CLK_SRC: .equ %100000000000000000 mWDOG_ST_CTRL_IRQ_RST_EN: .equ %1000000000000000000 mWDOG_ST_CTRL_WIN_EN: .equ %10000000000000000000 mWDOG_ST_CTRL_ALLOW_UPDATE: .equ %100000000000000000000 mWDOG_ST_CTRL_DBG_EN: .equ %1000000000000000000000 mWDOG_ST_CTRL_STOP_EN: .equ %10000000000000000000000 mWDOG_ST_CTRL_WAIT_EN: .equ %100000000000000000000000 mWDOG_ST_CTRL_TESTWDOG: .equ %100000000000000000000000000 mWDOG_ST_CTRL_TESTSEL: .equ %1000000000000000000000000000 mWDOG_ST_CTRL_BYTESEL0: .equ %10000000000000000000000000000 mWDOG_ST_CTRL_BYTESEL1: .equ %100000000000000000000000000000 mWDOG_ST_CTRL_DISABLE_TESTWDOG: .equ %1000000000000000000000000000000 ;*** WDOG_ST_CTRL_H - Watchdog Status and Control Register High; 0xFFFF9880 *** WDOG_ST_CTRL_H: .equ $FFFF9880 ;*** WDOG_ST_CTRL_H - Watchdog Status and Control Register High; 0xFFFF9880 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET WDOG_ST_CTRL_H_WDOG_EN: .equ 0 ; Watchdog Enable WDOG_ST_CTRL_H_CLK_SRC: .equ 1 ; Clock Source Select WDOG_ST_CTRL_H_IRQ_RST_EN: .equ 2 ; Interrupt Enable WDOG_ST_CTRL_H_WIN_EN: .equ 3 ; Window mode WDOG_ST_CTRL_H_ALLOW_UPDATE: .equ 4 ; Write once registers update WDOG_ST_CTRL_H_DBG_EN: .equ 5 ; Debug mode enable WDOG_ST_CTRL_H_STOP_EN: .equ 6 ; Stop mode enable WDOG_ST_CTRL_H_WAIT_EN: .equ 7 ; Wait mode enable WDOG_ST_CTRL_H_TESTWDOG: .equ 10 ; Test watchdog WDOG_ST_CTRL_H_TESTSEL: .equ 11 ; Test Selection WDOG_ST_CTRL_H_BYTESEL0: .equ 12 ; Byte Test Selection, bit 0 WDOG_ST_CTRL_H_BYTESEL1: .equ 13 ; Byte Test Selection, bit 1 WDOG_ST_CTRL_H_DISABLE_TESTWDOG: .equ 14 ; Test Mode Disable ; bit position masks mWDOG_ST_CTRL_H_WDOG_EN: .equ %00000001 mWDOG_ST_CTRL_H_CLK_SRC: .equ %00000010 mWDOG_ST_CTRL_H_IRQ_RST_EN: .equ %00000100 mWDOG_ST_CTRL_H_WIN_EN: .equ %00001000 mWDOG_ST_CTRL_H_ALLOW_UPDATE: .equ %00010000 mWDOG_ST_CTRL_H_DBG_EN: .equ %00100000 mWDOG_ST_CTRL_H_STOP_EN: .equ %01000000 mWDOG_ST_CTRL_H_WAIT_EN: .equ %10000000 mWDOG_ST_CTRL_H_TESTWDOG: .equ %10000000000 mWDOG_ST_CTRL_H_TESTSEL: .equ %100000000000 mWDOG_ST_CTRL_H_BYTESEL0: .equ %1000000000000 mWDOG_ST_CTRL_H_BYTESEL1: .equ %10000000000000 mWDOG_ST_CTRL_H_DISABLE_TESTWDOG: .equ %100000000000000 ;*** WDOG_ST_CTRL_L - Watchdog Status and Control Register Low; 0xFFFF9882 *** WDOG_ST_CTRL_L: .equ $FFFF9882 ;*** WDOG_ST_CTRL_L - Watchdog Status and Control Register Low; 0xFFFF9882 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET WDOG_ST_CTRL_L_INT_FLG: .equ 15 ; Interrupt Flag ; bit position masks mWDOG_ST_CTRL_L_INT_FLG: .equ %1000000000000000 ;*** WDOG_TO_VAL - Watchdog Control and Status Register; 0xFFFF9884 *** WDOG_TO_VAL: .equ $FFFF9884 ;*** WDOG_TO_VAL - Watchdog Control and Status Register; 0xFFFF9884 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET WDOG_TO_VAL_TO_VAL_LOW: .equ 0 ; Timeout Value Low WDOG_TO_VAL_TO_VAL_HIGH: .equ 16 ; Timeout Value High ; bit position masks mWDOG_TO_VAL_TO_VAL_LOW: .equ %1111111111111111 mWDOG_TO_VAL_TO_VAL_HIGH: .equ %11111111111111110000000000000000 ;*** WDOG_TO_VAL_H - Watchdog Control and Status Register High; 0xFFFF9884 *** WDOG_TO_VAL_H: .equ $FFFF9884 ;*** WDOG_TO_VAL_H - Watchdog Control and Status Register High; 0xFFFF9884 *** ;*** WDOG_TO_VAL_L - Watchdog Control and Status Register Low; 0xFFFF9886 *** WDOG_TO_VAL_L: .equ $FFFF9886 ;*** WDOG_TO_VAL_L - Watchdog Control and Status Register Low; 0xFFFF9886 *** ;*** WDOG_WIN - Watchdog Window Register; 0xFFFF9888 *** WDOG_WIN: .equ $FFFF9888 ;*** WDOG_WIN - Watchdog Window Register; 0xFFFF9888 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET WDOG_WIN_WIN_LOW: .equ 0 ; Window Low WDOG_WIN_WIN_HIGH: .equ 16 ; Window High ; bit position masks mWDOG_WIN_WIN_LOW: .equ %1111111111111111 mWDOG_WIN_WIN_HIGH: .equ %11111111111111110000000000000000 ;*** WDOG_WIN_H - Watchdog Window Register High; 0xFFFF9888 *** WDOG_WIN_H: .equ $FFFF9888 ;*** WDOG_WIN_H - Watchdog Window Register High; 0xFFFF9888 *** ;*** WDOG_WIN_L - Watchdog Window Register Low; 0xFFFF988A *** WDOG_WIN_L: .equ $FFFF988A ;*** WDOG_WIN_L - Watchdog Window Register Low; 0xFFFF988A *** ;*** WDOG_REFRESH - Watchdog Refresh Register; 0xFFFF988C *** WDOG_REFRESH: .equ $FFFF988C ;*** WDOG_REFRESH - Watchdog Refresh Register; 0xFFFF988C *** ;*** WDOG_REFRESH_H - Watchdog Refresh High Register; 0xFFFF988C *** WDOG_REFRESH_H: .equ $FFFF988C ;*** WDOG_REFRESH_H - Watchdog Refresh High Register; 0xFFFF988C *** ;*** WDOG_REFRESH_L - Watchdog Refresh Low Register; 0xFFFF988D *** WDOG_REFRESH_L: .equ $FFFF988D ;*** WDOG_REFRESH_L - Watchdog Refresh Low Register; 0xFFFF988D *** ;*** WDOG_UNLOCK - Watchdog Unlock Register; 0xFFFF988E *** WDOG_UNLOCK: .equ $FFFF988E ;*** WDOG_UNLOCK - Watchdog Unlock Register; 0xFFFF988E *** ;*** WDOG_UNLOCK_H - Watchdog Unlock High Register; 0xFFFF988E *** WDOG_UNLOCK_H: .equ $FFFF988E ;*** WDOG_UNLOCK_H - Watchdog Unlock High Register; 0xFFFF988E *** ;*** WDOG_UNLOCK_L - Watchdog Unlock Low Register; 0xFFFF988F *** WDOG_UNLOCK_L: .equ $FFFF988F ;*** WDOG_UNLOCK_L - Watchdog Unlock Low Register; 0xFFFF988F *** ;*** WDOG_TIMER_OUT - Watchdog Timer Output Register; 0xFFFF9890 *** WDOG_TIMER_OUT: .equ $FFFF9890 ;*** WDOG_TIMER_OUT - Watchdog Timer Output Register; 0xFFFF9890 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET WDOG_TIMER_OUT_TIMER_OUT_LOW: .equ 0 ; Timer Output Low WDOG_TIMER_OUT_TIMER_OUT_HIGH: .equ 16 ; Timer Output High ; bit position masks mWDOG_TIMER_OUT_TIMER_OUT_LOW: .equ %1111111111111111 mWDOG_TIMER_OUT_TIMER_OUT_HIGH: .equ %11111111111111110000000000000000 ;*** WDOG_TIMER_OUT_H - Watchdog Timer Output Register High; 0xFFFF9890 *** WDOG_TIMER_OUT_H: .equ $FFFF9890 ;*** WDOG_TIMER_OUT_H - Watchdog Timer Output Register High; 0xFFFF9890 *** ;*** WDOG_TIMER_OUT_L - Watchdog Timer Output Register Low; 0xFFFF9892 *** WDOG_TIMER_OUT_L: .equ $FFFF9892 ;*** WDOG_TIMER_OUT_L - Watchdog Timer Output Register Low; 0xFFFF9892 *** ;*** WDOG_RST_CNT - Watchdog Reset Count Register; 0xFFFF9894 *** WDOG_RST_CNT: .equ $FFFF9894 ;*** WDOG_RST_CNT - Watchdog Reset Count Register; 0xFFFF9894 *** ;*** IEVENT_DR0 - iEvent Data Register 0; 0xFFFF9A00 *** IEVENT_DR0: .equ $FFFF9A00 ;*** IEVENT_DR0 - iEvent Data Register 0; 0xFFFF9A00 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IEVENT_DR0_In_A: .equ 0 ; Event Input A IEVENT_DR0_In_B: .equ 1 ; Event Input B IEVENT_DR0_In_C: .equ 2 ; Event Input C IEVENT_DR0_In_D: .equ 3 ; Event Input D IEVENT_DR0_Output_FSM0: .equ 4 ; Output Finite State Machine, bit 0 IEVENT_DR0_Output_FSM1: .equ 5 ; Output Finite State Machine, bit 1 IEVENT_DR0_Output_FSM2: .equ 6 ; Output Finite State Machine, bit 2 IEVENT_DR0_Ev_Out: .equ 7 ; Event Output. This bit represents the state of the configured event output ; bit position masks mIEVENT_DR0_In_A: .equ %00000001 mIEVENT_DR0_In_B: .equ %00000010 mIEVENT_DR0_In_C: .equ %00000100 mIEVENT_DR0_In_D: .equ %00001000 mIEVENT_DR0_Output_FSM0: .equ %00010000 mIEVENT_DR0_Output_FSM1: .equ %00100000 mIEVENT_DR0_Output_FSM2: .equ %01000000 mIEVENT_DR0_Ev_Out: .equ %10000000 ;*** IEVENT_DR1 - iEvent Data Register 1; 0xFFFF9A01 *** IEVENT_DR1: .equ $FFFF9A01 ;*** IEVENT_DR1 - iEvent Data Register 1; 0xFFFF9A01 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IEVENT_DR1_In_A: .equ 0 ; Event Input A IEVENT_DR1_In_B: .equ 1 ; Event Input B IEVENT_DR1_In_C: .equ 2 ; Event Input C IEVENT_DR1_In_D: .equ 3 ; Event Input D IEVENT_DR1_Output_FSM0: .equ 4 ; Output Finite State Machine, bit 0 IEVENT_DR1_Output_FSM1: .equ 5 ; Output Finite State Machine, bit 1 IEVENT_DR1_Output_FSM2: .equ 6 ; Output Finite State Machine, bit 2 IEVENT_DR1_Ev_Out: .equ 7 ; Event Output. This bit represents the state of the configured event output ; bit position masks mIEVENT_DR1_In_A: .equ %00000001 mIEVENT_DR1_In_B: .equ %00000010 mIEVENT_DR1_In_C: .equ %00000100 mIEVENT_DR1_In_D: .equ %00001000 mIEVENT_DR1_Output_FSM0: .equ %00010000 mIEVENT_DR1_Output_FSM1: .equ %00100000 mIEVENT_DR1_Output_FSM2: .equ %01000000 mIEVENT_DR1_Ev_Out: .equ %10000000 ;*** IEVENT_DR2 - iEvent Data Register 2; 0xFFFF9A02 *** IEVENT_DR2: .equ $FFFF9A02 ;*** IEVENT_DR2 - iEvent Data Register 2; 0xFFFF9A02 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IEVENT_DR2_In_A: .equ 0 ; Event Input A IEVENT_DR2_In_B: .equ 1 ; Event Input B IEVENT_DR2_In_C: .equ 2 ; Event Input C IEVENT_DR2_In_D: .equ 3 ; Event Input D IEVENT_DR2_Output_FSM0: .equ 4 ; Output Finite State Machine, bit 0 IEVENT_DR2_Output_FSM1: .equ 5 ; Output Finite State Machine, bit 1 IEVENT_DR2_Output_FSM2: .equ 6 ; Output Finite State Machine, bit 2 IEVENT_DR2_Ev_Out: .equ 7 ; Event Output. This bit represents the state of the configured event output ; bit position masks mIEVENT_DR2_In_A: .equ %00000001 mIEVENT_DR2_In_B: .equ %00000010 mIEVENT_DR2_In_C: .equ %00000100 mIEVENT_DR2_In_D: .equ %00001000 mIEVENT_DR2_Output_FSM0: .equ %00010000 mIEVENT_DR2_Output_FSM1: .equ %00100000 mIEVENT_DR2_Output_FSM2: .equ %01000000 mIEVENT_DR2_Ev_Out: .equ %10000000 ;*** IEVENT_DR3 - iEvent Data Register 3; 0xFFFF9A03 *** IEVENT_DR3: .equ $FFFF9A03 ;*** IEVENT_DR3 - iEvent Data Register 3; 0xFFFF9A03 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IEVENT_DR3_In_A: .equ 0 ; Event Input A IEVENT_DR3_In_B: .equ 1 ; Event Input B IEVENT_DR3_In_C: .equ 2 ; Event Input C IEVENT_DR3_In_D: .equ 3 ; Event Input D IEVENT_DR3_Output_FSM0: .equ 4 ; Output Finite State Machine, bit 0 IEVENT_DR3_Output_FSM1: .equ 5 ; Output Finite State Machine, bit 1 IEVENT_DR3_Output_FSM2: .equ 6 ; Output Finite State Machine, bit 2 IEVENT_DR3_Ev_Out: .equ 7 ; Event Output. This bit represents the state of the configured event output ; bit position masks mIEVENT_DR3_In_A: .equ %00000001 mIEVENT_DR3_In_B: .equ %00000010 mIEVENT_DR3_In_C: .equ %00000100 mIEVENT_DR3_In_D: .equ %00001000 mIEVENT_DR3_Output_FSM0: .equ %00010000 mIEVENT_DR3_Output_FSM1: .equ %00100000 mIEVENT_DR3_Output_FSM2: .equ %01000000 mIEVENT_DR3_Ev_Out: .equ %10000000 ;*** IEVENT_CR0 - iEvent Control Register 0; 0xFFFF9A80 *** IEVENT_CR0: .equ $FFFF9A80 ;*** IEVENT_CR0 - iEvent Control Register 0; 0xFFFF9A80 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IEVENT_CR0_Type0: .equ 0 ; Output Channel Type, bit 0 IEVENT_CR0_Type1: .equ 1 ; Output Channel Type, bit 1 IEVENT_CR0_OSE: .equ 2 ; One-Shot Enable IEVENT_CR0_DDB: .equ 3 ; Disable Done Broadcast IEVENT_CR0_RO: .equ 7 ; Read-Only. This bit determines if the configuration registers can be written or are read-only ; bit position masks mIEVENT_CR0_Type0: .equ %00000001 mIEVENT_CR0_Type1: .equ %00000010 mIEVENT_CR0_OSE: .equ %00000100 mIEVENT_CR0_DDB: .equ %00001000 mIEVENT_CR0_RO: .equ %10000000 ;*** IEVENT_CR1 - iEvent Control Register 1; 0xFFFF9A81 *** IEVENT_CR1: .equ $FFFF9A81 ;*** IEVENT_CR1 - iEvent Control Register 1; 0xFFFF9A81 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IEVENT_CR1_Type0: .equ 0 ; Output Channel Type, bit 0 IEVENT_CR1_Type1: .equ 1 ; Output Channel Type, bit 1 IEVENT_CR1_OSE: .equ 2 ; One-Shot Enable IEVENT_CR1_DDB: .equ 3 ; Disable Done Broadcast IEVENT_CR1_RO: .equ 7 ; Read-Only. This bit determines if the configuration registers can be written or are read-only ; bit position masks mIEVENT_CR1_Type0: .equ %00000001 mIEVENT_CR1_Type1: .equ %00000010 mIEVENT_CR1_OSE: .equ %00000100 mIEVENT_CR1_DDB: .equ %00001000 mIEVENT_CR1_RO: .equ %10000000 ;*** IEVENT_CR2 - iEvent Control Register 2; 0xFFFF9A82 *** IEVENT_CR2: .equ $FFFF9A82 ;*** IEVENT_CR2 - iEvent Control Register 2; 0xFFFF9A82 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IEVENT_CR2_Type0: .equ 0 ; Output Channel Type, bit 0 IEVENT_CR2_Type1: .equ 1 ; Output Channel Type, bit 1 IEVENT_CR2_OSE: .equ 2 ; One-Shot Enable IEVENT_CR2_DDB: .equ 3 ; Disable Done Broadcast IEVENT_CR2_RO: .equ 7 ; Read-Only. This bit determines if the configuration registers can be written or are read-only ; bit position masks mIEVENT_CR2_Type0: .equ %00000001 mIEVENT_CR2_Type1: .equ %00000010 mIEVENT_CR2_OSE: .equ %00000100 mIEVENT_CR2_DDB: .equ %00001000 mIEVENT_CR2_RO: .equ %10000000 ;*** IEVENT_CR3 - iEvent Control Register 3; 0xFFFF9A83 *** IEVENT_CR3: .equ $FFFF9A83 ;*** IEVENT_CR3 - iEvent Control Register 3; 0xFFFF9A83 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IEVENT_CR3_Type0: .equ 0 ; Output Channel Type, bit 0 IEVENT_CR3_Type1: .equ 1 ; Output Channel Type, bit 1 IEVENT_CR3_OSE: .equ 2 ; One-Shot Enable IEVENT_CR3_DDB: .equ 3 ; Disable Done Broadcast IEVENT_CR3_RO: .equ 7 ; Read-Only. This bit determines if the configuration registers can be written or are read-only ; bit position masks mIEVENT_CR3_Type0: .equ %00000001 mIEVENT_CR3_Type1: .equ %00000010 mIEVENT_CR3_OSE: .equ %00000100 mIEVENT_CR3_DDB: .equ %00001000 mIEVENT_CR3_RO: .equ %10000000 ;*** IEVENT_IMXCR0 - iEvent Input Mux Configuration Register 0; 0xFFFF9B00 *** IEVENT_IMXCR0: .equ $FFFF9B00 ;*** IEVENT_IMXCR0 - iEvent Input Mux Configuration Register 0; 0xFFFF9B00 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IEVENT_IMXCR0_D_Select0: .equ 0 ; D_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input D, bit 0 IEVENT_IMXCR0_D_Select1: .equ 1 ; D_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input D, bit 1 IEVENT_IMXCR0_D_Select2: .equ 2 ; D_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input D, bit 2 IEVENT_IMXCR0_D_Select3: .equ 3 ; D_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input D, bit 3 IEVENT_IMXCR0_C_Select0: .equ 8 ; C_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input C, bit 0 IEVENT_IMXCR0_C_Select1: .equ 9 ; C_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input C, bit 1 IEVENT_IMXCR0_C_Select2: .equ 10 ; C_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input C, bit 2 IEVENT_IMXCR0_C_Select3: .equ 11 ; C_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input C, bit 3 IEVENT_IMXCR0_B_Select0: .equ 16 ; B_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input B, bit 0 IEVENT_IMXCR0_B_Select1: .equ 17 ; B_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input B, bit 1 IEVENT_IMXCR0_B_Select2: .equ 18 ; B_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input B, bit 2 IEVENT_IMXCR0_B_Select3: .equ 19 ; B_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input B, bit 3 IEVENT_IMXCR0_A_Select0: .equ 24 ; A_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input A, bit 0 IEVENT_IMXCR0_A_Select1: .equ 25 ; A_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input A, bit 1 IEVENT_IMXCR0_A_Select2: .equ 26 ; A_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input A, bit 2 IEVENT_IMXCR0_A_Select3: .equ 27 ; A_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input A, bit 3 ; bit position masks mIEVENT_IMXCR0_D_Select0: .equ %00000001 mIEVENT_IMXCR0_D_Select1: .equ %00000010 mIEVENT_IMXCR0_D_Select2: .equ %00000100 mIEVENT_IMXCR0_D_Select3: .equ %00001000 mIEVENT_IMXCR0_C_Select0: .equ %100000000 mIEVENT_IMXCR0_C_Select1: .equ %1000000000 mIEVENT_IMXCR0_C_Select2: .equ %10000000000 mIEVENT_IMXCR0_C_Select3: .equ %100000000000 mIEVENT_IMXCR0_B_Select0: .equ %10000000000000000 mIEVENT_IMXCR0_B_Select1: .equ %100000000000000000 mIEVENT_IMXCR0_B_Select2: .equ %1000000000000000000 mIEVENT_IMXCR0_B_Select3: .equ %10000000000000000000 mIEVENT_IMXCR0_A_Select0: .equ %1000000000000000000000000 mIEVENT_IMXCR0_A_Select1: .equ %10000000000000000000000000 mIEVENT_IMXCR0_A_Select2: .equ %100000000000000000000000000 mIEVENT_IMXCR0_A_Select3: .equ %1000000000000000000000000000 ;*** IEVENT_BFECR0 - iEvent Boolean Function Evaluation Configuration Register 0; 0xFFFF9B04 *** IEVENT_BFECR0: .equ $FFFF9B04 ;*** IEVENT_BFECR0 - iEvent Boolean Function Evaluation Configuration Register 0; 0xFFFF9B04 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IEVENT_BFECR0_PT3_DC0: .equ 0 ; Product Term 3, D input Configuration, bit 0 IEVENT_BFECR0_PT3_DC1: .equ 1 ; Product Term 3, D input Configuration, bit 1 IEVENT_BFECR0_PT3_CC0: .equ 2 ; Product Term 3, C input Configuration, bit 0 IEVENT_BFECR0_PT3_CC1: .equ 3 ; Product Term 3, C input Configuration, bit 1 IEVENT_BFECR0_PT3_BC0: .equ 4 ; Product Term 3, B input Configuration, bit 0 IEVENT_BFECR0_PT3_BC1: .equ 5 ; Product Term 3, B input Configuration, bit 1 IEVENT_BFECR0_PT3_AC0: .equ 6 ; Product Term 3, A input Configuration, bit 0 IEVENT_BFECR0_PT3_AC1: .equ 7 ; Product Term 3, A input Configuration, bit 1 IEVENT_BFECR0_PT2_DC0: .equ 8 ; Product Term 2, D input Configuration, bit 0 IEVENT_BFECR0_PT2_DC1: .equ 9 ; Product Term 2, D input Configuration, bit 1 IEVENT_BFECR0_PT2_CC0: .equ 10 ; Product Term 2, C input Configuration, bit 0 IEVENT_BFECR0_PT2_CC1: .equ 11 ; Product Term 2, C input Configuration, bit 1 IEVENT_BFECR0_PT2_BC0: .equ 12 ; Product Term 2, B input Configuration, bit 0 IEVENT_BFECR0_PT2_BC1: .equ 13 ; Product Term 2, B input Configuration, bit 1 IEVENT_BFECR0_PT2_AC0: .equ 14 ; Product Term 2, A input Configuration, bit 0 IEVENT_BFECR0_PT2_AC1: .equ 15 ; Product Term 2, A input Configuration, bit 1 IEVENT_BFECR0_PT1_DC0: .equ 16 ; Product Term 1, D input Configuration, bit 0 IEVENT_BFECR0_PT1_DC1: .equ 17 ; Product Term 1, D input Configuration, bit 1 IEVENT_BFECR0_PT1_CC0: .equ 18 ; Product Term 1, C input Configuration, bit 0 IEVENT_BFECR0_PT1_CC1: .equ 19 ; Product Term 1, C input Configuration, bit 1 IEVENT_BFECR0_PT1_BC0: .equ 20 ; Product Term 1, B input Configuration, bit 0 IEVENT_BFECR0_PT1_BC1: .equ 21 ; Product Term 1, B input Configuration, bit 1 IEVENT_BFECR0_PT1_AC0: .equ 22 ; Product Term 1, A input Configuration, bit 0 IEVENT_BFECR0_PT1_AC1: .equ 23 ; Product Term 1, A input Configuration, bit 1 IEVENT_BFECR0_PT0_DC0: .equ 24 ; Product Term 0, D input Configuration, bit 0 IEVENT_BFECR0_PT0_DC1: .equ 25 ; Product Term 0, D input Configuration, bit 1 IEVENT_BFECR0_PT0_CC0: .equ 26 ; Product Term 0, C input Configuration, bit 0 IEVENT_BFECR0_PT0_CC1: .equ 27 ; Product Term 0, C input Configuration, bit 1 IEVENT_BFECR0_PT0_BC0: .equ 28 ; Product Term 0, B input Configuration, bit 0 IEVENT_BFECR0_PT0_BC1: .equ 29 ; Product Term 0, B input Configuration, bit 1 IEVENT_BFECR0_PT0_AC0: .equ 30 ; Product Term 0, A input Configuration, bit 0 IEVENT_BFECR0_PT0_AC1: .equ 31 ; Product Term 0, A input Configuration, bit 1 ; bit position masks mIEVENT_BFECR0_PT3_DC0: .equ %00000001 mIEVENT_BFECR0_PT3_DC1: .equ %00000010 mIEVENT_BFECR0_PT3_CC0: .equ %00000100 mIEVENT_BFECR0_PT3_CC1: .equ %00001000 mIEVENT_BFECR0_PT3_BC0: .equ %00010000 mIEVENT_BFECR0_PT3_BC1: .equ %00100000 mIEVENT_BFECR0_PT3_AC0: .equ %01000000 mIEVENT_BFECR0_PT3_AC1: .equ %10000000 mIEVENT_BFECR0_PT2_DC0: .equ %100000000 mIEVENT_BFECR0_PT2_DC1: .equ %1000000000 mIEVENT_BFECR0_PT2_CC0: .equ %10000000000 mIEVENT_BFECR0_PT2_CC1: .equ %100000000000 mIEVENT_BFECR0_PT2_BC0: .equ %1000000000000 mIEVENT_BFECR0_PT2_BC1: .equ %10000000000000 mIEVENT_BFECR0_PT2_AC0: .equ %100000000000000 mIEVENT_BFECR0_PT2_AC1: .equ %1000000000000000 mIEVENT_BFECR0_PT1_DC0: .equ %10000000000000000 mIEVENT_BFECR0_PT1_DC1: .equ %100000000000000000 mIEVENT_BFECR0_PT1_CC0: .equ %1000000000000000000 mIEVENT_BFECR0_PT1_CC1: .equ %10000000000000000000 mIEVENT_BFECR0_PT1_BC0: .equ %100000000000000000000 mIEVENT_BFECR0_PT1_BC1: .equ %1000000000000000000000 mIEVENT_BFECR0_PT1_AC0: .equ %10000000000000000000000 mIEVENT_BFECR0_PT1_AC1: .equ %100000000000000000000000 mIEVENT_BFECR0_PT0_DC0: .equ %1000000000000000000000000 mIEVENT_BFECR0_PT0_DC1: .equ %10000000000000000000000000 mIEVENT_BFECR0_PT0_CC0: .equ %100000000000000000000000000 mIEVENT_BFECR0_PT0_CC1: .equ %1000000000000000000000000000 mIEVENT_BFECR0_PT0_BC0: .equ %10000000000000000000000000000 mIEVENT_BFECR0_PT0_BC1: .equ %100000000000000000000000000000 mIEVENT_BFECR0_PT0_AC0: .equ %1000000000000000000000000000000 mIEVENT_BFECR0_PT0_AC1: .equ %10000000000000000000000000000000 ;*** IEVENT_IMXCR1 - iEvent Input Mux Configuration Register 1; 0xFFFF9B08 *** IEVENT_IMXCR1: .equ $FFFF9B08 ;*** IEVENT_IMXCR1 - iEvent Input Mux Configuration Register 1; 0xFFFF9B08 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IEVENT_IMXCR1_D_Select0: .equ 0 ; D_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input D, bit 0 IEVENT_IMXCR1_D_Select1: .equ 1 ; D_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input D, bit 1 IEVENT_IMXCR1_D_Select2: .equ 2 ; D_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input D, bit 2 IEVENT_IMXCR1_D_Select3: .equ 3 ; D_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input D, bit 3 IEVENT_IMXCR1_C_Select0: .equ 8 ; C_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input C, bit 0 IEVENT_IMXCR1_C_Select1: .equ 9 ; C_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input C, bit 1 IEVENT_IMXCR1_C_Select2: .equ 10 ; C_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input C, bit 2 IEVENT_IMXCR1_C_Select3: .equ 11 ; C_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input C, bit 3 IEVENT_IMXCR1_B_Select0: .equ 16 ; B_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input B, bit 0 IEVENT_IMXCR1_B_Select1: .equ 17 ; B_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input B, bit 1 IEVENT_IMXCR1_B_Select2: .equ 18 ; B_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input B, bit 2 IEVENT_IMXCR1_B_Select3: .equ 19 ; B_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input B, bit 3 IEVENT_IMXCR1_A_Select0: .equ 24 ; A_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input A, bit 0 IEVENT_IMXCR1_A_Select1: .equ 25 ; A_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input A, bit 1 IEVENT_IMXCR1_A_Select2: .equ 26 ; A_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input A, bit 2 IEVENT_IMXCR1_A_Select3: .equ 27 ; A_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input A, bit 3 ; bit position masks mIEVENT_IMXCR1_D_Select0: .equ %00000001 mIEVENT_IMXCR1_D_Select1: .equ %00000010 mIEVENT_IMXCR1_D_Select2: .equ %00000100 mIEVENT_IMXCR1_D_Select3: .equ %00001000 mIEVENT_IMXCR1_C_Select0: .equ %100000000 mIEVENT_IMXCR1_C_Select1: .equ %1000000000 mIEVENT_IMXCR1_C_Select2: .equ %10000000000 mIEVENT_IMXCR1_C_Select3: .equ %100000000000 mIEVENT_IMXCR1_B_Select0: .equ %10000000000000000 mIEVENT_IMXCR1_B_Select1: .equ %100000000000000000 mIEVENT_IMXCR1_B_Select2: .equ %1000000000000000000 mIEVENT_IMXCR1_B_Select3: .equ %10000000000000000000 mIEVENT_IMXCR1_A_Select0: .equ %1000000000000000000000000 mIEVENT_IMXCR1_A_Select1: .equ %10000000000000000000000000 mIEVENT_IMXCR1_A_Select2: .equ %100000000000000000000000000 mIEVENT_IMXCR1_A_Select3: .equ %1000000000000000000000000000 ;*** IEVENT_BFECR1 - iEvent Boolean Function Evaluation Configuration Register 1; 0xFFFF9B0C *** IEVENT_BFECR1: .equ $FFFF9B0C ;*** IEVENT_BFECR1 - iEvent Boolean Function Evaluation Configuration Register 1; 0xFFFF9B0C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IEVENT_BFECR1_PT3_DC0: .equ 0 ; Product Term 3, D input Configuration, bit 0 IEVENT_BFECR1_PT3_DC1: .equ 1 ; Product Term 3, D input Configuration, bit 1 IEVENT_BFECR1_PT3_CC0: .equ 2 ; Product Term 3, C input Configuration, bit 0 IEVENT_BFECR1_PT3_CC1: .equ 3 ; Product Term 3, C input Configuration, bit 1 IEVENT_BFECR1_PT3_BC0: .equ 4 ; Product Term 3, B input Configuration, bit 0 IEVENT_BFECR1_PT3_BC1: .equ 5 ; Product Term 3, B input Configuration, bit 1 IEVENT_BFECR1_PT3_AC0: .equ 6 ; Product Term 3, A input Configuration, bit 0 IEVENT_BFECR1_PT3_AC1: .equ 7 ; Product Term 3, A input Configuration, bit 1 IEVENT_BFECR1_PT2_DC0: .equ 8 ; Product Term 2, D input Configuration, bit 0 IEVENT_BFECR1_PT2_DC1: .equ 9 ; Product Term 2, D input Configuration, bit 1 IEVENT_BFECR1_PT2_CC0: .equ 10 ; Product Term 2, C input Configuration, bit 0 IEVENT_BFECR1_PT2_CC1: .equ 11 ; Product Term 2, C input Configuration, bit 1 IEVENT_BFECR1_PT2_BC0: .equ 12 ; Product Term 2, B input Configuration, bit 0 IEVENT_BFECR1_PT2_BC1: .equ 13 ; Product Term 2, B input Configuration, bit 1 IEVENT_BFECR1_PT2_AC0: .equ 14 ; Product Term 2, A input Configuration, bit 0 IEVENT_BFECR1_PT2_AC1: .equ 15 ; Product Term 2, A input Configuration, bit 1 IEVENT_BFECR1_PT1_DC0: .equ 16 ; Product Term 1, D input Configuration, bit 0 IEVENT_BFECR1_PT1_DC1: .equ 17 ; Product Term 1, D input Configuration, bit 1 IEVENT_BFECR1_PT1_CC0: .equ 18 ; Product Term 1, C input Configuration, bit 0 IEVENT_BFECR1_PT1_CC1: .equ 19 ; Product Term 1, C input Configuration, bit 1 IEVENT_BFECR1_PT1_BC0: .equ 20 ; Product Term 1, B input Configuration, bit 0 IEVENT_BFECR1_PT1_BC1: .equ 21 ; Product Term 1, B input Configuration, bit 1 IEVENT_BFECR1_PT1_AC0: .equ 22 ; Product Term 1, A input Configuration, bit 0 IEVENT_BFECR1_PT1_AC1: .equ 23 ; Product Term 1, A input Configuration, bit 1 IEVENT_BFECR1_PT0_DC0: .equ 24 ; Product Term 0, D input Configuration, bit 0 IEVENT_BFECR1_PT0_DC1: .equ 25 ; Product Term 0, D input Configuration, bit 1 IEVENT_BFECR1_PT0_CC0: .equ 26 ; Product Term 0, C input Configuration, bit 0 IEVENT_BFECR1_PT0_CC1: .equ 27 ; Product Term 0, C input Configuration, bit 1 IEVENT_BFECR1_PT0_BC0: .equ 28 ; Product Term 0, B input Configuration, bit 0 IEVENT_BFECR1_PT0_BC1: .equ 29 ; Product Term 0, B input Configuration, bit 1 IEVENT_BFECR1_PT0_AC0: .equ 30 ; Product Term 0, A input Configuration, bit 0 IEVENT_BFECR1_PT0_AC1: .equ 31 ; Product Term 0, A input Configuration, bit 1 ; bit position masks mIEVENT_BFECR1_PT3_DC0: .equ %00000001 mIEVENT_BFECR1_PT3_DC1: .equ %00000010 mIEVENT_BFECR1_PT3_CC0: .equ %00000100 mIEVENT_BFECR1_PT3_CC1: .equ %00001000 mIEVENT_BFECR1_PT3_BC0: .equ %00010000 mIEVENT_BFECR1_PT3_BC1: .equ %00100000 mIEVENT_BFECR1_PT3_AC0: .equ %01000000 mIEVENT_BFECR1_PT3_AC1: .equ %10000000 mIEVENT_BFECR1_PT2_DC0: .equ %100000000 mIEVENT_BFECR1_PT2_DC1: .equ %1000000000 mIEVENT_BFECR1_PT2_CC0: .equ %10000000000 mIEVENT_BFECR1_PT2_CC1: .equ %100000000000 mIEVENT_BFECR1_PT2_BC0: .equ %1000000000000 mIEVENT_BFECR1_PT2_BC1: .equ %10000000000000 mIEVENT_BFECR1_PT2_AC0: .equ %100000000000000 mIEVENT_BFECR1_PT2_AC1: .equ %1000000000000000 mIEVENT_BFECR1_PT1_DC0: .equ %10000000000000000 mIEVENT_BFECR1_PT1_DC1: .equ %100000000000000000 mIEVENT_BFECR1_PT1_CC0: .equ %1000000000000000000 mIEVENT_BFECR1_PT1_CC1: .equ %10000000000000000000 mIEVENT_BFECR1_PT1_BC0: .equ %100000000000000000000 mIEVENT_BFECR1_PT1_BC1: .equ %1000000000000000000000 mIEVENT_BFECR1_PT1_AC0: .equ %10000000000000000000000 mIEVENT_BFECR1_PT1_AC1: .equ %100000000000000000000000 mIEVENT_BFECR1_PT0_DC0: .equ %1000000000000000000000000 mIEVENT_BFECR1_PT0_DC1: .equ %10000000000000000000000000 mIEVENT_BFECR1_PT0_CC0: .equ %100000000000000000000000000 mIEVENT_BFECR1_PT0_CC1: .equ %1000000000000000000000000000 mIEVENT_BFECR1_PT0_BC0: .equ %10000000000000000000000000000 mIEVENT_BFECR1_PT0_BC1: .equ %100000000000000000000000000000 mIEVENT_BFECR1_PT0_AC0: .equ %1000000000000000000000000000000 mIEVENT_BFECR1_PT0_AC1: .equ %10000000000000000000000000000000 ;*** IEVENT_IMXCR2 - iEvent Input Mux Configuration Register 2; 0xFFFF9B10 *** IEVENT_IMXCR2: .equ $FFFF9B10 ;*** IEVENT_IMXCR2 - iEvent Input Mux Configuration Register 2; 0xFFFF9B10 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IEVENT_IMXCR2_D_Select0: .equ 0 ; D_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input D, bit 0 IEVENT_IMXCR2_D_Select1: .equ 1 ; D_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input D, bit 1 IEVENT_IMXCR2_D_Select2: .equ 2 ; D_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input D, bit 2 IEVENT_IMXCR2_D_Select3: .equ 3 ; D_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input D, bit 3 IEVENT_IMXCR2_C_Select0: .equ 8 ; C_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input C, bit 0 IEVENT_IMXCR2_C_Select1: .equ 9 ; C_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input C, bit 1 IEVENT_IMXCR2_C_Select2: .equ 10 ; C_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input C, bit 2 IEVENT_IMXCR2_C_Select3: .equ 11 ; C_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input C, bit 3 IEVENT_IMXCR2_B_Select0: .equ 16 ; B_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input B, bit 0 IEVENT_IMXCR2_B_Select1: .equ 17 ; B_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input B, bit 1 IEVENT_IMXCR2_B_Select2: .equ 18 ; B_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input B, bit 2 IEVENT_IMXCR2_B_Select3: .equ 19 ; B_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input B, bit 3 IEVENT_IMXCR2_A_Select0: .equ 24 ; A_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input A, bit 0 IEVENT_IMXCR2_A_Select1: .equ 25 ; A_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input A, bit 1 IEVENT_IMXCR2_A_Select2: .equ 26 ; A_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input A, bit 2 IEVENT_IMXCR2_A_Select3: .equ 27 ; A_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input A, bit 3 ; bit position masks mIEVENT_IMXCR2_D_Select0: .equ %00000001 mIEVENT_IMXCR2_D_Select1: .equ %00000010 mIEVENT_IMXCR2_D_Select2: .equ %00000100 mIEVENT_IMXCR2_D_Select3: .equ %00001000 mIEVENT_IMXCR2_C_Select0: .equ %100000000 mIEVENT_IMXCR2_C_Select1: .equ %1000000000 mIEVENT_IMXCR2_C_Select2: .equ %10000000000 mIEVENT_IMXCR2_C_Select3: .equ %100000000000 mIEVENT_IMXCR2_B_Select0: .equ %10000000000000000 mIEVENT_IMXCR2_B_Select1: .equ %100000000000000000 mIEVENT_IMXCR2_B_Select2: .equ %1000000000000000000 mIEVENT_IMXCR2_B_Select3: .equ %10000000000000000000 mIEVENT_IMXCR2_A_Select0: .equ %1000000000000000000000000 mIEVENT_IMXCR2_A_Select1: .equ %10000000000000000000000000 mIEVENT_IMXCR2_A_Select2: .equ %100000000000000000000000000 mIEVENT_IMXCR2_A_Select3: .equ %1000000000000000000000000000 ;*** IEVENT_BFECR2 - iEvent Boolean Function Evaluation Configuration Register 2; 0xFFFF9B14 *** IEVENT_BFECR2: .equ $FFFF9B14 ;*** IEVENT_BFECR2 - iEvent Boolean Function Evaluation Configuration Register 2; 0xFFFF9B14 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IEVENT_BFECR2_PT3_DC0: .equ 0 ; Product Term 3, D input Configuration, bit 0 IEVENT_BFECR2_PT3_DC1: .equ 1 ; Product Term 3, D input Configuration, bit 1 IEVENT_BFECR2_PT3_CC0: .equ 2 ; Product Term 3, C input Configuration, bit 0 IEVENT_BFECR2_PT3_CC1: .equ 3 ; Product Term 3, C input Configuration, bit 1 IEVENT_BFECR2_PT3_BC0: .equ 4 ; Product Term 3, B input Configuration, bit 0 IEVENT_BFECR2_PT3_BC1: .equ 5 ; Product Term 3, B input Configuration, bit 1 IEVENT_BFECR2_PT3_AC0: .equ 6 ; Product Term 3, A input Configuration, bit 0 IEVENT_BFECR2_PT3_AC1: .equ 7 ; Product Term 3, A input Configuration, bit 1 IEVENT_BFECR2_PT2_DC0: .equ 8 ; Product Term 2, D input Configuration, bit 0 IEVENT_BFECR2_PT2_DC1: .equ 9 ; Product Term 2, D input Configuration, bit 1 IEVENT_BFECR2_PT2_CC0: .equ 10 ; Product Term 2, C input Configuration, bit 0 IEVENT_BFECR2_PT2_CC1: .equ 11 ; Product Term 2, C input Configuration, bit 1 IEVENT_BFECR2_PT2_BC0: .equ 12 ; Product Term 2, B input Configuration, bit 0 IEVENT_BFECR2_PT2_BC1: .equ 13 ; Product Term 2, B input Configuration, bit 1 IEVENT_BFECR2_PT2_AC0: .equ 14 ; Product Term 2, A input Configuration, bit 0 IEVENT_BFECR2_PT2_AC1: .equ 15 ; Product Term 2, A input Configuration, bit 1 IEVENT_BFECR2_PT1_DC0: .equ 16 ; Product Term 1, D input Configuration, bit 0 IEVENT_BFECR2_PT1_DC1: .equ 17 ; Product Term 1, D input Configuration, bit 1 IEVENT_BFECR2_PT1_CC0: .equ 18 ; Product Term 1, C input Configuration, bit 0 IEVENT_BFECR2_PT1_CC1: .equ 19 ; Product Term 1, C input Configuration, bit 1 IEVENT_BFECR2_PT1_BC0: .equ 20 ; Product Term 1, B input Configuration, bit 0 IEVENT_BFECR2_PT1_BC1: .equ 21 ; Product Term 1, B input Configuration, bit 1 IEVENT_BFECR2_PT1_AC0: .equ 22 ; Product Term 1, A input Configuration, bit 0 IEVENT_BFECR2_PT1_AC1: .equ 23 ; Product Term 1, A input Configuration, bit 1 IEVENT_BFECR2_PT0_DC0: .equ 24 ; Product Term 0, D input Configuration, bit 0 IEVENT_BFECR2_PT0_DC1: .equ 25 ; Product Term 0, D input Configuration, bit 1 IEVENT_BFECR2_PT0_CC0: .equ 26 ; Product Term 0, C input Configuration, bit 0 IEVENT_BFECR2_PT0_CC1: .equ 27 ; Product Term 0, C input Configuration, bit 1 IEVENT_BFECR2_PT0_BC0: .equ 28 ; Product Term 0, B input Configuration, bit 0 IEVENT_BFECR2_PT0_BC1: .equ 29 ; Product Term 0, B input Configuration, bit 1 IEVENT_BFECR2_PT0_AC0: .equ 30 ; Product Term 0, A input Configuration, bit 0 IEVENT_BFECR2_PT0_AC1: .equ 31 ; Product Term 0, A input Configuration, bit 1 ; bit position masks mIEVENT_BFECR2_PT3_DC0: .equ %00000001 mIEVENT_BFECR2_PT3_DC1: .equ %00000010 mIEVENT_BFECR2_PT3_CC0: .equ %00000100 mIEVENT_BFECR2_PT3_CC1: .equ %00001000 mIEVENT_BFECR2_PT3_BC0: .equ %00010000 mIEVENT_BFECR2_PT3_BC1: .equ %00100000 mIEVENT_BFECR2_PT3_AC0: .equ %01000000 mIEVENT_BFECR2_PT3_AC1: .equ %10000000 mIEVENT_BFECR2_PT2_DC0: .equ %100000000 mIEVENT_BFECR2_PT2_DC1: .equ %1000000000 mIEVENT_BFECR2_PT2_CC0: .equ %10000000000 mIEVENT_BFECR2_PT2_CC1: .equ %100000000000 mIEVENT_BFECR2_PT2_BC0: .equ %1000000000000 mIEVENT_BFECR2_PT2_BC1: .equ %10000000000000 mIEVENT_BFECR2_PT2_AC0: .equ %100000000000000 mIEVENT_BFECR2_PT2_AC1: .equ %1000000000000000 mIEVENT_BFECR2_PT1_DC0: .equ %10000000000000000 mIEVENT_BFECR2_PT1_DC1: .equ %100000000000000000 mIEVENT_BFECR2_PT1_CC0: .equ %1000000000000000000 mIEVENT_BFECR2_PT1_CC1: .equ %10000000000000000000 mIEVENT_BFECR2_PT1_BC0: .equ %100000000000000000000 mIEVENT_BFECR2_PT1_BC1: .equ %1000000000000000000000 mIEVENT_BFECR2_PT1_AC0: .equ %10000000000000000000000 mIEVENT_BFECR2_PT1_AC1: .equ %100000000000000000000000 mIEVENT_BFECR2_PT0_DC0: .equ %1000000000000000000000000 mIEVENT_BFECR2_PT0_DC1: .equ %10000000000000000000000000 mIEVENT_BFECR2_PT0_CC0: .equ %100000000000000000000000000 mIEVENT_BFECR2_PT0_CC1: .equ %1000000000000000000000000000 mIEVENT_BFECR2_PT0_BC0: .equ %10000000000000000000000000000 mIEVENT_BFECR2_PT0_BC1: .equ %100000000000000000000000000000 mIEVENT_BFECR2_PT0_AC0: .equ %1000000000000000000000000000000 mIEVENT_BFECR2_PT0_AC1: .equ %10000000000000000000000000000000 ;*** IEVENT_IMXCR3 - iEvent Input Mux Configuration Register 3; 0xFFFF9B18 *** IEVENT_IMXCR3: .equ $FFFF9B18 ;*** IEVENT_IMXCR3 - iEvent Input Mux Configuration Register 3; 0xFFFF9B18 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IEVENT_IMXCR3_D_Select0: .equ 0 ; D_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input D, bit 0 IEVENT_IMXCR3_D_Select1: .equ 1 ; D_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input D, bit 1 IEVENT_IMXCR3_D_Select2: .equ 2 ; D_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input D, bit 2 IEVENT_IMXCR3_D_Select3: .equ 3 ; D_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input D, bit 3 IEVENT_IMXCR3_C_Select0: .equ 8 ; C_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input C, bit 0 IEVENT_IMXCR3_C_Select1: .equ 9 ; C_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input C, bit 1 IEVENT_IMXCR3_C_Select2: .equ 10 ; C_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input C, bit 2 IEVENT_IMXCR3_C_Select3: .equ 11 ; C_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input C, bit 3 IEVENT_IMXCR3_B_Select0: .equ 16 ; B_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input B, bit 0 IEVENT_IMXCR3_B_Select1: .equ 17 ; B_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input B, bit 1 IEVENT_IMXCR3_B_Select2: .equ 18 ; B_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input B, bit 2 IEVENT_IMXCR3_B_Select3: .equ 19 ; B_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input B, bit 3 IEVENT_IMXCR3_A_Select0: .equ 24 ; A_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input A, bit 0 IEVENT_IMXCR3_A_Select1: .equ 25 ; A_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input A, bit 1 IEVENT_IMXCR3_A_Select2: .equ 26 ; A_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input A, bit 2 IEVENT_IMXCR3_A_Select3: .equ 27 ; A_Select. This 4-bit field defines the bit number of the 16-bit event input vector to be selected as input A, bit 3 ; bit position masks mIEVENT_IMXCR3_D_Select0: .equ %00000001 mIEVENT_IMXCR3_D_Select1: .equ %00000010 mIEVENT_IMXCR3_D_Select2: .equ %00000100 mIEVENT_IMXCR3_D_Select3: .equ %00001000 mIEVENT_IMXCR3_C_Select0: .equ %100000000 mIEVENT_IMXCR3_C_Select1: .equ %1000000000 mIEVENT_IMXCR3_C_Select2: .equ %10000000000 mIEVENT_IMXCR3_C_Select3: .equ %100000000000 mIEVENT_IMXCR3_B_Select0: .equ %10000000000000000 mIEVENT_IMXCR3_B_Select1: .equ %100000000000000000 mIEVENT_IMXCR3_B_Select2: .equ %1000000000000000000 mIEVENT_IMXCR3_B_Select3: .equ %10000000000000000000 mIEVENT_IMXCR3_A_Select0: .equ %1000000000000000000000000 mIEVENT_IMXCR3_A_Select1: .equ %10000000000000000000000000 mIEVENT_IMXCR3_A_Select2: .equ %100000000000000000000000000 mIEVENT_IMXCR3_A_Select3: .equ %1000000000000000000000000000 ;*** IEVENT_BFECR3 - iEvent Boolean Function Evaluation Configuration Register 3; 0xFFFF9B1C *** IEVENT_BFECR3: .equ $FFFF9B1C ;*** IEVENT_BFECR3 - iEvent Boolean Function Evaluation Configuration Register 3; 0xFFFF9B1C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET IEVENT_BFECR3_PT3_DC0: .equ 0 ; Product Term 3, D input Configuration, bit 0 IEVENT_BFECR3_PT3_DC1: .equ 1 ; Product Term 3, D input Configuration, bit 1 IEVENT_BFECR3_PT3_CC0: .equ 2 ; Product Term 3, C input Configuration, bit 0 IEVENT_BFECR3_PT3_CC1: .equ 3 ; Product Term 3, C input Configuration, bit 1 IEVENT_BFECR3_PT3_BC0: .equ 4 ; Product Term 3, B input Configuration, bit 0 IEVENT_BFECR3_PT3_BC1: .equ 5 ; Product Term 3, B input Configuration, bit 1 IEVENT_BFECR3_PT3_AC0: .equ 6 ; Product Term 3, A input Configuration, bit 0 IEVENT_BFECR3_PT3_AC1: .equ 7 ; Product Term 3, A input Configuration, bit 1 IEVENT_BFECR3_PT2_DC0: .equ 8 ; Product Term 2, D input Configuration, bit 0 IEVENT_BFECR3_PT2_DC1: .equ 9 ; Product Term 2, D input Configuration, bit 1 IEVENT_BFECR3_PT2_CC0: .equ 10 ; Product Term 2, C input Configuration, bit 0 IEVENT_BFECR3_PT2_CC1: .equ 11 ; Product Term 2, C input Configuration, bit 1 IEVENT_BFECR3_PT2_BC0: .equ 12 ; Product Term 2, B input Configuration, bit 0 IEVENT_BFECR3_PT2_BC1: .equ 13 ; Product Term 2, B input Configuration, bit 1 IEVENT_BFECR3_PT2_AC0: .equ 14 ; Product Term 2, A input Configuration, bit 0 IEVENT_BFECR3_PT2_AC1: .equ 15 ; Product Term 2, A input Configuration, bit 1 IEVENT_BFECR3_PT1_DC0: .equ 16 ; Product Term 1, D input Configuration, bit 0 IEVENT_BFECR3_PT1_DC1: .equ 17 ; Product Term 1, D input Configuration, bit 1 IEVENT_BFECR3_PT1_CC0: .equ 18 ; Product Term 1, C input Configuration, bit 0 IEVENT_BFECR3_PT1_CC1: .equ 19 ; Product Term 1, C input Configuration, bit 1 IEVENT_BFECR3_PT1_BC0: .equ 20 ; Product Term 1, B input Configuration, bit 0 IEVENT_BFECR3_PT1_BC1: .equ 21 ; Product Term 1, B input Configuration, bit 1 IEVENT_BFECR3_PT1_AC0: .equ 22 ; Product Term 1, A input Configuration, bit 0 IEVENT_BFECR3_PT1_AC1: .equ 23 ; Product Term 1, A input Configuration, bit 1 IEVENT_BFECR3_PT0_DC0: .equ 24 ; Product Term 0, D input Configuration, bit 0 IEVENT_BFECR3_PT0_DC1: .equ 25 ; Product Term 0, D input Configuration, bit 1 IEVENT_BFECR3_PT0_CC0: .equ 26 ; Product Term 0, C input Configuration, bit 0 IEVENT_BFECR3_PT0_CC1: .equ 27 ; Product Term 0, C input Configuration, bit 1 IEVENT_BFECR3_PT0_BC0: .equ 28 ; Product Term 0, B input Configuration, bit 0 IEVENT_BFECR3_PT0_BC1: .equ 29 ; Product Term 0, B input Configuration, bit 1 IEVENT_BFECR3_PT0_AC0: .equ 30 ; Product Term 0, A input Configuration, bit 0 IEVENT_BFECR3_PT0_AC1: .equ 31 ; Product Term 0, A input Configuration, bit 1 ; bit position masks mIEVENT_BFECR3_PT3_DC0: .equ %00000001 mIEVENT_BFECR3_PT3_DC1: .equ %00000010 mIEVENT_BFECR3_PT3_CC0: .equ %00000100 mIEVENT_BFECR3_PT3_CC1: .equ %00001000 mIEVENT_BFECR3_PT3_BC0: .equ %00010000 mIEVENT_BFECR3_PT3_BC1: .equ %00100000 mIEVENT_BFECR3_PT3_AC0: .equ %01000000 mIEVENT_BFECR3_PT3_AC1: .equ %10000000 mIEVENT_BFECR3_PT2_DC0: .equ %100000000 mIEVENT_BFECR3_PT2_DC1: .equ %1000000000 mIEVENT_BFECR3_PT2_CC0: .equ %10000000000 mIEVENT_BFECR3_PT2_CC1: .equ %100000000000 mIEVENT_BFECR3_PT2_BC0: .equ %1000000000000 mIEVENT_BFECR3_PT2_BC1: .equ %10000000000000 mIEVENT_BFECR3_PT2_AC0: .equ %100000000000000 mIEVENT_BFECR3_PT2_AC1: .equ %1000000000000000 mIEVENT_BFECR3_PT1_DC0: .equ %10000000000000000 mIEVENT_BFECR3_PT1_DC1: .equ %100000000000000000 mIEVENT_BFECR3_PT1_CC0: .equ %1000000000000000000 mIEVENT_BFECR3_PT1_CC1: .equ %10000000000000000000 mIEVENT_BFECR3_PT1_BC0: .equ %100000000000000000000 mIEVENT_BFECR3_PT1_BC1: .equ %1000000000000000000000 mIEVENT_BFECR3_PT1_AC0: .equ %10000000000000000000000 mIEVENT_BFECR3_PT1_AC1: .equ %100000000000000000000000 mIEVENT_BFECR3_PT0_DC0: .equ %1000000000000000000000000 mIEVENT_BFECR3_PT0_DC1: .equ %10000000000000000000000000 mIEVENT_BFECR3_PT0_CC0: .equ %100000000000000000000000000 mIEVENT_BFECR3_PT0_CC1: .equ %1000000000000000000000000000 mIEVENT_BFECR3_PT0_BC0: .equ %10000000000000000000000000000 mIEVENT_BFECR3_PT0_BC1: .equ %100000000000000000000000000000 mIEVENT_BFECR3_PT0_AC0: .equ %1000000000000000000000000000000 mIEVENT_BFECR3_PT0_AC1: .equ %10000000000000000000000000000000 ;*** DMAREQC - DMA Request Control; 0xFFFFE400 *** DMAREQC: .equ $FFFFE400 ;*** DMAREQC - DMA Request Control; 0xFFFFE400 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DMAREQC_DMAC3: .equ 0 ; DMA Channel 3 DMAREQC_DMAC2: .equ 8 ; DMA Channel 2 DMAREQC_DMAC1: .equ 16 ; DMA Channel 1 DMAREQC_DMAC0: .equ 24 ; DMA Channel 0 ; bit position masks mDMAREQC_DMAC3: .equ %00001111 mDMAREQC_DMAC2: .equ %111100000000 mDMAREQC_DMAC1: .equ %11110000000000000000 mDMAREQC_DMAC0: .equ %1111000000000000000000000000 ;*** SAR0 - Source Address Register 0; 0xFFFFE500 *** SAR0: .equ $FFFFE500 ;*** SAR0 - Source Address Register 0; 0xFFFFE500 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SAR0_SAR: .equ 0 ; Source address ; bit position masks mSAR0_SAR: .equ %111111111111111111111111 ;*** DAR0 - Destination Address Register 0; 0xFFFFE504 *** DAR0: .equ $FFFFE504 ;*** DAR0 - Destination Address Register 0; 0xFFFFE504 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DAR0_DAR: .equ 0 ; Destination address ; bit position masks mDAR0_DAR: .equ %111111111111111111111111 ;*** BCR0 - Byte Count Register 0; 0xFFFFE508 *** BCR0: .equ $FFFFE508 ;*** BCR0 - Byte Count Register 0; 0xFFFFE508 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET BCR0_BCR: .equ 0 ; Byte count BCR0_DSR: .equ 24 ; DMA Status Register ; bit position masks mBCR0_BCR: .equ %111111111111111111111111 mBCR0_DSR: .equ %11111111000000000000000000000000 ;*** DSR0 - DMA Status Register 0; 0xFFFFE508 *** DSR0: .equ $FFFFE508 ;*** DSR0 - DMA Status Register 0; 0xFFFFE508 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DSR0_DONE: .equ 0 ; Transactions done. Set when all DMA controller transactions complete, as determined by transfer count or error conditions. When BCR reaches zero, DONE is set when the final transfer completes successfully. DONE can also be used to abort a transfer by re... DSR0_BSY: .equ 1 ; Busy DSR0_REQ: .equ 2 ; Request DSR0_BED: .equ 4 ; Bus error on destination DSR0_BES: .equ 5 ; Bus error on source DSR0_CE: .equ 6 ; Configuration error. Occurs when BCR, SAR, or DAR does not match the requested transfer size, or if BCR = 0 when the DMA receives a start condition. CE is cleared at hardware reset or by writing a 1 to DSR[DONE] ; bit position masks mDSR0_DONE: .equ %00000001 mDSR0_BSY: .equ %00000010 mDSR0_REQ: .equ %00000100 mDSR0_BED: .equ %00010000 mDSR0_BES: .equ %00100000 mDSR0_CE: .equ %01000000 ;*** DCR0 - DMA Control Register 0; 0xFFFFE50C *** DCR0: .equ $FFFFE50C ;*** DCR0 - DMA Control Register 0; 0xFFFFE50C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DCR0_LCH2: .equ 0 ; Link channel 2. Indicates the DMA channel assigned as link channel 2. The link channel number cannot be the same as the currently executing channel, and generates a configuration error if this is attempted (DSR0[CE] is set) DCR0_LCH1: .equ 2 ; Link channel 1. Indicates the DMA channel assigned as link channel 1. The link channel number cannot be the same as the currently executing channel, and generates a configuration error if this is attempted (DSR0[CE] is set) DCR0_LINKCC: .equ 4 ; Link channel control. Allows DMA channels to have their transfers linked. The current DMA channel will trigger a DMA request to the linked channels (LCH1 or LCH2) depending on the condition described by the LINKCC bits. The LINKCC field provides a 2-bit... DCR0_D_REQ: .equ 7 ; Disable request. If this flag is set, the DMA hardware automatically clears the DCR0[ERQ] bit when the byte count register reaches zero DCR0_DMOD: .equ 8 ; Destination address modulo. Defines the size of the destination data circular buffer used by the DMA controller DCR0_SMOD: .equ 12 ; Source address modulo. Defines the size of the source data circular buffer used by the DMA controller DCR0_START: .equ 16 ; Start transfer DCR0_DSIZE: .equ 17 ; Destination size. Determines the data size of the destination bus cycle for the DMA controller DCR0_DINC: .equ 19 ; Destination increment. Controls whether a destination address increments after each successful transfer DCR0_SSIZE: .equ 20 ; Source size. Determines the data size of the source bus cycle for the DMA control module DCR0_SINC: .equ 22 ; Source increment. Controls whether a source address increments after each successful transfer DCR0_AA: .equ 28 ; Auto-align. AA and SIZE determine whether the source or destination is auto-aligned, that is, transfers are optimized based on the address and size DCR0_CS: .equ 29 ; Cycle steal DCR0_ERQ: .equ 30 ; Enable peripheral request. Care should be taken because a collision can occur between the START bit and DREQ0 when ERQ equals 1 DCR0_EINT: .equ 31 ; Interrupt on completion of transfer. Determines whether an interrupt is generated by completing a transfer or by the occurrence of an error condition ; bit position masks mDCR0_LCH2: .equ %00000011 mDCR0_LCH1: .equ %00001100 mDCR0_LINKCC: .equ %00110000 mDCR0_D_REQ: .equ %10000000 mDCR0_DMOD: .equ %111100000000 mDCR0_SMOD: .equ %1111000000000000 mDCR0_START: .equ %10000000000000000 mDCR0_DSIZE: .equ %1100000000000000000 mDCR0_DINC: .equ %10000000000000000000 mDCR0_SSIZE: .equ %1100000000000000000000 mDCR0_SINC: .equ %10000000000000000000000 mDCR0_AA: .equ %10000000000000000000000000000 mDCR0_CS: .equ %100000000000000000000000000000 mDCR0_ERQ: .equ %1000000000000000000000000000000 mDCR0_EINT: .equ %10000000000000000000000000000000 ;*** SAR1 - Source Address Register 1; 0xFFFFE510 *** SAR1: .equ $FFFFE510 ;*** SAR1 - Source Address Register 1; 0xFFFFE510 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SAR1_SAR: .equ 0 ; Source address ; bit position masks mSAR1_SAR: .equ %111111111111111111111111 ;*** DAR1 - Destination Address Register 1; 0xFFFFE514 *** DAR1: .equ $FFFFE514 ;*** DAR1 - Destination Address Register 1; 0xFFFFE514 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DAR1_DAR: .equ 0 ; Destination address ; bit position masks mDAR1_DAR: .equ %111111111111111111111111 ;*** BCR1 - Byte Count Register 1; 0xFFFFE518 *** BCR1: .equ $FFFFE518 ;*** BCR1 - Byte Count Register 1; 0xFFFFE518 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET BCR1_BCR: .equ 0 ; Byte count BCR1_DSR: .equ 24 ; DMA Status Register ; bit position masks mBCR1_BCR: .equ %111111111111111111111111 mBCR1_DSR: .equ %11111111000000000000000000000000 ;*** DSR1 - DMA Status Register 1; 0xFFFFE518 *** DSR1: .equ $FFFFE518 ;*** DSR1 - DMA Status Register 1; 0xFFFFE518 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DSR1_DONE: .equ 0 ; Transactions done. Set when all DMA controller transactions complete, as determined by transfer count or error conditions. When BCR reaches zero, DONE is set when the final transfer completes successfully. DONE can also be used to abort a transfer by re... DSR1_BSY: .equ 1 ; Busy DSR1_REQ: .equ 2 ; Request DSR1_BED: .equ 4 ; Bus error on destination DSR1_BES: .equ 5 ; Bus error on source DSR1_CE: .equ 6 ; Configuration error. Occurs when BCR, SAR, or DAR does not match the requested transfer size, or if BCR = 0 when the DMA receives a start condition. CE is cleared at hardware reset or by writing a 1 to DSR[DONE] ; bit position masks mDSR1_DONE: .equ %00000001 mDSR1_BSY: .equ %00000010 mDSR1_REQ: .equ %00000100 mDSR1_BED: .equ %00010000 mDSR1_BES: .equ %00100000 mDSR1_CE: .equ %01000000 ;*** DCR1 - DMA Control Register 1; 0xFFFFE51C *** DCR1: .equ $FFFFE51C ;*** DCR1 - DMA Control Register 1; 0xFFFFE51C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DCR1_LCH2: .equ 0 ; Link channel 2. Indicates the DMA channel assigned as link channel 2. The link channel number cannot be the same as the currently executing channel, and generates a configuration error if this is attempted (DSR1[CE] is set) DCR1_LCH1: .equ 2 ; Link channel 1. Indicates the DMA channel assigned as link channel 1. The link channel number cannot be the same as the currently executing channel, and generates a configuration error if this is attempted (DSR1[CE] is set) DCR1_LINKCC: .equ 4 ; Link channel control. Allows DMA channels to have their transfers linked. The current DMA channel will trigger a DMA request to the linked channels (LCH1 or LCH2) depending on the condition described by the LINKCC bits. The LINKCC field provides a 2-bit... DCR1_D_REQ: .equ 7 ; Disable request. If this flag is set, the DMA hardware automatically clears the DCR1[ERQ] bit when the byte count register reaches zero DCR1_DMOD: .equ 8 ; Destination address modulo. Defines the size of the destination data circular buffer used by the DMA controller DCR1_SMOD: .equ 12 ; Source address modulo. Defines the size of the source data circular buffer used by the DMA controller DCR1_START: .equ 16 ; Start transfer DCR1_DSIZE: .equ 17 ; Destination size. Determines the data size of the destination bus cycle for the DMA controller DCR1_DINC: .equ 19 ; Destination increment. Controls whether a destination address increments after each successful transfer DCR1_SSIZE: .equ 20 ; Source size. Determines the data size of the source bus cycle for the DMA control module DCR1_SINC: .equ 22 ; Source increment. Controls whether a source address increments after each successful transfer DCR1_AA: .equ 28 ; Auto-align. AA and SIZE determine whether the source or destination is auto-aligned, that is, transfers are optimized based on the address and size DCR1_CS: .equ 29 ; Cycle steal DCR1_ERQ: .equ 30 ; Enable peripheral request. Care should be taken because a collision can occur between the START bit and DREQ1 when ERQ equals 1 DCR1_EINT: .equ 31 ; Interrupt on completion of transfer. Determines whether an interrupt is generated by completing a transfer or by the occurrence of an error condition ; bit position masks mDCR1_LCH2: .equ %00000011 mDCR1_LCH1: .equ %00001100 mDCR1_LINKCC: .equ %00110000 mDCR1_D_REQ: .equ %10000000 mDCR1_DMOD: .equ %111100000000 mDCR1_SMOD: .equ %1111000000000000 mDCR1_START: .equ %10000000000000000 mDCR1_DSIZE: .equ %1100000000000000000 mDCR1_DINC: .equ %10000000000000000000 mDCR1_SSIZE: .equ %1100000000000000000000 mDCR1_SINC: .equ %10000000000000000000000 mDCR1_AA: .equ %10000000000000000000000000000 mDCR1_CS: .equ %100000000000000000000000000000 mDCR1_ERQ: .equ %1000000000000000000000000000000 mDCR1_EINT: .equ %10000000000000000000000000000000 ;*** SAR2 - Source Address Register 2; 0xFFFFE520 *** SAR2: .equ $FFFFE520 ;*** SAR2 - Source Address Register 2; 0xFFFFE520 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SAR2_SAR: .equ 0 ; Source address ; bit position masks mSAR2_SAR: .equ %111111111111111111111111 ;*** DAR2 - Destination Address Register 2; 0xFFFFE524 *** DAR2: .equ $FFFFE524 ;*** DAR2 - Destination Address Register 2; 0xFFFFE524 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DAR2_DAR: .equ 0 ; Destination address ; bit position masks mDAR2_DAR: .equ %111111111111111111111111 ;*** BCR2 - Byte Count Register 2; 0xFFFFE528 *** BCR2: .equ $FFFFE528 ;*** BCR2 - Byte Count Register 2; 0xFFFFE528 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET BCR2_BCR: .equ 0 ; Byte count BCR2_DSR: .equ 24 ; DMA Status Register ; bit position masks mBCR2_BCR: .equ %111111111111111111111111 mBCR2_DSR: .equ %11111111000000000000000000000000 ;*** DSR2 - DMA Status Register 2; 0xFFFFE528 *** DSR2: .equ $FFFFE528 ;*** DSR2 - DMA Status Register 2; 0xFFFFE528 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DSR2_DONE: .equ 0 ; Transactions done. Set when all DMA controller transactions complete, as determined by transfer count or error conditions. When BCR reaches zero, DONE is set when the final transfer completes successfully. DONE can also be used to abort a transfer by re... DSR2_BSY: .equ 1 ; Busy DSR2_REQ: .equ 2 ; Request DSR2_BED: .equ 4 ; Bus error on destination DSR2_BES: .equ 5 ; Bus error on source DSR2_CE: .equ 6 ; Configuration error. Occurs when BCR, SAR, or DAR does not match the requested transfer size, or if BCR = 0 when the DMA receives a start condition. CE is cleared at hardware reset or by writing a 1 to DSR[DONE] ; bit position masks mDSR2_DONE: .equ %00000001 mDSR2_BSY: .equ %00000010 mDSR2_REQ: .equ %00000100 mDSR2_BED: .equ %00010000 mDSR2_BES: .equ %00100000 mDSR2_CE: .equ %01000000 ;*** DCR2 - DMA Control Register 2; 0xFFFFE52C *** DCR2: .equ $FFFFE52C ;*** DCR2 - DMA Control Register 2; 0xFFFFE52C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DCR2_LCH2: .equ 0 ; Link channel 2. Indicates the DMA channel assigned as link channel 2. The link channel number cannot be the same as the currently executing channel, and generates a configuration error if this is attempted (DSR2[CE] is set) DCR2_LCH1: .equ 2 ; Link channel 1. Indicates the DMA channel assigned as link channel 1. The link channel number cannot be the same as the currently executing channel, and generates a configuration error if this is attempted (DSR2[CE] is set) DCR2_LINKCC: .equ 4 ; Link channel control. Allows DMA channels to have their transfers linked. The current DMA channel will trigger a DMA request to the linked channels (LCH1 or LCH2) depending on the condition described by the LINKCC bits. The LINKCC field provides a 2-bit... DCR2_D_REQ: .equ 7 ; Disable request. If this flag is set, the DMA hardware automatically clears the DCR2[ERQ] bit when the byte count register reaches zero DCR2_DMOD: .equ 8 ; Destination address modulo. Defines the size of the destination data circular buffer used by the DMA controller DCR2_SMOD: .equ 12 ; Source address modulo. Defines the size of the source data circular buffer used by the DMA controller DCR2_START: .equ 16 ; Start transfer DCR2_DSIZE: .equ 17 ; Destination size. Determines the data size of the destination bus cycle for the DMA controller DCR2_DINC: .equ 19 ; Destination increment. Controls whether a destination address increments after each successful transfer DCR2_SSIZE: .equ 20 ; Source size. Determines the data size of the source bus cycle for the DMA control module DCR2_SINC: .equ 22 ; Source increment. Controls whether a source address increments after each successful transfer DCR2_AA: .equ 28 ; Auto-align. AA and SIZE determine whether the source or destination is auto-aligned, that is, transfers are optimized based on the address and size DCR2_CS: .equ 29 ; Cycle steal DCR2_ERQ: .equ 30 ; Enable peripheral request. Care should be taken because a collision can occur between the START bit and DREQ2 when ERQ equals 1 DCR2_EINT: .equ 31 ; Interrupt on completion of transfer. Determines whether an interrupt is generated by completing a transfer or by the occurrence of an error condition ; bit position masks mDCR2_LCH2: .equ %00000011 mDCR2_LCH1: .equ %00001100 mDCR2_LINKCC: .equ %00110000 mDCR2_D_REQ: .equ %10000000 mDCR2_DMOD: .equ %111100000000 mDCR2_SMOD: .equ %1111000000000000 mDCR2_START: .equ %10000000000000000 mDCR2_DSIZE: .equ %1100000000000000000 mDCR2_DINC: .equ %10000000000000000000 mDCR2_SSIZE: .equ %1100000000000000000000 mDCR2_SINC: .equ %10000000000000000000000 mDCR2_AA: .equ %10000000000000000000000000000 mDCR2_CS: .equ %100000000000000000000000000000 mDCR2_ERQ: .equ %1000000000000000000000000000000 mDCR2_EINT: .equ %10000000000000000000000000000000 ;*** SAR3 - Source Address Register 3; 0xFFFFE530 *** SAR3: .equ $FFFFE530 ;*** SAR3 - Source Address Register 3; 0xFFFFE530 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET SAR3_SAR: .equ 0 ; Source address ; bit position masks mSAR3_SAR: .equ %111111111111111111111111 ;*** DAR3 - Destination Address Register 3; 0xFFFFE534 *** DAR3: .equ $FFFFE534 ;*** DAR3 - Destination Address Register 3; 0xFFFFE534 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DAR3_DAR: .equ 0 ; Destination address ; bit position masks mDAR3_DAR: .equ %111111111111111111111111 ;*** BCR3 - Byte Count Register 3; 0xFFFFE538 *** BCR3: .equ $FFFFE538 ;*** BCR3 - Byte Count Register 3; 0xFFFFE538 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET BCR3_BCR: .equ 0 ; Byte count BCR3_DSR: .equ 24 ; DMA Status Register ; bit position masks mBCR3_BCR: .equ %111111111111111111111111 mBCR3_DSR: .equ %11111111000000000000000000000000 ;*** DSR3 - DMA Status Register 3; 0xFFFFE538 *** DSR3: .equ $FFFFE538 ;*** DSR3 - DMA Status Register 3; 0xFFFFE538 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DSR3_DONE: .equ 0 ; Transactions done. Set when all DMA controller transactions complete, as determined by transfer count or error conditions. When BCR reaches zero, DONE is set when the final transfer completes successfully. DONE can also be used to abort a transfer by re... DSR3_BSY: .equ 1 ; Busy DSR3_REQ: .equ 2 ; Request DSR3_BED: .equ 4 ; Bus error on destination DSR3_BES: .equ 5 ; Bus error on source DSR3_CE: .equ 6 ; Configuration error. Occurs when BCR, SAR, or DAR does not match the requested transfer size, or if BCR = 0 when the DMA receives a start condition. CE is cleared at hardware reset or by writing a 1 to DSR[DONE] ; bit position masks mDSR3_DONE: .equ %00000001 mDSR3_BSY: .equ %00000010 mDSR3_REQ: .equ %00000100 mDSR3_BED: .equ %00010000 mDSR3_BES: .equ %00100000 mDSR3_CE: .equ %01000000 ;*** DCR3 - DMA Control Register 3; 0xFFFFE53C *** DCR3: .equ $FFFFE53C ;*** DCR3 - DMA Control Register 3; 0xFFFFE53C *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET DCR3_LCH2: .equ 0 ; Link channel 2. Indicates the DMA channel assigned as link channel 2. The link channel number cannot be the same as the currently executing channel, and generates a configuration error if this is attempted (DSR3[CE] is set) DCR3_LCH1: .equ 2 ; Link channel 1. Indicates the DMA channel assigned as link channel 1. The link channel number cannot be the same as the currently executing channel, and generates a configuration error if this is attempted (DSR3[CE] is set) DCR3_LINKCC: .equ 4 ; Link channel control. Allows DMA channels to have their transfers linked. The current DMA channel will trigger a DMA request to the linked channels (LCH1 or LCH2) depending on the condition described by the LINKCC bits. The LINKCC field provides a 2-bit... DCR3_D_REQ: .equ 7 ; Disable request. If this flag is set, the DMA hardware automatically clears the DCR3[ERQ] bit when the byte count register reaches zero DCR3_DMOD: .equ 8 ; Destination address modulo. Defines the size of the destination data circular buffer used by the DMA controller DCR3_SMOD: .equ 12 ; Source address modulo. Defines the size of the source data circular buffer used by the DMA controller DCR3_START: .equ 16 ; Start transfer DCR3_DSIZE: .equ 17 ; Destination size. Determines the data size of the destination bus cycle for the DMA controller DCR3_DINC: .equ 19 ; Destination increment. Controls whether a destination address increments after each successful transfer DCR3_SSIZE: .equ 20 ; Source size. Determines the data size of the source bus cycle for the DMA control module DCR3_SINC: .equ 22 ; Source increment. Controls whether a source address increments after each successful transfer DCR3_AA: .equ 28 ; Auto-align. AA and SIZE determine whether the source or destination is auto-aligned, that is, transfers are optimized based on the address and size DCR3_CS: .equ 29 ; Cycle steal DCR3_ERQ: .equ 30 ; Enable peripheral request. Care should be taken because a collision can occur between the START bit and DREQ3 when ERQ equals 1 DCR3_EINT: .equ 31 ; Interrupt on completion of transfer. Determines whether an interrupt is generated by completing a transfer or by the occurrence of an error condition ; bit position masks mDCR3_LCH2: .equ %00000011 mDCR3_LCH1: .equ %00001100 mDCR3_LINKCC: .equ %00110000 mDCR3_D_REQ: .equ %10000000 mDCR3_DMOD: .equ %111100000000 mDCR3_SMOD: .equ %1111000000000000 mDCR3_START: .equ %10000000000000000 mDCR3_DSIZE: .equ %1100000000000000000 mDCR3_DINC: .equ %10000000000000000000 mDCR3_SSIZE: .equ %1100000000000000000000 mDCR3_SINC: .equ %10000000000000000000000 mDCR3_AA: .equ %10000000000000000000000000000 mDCR3_CS: .equ %100000000000000000000000000000 mDCR3_ERQ: .equ %1000000000000000000000000000000 mDCR3_EINT: .equ %10000000000000000000000000000000 ;*** INTC_IMRH - Interrupt Mask Register High; 0xFFFFFFC8 *** INTC_IMRH: .equ $FFFFFFC8 ;*** INTC_IMRH - Interrupt Mask Register High; 0xFFFFFFC8 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_IMRH_IMR32: .equ 0 ; Interrupt mask register 32 INTC_IMRH_IMR33: .equ 1 ; Interrupt mask register 33 INTC_IMRH_IMR34: .equ 2 ; Interrupt mask register 34 INTC_IMRH_IMR35: .equ 3 ; Interrupt mask register 35 INTC_IMRH_IMR36: .equ 4 ; Interrupt mask register 36 INTC_IMRH_IMR37: .equ 5 ; Interrupt mask register 37 INTC_IMRH_IMR38: .equ 6 ; Interrupt mask register 38 INTC_IMRH_IMR39: .equ 7 ; Interrupt mask register 39 INTC_IMRH_IMR40: .equ 8 ; Interrupt mask register 40 INTC_IMRH_IMR41: .equ 9 ; Interrupt mask register 41 INTC_IMRH_IMR42: .equ 10 ; Interrupt mask register 42 INTC_IMRH_IMR43: .equ 11 ; Interrupt mask register 43 ; bit position masks mINTC_IMRH_IMR32: .equ %00000001 mINTC_IMRH_IMR33: .equ %00000010 mINTC_IMRH_IMR34: .equ %00000100 mINTC_IMRH_IMR35: .equ %00001000 mINTC_IMRH_IMR36: .equ %00010000 mINTC_IMRH_IMR37: .equ %00100000 mINTC_IMRH_IMR38: .equ %01000000 mINTC_IMRH_IMR39: .equ %10000000 mINTC_IMRH_IMR40: .equ %100000000 mINTC_IMRH_IMR41: .equ %1000000000 mINTC_IMRH_IMR42: .equ %10000000000 mINTC_IMRH_IMR43: .equ %100000000000 ;*** INTC_IMRL - Interrupt Mask Register Low; 0xFFFFFFCC *** INTC_IMRL: .equ $FFFFFFCC ;*** INTC_IMRL - Interrupt Mask Register Low; 0xFFFFFFCC *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_IMRL_IMR0: .equ 0 ; Interrupt mask register 0 INTC_IMRL_IMR1: .equ 1 ; Interrupt mask register 1 INTC_IMRL_IMR2: .equ 2 ; Interrupt mask register 2 INTC_IMRL_IMR3: .equ 3 ; Interrupt mask register 3 INTC_IMRL_IMR4: .equ 4 ; Interrupt mask register 4 INTC_IMRL_IMR5: .equ 5 ; Interrupt mask register 5 INTC_IMRL_IMR6: .equ 6 ; Interrupt mask register 6 INTC_IMRL_IMR7: .equ 7 ; Interrupt mask register 7 INTC_IMRL_IMR8: .equ 8 ; Interrupt mask register 8 INTC_IMRL_IMR9: .equ 9 ; Interrupt mask register 9 INTC_IMRL_IMR10: .equ 10 ; Interrupt mask register 10 INTC_IMRL_IMR11: .equ 11 ; Interrupt mask register 11 INTC_IMRL_IMR12: .equ 12 ; Interrupt mask register 12 INTC_IMRL_IMR13: .equ 13 ; Interrupt mask register 13 INTC_IMRL_IMR14: .equ 14 ; Interrupt mask register 14 INTC_IMRL_IMR15: .equ 15 ; Interrupt mask register 15 INTC_IMRL_IMR16: .equ 16 ; Interrupt mask register 16 INTC_IMRL_IMR17: .equ 17 ; Interrupt mask register 17 INTC_IMRL_IMR18: .equ 18 ; Interrupt mask register 18 INTC_IMRL_IMR19: .equ 19 ; Interrupt mask register 19 INTC_IMRL_IMR20: .equ 20 ; Interrupt mask register 20 INTC_IMRL_IMR21: .equ 21 ; Interrupt mask register 21 INTC_IMRL_IMR22: .equ 22 ; Interrupt mask register 22 INTC_IMRL_IMR23: .equ 23 ; Interrupt mask register 23 INTC_IMRL_IMR24: .equ 24 ; Interrupt mask register 24 INTC_IMRL_IMR25: .equ 25 ; Interrupt mask register 25 INTC_IMRL_IMR26: .equ 26 ; Interrupt mask register 26 INTC_IMRL_IMR27: .equ 27 ; Interrupt mask register 27 INTC_IMRL_IMR28: .equ 28 ; Interrupt mask register 28 INTC_IMRL_IMR29: .equ 29 ; Interrupt mask register 29 INTC_IMRL_IMR30: .equ 30 ; Interrupt mask register 30 INTC_IMRL_IMR31: .equ 31 ; Interrupt mask register 31 ; bit position masks mINTC_IMRL_IMR0: .equ %00000001 mINTC_IMRL_IMR1: .equ %00000010 mINTC_IMRL_IMR2: .equ %00000100 mINTC_IMRL_IMR3: .equ %00001000 mINTC_IMRL_IMR4: .equ %00010000 mINTC_IMRL_IMR5: .equ %00100000 mINTC_IMRL_IMR6: .equ %01000000 mINTC_IMRL_IMR7: .equ %10000000 mINTC_IMRL_IMR8: .equ %100000000 mINTC_IMRL_IMR9: .equ %1000000000 mINTC_IMRL_IMR10: .equ %10000000000 mINTC_IMRL_IMR11: .equ %100000000000 mINTC_IMRL_IMR12: .equ %1000000000000 mINTC_IMRL_IMR13: .equ %10000000000000 mINTC_IMRL_IMR14: .equ %100000000000000 mINTC_IMRL_IMR15: .equ %1000000000000000 mINTC_IMRL_IMR16: .equ %10000000000000000 mINTC_IMRL_IMR17: .equ %100000000000000000 mINTC_IMRL_IMR18: .equ %1000000000000000000 mINTC_IMRL_IMR19: .equ %10000000000000000000 mINTC_IMRL_IMR20: .equ %100000000000000000000 mINTC_IMRL_IMR21: .equ %1000000000000000000000 mINTC_IMRL_IMR22: .equ %10000000000000000000000 mINTC_IMRL_IMR23: .equ %100000000000000000000000 mINTC_IMRL_IMR24: .equ %1000000000000000000000000 mINTC_IMRL_IMR25: .equ %10000000000000000000000000 mINTC_IMRL_IMR26: .equ %100000000000000000000000000 mINTC_IMRL_IMR27: .equ %1000000000000000000000000000 mINTC_IMRL_IMR28: .equ %10000000000000000000000000000 mINTC_IMRL_IMR29: .equ %100000000000000000000000000000 mINTC_IMRL_IMR30: .equ %1000000000000000000000000000000 mINTC_IMRL_IMR31: .equ %10000000000000000000000000000000 ;*** INTC_FRC - INTC Force Interrupt Register; 0xFFFFFFD0 *** INTC_FRC: .equ $FFFFFFD0 ;*** INTC_FRC - INTC Force Interrupt Register; 0xFFFFFFD0 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_FRC_LVL7: .equ 0 ; Force Level 7 interrupt INTC_FRC_LVL6: .equ 1 ; Force Level 6 interrupt INTC_FRC_LVL5: .equ 2 ; Force Level 5 interrupt INTC_FRC_LVL4: .equ 3 ; Force Level 4 interrupt INTC_FRC_LVL3: .equ 4 ; Force Level 3 interrupt INTC_FRC_LVL2: .equ 5 ; Force Level 2 interrupt INTC_FRC_LVL1: .equ 6 ; Force Level 1 interrupt ; bit position masks mINTC_FRC_LVL7: .equ %00000001 mINTC_FRC_LVL6: .equ %00000010 mINTC_FRC_LVL5: .equ %00000100 mINTC_FRC_LVL4: .equ %00001000 mINTC_FRC_LVL3: .equ %00010000 mINTC_FRC_LVL2: .equ %00100000 mINTC_FRC_LVL1: .equ %01000000 ;*** INTC_PL6P7 - INTC Programmable Level 6, Priority 7 Register; 0xFFFFFFD8 *** INTC_PL6P7: .equ $FFFFFFD8 ;*** INTC_PL6P7 - INTC Programmable Level 6, Priority 7 Register; 0xFFFFFFD8 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_PL6P7_REQN0: .equ 0 ; Request number, bit 0 INTC_PL6P7_REQN1: .equ 1 ; Request number, bit 1 INTC_PL6P7_REQN2: .equ 2 ; Request number, bit 2 INTC_PL6P7_REQN3: .equ 3 ; Request number, bit 3 INTC_PL6P7_REQN4: .equ 4 ; Request number, bit 4 INTC_PL6P7_REQN5: .equ 5 ; Request number, bit 5 ; bit position masks mINTC_PL6P7_REQN0: .equ %00000001 mINTC_PL6P7_REQN1: .equ %00000010 mINTC_PL6P7_REQN2: .equ %00000100 mINTC_PL6P7_REQN3: .equ %00001000 mINTC_PL6P7_REQN4: .equ %00010000 mINTC_PL6P7_REQN5: .equ %00100000 ;*** INTC_PL6P6 - INTC Programmable Level 6, Priority 6 Register; 0xFFFFFFD9 *** INTC_PL6P6: .equ $FFFFFFD9 ;*** INTC_PL6P6 - INTC Programmable Level 6, Priority 6 Register; 0xFFFFFFD9 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_PL6P6_REQN0: .equ 0 ; Request number, bit 0 INTC_PL6P6_REQN1: .equ 1 ; Request number, bit 1 INTC_PL6P6_REQN2: .equ 2 ; Request number, bit 2 INTC_PL6P6_REQN3: .equ 3 ; Request number, bit 3 INTC_PL6P6_REQN4: .equ 4 ; Request number, bit 4 INTC_PL6P6_REQN5: .equ 5 ; Request number, bit 5 ; bit position masks mINTC_PL6P6_REQN0: .equ %00000001 mINTC_PL6P6_REQN1: .equ %00000010 mINTC_PL6P6_REQN2: .equ %00000100 mINTC_PL6P6_REQN3: .equ %00001000 mINTC_PL6P6_REQN4: .equ %00010000 mINTC_PL6P6_REQN5: .equ %00100000 ;*** INTC_WCR - INTC Wake-up Control Register; 0xFFFFFFDB *** INTC_WCR: .equ $FFFFFFDB ;*** INTC_WCR - INTC Wake-up Control Register; 0xFFFFFFDB *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_WCR_MASK0: .equ 0 ; Interrupt mask level, bit 0 INTC_WCR_MASK1: .equ 1 ; Interrupt mask level, bit 1 INTC_WCR_MASK2: .equ 2 ; Interrupt mask level, bit 2 INTC_WCR_ENB: .equ 7 ; Enable ; bit position masks mINTC_WCR_MASK0: .equ %00000001 mINTC_WCR_MASK1: .equ %00000010 mINTC_WCR_MASK2: .equ %00000100 mINTC_WCR_ENB: .equ %10000000 ;*** INTC_SIMR - Set Interrupt Mask Register; 0xFFFFFFDC *** INTC_SIMR: .equ $FFFFFFDC ;*** INTC_SIMR - Set Interrupt Mask Register; 0xFFFFFFDC *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_SIMR_SIMR0: .equ 0 ; Set the corresponding bit in the INTC_IMR{H,L} register, masking the interrupt request, bit 0 INTC_SIMR_SIMR1: .equ 1 ; Set the corresponding bit in the INTC_IMR{H,L} register, masking the interrupt request, bit 1 INTC_SIMR_SIMR2: .equ 2 ; Set the corresponding bit in the INTC_IMR{H,L} register, masking the interrupt request, bit 2 INTC_SIMR_SIMR3: .equ 3 ; Set the corresponding bit in the INTC_IMR{H,L} register, masking the interrupt request, bit 3 INTC_SIMR_SIMR4: .equ 4 ; Set the corresponding bit in the INTC_IMR{H,L} register, masking the interrupt request, bit 4 INTC_SIMR_SIMR5: .equ 5 ; Set the corresponding bit in the INTC_IMR{H,L} register, masking the interrupt request, bit 5 INTC_SIMR_SALL: .equ 6 ; Set all bits in the INTC_IMR{H,L} register, masking all interrupt requests ; bit position masks mINTC_SIMR_SIMR0: .equ %00000001 mINTC_SIMR_SIMR1: .equ %00000010 mINTC_SIMR_SIMR2: .equ %00000100 mINTC_SIMR_SIMR3: .equ %00001000 mINTC_SIMR_SIMR4: .equ %00010000 mINTC_SIMR_SIMR5: .equ %00100000 mINTC_SIMR_SALL: .equ %01000000 ;*** INTC_CIMR - Clear Interrupt Mask Register; 0xFFFFFFDD *** INTC_CIMR: .equ $FFFFFFDD ;*** INTC_CIMR - Clear Interrupt Mask Register; 0xFFFFFFDD *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_CIMR_CIMR0: .equ 0 ; Clear the corresponding bit in the INTC_IMR{H,L} registers, enabling the interrupt request, bit 0 INTC_CIMR_CIMR1: .equ 1 ; Clear the corresponding bit in the INTC_IMR{H,L} registers, enabling the interrupt request, bit 1 INTC_CIMR_CIMR2: .equ 2 ; Clear the corresponding bit in the INTC_IMR{H,L} registers, enabling the interrupt request, bit 2 INTC_CIMR_CIMR3: .equ 3 ; Clear the corresponding bit in the INTC_IMR{H,L} registers, enabling the interrupt request, bit 3 INTC_CIMR_CIMR4: .equ 4 ; Clear the corresponding bit in the INTC_IMR{H,L} registers, enabling the interrupt request, bit 4 INTC_CIMR_CIMR5: .equ 5 ; Clear the corresponding bit in the INTC_IMR{H,L} registers, enabling the interrupt request, bit 5 INTC_CIMR_CALL: .equ 6 ; Clear all bits in the INTC_IMR{H,L} register, enabling all interrupt requests ; bit position masks mINTC_CIMR_CIMR0: .equ %00000001 mINTC_CIMR_CIMR1: .equ %00000010 mINTC_CIMR_CIMR2: .equ %00000100 mINTC_CIMR_CIMR3: .equ %00001000 mINTC_CIMR_CIMR4: .equ %00010000 mINTC_CIMR_CIMR5: .equ %00100000 mINTC_CIMR_CALL: .equ %01000000 ;*** INTC_SFRC - INTC Set Interrupt Force Register; 0xFFFFFFDE *** INTC_SFRC: .equ $FFFFFFDE ;*** INTC_SFRC - INTC Set Interrupt Force Register; 0xFFFFFFDE *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_SFRC_SET0: .equ 0 ; Sets corresponding bits in the INTC_FRC register, bit 0 INTC_SFRC_SET1: .equ 1 ; Sets corresponding bits in the INTC_FRC register, bit 1 INTC_SFRC_SET2: .equ 2 ; Sets corresponding bits in the INTC_FRC register, bit 2 INTC_SFRC_SET3: .equ 3 ; Sets corresponding bits in the INTC_FRC register, bit 3 INTC_SFRC_SET4: .equ 4 ; Sets corresponding bits in the INTC_FRC register, bit 4 INTC_SFRC_SET5: .equ 5 ; Sets corresponding bits in the INTC_FRC register, bit 5 ; bit position masks mINTC_SFRC_SET0: .equ %00000001 mINTC_SFRC_SET1: .equ %00000010 mINTC_SFRC_SET2: .equ %00000100 mINTC_SFRC_SET3: .equ %00001000 mINTC_SFRC_SET4: .equ %00010000 mINTC_SFRC_SET5: .equ %00100000 ;*** INTC_CFRC - INTC Clear Interrupt Force Register; 0xFFFFFFDF *** INTC_CFRC: .equ $FFFFFFDF ;*** INTC_CFRC - INTC Clear Interrupt Force Register; 0xFFFFFFDF *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_CFRC_CLR0: .equ 0 ; Clears corresponding bits in the INTC_FRC register, bit 0 INTC_CFRC_CLR1: .equ 1 ; Clears corresponding bits in the INTC_FRC register, bit 1 INTC_CFRC_CLR2: .equ 2 ; Clears corresponding bits in the INTC_FRC register, bit 2 INTC_CFRC_CLR3: .equ 3 ; Clears corresponding bits in the INTC_FRC register, bit 3 INTC_CFRC_CLR4: .equ 4 ; Clears corresponding bits in the INTC_FRC register, bit 4 INTC_CFRC_CLR5: .equ 5 ; Clears corresponding bits in the INTC_FRC register, bit 5 ; bit position masks mINTC_CFRC_CLR0: .equ %00000001 mINTC_CFRC_CLR1: .equ %00000010 mINTC_CFRC_CLR2: .equ %00000100 mINTC_CFRC_CLR3: .equ %00001000 mINTC_CFRC_CLR4: .equ %00010000 mINTC_CFRC_CLR5: .equ %00100000 ;*** INTC_SWIACK - INTC Software IACK Register; 0xFFFFFFE0 *** INTC_SWIACK: .equ $FFFFFFE0 ;*** INTC_SWIACK - INTC Software IACK Register; 0xFFFFFFE0 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_SWIACK_VECN0: .equ 0 ; Vector number, bit 0 INTC_SWIACK_VECN1: .equ 1 ; Vector number, bit 1 INTC_SWIACK_VECN2: .equ 2 ; Vector number, bit 2 INTC_SWIACK_VECN3: .equ 3 ; Vector number, bit 3 INTC_SWIACK_VECN4: .equ 4 ; Vector number, bit 4 INTC_SWIACK_VECN5: .equ 5 ; Vector number, bit 5 INTC_SWIACK_VECN6: .equ 6 ; Vector number, bit 6 ; bit position masks mINTC_SWIACK_VECN0: .equ %00000001 mINTC_SWIACK_VECN1: .equ %00000010 mINTC_SWIACK_VECN2: .equ %00000100 mINTC_SWIACK_VECN3: .equ %00001000 mINTC_SWIACK_VECN4: .equ %00010000 mINTC_SWIACK_VECN5: .equ %00100000 mINTC_SWIACK_VECN6: .equ %01000000 ;*** INTC_LVL1IACK - INTC Level 1 IACK Register; 0xFFFFFFE4 *** INTC_LVL1IACK: .equ $FFFFFFE4 ;*** INTC_LVL1IACK - INTC Level 1 IACK Register; 0xFFFFFFE4 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_LVL1IACK_VECN0: .equ 0 ; Vector number, bit 0 INTC_LVL1IACK_VECN1: .equ 1 ; Vector number, bit 1 INTC_LVL1IACK_VECN2: .equ 2 ; Vector number, bit 2 INTC_LVL1IACK_VECN3: .equ 3 ; Vector number, bit 3 INTC_LVL1IACK_VECN4: .equ 4 ; Vector number, bit 4 INTC_LVL1IACK_VECN5: .equ 5 ; Vector number, bit 5 INTC_LVL1IACK_VECN6: .equ 6 ; Vector number, bit 6 ; bit position masks mINTC_LVL1IACK_VECN0: .equ %00000001 mINTC_LVL1IACK_VECN1: .equ %00000010 mINTC_LVL1IACK_VECN2: .equ %00000100 mINTC_LVL1IACK_VECN3: .equ %00001000 mINTC_LVL1IACK_VECN4: .equ %00010000 mINTC_LVL1IACK_VECN5: .equ %00100000 mINTC_LVL1IACK_VECN6: .equ %01000000 ;*** INTC_LVL2IACK - INTC Level 2 IACK Register; 0xFFFFFFE8 *** INTC_LVL2IACK: .equ $FFFFFFE8 ;*** INTC_LVL2IACK - INTC Level 2 IACK Register; 0xFFFFFFE8 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_LVL2IACK_VECN0: .equ 0 ; Vector number, bit 0 INTC_LVL2IACK_VECN1: .equ 1 ; Vector number, bit 1 INTC_LVL2IACK_VECN2: .equ 2 ; Vector number, bit 2 INTC_LVL2IACK_VECN3: .equ 3 ; Vector number, bit 3 INTC_LVL2IACK_VECN4: .equ 4 ; Vector number, bit 4 INTC_LVL2IACK_VECN5: .equ 5 ; Vector number, bit 5 INTC_LVL2IACK_VECN6: .equ 6 ; Vector number, bit 6 ; bit position masks mINTC_LVL2IACK_VECN0: .equ %00000001 mINTC_LVL2IACK_VECN1: .equ %00000010 mINTC_LVL2IACK_VECN2: .equ %00000100 mINTC_LVL2IACK_VECN3: .equ %00001000 mINTC_LVL2IACK_VECN4: .equ %00010000 mINTC_LVL2IACK_VECN5: .equ %00100000 mINTC_LVL2IACK_VECN6: .equ %01000000 ;*** INTC_LVL3IACK - INTC Level 3 IACK Register; 0xFFFFFFEC *** INTC_LVL3IACK: .equ $FFFFFFEC ;*** INTC_LVL3IACK - INTC Level 3 IACK Register; 0xFFFFFFEC *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_LVL3IACK_VECN0: .equ 0 ; Vector number, bit 0 INTC_LVL3IACK_VECN1: .equ 1 ; Vector number, bit 1 INTC_LVL3IACK_VECN2: .equ 2 ; Vector number, bit 2 INTC_LVL3IACK_VECN3: .equ 3 ; Vector number, bit 3 INTC_LVL3IACK_VECN4: .equ 4 ; Vector number, bit 4 INTC_LVL3IACK_VECN5: .equ 5 ; Vector number, bit 5 INTC_LVL3IACK_VECN6: .equ 6 ; Vector number, bit 6 ; bit position masks mINTC_LVL3IACK_VECN0: .equ %00000001 mINTC_LVL3IACK_VECN1: .equ %00000010 mINTC_LVL3IACK_VECN2: .equ %00000100 mINTC_LVL3IACK_VECN3: .equ %00001000 mINTC_LVL3IACK_VECN4: .equ %00010000 mINTC_LVL3IACK_VECN5: .equ %00100000 mINTC_LVL3IACK_VECN6: .equ %01000000 ;*** INTC_LVL4IACK - INTC Level 4 IACK Register; 0xFFFFFFF0 *** INTC_LVL4IACK: .equ $FFFFFFF0 ;*** INTC_LVL4IACK - INTC Level 4 IACK Register; 0xFFFFFFF0 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_LVL4IACK_VECN0: .equ 0 ; Vector number, bit 0 INTC_LVL4IACK_VECN1: .equ 1 ; Vector number, bit 1 INTC_LVL4IACK_VECN2: .equ 2 ; Vector number, bit 2 INTC_LVL4IACK_VECN3: .equ 3 ; Vector number, bit 3 INTC_LVL4IACK_VECN4: .equ 4 ; Vector number, bit 4 INTC_LVL4IACK_VECN5: .equ 5 ; Vector number, bit 5 INTC_LVL4IACK_VECN6: .equ 6 ; Vector number, bit 6 ; bit position masks mINTC_LVL4IACK_VECN0: .equ %00000001 mINTC_LVL4IACK_VECN1: .equ %00000010 mINTC_LVL4IACK_VECN2: .equ %00000100 mINTC_LVL4IACK_VECN3: .equ %00001000 mINTC_LVL4IACK_VECN4: .equ %00010000 mINTC_LVL4IACK_VECN5: .equ %00100000 mINTC_LVL4IACK_VECN6: .equ %01000000 ;*** INTC_LVL5IACK - INTC Level 5 IACK Register; 0xFFFFFFF4 *** INTC_LVL5IACK: .equ $FFFFFFF4 ;*** INTC_LVL5IACK - INTC Level 5 IACK Register; 0xFFFFFFF4 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_LVL5IACK_VECN0: .equ 0 ; Vector number, bit 0 INTC_LVL5IACK_VECN1: .equ 1 ; Vector number, bit 1 INTC_LVL5IACK_VECN2: .equ 2 ; Vector number, bit 2 INTC_LVL5IACK_VECN3: .equ 3 ; Vector number, bit 3 INTC_LVL5IACK_VECN4: .equ 4 ; Vector number, bit 4 INTC_LVL5IACK_VECN5: .equ 5 ; Vector number, bit 5 INTC_LVL5IACK_VECN6: .equ 6 ; Vector number, bit 6 ; bit position masks mINTC_LVL5IACK_VECN0: .equ %00000001 mINTC_LVL5IACK_VECN1: .equ %00000010 mINTC_LVL5IACK_VECN2: .equ %00000100 mINTC_LVL5IACK_VECN3: .equ %00001000 mINTC_LVL5IACK_VECN4: .equ %00010000 mINTC_LVL5IACK_VECN5: .equ %00100000 mINTC_LVL5IACK_VECN6: .equ %01000000 ;*** INTC_LVL6IACK - INTC Level 6 IACK Register; 0xFFFFFFF8 *** INTC_LVL6IACK: .equ $FFFFFFF8 ;*** INTC_LVL6IACK - INTC Level 6 IACK Register; 0xFFFFFFF8 *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_LVL6IACK_VECN0: .equ 0 ; Vector number, bit 0 INTC_LVL6IACK_VECN1: .equ 1 ; Vector number, bit 1 INTC_LVL6IACK_VECN2: .equ 2 ; Vector number, bit 2 INTC_LVL6IACK_VECN3: .equ 3 ; Vector number, bit 3 INTC_LVL6IACK_VECN4: .equ 4 ; Vector number, bit 4 INTC_LVL6IACK_VECN5: .equ 5 ; Vector number, bit 5 INTC_LVL6IACK_VECN6: .equ 6 ; Vector number, bit 6 ; bit position masks mINTC_LVL6IACK_VECN0: .equ %00000001 mINTC_LVL6IACK_VECN1: .equ %00000010 mINTC_LVL6IACK_VECN2: .equ %00000100 mINTC_LVL6IACK_VECN3: .equ %00001000 mINTC_LVL6IACK_VECN4: .equ %00010000 mINTC_LVL6IACK_VECN5: .equ %00100000 mINTC_LVL6IACK_VECN6: .equ %01000000 ;*** INTC_LVL7IACK - INTC Level 7 IACK Register; 0xFFFFFFFC *** INTC_LVL7IACK: .equ $FFFFFFFC ;*** INTC_LVL7IACK - INTC Level 7 IACK Register; 0xFFFFFFFC *** ; bit numbers for usage in BCLR, BSET, BRCLR and BRSET INTC_LVL7IACK_VECN0: .equ 0 ; Vector number, bit 0 INTC_LVL7IACK_VECN1: .equ 1 ; Vector number, bit 1 INTC_LVL7IACK_VECN2: .equ 2 ; Vector number, bit 2 INTC_LVL7IACK_VECN3: .equ 3 ; Vector number, bit 3 INTC_LVL7IACK_VECN4: .equ 4 ; Vector number, bit 4 INTC_LVL7IACK_VECN5: .equ 5 ; Vector number, bit 5 INTC_LVL7IACK_VECN6: .equ 6 ; Vector number, bit 6 ; bit position masks mINTC_LVL7IACK_VECN0: .equ %00000001 mINTC_LVL7IACK_VECN1: .equ %00000010 mINTC_LVL7IACK_VECN2: .equ %00000100 mINTC_LVL7IACK_VECN3: .equ %00001000 mINTC_LVL7IACK_VECN4: .equ %00010000 mINTC_LVL7IACK_VECN5: .equ %00100000 mINTC_LVL7IACK_VECN6: .equ %01000000 ; Flash commands mBlank: .equ $05 mBurstProg: .equ $25 mByteProg: .equ $20 mMassErase: .equ $41 mPageErase: .equ $40 ;*********************************************** ;** D E P R E C I A T E D S Y M B O L S ** ;*********************************************** .IFNDEF __GENERATE_APPLICATION__ ; not supported for absolute assembler .XREF This_symb_has_been_depreciated .ENDIF ; EOF