L 1 "..\src\STM32Lib\stm32f10x_exti.c"
N/**
N ******************************************************************************
N * @file stm32f10x_exti.c
N * @author MCD Application Team
N * @version V3.0.0
N * @date 04/06/2009
N * @brief This file provides all the EXTI firmware functions.
N ******************************************************************************
N * @copy
N *
N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N *
N * © COPYRIGHT 2009 STMicroelectronics
N */
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f10x_exti.h"
L 1 "..\src\STM32Lib\stm32f10x_exti.h" 1
N/**
N ******************************************************************************
N * @file stm32f10x_exti.h
N * @author MCD Application Team
N * @version V3.0.0
N * @date 04/06/2009
N * @brief This file contains all the functions prototypes for the EXTI
N * firmware library.
N ******************************************************************************
N * @copy
N *
N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N *
N * © COPYRIGHT 2009 STMicroelectronics
N */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F10x_EXTI_H
N#define __STM32F10x_EXTI_H
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f10x.h"
L 1 "..\src\STM32Lib\stm32f10x.h" 1
N/**
N ******************************************************************************
N * @file stm32f10x.h
N * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
N * This file contains all the peripheral register's definitions, bits
N * definitions and memory mapping for STM32F10x High Density, Medium
N * Density and Low Density devices.
N * @author STMicroelectronics - MCD Application Team
N * @version V3.0.0
N * @date 04/06/2009
N ******************************************************************************
N *
N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N *
N * © COPYRIGHT 2009 STMicroelectronics
N ******************************************************************************
N */
N
N/** @addtogroup CMSIS
N * @{
N */
N
N/** @addtogroup stm32f10x
N * @{
N */
N
N#ifndef __STM32F10x_H
N#define __STM32F10x_H
N
N/** @addtogroup Library_configuration_section
N * @{
N */
N
N/* Uncomment the line below according to the target STM32 device used in your
N application
N */
N
N#if !defined (STM32F10X_LD) && !defined (STM32F10X_MD) && !defined (STM32F10X_HD)
X#if !0L && !0L && !1L
S/* #define STM32F10X_LD */ /*!< STM32 Low density devices */
S#define STM32F10X_MD /*!< STM32 Medium density devices */
S/*#define STM32F10X_HD*/ /*!< STM32 High density devices */
N#endif
N/* Tip: To avoid modifying this file each time you need to switch between these
N devices, you can define the device in your toolchain compiler preprocessor.
N
N - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
N where the Flash memory density ranges between 16 and 32 Kbytes.
N - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
N where the Flash memory density ranges between 64 and 128 Kbytes.
N - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
N the Flash memory density ranges between 256 and 512 Kbytes.
N */
N
N#if !defined USE_STDPERIPH_DRIVER
X#if !0L
N/**
N * @brief Comment the line below if you will not use the peripherals drivers.
N In this case, these drivers will not be included and the application code will
N be based on direct access to peripherals registers
N */
N#define USE_STDPERIPH_DRIVER
N#endif
N
N/**
N * @brief In the following line adjust the value of External High Speed oscillator (HSE)
N used in your application
N */
N#define HSE_Value ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
N/**
N * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
N Timeout value
N */
N#define HSEStartUp_TimeOut ((uint16_t)0x0500) /*!< Time out for HSE start up */
N
N#define HSI_Value ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
N
N
N/*!< [31:16] STM32F10x Standard Peripheral Library main version */
N#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03)
N/*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */
N#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x00)
N/*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */
N#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00)
N/*!< STM32F10x Standard Peripheral Library version number */
N#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\
N | (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\
N | __STM32F10X_STDPERIPH_VERSION_SUB2)
X#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16) | (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8) | __STM32F10X_STDPERIPH_VERSION_SUB2)
N
N/**
N * @}
N */
N
N/** @addtogroup Configuration_section_for_CMSIS
N * @{
N */
N
N/**
N * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
N */
N#define __MPU_PRESENT 0 /*!< STM32 does not provide a MPU present or not */
N#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
N#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
N
N/*!< Interrupt Number Definition */
Ntypedef enum IRQn
N{
N /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
N NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
N MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
N BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
N UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
N SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
N DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
N PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
N SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
N
N /****** STM32 specific Interrupt Numbers *********************************************************/
N WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
N PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
N TAMPER_IRQn = 2, /*!< Tamper Interrupt */
N RTC_IRQn = 3, /*!< RTC global Interrupt */
N FLASH_IRQn = 4, /*!< FLASH global Interrupt */
N RCC_IRQn = 5, /*!< RCC global Interrupt */
N EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
N EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
N EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
N EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
N EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
N DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
N DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
N DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
N DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
N DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
N DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
N DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
N ADC1_2_IRQn = 18, /*!< ADC1 et ADC2 global Interrupt */
N USB_HP_CAN1_TX_IRQn = 19, /*!< USB High Priority or CAN1 TX Interrupts */
N USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Low Priority or CAN1 RX0 Interrupts */
N CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
N CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
N EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
N TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
N TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
N TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
N TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
N TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
N TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
N#ifndef STM32F10X_LD
N TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
N#endif
N I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
N I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
N#ifndef STM32F10X_LD
N I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
N I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
N#endif
N SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
N SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
N USART1_IRQn = 37, /*!< USART1 global Interrupt */
N USART2_IRQn = 38, /*!< USART2 global Interrupt */
N#ifndef STM32F10X_LD
N USART3_IRQn = 39, /*!< USART3 global Interrupt */
N#endif
N EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
N RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
N USBWakeUp_IRQn = 42, /*!< USB WakeUp from suspend through EXTI Line Interrupt */
N#ifdef STM32F10X_HD
N TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
N TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
N TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
N TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
N ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
N FSMC_IRQn = 48, /*!< FSMC global Interrupt */
N SDIO_IRQn = 49, /*!< SDIO global Interrupt */
N TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
N SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
N UART4_IRQn = 52, /*!< UART4 global Interrupt */
N UART5_IRQn = 53, /*!< UART5 global Interrupt */
N TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
N TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
N DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
N DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
N DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
N DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
N#endif
N} IRQn_Type;
N
N/**
N * @}
N */
N
N#include "core_cm3.h"
L 1 "..\src\STM32Lib\core_cm3.h" 1
N/******************************************************************************
N * @file: core_cm3.h
N * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File
N * @version: V1.10
N * @date: 24. Feb. 2009
N *----------------------------------------------------------------------------
N *
N * Copyright (C) 2009 ARM Limited. All rights reserved.
N *
N * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
N * processor based microcontrollers. This file can be freely distributed
N * within development tools that are supporting such ARM based processors.
N *
N * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
N * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
N * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
N * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
N * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
N *
N ******************************************************************************/
N
N
N
N
N#ifndef __CM3_CORE_H__
N#define __CM3_CORE_H__
N
N
N#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
N#define __CM3_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
N#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
N
N#define __CORTEX_M (0x03) /*!< Cortex core */
N
N/**
N * Lint configuration \n
N * ----------------------- \n
N *
N * The following Lint messages will be suppressed and not shown: \n
N * \n
N * --- Error 10: --- \n
N * register uint32_t __regBasePri __asm("basepri"); \n
N * Error 10: Expecting ';' \n
N * \n
N * --- Error 530: --- \n
N * return(__regBasePri); \n
N * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
N * \n
N * --- Error 550: --- \n
N * __regBasePri = (basePri & 0x1ff); \n
N * } \n
N * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
N * \n
N * --- Error 754: --- \n
N * uint32_t RESERVED0[24]; \n
N * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced \n
N * \n
N * --- Error 750: --- \n
N * #define __CM3_CORE_H__ \n
N * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
N * \n
N * --- Error 528: --- \n
N * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
N * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
N * \n
N * --- Error 751: --- \n
N * } InterruptType_Type; \n
N * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
N * \n
N * \n
N * Note: To re-enable a Message, insert a space before 'lint' * \n
N *
N */
N
N/*lint -save */
N/*lint -e10 */
N/*lint -e530 */
N/*lint -e550 */
N/*lint -e754 */
N/*lint -e750 */
N/*lint -e528 */
N/*lint -e751 */
N
N
N#include /* Include standard types */
L 1 "d:\Keil\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdint.h" 1
N/* Copyright (C) ARM Ltd., 1999,2014 */
N/* All rights reserved */
N
N/*
N * RCS $Revision$
N * Checkin $Date$
N * Revising $Author: agrant $
N */
N
N#ifndef __stdint_h
N#define __stdint_h
N#define __ARMCLIB_VERSION 5060044
N
N #ifdef __INT64_TYPE__
S /* armclang predefines '__INT64_TYPE__' and '__INT64_C_SUFFIX__' */
S #define __INT64 __INT64_TYPE__
N #else
N /* armcc has builtin '__int64' which can be used in --strict mode */
N #define __INT64 __int64
N #define __INT64_C_SUFFIX__ ll
N #endif
N #define __PASTE2(x, y) x ## y
N #define __PASTE(x, y) __PASTE2(x, y)
N #define __INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__))
N #define __UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__))
N #if defined(__clang__) || (defined(__ARMCC_VERSION) && !defined(__STRICT_ANSI__))
X #if 0L || (1L && !0L)
N /* armclang and non-strict armcc allow 'long long' in system headers */
N #define __LONGLONG long long
N #else
S /* strict armcc has '__int64' */
S #define __LONGLONG __int64
N #endif
N
N #ifndef __STDINT_DECLS
N #define __STDINT_DECLS
N
N #undef __CLIBNS
N
N #ifdef __cplusplus
S namespace std {
S #define __CLIBNS std::
S extern "C" {
N #else
N #define __CLIBNS
N #endif /* __cplusplus */
N
N
N/*
N * 'signed' is redundant below, except for 'signed char' and if
N * the typedef is used to declare a bitfield.
N */
N
N /* 7.18.1.1 */
N
N /* exact-width signed integer types */
Ntypedef signed char int8_t;
Ntypedef signed short int int16_t;
Ntypedef signed int int32_t;
Ntypedef signed __INT64 int64_t;
Xtypedef signed __int64 int64_t;
N
N /* exact-width unsigned integer types */
Ntypedef unsigned char uint8_t;
Ntypedef unsigned short int uint16_t;
Ntypedef unsigned int uint32_t;
Ntypedef unsigned __INT64 uint64_t;
Xtypedef unsigned __int64 uint64_t;
N
N /* 7.18.1.2 */
N
N /* smallest type of at least n bits */
N /* minimum-width signed integer types */
Ntypedef signed char int_least8_t;
Ntypedef signed short int int_least16_t;
Ntypedef signed int int_least32_t;
Ntypedef signed __INT64 int_least64_t;
Xtypedef signed __int64 int_least64_t;
N
N /* minimum-width unsigned integer types */
Ntypedef unsigned char uint_least8_t;
Ntypedef unsigned short int uint_least16_t;
Ntypedef unsigned int uint_least32_t;
Ntypedef unsigned __INT64 uint_least64_t;
Xtypedef unsigned __int64 uint_least64_t;
N
N /* 7.18.1.3 */
N
N /* fastest minimum-width signed integer types */
Ntypedef signed int int_fast8_t;
Ntypedef signed int int_fast16_t;
Ntypedef signed int int_fast32_t;
Ntypedef signed __INT64 int_fast64_t;
Xtypedef signed __int64 int_fast64_t;
N
N /* fastest minimum-width unsigned integer types */
Ntypedef unsigned int uint_fast8_t;
Ntypedef unsigned int uint_fast16_t;
Ntypedef unsigned int uint_fast32_t;
Ntypedef unsigned __INT64 uint_fast64_t;
Xtypedef unsigned __int64 uint_fast64_t;
N
N /* 7.18.1.4 integer types capable of holding object pointers */
N#if __sizeof_ptr == 8
X#if 4 == 8
Stypedef signed __INT64 intptr_t;
Stypedef unsigned __INT64 uintptr_t;
N#else
Ntypedef signed int intptr_t;
Ntypedef unsigned int uintptr_t;
N#endif
N
N /* 7.18.1.5 greatest-width integer types */
Ntypedef signed __LONGLONG intmax_t;
Xtypedef signed long long intmax_t;
Ntypedef unsigned __LONGLONG uintmax_t;
Xtypedef unsigned long long uintmax_t;
N
N
N#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS)
X#if !0L || 0L
N
N /* 7.18.2.1 */
N
N /* minimum values of exact-width signed integer types */
N#define INT8_MIN -128
N#define INT16_MIN -32768
N#define INT32_MIN (~0x7fffffff) /* -2147483648 is unsigned */
N#define INT64_MIN __INT64_C(~0x7fffffffffffffff) /* -9223372036854775808 is unsigned */
N
N /* maximum values of exact-width signed integer types */
N#define INT8_MAX 127
N#define INT16_MAX 32767
N#define INT32_MAX 2147483647
N#define INT64_MAX __INT64_C(9223372036854775807)
N
N /* maximum values of exact-width unsigned integer types */
N#define UINT8_MAX 255
N#define UINT16_MAX 65535
N#define UINT32_MAX 4294967295u
N#define UINT64_MAX __UINT64_C(18446744073709551615)
N
N /* 7.18.2.2 */
N
N /* minimum values of minimum-width signed integer types */
N#define INT_LEAST8_MIN -128
N#define INT_LEAST16_MIN -32768
N#define INT_LEAST32_MIN (~0x7fffffff)
N#define INT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff)
N
N /* maximum values of minimum-width signed integer types */
N#define INT_LEAST8_MAX 127
N#define INT_LEAST16_MAX 32767
N#define INT_LEAST32_MAX 2147483647
N#define INT_LEAST64_MAX __INT64_C(9223372036854775807)
N
N /* maximum values of minimum-width unsigned integer types */
N#define UINT_LEAST8_MAX 255
N#define UINT_LEAST16_MAX 65535
N#define UINT_LEAST32_MAX 4294967295u
N#define UINT_LEAST64_MAX __UINT64_C(18446744073709551615)
N
N /* 7.18.2.3 */
N
N /* minimum values of fastest minimum-width signed integer types */
N#define INT_FAST8_MIN (~0x7fffffff)
N#define INT_FAST16_MIN (~0x7fffffff)
N#define INT_FAST32_MIN (~0x7fffffff)
N#define INT_FAST64_MIN __INT64_C(~0x7fffffffffffffff)
N
N /* maximum values of fastest minimum-width signed integer types */
N#define INT_FAST8_MAX 2147483647
N#define INT_FAST16_MAX 2147483647
N#define INT_FAST32_MAX 2147483647
N#define INT_FAST64_MAX __INT64_C(9223372036854775807)
N
N /* maximum values of fastest minimum-width unsigned integer types */
N#define UINT_FAST8_MAX 4294967295u
N#define UINT_FAST16_MAX 4294967295u
N#define UINT_FAST32_MAX 4294967295u
N#define UINT_FAST64_MAX __UINT64_C(18446744073709551615)
N
N /* 7.18.2.4 */
N
N /* minimum value of pointer-holding signed integer type */
N#if __sizeof_ptr == 8
X#if 4 == 8
S#define INTPTR_MIN INT64_MIN
N#else
N#define INTPTR_MIN INT32_MIN
N#endif
N
N /* maximum value of pointer-holding signed integer type */
N#if __sizeof_ptr == 8
X#if 4 == 8
S#define INTPTR_MAX INT64_MAX
N#else
N#define INTPTR_MAX INT32_MAX
N#endif
N
N /* maximum value of pointer-holding unsigned integer type */
N#if __sizeof_ptr == 8
X#if 4 == 8
S#define UINTPTR_MAX UINT64_MAX
N#else
N#define UINTPTR_MAX UINT32_MAX
N#endif
N
N /* 7.18.2.5 */
N
N /* minimum value of greatest-width signed integer type */
N#define INTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll)
N
N /* maximum value of greatest-width signed integer type */
N#define INTMAX_MAX __ESCAPE__(9223372036854775807ll)
N
N /* maximum value of greatest-width unsigned integer type */
N#define UINTMAX_MAX __ESCAPE__(18446744073709551615ull)
N
N /* 7.18.3 */
N
N /* limits of ptrdiff_t */
N#if __sizeof_ptr == 8
X#if 4 == 8
S#define PTRDIFF_MIN INT64_MIN
S#define PTRDIFF_MAX INT64_MAX
N#else
N#define PTRDIFF_MIN INT32_MIN
N#define PTRDIFF_MAX INT32_MAX
N#endif
N
N /* limits of sig_atomic_t */
N#define SIG_ATOMIC_MIN (~0x7fffffff)
N#define SIG_ATOMIC_MAX 2147483647
N
N /* limit of size_t */
N#if __sizeof_ptr == 8
X#if 4 == 8
S#define SIZE_MAX UINT64_MAX
N#else
N#define SIZE_MAX UINT32_MAX
N#endif
N
N /* limits of wchar_t */
N /* NB we have to undef and redef because they're defined in both
N * stdint.h and wchar.h */
N#undef WCHAR_MIN
N#undef WCHAR_MAX
N
N#if defined(__WCHAR32) || (defined(__ARM_SIZEOF_WCHAR_T) && __ARM_SIZEOF_WCHAR_T == 4)
X#if 0L || (0L && __ARM_SIZEOF_WCHAR_T == 4)
S #define WCHAR_MIN 0
S #define WCHAR_MAX 0xffffffffU
N#else
N #define WCHAR_MIN 0
N #define WCHAR_MAX 65535
N#endif
N
N /* limits of wint_t */
N#define WINT_MIN (~0x7fffffff)
N#define WINT_MAX 2147483647
N
N#endif /* __STDC_LIMIT_MACROS */
N
N#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS)
X#if !0L || 0L
N
N /* 7.18.4.1 macros for minimum-width integer constants */
N#define INT8_C(x) (x)
N#define INT16_C(x) (x)
N#define INT32_C(x) (x)
N#define INT64_C(x) __INT64_C(x)
N
N#define UINT8_C(x) (x ## u)
N#define UINT16_C(x) (x ## u)
N#define UINT32_C(x) (x ## u)
N#define UINT64_C(x) __UINT64_C(x)
N
N /* 7.18.4.2 macros for greatest-width integer constants */
N#define INTMAX_C(x) __ESCAPE__(x ## ll)
N#define UINTMAX_C(x) __ESCAPE__(x ## ull)
N
N#endif /* __STDC_CONSTANT_MACROS */
N
N #ifdef __cplusplus
S } /* extern "C" */
S } /* namespace std */
N #endif /* __cplusplus */
N #endif /* __STDINT_DECLS */
N
N #ifdef __cplusplus
S #ifndef __STDINT_NO_EXPORTS
S using ::std::int8_t;
S using ::std::int16_t;
S using ::std::int32_t;
S using ::std::int64_t;
S using ::std::uint8_t;
S using ::std::uint16_t;
S using ::std::uint32_t;
S using ::std::uint64_t;
S using ::std::int_least8_t;
S using ::std::int_least16_t;
S using ::std::int_least32_t;
S using ::std::int_least64_t;
S using ::std::uint_least8_t;
S using ::std::uint_least16_t;
S using ::std::uint_least32_t;
S using ::std::uint_least64_t;
S using ::std::int_fast8_t;
S using ::std::int_fast16_t;
S using ::std::int_fast32_t;
S using ::std::int_fast64_t;
S using ::std::uint_fast8_t;
S using ::std::uint_fast16_t;
S using ::std::uint_fast32_t;
S using ::std::uint_fast64_t;
S using ::std::intptr_t;
S using ::std::uintptr_t;
S using ::std::intmax_t;
S using ::std::uintmax_t;
S #endif
N #endif /* __cplusplus */
N
N#undef __INT64
N#undef __LONGLONG
N
N#endif /* __stdint_h */
N
N/* end of stdint.h */
L 86 "..\src\STM32Lib\core_cm3.h" 2
N
N#if defined (__ICCARM__)
X#if 0L
S#include /* IAR Intrinsics */
N#endif
N
N
N#ifndef __NVIC_PRIO_BITS
S#define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
N#endif
N
N
N
N
N/**
N * IO definitions
N *
N * define access restrictions to peripheral registers
N */
N
N#define __I volatile const /*!< defines 'read only' permissions */
N#define __O volatile /*!< defines 'write only' permissions */
N#define __IO volatile /*!< defines 'read / write' permissions */
N
N
N
N/*******************************************************************************
N * Register Abstraction
N ******************************************************************************/
N
N
N/* System Reset */
N#define NVIC_VECTRESET 0 /*!< Vector Reset Bit */
N#define NVIC_SYSRESETREQ 2 /*!< System Reset Request */
N#define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */
N#define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */
N
N/* Core Debug */
N#define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */
N#define ITM_TCR_ITMENA 1 /*!< ITM enable */
N
N
N
N
N/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */
Ntypedef struct
N{
N __IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */
X volatile uint32_t ISER[8];
N uint32_t RESERVED0[24];
N __IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */
X volatile uint32_t ICER[8];
N uint32_t RSERVED1[24];
N __IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */
X volatile uint32_t ISPR[8];
N uint32_t RESERVED2[24];
N __IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */
X volatile uint32_t ICPR[8];
N uint32_t RESERVED3[24];
N __IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */
X volatile uint32_t IABR[8];
N uint32_t RESERVED4[56];
N __IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */
X volatile uint8_t IP[240];
N uint32_t RESERVED5[644];
N __O uint32_t STIR; /*!< Software Trigger Interrupt Register */
X volatile uint32_t STIR;
N} NVIC_Type;
N
N
N/* memory mapping struct for System Control Block */
Ntypedef struct
N{
N __I uint32_t CPUID; /*!< CPU ID Base Register */
X volatile const uint32_t CPUID;
N __IO uint32_t ICSR; /*!< Interrupt Control State Register */
X volatile uint32_t ICSR;
N __IO uint32_t VTOR; /*!< Vector Table Offset Register */
X volatile uint32_t VTOR;
N __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */
X volatile uint32_t AIRCR;
N __IO uint32_t SCR; /*!< System Control Register */
X volatile uint32_t SCR;
N __IO uint32_t CCR; /*!< Configuration Control Register */
X volatile uint32_t CCR;
N __IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */
X volatile uint8_t SHP[12];
N __IO uint32_t SHCSR; /*!< System Handler Control and State Register */
X volatile uint32_t SHCSR;
N __IO uint32_t CFSR; /*!< Configurable Fault Status Register */
X volatile uint32_t CFSR;
N __IO uint32_t HFSR; /*!< Hard Fault Status Register */
X volatile uint32_t HFSR;
N __IO uint32_t DFSR; /*!< Debug Fault Status Register */
X volatile uint32_t DFSR;
N __IO uint32_t MMFAR; /*!< Mem Manage Address Register */
X volatile uint32_t MMFAR;
N __IO uint32_t BFAR; /*!< Bus Fault Address Register */
X volatile uint32_t BFAR;
N __IO uint32_t AFSR; /*!< Auxiliary Fault Status Register */
X volatile uint32_t AFSR;
N __I uint32_t PFR[2]; /*!< Processor Feature Register */
X volatile const uint32_t PFR[2];
N __I uint32_t DFR; /*!< Debug Feature Register */
X volatile const uint32_t DFR;
N __I uint32_t ADR; /*!< Auxiliary Feature Register */
X volatile const uint32_t ADR;
N __I uint32_t MMFR[4]; /*!< Memory Model Feature Register */
X volatile const uint32_t MMFR[4];
N __I uint32_t ISAR[5]; /*!< ISA Feature Register */
X volatile const uint32_t ISAR[5];
N} SCB_Type;
N
N
N/* memory mapping struct for SysTick */
Ntypedef struct
N{
N __IO uint32_t CTRL; /*!< SysTick Control and Status Register */
X volatile uint32_t CTRL;
N __IO uint32_t LOAD; /*!< SysTick Reload Value Register */
X volatile uint32_t LOAD;
N __IO uint32_t VAL; /*!< SysTick Current Value Register */
X volatile uint32_t VAL;
N __I uint32_t CALIB; /*!< SysTick Calibration Register */
X volatile const uint32_t CALIB;
N} SysTick_Type;
N
N
N/* memory mapping structur for ITM */
Ntypedef struct
N{
N __O union
X volatile union
N {
N __O uint8_t u8; /*!< ITM Stimulus Port 8-bit */
X volatile uint8_t u8;
N __O uint16_t u16; /*!< ITM Stimulus Port 16-bit */
X volatile uint16_t u16;
N __O uint32_t u32; /*!< ITM Stimulus Port 32-bit */
X volatile uint32_t u32;
N } PORT [32]; /*!< ITM Stimulus Port Registers */
N uint32_t RESERVED0[864];
N __IO uint32_t TER; /*!< ITM Trace Enable Register */
X volatile uint32_t TER;
N uint32_t RESERVED1[15];
N __IO uint32_t TPR; /*!< ITM Trace Privilege Register */
X volatile uint32_t TPR;
N uint32_t RESERVED2[15];
N __IO uint32_t TCR; /*!< ITM Trace Control Register */
X volatile uint32_t TCR;
N uint32_t RESERVED3[29];
N __IO uint32_t IWR; /*!< ITM Integration Write Register */
X volatile uint32_t IWR;
N __IO uint32_t IRR; /*!< ITM Integration Read Register */
X volatile uint32_t IRR;
N __IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */
X volatile uint32_t IMCR;
N uint32_t RESERVED4[43];
N __IO uint32_t LAR; /*!< ITM Lock Access Register */
X volatile uint32_t LAR;
N __IO uint32_t LSR; /*!< ITM Lock Status Register */
X volatile uint32_t LSR;
N uint32_t RESERVED5[6];
N __I uint32_t PID4; /*!< ITM Product ID Registers */
X volatile const uint32_t PID4;
N __I uint32_t PID5;
X volatile const uint32_t PID5;
N __I uint32_t PID6;
X volatile const uint32_t PID6;
N __I uint32_t PID7;
X volatile const uint32_t PID7;
N __I uint32_t PID0;
X volatile const uint32_t PID0;
N __I uint32_t PID1;
X volatile const uint32_t PID1;
N __I uint32_t PID2;
X volatile const uint32_t PID2;
N __I uint32_t PID3;
X volatile const uint32_t PID3;
N __I uint32_t CID0;
X volatile const uint32_t CID0;
N __I uint32_t CID1;
X volatile const uint32_t CID1;
N __I uint32_t CID2;
X volatile const uint32_t CID2;
N __I uint32_t CID3;
X volatile const uint32_t CID3;
N} ITM_Type;
N
N
N/* memory mapped struct for Interrupt Type */
Ntypedef struct
N{
N uint32_t RESERVED0;
N __I uint32_t ICTR; /*!< Interrupt Control Type Register */
X volatile const uint32_t ICTR;
N#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
X#if ((0L) && (__CM3_REV >= 0x200))
S __IO uint32_t ACTLR; /*!< Auxiliary Control Register */
N#else
N uint32_t RESERVED1;
N#endif
N} InterruptType_Type;
N
N
N/* Memory Protection Unit */
N#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
X#if 1L && (0 == 1)
Stypedef struct
S{
S __I uint32_t TYPE; /*!< MPU Type Register */
S __IO uint32_t CTRL; /*!< MPU Control Register */
S __IO uint32_t RNR; /*!< MPU Region RNRber Register */
S __IO uint32_t RBAR; /*!< MPU Region Base Address Register */
S __IO uint32_t RASR; /*!< MPU Region Attribute and Size Register */
S __IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register */
S __IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register */
S __IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register */
S __IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register */
S __IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register */
S __IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register */
S} MPU_Type;
N#endif
N
N
N/* Core Debug Register */
Ntypedef struct
N{
N __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */
X volatile uint32_t DHCSR;
N __O uint32_t DCRSR; /*!< Debug Core Register Selector Register */
X volatile uint32_t DCRSR;
N __IO uint32_t DCRDR; /*!< Debug Core Register Data Register */
X volatile uint32_t DCRDR;
N __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */
X volatile uint32_t DEMCR;
N} CoreDebug_Type;
N
N
N/* Memory mapping of Cortex-M3 Hardware */
N#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
N#define ITM_BASE (0xE0000000) /*!< ITM Base Address */
N#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
N#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
N#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
N#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
N
N#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
N#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
N#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
N#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
N#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
N#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
N
N#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
X#if 1L && (0 == 1)
S#define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */
S#define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
N#endif
N
N
N
N/*******************************************************************************
N * Hardware Abstraction Layer
N ******************************************************************************/
N
N
N#if defined ( __CC_ARM )
X#if 1L
N#define __ASM __asm /*!< asm keyword for ARM Compiler */
N#define __INLINE __inline /*!< inline keyword for ARM Compiler */
N
N#elif defined ( __ICCARM__ )
S#define __ASM __asm /*!< asm keyword for IAR Compiler */
S#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
S#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */
S
S#elif defined ( __GNUC__ )
S#define __ASM asm /*!< asm keyword for GNU Compiler */
S#define __INLINE inline /*!< inline keyword for GNU Compiler */
S
N#endif
N
N
N/* ################### Compiler specific Intrinsics ########################### */
N
N#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
X#if 1L
N/* ARM armcc specific functions */
N
N#define __enable_fault_irq __enable_fiq
N#define __disable_fault_irq __disable_fiq
N
N#define __NOP __nop
N#define __WFI __wfi
N#define __WFE __wfe
N#define __SEV __sev
N#define __ISB() __isb(0)
N#define __DSB() __dsb(0)
N#define __DMB() __dmb(0)
N#define __REV __rev
N#define __RBIT __rbit
N#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
N#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
N#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
N#define __STREXB(value, ptr) __strex(value, ptr)
N#define __STREXH(value, ptr) __strex(value, ptr)
N#define __STREXW(value, ptr) __strex(value, ptr)
N
N
N/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
N/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
N/* intrinsic void __enable_irq(); */
N/* intrinsic void __disable_irq(); */
N
N
N/**
N * @brief Return the Process Stack Pointer
N *
N * @param none
N * @return uint32_t ProcessStackPointer
N *
N * Return the actual process stack pointer
N */
Nextern uint32_t __get_PSP(void);
N
N/**
N * @brief Set the Process Stack Pointer
N *
N * @param uint32_t Process Stack Pointer
N * @return none
N *
N * Assign the value ProcessStackPointer to the MSP
N * (process stack pointer) Cortex processor register
N */
Nextern void __set_PSP(uint32_t topOfProcStack);
N
N/**
N * @brief Return the Main Stack Pointer
N *
N * @param none
N * @return uint32_t Main Stack Pointer
N *
N * Return the current value of the MSP (main stack pointer)
N * Cortex processor register
N */
Nextern uint32_t __get_MSP(void);
N
N/**
N * @brief Set the Main Stack Pointer
N *
N * @param uint32_t Main Stack Pointer
N * @return none
N *
N * Assign the value mainStackPointer to the MSP
N * (main stack pointer) Cortex processor register
N */
Nextern void __set_MSP(uint32_t topOfMainStack);
N
N/**
N * @brief Reverse byte order in unsigned short value
N *
N * @param uint16_t value to reverse
N * @return uint32_t reversed value
N *
N * Reverse byte order in unsigned short value
N */
Nextern uint32_t __REV16(uint16_t value);
N
N/*
N * @brief Reverse byte order in signed short value with sign extension to integer
N *
N * @param int16_t value to reverse
N * @return int32_t reversed value
N *
N * Reverse byte order in signed short value with sign extension to integer
N */
Nextern int32_t __REVSH(int16_t value);
N
N
N#if (__ARMCC_VERSION < 400000)
X#if (5060960 < 400000)
S
S/**
S * @brief Remove the exclusive lock created by ldrex
S *
S * @param none
S * @return none
S *
S * Removes the exclusive lock which is created by ldrex.
S */
Sextern void __CLREX(void);
S
S/**
S * @brief Return the Base Priority value
S *
S * @param none
S * @return uint32_t BasePriority
S *
S * Return the content of the base priority register
S */
Sextern uint32_t __get_BASEPRI(void);
S
S/**
S * @brief Set the Base Priority value
S *
S * @param uint32_t BasePriority
S * @return none
S *
S * Set the base priority register
S */
Sextern void __set_BASEPRI(uint32_t basePri);
S
S/**
S * @brief Return the Priority Mask value
S *
S * @param none
S * @return uint32_t PriMask
S *
S * Return the state of the priority mask bit from the priority mask
S * register
S */
Sextern uint32_t __get_PRIMASK(void);
S
S/**
S * @brief Set the Priority Mask value
S *
S * @param uint32_t PriMask
S * @return none
S *
S * Set the priority mask bit in the priority mask register
S */
Sextern void __set_PRIMASK(uint32_t priMask);
S
S/**
S * @brief Return the Fault Mask value
S *
S * @param none
S * @return uint32_t FaultMask
S *
S * Return the content of the fault mask register
S */
Sextern uint32_t __get_FAULTMASK(void);
S
S/**
S * @brief Set the Fault Mask value
S *
S * @param uint32_t faultMask value
S * @return none
S *
S * Set the fault mask register
S */
Sextern void __set_FAULTMASK(uint32_t faultMask);
S
S/**
S * @brief Return the Control Register value
S *
S * @param none
S * @return uint32_t Control value
S *
S * Return the content of the control register
S */
Sextern uint32_t __get_CONTROL(void);
S
S/**
S * @brief Set the Control Register value
S *
S * @param uint32_t Control value
S * @return none
S *
S * Set the control register
S */
Sextern void __set_CONTROL(uint32_t control);
S
N#else /* (__ARMCC_VERSION >= 400000) */
N
N
N/**
N * @brief Remove the exclusive lock created by ldrex
N *
N * @param none
N * @return none
N *
N * Removes the exclusive lock which is created by ldrex.
N */
N#define __CLREX __clrex
N
N/**
N * @brief Return the Base Priority value
N *
N * @param none
N * @return uint32_t BasePriority
N *
N * Return the content of the base priority register
N */
Nstatic __INLINE uint32_t __get_BASEPRI(void)
Xstatic __inline uint32_t __get_BASEPRI(void)
N{
N register uint32_t __regBasePri __ASM("basepri");
X register uint32_t __regBasePri __asm("basepri");
N return(__regBasePri);
N}
N
N/**
N * @brief Set the Base Priority value
N *
N * @param uint32_t BasePriority
N * @return none
N *
N * Set the base priority register
N */
Nstatic __INLINE void __set_BASEPRI(uint32_t basePri)
Xstatic __inline void __set_BASEPRI(uint32_t basePri)
N{
N register uint32_t __regBasePri __ASM("basepri");
X register uint32_t __regBasePri __asm("basepri");
N __regBasePri = (basePri & 0x1ff);
N}
N
N/**
N * @brief Return the Priority Mask value
N *
N * @param none
N * @return uint32_t PriMask
N *
N * Return the state of the priority mask bit from the priority mask
N * register
N */
Nstatic __INLINE uint32_t __get_PRIMASK(void)
Xstatic __inline uint32_t __get_PRIMASK(void)
N{
N register uint32_t __regPriMask __ASM("primask");
X register uint32_t __regPriMask __asm("primask");
N return(__regPriMask);
N}
N
N/**
N * @brief Set the Priority Mask value
N *
N * @param uint32_t PriMask
N * @return none
N *
N * Set the priority mask bit in the priority mask register
N */
Nstatic __INLINE void __set_PRIMASK(uint32_t priMask)
Xstatic __inline void __set_PRIMASK(uint32_t priMask)
N{
N register uint32_t __regPriMask __ASM("primask");
X register uint32_t __regPriMask __asm("primask");
N __regPriMask = (priMask);
N}
N
N/**
N * @brief Return the Fault Mask value
N *
N * @param none
N * @return uint32_t FaultMask
N *
N * Return the content of the fault mask register
N */
Nstatic __INLINE uint32_t __get_FAULTMASK(void)
Xstatic __inline uint32_t __get_FAULTMASK(void)
N{
N register uint32_t __regFaultMask __ASM("faultmask");
X register uint32_t __regFaultMask __asm("faultmask");
N return(__regFaultMask);
N}
N
N/**
N * @brief Set the Fault Mask value
N *
N * @param uint32_t faultMask value
N * @return none
N *
N * Set the fault mask register
N */
Nstatic __INLINE void __set_FAULTMASK(uint32_t faultMask)
Xstatic __inline void __set_FAULTMASK(uint32_t faultMask)
N{
N register uint32_t __regFaultMask __ASM("faultmask");
X register uint32_t __regFaultMask __asm("faultmask");
N __regFaultMask = (faultMask & 1);
N}
N
N/**
N * @brief Return the Control Register value
N *
N * @param none
N * @return uint32_t Control value
N *
N * Return the content of the control register
N */
Nstatic __INLINE uint32_t __get_CONTROL(void)
Xstatic __inline uint32_t __get_CONTROL(void)
N{
N register uint32_t __regControl __ASM("control");
X register uint32_t __regControl __asm("control");
N return(__regControl);
N}
N
N/**
N * @brief Set the Control Register value
N *
N * @param uint32_t Control value
N * @return none
N *
N * Set the control register
N */
Nstatic __INLINE void __set_CONTROL(uint32_t control)
Xstatic __inline void __set_CONTROL(uint32_t control)
N{
N register uint32_t __regControl __ASM("control");
X register uint32_t __regControl __asm("control");
N __regControl = control;
N}
N
N#endif /* __ARMCC_VERSION */
N
N
N
N#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
S/* IAR iccarm specific functions */
S
S#define __enable_irq __enable_interrupt /*!< global Interrupt enable */
S#define __disable_irq __disable_interrupt /*!< global Interrupt disable */
S
Sstatic __INLINE void __enable_fault_irq()
S{
S __ASM ("cpsie f");
S}
Sstatic __INLINE void __disable_fault_irq()
S{
S __ASM ("cpsid f");
S}
S
Sstatic __INLINE void __WFI()
S{
S __ASM ("wfi");
S}
Sstatic __INLINE void __WFE()
S{
S __ASM ("wfe");
S}
Sstatic __INLINE void __SEV()
S{
S __ASM ("sev");
S}
Sstatic __INLINE void __CLREX()
S{
S __ASM ("clrex");
S}
S
S/**
S * @brief Return the Process Stack Pointer
S *
S * @param none
S * @return uint32_t ProcessStackPointer
S *
S * Return the actual process stack pointer
S */
Sextern uint32_t __get_PSP(void);
S
S/**
S * @brief Set the Process Stack Pointer
S *
S * @param uint32_t Process Stack Pointer
S * @return none
S *
S * Assign the value ProcessStackPointer to the MSP
S * (process stack pointer) Cortex processor register
S */
Sextern void __set_PSP(uint32_t topOfProcStack);
S
S/**
S * @brief Return the Main Stack Pointer
S *
S * @param none
S * @return uint32_t Main Stack Pointer
S *
S * Return the current value of the MSP (main stack pointer)
S * Cortex processor register
S */
Sextern uint32_t __get_MSP(void);
S
S/**
S * @brief Set the Main Stack Pointer
S *
S * @param uint32_t Main Stack Pointer
S * @return none
S *
S * Assign the value mainStackPointer to the MSP
S * (main stack pointer) Cortex processor register
S */
Sextern void __set_MSP(uint32_t topOfMainStack);
S
S/**
S * @brief Reverse byte order in unsigned short value
S *
S * @param uint16_t value to reverse
S * @return uint32_t reversed value
S *
S * Reverse byte order in unsigned short value
S */
Sextern uint32_t __REV16(uint16_t value);
S
S/**
S * @brief Reverse bit order of value
S *
S * @param uint32_t value to reverse
S * @return uint32_t reversed value
S *
S * Reverse bit order of value
S */
Sextern uint32_t __RBIT(uint32_t value);
S
S/**
S * @brief LDR Exclusive
S *
S * @param uint8_t* address
S * @return uint8_t value of (*address)
S *
S * Exclusive LDR command
S */
Sextern uint8_t __LDREXB(uint8_t *addr);
S
S/**
S * @brief LDR Exclusive
S *
S * @param uint16_t* address
S * @return uint16_t value of (*address)
S *
S * Exclusive LDR command
S */
Sextern uint16_t __LDREXH(uint16_t *addr);
S
S/**
S * @brief LDR Exclusive
S *
S * @param uint32_t* address
S * @return uint32_t value of (*address)
S *
S * Exclusive LDR command
S */
Sextern uint32_t __LDREXW(uint32_t *addr);
S
S/**
S * @brief STR Exclusive
S *
S * @param uint8_t *address
S * @param uint8_t value to store
S * @return uint32_t successful / failed
S *
S * Exclusive STR command
S */
Sextern uint32_t __STREXB(uint8_t value, uint8_t *addr);
S
S/**
S * @brief STR Exclusive
S *
S * @param uint16_t *address
S * @param uint16_t value to store
S * @return uint32_t successful / failed
S *
S * Exclusive STR command
S */
Sextern uint32_t __STREXH(uint16_t value, uint16_t *addr);
S
S/**
S * @brief STR Exclusive
S *
S * @param uint32_t *address
S * @param uint32_t value to store
S * @return uint32_t successful / failed
S *
S * Exclusive STR command
S */
Sextern uint32_t __STREXW(uint32_t value, uint32_t *addr);
S
S
S/* intrinsic void __set_PRIMASK(); */
S/* intrinsic void __get_PRIMASK(); */
S/* intrinsic void __set_FAULTMASK(); */
S/* intrinsic void __get_FAULTMASK(); */
S/* intrinsic uint32_t __REV(uint32_t value); */
S/* intrinsic uint32_t __REVSH(uint32_t value); */
S/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
S/* intrinsic unsigned long __LDREX(unsigned long *); */
S
S
S
S#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
S/* GNU gcc specific functions */
S
Sstatic __INLINE void __NOP()
S{
S __ASM volatile ("nop");
S}
Sstatic __INLINE void __enable_irq()
S{
S __ASM volatile ("cpsie i");
S}
Sstatic __INLINE void __disable_irq()
S{
S __ASM volatile ("cpsid i");
S}
S
Sstatic __INLINE void __enable_fault_irq()
S{
S __ASM volatile ("cpsie f");
S}
Sstatic __INLINE void __disable_fault_irq()
S{
S __ASM volatile ("cpsid f");
S}
S
Sstatic __INLINE void __WFI()
S{
S __ASM volatile ("wfi");
S}
Sstatic __INLINE void __WFE()
S{
S __ASM volatile ("wfe");
S}
Sstatic __INLINE void __SEV()
S{
S __ASM volatile ("sev");
S}
Sstatic __INLINE void __ISB(arg)
S{
S __ASM volatile ("isb");
S}
Sstatic __INLINE void __DSB(arg)
S{
S __ASM volatile ("dsb");
S}
Sstatic __INLINE void __DMB(arg)
S{
S __ASM volatile ("dmb");
S}
Sstatic __INLINE void __CLREX()
S{
S __ASM volatile ("clrex");
S}
S
S
S/**
S * @brief Return the Process Stack Pointer
S *
S * @param none
S * @return uint32_t ProcessStackPointer
S *
S * Return the actual process stack pointer
S */
Sextern uint32_t __get_PSP(void);
S
S/**
S * @brief Set the Process Stack Pointer
S *
S * @param uint32_t Process Stack Pointer
S * @return none
S *
S * Assign the value ProcessStackPointer to the MSP
S * (process stack pointer) Cortex processor register
S */
Sextern void __set_PSP(uint32_t topOfProcStack);
S
S/**
S * @brief Return the Main Stack Pointer
S *
S * @param none
S * @return uint32_t Main Stack Pointer
S *
S * Return the current value of the MSP (main stack pointer)
S * Cortex processor register
S */
Sextern uint32_t __get_MSP(void);
S
S/**
S * @brief Set the Main Stack Pointer
S *
S * @param uint32_t Main Stack Pointer
S * @return none
S *
S * Assign the value mainStackPointer to the MSP
S * (main stack pointer) Cortex processor register
S */
Sextern void __set_MSP(uint32_t topOfMainStack);
S
S/**
S * @brief Return the Base Priority value
S *
S * @param none
S * @return uint32_t BasePriority
S *
S * Return the content of the base priority register
S */
Sextern uint32_t __get_BASEPRI(void);
S
S/**
S * @brief Set the Base Priority value
S *
S * @param uint32_t BasePriority
S * @return none
S *
S * Set the base priority register
S */
Sextern void __set_BASEPRI(uint32_t basePri);
S
S/**
S * @brief Return the Priority Mask value
S *
S * @param none
S * @return uint32_t PriMask
S *
S * Return the state of the priority mask bit from the priority mask
S * register
S */
Sextern uint32_t __get_PRIMASK(void);
S
S/**
S * @brief Set the Priority Mask value
S *
S * @param uint32_t PriMask
S * @return none
S *
S * Set the priority mask bit in the priority mask register
S */
Sextern void __set_PRIMASK(uint32_t priMask);
S
S/**
S * @brief Return the Fault Mask value
S *
S * @param none
S * @return uint32_t FaultMask
S *
S * Return the content of the fault mask register
S */
Sextern uint32_t __get_FAULTMASK(void);
S
S/**
S * @brief Set the Fault Mask value
S *
S * @param uint32_t faultMask value
S * @return none
S *
S * Set the fault mask register
S */
Sextern void __set_FAULTMASK(uint32_t faultMask);
S
S/**
S * @brief Return the Control Register value
S*
S* @param none
S* @return uint32_t Control value
S *
S * Return the content of the control register
S */
Sextern uint32_t __get_CONTROL(void);
S
S/**
S * @brief Set the Control Register value
S *
S * @param uint32_t Control value
S * @return none
S *
S * Set the control register
S */
Sextern void __set_CONTROL(uint32_t control);
S
S/**
S * @brief Reverse byte order in integer value
S *
S * @param uint32_t value to reverse
S * @return uint32_t reversed value
S *
S * Reverse byte order in integer value
S */
Sextern uint32_t __REV(uint32_t value);
S
S/**
S * @brief Reverse byte order in unsigned short value
S *
S * @param uint16_t value to reverse
S * @return uint32_t reversed value
S *
S * Reverse byte order in unsigned short value
S */
Sextern uint32_t __REV16(uint16_t value);
S
S/*
S * Reverse byte order in signed short value with sign extension to integer
S *
S * @param int16_t value to reverse
S * @return int32_t reversed value
S *
S * @brief Reverse byte order in signed short value with sign extension to integer
S */
Sextern int32_t __REVSH(int16_t value);
S
S/**
S * @brief Reverse bit order of value
S *
S * @param uint32_t value to reverse
S * @return uint32_t reversed value
S *
S * Reverse bit order of value
S */
Sextern uint32_t __RBIT(uint32_t value);
S
S/**
S * @brief LDR Exclusive
S *
S * @param uint8_t* address
S * @return uint8_t value of (*address)
S *
S * Exclusive LDR command
S */
Sextern uint8_t __LDREXB(uint8_t *addr);
S
S/**
S * @brief LDR Exclusive
S *
S * @param uint16_t* address
S * @return uint16_t value of (*address)
S *
S * Exclusive LDR command
S */
Sextern uint16_t __LDREXH(uint16_t *addr);
S
S/**
S * @brief LDR Exclusive
S *
S * @param uint32_t* address
S * @return uint32_t value of (*address)
S *
S * Exclusive LDR command
S */
Sextern uint32_t __LDREXW(uint32_t *addr);
S
S/**
S * @brief STR Exclusive
S *
S * @param uint8_t *address
S * @param uint8_t value to store
S * @return uint32_t successful / failed
S *
S * Exclusive STR command
S */
Sextern uint32_t __STREXB(uint8_t value, uint8_t *addr);
S
S/**
S * @brief STR Exclusive
S *
S * @param uint16_t *address
S * @param uint16_t value to store
S * @return uint32_t successful / failed
S *
S * Exclusive STR command
S */
Sextern uint32_t __STREXH(uint16_t value, uint16_t *addr);
S
S/**
S * @brief STR Exclusive
S *
S * @param uint32_t *address
S * @param uint32_t value to store
S * @return uint32_t successful / failed
S *
S * Exclusive STR command
S */
Sextern uint32_t __STREXW(uint32_t value, uint32_t *addr);
S
S
N#endif
N
N
N
N/* ########################## NVIC functions #################################### */
N
N/**
N * @brief Set the Priority Grouping in NVIC Interrupt Controller
N *
N * @param uint32_t priority_grouping is priority grouping field
N * @return
N *
N * Set the priority grouping field using the required unlock sequence.
N * The parameter priority_grouping is assigned to the field
N * SCB->AIRCR [10:8] PRIGROUP field.
N */
Nstatic __INLINE void NVIC_SetPriorityGrouping(uint32_t priority_grouping)
Xstatic __inline void NVIC_SetPriorityGrouping(uint32_t priority_grouping)
N{
N uint32_t reg_value = 0;
N
N reg_value = SCB->AIRCR; /* read old register configuration */
X reg_value = ((SCB_Type *) ((0xE000E000) + 0x0D00))->AIRCR;
N reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */
N reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (priority_grouping << 8))); /* Insert write key and priorty group */
X reg_value = ((reg_value | (0x5FA << 16) | (priority_grouping << 8)));
N SCB->AIRCR = reg_value;
X ((SCB_Type *) ((0xE000E000) + 0x0D00))->AIRCR = reg_value;
N}
N
N/**
N * @brief Enable Interrupt in NVIC Interrupt Controller
N *
N * @param IRQn_Type IRQn specifies the interrupt number
N * @return none
N *
N * Enable a device specific interupt in the NVIC interrupt controller.
N * The interrupt number cannot be a negative value.
N */
Nstatic __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Xstatic __inline void NVIC_EnableIRQ(IRQn_Type IRQn)
N{
N NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
X ((NVIC_Type *) ((0xE000E000) + 0x0100))->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
N}
N
N/**
N * @brief Disable the interrupt line for external interrupt specified
N *
N * @param IRQn_Type IRQn is the positive number of the external interrupt
N * @return none
N *
N * Disable a device specific interupt in the NVIC interrupt controller.
N * The interrupt number cannot be a negative value.
N */
Nstatic __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Xstatic __inline void NVIC_DisableIRQ(IRQn_Type IRQn)
N{
N NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
X ((NVIC_Type *) ((0xE000E000) + 0x0100))->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
N}
N
N/**
N * @brief Read the interrupt pending bit for a device specific interrupt source
N *
N * @param IRQn_Type IRQn is the number of the device specifc interrupt
N * @return IRQn_Type Number of pending interrupt or zero
N *
N * Read the pending register in NVIC and return the number of the
N * specified interrupt if its status is pending, otherwise it returns
N * zero. The interrupt number cannot be a negative value.
N */
Nstatic __INLINE IRQn_Type NVIC_GetPendingIRQ(IRQn_Type IRQn)
Xstatic __inline IRQn_Type NVIC_GetPendingIRQ(IRQn_Type IRQn)
N{
N return((IRQn_Type) (NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))); /* Return Interrupt bit or 'zero' */
X return((IRQn_Type) (((NVIC_Type *) ((0xE000E000) + 0x0100))->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))));
N}
N
N/**
N * @brief Set the pending bit for an external interrupt
N *
N * @param IRQn_Type IRQn is the Number of the interrupt
N * @return none
N *
N * Set the pending bit for the specified interrupt.
N * The interrupt number cannot be a negative value.
N */
Nstatic __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Xstatic __inline void NVIC_SetPendingIRQ(IRQn_Type IRQn)
N{
N NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
X ((NVIC_Type *) ((0xE000E000) + 0x0100))->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
N}
N
N/**
N * @brief Clear the pending bit for an external interrupt
N *
N * @param IRQn_Type IRQn is the Number of the interrupt
N * @return none
N *
N * Clear the pending bit for the specified interrupt.
N * The interrupt number cannot be a negative value.
N */
Nstatic __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Xstatic __inline void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
N{
N NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
X ((NVIC_Type *) ((0xE000E000) + 0x0100))->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
N}
N
N/**
N * @brief Read the active bit for an external interrupt
N *
N * @param IRQn_Type IRQn is the Number of the interrupt
N * @return IRQn_Type Number of pending interrupt or zero
N *
N * Read the active register in NVIC and returns the number of the
N * specified interrupt if its status is active, otherwise it
N * returns zero. The interrupt number cannot be a negative value.
N */
Nstatic __INLINE IRQn_Type NVIC_GetActive(IRQn_Type IRQn)
Xstatic __inline IRQn_Type NVIC_GetActive(IRQn_Type IRQn)
N{
N return((IRQn_Type)(NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))); /* Return Interruptnumber or 'zero' */
X return((IRQn_Type)(((NVIC_Type *) ((0xE000E000) + 0x0100))->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))));
N}
N
N/**
N * @brief Set the priority for an interrupt
N *
N * @param IRQn_Type IRQn is the Number of the interrupt
N * @param priority is the priority for the interrupt
N * @return none
N *
N * Set the priority for the specified interrupt. The interrupt
N * number can be positive to specify an external (device specific)
N * interrupt, or negative to specify an internal (core) interrupt. \n
N *
N * Note: The priority cannot be set for every core interrupt.
N */
Nstatic __INLINE void NVIC_SetPriority(IRQn_Type IRQn, int32_t priority)
Xstatic __inline void NVIC_SetPriority(IRQn_Type IRQn, int32_t priority)
N{
N if(IRQn < 0)
N {
N SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
X ((SCB_Type *) ((0xE000E000) + 0x0D00))->SHP[((uint32_t)(IRQn) & 0xF) - 4] = ((priority << (8 - 4)) & 0xff);
N } /* set Priority for Cortex-M3 System Interrupts */
N else
N {
N NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
X ((NVIC_Type *) ((0xE000E000) + 0x0100))->IP[(uint32_t)(IRQn)] = ((priority << (8 - 4)) & 0xff);
N } /* set Priority for device specific Interrupts */
N}
N
N/**
N * @brief Read the priority for an interrupt
N *
N * @param IRQn_Type IRQn is the Number of the interrupt
N * @return priority is the priority for the interrupt
N *
N * Read the priority for the specified interrupt. The interrupt
N * number can be positive to specify an external (device specific)
N * interrupt, or negative to specify an internal (core) interrupt.
N *
N * The returned priority value is automatically aligned to the implemented
N * priority bits of the microcontroller.
N *
N * Note: The priority cannot be set for every core interrupt.
N */
Nstatic __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Xstatic __inline uint32_t NVIC_GetPriority(IRQn_Type IRQn)
N{
N
N if(IRQn < 0)
N {
N return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] >> (8 - __NVIC_PRIO_BITS)));
X return((uint32_t)(((SCB_Type *) ((0xE000E000) + 0x0D00))->SHP[((uint32_t)(IRQn) & 0xF) - 4] >> (8 - 4)));
N } /* get priority for Cortex-M3 system interrupts */
N else
N {
N return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS)));
X return((uint32_t)(((NVIC_Type *) ((0xE000E000) + 0x0100))->IP[(uint32_t)(IRQn)] >> (8 - 4)));
N } /* get priority for device specific interrupts */
N}
N
N
N
N/* ################################## SysTick function ############################################ */
N
N#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
X#if (!1L) || (0 == 0)
N
N/* SysTick constants */
N#define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */
N#define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */
N#define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */
N#define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */
N
N/**
N * @brief Initialize and start the SysTick counter and its interrupt.
N *
N * @param uint32_t ticks is the number of ticks between two interrupts
N * @return none
N *
N * Initialise the system tick timer and its interrupt and start the
N * system tick timer / counter in free running mode to generate
N * periodical interrupts.
N */
Nstatic __INLINE uint32_t SysTick_Config(uint32_t ticks)
Xstatic __inline uint32_t SysTick_Config(uint32_t ticks)
N{
N if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */
X if (ticks > ((1<<24) -1)) return (1);
N
N SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */
X ((SysTick_Type *) ((0xE000E000) + 0x0010))->LOAD = (ticks & ((1<<24) -1)) - 1;
N //NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
N NVIC_SetPriority (SysTick_IRQn, 0); //HQ20110716 /* set Priority for Cortex-M0 System Interrupts */
N SysTick->VAL = (0x00); /* Load the SysTick Counter Value */
X ((SysTick_Type *) ((0xE000E000) + 0x0010))->VAL = (0x00);
N SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1 << SYSTICK_ENABLE) | (1 << SYSTICK_TICKINT); /* Enable SysTick IRQ and SysTick Timer */
X ((SysTick_Type *) ((0xE000E000) + 0x0010))->CTRL = (1 << 2) | (1 << 0) | (1 << 1);
N return (0); /* Function successful */
N}
N
N#endif
N
N
N
N
N
N/* ################################## Reset function ############################################ */
N
N/**
N * @brief Initiate a system reset request.
N *
N * @param none
N * @return none
N *
N * Initialize a system reset request to reset the MCU
N */
Nstatic __INLINE void NVIC_SystemReset(void)
Xstatic __inline void NVIC_SystemReset(void)
N{
N SCB->AIRCR = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1 << NVIC_SYSRESETREQ)); /* Keep priority group unchanged */
X ((SCB_Type *) ((0xE000E000) + 0x0D00))->AIRCR = ((0x5FA << 16) | (((SCB_Type *) ((0xE000E000) + 0x0D00))->AIRCR & (0x700)) | (1 << 2));
N}
N
N
N/* ################################## Debug Output function ############################################ */
N
N
N/**
N * @brief Outputs a character via the ITM channel 0
N *
N * @param uint32_t character to output
N * @return uint32_t input character
N *
N * The function outputs a character via the ITM channel 0.
N * The function returns when no debugger is connected that has booked the output.
N * It is blocking when a debugger is connected, but the previous character send is not transmitted.
N */
Nstatic __INLINE uint32_t ITM_SendChar (uint32_t ch)
Xstatic __inline uint32_t ITM_SendChar (uint32_t ch)
N{
N if(ch == '\n') ITM_SendChar('\r');
N
N if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
X if ((((CoreDebug_Type *) (0xE000EDF0))->DEMCR & (1 << 24)) &&
N (ITM->TCR & ITM_TCR_ITMENA) &&
X (((ITM_Type *) (0xE0000000))->TCR & 1) &&
N (ITM->TER & (1UL << 0)) )
X (((ITM_Type *) (0xE0000000))->TER & (1UL << 0)) )
N {
N while (ITM->PORT[0].u32 == 0);
X while (((ITM_Type *) (0xE0000000))->PORT[0].u32 == 0);
N ITM->PORT[0].u8 = (uint8_t) ch;
X ((ITM_Type *) (0xE0000000))->PORT[0].u8 = (uint8_t) ch;
N }
N return (ch);
N}
N
N#endif
N
N/*lint -restore */
L 197 "..\src\STM32Lib\stm32f10x.h" 2
N#include "system_stm32f10x.h"
L 1 "..\src\STM32Lib\system_stm32f10x.h" 1
N/**
N ******************************************************************************
N * @file system_stm32f10x.h
N * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
N * @author STMicroelectronics - MCD Application Team
N * @version V3.0.0
N * @date 04/06/2009
N ******************************************************************************
N *
N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N *
N * © COPYRIGHT 2009 STMicroelectronics
N ******************************************************************************
N */
N
N/**
N * @brief Define to prevent recursive inclusion
N */
N#ifndef __SYSTEM_STM32F10X_H
N#define __SYSTEM_STM32F10X_H
N
N/** @addtogroup Includes
N * @{
N */
N
N/**
N * @}
N */
N
N
N/** @addtogroup Exported_types
N * @{
N */
N
Nextern const uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */
Nextern const uint32_t SystemFrequency_SysClk; /*!< System clock */
Nextern const uint32_t SystemFrequency_AHBClk; /*!< AHB System bus speed */
Nextern const uint32_t SystemFrequency_APB1Clk; /*!< APB Peripheral Bus 1 (low) speed */
Nextern const uint32_t SystemFrequency_APB2Clk; /*!< APB Peripheral Bus 2 (high) speed */
N
N/**
N * @}
N */
N
N/** @addtogroup Exported_Constants
N * @{
N */
N
N/**
N * @}
N */
N
N/** @addtogroup Exported_Macros
N * @{
N */
N
N/**
N * @}
N */
N
N/** @addtogroup Exported_Functions
N * @{
N */
N
Nextern void SystemInit(void);
N/**
N * @}
N */
N
N#endif /*__SYSTEM_STM32F10X_H */
N
N/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
L 198 "..\src\STM32Lib\stm32f10x.h" 2
N#include
N
N/** @addtogroup Exported_types
N * @{
N */
N
N/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy prupose) */
Ntypedef int32_t s32;
Ntypedef int16_t s16;
Ntypedef int8_t s8;
N
Ntypedef const int32_t sc32; /*!< Read Only */
Ntypedef const int16_t sc16; /*!< Read Only */
Ntypedef const int8_t sc8; /*!< Read Only */
N
Ntypedef __IO int32_t vs32;
Xtypedef volatile int32_t vs32;
Ntypedef __IO int16_t vs16;
Xtypedef volatile int16_t vs16;
Ntypedef __IO int8_t vs8;
Xtypedef volatile int8_t vs8;
N
Ntypedef __I int32_t vsc32; /*!< Read Only */
Xtypedef volatile const int32_t vsc32;
Ntypedef __I int16_t vsc16; /*!< Read Only */
Xtypedef volatile const int16_t vsc16;
Ntypedef __I int8_t vsc8; /*!< Read Only */
Xtypedef volatile const int8_t vsc8;
N
Ntypedef uint32_t u32;
Ntypedef uint16_t u16;
Ntypedef uint8_t u8;
N
Ntypedef const uint32_t uc32; /*!< Read Only */
Ntypedef const uint16_t uc16; /*!< Read Only */
Ntypedef const uint8_t uc8; /*!< Read Only */
N
Ntypedef __IO uint32_t vu32;
Xtypedef volatile uint32_t vu32;
Ntypedef __IO uint16_t vu16;
Xtypedef volatile uint16_t vu16;
Ntypedef __IO uint8_t vu8;
Xtypedef volatile uint8_t vu8;
N
Ntypedef __I uint32_t vuc32; /*!< Read Only */
Xtypedef volatile const uint32_t vuc32;
Ntypedef __I uint16_t vuc16; /*!< Read Only */
Xtypedef volatile const uint16_t vuc16;
Ntypedef __I uint8_t vuc8; /*!< Read Only */
Xtypedef volatile const uint8_t vuc8;
N
Ntypedef enum {FALSE = 0, TRUE = !FALSE} bool;
N
Ntypedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
N
Ntypedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
N#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
N
Ntypedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
N
N/**
N * @}
N */
N
N/** @addtogroup Peripheral_registers_structures
N * @{
N */
N
N/**
N * @brief Analog to Digital Converter
N */
N
Ntypedef struct
N{
N __IO uint32_t SR;
X volatile uint32_t SR;
N __IO uint32_t CR1;
X volatile uint32_t CR1;
N __IO uint32_t CR2;
X volatile uint32_t CR2;
N __IO uint32_t SMPR1;
X volatile uint32_t SMPR1;
N __IO uint32_t SMPR2;
X volatile uint32_t SMPR2;
N __IO uint32_t JOFR1;
X volatile uint32_t JOFR1;
N __IO uint32_t JOFR2;
X volatile uint32_t JOFR2;
N __IO uint32_t JOFR3;
X volatile uint32_t JOFR3;
N __IO uint32_t JOFR4;
X volatile uint32_t JOFR4;
N __IO uint32_t HTR;
X volatile uint32_t HTR;
N __IO uint32_t LTR;
X volatile uint32_t LTR;
N __IO uint32_t SQR1;
X volatile uint32_t SQR1;
N __IO uint32_t SQR2;
X volatile uint32_t SQR2;
N __IO uint32_t SQR3;
X volatile uint32_t SQR3;
N __IO uint32_t JSQR;
X volatile uint32_t JSQR;
N __IO uint32_t JDR1;
X volatile uint32_t JDR1;
N __IO uint32_t JDR2;
X volatile uint32_t JDR2;
N __IO uint32_t JDR3;
X volatile uint32_t JDR3;
N __IO uint32_t JDR4;
X volatile uint32_t JDR4;
N __IO uint32_t DR;
X volatile uint32_t DR;
N} ADC_TypeDef;
N
N/**
N * @brief Backup Registers
N */
N
Ntypedef struct
N{
N uint32_t RESERVED0;
N __IO uint16_t DR1;
X volatile uint16_t DR1;
N uint16_t RESERVED1;
N __IO uint16_t DR2;
X volatile uint16_t DR2;
N uint16_t RESERVED2;
N __IO uint16_t DR3;
X volatile uint16_t DR3;
N uint16_t RESERVED3;
N __IO uint16_t DR4;
X volatile uint16_t DR4;
N uint16_t RESERVED4;
N __IO uint16_t DR5;
X volatile uint16_t DR5;
N uint16_t RESERVED5;
N __IO uint16_t DR6;
X volatile uint16_t DR6;
N uint16_t RESERVED6;
N __IO uint16_t DR7;
X volatile uint16_t DR7;
N uint16_t RESERVED7;
N __IO uint16_t DR8;
X volatile uint16_t DR8;
N uint16_t RESERVED8;
N __IO uint16_t DR9;
X volatile uint16_t DR9;
N uint16_t RESERVED9;
N __IO uint16_t DR10;
X volatile uint16_t DR10;
N uint16_t RESERVED10;
N __IO uint16_t RTCCR;
X volatile uint16_t RTCCR;
N uint16_t RESERVED11;
N __IO uint16_t CR;
X volatile uint16_t CR;
N uint16_t RESERVED12;
N __IO uint16_t CSR;
X volatile uint16_t CSR;
N uint16_t RESERVED13[5];
N __IO uint16_t DR11;
X volatile uint16_t DR11;
N uint16_t RESERVED14;
N __IO uint16_t DR12;
X volatile uint16_t DR12;
N uint16_t RESERVED15;
N __IO uint16_t DR13;
X volatile uint16_t DR13;
N uint16_t RESERVED16;
N __IO uint16_t DR14;
X volatile uint16_t DR14;
N uint16_t RESERVED17;
N __IO uint16_t DR15;
X volatile uint16_t DR15;
N uint16_t RESERVED18;
N __IO uint16_t DR16;
X volatile uint16_t DR16;
N uint16_t RESERVED19;
N __IO uint16_t DR17;
X volatile uint16_t DR17;
N uint16_t RESERVED20;
N __IO uint16_t DR18;
X volatile uint16_t DR18;
N uint16_t RESERVED21;
N __IO uint16_t DR19;
X volatile uint16_t DR19;
N uint16_t RESERVED22;
N __IO uint16_t DR20;
X volatile uint16_t DR20;
N uint16_t RESERVED23;
N __IO uint16_t DR21;
X volatile uint16_t DR21;
N uint16_t RESERVED24;
N __IO uint16_t DR22;
X volatile uint16_t DR22;
N uint16_t RESERVED25;
N __IO uint16_t DR23;
X volatile uint16_t DR23;
N uint16_t RESERVED26;
N __IO uint16_t DR24;
X volatile uint16_t DR24;
N uint16_t RESERVED27;
N __IO uint16_t DR25;
X volatile uint16_t DR25;
N uint16_t RESERVED28;
N __IO uint16_t DR26;
X volatile uint16_t DR26;
N uint16_t RESERVED29;
N __IO uint16_t DR27;
X volatile uint16_t DR27;
N uint16_t RESERVED30;
N __IO uint16_t DR28;
X volatile uint16_t DR28;
N uint16_t RESERVED31;
N __IO uint16_t DR29;
X volatile uint16_t DR29;
N uint16_t RESERVED32;
N __IO uint16_t DR30;
X volatile uint16_t DR30;
N uint16_t RESERVED33;
N __IO uint16_t DR31;
X volatile uint16_t DR31;
N uint16_t RESERVED34;
N __IO uint16_t DR32;
X volatile uint16_t DR32;
N uint16_t RESERVED35;
N __IO uint16_t DR33;
X volatile uint16_t DR33;
N uint16_t RESERVED36;
N __IO uint16_t DR34;
X volatile uint16_t DR34;
N uint16_t RESERVED37;
N __IO uint16_t DR35;
X volatile uint16_t DR35;
N uint16_t RESERVED38;
N __IO uint16_t DR36;
X volatile uint16_t DR36;
N uint16_t RESERVED39;
N __IO uint16_t DR37;
X volatile uint16_t DR37;
N uint16_t RESERVED40;
N __IO uint16_t DR38;
X volatile uint16_t DR38;
N uint16_t RESERVED41;
N __IO uint16_t DR39;
X volatile uint16_t DR39;
N uint16_t RESERVED42;
N __IO uint16_t DR40;
X volatile uint16_t DR40;
N uint16_t RESERVED43;
N __IO uint16_t DR41;
X volatile uint16_t DR41;
N uint16_t RESERVED44;
N __IO uint16_t DR42;
X volatile uint16_t DR42;
N uint16_t RESERVED45;
N} BKP_TypeDef;
N
N/**
N * @brief Controller Area Network TxMailBox
N */
N
Ntypedef struct
N{
N __IO uint32_t TIR;
X volatile uint32_t TIR;
N __IO uint32_t TDTR;
X volatile uint32_t TDTR;
N __IO uint32_t TDLR;
X volatile uint32_t TDLR;
N __IO uint32_t TDHR;
X volatile uint32_t TDHR;
N} CAN_TxMailBox_TypeDef;
N
N/**
N * @brief Controller Area Network FIFOMailBox
N */
N
Ntypedef struct
N{
N __IO uint32_t RIR;
X volatile uint32_t RIR;
N __IO uint32_t RDTR;
X volatile uint32_t RDTR;
N __IO uint32_t RDLR;
X volatile uint32_t RDLR;
N __IO uint32_t RDHR;
X volatile uint32_t RDHR;
N} CAN_FIFOMailBox_TypeDef;
N
N/**
N * @brief Controller Area Network FilterRegister
N */
N
Ntypedef struct
N{
N __IO uint32_t FR1;
X volatile uint32_t FR1;
N __IO uint32_t FR2;
X volatile uint32_t FR2;
N} CAN_FilterRegister_TypeDef;
N
N/**
N * @brief Controller Area Network
N */
N
Ntypedef struct
N{
N __IO uint32_t MCR;
X volatile uint32_t MCR;
N __IO uint32_t MSR;
X volatile uint32_t MSR;
N __IO uint32_t TSR;
X volatile uint32_t TSR;
N __IO uint32_t RF0R;
X volatile uint32_t RF0R;
N __IO uint32_t RF1R;
X volatile uint32_t RF1R;
N __IO uint32_t IER;
X volatile uint32_t IER;
N __IO uint32_t ESR;
X volatile uint32_t ESR;
N __IO uint32_t BTR;
X volatile uint32_t BTR;
N uint32_t RESERVED0[88];
N CAN_TxMailBox_TypeDef sTxMailBox[3];
N CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
N uint32_t RESERVED1[12];
N __IO uint32_t FMR;
X volatile uint32_t FMR;
N __IO uint32_t FM1R;
X volatile uint32_t FM1R;
N uint32_t RESERVED2;
N __IO uint32_t FS1R;
X volatile uint32_t FS1R;
N uint32_t RESERVED3;
N __IO uint32_t FFA1R;
X volatile uint32_t FFA1R;
N uint32_t RESERVED4;
N __IO uint32_t FA1R;
X volatile uint32_t FA1R;
N uint32_t RESERVED5[8];
N CAN_FilterRegister_TypeDef sFilterRegister[14];
N} CAN_TypeDef;
N
N/**
N * @brief CRC calculation unit
N */
N
Ntypedef struct
N{
N __IO uint32_t DR;
X volatile uint32_t DR;
N __IO uint8_t IDR;
X volatile uint8_t IDR;
N uint8_t RESERVED0;
N uint16_t RESERVED1;
N __IO uint32_t CR;
X volatile uint32_t CR;
N} CRC_TypeDef;
N
N/**
N * @brief Digital to Analog Converter
N */
N
Ntypedef struct
N{
N __IO uint32_t CR;
X volatile uint32_t CR;
N __IO uint32_t SWTRIGR;
X volatile uint32_t SWTRIGR;
N __IO uint32_t DHR12R1;
X volatile uint32_t DHR12R1;
N __IO uint32_t DHR12L1;
X volatile uint32_t DHR12L1;
N __IO uint32_t DHR8R1;
X volatile uint32_t DHR8R1;
N __IO uint32_t DHR12R2;
X volatile uint32_t DHR12R2;
N __IO uint32_t DHR12L2;
X volatile uint32_t DHR12L2;
N __IO uint32_t DHR8R2;
X volatile uint32_t DHR8R2;
N __IO uint32_t DHR12RD;
X volatile uint32_t DHR12RD;
N __IO uint32_t DHR12LD;
X volatile uint32_t DHR12LD;
N __IO uint32_t DHR8RD;
X volatile uint32_t DHR8RD;
N __IO uint32_t DOR1;
X volatile uint32_t DOR1;
N __IO uint32_t DOR2;
X volatile uint32_t DOR2;
N} DAC_TypeDef;
N
N/**
N * @brief Debug MCU
N */
N
Ntypedef struct
N{
N __IO uint32_t IDCODE;
X volatile uint32_t IDCODE;
N __IO uint32_t CR;
X volatile uint32_t CR;
N} DBGMCU_TypeDef;
N
N/**
N * @brief DMA Controller
N */
N
Ntypedef struct
N{
N __IO uint32_t CCR;
X volatile uint32_t CCR;
N __IO uint32_t CNDTR;
X volatile uint32_t CNDTR;
N __IO uint32_t CPAR;
X volatile uint32_t CPAR;
N __IO uint32_t CMAR;
X volatile uint32_t CMAR;
N} DMA_Channel_TypeDef;
N
Ntypedef struct
N{
N __IO uint32_t ISR;
X volatile uint32_t ISR;
N __IO uint32_t IFCR;
X volatile uint32_t IFCR;
N} DMA_TypeDef;
N
N/**
N * @brief External Interrupt/Event Controller
N */
N
Ntypedef struct
N{
N __IO uint32_t IMR;
X volatile uint32_t IMR;
N __IO uint32_t EMR;
X volatile uint32_t EMR;
N __IO uint32_t RTSR;
X volatile uint32_t RTSR;
N __IO uint32_t FTSR;
X volatile uint32_t FTSR;
N __IO uint32_t SWIER;
X volatile uint32_t SWIER;
N __IO uint32_t PR;
X volatile uint32_t PR;
N} EXTI_TypeDef;
N
N/**
N * @brief FLASH Registers
N */
N
Ntypedef struct
N{
N __IO uint32_t ACR;
X volatile uint32_t ACR;
N __IO uint32_t KEYR;
X volatile uint32_t KEYR;
N __IO uint32_t OPTKEYR;
X volatile uint32_t OPTKEYR;
N __IO uint32_t SR;
X volatile uint32_t SR;
N __IO uint32_t CR;
X volatile uint32_t CR;
N __IO uint32_t AR;
X volatile uint32_t AR;
N __IO uint32_t RESERVED;
X volatile uint32_t RESERVED;
N __IO uint32_t OBR;
X volatile uint32_t OBR;
N __IO uint32_t WRPR;
X volatile uint32_t WRPR;
N} FLASH_TypeDef;
N
N/**
N * @brief Option Bytes Registers
N */
N
Ntypedef struct
N{
N __IO uint16_t RDP;
X volatile uint16_t RDP;
N __IO uint16_t USER;
X volatile uint16_t USER;
N __IO uint16_t Data0;
X volatile uint16_t Data0;
N __IO uint16_t Data1;
X volatile uint16_t Data1;
N __IO uint16_t WRP0;
X volatile uint16_t WRP0;
N __IO uint16_t WRP1;
X volatile uint16_t WRP1;
N __IO uint16_t WRP2;
X volatile uint16_t WRP2;
N __IO uint16_t WRP3;
X volatile uint16_t WRP3;
N} OB_TypeDef;
N
N/**
N * @brief Flexible Static Memory Controller
N */
N
Ntypedef struct
N{
N __IO uint32_t BTCR[8];
X volatile uint32_t BTCR[8];
N} FSMC_Bank1_TypeDef;
N
N/**
N * @brief Flexible Static Memory Controller Bank1E
N */
N
Ntypedef struct
N{
N __IO uint32_t BWTR[7];
X volatile uint32_t BWTR[7];
N} FSMC_Bank1E_TypeDef;
N
N/**
N * @brief Flexible Static Memory Controller Bank2
N */
N
Ntypedef struct
N{
N __IO uint32_t PCR2;
X volatile uint32_t PCR2;
N __IO uint32_t SR2;
X volatile uint32_t SR2;
N __IO uint32_t PMEM2;
X volatile uint32_t PMEM2;
N __IO uint32_t PATT2;
X volatile uint32_t PATT2;
N uint32_t RESERVED0;
N __IO uint32_t ECCR2;
X volatile uint32_t ECCR2;
N} FSMC_Bank2_TypeDef;
N
N/**
N * @brief Flexible Static Memory Controller Bank3
N */
N
Ntypedef struct
N{
N __IO uint32_t PCR3;
X volatile uint32_t PCR3;
N __IO uint32_t SR3;
X volatile uint32_t SR3;
N __IO uint32_t PMEM3;
X volatile uint32_t PMEM3;
N __IO uint32_t PATT3;
X volatile uint32_t PATT3;
N uint32_t RESERVED0;
N __IO uint32_t ECCR3;
X volatile uint32_t ECCR3;
N} FSMC_Bank3_TypeDef;
N
N/**
N * @brief Flexible Static Memory Controller Bank4
N */
N
Ntypedef struct
N{
N __IO uint32_t PCR4;
X volatile uint32_t PCR4;
N __IO uint32_t SR4;
X volatile uint32_t SR4;
N __IO uint32_t PMEM4;
X volatile uint32_t PMEM4;
N __IO uint32_t PATT4;
X volatile uint32_t PATT4;
N __IO uint32_t PIO4;
X volatile uint32_t PIO4;
N} FSMC_Bank4_TypeDef;
N
N/**
N * @brief General Purpose IO
N */
N
Ntypedef struct
N{
N __IO uint32_t CRL;
X volatile uint32_t CRL;
N __IO uint32_t CRH;
X volatile uint32_t CRH;
N __IO uint32_t IDR;
X volatile uint32_t IDR;
N __IO uint32_t ODR;
X volatile uint32_t ODR;
N __IO uint32_t BSRR;
X volatile uint32_t BSRR;
N __IO uint32_t BRR;
X volatile uint32_t BRR;
N __IO uint32_t LCKR;
X volatile uint32_t LCKR;
N} GPIO_TypeDef;
N
N/**
N * @brief Alternate Function IO
N */
N
Ntypedef struct
N{
N __IO uint32_t EVCR;
X volatile uint32_t EVCR;
N __IO uint32_t MAPR;
X volatile uint32_t MAPR;
N __IO uint32_t EXTICR[4];
X volatile uint32_t EXTICR[4];
N} AFIO_TypeDef;
N/**
N * @brief Inter-integrated Circuit Interface
N */
N
Ntypedef struct
N{
N __IO uint16_t CR1;
X volatile uint16_t CR1;
N uint16_t RESERVED0;
N __IO uint16_t CR2;
X volatile uint16_t CR2;
N uint16_t RESERVED1;
N __IO uint16_t OAR1;
X volatile uint16_t OAR1;
N uint16_t RESERVED2;
N __IO uint16_t OAR2;
X volatile uint16_t OAR2;
N uint16_t RESERVED3;
N __IO uint16_t DR;
X volatile uint16_t DR;
N uint16_t RESERVED4;
N __IO uint16_t SR1;
X volatile uint16_t SR1;
N uint16_t RESERVED5;
N __IO uint16_t SR2;
X volatile uint16_t SR2;
N uint16_t RESERVED6;
N __IO uint16_t CCR;
X volatile uint16_t CCR;
N uint16_t RESERVED7;
N __IO uint16_t TRISE;
X volatile uint16_t TRISE;
N uint16_t RESERVED8;
N} I2C_TypeDef;
N
N/**
N * @brief Independent WATCHDOG
N */
N
Ntypedef struct
N{
N __IO uint32_t KR;
X volatile uint32_t KR;
N __IO uint32_t PR;
X volatile uint32_t PR;
N __IO uint32_t RLR;
X volatile uint32_t RLR;
N __IO uint32_t SR;
X volatile uint32_t SR;
N} IWDG_TypeDef;
N
N/**
N * @brief Power Control
N */
N
Ntypedef struct
N{
N __IO uint32_t CR;
X volatile uint32_t CR;
N __IO uint32_t CSR;
X volatile uint32_t CSR;
N} PWR_TypeDef;
N
N/**
N * @brief Reset and Clock Control
N */
N
Ntypedef struct
N{
N __IO uint32_t CR;
X volatile uint32_t CR;
N __IO uint32_t CFGR;
X volatile uint32_t CFGR;
N __IO uint32_t CIR;
X volatile uint32_t CIR;
N __IO uint32_t APB2RSTR;
X volatile uint32_t APB2RSTR;
N __IO uint32_t APB1RSTR;
X volatile uint32_t APB1RSTR;
N __IO uint32_t AHBENR;
X volatile uint32_t AHBENR;
N __IO uint32_t APB2ENR;
X volatile uint32_t APB2ENR;
N __IO uint32_t APB1ENR;
X volatile uint32_t APB1ENR;
N __IO uint32_t BDCR;
X volatile uint32_t BDCR;
N __IO uint32_t CSR;
X volatile uint32_t CSR;
N} RCC_TypeDef;
N
N/**
N * @brief Real-Time Clock
N */
N
Ntypedef struct
N{
N __IO uint16_t CRH;
X volatile uint16_t CRH;
N uint16_t RESERVED0;
N __IO uint16_t CRL;
X volatile uint16_t CRL;
N uint16_t RESERVED1;
N __IO uint16_t PRLH;
X volatile uint16_t PRLH;
N uint16_t RESERVED2;
N __IO uint16_t PRLL;
X volatile uint16_t PRLL;
N uint16_t RESERVED3;
N __IO uint16_t DIVH;
X volatile uint16_t DIVH;
N uint16_t RESERVED4;
N __IO uint16_t DIVL;
X volatile uint16_t DIVL;
N uint16_t RESERVED5;
N __IO uint16_t CNTH;
X volatile uint16_t CNTH;
N uint16_t RESERVED6;
N __IO uint16_t CNTL;
X volatile uint16_t CNTL;
N uint16_t RESERVED7;
N __IO uint16_t ALRH;
X volatile uint16_t ALRH;
N uint16_t RESERVED8;
N __IO uint16_t ALRL;
X volatile uint16_t ALRL;
N uint16_t RESERVED9;
N} RTC_TypeDef;
N
N/**
N * @brief SD host Interface
N */
N
Ntypedef struct
N{
N __IO uint32_t POWER;
X volatile uint32_t POWER;
N __IO uint32_t CLKCR;
X volatile uint32_t CLKCR;
N __IO uint32_t ARG;
X volatile uint32_t ARG;
N __IO uint32_t CMD;
X volatile uint32_t CMD;
N __I uint32_t RESPCMD;
X volatile const uint32_t RESPCMD;
N __I uint32_t RESP1;
X volatile const uint32_t RESP1;
N __I uint32_t RESP2;
X volatile const uint32_t RESP2;
N __I uint32_t RESP3;
X volatile const uint32_t RESP3;
N __I uint32_t RESP4;
X volatile const uint32_t RESP4;
N __IO uint32_t DTIMER;
X volatile uint32_t DTIMER;
N __IO uint32_t DLEN;
X volatile uint32_t DLEN;
N __IO uint32_t DCTRL;
X volatile uint32_t DCTRL;
N __I uint32_t DCOUNT;
X volatile const uint32_t DCOUNT;
N __I uint32_t STA;
X volatile const uint32_t STA;
N __IO uint32_t ICR;
X volatile uint32_t ICR;
N __IO uint32_t MASK;
X volatile uint32_t MASK;
N uint32_t RESERVED0[2];
N __I uint32_t FIFOCNT;
X volatile const uint32_t FIFOCNT;
N uint32_t RESERVED1[13];
N __IO uint32_t FIFO;
X volatile uint32_t FIFO;
N} SDIO_TypeDef;
N
N/**
N * @brief Serial Peripheral Interface
N */
N
Ntypedef struct
N{
N __IO uint16_t CR1;
X volatile uint16_t CR1;
N uint16_t RESERVED0;
N __IO uint16_t CR2;
X volatile uint16_t CR2;
N uint16_t RESERVED1;
N __IO uint16_t SR;
X volatile uint16_t SR;
N uint16_t RESERVED2;
N __IO uint16_t DR;
X volatile uint16_t DR;
N uint16_t RESERVED3;
N __IO uint16_t CRCPR;
X volatile uint16_t CRCPR;
N uint16_t RESERVED4;
N __IO uint16_t RXCRCR;
X volatile uint16_t RXCRCR;
N uint16_t RESERVED5;
N __IO uint16_t TXCRCR;
X volatile uint16_t TXCRCR;
N uint16_t RESERVED6;
N __IO uint16_t I2SCFGR;
X volatile uint16_t I2SCFGR;
N uint16_t RESERVED7;
N __IO uint16_t I2SPR;
X volatile uint16_t I2SPR;
N uint16_t RESERVED8;
N} SPI_TypeDef;
N
N/**
N * @brief TIM
N */
N
Ntypedef struct
N{
N __IO uint16_t CR1;
X volatile uint16_t CR1;
N uint16_t RESERVED0;
N __IO uint16_t CR2;
X volatile uint16_t CR2;
N uint16_t RESERVED1;
N __IO uint16_t SMCR;
X volatile uint16_t SMCR;
N uint16_t RESERVED2;
N __IO uint16_t DIER;
X volatile uint16_t DIER;
N uint16_t RESERVED3;
N __IO uint16_t SR;
X volatile uint16_t SR;
N uint16_t RESERVED4;
N __IO uint16_t EGR;
X volatile uint16_t EGR;
N uint16_t RESERVED5;
N __IO uint16_t CCMR1;
X volatile uint16_t CCMR1;
N uint16_t RESERVED6;
N __IO uint16_t CCMR2;
X volatile uint16_t CCMR2;
N uint16_t RESERVED7;
N __IO uint16_t CCER;
X volatile uint16_t CCER;
N uint16_t RESERVED8;
N __IO uint16_t CNT;
X volatile uint16_t CNT;
N uint16_t RESERVED9;
N __IO uint16_t PSC;
X volatile uint16_t PSC;
N uint16_t RESERVED10;
N __IO uint16_t ARR;
X volatile uint16_t ARR;
N uint16_t RESERVED11;
N __IO uint16_t RCR;
X volatile uint16_t RCR;
N uint16_t RESERVED12;
N __IO uint16_t CCR1;
X volatile uint16_t CCR1;
N uint16_t RESERVED13;
N __IO uint16_t CCR2;
X volatile uint16_t CCR2;
N uint16_t RESERVED14;
N __IO uint16_t CCR3;
X volatile uint16_t CCR3;
N uint16_t RESERVED15;
N __IO uint16_t CCR4;
X volatile uint16_t CCR4;
N uint16_t RESERVED16;
N __IO uint16_t BDTR;
X volatile uint16_t BDTR;
N uint16_t RESERVED17;
N __IO uint16_t DCR;
X volatile uint16_t DCR;
N uint16_t RESERVED18;
N __IO uint16_t DMAR;
X volatile uint16_t DMAR;
N uint16_t RESERVED19;
N} TIM_TypeDef;
N
N/**
N * @brief Universal Synchronous Asynchronous Receiver Transmitter
N */
N
Ntypedef struct
N{
N __IO uint16_t SR;
X volatile uint16_t SR;
N uint16_t RESERVED0;
N __IO uint16_t DR;
X volatile uint16_t DR;
N uint16_t RESERVED1;
N __IO uint16_t BRR;
X volatile uint16_t BRR;
N uint16_t RESERVED2;
N __IO uint16_t CR1;
X volatile uint16_t CR1;
N uint16_t RESERVED3;
N __IO uint16_t CR2;
X volatile uint16_t CR2;
N uint16_t RESERVED4;
N __IO uint16_t CR3;
X volatile uint16_t CR3;
N uint16_t RESERVED5;
N __IO uint16_t GTPR;
X volatile uint16_t GTPR;
N uint16_t RESERVED6;
N} USART_TypeDef;
N
N/**
N * @brief Window WATCHDOG
N */
N
Ntypedef struct
N{
N __IO uint32_t CR;
X volatile uint32_t CR;
N __IO uint32_t CFR;
X volatile uint32_t CFR;
N __IO uint32_t SR;
X volatile uint32_t SR;
N} WWDG_TypeDef;
N
N/**
N * @}
N */
N
N/** @addtogroup Peripheral_memory_map
N * @{
N */
N
N#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */
N#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */
N
N#define SRAM_BASE ((uint32_t)0x20000000) /*!< Peripheral base address in the bit-band region */
N#define PERIPH_BASE ((uint32_t)0x40000000) /*!< SRAM base address in the bit-band region */
N
N#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
N
N/*!< Peripheral memory map */
N#define APB1PERIPH_BASE PERIPH_BASE
N#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
N#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
N
N#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
N#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
N#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
N#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
N#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
N#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
N#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
N#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
N#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
N#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
N#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
N#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
N#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
N#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
N#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
N#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
N#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
N#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
N#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
N#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
N#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
N
N#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
N#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
N#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
N#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
N#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
N#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
N#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
N#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
N#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
N#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
N#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
N#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
N#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
N#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
N#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
N#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
N
N#define SDIO_BASE (PERIPH_BASE + 0x18000)
N
N#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
N#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
N#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
N#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
N#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
N#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
N#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
N#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
N#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
N#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
N#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
N#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
N#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
N#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
N#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
N#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
N
N#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
N#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
N
N#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
N#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
N#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */
N#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */
N#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
N
N#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
N
N/**
N * @}
N */
N
N/** @addtogroup Peripheral_declaration
N * @{
N */
N
N#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
N#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
N#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
N#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
N#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
N#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
N#define RTC ((RTC_TypeDef *) RTC_BASE)
N#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
N#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
N#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
N#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
N#define USART2 ((USART_TypeDef *) USART2_BASE)
N#define USART3 ((USART_TypeDef *) USART3_BASE)
N#define UART4 ((USART_TypeDef *) UART4_BASE)
N#define UART5 ((USART_TypeDef *) UART5_BASE)
N#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
N#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
N#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
N#define BKP ((BKP_TypeDef *) BKP_BASE)
N#define PWR ((PWR_TypeDef *) PWR_BASE)
N#define DAC ((DAC_TypeDef *) DAC_BASE)
N#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
N#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
N#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
N#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
N#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
N#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
N#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
N#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
N#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
N#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
N#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
N#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
N#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
N#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
N#define USART1 ((USART_TypeDef *) USART1_BASE)
N#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
N#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
N#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
N#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
N#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
N#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
N#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
N#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
N#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
N#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
N#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
N#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
N#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
N#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
N#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
N#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
N#define RCC ((RCC_TypeDef *) RCC_BASE)
N#define CRC ((CRC_TypeDef *) CRC_BASE)
N#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
N#define OB ((OB_TypeDef *) OB_BASE)
N#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
N#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
N#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
N#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
N#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
N#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
N
N/**
N * @}
N */
N
N/** @addtogroup Exported_constants
N * @{
N */
N
N/** @addtogroup Peripheral_Registers_Bits_Definition
N* @{
N*/
N
N/******************************************************************************/
N/* Peripheral Registers_Bits_Definition */
N/******************************************************************************/
N
N/******************************************************************************/
N/* */
N/* CRC calculation unit */
N/* */
N/******************************************************************************/
N
N/******************* Bit definition for CRC_DR register *********************/
N#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
N
N
N/******************* Bit definition for CRC_IDR register ********************/
N#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
N
N
N/******************** Bit definition for CRC_CR register ********************/
N#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */
N
N/******************************************************************************/
N/* */
N/* Power Control */
N/* */
N/******************************************************************************/
N
N/******************** Bit definition for PWR_CR register ********************/
N#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */
N#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
N#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
N#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
N#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
N
N#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
N#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
N#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
N#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
N
N/*!< PVD level configuration */
N#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */
N#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */
N#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */
N#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */
N#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */
N#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */
N#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */
N#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */
N
N#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
N
N
N/******************* Bit definition for PWR_CSR register ********************/
N#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
N#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
N#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
N#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */
N
N/******************************************************************************/
N/* */
N/* Backup registers */
N/* */
N/******************************************************************************/
N
N/******************* Bit definition for BKP_DR1 register ********************/
N#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR2 register ********************/
N#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR3 register ********************/
N#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR4 register ********************/
N#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR5 register ********************/
N#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR6 register ********************/
N#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR7 register ********************/
N#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR8 register ********************/
N#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR9 register ********************/
N#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR10 register *******************/
N#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR11 register *******************/
N#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR12 register *******************/
N#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR13 register *******************/
N#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR14 register *******************/
N#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR15 register *******************/
N#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR16 register *******************/
N#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR17 register *******************/
N#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/****************** Bit definition for BKP_DR18 register ********************/
N#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR19 register *******************/
N#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR20 register *******************/
N#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR21 register *******************/
N#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR22 register *******************/
N#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR23 register *******************/
N#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR24 register *******************/
N#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR25 register *******************/
N#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR26 register *******************/
N#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR27 register *******************/
N#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR28 register *******************/
N#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR29 register *******************/
N#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR30 register *******************/
N#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR31 register *******************/
N#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR32 register *******************/
N#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR33 register *******************/
N#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR34 register *******************/
N#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR35 register *******************/
N#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR36 register *******************/
N#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR37 register *******************/
N#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR38 register *******************/
N#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR39 register *******************/
N#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR40 register *******************/
N#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR41 register *******************/
N#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/******************* Bit definition for BKP_DR42 register *******************/
N#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */
N
N/****************** Bit definition for BKP_RTCCR register *******************/
N#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */
N#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */
N#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */
N#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */
N
N/******************** Bit definition for BKP_CR register ********************/
N#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */
N#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */
N
N/******************* Bit definition for BKP_CSR register ********************/
N#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */
N#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */
N#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */
N#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */
N#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */
N
N/******************************************************************************/
N/* */
N/* Reset and Clock Control */
N/* */
N/******************************************************************************/
N
N/******************** Bit definition for RCC_CR register ********************/
N#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
N#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
N#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
N#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
N#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
N#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
N#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
N#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
N#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
N#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
N
N/******************* Bit definition for RCC_CFGR register *******************/
N#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
N#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
N#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
N
N/*!< SW configuration */
N#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
N#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
N#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
N
N#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
N#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
N#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
N
N/*!< SWS configuration */
N#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
N#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
N#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
N
N#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
N#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
N#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
N#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
N#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
N
N/*!< HPRE configuration */
N#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
N#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
N#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
N#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
N#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
N#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
N#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
N#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
N#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
N
N#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
N#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
N#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
N#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
N
N/*!< PPRE1 configuration */
N#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
N#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
N#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
N#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
N#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
N
N#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
N#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
N#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
N#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
N
N/*!< PPRE2 configuration */
N#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
N#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
N#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
N#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
N#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
N
N#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */
N#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
N#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
N
N/*!< ADCPPRE configuration */
N#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
N#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
N#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
N#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
N
N#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
N#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
N
N#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
N#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
N#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
N#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
N#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
N
N/*!< PLLMUL configuration */
N#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
N#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
N#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
N#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
N#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
N#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
N#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
N#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
N#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
N#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
N#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
N#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
N#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
N#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
N#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
N
N#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */
N
N#define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
N#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
N#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
N#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
N
N/*!< MCO configuration */
N#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
N#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected */
N#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< Internal 8 MHz RC oscillator clock selected */
N#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< External 1-25 MHz oscillator clock selected */
N#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected*/
N
N/*!<****************** Bit definition for RCC_CIR register ********************/
N#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
N#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
N#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
N#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
N#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
N#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
N#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
N#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
N#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
N#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
N#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
N#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
N#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
N#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
N#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
N#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
N#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
N
N/***************** Bit definition for RCC_APB2RSTR register *****************/
N#define RCC_APB2RSTR_AFIORST ((uint16_t)0x0001) /*!< Alternate Function I/O reset */
N#define RCC_APB2RSTR_IOPARST ((uint16_t)0x0004) /*!< I/O port A reset */
N#define RCC_APB2RSTR_IOPBRST ((uint16_t)0x0008) /*!< IO port B reset */
N#define RCC_APB2RSTR_IOPCRST ((uint16_t)0x0010) /*!< IO port C reset */
N#define RCC_APB2RSTR_IOPDRST ((uint16_t)0x0020) /*!< IO port D reset */
N#define RCC_APB2RSTR_IOPERST ((uint16_t)0x0040) /*!< IO port E reset */
N#define RCC_APB2RSTR_IOPFRST ((uint16_t)0x0080) /*!< IO port F reset */
N#define RCC_APB2RSTR_IOPGRST ((uint16_t)0x0100) /*!< IO port G reset */
N#define RCC_APB2RSTR_ADC1RST ((uint16_t)0x0200) /*!< ADC 1 interface reset */
N#define RCC_APB2RSTR_ADC2RST ((uint16_t)0x0400) /*!< ADC 2 interface reset */
N#define RCC_APB2RSTR_TIM1RST ((uint16_t)0x0800) /*!< TIM1 Timer reset */
N#define RCC_APB2RSTR_SPI1RST ((uint16_t)0x1000) /*!< SPI 1 reset */
N#define RCC_APB2RSTR_TIM8RST ((uint16_t)0x2000) /*!< TIM8 Timer reset */
N#define RCC_APB2RSTR_USART1RST ((uint16_t)0x4000) /*!< USART1 reset */
N#define RCC_APB2RSTR_ADC3RST ((uint16_t)0x8000) /*!< ADC3 interface reset */
N
N/***************** Bit definition for RCC_APB1RSTR register *****************/
N#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
N#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
N#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
N#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
N#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
N#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
N#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
N#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
N#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */
N#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
N#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */
N#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< USART 4 reset */
N#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< USART 5 reset */
N#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
N#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
N#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */
N#define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN reset */
N#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */
N#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
N#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
N
N/****************** Bit definition for RCC_AHBENR register ******************/
N#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */
N#define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */
N#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */
N#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */
N#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */
N#define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */
N#define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */
N
N/****************** Bit definition for RCC_APB2ENR register *****************/
N#define RCC_APB2ENR_AFIOEN ((uint16_t)0x0001) /*!< Alternate Function I/O clock enable */
N#define RCC_APB2ENR_IOPAEN ((uint16_t)0x0004) /*!< I/O port A clock enable */
N#define RCC_APB2ENR_IOPBEN ((uint16_t)0x0008) /*!< I/O port B clock enable */
N#define RCC_APB2ENR_IOPCEN ((uint16_t)0x0010) /*!< I/O port C clock enable */
N#define RCC_APB2ENR_IOPDEN ((uint16_t)0x0020) /*!< I/O port D clock enable */
N#define RCC_APB2ENR_IOPEEN ((uint16_t)0x0040) /*!< I/O port E clock enable */
N#define RCC_APB2ENR_IOPFEN ((uint16_t)0x0080) /*!< I/O port F clock enable */
N#define RCC_APB2ENR_IOPGEN ((uint16_t)0x0100) /*!< I/O port G clock enable */
N#define RCC_APB2ENR_ADC1EN ((uint16_t)0x0200) /*!< ADC 1 interface clock enable */
N#define RCC_APB2ENR_ADC2EN ((uint16_t)0x0400) /*!< ADC 2 interface clock enable */
N#define RCC_APB2ENR_TIM1EN ((uint16_t)0x0800) /*!< TIM1 Timer clock enable */
N#define RCC_APB2ENR_SPI1EN ((uint16_t)0x1000) /*!< SPI 1 clock enable */
N#define RCC_APB2ENR_TIM8EN ((uint16_t)0x2000) /*!< TIM8 Timer clock enable */
N#define RCC_APB2ENR_USART1EN ((uint16_t)0x4000) /*!< USART1 clock enable */
N#define RCC_APB2ENR_ADC3EN ((uint16_t)0x8000) /*!< DMA1 clock enable */
N
N/***************** Bit definition for RCC_APB1ENR register ******************/
N#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
N#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
N#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
N#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
N#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
N#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
N#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
N#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
N#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */
N#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
N#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
N#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< USART 4 clock enable */
N#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< USART 5 clock enable */
N#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
N#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
N#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
N#define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
N#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */
N#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
N#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
N
N/******************* Bit definition for RCC_BDCR register *******************/
N#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
N#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
N#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
N
N#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
N#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
N#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
N
N/*!< RTC congiguration */
N#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
N#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
N#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
N#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
N
N#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
N#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
N
N/******************* Bit definition for RCC_CSR register ********************/
N#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
N#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
N#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
N#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
N#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
N#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
N#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
N#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
N#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
N
N/******************************************************************************/
N/* */
N/* General Purpose and Alternate Function IO */
N/* */
N/******************************************************************************/
N
N/******************* Bit definition for GPIO_CRL register *******************/
N#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
N
N#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
N#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
N#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
N
N#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
N#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */
N#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */
N
N#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
N#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
N#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
N
N#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
N#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */
N#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */
N
N#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
N#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
N#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
N
N#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
N#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
N#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
N
N#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
N#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */
N#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */
N
N#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
N#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */
N#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */
N
N#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
N
N#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
N#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */
N#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */
N
N#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
N#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
N#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
N
N#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
N#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */
N#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */
N
N#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
N#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */
N#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */
N
N#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
N#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */
N#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */
N
N#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
N#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */
N#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */
N
N#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
N#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */
N#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */
N
N#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
N#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */
N#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */
N
N/******************* Bit definition for GPIO_CRH register *******************/
N#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
N
N#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
N#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */
N#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */
N
N#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
N#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */
N#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */
N
N#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
N#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */
N#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */
N
N#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
N#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */
N#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */
N
N#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
N#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */
N#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */
N
N#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
N#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */
N#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */
N
N#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
N#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */
N#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */
N
N#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
N#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */
N#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */
N
N#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
N
N#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
N#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */
N#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */
N
N#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
N#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */
N#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */
N
N#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
N#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */
N#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */
N
N#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
N#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */
N#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */
N
N#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
N#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */
N#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */
N
N#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
N#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */
N#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */
N
N#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
N#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */
N#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */
N
N#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
N#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */
N#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */
N
N/*!<****************** Bit definition for GPIO_IDR register *******************/
N#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */
N#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */
N#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */
N#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */
N#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */
N#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */
N#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */
N#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */
N#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */
N#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */
N#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */
N#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */
N#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */
N#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */
N#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */
N#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */
N
N/******************* Bit definition for GPIO_ODR register *******************/
N#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */
N#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */
N#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */
N#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */
N#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */
N#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */
N#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */
N#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */
N#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */
N#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */
N#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */
N#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */
N#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */
N#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */
N#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */
N#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */
N
N/****************** Bit definition for GPIO_BSRR register *******************/
N#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */
N#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */
N#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */
N#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */
N#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */
N#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */
N#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */
N#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */
N#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */
N#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */
N#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */
N#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */
N#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */
N#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */
N#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */
N#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */
N
N#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */
N#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */
N#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */
N#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */
N#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */
N#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */
N#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */
N#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */
N#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */
N#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */
N#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */
N#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */
N#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */
N#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */
N#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */
N#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */
N
N/******************* Bit definition for GPIO_BRR register *******************/
N#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */
N#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */
N#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */
N#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */
N#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */
N#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */
N#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */
N#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */
N#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */
N#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */
N#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */
N#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */
N#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */
N#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */
N#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */
N#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */
N
N/****************** Bit definition for GPIO_LCKR register *******************/
N#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */
N#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */
N#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */
N#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */
N#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */
N#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */
N#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */
N#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */
N#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */
N#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */
N#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */
N#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */
N#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */
N#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */
N#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */
N#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */
N#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */
N
N/*----------------------------------------------------------------------------*/
N
N/****************** Bit definition for AFIO_EVCR register *******************/
N#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */
N#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */
N#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */
N#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */
N#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */
N
N/*!< PIN configuration */
N#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */
N#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */
N#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */
N#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */
N#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */
N#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */
N#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */
N#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */
N#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */
N#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */
N#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */
N#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */
N#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */
N#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */
N#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */
N#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */
N
N#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */
N#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */
N#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */
N#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */
N
N/*!< PORT configuration */
N#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */
N#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */
N#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */
N#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */
N#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */
N
N#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */
N
N/****************** Bit definition for AFIO_MAPR register *******************/
N#define AFIO_MAPR_SPI1 _REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */
N#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */
N#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */
N#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */
N
N#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
N#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */
N#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */
N
N/* USART3_REMAP configuration */
N#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
N#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
N#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
N
N#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
N#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */
N#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */
N
N/*!< TIM1_REMAP configuration */
N#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
N#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
N#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
N
N#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
N#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
N#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
N
N/*!< TIM2_REMAP configuration */
N#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
N#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
N#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
N#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
N
N#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
N#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */
N#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */
N
N/*!< TIM3_REMAP configuration */
N#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
N#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
N#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
N
N#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
N
N#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
N#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */
N#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */
N
N/*!< CAN_REMAP configuration */
N#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
N#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
N#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
N
N#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
N#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */
N#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */
N#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */
N#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */
N#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */
N
N#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
N#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */
N#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */
N#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */
N
N/*!< SWJ_CFG configuration */
N#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
N#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
N#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */
N#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */
N
N/***************** Bit definition for AFIO_EXTICR1 register *****************/
N#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
N#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
N#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
N#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
N
N/*!< EXTI0 configuration */
N#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
N#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
N#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
N#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
N#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
N#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
N#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */
N
N/*!< EXTI1 configuration */
N#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
N#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
N#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
N#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
N#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
N#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
N#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */
N
N/*!< EXTI2 configuration */
N#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
N#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
N#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
N#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
N#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
N#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
N#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */
N
N/*!< EXTI3 configuration */
N#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
N#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
N#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
N#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
N#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
N#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
N#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */
N
N/***************** Bit definition for AFIO_EXTICR2 register *****************/
N#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
N#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
N#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
N#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
N
N/*!< EXTI4 configuration */
N#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
N#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
N#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
N#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
N#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
N#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
N#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */
N
N/* EXTI5 configuration */
N#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
N#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
N#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
N#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
N#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
N#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
N#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */
N
N/*!< EXTI6 configuration */
N#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
N#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
N#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
N#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
N#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
N#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
N#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */
N
N/*!< EXTI7 configuration */
N#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
N#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
N#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
N#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
N#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
N#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
N#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */
N
N/***************** Bit definition for AFIO_EXTICR3 register *****************/
N#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
N#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
N#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
N#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
N
N/*!< EXTI8 configuration */
N#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
N#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
N#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
N#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
N#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
N#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */
N#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */
N
N/*!< EXTI9 configuration */
N#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
N#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
N#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
N#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
N#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
N#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
N#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */
N
N/*!< EXTI10 configuration */
N#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
N#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
N#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
N#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
N#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */
N#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
N#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */
N
N/*!< EXTI11 configuration */
N#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
N#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
N#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
N#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
N#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
N#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */
N#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */
N
N/***************** Bit definition for AFIO_EXTICR4 register *****************/
N#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
N#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
N#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
N#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
N
N/* EXTI12 configuration */
N#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
N#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
N#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
N#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
N#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
N#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */
N#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */
N
N/* EXTI13 configuration */
N#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
N#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
N#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
N#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
N#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
N#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */
N#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */
N
N/*!< EXTI14 configuration */
N#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
N#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
N#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
N#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
N#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
N#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */
N#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */
N
N/*!< EXTI15 configuration */
N#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
N#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
N#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
N#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
N#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
N#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
N#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */
N
N/******************************************************************************/
N/* */
N/* SystemTick */
N/* */
N/******************************************************************************/
N
N/***************** Bit definition for SysTick_CTRL register *****************/
N#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
N#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
N#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
N#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
N
N/***************** Bit definition for SysTick_LOAD register *****************/
N#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
N
N/***************** Bit definition for SysTick_VAL register ******************/
N#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
N
N/***************** Bit definition for SysTick_CALIB register ****************/
N#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
N#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
N#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
N
N/******************************************************************************/
N/* */
N/* Nested Vectored Interrupt Controller */
N/* */
N/******************************************************************************/
N
N/****************** Bit definition for NVIC_ISER register *******************/
N#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
N#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
N#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
N#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
N#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
N#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
N#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
N#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
N#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
N#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
N#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
N#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
N#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
N#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
N#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
N#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
N#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
N#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
N#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
N#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
N#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
N#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
N#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
N#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
N#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
N#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
N#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
N#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
N#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
N#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
N#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
N#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
N#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
N
N/****************** Bit definition for NVIC_ICER register *******************/
N#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
N#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
N#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
N#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
N#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
N#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
N#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
N#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
N#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
N#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
N#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
N#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
N#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
N#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
N#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
N#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
N#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
N#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
N#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
N#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
N#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
N#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
N#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
N#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
N#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
N#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
N#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
N#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
N#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
N#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
N#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
N#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
N#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
N
N/****************** Bit definition for NVIC_ISPR register *******************/
N#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
N#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
N#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
N#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
N#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
N#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
N#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
N#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
N#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
N#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
N#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
N#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
N#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
N#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
N#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
N#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
N#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
N#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
N#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
N#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
N#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
N#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
N#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
N#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
N#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
N#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
N#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
N#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
N#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
N#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
N#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
N#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
N#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
N
N/****************** Bit definition for NVIC_ICPR register *******************/
N#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
N#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
N#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
N#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
N#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
N#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
N#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
N#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
N#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
N#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
N#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
N#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
N#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
N#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
N#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
N#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
N#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
N#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
N#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
N#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
N#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
N#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
N#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
N#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
N#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
N#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
N#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
N#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
N#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
N#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
N#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
N#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
N#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
N
N/****************** Bit definition for NVIC_IABR register *******************/
N#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
N#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
N#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
N#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
N#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
N#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
N#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
N#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
N#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
N#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
N#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
N#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
N#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
N#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
N#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
N#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
N#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
N#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
N#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
N#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
N#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
N#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
N#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
N#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
N#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
N#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
N#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
N#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
N#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
N#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
N#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
N#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
N#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
N
N/****************** Bit definition for NVIC_PRI0 register *******************/
N#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
N#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
N#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
N#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
N
N/****************** Bit definition for NVIC_PRI1 register *******************/
N#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
N#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
N#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
N#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
N
N/****************** Bit definition for NVIC_PRI2 register *******************/
N#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
N#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
N#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
N#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
N
N/****************** Bit definition for NVIC_PRI3 register *******************/
N#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
N#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
N#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
N#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
N
N/****************** Bit definition for NVIC_PRI4 register *******************/
N#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
N#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
N#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
N#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
N
N/****************** Bit definition for NVIC_PRI5 register *******************/
N#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
N#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
N#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
N#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
N
N/****************** Bit definition for NVIC_PRI6 register *******************/
N#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
N#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
N#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
N#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
N
N/****************** Bit definition for NVIC_PRI7 register *******************/
N#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
N#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
N#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
N#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
N
N/****************** Bit definition for SCB_CPUID register *******************/
N#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
N#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
N#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
N#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
N#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
N
N/******************* Bit definition for SCB_ICSR register *******************/
N#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
N#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
N#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
N#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
N#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
N#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
N#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
N#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
N#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
N#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
N
N/******************* Bit definition for SCB_VTOR register *******************/
N#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
N#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
N
N/*!<***************** Bit definition for SCB_AIRCR register *******************/
N#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
N#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
N#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
N
N#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
N#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
N#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
N#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
N
N/* prority group configuration */
N#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
N#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
N#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
N#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
N#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
N#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
N#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
N#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
N
N#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
N#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
N
N/******************* Bit definition for SCB_SCR register ********************/
N#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */
N#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */
N#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */
N
N/******************** Bit definition for SCB_CCR register *******************/
N#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
N#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
N#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */
N#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */
N#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */
N#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
N
N/******************* Bit definition for SCB_SHPR register ********************/
N#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
N#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
N#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
N#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
N
N/****************** Bit definition for SCB_SHCSR register *******************/
N#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
N#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
N#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
N#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
N#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
N#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
N#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
N#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
N#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
N#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
N#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
N#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
N#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
N#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
N
N/******************* Bit definition for SCB_CFSR register *******************/
N/*!< MFSR */
N#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
N#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
N#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
N#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
N#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
N/*!< BFSR */
N#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
N#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
N#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
N#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
N#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
N#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
N/*!< UFSR */
N#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */
N#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
N#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
N#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
N#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
N#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
N
N/******************* Bit definition for SCB_HFSR register *******************/
N#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */
N#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
N#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
N
N/******************* Bit definition for SCB_DFSR register *******************/
N#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */
N#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */
N#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */
N#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */
N#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */
N
N/******************* Bit definition for SCB_MMFAR register ******************/
N#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
N
N/******************* Bit definition for SCB_BFAR register *******************/
N#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
N
N/******************* Bit definition for SCB_afsr register *******************/
N#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
N
N/******************************************************************************/
N/* */
N/* External Interrupt/Event Controller */
N/* */
N/******************************************************************************/
N
N/******************* Bit definition for EXTI_IMR register *******************/
N#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
N#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
N#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
N#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
N#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
N#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
N#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
N#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
N#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
N#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
N#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
N#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
N#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
N#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
N#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
N#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
N#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
N#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
N#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
N
N/******************* Bit definition for EXTI_EMR register *******************/
N#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
N#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
N#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
N#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
N#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
N#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
N#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
N#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
N#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
N#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
N#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
N#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
N#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
N#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
N#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
N#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
N#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
N#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
N#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
N
N/****************** Bit definition for EXTI_RTSR register *******************/
N#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
N#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
N#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
N#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
N#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
N#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
N#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
N#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
N#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
N#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
N#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
N#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
N#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
N#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
N#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
N#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
N#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
N#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
N#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
N
N/****************** Bit definition for EXTI_FTSR register *******************/
N#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
N#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
N#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
N#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
N#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
N#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
N#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
N#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
N#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
N#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
N#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
N#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
N#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
N#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
N#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
N#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
N#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
N#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
N#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
N
N/****************** Bit definition for EXTI_SWIER register ******************/
N#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
N#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
N#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
N#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
N#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
N#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
N#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
N#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
N#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
N#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
N#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
N#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
N#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
N#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
N#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
N#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
N#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
N#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
N#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
N
N/******************* Bit definition for EXTI_PR register ********************/
N#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
N#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
N#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
N#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
N#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
N#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
N#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
N#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
N#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
N#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
N#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
N#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
N#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
N#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
N#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
N#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
N#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
N#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
N#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Trigger request occurred on the external interrupt line 18 */
N
N/******************************************************************************/
N/* */
N/* DMA Controller */
N/* */
N/******************************************************************************/
N
N/******************* Bit definition for DMA_ISR register ********************/
N#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
N#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
N#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
N#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
N#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
N#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
N#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
N#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
N#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
N#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
N#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
N#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
N#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
N#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
N#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
N#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
N#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
N#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
N#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
N#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
N#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
N#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
N#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
N#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
N#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
N#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
N#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
N#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
N
N/******************* Bit definition for DMA_IFCR register *******************/
N#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */
N#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
N#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
N#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
N#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
N#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
N#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
N#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
N#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
N#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
N#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
N#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
N#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
N#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
N#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
N#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
N#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
N#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
N#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
N#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
N#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
N#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
N#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
N#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
N#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
N#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
N#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
N#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
N
N/******************* Bit definition for DMA_CCR1 register *******************/
N#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/
N#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
N#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
N#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
N#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
N#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */
N#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
N#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
N
N#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
N#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
N#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
N
N#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
N#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
N#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
N
N#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */
N#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
N#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
N
N#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
N
N/******************* Bit definition for DMA_CCR2 register *******************/
N#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */
N#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */
N#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
N#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
N#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
N#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */
N#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
N#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
N
N#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
N#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
N#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
N
N#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
N#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
N#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
N
N#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
N#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
N#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
N
N#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
N
N/******************* Bit definition for DMA_CCR3 register *******************/
N#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */
N#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
N#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
N#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
N#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
N#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */
N#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
N#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
N
N#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
N#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
N#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
N
N#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
N#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
N#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
N
N#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
N#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
N#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
N
N#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
N
N/*!<****************** Bit definition for DMA_CCR4 register *******************/
N#define DMA_CCR4_EN ((uint16_t)0x0001) /*!© COPYRIGHT 2009 STMicroelectronics
N */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F10x_CONF_H
N#define __STM32F10x_CONF_H
N
N/* Includes ------------------------------------------------------------------*/
N/* Uncomment the line below to enable peripheral header file inclusion */
N#include "stm32f10x_adc.h"
L 1 "..\src\STM32Lib\stm32f10x_adc.h" 1
N/**
N ******************************************************************************
N * @file stm32f10x_adc.h
N * @author MCD Application Team
N * @version V3.0.0
N * @date 04/06/2009
N * @brief This file contains all the functions prototypes for the ADC firmware
N * library.
N ******************************************************************************
N * @copy
N *
N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N *
N * © COPYRIGHT 2009 STMicroelectronics
N */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F10x_ADC_H
N#define __STM32F10x_ADC_H
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f10x.h"
L 1 "..\src\STM32Lib\stm32f10x.h" 1
N/**
N ******************************************************************************
N * @file stm32f10x.h
N * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
N * This file contains all the peripheral register's definitions, bits
N * definitions and memory mapping for STM32F10x High Density, Medium
N * Density and Low Density devices.
N * @author STMicroelectronics - MCD Application Team
N * @version V3.0.0
N * @date 04/06/2009
N ******************************************************************************
N *
N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N *
N * © COPYRIGHT 2009 STMicroelectronics
N ******************************************************************************
N */
N
N/** @addtogroup CMSIS
N * @{
N */
N
N/** @addtogroup stm32f10x
N * @{
N */
N
N#ifndef __STM32F10x_H
S#define __STM32F10x_H
S
S/** @addtogroup Library_configuration_section
S * @{
S */
S
S/* Uncomment the line below according to the target STM32 device used in your
S application
S */
S
S#if !defined (STM32F10X_LD) && !defined (STM32F10X_MD) && !defined (STM32F10X_HD)
S/* #define STM32F10X_LD */ /*!< STM32 Low density devices */
S#define STM32F10X_MD /*!< STM32 Medium density devices */
S/*#define STM32F10X_HD*/ /*!< STM32 High density devices */
S#endif
S/* Tip: To avoid modifying this file each time you need to switch between these
S devices, you can define the device in your toolchain compiler preprocessor.
S
S - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
S where the Flash memory density ranges between 16 and 32 Kbytes.
S - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
S where the Flash memory density ranges between 64 and 128 Kbytes.
S - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
S the Flash memory density ranges between 256 and 512 Kbytes.
S */
S
S#if !defined USE_STDPERIPH_DRIVER
S/**
S * @brief Comment the line below if you will not use the peripherals drivers.
S In this case, these drivers will not be included and the application code will
S be based on direct access to peripherals registers
S */
S#define USE_STDPERIPH_DRIVER
S#endif
S
S/**
S * @brief In the following line adjust the value of External High Speed oscillator (HSE)
S used in your application
S */
S#define HSE_Value ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
S/**
S * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
S Timeout value
S */
S#define HSEStartUp_TimeOut ((uint16_t)0x0500) /*!< Time out for HSE start up */
S
S#define HSI_Value ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
S
S
S/*!< [31:16] STM32F10x Standard Peripheral Library main version */
S#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03)
S/*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */
S#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x00)
S/*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */
S#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00)
S/*!< STM32F10x Standard Peripheral Library version number */
S#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\
S | (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\
S | __STM32F10X_STDPERIPH_VERSION_SUB2)
X#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16) | (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8) | __STM32F10X_STDPERIPH_VERSION_SUB2)
S
S/**
S * @}
S */
S
S/** @addtogroup Configuration_section_for_CMSIS
S * @{
S */
S
S/**
S * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
S */
S#define __MPU_PRESENT 0 /*!< STM32 does not provide a MPU present or not */
S#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
S#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
S
S/*!< Interrupt Number Definition */
Stypedef enum IRQn
S{
S /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
S NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
S MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
S BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
S UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
S SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
S DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
S PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
S SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
S
S /****** STM32 specific Interrupt Numbers *********************************************************/
S WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
S PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
S TAMPER_IRQn = 2, /*!< Tamper Interrupt */
S RTC_IRQn = 3, /*!< RTC global Interrupt */
S FLASH_IRQn = 4, /*!< FLASH global Interrupt */
S RCC_IRQn = 5, /*!< RCC global Interrupt */
S EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
S EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
S EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
S EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
S EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
S DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
S DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
S DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
S DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
S DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
S DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
S DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
S ADC1_2_IRQn = 18, /*!< ADC1 et ADC2 global Interrupt */
S USB_HP_CAN1_TX_IRQn = 19, /*!< USB High Priority or CAN1 TX Interrupts */
S USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Low Priority or CAN1 RX0 Interrupts */
S CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
S CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
S EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
S TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
S TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
S TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
S TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
S TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
S TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
S#ifndef STM32F10X_LD
S TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
S#endif
S I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
S I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
S#ifndef STM32F10X_LD
S I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
S I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
S#endif
S SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
S SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
S USART1_IRQn = 37, /*!< USART1 global Interrupt */
S USART2_IRQn = 38, /*!< USART2 global Interrupt */
S#ifndef STM32F10X_LD
S USART3_IRQn = 39, /*!< USART3 global Interrupt */
S#endif
S EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
S RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
S USBWakeUp_IRQn = 42, /*!< USB WakeUp from suspend through EXTI Line Interrupt */
S#ifdef STM32F10X_HD
S TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
S TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
S TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
S TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
S ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
S FSMC_IRQn = 48, /*!< FSMC global Interrupt */
S SDIO_IRQn = 49, /*!< SDIO global Interrupt */
S TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
S SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
S UART4_IRQn = 52, /*!< UART4 global Interrupt */
S UART5_IRQn = 53, /*!< UART5 global Interrupt */
S TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
S TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
S DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
S DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
S DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
S DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
S#endif
S} IRQn_Type;
S
S/**
S * @}
S */
S
S#include "core_cm3.h"
S#include "system_stm32f10x.h"
S#include
S
S/** @addtogroup Exported_types
S * @{
S */
S
S/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy prupose) */
Stypedef int32_t s32;
Stypedef int16_t s16;
Stypedef int8_t s8;
S
Stypedef const int32_t sc32; /*!< Read Only */
Stypedef const int16_t sc16; /*!< Read Only */
Stypedef const int8_t sc8; /*!< Read Only */
S
Stypedef __IO int32_t vs32;
Stypedef __IO int16_t vs16;
Stypedef __IO int8_t vs8;
S
Stypedef __I int32_t vsc32; /*!< Read Only */
Stypedef __I int16_t vsc16; /*!< Read Only */
Stypedef __I int8_t vsc8; /*!< Read Only */
S
Stypedef uint32_t u32;
Stypedef uint16_t u16;
Stypedef uint8_t u8;
S
Stypedef const uint32_t uc32; /*!< Read Only */
Stypedef const uint16_t uc16; /*!< Read Only */
Stypedef const uint8_t uc8; /*!< Read Only */
S
Stypedef __IO uint32_t vu32;
Stypedef __IO uint16_t vu16;
Stypedef __IO uint8_t vu8;
S
Stypedef __I uint32_t vuc32; /*!< Read Only */
Stypedef __I uint16_t vuc16; /*!< Read Only */
Stypedef __I uint8_t vuc8; /*!< Read Only */
S
Stypedef enum {FALSE = 0, TRUE = !FALSE} bool;
S
Stypedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
S
Stypedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
S#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
S
Stypedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
S
S/**
S * @}
S */
S
S/** @addtogroup Peripheral_registers_structures
S * @{
S */
S
S/**
S * @brief Analog to Digital Converter
S */
S
Stypedef struct
S{
S __IO uint32_t SR;
S __IO uint32_t CR1;
S __IO uint32_t CR2;
S __IO uint32_t SMPR1;
S __IO uint32_t SMPR2;
S __IO uint32_t JOFR1;
S __IO uint32_t JOFR2;
S __IO uint32_t JOFR3;
S __IO uint32_t JOFR4;
S __IO uint32_t HTR;
S __IO uint32_t LTR;
S __IO uint32_t SQR1;
S __IO uint32_t SQR2;
S __IO uint32_t SQR3;
S __IO uint32_t JSQR;
S __IO uint32_t JDR1;
S __IO uint32_t JDR2;
S __IO uint32_t JDR3;
S __IO uint32_t JDR4;
S __IO uint32_t DR;
S} ADC_TypeDef;
S
S/**
S * @brief Backup Registers
S */
S
Stypedef struct
S{
S uint32_t RESERVED0;
S __IO uint16_t DR1;
S uint16_t RESERVED1;
S __IO uint16_t DR2;
S uint16_t RESERVED2;
S __IO uint16_t DR3;
S uint16_t RESERVED3;
S __IO uint16_t DR4;
S uint16_t RESERVED4;
S __IO uint16_t DR5;
S uint16_t RESERVED5;
S __IO uint16_t DR6;
S uint16_t RESERVED6;
S __IO uint16_t DR7;
S uint16_t RESERVED7;
S __IO uint16_t DR8;
S uint16_t RESERVED8;
S __IO uint16_t DR9;
S uint16_t RESERVED9;
S __IO uint16_t DR10;
S uint16_t RESERVED10;
S __IO uint16_t RTCCR;
S uint16_t RESERVED11;
S __IO uint16_t CR;
S uint16_t RESERVED12;
S __IO uint16_t CSR;
S uint16_t RESERVED13[5];
S __IO uint16_t DR11;
S uint16_t RESERVED14;
S __IO uint16_t DR12;
S uint16_t RESERVED15;
S __IO uint16_t DR13;
S uint16_t RESERVED16;
S __IO uint16_t DR14;
S uint16_t RESERVED17;
S __IO uint16_t DR15;
S uint16_t RESERVED18;
S __IO uint16_t DR16;
S uint16_t RESERVED19;
S __IO uint16_t DR17;
S uint16_t RESERVED20;
S __IO uint16_t DR18;
S uint16_t RESERVED21;
S __IO uint16_t DR19;
S uint16_t RESERVED22;
S __IO uint16_t DR20;
S uint16_t RESERVED23;
S __IO uint16_t DR21;
S uint16_t RESERVED24;
S __IO uint16_t DR22;
S uint16_t RESERVED25;
S __IO uint16_t DR23;
S uint16_t RESERVED26;
S __IO uint16_t DR24;
S uint16_t RESERVED27;
S __IO uint16_t DR25;
S uint16_t RESERVED28;
S __IO uint16_t DR26;
S uint16_t RESERVED29;
S __IO uint16_t DR27;
S uint16_t RESERVED30;
S __IO uint16_t DR28;
S uint16_t RESERVED31;
S __IO uint16_t DR29;
S uint16_t RESERVED32;
S __IO uint16_t DR30;
S uint16_t RESERVED33;
S __IO uint16_t DR31;
S uint16_t RESERVED34;
S __IO uint16_t DR32;
S uint16_t RESERVED35;
S __IO uint16_t DR33;
S uint16_t RESERVED36;
S __IO uint16_t DR34;
S uint16_t RESERVED37;
S __IO uint16_t DR35;
S uint16_t RESERVED38;
S __IO uint16_t DR36;
S uint16_t RESERVED39;
S __IO uint16_t DR37;
S uint16_t RESERVED40;
S __IO uint16_t DR38;
S uint16_t RESERVED41;
S __IO uint16_t DR39;
S uint16_t RESERVED42;
S __IO uint16_t DR40;
S uint16_t RESERVED43;
S __IO uint16_t DR41;
S uint16_t RESERVED44;
S __IO uint16_t DR42;
S uint16_t RESERVED45;
S} BKP_TypeDef;
S
S/**
S * @brief Controller Area Network TxMailBox
S */
S
Stypedef struct
S{
S __IO uint32_t TIR;
S __IO uint32_t TDTR;
S __IO uint32_t TDLR;
S __IO uint32_t TDHR;
S} CAN_TxMailBox_TypeDef;
S
S/**
S * @brief Controller Area Network FIFOMailBox
S */
S
Stypedef struct
S{
S __IO uint32_t RIR;
S __IO uint32_t RDTR;
S __IO uint32_t RDLR;
S __IO uint32_t RDHR;
S} CAN_FIFOMailBox_TypeDef;
S
S/**
S * @brief Controller Area Network FilterRegister
S */
S
Stypedef struct
S{
S __IO uint32_t FR1;
S __IO uint32_t FR2;
S} CAN_FilterRegister_TypeDef;
S
S/**
S * @brief Controller Area Network
S */
S
Stypedef struct
S{
S __IO uint32_t MCR;
S __IO uint32_t MSR;
S __IO uint32_t TSR;
S __IO uint32_t RF0R;
S __IO uint32_t RF1R;
S __IO uint32_t IER;
S __IO uint32_t ESR;
S __IO uint32_t BTR;
S uint32_t RESERVED0[88];
S CAN_TxMailBox_TypeDef sTxMailBox[3];
S CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
S uint32_t RESERVED1[12];
S __IO uint32_t FMR;
S __IO uint32_t FM1R;
S uint32_t RESERVED2;
S __IO uint32_t FS1R;
S uint32_t RESERVED3;
S __IO uint32_t FFA1R;
S uint32_t RESERVED4;
S __IO uint32_t FA1R;
S uint32_t RESERVED5[8];
S CAN_FilterRegister_TypeDef sFilterRegister[14];
S} CAN_TypeDef;
S
S/**
S * @brief CRC calculation unit
S */
S
Stypedef struct
S{
S __IO uint32_t DR;
S __IO uint8_t IDR;
S uint8_t RESERVED0;
S uint16_t RESERVED1;
S __IO uint32_t CR;
S} CRC_TypeDef;
S
S/**
S * @brief Digital to Analog Converter
S */
S
Stypedef struct
S{
S __IO uint32_t CR;
S __IO uint32_t SWTRIGR;
S __IO uint32_t DHR12R1;
S __IO uint32_t DHR12L1;
S __IO uint32_t DHR8R1;
S __IO uint32_t DHR12R2;
S __IO uint32_t DHR12L2;
S __IO uint32_t DHR8R2;
S __IO uint32_t DHR12RD;
S __IO uint32_t DHR12LD;
S __IO uint32_t DHR8RD;
S __IO uint32_t DOR1;
S __IO uint32_t DOR2;
S} DAC_TypeDef;
S
S/**
S * @brief Debug MCU
S */
S
Stypedef struct
S{
S __IO uint32_t IDCODE;
S __IO uint32_t CR;
S} DBGMCU_TypeDef;
S
S/**
S * @brief DMA Controller
S */
S
Stypedef struct
S{
S __IO uint32_t CCR;
S __IO uint32_t CNDTR;
S __IO uint32_t CPAR;
S __IO uint32_t CMAR;
S} DMA_Channel_TypeDef;
S
Stypedef struct
S{
S __IO uint32_t ISR;
S __IO uint32_t IFCR;
S} DMA_TypeDef;
S
S/**
S * @brief External Interrupt/Event Controller
S */
S
Stypedef struct
S{
S __IO uint32_t IMR;
S __IO uint32_t EMR;
S __IO uint32_t RTSR;
S __IO uint32_t FTSR;
S __IO uint32_t SWIER;
S __IO uint32_t PR;
S} EXTI_TypeDef;
S
S/**
S * @brief FLASH Registers
S */
S
Stypedef struct
S{
S __IO uint32_t ACR;
S __IO uint32_t KEYR;
S __IO uint32_t OPTKEYR;
S __IO uint32_t SR;
S __IO uint32_t CR;
S __IO uint32_t AR;
S __IO uint32_t RESERVED;
S __IO uint32_t OBR;
S __IO uint32_t WRPR;
S} FLASH_TypeDef;
S
S/**
S * @brief Option Bytes Registers
S */
S
Stypedef struct
S{
S __IO uint16_t RDP;
S __IO uint16_t USER;
S __IO uint16_t Data0;
S __IO uint16_t Data1;
S __IO uint16_t WRP0;
S __IO uint16_t WRP1;
S __IO uint16_t WRP2;
S __IO uint16_t WRP3;
S} OB_TypeDef;
S
S/**
S * @brief Flexible Static Memory Controller
S */
S
Stypedef struct
S{
S __IO uint32_t BTCR[8];
S} FSMC_Bank1_TypeDef;
S
S/**
S * @brief Flexible Static Memory Controller Bank1E
S */
S
Stypedef struct
S{
S __IO uint32_t BWTR[7];
S} FSMC_Bank1E_TypeDef;
S
S/**
S * @brief Flexible Static Memory Controller Bank2
S */
S
Stypedef struct
S{
S __IO uint32_t PCR2;
S __IO uint32_t SR2;
S __IO uint32_t PMEM2;
S __IO uint32_t PATT2;
S uint32_t RESERVED0;
S __IO uint32_t ECCR2;
S} FSMC_Bank2_TypeDef;
S
S/**
S * @brief Flexible Static Memory Controller Bank3
S */
S
Stypedef struct
S{
S __IO uint32_t PCR3;
S __IO uint32_t SR3;
S __IO uint32_t PMEM3;
S __IO uint32_t PATT3;
S uint32_t RESERVED0;
S __IO uint32_t ECCR3;
S} FSMC_Bank3_TypeDef;
S
S/**
S * @brief Flexible Static Memory Controller Bank4
S */
S
Stypedef struct
S{
S __IO uint32_t PCR4;
S __IO uint32_t SR4;
S __IO uint32_t PMEM4;
S __IO uint32_t PATT4;
S __IO uint32_t PIO4;
S} FSMC_Bank4_TypeDef;
S
S/**
S * @brief General Purpose IO
S */
S
Stypedef struct
S{
S __IO uint32_t CRL;
S __IO uint32_t CRH;
S __IO uint32_t IDR;
S __IO uint32_t ODR;
S __IO uint32_t BSRR;
S __IO uint32_t BRR;
S __IO uint32_t LCKR;
S} GPIO_TypeDef;
S
S/**
S * @brief Alternate Function IO
S */
S
Stypedef struct
S{
S __IO uint32_t EVCR;
S __IO uint32_t MAPR;
S __IO uint32_t EXTICR[4];
S} AFIO_TypeDef;
S/**
S * @brief Inter-integrated Circuit Interface
S */
S
Stypedef struct
S{
S __IO uint16_t CR1;
S uint16_t RESERVED0;
S __IO uint16_t CR2;
S uint16_t RESERVED1;
S __IO uint16_t OAR1;
S uint16_t RESERVED2;
S __IO uint16_t OAR2;
S uint16_t RESERVED3;
S __IO uint16_t DR;
S uint16_t RESERVED4;
S __IO uint16_t SR1;
S uint16_t RESERVED5;
S __IO uint16_t SR2;
S uint16_t RESERVED6;
S __IO uint16_t CCR;
S uint16_t RESERVED7;
S __IO uint16_t TRISE;
S uint16_t RESERVED8;
S} I2C_TypeDef;
S
S/**
S * @brief Independent WATCHDOG
S */
S
Stypedef struct
S{
S __IO uint32_t KR;
S __IO uint32_t PR;
S __IO uint32_t RLR;
S __IO uint32_t SR;
S} IWDG_TypeDef;
S
S/**
S * @brief Power Control
S */
S
Stypedef struct
S{
S __IO uint32_t CR;
S __IO uint32_t CSR;
S} PWR_TypeDef;
S
S/**
S * @brief Reset and Clock Control
S */
S
Stypedef struct
S{
S __IO uint32_t CR;
S __IO uint32_t CFGR;
S __IO uint32_t CIR;
S __IO uint32_t APB2RSTR;
S __IO uint32_t APB1RSTR;
S __IO uint32_t AHBENR;
S __IO uint32_t APB2ENR;
S __IO uint32_t APB1ENR;
S __IO uint32_t BDCR;
S __IO uint32_t CSR;
S} RCC_TypeDef;
S
S/**
S * @brief Real-Time Clock
S */
S
Stypedef struct
S{
S __IO uint16_t CRH;
S uint16_t RESERVED0;
S __IO uint16_t CRL;
S uint16_t RESERVED1;
S __IO uint16_t PRLH;
S uint16_t RESERVED2;
S __IO uint16_t PRLL;
S uint16_t RESERVED3;
S __IO uint16_t DIVH;
S uint16_t RESERVED4;
S __IO uint16_t DIVL;
S uint16_t RESERVED5;
S __IO uint16_t CNTH;
S uint16_t RESERVED6;
S __IO uint16_t CNTL;
S uint16_t RESERVED7;
S __IO uint16_t ALRH;
S uint16_t RESERVED8;
S __IO uint16_t ALRL;
S uint16_t RESERVED9;
S} RTC_TypeDef;
S
S/**
S * @brief SD host Interface
S */
S
Stypedef struct
S{
S __IO uint32_t POWER;
S __IO uint32_t CLKCR;
S __IO uint32_t ARG;
S __IO uint32_t CMD;
S __I uint32_t RESPCMD;
S __I uint32_t RESP1;
S __I uint32_t RESP2;
S __I uint32_t RESP3;
S __I uint32_t RESP4;
S __IO uint32_t DTIMER;
S __IO uint32_t DLEN;
S __IO uint32_t DCTRL;
S __I uint32_t DCOUNT;
S __I uint32_t STA;
S __IO uint32_t ICR;
S __IO uint32_t MASK;
S uint32_t RESERVED0[2];
S __I uint32_t FIFOCNT;
S uint32_t RESERVED1[13];
S __IO uint32_t FIFO;
S} SDIO_TypeDef;
S
S/**
S * @brief Serial Peripheral Interface
S */
S
Stypedef struct
S{
S __IO uint16_t CR1;
S uint16_t RESERVED0;
S __IO uint16_t CR2;
S uint16_t RESERVED1;
S __IO uint16_t SR;
S uint16_t RESERVED2;
S __IO uint16_t DR;
S uint16_t RESERVED3;
S __IO uint16_t CRCPR;
S uint16_t RESERVED4;
S __IO uint16_t RXCRCR;
S uint16_t RESERVED5;
S __IO uint16_t TXCRCR;
S uint16_t RESERVED6;
S __IO uint16_t I2SCFGR;
S uint16_t RESERVED7;
S __IO uint16_t I2SPR;
S uint16_t RESERVED8;
S} SPI_TypeDef;
S
S/**
S * @brief TIM
S */
S
Stypedef struct
S{
S __IO uint16_t CR1;
S uint16_t RESERVED0;
S __IO uint16_t CR2;
S uint16_t RESERVED1;
S __IO uint16_t SMCR;
S uint16_t RESERVED2;
S __IO uint16_t DIER;
S uint16_t RESERVED3;
S __IO uint16_t SR;
S uint16_t RESERVED4;
S __IO uint16_t EGR;
S uint16_t RESERVED5;
S __IO uint16_t CCMR1;
S uint16_t RESERVED6;
S __IO uint16_t CCMR2;
S uint16_t RESERVED7;
S __IO uint16_t CCER;
S uint16_t RESERVED8;
S __IO uint16_t CNT;
S uint16_t RESERVED9;
S __IO uint16_t PSC;
S uint16_t RESERVED10;
S __IO uint16_t ARR;
S uint16_t RESERVED11;
S __IO uint16_t RCR;
S uint16_t RESERVED12;
S __IO uint16_t CCR1;
S uint16_t RESERVED13;
S __IO uint16_t CCR2;
S uint16_t RESERVED14;
S __IO uint16_t CCR3;
S uint16_t RESERVED15;
S __IO uint16_t CCR4;
S uint16_t RESERVED16;
S __IO uint16_t BDTR;
S uint16_t RESERVED17;
S __IO uint16_t DCR;
S uint16_t RESERVED18;
S __IO uint16_t DMAR;
S uint16_t RESERVED19;
S} TIM_TypeDef;
S
S/**
S * @brief Universal Synchronous Asynchronous Receiver Transmitter
S */
S
Stypedef struct
S{
S __IO uint16_t SR;
S uint16_t RESERVED0;
S __IO uint16_t DR;
S uint16_t RESERVED1;
S __IO uint16_t BRR;
S uint16_t RESERVED2;
S __IO uint16_t CR1;
S uint16_t RESERVED3;
S __IO uint16_t CR2;
S uint16_t RESERVED4;
S __IO uint16_t CR3;
S uint16_t RESERVED5;
S __IO uint16_t GTPR;
S uint16_t RESERVED6;
S} USART_TypeDef;
S
S/**
S * @brief Window WATCHDOG
S */
S
Stypedef struct
S{
S __IO uint32_t CR;
S __IO uint32_t CFR;
S __IO uint32_t SR;
S} WWDG_TypeDef;
S
S/**
S * @}
S */
S
S/** @addtogroup Peripheral_memory_map
S * @{
S */
S
S#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */
S#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */
S
S#define SRAM_BASE ((uint32_t)0x20000000) /*!< Peripheral base address in the bit-band region */
S#define PERIPH_BASE ((uint32_t)0x40000000) /*!< SRAM base address in the bit-band region */
S
S#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
S
S/*!< Peripheral memory map */
S#define APB1PERIPH_BASE PERIPH_BASE
S#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
S#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
S
S#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
S#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
S#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
S#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
S#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
S#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
S#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
S#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
S#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
S#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
S#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
S#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
S#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
S#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
S#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
S#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
S#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
S#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
S#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
S#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
S#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
S
S#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
S#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
S#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
S#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
S#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
S#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
S#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
S#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
S#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
S#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
S#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
S#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
S#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
S#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
S#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
S#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
S
S#define SDIO_BASE (PERIPH_BASE + 0x18000)
S
S#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
S#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
S#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
S#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
S#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
S#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
S#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
S#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
S#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
S#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
S#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
S#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
S#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
S#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
S#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
S#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
S
S#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
S#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
S
S#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
S#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
S#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */
S#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */
S#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
S
S#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
S
S/**
S * @}
S */
S
S/** @addtogroup Peripheral_declaration
S * @{
S */
S
S#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
S#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
S#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
S#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
S#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
S#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
S#define RTC ((RTC_TypeDef *) RTC_BASE)
S#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
S#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
S#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
S#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
S#define USART2 ((USART_TypeDef *) USART2_BASE)
S#define USART3 ((USART_TypeDef *) USART3_BASE)
S#define UART4 ((USART_TypeDef *) UART4_BASE)
S#define UART5 ((USART_TypeDef *) UART5_BASE)
S#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
S#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
S#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
S#define BKP ((BKP_TypeDef *) BKP_BASE)
S#define PWR ((PWR_TypeDef *) PWR_BASE)
S#define DAC ((DAC_TypeDef *) DAC_BASE)
S#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
S#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
S#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
S#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
S#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
S#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
S#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
S#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
S#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
S#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
S#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
S#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
S#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
S#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
S#define USART1 ((USART_TypeDef *) USART1_BASE)
S#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
S#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
S#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
S#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
S#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
S#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
S#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
S#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
S#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
S#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
S#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
S#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
S#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
S#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
S#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
S#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
S#define RCC ((RCC_TypeDef *) RCC_BASE)
S#define CRC ((CRC_TypeDef *) CRC_BASE)
S#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
S#define OB ((OB_TypeDef *) OB_BASE)
S#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
S#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
S#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
S#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
S#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
S#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
S
S/**
S * @}
S */
S
S/** @addtogroup Exported_constants
S * @{
S */
S
S/** @addtogroup Peripheral_Registers_Bits_Definition
S* @{
S*/
S
S/******************************************************************************/
S/* Peripheral Registers_Bits_Definition */
S/******************************************************************************/
S
S/******************************************************************************/
S/* */
S/* CRC calculation unit */
S/* */
S/******************************************************************************/
S
S/******************* Bit definition for CRC_DR register *********************/
S#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
S
S
S/******************* Bit definition for CRC_IDR register ********************/
S#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
S
S
S/******************** Bit definition for CRC_CR register ********************/
S#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */
S
S/******************************************************************************/
S/* */
S/* Power Control */
S/* */
S/******************************************************************************/
S
S/******************** Bit definition for PWR_CR register ********************/
S#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */
S#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
S#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
S#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
S#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
S
S#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
S#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
S#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
S#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
S
S/*!< PVD level configuration */
S#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */
S#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */
S#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */
S#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */
S#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */
S#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */
S#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */
S#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */
S
S#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
S
S
S/******************* Bit definition for PWR_CSR register ********************/
S#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
S#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
S#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
S#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */
S
S/******************************************************************************/
S/* */
S/* Backup registers */
S/* */
S/******************************************************************************/
S
S/******************* Bit definition for BKP_DR1 register ********************/
S#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR2 register ********************/
S#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR3 register ********************/
S#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR4 register ********************/
S#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR5 register ********************/
S#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR6 register ********************/
S#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR7 register ********************/
S#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR8 register ********************/
S#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR9 register ********************/
S#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR10 register *******************/
S#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR11 register *******************/
S#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR12 register *******************/
S#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR13 register *******************/
S#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR14 register *******************/
S#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR15 register *******************/
S#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR16 register *******************/
S#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR17 register *******************/
S#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/****************** Bit definition for BKP_DR18 register ********************/
S#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR19 register *******************/
S#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR20 register *******************/
S#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR21 register *******************/
S#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR22 register *******************/
S#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR23 register *******************/
S#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR24 register *******************/
S#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR25 register *******************/
S#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR26 register *******************/
S#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR27 register *******************/
S#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR28 register *******************/
S#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR29 register *******************/
S#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR30 register *******************/
S#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR31 register *******************/
S#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR32 register *******************/
S#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR33 register *******************/
S#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR34 register *******************/
S#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR35 register *******************/
S#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR36 register *******************/
S#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR37 register *******************/
S#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR38 register *******************/
S#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR39 register *******************/
S#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR40 register *******************/
S#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR41 register *******************/
S#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/******************* Bit definition for BKP_DR42 register *******************/
S#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */
S
S/****************** Bit definition for BKP_RTCCR register *******************/
S#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */
S#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */
S#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */
S#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */
S
S/******************** Bit definition for BKP_CR register ********************/
S#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */
S#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */
S
S/******************* Bit definition for BKP_CSR register ********************/
S#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */
S#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */
S#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */
S#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */
S#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */
S
S/******************************************************************************/
S/* */
S/* Reset and Clock Control */
S/* */
S/******************************************************************************/
S
S/******************** Bit definition for RCC_CR register ********************/
S#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
S#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
S#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
S#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
S#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
S#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
S#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
S#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
S#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
S#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
S
S/******************* Bit definition for RCC_CFGR register *******************/
S#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
S#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
S#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
S
S/*!< SW configuration */
S#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
S#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
S#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
S
S#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
S#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
S#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
S
S/*!< SWS configuration */
S#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
S#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
S#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
S
S#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
S#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
S#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
S#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
S#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
S
S/*!< HPRE configuration */
S#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
S#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
S#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
S#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
S#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
S#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
S#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
S#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
S#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
S
S#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
S#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
S#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
S#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
S
S/*!< PPRE1 configuration */
S#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
S#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
S#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
S#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
S#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
S
S#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
S#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
S#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
S#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
S
S/*!< PPRE2 configuration */
S#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
S#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
S#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
S#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
S#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
S
S#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */
S#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
S#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
S
S/*!< ADCPPRE configuration */
S#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
S#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
S#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
S#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
S
S#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
S#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
S
S#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
S#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
S#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
S#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
S#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
S
S/*!< PLLMUL configuration */
S#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
S#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
S#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
S#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
S#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
S#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
S#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
S#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
S#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
S#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
S#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
S#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
S#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
S#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
S#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
S
S#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */
S
S#define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
S#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
S#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
S#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
S
S/*!< MCO configuration */
S#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
S#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected */
S#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< Internal 8 MHz RC oscillator clock selected */
S#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< External 1-25 MHz oscillator clock selected */
S#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected*/
S
S/*!<****************** Bit definition for RCC_CIR register ********************/
S#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
S#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
S#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
S#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
S#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
S#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
S#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
S#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
S#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
S#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
S#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
S#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
S#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
S#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
S#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
S#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
S#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
S
S/***************** Bit definition for RCC_APB2RSTR register *****************/
S#define RCC_APB2RSTR_AFIORST ((uint16_t)0x0001) /*!< Alternate Function I/O reset */
S#define RCC_APB2RSTR_IOPARST ((uint16_t)0x0004) /*!< I/O port A reset */
S#define RCC_APB2RSTR_IOPBRST ((uint16_t)0x0008) /*!< IO port B reset */
S#define RCC_APB2RSTR_IOPCRST ((uint16_t)0x0010) /*!< IO port C reset */
S#define RCC_APB2RSTR_IOPDRST ((uint16_t)0x0020) /*!< IO port D reset */
S#define RCC_APB2RSTR_IOPERST ((uint16_t)0x0040) /*!< IO port E reset */
S#define RCC_APB2RSTR_IOPFRST ((uint16_t)0x0080) /*!< IO port F reset */
S#define RCC_APB2RSTR_IOPGRST ((uint16_t)0x0100) /*!< IO port G reset */
S#define RCC_APB2RSTR_ADC1RST ((uint16_t)0x0200) /*!< ADC 1 interface reset */
S#define RCC_APB2RSTR_ADC2RST ((uint16_t)0x0400) /*!< ADC 2 interface reset */
S#define RCC_APB2RSTR_TIM1RST ((uint16_t)0x0800) /*!< TIM1 Timer reset */
S#define RCC_APB2RSTR_SPI1RST ((uint16_t)0x1000) /*!< SPI 1 reset */
S#define RCC_APB2RSTR_TIM8RST ((uint16_t)0x2000) /*!< TIM8 Timer reset */
S#define RCC_APB2RSTR_USART1RST ((uint16_t)0x4000) /*!< USART1 reset */
S#define RCC_APB2RSTR_ADC3RST ((uint16_t)0x8000) /*!< ADC3 interface reset */
S
S/***************** Bit definition for RCC_APB1RSTR register *****************/
S#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
S#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
S#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
S#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
S#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
S#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
S#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
S#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
S#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */
S#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
S#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */
S#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< USART 4 reset */
S#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< USART 5 reset */
S#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
S#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
S#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */
S#define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN reset */
S#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */
S#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
S#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
S
S/****************** Bit definition for RCC_AHBENR register ******************/
S#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */
S#define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */
S#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */
S#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */
S#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */
S#define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */
S#define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */
S
S/****************** Bit definition for RCC_APB2ENR register *****************/
S#define RCC_APB2ENR_AFIOEN ((uint16_t)0x0001) /*!< Alternate Function I/O clock enable */
S#define RCC_APB2ENR_IOPAEN ((uint16_t)0x0004) /*!< I/O port A clock enable */
S#define RCC_APB2ENR_IOPBEN ((uint16_t)0x0008) /*!< I/O port B clock enable */
S#define RCC_APB2ENR_IOPCEN ((uint16_t)0x0010) /*!< I/O port C clock enable */
S#define RCC_APB2ENR_IOPDEN ((uint16_t)0x0020) /*!< I/O port D clock enable */
S#define RCC_APB2ENR_IOPEEN ((uint16_t)0x0040) /*!< I/O port E clock enable */
S#define RCC_APB2ENR_IOPFEN ((uint16_t)0x0080) /*!< I/O port F clock enable */
S#define RCC_APB2ENR_IOPGEN ((uint16_t)0x0100) /*!< I/O port G clock enable */
S#define RCC_APB2ENR_ADC1EN ((uint16_t)0x0200) /*!< ADC 1 interface clock enable */
S#define RCC_APB2ENR_ADC2EN ((uint16_t)0x0400) /*!< ADC 2 interface clock enable */
S#define RCC_APB2ENR_TIM1EN ((uint16_t)0x0800) /*!< TIM1 Timer clock enable */
S#define RCC_APB2ENR_SPI1EN ((uint16_t)0x1000) /*!< SPI 1 clock enable */
S#define RCC_APB2ENR_TIM8EN ((uint16_t)0x2000) /*!< TIM8 Timer clock enable */
S#define RCC_APB2ENR_USART1EN ((uint16_t)0x4000) /*!< USART1 clock enable */
S#define RCC_APB2ENR_ADC3EN ((uint16_t)0x8000) /*!< DMA1 clock enable */
S
S/***************** Bit definition for RCC_APB1ENR register ******************/
S#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
S#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
S#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
S#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
S#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
S#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
S#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
S#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
S#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */
S#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
S#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
S#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< USART 4 clock enable */
S#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< USART 5 clock enable */
S#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
S#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
S#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
S#define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
S#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */
S#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
S#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
S
S/******************* Bit definition for RCC_BDCR register *******************/
S#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
S#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
S#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
S
S#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
S#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
S#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
S
S/*!< RTC congiguration */
S#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
S#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
S#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
S#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
S
S#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
S#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
S
S/******************* Bit definition for RCC_CSR register ********************/
S#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
S#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
S#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
S#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
S#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
S#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
S#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
S#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
S#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
S
S/******************************************************************************/
S/* */
S/* General Purpose and Alternate Function IO */
S/* */
S/******************************************************************************/
S
S/******************* Bit definition for GPIO_CRL register *******************/
S#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
S
S#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
S#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
S#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
S
S#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
S#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */
S#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */
S
S#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
S#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
S#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
S
S#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
S#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */
S#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */
S
S#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
S#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
S#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
S
S#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
S#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
S#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
S
S#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
S#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */
S#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */
S
S#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
S#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */
S#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */
S
S#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
S
S#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
S#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */
S#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */
S
S#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
S#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
S#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
S
S#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
S#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */
S#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */
S
S#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
S#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */
S#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */
S
S#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
S#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */
S#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */
S
S#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
S#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */
S#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */
S
S#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
S#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */
S#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */
S
S#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
S#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */
S#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */
S
S/******************* Bit definition for GPIO_CRH register *******************/
S#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
S
S#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
S#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */
S#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */
S
S#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
S#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */
S#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */
S
S#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
S#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */
S#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */
S
S#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
S#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */
S#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */
S
S#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
S#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */
S#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */
S
S#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
S#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */
S#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */
S
S#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
S#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */
S#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */
S
S#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
S#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */
S#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */
S
S#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
S
S#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
S#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */
S#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */
S
S#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
S#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */
S#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */
S
S#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
S#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */
S#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */
S
S#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
S#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */
S#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */
S
S#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
S#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */
S#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */
S
S#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
S#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */
S#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */
S
S#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
S#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */
S#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */
S
S#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
S#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */
S#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */
S
S/*!<****************** Bit definition for GPIO_IDR register *******************/
S#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */
S#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */
S#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */
S#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */
S#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */
S#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */
S#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */
S#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */
S#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */
S#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */
S#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */
S#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */
S#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */
S#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */
S#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */
S#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */
S
S/******************* Bit definition for GPIO_ODR register *******************/
S#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */
S#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */
S#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */
S#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */
S#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */
S#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */
S#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */
S#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */
S#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */
S#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */
S#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */
S#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */
S#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */
S#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */
S#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */
S#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */
S
S/****************** Bit definition for GPIO_BSRR register *******************/
S#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */
S#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */
S#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */
S#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */
S#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */
S#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */
S#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */
S#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */
S#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */
S#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */
S#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */
S#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */
S#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */
S#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */
S#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */
S#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */
S
S#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */
S#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */
S#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */
S#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */
S#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */
S#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */
S#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */
S#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */
S#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */
S#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */
S#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */
S#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */
S#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */
S#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */
S#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */
S#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */
S
S/******************* Bit definition for GPIO_BRR register *******************/
S#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */
S#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */
S#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */
S#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */
S#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */
S#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */
S#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */
S#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */
S#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */
S#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */
S#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */
S#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */
S#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */
S#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */
S#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */
S#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */
S
S/****************** Bit definition for GPIO_LCKR register *******************/
S#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */
S#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */
S#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */
S#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */
S#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */
S#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */
S#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */
S#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */
S#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */
S#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */
S#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */
S#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */
S#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */
S#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */
S#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */
S#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */
S#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */
S
S/*----------------------------------------------------------------------------*/
S
S/****************** Bit definition for AFIO_EVCR register *******************/
S#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */
S#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */
S#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */
S#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */
S#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */
S
S/*!< PIN configuration */
S#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */
S#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */
S#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */
S#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */
S#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */
S#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */
S#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */
S#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */
S#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */
S#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */
S#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */
S#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */
S#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */
S#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */
S#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */
S#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */
S
S#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */
S#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */
S#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */
S#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */
S
S/*!< PORT configuration */
S#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */
S#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */
S#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */
S#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */
S#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */
S
S#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */
S
S/****************** Bit definition for AFIO_MAPR register *******************/
S#define AFIO_MAPR_SPI1 _REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */
S#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */
S#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */
S#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */
S
S#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
S#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */
S#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */
S
S/* USART3_REMAP configuration */
S#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
S#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
S#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
S
S#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
S#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */
S#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */
S
S/*!< TIM1_REMAP configuration */
S#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
S#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
S#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
S
S#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
S#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
S#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
S
S/*!< TIM2_REMAP configuration */
S#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
S#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
S#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
S#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
S
S#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
S#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */
S#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */
S
S/*!< TIM3_REMAP configuration */
S#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
S#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
S#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
S
S#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
S
S#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
S#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */
S#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */
S
S/*!< CAN_REMAP configuration */
S#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
S#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
S#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
S
S#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
S#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */
S#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */
S#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */
S#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */
S#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */
S
S#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
S#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */
S#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */
S#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */
S
S/*!< SWJ_CFG configuration */
S#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
S#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
S#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */
S#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */
S
S/***************** Bit definition for AFIO_EXTICR1 register *****************/
S#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
S#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
S#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
S#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
S
S/*!< EXTI0 configuration */
S#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
S#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
S#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
S#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
S#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
S#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
S#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */
S
S/*!< EXTI1 configuration */
S#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
S#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
S#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
S#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
S#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
S#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
S#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */
S
S/*!< EXTI2 configuration */
S#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
S#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
S#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
S#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
S#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
S#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
S#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */
S
S/*!< EXTI3 configuration */
S#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
S#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
S#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
S#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
S#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
S#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
S#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */
S
S/***************** Bit definition for AFIO_EXTICR2 register *****************/
S#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
S#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
S#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
S#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
S
S/*!< EXTI4 configuration */
S#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
S#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
S#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
S#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
S#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
S#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
S#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */
S
S/* EXTI5 configuration */
S#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
S#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
S#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
S#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
S#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
S#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
S#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */
S
S/*!< EXTI6 configuration */
S#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
S#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
S#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
S#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
S#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
S#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
S#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */
S
S/*!< EXTI7 configuration */
S#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
S#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
S#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
S#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
S#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
S#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
S#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */
S
S/***************** Bit definition for AFIO_EXTICR3 register *****************/
S#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
S#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
S#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
S#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
S
S/*!< EXTI8 configuration */
S#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
S#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
S#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
S#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
S#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
S#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */
S#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */
S
S/*!< EXTI9 configuration */
S#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
S#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
S#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
S#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
S#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
S#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
S#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */
S
S/*!< EXTI10 configuration */
S#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
S#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
S#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
S#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
S#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */
S#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
S#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */
S
S/*!< EXTI11 configuration */
S#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
S#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
S#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
S#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
S#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
S#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */
S#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */
S
S/***************** Bit definition for AFIO_EXTICR4 register *****************/
S#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
S#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
S#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
S#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
S
S/* EXTI12 configuration */
S#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
S#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
S#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
S#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
S#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
S#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */
S#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */
S
S/* EXTI13 configuration */
S#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
S#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
S#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
S#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
S#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
S#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */
S#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */
S
S/*!< EXTI14 configuration */
S#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
S#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
S#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
S#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
S#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
S#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */
S#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */
S
S/*!< EXTI15 configuration */
S#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
S#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
S#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
S#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
S#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
S#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
S#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */
S
S/******************************************************************************/
S/* */
S/* SystemTick */
S/* */
S/******************************************************************************/
S
S/***************** Bit definition for SysTick_CTRL register *****************/
S#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
S#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
S#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
S#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
S
S/***************** Bit definition for SysTick_LOAD register *****************/
S#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
S
S/***************** Bit definition for SysTick_VAL register ******************/
S#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
S
S/***************** Bit definition for SysTick_CALIB register ****************/
S#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
S#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
S#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
S
S/******************************************************************************/
S/* */
S/* Nested Vectored Interrupt Controller */
S/* */
S/******************************************************************************/
S
S/****************** Bit definition for NVIC_ISER register *******************/
S#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
S#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
S#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
S#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
S#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
S#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
S#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
S#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
S#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
S#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
S#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
S#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
S#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
S#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
S#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
S#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
S#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
S#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
S#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
S#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
S#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
S#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
S#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
S#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
S#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
S#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
S#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
S#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
S#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
S#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
S#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
S#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
S#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
S
S/****************** Bit definition for NVIC_ICER register *******************/
S#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
S#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
S#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
S#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
S#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
S#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
S#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
S#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
S#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
S#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
S#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
S#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
S#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
S#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
S#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
S#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
S#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
S#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
S#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
S#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
S#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
S#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
S#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
S#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
S#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
S#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
S#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
S#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
S#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
S#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
S#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
S#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
S#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
S
S/****************** Bit definition for NVIC_ISPR register *******************/
S#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
S#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
S#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
S#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
S#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
S#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
S#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
S#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
S#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
S#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
S#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
S#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
S#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
S#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
S#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
S#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
S#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
S#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
S#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
S#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
S#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
S#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
S#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
S#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
S#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
S#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
S#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
S#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
S#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
S#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
S#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
S#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
S#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
S
S/****************** Bit definition for NVIC_ICPR register *******************/
S#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
S#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
S#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
S#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
S#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
S#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
S#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
S#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
S#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
S#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
S#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
S#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
S#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
S#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
S#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
S#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
S#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
S#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
S#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
S#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
S#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
S#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
S#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
S#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
S#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
S#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
S#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
S#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
S#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
S#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
S#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
S#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
S#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
S
S/****************** Bit definition for NVIC_IABR register *******************/
S#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
S#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
S#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
S#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
S#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
S#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
S#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
S#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
S#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
S#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
S#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
S#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
S#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
S#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
S#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
S#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
S#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
S#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
S#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
S#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
S#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
S#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
S#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
S#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
S#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
S#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
S#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
S#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
S#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
S#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
S#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
S#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
S#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
S
S/****************** Bit definition for NVIC_PRI0 register *******************/
S#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
S#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
S#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
S#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
S
S/****************** Bit definition for NVIC_PRI1 register *******************/
S#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
S#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
S#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
S#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
S
S/****************** Bit definition for NVIC_PRI2 register *******************/
S#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
S#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
S#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
S#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
S
S/****************** Bit definition for NVIC_PRI3 register *******************/
S#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
S#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
S#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
S#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
S
S/****************** Bit definition for NVIC_PRI4 register *******************/
S#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
S#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
S#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
S#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
S
S/****************** Bit definition for NVIC_PRI5 register *******************/
S#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
S#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
S#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
S#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
S
S/****************** Bit definition for NVIC_PRI6 register *******************/
S#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
S#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
S#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
S#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
S
S/****************** Bit definition for NVIC_PRI7 register *******************/
S#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
S#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
S#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
S#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
S
S/****************** Bit definition for SCB_CPUID register *******************/
S#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
S#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
S#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
S#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
S#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
S
S/******************* Bit definition for SCB_ICSR register *******************/
S#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
S#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
S#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
S#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
S#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
S#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
S#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
S#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
S#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
S#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
S
S/******************* Bit definition for SCB_VTOR register *******************/
S#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
S#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
S
S/*!<***************** Bit definition for SCB_AIRCR register *******************/
S#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
S#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
S#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
S
S#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
S#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
S#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
S#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
S
S/* prority group configuration */
S#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
S#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
S#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
S#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
S#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
S#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
S#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
S#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
S
S#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
S#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
S
S/******************* Bit definition for SCB_SCR register ********************/
S#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */
S#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */
S#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */
S
S/******************** Bit definition for SCB_CCR register *******************/
S#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
S#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
S#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */
S#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */
S#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */
S#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
S
S/******************* Bit definition for SCB_SHPR register ********************/
S#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
S#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
S#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
S#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
S
S/****************** Bit definition for SCB_SHCSR register *******************/
S#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
S#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
S#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
S#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
S#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
S#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
S#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
S#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
S#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
S#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
S#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
S#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
S#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
S#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
S
S/******************* Bit definition for SCB_CFSR register *******************/
S/*!< MFSR */
S#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
S#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
S#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
S#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
S#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
S/*!< BFSR */
S#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
S#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
S#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
S#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
S#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
S#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
S/*!< UFSR */
S#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */
S#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
S#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
S#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
S#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
S#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
S
S/******************* Bit definition for SCB_HFSR register *******************/
S#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */
S#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
S#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
S
S/******************* Bit definition for SCB_DFSR register *******************/
S#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */
S#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */
S#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */
S#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */
S#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */
S
S/******************* Bit definition for SCB_MMFAR register ******************/
S#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
S
S/******************* Bit definition for SCB_BFAR register *******************/
S#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
S
S/******************* Bit definition for SCB_afsr register *******************/
S#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
S
S/******************************************************************************/
S/* */
S/* External Interrupt/Event Controller */
S/* */
S/******************************************************************************/
S
S/******************* Bit definition for EXTI_IMR register *******************/
S#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
S#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
S#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
S#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
S#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
S#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
S#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
S#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
S#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
S#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
S#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
S#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
S#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
S#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
S#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
S#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
S#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
S#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
S#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
S
S/******************* Bit definition for EXTI_EMR register *******************/
S#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
S#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
S#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
S#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
S#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
S#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
S#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
S#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
S#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
S#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
S#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
S#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
S#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
S#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
S#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
S#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
S#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
S#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
S#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
S
S/****************** Bit definition for EXTI_RTSR register *******************/
S#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
S#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
S#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
S#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
S#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
S#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
S#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
S#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
S#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
S#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
S#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
S#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
S#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
S#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
S#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
S#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
S#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
S#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
S#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
S
S/****************** Bit definition for EXTI_FTSR register *******************/
S#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
S#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
S#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
S#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
S#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
S#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
S#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
S#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
S#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
S#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
S#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
S#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
S#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
S#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
S#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
S#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
S#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
S#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
S#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
S
S/****************** Bit definition for EXTI_SWIER register ******************/
S#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
S#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
S#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
S#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
S#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
S#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
S#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
S#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
S#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
S#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
S#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
S#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
S#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
S#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
S#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
S#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
S#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
S#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
S#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
S
S/******************* Bit definition for EXTI_PR register ********************/
S#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
S#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
S#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
S#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
S#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
S#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
S#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
S#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
S#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
S#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
S#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
S#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
S#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
S#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
S#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
S#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
S#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
S#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
S#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Trigger request occurred on the external interrupt line 18 */
S
S/******************************************************************************/
S/* */
S/* DMA Controller */
S/* */
S/******************************************************************************/
S
S/******************* Bit definition for DMA_ISR register ********************/
S#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
S#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
S#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
S#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
S#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
S#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
S#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
S#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
S#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
S#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
S#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
S#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
S#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
S#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
S#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
S#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
S#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
S#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
S#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
S#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
S#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
S#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
S#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
S#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
S#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
S#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
S#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
S#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
S
S/******************* Bit definition for DMA_IFCR register *******************/
S#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */
S#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
S#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
S#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
S#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
S#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
S#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
S#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
S#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
S#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
S#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
S#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
S#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
S#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
S#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
S#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
S#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
S#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
S#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
S#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
S#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
S#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
S#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
S#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
S#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
S#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
S#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
S#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
S
S/******************* Bit definition for DMA_CCR1 register *******************/
S#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/
S#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
S#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
S#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
S#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
S#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */
S#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
S#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
S
S#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
S#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
S#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
S
S#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
S#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
S#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
S
S#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */
S#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
S#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
S
S#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
S
S/******************* Bit definition for DMA_CCR2 register *******************/
S#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */
S#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */
S#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
S#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
S#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
S#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */
S#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
S#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
S
S#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
S#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
S#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
S
S#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
S#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
S#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
S
S#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
S#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
S#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
S
S#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
S
S/******************* Bit definition for DMA_CCR3 register *******************/
S#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */
S#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
S#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
S#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
S#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
S#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */
S#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
S#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
S
S#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
S#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
S#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
S
S#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
S#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
S#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
S
S#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
S#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
S#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
S
S#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
S
S/*!<****************** Bit definition for DMA_CCR4 register *******************/
S#define DMA_CCR4_EN ((uint16_t)0x0001) /*!= 0x1) && ((LENGTH) <= 0x4))
N
N/**
N * @}
N */
N
N/** @defgroup ADC_injected_rank
N * @{
N */
N
N#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
N
N/**
N * @}
N */
N
N
N/** @defgroup ADC_regular_length
N * @{
N */
N
N#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
N/**
N * @}
N */
N
N/** @defgroup ADC_regular_rank
N * @{
N */
N
N#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
N
N/**
N * @}
N */
N
N/** @defgroup ADC_regular_discontinuous_mode_number
N * @{
N */
N
N#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
N
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/** @defgroup ADC_Exported_Macros
N * @{
N */
N
N/**
N * @}
N */
N
N/** @defgroup ADC_Exported_Functions
N * @{
N */
N
Nvoid ADC_DeInit(ADC_TypeDef *ADCx);
Nvoid ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct);
Nvoid ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct);
Nvoid ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState);
Nvoid ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState);
Nvoid ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState);
Nvoid ADC_ResetCalibration(ADC_TypeDef *ADCx);
NFlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx);
Nvoid ADC_StartCalibration(ADC_TypeDef *ADCx);
NFlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx);
Nvoid ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
NFlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx);
Nvoid ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number);
Nvoid ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
Nvoid ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
Nvoid ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
Nuint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx);
Nuint32_t ADC_GetDualModeConversionValue(void);
Nvoid ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
Nvoid ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
Nvoid ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv);
Nvoid ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
Nvoid ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
NFlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx);
Nvoid ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
Nvoid ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length);
Nvoid ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
Nuint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel);
Nvoid ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog);
Nvoid ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
Nvoid ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel);
Nvoid ADC_TempSensorVrefintCmd(FunctionalState NewState);
NFlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG);
Nvoid ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG);
NITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT);
Nvoid ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT);
N
N#endif /*__STM32F10x_ADC_H */
N
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
L 28 "..\src\STM32Lib\stm32f10x_conf.h" 2
N// #include "stm32f10x_bkp.h"
N// #include "stm32f10x_can.h"
N// #include "stm32f10x_crc.h"
N#include "stm32f10x_dac.h"
L 1 "..\src\STM32Lib\stm32f10x_dac.h" 1
N/**
N ******************************************************************************
N * @file stm32f10x_dac.h
N * @author MCD Application Team
N * @version V3.0.0
N * @date 04/06/2009
N * @brief This file contains all the functions prototypes for the DAC firmware
N * library.
N ******************************************************************************
N * @copy
N *
N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N *
N * © COPYRIGHT 2009 STMicroelectronics
N */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F10x_DAC_H
N#define __STM32F10x_DAC_H
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f10x.h"
N
N/** @addtogroup StdPeriph_Driver
N * @{
N */
N
N/** @addtogroup DAC
N * @{
N */
N
N/** @defgroup DAC_Exported_Types
N * @{
N */
N
N/**
N * @brief DAC Init structure definition
N */
N
Ntypedef struct
N{
N uint32_t DAC_Trigger;
N uint32_t DAC_WaveGeneration;
N uint32_t DAC_LFSRUnmask_TriangleAmplitude;
N uint32_t DAC_OutputBuffer;
N} DAC_InitTypeDef;
N
N/**
N * @}
N */
N
N/** @defgroup DAC_Exported_Constants
N * @{
N */
N
N/** @defgroup DAC_trigger_selection
N * @{
N */
N
N#define DAC_Trigger_None ((uint32_t)0x00000000)
N#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004)
N#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C)
N#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014)
N#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C)
N#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024)
N#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C)
N#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034)
N#define DAC_Trigger_Software ((uint32_t)0x0000003C)
N
N#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
N ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
N ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
N ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
N ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
N ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
N ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
N ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
N ((TRIGGER) == DAC_Trigger_Software))
X#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || ((TRIGGER) == DAC_Trigger_T6_TRGO) || ((TRIGGER) == DAC_Trigger_T8_TRGO) || ((TRIGGER) == DAC_Trigger_T7_TRGO) || ((TRIGGER) == DAC_Trigger_T5_TRGO) || ((TRIGGER) == DAC_Trigger_T2_TRGO) || ((TRIGGER) == DAC_Trigger_T4_TRGO) || ((TRIGGER) == DAC_Trigger_Ext_IT9) || ((TRIGGER) == DAC_Trigger_Software))
N
N/**
N * @}
N */
N
N/** @defgroup DAC_wave_generation
N * @{
N */
N
N#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
N#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
N#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
N#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
N ((WAVE) == DAC_WaveGeneration_Noise) || \
N ((WAVE) == DAC_WaveGeneration_Triangle))
X#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || ((WAVE) == DAC_WaveGeneration_Noise) || ((WAVE) == DAC_WaveGeneration_Triangle))
N/**
N * @}
N */
N
N/** @defgroup DAC_noise_wave_generation_mask_triangle_wave_generation_max_amplitude
N * @{
N */
N
N#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000)
N#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100)
N#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200)
N#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300)
N#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400)
N#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500)
N#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600)
N#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700)
N#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800)
N#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900)
N#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00)
N#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00)
N#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000)
N#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100)
N#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200)
N#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300)
N#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400)
N#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500)
N#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600)
N#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700)
N#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800)
N#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900)
N#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00)
N#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00)
N
N#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
N ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
N ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
N ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
N ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
N ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
N ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
N ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
N ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
N ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
N ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
N ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
N ((VALUE) == DAC_TriangleAmplitude_1) || \
N ((VALUE) == DAC_TriangleAmplitude_3) || \
N ((VALUE) == DAC_TriangleAmplitude_7) || \
N ((VALUE) == DAC_TriangleAmplitude_15) || \
N ((VALUE) == DAC_TriangleAmplitude_31) || \
N ((VALUE) == DAC_TriangleAmplitude_63) || \
N ((VALUE) == DAC_TriangleAmplitude_127) || \
N ((VALUE) == DAC_TriangleAmplitude_255) || \
N ((VALUE) == DAC_TriangleAmplitude_511) || \
N ((VALUE) == DAC_TriangleAmplitude_1023) || \
N ((VALUE) == DAC_TriangleAmplitude_2047) || \
N ((VALUE) == DAC_TriangleAmplitude_4095))
X#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || ((VALUE) == DAC_LFSRUnmask_Bits1_0) || ((VALUE) == DAC_LFSRUnmask_Bits2_0) || ((VALUE) == DAC_LFSRUnmask_Bits3_0) || ((VALUE) == DAC_LFSRUnmask_Bits4_0) || ((VALUE) == DAC_LFSRUnmask_Bits5_0) || ((VALUE) == DAC_LFSRUnmask_Bits6_0) || ((VALUE) == DAC_LFSRUnmask_Bits7_0) || ((VALUE) == DAC_LFSRUnmask_Bits8_0) || ((VALUE) == DAC_LFSRUnmask_Bits9_0) || ((VALUE) == DAC_LFSRUnmask_Bits10_0) || ((VALUE) == DAC_LFSRUnmask_Bits11_0) || ((VALUE) == DAC_TriangleAmplitude_1) || ((VALUE) == DAC_TriangleAmplitude_3) || ((VALUE) == DAC_TriangleAmplitude_7) || ((VALUE) == DAC_TriangleAmplitude_15) || ((VALUE) == DAC_TriangleAmplitude_31) || ((VALUE) == DAC_TriangleAmplitude_63) || ((VALUE) == DAC_TriangleAmplitude_127) || ((VALUE) == DAC_TriangleAmplitude_255) || ((VALUE) == DAC_TriangleAmplitude_511) || ((VALUE) == DAC_TriangleAmplitude_1023) || ((VALUE) == DAC_TriangleAmplitude_2047) || ((VALUE) == DAC_TriangleAmplitude_4095))
N/**
N * @}
N */
N
N/** @defgroup DAC_output_buffer
N * @{
N */
N
N#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
N#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
N#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
N ((STATE) == DAC_OutputBuffer_Disable))
X#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || ((STATE) == DAC_OutputBuffer_Disable))
N/**
N * @}
N */
N
N/** @defgroup DAC_Channel_selection
N * @{
N */
N
N#define DAC_Channel_1 ((uint32_t)0x00000000)
N#define DAC_Channel_2 ((uint32_t)0x00000010)
N#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
N ((CHANNEL) == DAC_Channel_2))
X#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || ((CHANNEL) == DAC_Channel_2))
N/**
N * @}
N */
N
N/** @defgroup DAC_data_alignement
N * @{
N */
N
N#define DAC_Align_12b_R ((uint32_t)0x00000000)
N#define DAC_Align_12b_L ((uint32_t)0x00000004)
N#define DAC_Align_8b_R ((uint32_t)0x00000008)
N#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
N ((ALIGN) == DAC_Align_12b_L) || \
N ((ALIGN) == DAC_Align_8b_R))
X#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || ((ALIGN) == DAC_Align_12b_L) || ((ALIGN) == DAC_Align_8b_R))
N/**
N * @}
N */
N
N/** @defgroup DAC_wave_generation
N * @{
N */
N
N#define DAC_Wave_Noise ((uint32_t)0x00000040)
N#define DAC_Wave_Triangle ((uint32_t)0x00000080)
N#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
N ((WAVE) == DAC_Wave_Triangle))
X#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || ((WAVE) == DAC_Wave_Triangle))
N/**
N * @}
N */
N
N/** @defgroup DAC_data
N * @{
N */
N
N#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/** @defgroup DAC_Exported_Macros
N * @{
N */
N
N/**
N * @}
N */
N
N/** @defgroup DAC_Exported_Functions
N * @{
N */
N
Nvoid DAC_DeInit(void);
Nvoid DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct);
Nvoid DAC_StructInit(DAC_InitTypeDef *DAC_InitStruct);
Nvoid DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
Nvoid DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
Nvoid DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
Nvoid DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
Nvoid DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
Nvoid DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
Nvoid DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
Nvoid DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
Nuint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
N
N#endif /*__STM32F10x_DAC_H */
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
L 32 "..\src\STM32Lib\stm32f10x_conf.h" 2
N// #include "stm32f10x_dbgmcu.h"
N#include "stm32f10x_dma.h"
L 1 "..\src\STM32Lib\stm32f10x_dma.h" 1
N/**
N ******************************************************************************
N * @file stm32f10x_dma.h
N * @author MCD Application Team
N * @version V3.0.0
N * @date 04/06/2009
N * @brief This file contains all the functions prototypes for the DMA firmware
N * library.
N ******************************************************************************
N * @copy
N *
N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N *
N * © COPYRIGHT 2009 STMicroelectronics
N */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F10x_DMA_H
N#define __STM32F10x_DMA_H
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f10x.h"
N
N/** @addtogroup StdPeriph_Driver
N * @{
N */
N
N/** @addtogroup DMA
N * @{
N */
N
N/** @defgroup DMA_Exported_Types
N * @{
N */
N
N/**
N * @brief DMA Init structure definition
N */
N
Ntypedef struct
N{
N uint32_t DMA_PeripheralBaseAddr;
N uint32_t DMA_MemoryBaseAddr;
N uint32_t DMA_DIR;
N uint32_t DMA_BufferSize;
N uint32_t DMA_PeripheralInc;
N uint32_t DMA_MemoryInc;
N uint32_t DMA_PeripheralDataSize;
N uint32_t DMA_MemoryDataSize;
N uint32_t DMA_Mode;
N uint32_t DMA_Priority;
N uint32_t DMA_M2M;
N} DMA_InitTypeDef;
N
N/**
N * @}
N */
N
N/** @defgroup DMA_Exported_Constants
N * @{
N */
N
N#define IS_DMA_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == DMA1_Channel1_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == DMA1_Channel2_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == DMA1_Channel3_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == DMA1_Channel4_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == DMA1_Channel5_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == DMA1_Channel6_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == DMA1_Channel7_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == DMA2_Channel1_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == DMA2_Channel2_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == DMA2_Channel3_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == DMA2_Channel4_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == DMA2_Channel5_BASE))
X#define IS_DMA_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == DMA1_Channel1_BASE) || ((*(uint32_t*)&(PERIPH)) == DMA1_Channel2_BASE) || ((*(uint32_t*)&(PERIPH)) == DMA1_Channel3_BASE) || ((*(uint32_t*)&(PERIPH)) == DMA1_Channel4_BASE) || ((*(uint32_t*)&(PERIPH)) == DMA1_Channel5_BASE) || ((*(uint32_t*)&(PERIPH)) == DMA1_Channel6_BASE) || ((*(uint32_t*)&(PERIPH)) == DMA1_Channel7_BASE) || ((*(uint32_t*)&(PERIPH)) == DMA2_Channel1_BASE) || ((*(uint32_t*)&(PERIPH)) == DMA2_Channel2_BASE) || ((*(uint32_t*)&(PERIPH)) == DMA2_Channel3_BASE) || ((*(uint32_t*)&(PERIPH)) == DMA2_Channel4_BASE) || ((*(uint32_t*)&(PERIPH)) == DMA2_Channel5_BASE))
N
N/** @defgroup DMA_data_transfer_direction
N * @{
N */
N
N#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
N#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
N#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
N ((DIR) == DMA_DIR_PeripheralSRC))
X#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || ((DIR) == DMA_DIR_PeripheralSRC))
N/**
N * @}
N */
N
N/** @defgroup DMA_peripheral_incremented_mode
N * @{
N */
N
N#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
N#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
N#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
N ((STATE) == DMA_PeripheralInc_Disable))
X#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || ((STATE) == DMA_PeripheralInc_Disable))
N/**
N * @}
N */
N
N/** @defgroup DMA_memory_incremented_mode
N * @{
N */
N
N#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
N#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
N#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
N ((STATE) == DMA_MemoryInc_Disable))
X#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || ((STATE) == DMA_MemoryInc_Disable))
N/**
N * @}
N */
N
N/** @defgroup DMA_peripheral_data_size
N * @{
N */
N
N#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
N#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
N#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
N#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
N ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
N ((SIZE) == DMA_PeripheralDataSize_Word))
X#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || ((SIZE) == DMA_PeripheralDataSize_HalfWord) || ((SIZE) == DMA_PeripheralDataSize_Word))
N/**
N * @}
N */
N
N/** @defgroup DMA_memory_data_size
N * @{
N */
N
N#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
N#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
N#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
N#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
N ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
N ((SIZE) == DMA_MemoryDataSize_Word))
X#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || ((SIZE) == DMA_MemoryDataSize_HalfWord) || ((SIZE) == DMA_MemoryDataSize_Word))
N/**
N * @}
N */
N
N/** @defgroup DMA_circular_normal_mode
N * @{
N */
N
N#define DMA_Mode_Circular ((uint32_t)0x00000020)
N#define DMA_Mode_Normal ((uint32_t)0x00000000)
N#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
N/**
N * @}
N */
N
N/** @defgroup DMA_priority_level
N * @{
N */
N
N#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
N#define DMA_Priority_High ((uint32_t)0x00002000)
N#define DMA_Priority_Medium ((uint32_t)0x00001000)
N#define DMA_Priority_Low ((uint32_t)0x00000000)
N#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
N ((PRIORITY) == DMA_Priority_High) || \
N ((PRIORITY) == DMA_Priority_Medium) || \
N ((PRIORITY) == DMA_Priority_Low))
X#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || ((PRIORITY) == DMA_Priority_High) || ((PRIORITY) == DMA_Priority_Medium) || ((PRIORITY) == DMA_Priority_Low))
N/**
N * @}
N */
N
N/** @defgroup DMA_memory_to_memory
N * @{
N */
N
N#define DMA_M2M_Enable ((uint32_t)0x00004000)
N#define DMA_M2M_Disable ((uint32_t)0x00000000)
N#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
N
N/**
N * @}
N */
N
N/** @defgroup DMA_interrupts_definition
N * @{
N */
N
N#define DMA_IT_TC ((uint32_t)0x00000002)
N#define DMA_IT_HT ((uint32_t)0x00000004)
N#define DMA_IT_TE ((uint32_t)0x00000008)
N#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
N
N/**
N * @brief For DMA1
N */
N
N#define DMA1_IT_GL1 ((uint32_t)0x00000001)
N#define DMA1_IT_TC1 ((uint32_t)0x00000002)
N#define DMA1_IT_HT1 ((uint32_t)0x00000004)
N#define DMA1_IT_TE1 ((uint32_t)0x00000008)
N#define DMA1_IT_GL2 ((uint32_t)0x00000010)
N#define DMA1_IT_TC2 ((uint32_t)0x00000020)
N#define DMA1_IT_HT2 ((uint32_t)0x00000040)
N#define DMA1_IT_TE2 ((uint32_t)0x00000080)
N#define DMA1_IT_GL3 ((uint32_t)0x00000100)
N#define DMA1_IT_TC3 ((uint32_t)0x00000200)
N#define DMA1_IT_HT3 ((uint32_t)0x00000400)
N#define DMA1_IT_TE3 ((uint32_t)0x00000800)
N#define DMA1_IT_GL4 ((uint32_t)0x00001000)
N#define DMA1_IT_TC4 ((uint32_t)0x00002000)
N#define DMA1_IT_HT4 ((uint32_t)0x00004000)
N#define DMA1_IT_TE4 ((uint32_t)0x00008000)
N#define DMA1_IT_GL5 ((uint32_t)0x00010000)
N#define DMA1_IT_TC5 ((uint32_t)0x00020000)
N#define DMA1_IT_HT5 ((uint32_t)0x00040000)
N#define DMA1_IT_TE5 ((uint32_t)0x00080000)
N#define DMA1_IT_GL6 ((uint32_t)0x00100000)
N#define DMA1_IT_TC6 ((uint32_t)0x00200000)
N#define DMA1_IT_HT6 ((uint32_t)0x00400000)
N#define DMA1_IT_TE6 ((uint32_t)0x00800000)
N#define DMA1_IT_GL7 ((uint32_t)0x01000000)
N#define DMA1_IT_TC7 ((uint32_t)0x02000000)
N#define DMA1_IT_HT7 ((uint32_t)0x04000000)
N#define DMA1_IT_TE7 ((uint32_t)0x08000000)
N
N/**
N * @brief For DMA2
N */
N
N#define DMA2_IT_GL1 ((uint32_t)0x10000001)
N#define DMA2_IT_TC1 ((uint32_t)0x10000002)
N#define DMA2_IT_HT1 ((uint32_t)0x10000004)
N#define DMA2_IT_TE1 ((uint32_t)0x10000008)
N#define DMA2_IT_GL2 ((uint32_t)0x10000010)
N#define DMA2_IT_TC2 ((uint32_t)0x10000020)
N#define DMA2_IT_HT2 ((uint32_t)0x10000040)
N#define DMA2_IT_TE2 ((uint32_t)0x10000080)
N#define DMA2_IT_GL3 ((uint32_t)0x10000100)
N#define DMA2_IT_TC3 ((uint32_t)0x10000200)
N#define DMA2_IT_HT3 ((uint32_t)0x10000400)
N#define DMA2_IT_TE3 ((uint32_t)0x10000800)
N#define DMA2_IT_GL4 ((uint32_t)0x10001000)
N#define DMA2_IT_TC4 ((uint32_t)0x10002000)
N#define DMA2_IT_HT4 ((uint32_t)0x10004000)
N#define DMA2_IT_TE4 ((uint32_t)0x10008000)
N#define DMA2_IT_GL5 ((uint32_t)0x10010000)
N#define DMA2_IT_TC5 ((uint32_t)0x10020000)
N#define DMA2_IT_HT5 ((uint32_t)0x10040000)
N#define DMA2_IT_TE5 ((uint32_t)0x10080000)
N
N#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
N
N#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
N ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
N ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
N ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
N ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
N ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
N ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
N ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
N ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
N ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
N ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
N ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
N ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
N ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
N ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
N ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
N ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
N ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
N ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
N ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
N ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
N ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
N ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
N ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
X#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
N
N/**
N * @}
N */
N
N/** @defgroup DMA_flags_definition
N * @{
N */
N
N/**
N * @brief For DMA1
N */
N
N#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
N#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
N#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
N#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
N#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
N#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
N#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
N#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
N#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
N#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
N#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
N#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
N#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
N#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
N#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
N#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
N#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
N#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
N#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
N#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
N#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
N#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
N#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
N#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
N#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
N#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
N#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
N#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
N
N/**
N * @brief For DMA2
N */
N
N#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
N#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
N#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
N#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
N#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
N#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
N#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
N#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
N#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
N#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
N#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
N#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
N#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
N#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
N#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
N#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
N#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
N#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
N#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
N#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
N
N#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
N
N#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
N ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
N ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
N ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
N ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
N ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
N ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
N ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
N ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
N ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
N ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
N ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
N ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
N ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
N ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
N ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
N ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
N ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
N ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
N ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
N ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
N ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
N ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
N ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
X#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
N/**
N * @}
N */
N
N/** @defgroup DMA_Buffer_Size
N * @{
N */
N
N#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
N
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/** @defgroup DMA_Exported_Macros
N * @{
N */
N
N/**
N * @}
N */
N
N/** @defgroup DMA_Exported_Functions
N * @{
N */
N
Nvoid DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx);
Nvoid DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct);
Nvoid DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct);
Nvoid DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState);
Nvoid DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
Nuint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx);
NFlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
Nvoid DMA_ClearFlag(uint32_t DMA_FLAG);
NITStatus DMA_GetITStatus(uint32_t DMA_IT);
Nvoid DMA_ClearITPendingBit(uint32_t DMA_IT);
N
N#endif /*__STM32F10x_DMA_H */
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
L 34 "..\src\STM32Lib\stm32f10x_conf.h" 2
N#include "stm32f10x_exti.h"
L 1 "..\src\STM32Lib\stm32f10x_exti.h" 1
N/**
N ******************************************************************************
N * @file stm32f10x_exti.h
N * @author MCD Application Team
N * @version V3.0.0
N * @date 04/06/2009
N * @brief This file contains all the functions prototypes for the EXTI
N * firmware library.
N ******************************************************************************
N * @copy
N *
N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N *
N * © COPYRIGHT 2009 STMicroelectronics
N */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F10x_EXTI_H
S#define __STM32F10x_EXTI_H
S
S/* Includes ------------------------------------------------------------------*/
S#include "stm32f10x.h"
S
S/** @addtogroup StdPeriph_Driver
S * @{
S */
S
S/** @addtogroup EXTI
S * @{
S */
S
S/** @defgroup EXTI_Exported_Types
S * @{
S */
S
S/**
S * @brief EXTI mode enumeration
S */
S
Stypedef enum
S{
S EXTI_Mode_Interrupt = 0x00,
S EXTI_Mode_Event = 0x04
S} EXTIMode_TypeDef;
S
S#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
S
S/**
S * @brief EXTI Trigger enumeration
S */
S
Stypedef enum
S{
S EXTI_Trigger_Rising = 0x08,
S EXTI_Trigger_Falling = 0x0C,
S EXTI_Trigger_Rising_Falling = 0x10
S} EXTITrigger_TypeDef;
S
S#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
S ((TRIGGER) == EXTI_Trigger_Falling) || \
S ((TRIGGER) == EXTI_Trigger_Rising_Falling))
X#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || ((TRIGGER) == EXTI_Trigger_Falling) || ((TRIGGER) == EXTI_Trigger_Rising_Falling))
S/**
S * @brief EXTI Init Structure definition
S */
S
Stypedef struct
S{
S uint32_t EXTI_Line;
S EXTIMode_TypeDef EXTI_Mode;
S EXTITrigger_TypeDef EXTI_Trigger;
S FunctionalState EXTI_LineCmd;
S} EXTI_InitTypeDef;
S
S/**
S * @}
S */
S
S/** @defgroup EXTI_Exported_Constants
S * @{
S */
S
S/** @defgroup EXTI_Lines
S * @{
S */
S
S#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */
S#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */
S#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */
S#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */
S#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */
S#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */
S#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */
S#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */
S#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */
S#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */
S#define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */
S#define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */
S#define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */
S#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */
S#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */
S#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */
S#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16
S Connected to the PVD Output */
S#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17
S Connected to the RTC Alarm event */
S#define EXTI_Line18 ((uint32_t)0x40000) /* External interrupt line 18
S Connected to the USB Wakeup from
S suspend event */
S
S#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF80000) == 0x00) && ((LINE) != (uint16_t)0x00))
S
S#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
S ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
S ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
S ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
S ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
S ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
S ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
S ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
S ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
S ((LINE) == EXTI_Line18))
X#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || ((LINE) == EXTI_Line18))
S
S/**
S * @}
S */
S
S/**
S * @}
S */
S
S/** @defgroup EXTI_Exported_Macros
S * @{
S */
S
S/**
S * @}
S */
S
S/** @defgroup EXTI_Exported_Functions
S * @{
S */
S
Svoid EXTI_DeInit(void);
Svoid EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct);
Svoid EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct);
Svoid EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
SFlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
Svoid EXTI_ClearFlag(uint32_t EXTI_Line);
SITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
Svoid EXTI_ClearITPendingBit(uint32_t EXTI_Line);
S
N#endif /* __STM32F10x_EXTI_H */
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
L 35 "..\src\STM32Lib\stm32f10x_conf.h" 2
N// #include "stm32f10x_flash.h"
N#include "stm32f10x_fsmc.h"
L 1 "..\src\STM32Lib\stm32f10x_fsmc.h" 1
N/**
N ******************************************************************************
N * @file stm32f10x_fsmc.h
N * @author MCD Application Team
N * @version V3.0.0
N * @date 04/06/2009
N * @brief This file contains all the functions prototypes for the FSMC
N * firmware library.
N ******************************************************************************
N * @copy
N *
N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N *
N * © COPYRIGHT 2009 STMicroelectronics
N */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F10x_FSMC_H
N#define __STM32F10x_FSMC_H
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f10x.h"
N
N/** @addtogroup StdPeriph_Driver
N * @{
N */
N
N/** @addtogroup FSMC
N * @{
N */
N
N/** @defgroup FSMC_Exported_Types
N * @{
N */
N
N/**
N * @brief Timing parameters For NOR/SRAM Banks
N */
N
Ntypedef struct
N{
N uint32_t FSMC_AddressSetupTime;
N uint32_t FSMC_AddressHoldTime;
N uint32_t FSMC_DataSetupTime;
N uint32_t FSMC_BusTurnAroundDuration;
N uint32_t FSMC_CLKDivision;
N uint32_t FSMC_DataLatency;
N uint32_t FSMC_AccessMode;
N} FSMC_NORSRAMTimingInitTypeDef;
N
N/**
N * @brief FSMC NOR/SRAM Init structure definition
N */
N
Ntypedef struct
N{
N uint32_t FSMC_Bank;
N uint32_t FSMC_DataAddressMux;
N uint32_t FSMC_MemoryType;
N uint32_t FSMC_MemoryDataWidth;
N uint32_t FSMC_BurstAccessMode;
N uint32_t FSMC_WaitSignalPolarity;
N uint32_t FSMC_WrapMode;
N uint32_t FSMC_WaitSignalActive;
N uint32_t FSMC_WriteOperation;
N uint32_t FSMC_WaitSignal;
N uint32_t FSMC_ExtendedMode;
N uint32_t FSMC_WriteBurst;
N FSMC_NORSRAMTimingInitTypeDef *FSMC_ReadWriteTimingStruct;/* Timing Parameters for write and read access if the ExtendedMode is not used*/
N FSMC_NORSRAMTimingInitTypeDef *FSMC_WriteTimingStruct;/* Timing Parameters for write access if the ExtendedMode is used*/
N} FSMC_NORSRAMInitTypeDef;
N
N/**
N * @brief Timing parameters For FSMC NAND and PCCARD Banks
N */
N
Ntypedef struct
N{
N uint32_t FSMC_SetupTime;
N uint32_t FSMC_WaitSetupTime;
N uint32_t FSMC_HoldSetupTime;
N uint32_t FSMC_HiZSetupTime;
N} FSMC_NAND_PCCARDTimingInitTypeDef;
N
N/**
N * @brief FSMC NAND Init structure definition
N */
N
Ntypedef struct
N{
N uint32_t FSMC_Bank;
N uint32_t FSMC_Waitfeature;
N uint32_t FSMC_MemoryDataWidth;
N uint32_t FSMC_ECC;
N uint32_t FSMC_ECCPageSize;
N uint32_t FSMC_TCLRSetupTime;
N uint32_t FSMC_TARSetupTime;
N FSMC_NAND_PCCARDTimingInitTypeDef *FSMC_CommonSpaceTimingStruct;/* FSMC Common Space Timing */
N FSMC_NAND_PCCARDTimingInitTypeDef *FSMC_AttributeSpaceTimingStruct;/* FSMC Attribute Space Timing */
N} FSMC_NANDInitTypeDef;
N
N/**
N * @brief FSMC PCCARD Init structure definition
N */
N
Ntypedef struct
N{
N uint32_t FSMC_Waitfeature;
N uint32_t FSMC_TCLRSetupTime;
N uint32_t FSMC_TARSetupTime;
N FSMC_NAND_PCCARDTimingInitTypeDef *FSMC_CommonSpaceTimingStruct;/* FSMC Common Space Timing */
N FSMC_NAND_PCCARDTimingInitTypeDef *FSMC_AttributeSpaceTimingStruct; /* FSMC Attribute Space Timing */
N FSMC_NAND_PCCARDTimingInitTypeDef *FSMC_IOSpaceTimingStruct; /* FSMC IO Space Timing */
N} FSMC_PCCARDInitTypeDef;
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_Exported_Constants
N * @{
N */
N
N/** @defgroup FSMC_Banks_definitions
N * @{
N */
N
N#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
N#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
N#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
N#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
N#define FSMC_Bank2_NAND ((uint32_t)0x00000010)
N#define FSMC_Bank3_NAND ((uint32_t)0x00000100)
N#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
N
N#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
N ((BANK) == FSMC_Bank1_NORSRAM2) || \
N ((BANK) == FSMC_Bank1_NORSRAM3) || \
N ((BANK) == FSMC_Bank1_NORSRAM4))
X#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || ((BANK) == FSMC_Bank1_NORSRAM2) || ((BANK) == FSMC_Bank1_NORSRAM3) || ((BANK) == FSMC_Bank1_NORSRAM4))
N
N#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
N ((BANK) == FSMC_Bank3_NAND))
X#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || ((BANK) == FSMC_Bank3_NAND))
N
N#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
N ((BANK) == FSMC_Bank3_NAND) || \
N ((BANK) == FSMC_Bank4_PCCARD))
X#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || ((BANK) == FSMC_Bank3_NAND) || ((BANK) == FSMC_Bank4_PCCARD))
N
N#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
N ((BANK) == FSMC_Bank3_NAND) || \
N ((BANK) == FSMC_Bank4_PCCARD))
X#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || ((BANK) == FSMC_Bank3_NAND) || ((BANK) == FSMC_Bank4_PCCARD))
N/**
N * @}
N */
N
N/** @defgroup NOR_SRAM_Banks
N * @{
N */
N
N/** @defgroup FSMC_Data_Address_Bus_Multiplexing
N * @{
N */
N
N#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
N#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
N#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
N ((MUX) == FSMC_DataAddressMux_Enable))
X#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || ((MUX) == FSMC_DataAddressMux_Enable))
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_Memory_Type
N * @{
N */
N
N#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
N#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
N#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
N#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
N ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
N ((MEMORY) == FSMC_MemoryType_NOR))
X#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || ((MEMORY) == FSMC_MemoryType_PSRAM)|| ((MEMORY) == FSMC_MemoryType_NOR))
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_Data_Width
N * @{
N */
N
N#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
N#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
N#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
N ((WIDTH) == FSMC_MemoryDataWidth_16b))
X#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || ((WIDTH) == FSMC_MemoryDataWidth_16b))
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_Burst_Access_Mode
N * @{
N */
N
N#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
N#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
N#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
N ((STATE) == FSMC_BurstAccessMode_Enable))
X#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || ((STATE) == FSMC_BurstAccessMode_Enable))
N/**
N * @}
N */
N
N/** @defgroup FSMC_Wait_Signal_Polarity
N * @{
N */
N
N#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
N#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
N#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
N ((POLARITY) == FSMC_WaitSignalPolarity_High))
X#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || ((POLARITY) == FSMC_WaitSignalPolarity_High))
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_Wrap_Mode
N * @{
N */
N
N#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
N#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
N#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
N ((MODE) == FSMC_WrapMode_Enable))
X#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || ((MODE) == FSMC_WrapMode_Enable))
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_Wait_Timing
N * @{
N */
N
N#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
N#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
N#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
N ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
X#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_Write_Operation
N * @{
N */
N
N#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
N#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
N#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
N ((OPERATION) == FSMC_WriteOperation_Enable))
X#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || ((OPERATION) == FSMC_WriteOperation_Enable))
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_Wait_Signal
N * @{
N */
N
N#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
N#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
N#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
N ((SIGNAL) == FSMC_WaitSignal_Enable))
X#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || ((SIGNAL) == FSMC_WaitSignal_Enable))
N/**
N * @}
N */
N
N/** @defgroup FSMC_Extended_Mode
N * @{
N */
N
N#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
N#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
N
N#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
N ((MODE) == FSMC_ExtendedMode_Enable))
X#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || ((MODE) == FSMC_ExtendedMode_Enable))
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_Write_Burst
N * @{
N */
N
N#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
N#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
N#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
N ((BURST) == FSMC_WriteBurst_Enable))
X#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || ((BURST) == FSMC_WriteBurst_Enable))
N/**
N * @}
N */
N
N/** @defgroup FSMC_Address_Setup_Time
N * @{
N */
N
N#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_Address_Hold_Time
N * @{
N */
N
N#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_Data_Setup_Time
N * @{
N */
N
N#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_Bus_Turn_around_Duration
N * @{
N */
N
N#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_CLK_Division
N * @{
N */
N
N#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_Data_Latency
N * @{
N */
N
N#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_Access_Mode
N * @{
N */
N
N#define FSMC_AccessMode_A ((uint32_t)0x00000000)
N#define FSMC_AccessMode_B ((uint32_t)0x10000000)
N#define FSMC_AccessMode_C ((uint32_t)0x20000000)
N#define FSMC_AccessMode_D ((uint32_t)0x30000000)
N#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
N ((MODE) == FSMC_AccessMode_B) || \
N ((MODE) == FSMC_AccessMode_C) || \
N ((MODE) == FSMC_AccessMode_D))
X#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || ((MODE) == FSMC_AccessMode_B) || ((MODE) == FSMC_AccessMode_C) || ((MODE) == FSMC_AccessMode_D))
N
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/** @defgroup NAND_and_PCCARD_Banks
N * @{
N */
N
N/** @defgroup FSMC_Wait_feature
N * @{
N */
N
N#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
N#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
N#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
N ((FEATURE) == FSMC_Waitfeature_Enable))
X#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || ((FEATURE) == FSMC_Waitfeature_Enable))
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_Memory_Data_Width
N * @{
N */
N#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
N#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
N#define IS_FSMC_DATA_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
N ((WIDTH) == FSMC_MemoryDataWidth_16b))
X#define IS_FSMC_DATA_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || ((WIDTH) == FSMC_MemoryDataWidth_16b))
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_ECC
N * @{
N */
N
N#define FSMC_ECC_Disable ((uint32_t)0x00000000)
N#define FSMC_ECC_Enable ((uint32_t)0x00000040)
N#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
N ((STATE) == FSMC_ECC_Enable))
X#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || ((STATE) == FSMC_ECC_Enable))
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_ECC_Page_Size
N * @{
N */
N
N#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
N#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
N#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
N#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
N#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
N#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
N#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
N ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
N ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
N ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
N ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
N ((SIZE) == FSMC_ECCPageSize_8192Bytes))
X#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || ((SIZE) == FSMC_ECCPageSize_512Bytes) || ((SIZE) == FSMC_ECCPageSize_1024Bytes) || ((SIZE) == FSMC_ECCPageSize_2048Bytes) || ((SIZE) == FSMC_ECCPageSize_4096Bytes) || ((SIZE) == FSMC_ECCPageSize_8192Bytes))
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_TCLR_Setup_Time
N * @{
N */
N
N#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_TAR_Setup_Time
N * @{
N */
N
N#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_Setup_Time
N * @{
N */
N
N#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_Wait_Setup_Time
N * @{
N */
N
N#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_Hold_Setup_Time
N * @{
N */
N
N#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_HiZ_Setup_Time
N * @{
N */
N
N#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_Interrupt_sources
N * @{
N */
N
N#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
N#define FSMC_IT_Level ((uint32_t)0x00000010)
N#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
N#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
N#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
N ((IT) == FSMC_IT_Level) || \
N ((IT) == FSMC_IT_FallingEdge))
X#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || ((IT) == FSMC_IT_Level) || ((IT) == FSMC_IT_FallingEdge))
N/**
N * @}
N */
N
N/** @defgroup FSMC_Flags
N * @{
N */
N
N#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
N#define FSMC_FLAG_Level ((uint32_t)0x00000002)
N#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
N#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
N#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
N ((FLAG) == FSMC_FLAG_Level) || \
N ((FLAG) == FSMC_FLAG_FallingEdge) || \
N ((FLAG) == FSMC_FLAG_FEMPT))
X#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || ((FLAG) == FSMC_FLAG_Level) || ((FLAG) == FSMC_FLAG_FallingEdge) || ((FLAG) == FSMC_FLAG_FEMPT))
N
N#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
N
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_Exported_Macros
N * @{
N */
N
N/**
N * @}
N */
N
N/** @defgroup FSMC_Exported_Functions
N * @{
N */
N
Nvoid FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
Nvoid FSMC_NANDDeInit(uint32_t FSMC_Bank);
Nvoid FSMC_PCCARDDeInit(void);
Nvoid FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct);
Nvoid FSMC_NANDInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct);
Nvoid FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct);
Nvoid FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct);
Nvoid FSMC_NANDStructInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct);
Nvoid FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct);
Nvoid FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
Nvoid FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
Nvoid FSMC_PCCARDCmd(FunctionalState NewState);
Nvoid FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
Nuint32_t FSMC_GetECC(uint32_t FSMC_Bank);
Nvoid FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
NFlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
Nvoid FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
NITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
Nvoid FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
N
N#endif /*__STM32F10x_FSMC_H */
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
L 37 "..\src\STM32Lib\stm32f10x_conf.h" 2
N#include "stm32f10x_gpio.h"
L 1 "..\src\STM32Lib\stm32f10x_gpio.h" 1
N/**
N ******************************************************************************
N * @file stm32f10x_gpio.h
N * @author MCD Application Team
N * @version V3.0.0
N * @date 04/06/2009
N * @brief This file contains all the functions prototypes for the GPIO
N * firmware library.
N ******************************************************************************
N * @copy
N *
N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N *
N * © COPYRIGHT 2009 STMicroelectronics
N */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F10x_GPIO_H
N#define __STM32F10x_GPIO_H
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f10x.h"
N
N/** @addtogroup StdPeriph_Driver
N * @{
N */
N
N/** @addtogroup GPIO
N * @{
N */
N
N/** @defgroup GPIO_Exported_Types
N * @{
N */
N
N#define IS_GPIO_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == GPIOA_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == GPIOB_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == GPIOC_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == GPIOD_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == GPIOE_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == GPIOF_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == GPIOG_BASE))
X#define IS_GPIO_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == GPIOA_BASE) || ((*(uint32_t*)&(PERIPH)) == GPIOB_BASE) || ((*(uint32_t*)&(PERIPH)) == GPIOC_BASE) || ((*(uint32_t*)&(PERIPH)) == GPIOD_BASE) || ((*(uint32_t*)&(PERIPH)) == GPIOE_BASE) || ((*(uint32_t*)&(PERIPH)) == GPIOF_BASE) || ((*(uint32_t*)&(PERIPH)) == GPIOG_BASE))
N
N/**
N * @brief Output Maximum frequency selection
N */
N
Ntypedef enum
N{
N GPIO_Speed_10MHz = 1,
N GPIO_Speed_2MHz,
N GPIO_Speed_50MHz
N} GPIOSpeed_TypeDef;
N#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \
N ((SPEED) == GPIO_Speed_50MHz))
X#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || ((SPEED) == GPIO_Speed_50MHz))
N
N/**
N * @brief Configuration Mode enumeration
N */
N
Ntypedef enum
N{
N GPIO_Mode_AIN = 0x0, //Ä£ÄâÊäÈë
N GPIO_Mode_IN_FLOATING = 0x04, //¸¡¿ÕÊäÈë
N GPIO_Mode_IPD = 0x28, //ÏÂÀÊäÈë
N GPIO_Mode_IPU = 0x48, //ÉÏÀÊäÈë
N GPIO_Mode_Out_OD = 0x14, //¿ªÂ©Êä³ö
N GPIO_Mode_Out_PP = 0x10, //ÍÆÍìÊä³ö
N GPIO_Mode_AF_OD = 0x1C, //¿ªÂ©¸´Óù¦ÄÜ
N GPIO_Mode_AF_PP = 0x18 //ÍÆÍ츴Óù¦ÄÜ
N} GPIOMode_TypeDef;
N
N#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \
N ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \
N ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \
N ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))
X#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))
N
N/**
N * @brief GPIO Init structure definition
N */
N
Ntypedef struct
N{
N uint16_t GPIO_Pin;
N GPIOSpeed_TypeDef GPIO_Speed;
N GPIOMode_TypeDef GPIO_Mode;
N} GPIO_InitTypeDef;
N
N/**
N * @brief Bit_SET and Bit_RESET enumeration
N */
N
Ntypedef enum
N{
N Bit_RESET = 0,
N Bit_SET
N} BitAction;
N
N#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
N
N/**
N * @}
N */
N
N/** @defgroup GPIO_Exported_Constants
N * @{
N */
N
N/** @defgroup GPIO_pins_define
N * @{
N */
N
N#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */
N#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */
N#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */
N#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */
N#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */
N#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */
N#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */
N#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */
N#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */
N#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */
N#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */
N#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */
N#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */
N#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */
N#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */
N#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */
N#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */
N
N#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
N
N#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
N ((PIN) == GPIO_Pin_1) || \
N ((PIN) == GPIO_Pin_2) || \
N ((PIN) == GPIO_Pin_3) || \
N ((PIN) == GPIO_Pin_4) || \
N ((PIN) == GPIO_Pin_5) || \
N ((PIN) == GPIO_Pin_6) || \
N ((PIN) == GPIO_Pin_7) || \
N ((PIN) == GPIO_Pin_8) || \
N ((PIN) == GPIO_Pin_9) || \
N ((PIN) == GPIO_Pin_10) || \
N ((PIN) == GPIO_Pin_11) || \
N ((PIN) == GPIO_Pin_12) || \
N ((PIN) == GPIO_Pin_13) || \
N ((PIN) == GPIO_Pin_14) || \
N ((PIN) == GPIO_Pin_15))
X#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || ((PIN) == GPIO_Pin_1) || ((PIN) == GPIO_Pin_2) || ((PIN) == GPIO_Pin_3) || ((PIN) == GPIO_Pin_4) || ((PIN) == GPIO_Pin_5) || ((PIN) == GPIO_Pin_6) || ((PIN) == GPIO_Pin_7) || ((PIN) == GPIO_Pin_8) || ((PIN) == GPIO_Pin_9) || ((PIN) == GPIO_Pin_10) || ((PIN) == GPIO_Pin_11) || ((PIN) == GPIO_Pin_12) || ((PIN) == GPIO_Pin_13) || ((PIN) == GPIO_Pin_14) || ((PIN) == GPIO_Pin_15))
N
N/**
N * @}
N */
N
N/** @defgroup GPIO_Remap_define
N * @{
N */
N
N#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */
N#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */
N#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /* USART1 Alternate Function mapping */
N#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /* USART2 Alternate Function mapping */
N#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /* USART3 Partial Alternate Function mapping */
N#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */
N#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */
N#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */
N#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */
N#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */
N#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */
N#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */
N#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */
N#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */
N#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN Alternate Function mapping */
N#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN Alternate Function mapping */
N#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */
N#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */
N#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */
N#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */
N#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */
N#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */
N#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
N#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /* JTAG-DP Disabled and SW-DP Enabled */
N#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */
N
N#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \
N ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \
N ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \
N ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \
N ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \
N ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \
N ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \
N ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \
N ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \
N ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \
N ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \
N ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable)|| \
N ((REMAP) == GPIO_Remap_SWJ_Disable))
X#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable)|| ((REMAP) == GPIO_Remap_SWJ_Disable))
N
N/**
N * @}
N */
N
N/** @defgroup GPIO_Port_Sources
N * @{
N */
N
N#define GPIO_PortSourceGPIOA ((uint8_t)0x00)
N#define GPIO_PortSourceGPIOB ((uint8_t)0x01)
N#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
N#define GPIO_PortSourceGPIOD ((uint8_t)0x03)
N#define GPIO_PortSourceGPIOE ((uint8_t)0x04)
N#define GPIO_PortSourceGPIOF ((uint8_t)0x05)
N#define GPIO_PortSourceGPIOG ((uint8_t)0x06)
N#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
N ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
N ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
N ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
N ((PORTSOURCE) == GPIO_PortSourceGPIOE))
X#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || ((PORTSOURCE) == GPIO_PortSourceGPIOB) || ((PORTSOURCE) == GPIO_PortSourceGPIOC) || ((PORTSOURCE) == GPIO_PortSourceGPIOD) || ((PORTSOURCE) == GPIO_PortSourceGPIOE))
N
N#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
N ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
N ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
N ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
N ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \
N ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \
N ((PORTSOURCE) == GPIO_PortSourceGPIOG))
X#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || ((PORTSOURCE) == GPIO_PortSourceGPIOB) || ((PORTSOURCE) == GPIO_PortSourceGPIOC) || ((PORTSOURCE) == GPIO_PortSourceGPIOD) || ((PORTSOURCE) == GPIO_PortSourceGPIOE) || ((PORTSOURCE) == GPIO_PortSourceGPIOF) || ((PORTSOURCE) == GPIO_PortSourceGPIOG))
N
N/**
N * @}
N */
N
N/** @defgroup GPIO_Pin_sources
N * @{
N */
N
N#define GPIO_PinSource0 ((uint8_t)0x00)
N#define GPIO_PinSource1 ((uint8_t)0x01)
N#define GPIO_PinSource2 ((uint8_t)0x02)
N#define GPIO_PinSource3 ((uint8_t)0x03)
N#define GPIO_PinSource4 ((uint8_t)0x04)
N#define GPIO_PinSource5 ((uint8_t)0x05)
N#define GPIO_PinSource6 ((uint8_t)0x06)
N#define GPIO_PinSource7 ((uint8_t)0x07)
N#define GPIO_PinSource8 ((uint8_t)0x08)
N#define GPIO_PinSource9 ((uint8_t)0x09)
N#define GPIO_PinSource10 ((uint8_t)0x0A)
N#define GPIO_PinSource11 ((uint8_t)0x0B)
N#define GPIO_PinSource12 ((uint8_t)0x0C)
N#define GPIO_PinSource13 ((uint8_t)0x0D)
N#define GPIO_PinSource14 ((uint8_t)0x0E)
N#define GPIO_PinSource15 ((uint8_t)0x0F)
N
N#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
N ((PINSOURCE) == GPIO_PinSource1) || \
N ((PINSOURCE) == GPIO_PinSource2) || \
N ((PINSOURCE) == GPIO_PinSource3) || \
N ((PINSOURCE) == GPIO_PinSource4) || \
N ((PINSOURCE) == GPIO_PinSource5) || \
N ((PINSOURCE) == GPIO_PinSource6) || \
N ((PINSOURCE) == GPIO_PinSource7) || \
N ((PINSOURCE) == GPIO_PinSource8) || \
N ((PINSOURCE) == GPIO_PinSource9) || \
N ((PINSOURCE) == GPIO_PinSource10) || \
N ((PINSOURCE) == GPIO_PinSource11) || \
N ((PINSOURCE) == GPIO_PinSource12) || \
N ((PINSOURCE) == GPIO_PinSource13) || \
N ((PINSOURCE) == GPIO_PinSource14) || \
N ((PINSOURCE) == GPIO_PinSource15))
X#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || ((PINSOURCE) == GPIO_PinSource1) || ((PINSOURCE) == GPIO_PinSource2) || ((PINSOURCE) == GPIO_PinSource3) || ((PINSOURCE) == GPIO_PinSource4) || ((PINSOURCE) == GPIO_PinSource5) || ((PINSOURCE) == GPIO_PinSource6) || ((PINSOURCE) == GPIO_PinSource7) || ((PINSOURCE) == GPIO_PinSource8) || ((PINSOURCE) == GPIO_PinSource9) || ((PINSOURCE) == GPIO_PinSource10) || ((PINSOURCE) == GPIO_PinSource11) || ((PINSOURCE) == GPIO_PinSource12) || ((PINSOURCE) == GPIO_PinSource13) || ((PINSOURCE) == GPIO_PinSource14) || ((PINSOURCE) == GPIO_PinSource15))
N
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/** @defgroup GPIO_Exported_Macros
N * @{
N */
N
N/**
N * @}
N */
N
N/** @defgroup GPIO_Exported_Functions
N * @{
N */
N
Nvoid GPIO_DeInit(GPIO_TypeDef *GPIOx);
Nvoid GPIO_AFIODeInit(void);
Nvoid GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct);
Nvoid GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct);
Nuint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
Nuint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx);
Nuint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
Nuint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx);
Nvoid GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
Nvoid GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
Nvoid GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
Nvoid GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal);
Nvoid GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
Nvoid GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
Nvoid GPIO_EventOutputCmd(FunctionalState NewState);
Nvoid GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
Nvoid GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
N
N#endif /* __STM32F10x_GPIO_H */
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
L 38 "..\src\STM32Lib\stm32f10x_conf.h" 2
N#include "stm32f10x_i2c.h"
L 1 "..\src\STM32Lib\stm32f10x_i2c.h" 1
N/**
N ******************************************************************************
N * @file stm32f10x_i2c.h
N * @author MCD Application Team
N * @version V3.0.0
N * @date 04/06/2009
N * @brief This file contains all the functions prototypes for the I2C firmware
N * library.
N ******************************************************************************
N * @copy
N *
N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N *
N * © COPYRIGHT 2009 STMicroelectronics
N */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F10x_I2C_H
N#define __STM32F10x_I2C_H
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f10x.h"
N
N/** @addtogroup StdPeriph_Driver
N * @{
N */
N
N/** @addtogroup I2C
N * @{
N */
N
N/** @defgroup I2C_Exported_Types
N * @{
N */
N
N/**
N * @brief I2C Init structure definition
N */
N
Ntypedef struct
N{
N uint16_t I2C_Mode;
N uint16_t I2C_DutyCycle;
N uint16_t I2C_OwnAddress1;
N uint16_t I2C_Ack;
N uint16_t I2C_AcknowledgedAddress;
N uint32_t I2C_ClockSpeed;
N} I2C_InitTypeDef;
N
N/**
N * @}
N */
N
N
N/** @defgroup I2C_Exported_Constants
N * @{
N */
N
N#define IS_I2C_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == I2C1_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == I2C2_BASE))
X#define IS_I2C_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == I2C1_BASE) || ((*(uint32_t*)&(PERIPH)) == I2C2_BASE))
N/** @defgroup I2C_modes
N * @{
N */
N
N#define I2C_Mode_I2C ((uint16_t)0x0000)
N#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
N#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
N#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
N ((MODE) == I2C_Mode_SMBusDevice) || \
N ((MODE) == I2C_Mode_SMBusHost))
X#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || ((MODE) == I2C_Mode_SMBusDevice) || ((MODE) == I2C_Mode_SMBusHost))
N/**
N * @}
N */
N
N/** @defgroup I2C_duty_cycle_in_fast_mode
N * @{
N */
N
N#define I2C_DutyCycle_16_9 ((uint16_t)0x4000)
N#define I2C_DutyCycle_2 ((uint16_t)0xBFFF)
N#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
N ((CYCLE) == I2C_DutyCycle_2))
X#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || ((CYCLE) == I2C_DutyCycle_2))
N/**
N * @}
N */
N
N/** @defgroup I2C_cknowledgementy
N * @{
N */
N
N#define I2C_Ack_Enable ((uint16_t)0x0400)
N#define I2C_Ack_Disable ((uint16_t)0x0000)
N#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
N ((STATE) == I2C_Ack_Disable))
X#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || ((STATE) == I2C_Ack_Disable))
N/**
N * @}
N */
N
N/** @defgroup I2C_transfer_direction
N * @{
N */
N
N#define I2C_Direction_Transmitter ((uint8_t)0x00)
N#define I2C_Direction_Receiver ((uint8_t)0x01)
N#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
N ((DIRECTION) == I2C_Direction_Receiver))
X#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || ((DIRECTION) == I2C_Direction_Receiver))
N/**
N * @}
N */
N
N/** @defgroup I2C_acknowledged_address_defines
N * @{
N */
N
N#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
N#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
N#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
N ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
X#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
N/**
N * @}
N */
N
N/** @defgroup I2C_registers
N * @{
N */
N
N#define I2C_Register_CR1 ((uint8_t)0x00)
N#define I2C_Register_CR2 ((uint8_t)0x04)
N#define I2C_Register_OAR1 ((uint8_t)0x08)
N#define I2C_Register_OAR2 ((uint8_t)0x0C)
N#define I2C_Register_DR ((uint8_t)0x10)
N#define I2C_Register_SR1 ((uint8_t)0x14)
N#define I2C_Register_SR2 ((uint8_t)0x18)
N#define I2C_Register_CCR ((uint8_t)0x1C)
N#define I2C_Register_TRISE ((uint8_t)0x20)
N#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
N ((REGISTER) == I2C_Register_CR2) || \
N ((REGISTER) == I2C_Register_OAR1) || \
N ((REGISTER) == I2C_Register_OAR2) || \
N ((REGISTER) == I2C_Register_DR) || \
N ((REGISTER) == I2C_Register_SR1) || \
N ((REGISTER) == I2C_Register_SR2) || \
N ((REGISTER) == I2C_Register_CCR) || \
N ((REGISTER) == I2C_Register_TRISE))
X#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || ((REGISTER) == I2C_Register_CR2) || ((REGISTER) == I2C_Register_OAR1) || ((REGISTER) == I2C_Register_OAR2) || ((REGISTER) == I2C_Register_DR) || ((REGISTER) == I2C_Register_SR1) || ((REGISTER) == I2C_Register_SR2) || ((REGISTER) == I2C_Register_CCR) || ((REGISTER) == I2C_Register_TRISE))
N/**
N * @}
N */
N
N/** @defgroup I2C_SMBus_alert_pin_level
N * @{
N */
N
N#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
N#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
N#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
N ((ALERT) == I2C_SMBusAlert_High))
X#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || ((ALERT) == I2C_SMBusAlert_High))
N/**
N * @}
N */
N
N/** @defgroup I2C_PEC_position
N * @{
N */
N
N#define I2C_PECPosition_Next ((uint16_t)0x0800)
N#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
N#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
N ((POSITION) == I2C_PECPosition_Current))
X#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || ((POSITION) == I2C_PECPosition_Current))
N/**
N * @}
N */
N
N/** @defgroup I2C_interrupts_definition
N * @{
N */
N
N#define I2C_IT_BUF ((uint16_t)0x0400)
N#define I2C_IT_EVT ((uint16_t)0x0200)
N#define I2C_IT_ERR ((uint16_t)0x0100)
N#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
N/**
N * @}
N */
N
N/** @defgroup I2C_interrupts_definition
N * @{
N */
N
N#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
N#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
N#define I2C_IT_PECERR ((uint32_t)0x01001000)
N#define I2C_IT_OVR ((uint32_t)0x01000800)
N#define I2C_IT_AF ((uint32_t)0x01000400)
N#define I2C_IT_ARLO ((uint32_t)0x01000200)
N#define I2C_IT_BERR ((uint32_t)0x01000100)
N#define I2C_IT_TXE ((uint32_t)0x06000080)
N#define I2C_IT_RXNE ((uint32_t)0x06000040)
N#define I2C_IT_STOPF ((uint32_t)0x02000010)
N#define I2C_IT_ADD10 ((uint32_t)0x02000008)
N#define I2C_IT_BTF ((uint32_t)0x02000004)
N#define I2C_IT_ADDR ((uint32_t)0x02000002)
N#define I2C_IT_SB ((uint32_t)0x02000001)
N
N#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
N
N#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
N ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
N ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
N ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
N ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
N ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
N ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
X#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
N/**
N * @}
N */
N
N/** @defgroup I2C_flags_definition
N * @{
N */
N
N/**
N * @brief SR2 register flags
N */
N
N#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
N#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
N#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
N#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
N#define I2C_FLAG_TRA ((uint32_t)0x00040000)
N#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
N#define I2C_FLAG_MSL ((uint32_t)0x00010000)
N
N/**
N * @brief SR1 register flags
N */
N
N#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
N#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
N#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
N#define I2C_FLAG_OVR ((uint32_t)0x10000800)
N#define I2C_FLAG_AF ((uint32_t)0x10000400)
N#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
N#define I2C_FLAG_BERR ((uint32_t)0x10000100)
N#define I2C_FLAG_TXE ((uint32_t)0x10000080)
N#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
N#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
N#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
N#define I2C_FLAG_BTF ((uint32_t)0x10000004)
N#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
N#define I2C_FLAG_SB ((uint32_t)0x10000001)
N
N#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
N
N#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
N ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
N ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
N ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
N ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
N ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
N ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
N ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
N ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
N ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
N ((FLAG) == I2C_FLAG_SB))
X#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || ((FLAG) == I2C_FLAG_SB))
N/**
N * @}
N */
N
N/** @defgroup I2C_Events
N * @{
N */
N
N/**
N * @brief EV1
N */
N
N#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
N#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
N#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
N#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
N#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
N
N/**
N * @brief EV2
N */
N
N#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
N
N/**
N * @brief EV3
N */
N
N#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
N
N/**
N * @brief EV4
N */
N
N#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
N
N/**
N * @brief EV5
N */
N
N#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
N
N/**
N * @brief EV6
N */
N
N#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
N#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
N
N/**
N * @brief EV7
N */
N
N#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
N
N/**
N * @brief EV8
N */
N
N#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
N
N/**
N * @brief EV8_2
N */
N
N#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
N
N/**
N * @brief EV9
N */
N
N#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
N
N/**
N * @brief EV3_2
N */
N
N#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
N
N#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
N ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
N ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
N ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
N ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
N ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
N ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
N ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
N ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
N ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
N ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
N ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
N ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
N ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
N ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
N ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
N ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
N ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
N ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
N ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
X#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
N/**
N * @}
N */
N
N/** @defgroup I2C_own_address1
N * @{
N */
N
N#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
N/**
N * @}
N */
N
N/** @defgroup I2C_clock_speed
N * @{
N */
N
N#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/** @defgroup I2C_Exported_Macros
N * @{
N */
N
N/**
N * @}
N */
N
N/** @defgroup I2C_Exported_Functions
N * @{
N */
N
Nvoid I2C_DeInit(I2C_TypeDef *I2Cx);
Nvoid I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct);
Nvoid I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct);
Nvoid I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
Nvoid I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
Nvoid I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
Nvoid I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState);
Nvoid I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState);
Nvoid I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState);
Nvoid I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address);
Nvoid I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
Nvoid I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
Nvoid I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState);
Nvoid I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data);
Nuint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx);
Nvoid I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction);
Nuint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register);
Nvoid I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
Nvoid I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert);
Nvoid I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState);
Nvoid I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition);
Nvoid I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState);
Nuint8_t I2C_GetPEC(I2C_TypeDef *I2Cx);
Nvoid I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
Nvoid I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
Nvoid I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle);
Nuint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx);
NErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT);
NFlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG);
Nvoid I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG);
NITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT);
Nvoid I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT);
N
N#endif /*__STM32F10x_I2C_H */
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
L 39 "..\src\STM32Lib\stm32f10x_conf.h" 2
N// #include "stm32f10x_iwdg.h"
N// #include "stm32f10x_pwr.h"
N#include "stm32f10x_rcc.h"
L 1 "..\src\STM32Lib\stm32f10x_rcc.h" 1
N/**
N ******************************************************************************
N * @file stm32f10x_rcc.h
N * @author MCD Application Team
N * @version V3.0.0
N * @date 04/06/2009
N * @brief This file contains all the functions prototypes for the RCC firmware
N * library.
N ******************************************************************************
N * @copy
N *
N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N *
N * © COPYRIGHT 2009 STMicroelectronics
N */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F10x_RCC_H
N#define __STM32F10x_RCC_H
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f10x.h"
N
N/** @addtogroup StdPeriph_Driver
N * @{
N */
N
N/** @addtogroup RCC
N * @{
N */
N
N/** @defgroup RCC_Exported_Types
N * @{
N */
N
Ntypedef struct
N{
N uint32_t SYSCLK_Frequency;
N uint32_t HCLK_Frequency;
N uint32_t PCLK1_Frequency;
N uint32_t PCLK2_Frequency;
N uint32_t ADCCLK_Frequency;
N} RCC_ClocksTypeDef;
N
N/**
N * @}
N */
N
N/** @defgroup RCC_Exported_Constants
N * @{
N */
N
N/** @defgroup HSE_configuration
N * @{
N */
N
N#define RCC_HSE_OFF ((uint32_t)0x00000000)
N#define RCC_HSE_ON ((uint32_t)0x00010000)
N#define RCC_HSE_Bypass ((uint32_t)0x00040000)
N#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
N ((HSE) == RCC_HSE_Bypass))
X#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || ((HSE) == RCC_HSE_Bypass))
N
N/**
N * @}
N */
N
N/** @defgroup PLL_entry_clock_source
N * @{
N */
N
N#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)
N#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)
N#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)
N#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
N ((SOURCE) == RCC_PLLSource_HSE_Div1) || \
N ((SOURCE) == RCC_PLLSource_HSE_Div2))
X#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || ((SOURCE) == RCC_PLLSource_HSE_Div1) || ((SOURCE) == RCC_PLLSource_HSE_Div2))
N/**
N * @}
N */
N
N/** @defgroup PLL_multiplication_factor
N * @{
N */
N
N#define RCC_PLLMul_2 ((uint32_t)0x00000000)
N#define RCC_PLLMul_3 ((uint32_t)0x00040000)
N#define RCC_PLLMul_4 ((uint32_t)0x00080000)
N#define RCC_PLLMul_5 ((uint32_t)0x000C0000)
N#define RCC_PLLMul_6 ((uint32_t)0x00100000)
N#define RCC_PLLMul_7 ((uint32_t)0x00140000)
N#define RCC_PLLMul_8 ((uint32_t)0x00180000)
N#define RCC_PLLMul_9 ((uint32_t)0x001C0000)
N#define RCC_PLLMul_10 ((uint32_t)0x00200000)
N#define RCC_PLLMul_11 ((uint32_t)0x00240000)
N#define RCC_PLLMul_12 ((uint32_t)0x00280000)
N#define RCC_PLLMul_13 ((uint32_t)0x002C0000)
N#define RCC_PLLMul_14 ((uint32_t)0x00300000)
N#define RCC_PLLMul_15 ((uint32_t)0x00340000)
N#define RCC_PLLMul_16 ((uint32_t)0x00380000)
N#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
N ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
N ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
N ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
N ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
N ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
N ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
N ((MUL) == RCC_PLLMul_16))
X#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || ((MUL) == RCC_PLLMul_16))
N/**
N * @}
N */
N
N/** @defgroup System_clock_source
N * @{
N */
N
N#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
N#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
N#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
N#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
N ((SOURCE) == RCC_SYSCLKSource_HSE) || \
N ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
X#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || ((SOURCE) == RCC_SYSCLKSource_HSE) || ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
N/**
N * @}
N */
N
N/** @defgroup AHB_clock_source
N * @{
N */
N
N#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
N#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
N#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
N#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
N#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
N#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
N#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
N#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
N#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
N#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
N ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
N ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
N ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
N ((HCLK) == RCC_SYSCLK_Div512))
X#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || ((HCLK) == RCC_SYSCLK_Div512))
N/**
N * @}
N */
N
N/** @defgroup APB1_APB2_clock_source
N * @{
N */
N
N#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
N#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
N#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
N#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
N#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
N#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
N ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
N ((PCLK) == RCC_HCLK_Div16))
X#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || ((PCLK) == RCC_HCLK_Div16))
N/**
N * @}
N */
N
N/** @defgroup RCC_Interrupt_source
N * @{
N */
N
N#define RCC_IT_LSIRDY ((uint8_t)0x01)
N#define RCC_IT_LSERDY ((uint8_t)0x02)
N#define RCC_IT_HSIRDY ((uint8_t)0x04)
N#define RCC_IT_HSERDY ((uint8_t)0x08)
N#define RCC_IT_PLLRDY ((uint8_t)0x10)
N#define RCC_IT_CSS ((uint8_t)0x80)
N#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))
N#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
N ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
N ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
X#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
N
N#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))
N/**
N * @}
N */
N
N/** @defgroup USB_clock_source
N * @{
N */
N
N#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
N#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
N#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
N ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
X#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
N/**
N * @}
N */
N
N/** @defgroup ADC_clock_source
N * @{
N */
N
N#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
N#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
N#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
N#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
N#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
N ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
X#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
N/**
N * @}
N */
N
N/** @defgroup LSE_configuration
N * @{
N */
N
N#define RCC_LSE_OFF ((uint8_t)0x00)
N#define RCC_LSE_ON ((uint8_t)0x01)
N#define RCC_LSE_Bypass ((uint8_t)0x04)
N#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
N ((LSE) == RCC_LSE_Bypass))
X#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || ((LSE) == RCC_LSE_Bypass))
N/**
N * @}
N */
N
N/** @defgroup RTC_clock_source
N * @{
N */
N
N#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
N#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
N#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
N#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
N ((SOURCE) == RCC_RTCCLKSource_LSI) || \
N ((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
X#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || ((SOURCE) == RCC_RTCCLKSource_LSI) || ((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
N/**
N * @}
N */
N
N/** @defgroup AHB_peripheral
N * @{
N */
N
N#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
N#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
N#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
N#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
N#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
N#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
N#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
N#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
N/**
N * @}
N */
N
N/** @defgroup APB2_peripheral
N * @{
N */
N
N#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
N#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
N#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
N#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
N#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
N#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
N#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)
N#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)
N#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
N#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
N#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
N#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
N#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
N#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
N#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
N#define RCC_APB2Periph_ALL ((uint32_t)0x0000FFFD)
N
N#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFF0002) == 0x00) && ((PERIPH) != 0x00))
N/**
N * @}
N */
N
N/** @defgroup APB1_peripheral
N * @{
N */
N
N#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
N#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
N#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
N#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
N#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
N#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
N#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
N#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
N#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
N#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
N#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
N#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
N#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
N#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
N#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
N#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
N#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
N#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
N#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
N#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
N#define RCC_APB1Periph_ALL ((uint32_t)0x3AFEC83F)
N
N#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC50137C0) == 0x00) && ((PERIPH) != 0x00))
N/**
N * @}
N */
N
N/** @defgroup Clock_source_to_output_on_MCO_pin
N * @{
N */
N
N#define RCC_MCO_NoClock ((uint8_t)0x00)
N#define RCC_MCO_SYSCLK ((uint8_t)0x04)
N#define RCC_MCO_HSI ((uint8_t)0x05)
N#define RCC_MCO_HSE ((uint8_t)0x06)
N#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)
N#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
N ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
N ((MCO) == RCC_MCO_PLLCLK_Div2))
X#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || ((MCO) == RCC_MCO_PLLCLK_Div2))
N/**
N * @}
N */
N
N/** @defgroup RCC_Flag
N * @{
N */
N
N#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
N#define RCC_FLAG_HSERDY ((uint8_t)0x31)
N#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
N#define RCC_FLAG_LSERDY ((uint8_t)0x41)
N#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
N#define RCC_FLAG_PINRST ((uint8_t)0x7A)
N#define RCC_FLAG_PORRST ((uint8_t)0x7B)
N#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
N#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
N#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
N#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
N#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
N ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
N ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
N ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
N ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
N ((FLAG) == RCC_FLAG_LPWRRST))
X#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST))
N
N#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/** @defgroup RCC_Exported_Macros
N * @{
N */
N
N/**
N * @}
N */
N
N/** @defgroup RCC_Exported_Functions
N * @{
N */
N
Nvoid RCC_DeInit(void);
Nvoid RCC_HSEConfig(uint32_t RCC_HSE);
NErrorStatus RCC_WaitForHSEStartUp(void);
Nvoid RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
Nvoid RCC_HSICmd(FunctionalState NewState);
Nvoid RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
Nvoid RCC_PLLCmd(FunctionalState NewState);
Nvoid RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
Nuint8_t RCC_GetSYSCLKSource(void);
Nvoid RCC_HCLKConfig(uint32_t RCC_SYSCLK);
Nvoid RCC_PCLK1Config(uint32_t RCC_HCLK);
Nvoid RCC_PCLK2Config(uint32_t RCC_HCLK);
Nvoid RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
Nvoid RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
Nvoid RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
Nvoid RCC_LSEConfig(uint8_t RCC_LSE);
Nvoid RCC_LSICmd(FunctionalState NewState);
Nvoid RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
Nvoid RCC_RTCCLKCmd(FunctionalState NewState);
Nvoid RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks);
Nvoid RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
Nvoid RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
Nvoid RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
Nvoid RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
Nvoid RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
Nvoid RCC_BackupResetCmd(FunctionalState NewState);
Nvoid RCC_ClockSecuritySystemCmd(FunctionalState NewState);
Nvoid RCC_MCOConfig(uint8_t RCC_MCO);
NFlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
Nvoid RCC_ClearFlag(void);
NITStatus RCC_GetITStatus(uint8_t RCC_IT);
Nvoid RCC_ClearITPendingBit(uint8_t RCC_IT);
N
N#endif /* __STM32F10x_RCC_H */
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
L 42 "..\src\STM32Lib\stm32f10x_conf.h" 2
N// #include "stm32f10x_rtc.h"
N// #include "stm32f10x_sdio.h"
N#include "stm32f10x_spi.h"
L 1 "..\src\STM32Lib\stm32f10x_spi.h" 1
N/**
N ******************************************************************************
N * @file stm32f10x_spi.h
N * @author MCD Application Team
N * @version V3.0.0
N * @date 04/06/2009
N * @brief This file contains all the functions prototypes for the SPI firmware
N * library.
N ******************************************************************************
N * @copy
N *
N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N *
N * © COPYRIGHT 2009 STMicroelectronics
N */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F10x_SPI_H
N#define __STM32F10x_SPI_H
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f10x.h"
N
N/** @addtogroup StdPeriph_Driver
N * @{
N */
N
N/** @addtogroup SPI
N * @{
N */
N
N/** @defgroup SPI_Exported_Types
N * @{
N */
N
N/**
N * @brief SPI Init structure definition
N */
N
Ntypedef struct
N{
N uint16_t SPI_Direction;
N uint16_t SPI_Mode;
N uint16_t SPI_DataSize;
N uint16_t SPI_CPOL;
N uint16_t SPI_CPHA;
N uint16_t SPI_NSS;
N uint16_t SPI_BaudRatePrescaler;
N uint16_t SPI_FirstBit;
N uint16_t SPI_CRCPolynomial;
N} SPI_InitTypeDef;
N
N/**
N * @brief I2S Init structure definition
N */
N
Ntypedef struct
N{
N uint16_t I2S_Mode;
N uint16_t I2S_Standard;
N uint16_t I2S_DataFormat;
N uint16_t I2S_MCLKOutput;
N uint16_t I2S_AudioFreq;
N uint16_t I2S_CPOL;
N} I2S_InitTypeDef;
N
N/**
N * @}
N */
N
N/** @defgroup SPI_Exported_Constants
N * @{
N */
N
N#define IS_SPI_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == SPI1_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == SPI2_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == SPI3_BASE))
X#define IS_SPI_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == SPI1_BASE) || ((*(uint32_t*)&(PERIPH)) == SPI2_BASE) || ((*(uint32_t*)&(PERIPH)) == SPI3_BASE))
N#define IS_SPI_23_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == SPI2_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == SPI3_BASE))
X#define IS_SPI_23_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == SPI2_BASE) || ((*(uint32_t*)&(PERIPH)) == SPI3_BASE))
N
N/** @defgroup SPI_data_direction_mode
N * @{
N */
N
N#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
N#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
N#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
N#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
N#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
N ((MODE) == SPI_Direction_2Lines_RxOnly) || \
N ((MODE) == SPI_Direction_1Line_Rx) || \
N ((MODE) == SPI_Direction_1Line_Tx))
X#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || ((MODE) == SPI_Direction_2Lines_RxOnly) || ((MODE) == SPI_Direction_1Line_Rx) || ((MODE) == SPI_Direction_1Line_Tx))
N/**
N * @}
N */
N
N/** @defgroup SPI_master_slave_mode
N * @{
N */
N
N#define SPI_Mode_Master ((uint16_t)0x0104)
N#define SPI_Mode_Slave ((uint16_t)0x0000)
N#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
N ((MODE) == SPI_Mode_Slave))
X#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || ((MODE) == SPI_Mode_Slave))
N/**
N * @}
N */
N
N/** @defgroup SPI_data_size
N * @{
N */
N
N#define SPI_DataSize_16b ((uint16_t)0x0800)
N#define SPI_DataSize_8b ((uint16_t)0x0000)
N#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
N ((DATASIZE) == SPI_DataSize_8b))
X#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || ((DATASIZE) == SPI_DataSize_8b))
N/**
N * @}
N */
N
N/** @defgroup SPI_Clock_Polarity
N * @{
N */
N
N#define SPI_CPOL_Low ((uint16_t)0x0000)
N#define SPI_CPOL_High ((uint16_t)0x0002)
N#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
N ((CPOL) == SPI_CPOL_High))
X#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || ((CPOL) == SPI_CPOL_High))
N/**
N * @}
N */
N
N/** @defgroup SPI_Clock_Phase
N * @{
N */
N
N#define SPI_CPHA_1Edge ((uint16_t)0x0000)
N#define SPI_CPHA_2Edge ((uint16_t)0x0001)
N#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
N ((CPHA) == SPI_CPHA_2Edge))
X#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || ((CPHA) == SPI_CPHA_2Edge))
N/**
N * @}
N */
N
N/** @defgroup SPI_Slave_Select_management
N * @{
N */
N
N#define SPI_NSS_Soft ((uint16_t)0x0200)
N#define SPI_NSS_Hard ((uint16_t)0x0000)
N#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
N ((NSS) == SPI_NSS_Hard))
X#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || ((NSS) == SPI_NSS_Hard))
N/**
N * @}
N */
N
N/** @defgroup SPI_BaudRate_Prescaler_
N * @{
N */
N
N#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
N#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
N#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
N#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
N#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
N#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
N#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
N#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
N#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
N ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
N ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
N ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
N ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
N ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
N ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
N ((PRESCALER) == SPI_BaudRatePrescaler_256))
X#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || ((PRESCALER) == SPI_BaudRatePrescaler_4) || ((PRESCALER) == SPI_BaudRatePrescaler_8) || ((PRESCALER) == SPI_BaudRatePrescaler_16) || ((PRESCALER) == SPI_BaudRatePrescaler_32) || ((PRESCALER) == SPI_BaudRatePrescaler_64) || ((PRESCALER) == SPI_BaudRatePrescaler_128) || ((PRESCALER) == SPI_BaudRatePrescaler_256))
N/**
N * @}
N */
N
N/** @defgroup SPI_MSB_LSB_transmission
N * @{
N */
N
N#define SPI_FirstBit_MSB ((uint16_t)0x0000)
N#define SPI_FirstBit_LSB ((uint16_t)0x0080)
N#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
N ((BIT) == SPI_FirstBit_LSB))
X#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || ((BIT) == SPI_FirstBit_LSB))
N/**
N * @}
N */
N
N/** @defgroup I2S_Mode
N * @{
N */
N
N#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
N#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
N#define I2S_Mode_MasterTx ((uint16_t)0x0200)
N#define I2S_Mode_MasterRx ((uint16_t)0x0300)
N#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
N ((MODE) == I2S_Mode_SlaveRx) || \
N ((MODE) == I2S_Mode_MasterTx) || \
N ((MODE) == I2S_Mode_MasterRx) )
X#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || ((MODE) == I2S_Mode_SlaveRx) || ((MODE) == I2S_Mode_MasterTx) || ((MODE) == I2S_Mode_MasterRx) )
N/**
N * @}
N */
N
N/** @defgroup I2S_Standard
N * @{
N */
N
N#define I2S_Standard_Phillips ((uint16_t)0x0000)
N#define I2S_Standard_MSB ((uint16_t)0x0010)
N#define I2S_Standard_LSB ((uint16_t)0x0020)
N#define I2S_Standard_PCMShort ((uint16_t)0x0030)
N#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
N#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
N ((STANDARD) == I2S_Standard_MSB) || \
N ((STANDARD) == I2S_Standard_LSB) || \
N ((STANDARD) == I2S_Standard_PCMShort) || \
N ((STANDARD) == I2S_Standard_PCMLong))
X#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || ((STANDARD) == I2S_Standard_MSB) || ((STANDARD) == I2S_Standard_LSB) || ((STANDARD) == I2S_Standard_PCMShort) || ((STANDARD) == I2S_Standard_PCMLong))
N/**
N * @}
N */
N
N/** @defgroup I2S_Data_Format
N * @{
N */
N
N#define I2S_DataFormat_16b ((uint16_t)0x0000)
N#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
N#define I2S_DataFormat_24b ((uint16_t)0x0003)
N#define I2S_DataFormat_32b ((uint16_t)0x0005)
N#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
N ((FORMAT) == I2S_DataFormat_16bextended) || \
N ((FORMAT) == I2S_DataFormat_24b) || \
N ((FORMAT) == I2S_DataFormat_32b))
X#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || ((FORMAT) == I2S_DataFormat_16bextended) || ((FORMAT) == I2S_DataFormat_24b) || ((FORMAT) == I2S_DataFormat_32b))
N/**
N * @}
N */
N
N/** @defgroup I2S_MCLK_Output
N * @{
N */
N
N#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
N#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
N#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
N ((OUTPUT) == I2S_MCLKOutput_Disable))
X#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || ((OUTPUT) == I2S_MCLKOutput_Disable))
N/**
N * @}
N */
N
N/** @defgroup I2S_Audio_Frequency
N * @{
N */
N
N#define I2S_AudioFreq_48k ((uint16_t)48000)
N#define I2S_AudioFreq_44k ((uint16_t)44100)
N#define I2S_AudioFreq_22k ((uint16_t)22050)
N#define I2S_AudioFreq_16k ((uint16_t)16000)
N#define I2S_AudioFreq_8k ((uint16_t)8000)
N#define I2S_AudioFreq_Default ((uint16_t)2)
N#define IS_I2S_AUDIO_FREQ(FREQ) (((FREQ) == I2S_AudioFreq_48k) || \
N ((FREQ) == I2S_AudioFreq_44k) || \
N ((FREQ) == I2S_AudioFreq_22k) || \
N ((FREQ) == I2S_AudioFreq_16k) || \
N ((FREQ) == I2S_AudioFreq_8k) || \
N ((FREQ) == I2S_AudioFreq_Default))
X#define IS_I2S_AUDIO_FREQ(FREQ) (((FREQ) == I2S_AudioFreq_48k) || ((FREQ) == I2S_AudioFreq_44k) || ((FREQ) == I2S_AudioFreq_22k) || ((FREQ) == I2S_AudioFreq_16k) || ((FREQ) == I2S_AudioFreq_8k) || ((FREQ) == I2S_AudioFreq_Default))
N/**
N * @}
N */
N
N/** @defgroup I2S_Clock_Polarity
N * @{
N */
N
N#define I2S_CPOL_Low ((uint16_t)0x0000)
N#define I2S_CPOL_High ((uint16_t)0x0008)
N#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
N ((CPOL) == I2S_CPOL_High))
X#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || ((CPOL) == I2S_CPOL_High))
N/**
N * @}
N */
N
N/** @defgroup SPI_I2S_DMA_transfer_requests
N * @{
N */
N
N#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
N#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
N#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
N/**
N * @}
N */
N
N/** @defgroup SPI_NSS_internal_software_mangement
N * @{
N */
N
N#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
N#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
N#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
N ((INTERNAL) == SPI_NSSInternalSoft_Reset))
X#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || ((INTERNAL) == SPI_NSSInternalSoft_Reset))
N/**
N * @}
N */
N
N/** @defgroup SPI_CRC_Transmit_Receive
N * @{
N */
N
N#define SPI_CRC_Tx ((uint8_t)0x00)
N#define SPI_CRC_Rx ((uint8_t)0x01)
N#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
N/**
N * @}
N */
N
N/** @defgroup SPI_direction_transmit_receive
N * @{
N */
N
N#define SPI_Direction_Rx ((uint16_t)0xBFFF)
N#define SPI_Direction_Tx ((uint16_t)0x4000)
N#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
N ((DIRECTION) == SPI_Direction_Tx))
X#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || ((DIRECTION) == SPI_Direction_Tx))
N/**
N * @}
N */
N
N/** @defgroup SPI_I2S_interrupts_definition
N * @{
N */
N
N#define SPI_I2S_IT_TXE ((uint8_t)0x71)
N#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
N#define SPI_I2S_IT_ERR ((uint8_t)0x50)
N#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
N ((IT) == SPI_I2S_IT_RXNE) || \
N ((IT) == SPI_I2S_IT_ERR))
X#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || ((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_ERR))
N#define SPI_I2S_IT_OVR ((uint8_t)0x56)
N#define SPI_IT_MODF ((uint8_t)0x55)
N#define SPI_IT_CRCERR ((uint8_t)0x54)
N#define I2S_IT_UDR ((uint8_t)0x53)
N#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
N#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
N ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \
N ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))
X#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))
N/**
N * @}
N */
N
N/** @defgroup SPI_I2S_flags_definition
N * @{
N */
N
N#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
N#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
N#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
N#define I2S_FLAG_UDR ((uint16_t)0x0008)
N#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
N#define SPI_FLAG_MODF ((uint16_t)0x0020)
N#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
N#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
N#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
N#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
N ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
N ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
N ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))
X#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))
N/**
N * @}
N */
N
N/** @defgroup SPI_CRC_polynomial
N * @{
N */
N
N#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/** @defgroup SPI_Exported_Macros
N * @{
N */
N
N/**
N * @}
N */
N
N/** @defgroup SPI_Exported_Functions
N * @{
N */
N
Nvoid SPI_I2S_DeInit(SPI_TypeDef *SPIx);
Nvoid SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct);
Nvoid I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct);
Nvoid SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct);
Nvoid I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct);
Nvoid SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState);
Nvoid I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState);
Nvoid SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
Nvoid SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
Nvoid SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data);
Nuint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx);
Nvoid SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft);
Nvoid SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState);
Nvoid SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize);
Nvoid SPI_TransmitCRC(SPI_TypeDef *SPIx);
Nvoid SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState);
Nuint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC);
Nuint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx);
Nvoid SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction);
NFlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG);
Nvoid SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG);
NITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT);
Nvoid SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT);
N
N#endif /*__STM32F10x_SPI_H */
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
L 45 "..\src\STM32Lib\stm32f10x_conf.h" 2
N#include "stm32f10x_tim.h"
L 1 "..\src\STM32Lib\stm32f10x_tim.h" 1
N/**
N ******************************************************************************
N * @file stm32f10x_tim.h
N * @author MCD Application Team
N * @version V3.0.0
N * @date 04/06/2009
N * @brief This file contains all the functions prototypes for the TIM firmware
N * library.
N ******************************************************************************
N * @copy
N *
N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N *
N * © COPYRIGHT 2009 STMicroelectronics
N */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F10x_TIM_H
N#define __STM32F10x_TIM_H
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f10x.h"
N
N/** @addtogroup StdPeriph_Driver
N * @{
N */
N
N/** @addtogroup TIM
N * @{
N */
N
N/** @defgroup TIM_Exported_Types
N * @{
N */
N
N/**
N * @brief TIM Time Base Init structure definition
N */
N
Ntypedef struct
N{
N uint16_t TIM_Prescaler;
N uint16_t TIM_CounterMode;
N uint16_t TIM_Period;
N uint16_t TIM_ClockDivision;
N uint8_t TIM_RepetitionCounter;
N} TIM_TimeBaseInitTypeDef;
N
N/**
N * @brief TIM Output Compare Init structure definition
N */
N
Ntypedef struct
N{
N uint16_t TIM_OCMode;
N uint16_t TIM_OutputState;
N uint16_t TIM_OutputNState;
N uint16_t TIM_Pulse;
N uint16_t TIM_OCPolarity;
N uint16_t TIM_OCNPolarity;
N uint16_t TIM_OCIdleState;
N uint16_t TIM_OCNIdleState;
N} TIM_OCInitTypeDef;
N
N/**
N * @brief TIM Input Capture Init structure definition
N */
N
Ntypedef struct
N{
N uint16_t TIM_Channel;
N uint16_t TIM_ICPolarity;
N uint16_t TIM_ICSelection;
N uint16_t TIM_ICPrescaler;
N uint16_t TIM_ICFilter;
N} TIM_ICInitTypeDef;
N
N/**
N * @brief BDTR structure definition
N */
N
Ntypedef struct
N{
N uint16_t TIM_OSSRState;
N uint16_t TIM_OSSIState;
N uint16_t TIM_LOCKLevel;
N uint16_t TIM_DeadTime;
N uint16_t TIM_Break;
N uint16_t TIM_BreakPolarity;
N uint16_t TIM_AutomaticOutput;
N} TIM_BDTRInitTypeDef;
N
N/** @defgroup TIM_Exported_constants
N * @{
N */
N
N#define IS_TIM_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == TIM4_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == TIM5_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == TIM6_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == TIM7_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == TIM8_BASE))
X#define IS_TIM_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM4_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM5_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM6_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM7_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM8_BASE))
N#define IS_TIM_18_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == TIM8_BASE))
X#define IS_TIM_18_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM8_BASE))
N#define IS_TIM_123458_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == TIM4_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == TIM5_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == TIM8_BASE))
X#define IS_TIM_123458_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM4_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM5_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM8_BASE))
N/**
N * @}
N */
N
N/** @defgroup TIM_Output_Compare_and_PWM_modes
N * @{
N */
N
N#define TIM_OCMode_Timing ((uint16_t)0x0000)
N#define TIM_OCMode_Active ((uint16_t)0x0010)
N#define TIM_OCMode_Inactive ((uint16_t)0x0020)
N#define TIM_OCMode_Toggle ((uint16_t)0x0030)
N#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
N#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
N#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
N ((MODE) == TIM_OCMode_Active) || \
N ((MODE) == TIM_OCMode_Inactive) || \
N ((MODE) == TIM_OCMode_Toggle)|| \
N ((MODE) == TIM_OCMode_PWM1) || \
N ((MODE) == TIM_OCMode_PWM2))
X#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || ((MODE) == TIM_OCMode_Active) || ((MODE) == TIM_OCMode_Inactive) || ((MODE) == TIM_OCMode_Toggle)|| ((MODE) == TIM_OCMode_PWM1) || ((MODE) == TIM_OCMode_PWM2))
N#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
N ((MODE) == TIM_OCMode_Active) || \
N ((MODE) == TIM_OCMode_Inactive) || \
N ((MODE) == TIM_OCMode_Toggle)|| \
N ((MODE) == TIM_OCMode_PWM1) || \
N ((MODE) == TIM_OCMode_PWM2) || \
N ((MODE) == TIM_ForcedAction_Active) || \
N ((MODE) == TIM_ForcedAction_InActive))
X#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || ((MODE) == TIM_OCMode_Active) || ((MODE) == TIM_OCMode_Inactive) || ((MODE) == TIM_OCMode_Toggle)|| ((MODE) == TIM_OCMode_PWM1) || ((MODE) == TIM_OCMode_PWM2) || ((MODE) == TIM_ForcedAction_Active) || ((MODE) == TIM_ForcedAction_InActive))
N/**
N * @}
N */
N
N/** @defgroup TIM_One_Pulse_Mode
N * @{
N */
N
N#define TIM_OPMode_Single ((uint16_t)0x0008)
N#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
N#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
N ((MODE) == TIM_OPMode_Repetitive))
X#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || ((MODE) == TIM_OPMode_Repetitive))
N/**
N * @}
N */
N
N/** @defgroup TIM_Channel
N * @{
N */
N
N#define TIM_Channel_1 ((uint16_t)0x0000)
N#define TIM_Channel_2 ((uint16_t)0x0004)
N#define TIM_Channel_3 ((uint16_t)0x0008)
N#define TIM_Channel_4 ((uint16_t)0x000C)
N#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
N ((CHANNEL) == TIM_Channel_2) || \
N ((CHANNEL) == TIM_Channel_3) || \
N ((CHANNEL) == TIM_Channel_4))
X#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || ((CHANNEL) == TIM_Channel_2) || ((CHANNEL) == TIM_Channel_3) || ((CHANNEL) == TIM_Channel_4))
N#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
N ((CHANNEL) == TIM_Channel_2))
X#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || ((CHANNEL) == TIM_Channel_2))
N#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
N ((CHANNEL) == TIM_Channel_2) || \
N ((CHANNEL) == TIM_Channel_3))
X#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || ((CHANNEL) == TIM_Channel_2) || ((CHANNEL) == TIM_Channel_3))
N/**
N * @}
N */
N
N/** @defgroup TIM_Clock_Division_CKD
N * @{
N */
N
N#define TIM_CKD_DIV1 ((uint16_t)0x0000)
N#define TIM_CKD_DIV2 ((uint16_t)0x0100)
N#define TIM_CKD_DIV4 ((uint16_t)0x0200)
N#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
N ((DIV) == TIM_CKD_DIV2) || \
N ((DIV) == TIM_CKD_DIV4))
X#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || ((DIV) == TIM_CKD_DIV2) || ((DIV) == TIM_CKD_DIV4))
N/**
N * @}
N */
N
N/** @defgroup TIM_Counter_Mode
N * @{
N */
N
N#define TIM_CounterMode_Up ((uint16_t)0x0000)
N#define TIM_CounterMode_Down ((uint16_t)0x0010)
N#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
N#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
N#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
N#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
N ((MODE) == TIM_CounterMode_Down) || \
N ((MODE) == TIM_CounterMode_CenterAligned1) || \
N ((MODE) == TIM_CounterMode_CenterAligned2) || \
N ((MODE) == TIM_CounterMode_CenterAligned3))
X#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || ((MODE) == TIM_CounterMode_Down) || ((MODE) == TIM_CounterMode_CenterAligned1) || ((MODE) == TIM_CounterMode_CenterAligned2) || ((MODE) == TIM_CounterMode_CenterAligned3))
N/**
N * @}
N */
N
N/** @defgroup TIM_Output_Compare_Polarity
N * @{
N */
N
N#define TIM_OCPolarity_High ((uint16_t)0x0000)
N#define TIM_OCPolarity_Low ((uint16_t)0x0002)
N#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
N ((POLARITY) == TIM_OCPolarity_Low))
X#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || ((POLARITY) == TIM_OCPolarity_Low))
N/**
N * @}
N */
N
N/** @defgroup TIM_Output_Compare_N_Polarity
N * @{
N */
N
N#define TIM_OCNPolarity_High ((uint16_t)0x0000)
N#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
N#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
N ((POLARITY) == TIM_OCNPolarity_Low))
X#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || ((POLARITY) == TIM_OCNPolarity_Low))
N/**
N * @}
N */
N
N/** @defgroup TIM_Output_Compare_states
N * @{
N */
N
N#define TIM_OutputState_Disable ((uint16_t)0x0000)
N#define TIM_OutputState_Enable ((uint16_t)0x0001)
N#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
N ((STATE) == TIM_OutputState_Enable))
X#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || ((STATE) == TIM_OutputState_Enable))
N/**
N * @}
N */
N
N/** @defgroup TIM_Output_Compare_N_States
N * @{
N */
N
N#define TIM_OutputNState_Disable ((uint16_t)0x0000)
N#define TIM_OutputNState_Enable ((uint16_t)0x0004)
N#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
N ((STATE) == TIM_OutputNState_Enable))
X#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || ((STATE) == TIM_OutputNState_Enable))
N/**
N * @}
N */
N
N/** @defgroup TIM_Capture_Compare_States
N * @{
N */
N
N#define TIM_CCx_Enable ((uint16_t)0x0001)
N#define TIM_CCx_Disable ((uint16_t)0x0000)
N#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
N ((CCX) == TIM_CCx_Disable))
X#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || ((CCX) == TIM_CCx_Disable))
N/**
N * @}
N */
N
N/** @defgroup TIM_Capture_Compare_N_States
N * @{
N */
N
N#define TIM_CCxN_Enable ((uint16_t)0x0004)
N#define TIM_CCxN_Disable ((uint16_t)0x0000)
N#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
N ((CCXN) == TIM_CCxN_Disable))
X#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || ((CCXN) == TIM_CCxN_Disable))
N/**
N * @}
N */
N
N/** @defgroup Break_Input_enable_disable
N * @{
N */
N
N#define TIM_Break_Enable ((uint16_t)0x1000)
N#define TIM_Break_Disable ((uint16_t)0x0000)
N#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
N ((STATE) == TIM_Break_Disable))
X#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || ((STATE) == TIM_Break_Disable))
N/**
N * @}
N */
N
N/** @defgroup Break_Polarity
N * @{
N */
N
N#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
N#define TIM_BreakPolarity_High ((uint16_t)0x2000)
N#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
N ((POLARITY) == TIM_BreakPolarity_High))
X#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || ((POLARITY) == TIM_BreakPolarity_High))
N/**
N * @}
N */
N
N/** @defgroup TIM_AOE_Bit_Set_Reset
N * @{
N */
N
N#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
N#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
N#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
N ((STATE) == TIM_AutomaticOutput_Disable))
X#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || ((STATE) == TIM_AutomaticOutput_Disable))
N/**
N * @}
N */
N
N/** @defgroup Lock_levels
N * @{
N */
N
N#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
N#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
N#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
N#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
N#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
N ((LEVEL) == TIM_LOCKLevel_1) || \
N ((LEVEL) == TIM_LOCKLevel_2) || \
N ((LEVEL) == TIM_LOCKLevel_3))
X#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || ((LEVEL) == TIM_LOCKLevel_1) || ((LEVEL) == TIM_LOCKLevel_2) || ((LEVEL) == TIM_LOCKLevel_3))
N/**
N * @}
N */
N
N/** @defgroup OSSI:_Off-State_Selection_for_Idle_mode_states
N * @{
N */
N
N#define TIM_OSSIState_Enable ((uint16_t)0x0400)
N#define TIM_OSSIState_Disable ((uint16_t)0x0000)
N#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
N ((STATE) == TIM_OSSIState_Disable))
X#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || ((STATE) == TIM_OSSIState_Disable))
N/**
N * @}
N */
N
N/** @defgroup OSSR:_Off-State_Selection_for_Run_mode_states
N * @{
N */
N
N#define TIM_OSSRState_Enable ((uint16_t)0x0800)
N#define TIM_OSSRState_Disable ((uint16_t)0x0000)
N#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
N ((STATE) == TIM_OSSRState_Disable))
X#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || ((STATE) == TIM_OSSRState_Disable))
N/**
N * @}
N */
N
N/** @defgroup TIM_Output_Compare_Idle_State
N * @{
N */
N
N#define TIM_OCIdleState_Set ((uint16_t)0x0100)
N#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
N#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
N ((STATE) == TIM_OCIdleState_Reset))
X#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || ((STATE) == TIM_OCIdleState_Reset))
N/**
N * @}
N */
N
N/** @defgroup TIM_Output_Compare_N_Idle_State
N * @{
N */
N
N#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
N#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
N#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
N ((STATE) == TIM_OCNIdleState_Reset))
X#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || ((STATE) == TIM_OCNIdleState_Reset))
N/**
N * @}
N */
N
N/** @defgroup TIM_Input_Capture_Polarity
N * @{
N */
N
N#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
N#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
N#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
N ((POLARITY) == TIM_ICPolarity_Falling))
X#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || ((POLARITY) == TIM_ICPolarity_Falling))
N/**
N * @}
N */
N
N/** @defgroup TIM_Input_Capture_Selection
N * @{
N */
N
N#define TIM_ICSelection_DirectTI ((uint16_t)0x0001)
N#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002)
N#define TIM_ICSelection_TRC ((uint16_t)0x0003)
N#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
N ((SELECTION) == TIM_ICSelection_IndirectTI) || \
N ((SELECTION) == TIM_ICSelection_TRC))
X#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || ((SELECTION) == TIM_ICSelection_IndirectTI) || ((SELECTION) == TIM_ICSelection_TRC))
N/**
N * @}
N */
N
N/** @defgroup TIM_Input_Capture_Prescaler
N * @{
N */
N
N#define TIM_ICPSC_DIV1 ((uint16_t)0x0000)
N#define TIM_ICPSC_DIV2 ((uint16_t)0x0004)
N#define TIM_ICPSC_DIV4 ((uint16_t)0x0008)
N#define TIM_ICPSC_DIV8 ((uint16_t)0x000C)
N#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
N ((PRESCALER) == TIM_ICPSC_DIV2) || \
N ((PRESCALER) == TIM_ICPSC_DIV4) || \
N ((PRESCALER) == TIM_ICPSC_DIV8))
X#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || ((PRESCALER) == TIM_ICPSC_DIV2) || ((PRESCALER) == TIM_ICPSC_DIV4) || ((PRESCALER) == TIM_ICPSC_DIV8))
N/**
N * @}
N */
N
N/** @defgroup TIM_interrupt_sources
N * @{
N */
N
N#define TIM_IT_Update ((uint16_t)0x0001)
N#define TIM_IT_CC1 ((uint16_t)0x0002)
N#define TIM_IT_CC2 ((uint16_t)0x0004)
N#define TIM_IT_CC3 ((uint16_t)0x0008)
N#define TIM_IT_CC4 ((uint16_t)0x0010)
N#define TIM_IT_COM ((uint16_t)0x0020)
N#define TIM_IT_Trigger ((uint16_t)0x0040)
N#define TIM_IT_Break ((uint16_t)0x0080)
N#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
N#define IS_TIM_PERIPH_IT(PERIPH, TIM_IT) ((((((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||\
N (((*(uint32_t*)&(PERIPH)) == TIM4_BASE)) || (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))))&& \
N (((TIM_IT) & (uint16_t)0xFFA0) == 0x0000) && ((TIM_IT) != 0x0000)) ||\
N (((((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM8_BASE))))&& \
N (((TIM_IT) & (uint16_t)0xFF00) == 0x0000) && ((TIM_IT) != 0x0000)) ||\
N (((((*(uint32_t*)&(PERIPH)) == TIM6_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM7_BASE))))&& \
N (((TIM_IT) & (uint16_t)0xFFFE) == 0x0000) && ((TIM_IT) != 0x0000)))
X#define IS_TIM_PERIPH_IT(PERIPH, TIM_IT) ((((((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))|| (((*(uint32_t*)&(PERIPH)) == TIM4_BASE)) || (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))))&& (((TIM_IT) & (uint16_t)0xFFA0) == 0x0000) && ((TIM_IT) != 0x0000)) || (((((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM8_BASE))))&& (((TIM_IT) & (uint16_t)0xFF00) == 0x0000) && ((TIM_IT) != 0x0000)) || (((((*(uint32_t*)&(PERIPH)) == TIM6_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM7_BASE))))&& (((TIM_IT) & (uint16_t)0xFFFE) == 0x0000) && ((TIM_IT) != 0x0000)))
N#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
N ((IT) == TIM_IT_CC1) || \
N ((IT) == TIM_IT_CC2) || \
N ((IT) == TIM_IT_CC3) || \
N ((IT) == TIM_IT_CC4) || \
N ((IT) == TIM_IT_COM) || \
N ((IT) == TIM_IT_Trigger) || \
N ((IT) == TIM_IT_Break))
X#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || ((IT) == TIM_IT_CC1) || ((IT) == TIM_IT_CC2) || ((IT) == TIM_IT_CC3) || ((IT) == TIM_IT_CC4) || ((IT) == TIM_IT_COM) || ((IT) == TIM_IT_Trigger) || ((IT) == TIM_IT_Break))
N/**
N * @}
N */
N
N/** @defgroup TIM_DMA_Base_address
N * @{
N */
N
N#define TIM_DMABase_CR1 ((uint16_t)0x0000)
N#define TIM_DMABase_CR2 ((uint16_t)0x0001)
N#define TIM_DMABase_SMCR ((uint16_t)0x0002)
N#define TIM_DMABase_DIER ((uint16_t)0x0003)
N#define TIM_DMABase_SR ((uint16_t)0x0004)
N#define TIM_DMABase_EGR ((uint16_t)0x0005)
N#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
N#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
N#define TIM_DMABase_CCER ((uint16_t)0x0008)
N#define TIM_DMABase_CNT ((uint16_t)0x0009)
N#define TIM_DMABase_PSC ((uint16_t)0x000A)
N#define TIM_DMABase_ARR ((uint16_t)0x000B)
N#define TIM_DMABase_RCR ((uint16_t)0x000C)
N#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
N#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
N#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
N#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
N#define TIM_DMABase_BDTR ((uint16_t)0x0011)
N#define TIM_DMABase_DCR ((uint16_t)0x0012)
N#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
N ((BASE) == TIM_DMABase_CR2) || \
N ((BASE) == TIM_DMABase_SMCR) || \
N ((BASE) == TIM_DMABase_DIER) || \
N ((BASE) == TIM_DMABase_SR) || \
N ((BASE) == TIM_DMABase_EGR) || \
N ((BASE) == TIM_DMABase_CCMR1) || \
N ((BASE) == TIM_DMABase_CCMR2) || \
N ((BASE) == TIM_DMABase_CCER) || \
N ((BASE) == TIM_DMABase_CNT) || \
N ((BASE) == TIM_DMABase_PSC) || \
N ((BASE) == TIM_DMABase_ARR) || \
N ((BASE) == TIM_DMABase_RCR) || \
N ((BASE) == TIM_DMABase_CCR1) || \
N ((BASE) == TIM_DMABase_CCR2) || \
N ((BASE) == TIM_DMABase_CCR3) || \
N ((BASE) == TIM_DMABase_CCR4) || \
N ((BASE) == TIM_DMABase_BDTR) || \
N ((BASE) == TIM_DMABase_DCR))
X#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || ((BASE) == TIM_DMABase_CR2) || ((BASE) == TIM_DMABase_SMCR) || ((BASE) == TIM_DMABase_DIER) || ((BASE) == TIM_DMABase_SR) || ((BASE) == TIM_DMABase_EGR) || ((BASE) == TIM_DMABase_CCMR1) || ((BASE) == TIM_DMABase_CCMR2) || ((BASE) == TIM_DMABase_CCER) || ((BASE) == TIM_DMABase_CNT) || ((BASE) == TIM_DMABase_PSC) || ((BASE) == TIM_DMABase_ARR) || ((BASE) == TIM_DMABase_RCR) || ((BASE) == TIM_DMABase_CCR1) || ((BASE) == TIM_DMABase_CCR2) || ((BASE) == TIM_DMABase_CCR3) || ((BASE) == TIM_DMABase_CCR4) || ((BASE) == TIM_DMABase_BDTR) || ((BASE) == TIM_DMABase_DCR))
N/**
N * @}
N */
N
N/** @defgroup TIM_DMA_Burst_Length
N * @{
N */
N
N#define TIM_DMABurstLength_1Byte ((uint16_t)0x0000)
N#define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100)
N#define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200)
N#define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300)
N#define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400)
N#define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500)
N#define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600)
N#define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700)
N#define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800)
N#define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900)
N#define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00)
N#define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00)
N#define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00)
N#define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00)
N#define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00)
N#define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00)
N#define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000)
N#define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100)
N#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \
N ((LENGTH) == TIM_DMABurstLength_2Bytes) || \
N ((LENGTH) == TIM_DMABurstLength_3Bytes) || \
N ((LENGTH) == TIM_DMABurstLength_4Bytes) || \
N ((LENGTH) == TIM_DMABurstLength_5Bytes) || \
N ((LENGTH) == TIM_DMABurstLength_6Bytes) || \
N ((LENGTH) == TIM_DMABurstLength_7Bytes) || \
N ((LENGTH) == TIM_DMABurstLength_8Bytes) || \
N ((LENGTH) == TIM_DMABurstLength_9Bytes) || \
N ((LENGTH) == TIM_DMABurstLength_10Bytes) || \
N ((LENGTH) == TIM_DMABurstLength_11Bytes) || \
N ((LENGTH) == TIM_DMABurstLength_12Bytes) || \
N ((LENGTH) == TIM_DMABurstLength_13Bytes) || \
N ((LENGTH) == TIM_DMABurstLength_14Bytes) || \
N ((LENGTH) == TIM_DMABurstLength_15Bytes) || \
N ((LENGTH) == TIM_DMABurstLength_16Bytes) || \
N ((LENGTH) == TIM_DMABurstLength_17Bytes) || \
N ((LENGTH) == TIM_DMABurstLength_18Bytes))
X#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || ((LENGTH) == TIM_DMABurstLength_2Bytes) || ((LENGTH) == TIM_DMABurstLength_3Bytes) || ((LENGTH) == TIM_DMABurstLength_4Bytes) || ((LENGTH) == TIM_DMABurstLength_5Bytes) || ((LENGTH) == TIM_DMABurstLength_6Bytes) || ((LENGTH) == TIM_DMABurstLength_7Bytes) || ((LENGTH) == TIM_DMABurstLength_8Bytes) || ((LENGTH) == TIM_DMABurstLength_9Bytes) || ((LENGTH) == TIM_DMABurstLength_10Bytes) || ((LENGTH) == TIM_DMABurstLength_11Bytes) || ((LENGTH) == TIM_DMABurstLength_12Bytes) || ((LENGTH) == TIM_DMABurstLength_13Bytes) || ((LENGTH) == TIM_DMABurstLength_14Bytes) || ((LENGTH) == TIM_DMABurstLength_15Bytes) || ((LENGTH) == TIM_DMABurstLength_16Bytes) || ((LENGTH) == TIM_DMABurstLength_17Bytes) || ((LENGTH) == TIM_DMABurstLength_18Bytes))
N/**
N * @}
N */
N
N/** @defgroup TIM_DMA_sources
N * @{
N */
N
N#define TIM_DMA_Update ((uint16_t)0x0100)
N#define TIM_DMA_CC1 ((uint16_t)0x0200)
N#define TIM_DMA_CC2 ((uint16_t)0x0400)
N#define TIM_DMA_CC3 ((uint16_t)0x0800)
N#define TIM_DMA_CC4 ((uint16_t)0x1000)
N#define TIM_DMA_COM ((uint16_t)0x2000)
N#define TIM_DMA_Trigger ((uint16_t)0x4000)
N#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
N#define IS_TIM_PERIPH_DMA(PERIPH, SOURCE) ((((((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||\
N (((*(uint32_t*)&(PERIPH)) == TIM4_BASE)) || (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))))&& \
N (((SOURCE) & (uint16_t)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000)) ||\
N (((((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM8_BASE))))&& \
N (((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) ||\
N (((((*(uint32_t*)&(PERIPH)) == TIM6_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM7_BASE))))&& \
N (((SOURCE) & (uint16_t)0xFEFF) == 0x0000) && ((SOURCE) != 0x0000)))
X#define IS_TIM_PERIPH_DMA(PERIPH, SOURCE) ((((((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))|| (((*(uint32_t*)&(PERIPH)) == TIM4_BASE)) || (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))))&& (((SOURCE) & (uint16_t)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000)) || (((((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM8_BASE))))&& (((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) || (((((*(uint32_t*)&(PERIPH)) == TIM6_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM7_BASE))))&& (((SOURCE) & (uint16_t)0xFEFF) == 0x0000) && ((SOURCE) != 0x0000)))
N/**
N * @}
N */
N
N/** @defgroup TIM_External_Trigger_Prescaler
N * @{
N */
N
N#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
N#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
N#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
N#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
N#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
N ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
N ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
N ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
X#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
N/**
N * @}
N */
N
N/** @defgroup TIM_Internal_Trigger_Selection
N * @{
N */
N
N#define TIM_TS_ITR0 ((uint16_t)0x0000)
N#define TIM_TS_ITR1 ((uint16_t)0x0010)
N#define TIM_TS_ITR2 ((uint16_t)0x0020)
N#define TIM_TS_ITR3 ((uint16_t)0x0030)
N#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
N#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
N#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
N#define TIM_TS_ETRF ((uint16_t)0x0070)
N#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
N ((SELECTION) == TIM_TS_ITR1) || \
N ((SELECTION) == TIM_TS_ITR2) || \
N ((SELECTION) == TIM_TS_ITR3) || \
N ((SELECTION) == TIM_TS_TI1F_ED) || \
N ((SELECTION) == TIM_TS_TI1FP1) || \
N ((SELECTION) == TIM_TS_TI2FP2) || \
N ((SELECTION) == TIM_TS_ETRF))
X#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || ((SELECTION) == TIM_TS_ITR1) || ((SELECTION) == TIM_TS_ITR2) || ((SELECTION) == TIM_TS_ITR3) || ((SELECTION) == TIM_TS_TI1F_ED) || ((SELECTION) == TIM_TS_TI1FP1) || ((SELECTION) == TIM_TS_TI2FP2) || ((SELECTION) == TIM_TS_ETRF))
N#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
N ((SELECTION) == TIM_TS_ITR1) || \
N ((SELECTION) == TIM_TS_ITR2) || \
N ((SELECTION) == TIM_TS_ITR3))
X#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || ((SELECTION) == TIM_TS_ITR1) || ((SELECTION) == TIM_TS_ITR2) || ((SELECTION) == TIM_TS_ITR3))
N/**
N * @}
N */
N
N/** @defgroup TIM_TIx_External_Clock_Source
N * @{
N */
N
N#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
N#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
N#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
N#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \
N ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \
N ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))
X#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))
N/**
N * @}
N */
N
N/** @defgroup TIM_External_Trigger_Polarity
N * @{
N */
N#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
N#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
N#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
N ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
X#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
N/**
N * @}
N */
N
N/** @defgroup TIM_Prescaler_Reload_Mode
N * @{
N */
N
N#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
N#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
N#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
N ((RELOAD) == TIM_PSCReloadMode_Immediate))
X#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || ((RELOAD) == TIM_PSCReloadMode_Immediate))
N/**
N * @}
N */
N
N/** @defgroup TIM_Forced_Action
N * @{
N */
N
N#define TIM_ForcedAction_Active ((uint16_t)0x0050)
N#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
N#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
N ((ACTION) == TIM_ForcedAction_InActive))
X#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || ((ACTION) == TIM_ForcedAction_InActive))
N/**
N * @}
N */
N
N/** @defgroup TIM_Encoder_Mode
N * @{
N */
N
N#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
N#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
N#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
N#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
N ((MODE) == TIM_EncoderMode_TI2) || \
N ((MODE) == TIM_EncoderMode_TI12))
X#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || ((MODE) == TIM_EncoderMode_TI2) || ((MODE) == TIM_EncoderMode_TI12))
N/**
N * @}
N */
N
N
N/** @defgroup TIM_Event_Source
N * @{
N */
N
N#define TIM_EventSource_Update ((uint16_t)0x0001)
N#define TIM_EventSource_CC1 ((uint16_t)0x0002)
N#define TIM_EventSource_CC2 ((uint16_t)0x0004)
N#define TIM_EventSource_CC3 ((uint16_t)0x0008)
N#define TIM_EventSource_CC4 ((uint16_t)0x0010)
N#define TIM_EventSource_COM ((uint16_t)0x0020)
N#define TIM_EventSource_Trigger ((uint16_t)0x0040)
N#define TIM_EventSource_Break ((uint16_t)0x0080)
N#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
N#define IS_TIM_PERIPH_EVENT(PERIPH, EVENT) ((((((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||\
N (((*(uint32_t*)&(PERIPH)) == TIM4_BASE)) || (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))))&& \
N (((EVENT) & (uint16_t)0xFFA0) == 0x0000) && ((EVENT) != 0x0000)) ||\
N (((((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM8_BASE))))&& \
N (((EVENT) & (uint16_t)0xFF00) == 0x0000) && ((EVENT) != 0x0000)) ||\
N (((((*(uint32_t*)&(PERIPH)) == TIM6_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM7_BASE))))&& \
N (((EVENT) & (uint16_t)0xFFFE) == 0x0000) && ((EVENT) != 0x0000)))
X#define IS_TIM_PERIPH_EVENT(PERIPH, EVENT) ((((((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))|| (((*(uint32_t*)&(PERIPH)) == TIM4_BASE)) || (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))))&& (((EVENT) & (uint16_t)0xFFA0) == 0x0000) && ((EVENT) != 0x0000)) || (((((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM8_BASE))))&& (((EVENT) & (uint16_t)0xFF00) == 0x0000) && ((EVENT) != 0x0000)) || (((((*(uint32_t*)&(PERIPH)) == TIM6_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM7_BASE))))&& (((EVENT) & (uint16_t)0xFFFE) == 0x0000) && ((EVENT) != 0x0000)))
N/**
N * @}
N */
N
N/** @defgroup TIM_Update_Source
N * @{
N */
N
N#define TIM_UpdateSource_Global ((uint16_t)0x0000)
N#define TIM_UpdateSource_Regular ((uint16_t)0x0001)
N#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
N ((SOURCE) == TIM_UpdateSource_Regular))
X#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || ((SOURCE) == TIM_UpdateSource_Regular))
N/**
N * @}
N */
N
N/** @defgroup TIM_Ouput_Compare_Preload_State
N * @{
N */
N
N#define TIM_OCPreload_Enable ((uint16_t)0x0008)
N#define TIM_OCPreload_Disable ((uint16_t)0x0000)
N#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
N ((STATE) == TIM_OCPreload_Disable))
X#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || ((STATE) == TIM_OCPreload_Disable))
N/**
N * @}
N */
N
N/** @defgroup TIM_Ouput_Compare_Fast_State
N * @{
N */
N
N#define TIM_OCFast_Enable ((uint16_t)0x0004)
N#define TIM_OCFast_Disable ((uint16_t)0x0000)
N#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
N ((STATE) == TIM_OCFast_Disable))
X#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || ((STATE) == TIM_OCFast_Disable))
N
N/**
N * @}
N */
N
N/** @defgroup TIM_Ouput_Compare_Clear_State
N * @{
N */
N
N#define TIM_OCClear_Enable ((uint16_t)0x0080)
N#define TIM_OCClear_Disable ((uint16_t)0x0000)
N#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
N ((STATE) == TIM_OCClear_Disable))
X#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || ((STATE) == TIM_OCClear_Disable))
N/**
N * @}
N */
N
N/** @defgroup TIM_Trigger_Output_Source
N * @{
N */
N
N#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
N#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
N#define TIM_TRGOSource_Update ((uint16_t)0x0020)
N#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
N#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
N#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
N#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
N#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
N#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
N ((SOURCE) == TIM_TRGOSource_Enable) || \
N ((SOURCE) == TIM_TRGOSource_Update) || \
N ((SOURCE) == TIM_TRGOSource_OC1) || \
N ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
N ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
N ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
N ((SOURCE) == TIM_TRGOSource_OC4Ref))
X#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || ((SOURCE) == TIM_TRGOSource_Enable) || ((SOURCE) == TIM_TRGOSource_Update) || ((SOURCE) == TIM_TRGOSource_OC1) || ((SOURCE) == TIM_TRGOSource_OC1Ref) || ((SOURCE) == TIM_TRGOSource_OC2Ref) || ((SOURCE) == TIM_TRGOSource_OC3Ref) || ((SOURCE) == TIM_TRGOSource_OC4Ref))
N#define IS_TIM_PERIPH_TRGO(PERIPH, TRGO) (((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\
N (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \
N (((*(uint32_t*)&(PERIPH)) == TIM6_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM7_BASE))|| \
N (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \
N ((TRGO) == TIM_TRGOSource_Reset)) ||\
N ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\
N (((*(uint32_t*)&(PERIPH)) == TIM6_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM7_BASE))|| \
N (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \
N (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \
N ((TRGO) == TIM_TRGOSource_Enable)) ||\
N ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\
N (((*(uint32_t*)&(PERIPH)) == TIM6_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM7_BASE))|| \
N (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \
N (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \
N ((TRGO) == TIM_TRGOSource_Update)) ||\
N ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\
N (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \
N (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \
N ((TRGO) == TIM_TRGOSource_OC1)) ||\
N ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\
N (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \
N (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \
N ((TRGO) == TIM_TRGOSource_OC1Ref)) ||\
N ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\
N (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \
N (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \
N ((TRGO) == TIM_TRGOSource_OC2Ref)) ||\
N ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\
N (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \
N (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \
N ((TRGO) == TIM_TRGOSource_OC3Ref)) ||\
N ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\
N (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \
N (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \
N ((TRGO) == TIM_TRGOSource_OC4Ref)))
X#define IS_TIM_PERIPH_TRGO(PERIPH, TRGO) (((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))|| (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| (((*(uint32_t*)&(PERIPH)) == TIM6_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM7_BASE))|| (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && ((TRGO) == TIM_TRGOSource_Reset)) || ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))|| (((*(uint32_t*)&(PERIPH)) == TIM6_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM7_BASE))|| (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && ((TRGO) == TIM_TRGOSource_Enable)) || ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))|| (((*(uint32_t*)&(PERIPH)) == TIM6_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM7_BASE))|| (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && ((TRGO) == TIM_TRGOSource_Update)) || ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))|| (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && ((TRGO) == TIM_TRGOSource_OC1)) || ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))|| (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && ((TRGO) == TIM_TRGOSource_OC1Ref)) || ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))|| (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && ((TRGO) == TIM_TRGOSource_OC2Ref)) || ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))|| (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && ((TRGO) == TIM_TRGOSource_OC3Ref)) || ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))|| (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && ((TRGO) == TIM_TRGOSource_OC4Ref)))
N/**
N * @}
N */
N
N/** @defgroup TIM_Slave_Mode
N * @{
N */
N
N#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
N#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
N#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
N#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
N#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
N ((MODE) == TIM_SlaveMode_Gated) || \
N ((MODE) == TIM_SlaveMode_Trigger) || \
N ((MODE) == TIM_SlaveMode_External1))
X#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || ((MODE) == TIM_SlaveMode_Gated) || ((MODE) == TIM_SlaveMode_Trigger) || ((MODE) == TIM_SlaveMode_External1))
N/**
N * @}
N */
N
N/** @defgroup TIM_Master_Slave_Mode
N * @{
N */
N
N#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
N#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
N#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
N ((STATE) == TIM_MasterSlaveMode_Disable))
X#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || ((STATE) == TIM_MasterSlaveMode_Disable))
N/**
N * @}
N */
N
N/** @defgroup TIM_Flags
N * @{
N */
N
N#define TIM_FLAG_Update ((uint16_t)0x0001)
N#define TIM_FLAG_CC1 ((uint16_t)0x0002)
N#define TIM_FLAG_CC2 ((uint16_t)0x0004)
N#define TIM_FLAG_CC3 ((uint16_t)0x0008)
N#define TIM_FLAG_CC4 ((uint16_t)0x0010)
N#define TIM_FLAG_COM ((uint16_t)0x0020)
N#define TIM_FLAG_Trigger ((uint16_t)0x0040)
N#define TIM_FLAG_Break ((uint16_t)0x0080)
N#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
N#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
N#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
N#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
N#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
N ((FLAG) == TIM_FLAG_CC1) || \
N ((FLAG) == TIM_FLAG_CC2) || \
N ((FLAG) == TIM_FLAG_CC3) || \
N ((FLAG) == TIM_FLAG_CC4) || \
N ((FLAG) == TIM_FLAG_COM) || \
N ((FLAG) == TIM_FLAG_Trigger) || \
N ((FLAG) == TIM_FLAG_Break) || \
N ((FLAG) == TIM_FLAG_CC1OF) || \
N ((FLAG) == TIM_FLAG_CC2OF) || \
N ((FLAG) == TIM_FLAG_CC3OF) || \
N ((FLAG) == TIM_FLAG_CC4OF))
X#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || ((FLAG) == TIM_FLAG_CC1) || ((FLAG) == TIM_FLAG_CC2) || ((FLAG) == TIM_FLAG_CC3) || ((FLAG) == TIM_FLAG_CC4) || ((FLAG) == TIM_FLAG_COM) || ((FLAG) == TIM_FLAG_Trigger) || ((FLAG) == TIM_FLAG_Break) || ((FLAG) == TIM_FLAG_CC1OF) || ((FLAG) == TIM_FLAG_CC2OF) || ((FLAG) == TIM_FLAG_CC3OF) || ((FLAG) == TIM_FLAG_CC4OF))
N#define IS_TIM_CLEAR_FLAG(PERIPH, TIM_FLAG) ((((((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||\
N (((*(uint32_t*)&(PERIPH)) == TIM4_BASE)) || (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))))&& \
N (((TIM_FLAG) & (uint16_t)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000)) ||\
N (((((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM8_BASE))))&& \
N (((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) ||\
N (((((*(uint32_t*)&(PERIPH)) == TIM6_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM7_BASE))))&& \
N (((TIM_FLAG) & (uint16_t)0xFFFE) == 0x0000) && ((TIM_FLAG) != 0x0000)))
X#define IS_TIM_CLEAR_FLAG(PERIPH, TIM_FLAG) ((((((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))|| (((*(uint32_t*)&(PERIPH)) == TIM4_BASE)) || (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))))&& (((TIM_FLAG) & (uint16_t)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000)) || (((((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM8_BASE))))&& (((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) || (((((*(uint32_t*)&(PERIPH)) == TIM6_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM7_BASE))))&& (((TIM_FLAG) & (uint16_t)0xFFFE) == 0x0000) && ((TIM_FLAG) != 0x0000)))
N#define IS_TIM_PERIPH_FLAG(PERIPH, TIM_FLAG) (((((*(uint32_t*)&(PERIPH))==TIM2_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) ||\
N ((*(uint32_t*)&(PERIPH)) == TIM4_BASE) || ((*(uint32_t*)&(PERIPH))==TIM5_BASE) || \
N ((*(uint32_t*)&(PERIPH))==TIM1_BASE) || ((*(uint32_t*)&(PERIPH))==TIM8_BASE)) &&\
N (((TIM_FLAG) == TIM_FLAG_CC1) || ((TIM_FLAG) == TIM_FLAG_CC2) ||\
N ((TIM_FLAG) == TIM_FLAG_CC3) || ((TIM_FLAG) == TIM_FLAG_CC4) || \
N ((TIM_FLAG) == TIM_FLAG_Trigger))) ||\
N ((((*(uint32_t*)&(PERIPH))==TIM2_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == TIM4_BASE) || ((*(uint32_t*)&(PERIPH))==TIM5_BASE) ||\
N ((*(uint32_t*)&(PERIPH))==TIM1_BASE)|| ((*(uint32_t*)&(PERIPH))==TIM8_BASE) || \
N ((*(uint32_t*)&(PERIPH))==TIM7_BASE) || ((*(uint32_t*)&(PERIPH))==TIM6_BASE)) && \
N (((TIM_FLAG) == TIM_FLAG_Update))) ||\
N ((((*(uint32_t*)&(PERIPH))==TIM1_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM8_BASE)) &&\
N (((TIM_FLAG) == TIM_FLAG_COM) || ((TIM_FLAG) == TIM_FLAG_Break))) ||\
N ((((*(uint32_t*)&(PERIPH))==TIM2_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == TIM4_BASE) || ((*(uint32_t*)&(PERIPH))==TIM5_BASE) || \
N ((*(uint32_t*)&(PERIPH))==TIM1_BASE) || ((*(uint32_t*)&(PERIPH))==TIM8_BASE)) &&\
N (((TIM_FLAG) == TIM_FLAG_CC1OF) || ((TIM_FLAG) == TIM_FLAG_CC2OF) ||\
N ((TIM_FLAG) == TIM_FLAG_CC3OF) || ((TIM_FLAG) == TIM_FLAG_CC4OF))))
X#define IS_TIM_PERIPH_FLAG(PERIPH, TIM_FLAG) (((((*(uint32_t*)&(PERIPH))==TIM2_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM4_BASE) || ((*(uint32_t*)&(PERIPH))==TIM5_BASE) || ((*(uint32_t*)&(PERIPH))==TIM1_BASE) || ((*(uint32_t*)&(PERIPH))==TIM8_BASE)) && (((TIM_FLAG) == TIM_FLAG_CC1) || ((TIM_FLAG) == TIM_FLAG_CC2) || ((TIM_FLAG) == TIM_FLAG_CC3) || ((TIM_FLAG) == TIM_FLAG_CC4) || ((TIM_FLAG) == TIM_FLAG_Trigger))) || ((((*(uint32_t*)&(PERIPH))==TIM2_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM4_BASE) || ((*(uint32_t*)&(PERIPH))==TIM5_BASE) || ((*(uint32_t*)&(PERIPH))==TIM1_BASE)|| ((*(uint32_t*)&(PERIPH))==TIM8_BASE) || ((*(uint32_t*)&(PERIPH))==TIM7_BASE) || ((*(uint32_t*)&(PERIPH))==TIM6_BASE)) && (((TIM_FLAG) == TIM_FLAG_Update))) || ((((*(uint32_t*)&(PERIPH))==TIM1_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM8_BASE)) && (((TIM_FLAG) == TIM_FLAG_COM) || ((TIM_FLAG) == TIM_FLAG_Break))) || ((((*(uint32_t*)&(PERIPH))==TIM2_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM4_BASE) || ((*(uint32_t*)&(PERIPH))==TIM5_BASE) || ((*(uint32_t*)&(PERIPH))==TIM1_BASE) || ((*(uint32_t*)&(PERIPH))==TIM8_BASE)) && (((TIM_FLAG) == TIM_FLAG_CC1OF) || ((TIM_FLAG) == TIM_FLAG_CC2OF) || ((TIM_FLAG) == TIM_FLAG_CC3OF) || ((TIM_FLAG) == TIM_FLAG_CC4OF))))
N
N/**
N * @}
N */
N
N/** @defgroup TIM_Input_Capture_Filer_Value
N * @{
N */
N
N#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
N/**
N * @}
N */
N
N/** @defgroup TIM_External_Trigger_Filter
N * @{
N */
N
N#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/** @defgroup TIM_Exported_Macros
N * @{
N */
N
N/**
N * @}
N */
N
N/** @defgroup TIM_Exported_Functions
N * @{
N */
N
Nvoid TIM_DeInit(TIM_TypeDef *TIMx);
Nvoid TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct);
Nvoid TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
Nvoid TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
Nvoid TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
Nvoid TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
Nvoid TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct);
Nvoid TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct);
Nvoid TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
Nvoid TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct);
Nvoid TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct);
Nvoid TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct);
Nvoid TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
Nvoid TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState);
Nvoid TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState);
Nvoid TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState);
Nvoid TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource);
Nvoid TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
Nvoid TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
Nvoid TIM_InternalClockConfig(TIM_TypeDef *TIMx);
Nvoid TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource);
Nvoid TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource,
N uint16_t TIM_ICPolarity, uint16_t ICFilter);
Nvoid TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
N uint16_t ExtTRGFilter);
Nvoid TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler,
N uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
Nvoid TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
N uint16_t ExtTRGFilter);
Nvoid TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
Nvoid TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode);
Nvoid TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource);
Nvoid TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode,
N uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
Nvoid TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
Nvoid TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
Nvoid TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
Nvoid TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
Nvoid TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState);
Nvoid TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState);
Nvoid TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState);
Nvoid TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState);
Nvoid TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
Nvoid TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
Nvoid TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
Nvoid TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
Nvoid TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
Nvoid TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
Nvoid TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
Nvoid TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
Nvoid TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
Nvoid TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
Nvoid TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
Nvoid TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
Nvoid TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
Nvoid TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity);
Nvoid TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
Nvoid TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity);
Nvoid TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
Nvoid TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity);
Nvoid TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
Nvoid TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
Nvoid TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
Nvoid TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
Nvoid TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState);
Nvoid TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource);
Nvoid TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState);
Nvoid TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode);
Nvoid TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource);
Nvoid TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode);
Nvoid TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode);
Nvoid TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter);
Nvoid TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload);
Nvoid TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1);
Nvoid TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2);
Nvoid TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3);
Nvoid TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4);
Nvoid TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
Nvoid TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
Nvoid TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
Nvoid TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
Nvoid TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD);
Nuint16_t TIM_GetCapture1(TIM_TypeDef *TIMx);
Nuint16_t TIM_GetCapture2(TIM_TypeDef *TIMx);
Nuint16_t TIM_GetCapture3(TIM_TypeDef *TIMx);
Nuint16_t TIM_GetCapture4(TIM_TypeDef *TIMx);
Nuint16_t TIM_GetCounter(TIM_TypeDef *TIMx);
Nuint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx);
NFlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG);
Nvoid TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG);
NITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT);
Nvoid TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT);
N
N#endif /*__STM32F10x_TIM_H */
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
L 46 "..\src\STM32Lib\stm32f10x_conf.h" 2
N#include "stm32f10x_usart.h"
L 1 "..\src\STM32Lib\stm32f10x_usart.h" 1
N/**
N ******************************************************************************
N * @file stm32f10x_usart.h
N * @author MCD Application Team
N * @version V3.0.0
N * @date 04/06/2009
N * @brief This file contains all the functions prototypes for the USART
N * firmware library.
N ******************************************************************************
N * @copy
N *
N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N *
N * © COPYRIGHT 2009 STMicroelectronics
N */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __STM32F10x_USART_H
N#define __STM32F10x_USART_H
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f10x.h"
N
N/** @addtogroup StdPeriph_Driver
N * @{
N */
N
N/** @addtogroup USART
N * @{
N */
N
N/** @defgroup USART_Exported_Types
N * @{
N */
N
N/**
N * @brief USART Init Structure definition
N */
N
Ntypedef struct
N{
N uint32_t USART_BaudRate;
N uint16_t USART_WordLength;
N uint16_t USART_StopBits;
N uint16_t USART_Parity;
N uint16_t USART_Mode;
N uint16_t USART_HardwareFlowControl;
N} USART_InitTypeDef;
N
N/**
N * @brief USART Clock Init Structure definition
N */
N
Ntypedef struct
N{
N uint16_t USART_Clock;
N uint16_t USART_CPOL;
N uint16_t USART_CPHA;
N uint16_t USART_LastBit;
N} USART_ClockInitTypeDef;
N
N/**
N * @}
N */
N
N/** @defgroup USART_Exported_Constants
N * @{
N */
N
N#define IS_USART_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == USART1_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == USART2_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == USART3_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == UART4_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == UART5_BASE))
X#define IS_USART_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == USART1_BASE) || ((*(uint32_t*)&(PERIPH)) == USART2_BASE) || ((*(uint32_t*)&(PERIPH)) == USART3_BASE) || ((*(uint32_t*)&(PERIPH)) == UART4_BASE) || ((*(uint32_t*)&(PERIPH)) == UART5_BASE))
N#define IS_USART_123_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == USART1_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == USART2_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == USART3_BASE))
X#define IS_USART_123_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == USART1_BASE) || ((*(uint32_t*)&(PERIPH)) == USART2_BASE) || ((*(uint32_t*)&(PERIPH)) == USART3_BASE))
N#define IS_USART_1234_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == USART1_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == USART2_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == USART3_BASE) || \
N ((*(uint32_t*)&(PERIPH)) == UART4_BASE))
X#define IS_USART_1234_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == USART1_BASE) || ((*(uint32_t*)&(PERIPH)) == USART2_BASE) || ((*(uint32_t*)&(PERIPH)) == USART3_BASE) || ((*(uint32_t*)&(PERIPH)) == UART4_BASE))
N/** @defgroup USART_Word_Length
N * @{
N */
N
N#define USART_WordLength_8b ((uint16_t)0x0000)
N#define USART_WordLength_9b ((uint16_t)0x1000)
N
N#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
N ((LENGTH) == USART_WordLength_9b))
X#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || ((LENGTH) == USART_WordLength_9b))
N/**
N * @}
N */
N
N/** @defgroup USART_Stop_Bits
N * @{
N */
N
N#define USART_StopBits_1 ((uint16_t)0x0000)
N#define USART_StopBits_0_5 ((uint16_t)0x1000)
N#define USART_StopBits_2 ((uint16_t)0x2000)
N#define USART_StopBits_1_5 ((uint16_t)0x3000)
N#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
N ((STOPBITS) == USART_StopBits_0_5) || \
N ((STOPBITS) == USART_StopBits_2) || \
N ((STOPBITS) == USART_StopBits_1_5))
X#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || ((STOPBITS) == USART_StopBits_0_5) || ((STOPBITS) == USART_StopBits_2) || ((STOPBITS) == USART_StopBits_1_5))
N/**
N * @}
N */
N
N/** @defgroup USART_Parity
N * @{
N */
N
N#define USART_Parity_No ((uint16_t)0x0000)
N#define USART_Parity_Even ((uint16_t)0x0400)
N#define USART_Parity_Odd ((uint16_t)0x0600)
N#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
N ((PARITY) == USART_Parity_Even) || \
N ((PARITY) == USART_Parity_Odd))
X#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || ((PARITY) == USART_Parity_Even) || ((PARITY) == USART_Parity_Odd))
N/**
N * @}
N */
N
N/** @defgroup USART_Mode
N * @{
N */
N
N#define USART_Mode_Rx ((uint16_t)0x0004)
N#define USART_Mode_Tx ((uint16_t)0x0008)
N#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
N/**
N * @}
N */
N
N/** @defgroup USART_Hardware_Flow_Control
N * @{
N */
N#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
N#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
N#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
N#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
N#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
N (((CONTROL) == USART_HardwareFlowControl_None) || \
N ((CONTROL) == USART_HardwareFlowControl_RTS) || \
N ((CONTROL) == USART_HardwareFlowControl_CTS) || \
N ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
X#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == USART_HardwareFlowControl_None) || ((CONTROL) == USART_HardwareFlowControl_RTS) || ((CONTROL) == USART_HardwareFlowControl_CTS) || ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
N#define IS_USART_PERIPH_HFC(PERIPH, HFC) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) && \
N ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
N || ((HFC) == USART_HardwareFlowControl_None))
X#define IS_USART_PERIPH_HFC(PERIPH, HFC) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) && ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) || ((HFC) == USART_HardwareFlowControl_None))
N/**
N * @}
N */
N
N/** @defgroup USART_Clock
N * @{
N */
N#define USART_Clock_Disable ((uint16_t)0x0000)
N#define USART_Clock_Enable ((uint16_t)0x0800)
N#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
N ((CLOCK) == USART_Clock_Enable))
X#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || ((CLOCK) == USART_Clock_Enable))
N/**
N * @}
N */
N
N/** @defgroup USART_Clock_Polarity
N * @{
N */
N
N#define USART_CPOL_Low ((uint16_t)0x0000)
N#define USART_CPOL_High ((uint16_t)0x0400)
N#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
N
N/**
N * @}
N */
N
N/** @defgroup USART_Clock_Phase
N * @{
N */
N
N#define USART_CPHA_1Edge ((uint16_t)0x0000)
N#define USART_CPHA_2Edge ((uint16_t)0x0200)
N#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
N
N/**
N * @}
N */
N
N/** @defgroup USART_Last_Bit
N * @{
N */
N
N#define USART_LastBit_Disable ((uint16_t)0x0000)
N#define USART_LastBit_Enable ((uint16_t)0x0100)
N#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
N ((LASTBIT) == USART_LastBit_Enable))
X#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || ((LASTBIT) == USART_LastBit_Enable))
N/**
N * @}
N */
N
N/** @defgroup USART_Interrupt_definition
N * @{
N */
N
N#define USART_IT_PE ((uint16_t)0x0028)
N#define USART_IT_TXE ((uint16_t)0x0727)
N#define USART_IT_TC ((uint16_t)0x0626)
N#define USART_IT_RXNE ((uint16_t)0x0525)
N#define USART_IT_IDLE ((uint16_t)0x0424)
N#define USART_IT_LBD ((uint16_t)0x0846)
N#define USART_IT_CTS ((uint16_t)0x096A)
N#define USART_IT_ERR ((uint16_t)0x0060)
N#define USART_IT_ORE ((uint16_t)0x0360)
N#define USART_IT_NE ((uint16_t)0x0260)
N#define USART_IT_FE ((uint16_t)0x0160)
N#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
N ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
N ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
N ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
X#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
N#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
N ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
N ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
N ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
N ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
X#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
N#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
N ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
X#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
N#define IS_USART_PERIPH_IT(PERIPH, USART_IT) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) && \
N ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
N || ((USART_IT) != USART_IT_CTS))
X#define IS_USART_PERIPH_IT(PERIPH, USART_IT) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) && ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) || ((USART_IT) != USART_IT_CTS))
N/**
N * @}
N */
N
N/** @defgroup USART_DMA_Requests
N * @{
N */
N
N#define USART_DMAReq_Tx ((uint16_t)0x0080)
N#define USART_DMAReq_Rx ((uint16_t)0x0040)
N#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
N
N/**
N * @}
N */
N
N/** @defgroup USART_WakeUp_methods
N * @{
N */
N
N#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
N#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
N#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
N ((WAKEUP) == USART_WakeUp_AddressMark))
X#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || ((WAKEUP) == USART_WakeUp_AddressMark))
N/**
N * @}
N */
N
N/** @defgroup USART_LIN_Break_Detection_Length
N * @{
N */
N
N#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
N#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
N#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
N (((LENGTH) == USART_LINBreakDetectLength_10b) || \
N ((LENGTH) == USART_LINBreakDetectLength_11b))
X#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == USART_LINBreakDetectLength_10b) || ((LENGTH) == USART_LINBreakDetectLength_11b))
N/**
N * @}
N */
N
N/** @defgroup USART_IrDA_Low_Power
N * @{
N */
N
N#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
N#define USART_IrDAMode_Normal ((uint16_t)0x0000)
N#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
N ((MODE) == USART_IrDAMode_Normal))
X#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || ((MODE) == USART_IrDAMode_Normal))
N/**
N * @}
N */
N
N/** @defgroup USART_Flags
N * @{
N */
N
N#define USART_FLAG_CTS ((uint16_t)0x0200)
N#define USART_FLAG_LBD ((uint16_t)0x0100)
N#define USART_FLAG_TXE ((uint16_t)0x0080)
N#define USART_FLAG_TC ((uint16_t)0x0040)
N#define USART_FLAG_RXNE ((uint16_t)0x0020)
N#define USART_FLAG_IDLE ((uint16_t)0x0010)
N#define USART_FLAG_ORE ((uint16_t)0x0008)
N#define USART_FLAG_NE ((uint16_t)0x0004)
N#define USART_FLAG_FE ((uint16_t)0x0002)
N#define USART_FLAG_PE ((uint16_t)0x0001)
N#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
N ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
N ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
N ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
N ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
X#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
N
N#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
N#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\
N ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
N || ((USART_FLAG) != USART_FLAG_CTS))
X#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) && ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) || ((USART_FLAG) != USART_FLAG_CTS))
N#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
N#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
N#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
N
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/** @defgroup USART_Exported_Macros
N * @{
N */
N
N/**
N * @}
N */
N
N/** @defgroup USART_Exported_Functions
N * @{
N */
N
Nvoid USART_DeInit(USART_TypeDef *USARTx);
Nvoid USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct);
Nvoid USART_StructInit(USART_InitTypeDef *USART_InitStruct);
Nvoid USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct);
Nvoid USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct);
Nvoid USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState);
Nvoid USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState);
Nvoid USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
Nvoid USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address);
Nvoid USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp);
Nvoid USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState);
Nvoid USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength);
Nvoid USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState);
Nvoid USART_SendData(USART_TypeDef *USARTx, uint16_t Data);
Nuint16_t USART_ReceiveData(USART_TypeDef *USARTx);
Nvoid USART_SendBreak(USART_TypeDef *USARTx);
Nvoid USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime);
Nvoid USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler);
Nvoid USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState);
Nvoid USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState);
Nvoid USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState);
Nvoid USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode);
Nvoid USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState);
NFlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG);
Nvoid USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG);
NITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT);
Nvoid USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT);
N
N#endif /* __STM32F10x_USART_H */
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
L 47 "..\src\STM32Lib\stm32f10x_conf.h" 2
N// #include "stm32f10x_wwdg.h"
N#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
L 1 "..\src\STM32Lib\misc.h" 1
N/**
N ******************************************************************************
N * @file misc.h
N * @author MCD Application Team
N * @version V3.0.0
N * @date 04/06/2009
N * @brief This file contains all the functions prototypes for the
N * miscellaneous firmware library functions.
N ******************************************************************************
N * @copy
N *
N * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
N * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
N * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
N * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
N * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
N * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
N *
N * © COPYRIGHT 2009 STMicroelectronics
N */
N
N/* Define to prevent recursive inclusion -------------------------------------*/
N#ifndef __MISC_H
N#define __MISC_H
N
N/* Includes ------------------------------------------------------------------*/
N#include "stm32f10x.h"
N
N/** @addtogroup StdPeriph_Driver
N * @{
N */
N
N/** @addtogroup MISC
N * @{
N */
N
N/** @defgroup MISC_Exported_Types
N * @{
N */
N
N/**
N * @brief NVIC Init Structure definition
N */
N
Ntypedef struct
N{
N uint8_t NVIC_IRQChannel;
N uint8_t NVIC_IRQChannelPreemptionPriority;
N uint8_t NVIC_IRQChannelSubPriority;
N FunctionalState NVIC_IRQChannelCmd;
N} NVIC_InitTypeDef;
N
N/**
N * @}
N */
N
N/** @defgroup MISC_Exported_Constants
N * @{
N */
N
N/** @defgroup Vector_Table_Base
N * @{
N */
N
N#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
N#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
N#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
N ((VECTTAB) == NVIC_VectTab_FLASH))
X#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || ((VECTTAB) == NVIC_VectTab_FLASH))
N/**
N * @}
N */
N
N/** @defgroup System_Low_Power
N * @{
N */
N
N#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
N#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
N#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
N#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
N ((LP) == NVIC_LP_SLEEPDEEP) || \
N ((LP) == NVIC_LP_SLEEPONEXIT))
X#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || ((LP) == NVIC_LP_SLEEPDEEP) || ((LP) == NVIC_LP_SLEEPONEXIT))
N/**
N * @}
N */
N
N/** @defgroup Preemption_Priority_Group
N * @{
N */
N
N#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /* 0 bits for pre-emption priority
N 4 bits for subpriority */
N#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /* 1 bits for pre-emption priority
N 3 bits for subpriority */
N#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /* 2 bits for pre-emption priority
N 2 bits for subpriority */
N#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /* 3 bits for pre-emption priority
N 1 bits for subpriority */
N#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /* 4 bits for pre-emption priority
N 0 bits for subpriority */
N
N#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
N ((GROUP) == NVIC_PriorityGroup_1) || \
N ((GROUP) == NVIC_PriorityGroup_2) || \
N ((GROUP) == NVIC_PriorityGroup_3) || \
N ((GROUP) == NVIC_PriorityGroup_4))
X#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || ((GROUP) == NVIC_PriorityGroup_1) || ((GROUP) == NVIC_PriorityGroup_2) || ((GROUP) == NVIC_PriorityGroup_3) || ((GROUP) == NVIC_PriorityGroup_4))
N
N#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
N
N#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
N
N#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF)
N
N/**
N * @}
N */
N
N/** @defgroup SysTick_clock_source
N * @{
N */
N
N#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
N#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
N#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
N ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
X#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/** @defgroup MISC_Exported_Macros
N * @{
N */
N
N/**
N * @}
N */
N
N/** @defgroup MISC_Exported_Functions
N * @{
N */
N
Nvoid NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
Nvoid NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct);
Nvoid NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
Nvoid NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
Nvoid SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
N
N#endif /* __MISC_H */
N
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
L 49 "..\src\STM32Lib\stm32f10x_conf.h" 2
N
N/* Exported types ------------------------------------------------------------*/
N/* Exported constants --------------------------------------------------------*/
N/* Uncomment the line below to expanse the "assert_param" macro in the
N Standard Peripheral Library drivers code */
N/* #define USE_FULL_ASSERT 1 */
N
N/* Exported macro ------------------------------------------------------------*/
N#ifdef USE_FULL_ASSERT
S
S/**
S * @brief The assert_param macro is used for function's parameters check.
S * @param expr: If expr is false, it calls assert_failed function
S * which reports the name of the source file and the source
S * line number of the call that failed.
S * If expr is true, it returns no value.
S * @retval : None
S */
S#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
S/* Exported functions ------------------------------------------------------- */
Svoid assert_failed(uint8_t *file, uint32_t line);
N#else
N#define assert_param(expr) ((void)0)
N#endif /* USE_FULL_ASSERT */
N
N#endif /* __STM32F10x_CONF_H */
N
N/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
L 6972 "..\src\STM32Lib\stm32f10x.h" 2
N#endif
N
N/** @addtogroup Exported_macro
N * @{
N */
N
N#define SET_BIT(REG, BIT) ((REG) |= (BIT))
N
N#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
N
N#define READ_BIT(REG, BIT) ((REG) & (BIT))
N
N#define CLEAR_REG(REG) ((REG) = (0x0))
N
N#define WRITE_REG(REG, VAL) ((REG) = (VAL))
N
N#define READ_REG(REG) ((REG))
N
N#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~CLEARMASK)) | (SETMASK)))
N
N/**
N * @}
N */
N
N#endif /* __STM32F10x_H */
N
N/**
N * @}
N */
N
N/**
N* @}
N*/
N
N/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
L 28 "..\src\STM32Lib\stm32f10x_exti.h" 2
N
N/** @addtogroup StdPeriph_Driver
N * @{
N */
N
N/** @addtogroup EXTI
N * @{
N */
N
N/** @defgroup EXTI_Exported_Types
N * @{
N */
N
N/**
N * @brief EXTI mode enumeration
N */
N
Ntypedef enum
N{
N EXTI_Mode_Interrupt = 0x00,
N EXTI_Mode_Event = 0x04
N} EXTIMode_TypeDef;
N
N#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
N
N/**
N * @brief EXTI Trigger enumeration
N */
N
Ntypedef enum
N{
N EXTI_Trigger_Rising = 0x08,
N EXTI_Trigger_Falling = 0x0C,
N EXTI_Trigger_Rising_Falling = 0x10
N} EXTITrigger_TypeDef;
N
N#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
N ((TRIGGER) == EXTI_Trigger_Falling) || \
N ((TRIGGER) == EXTI_Trigger_Rising_Falling))
X#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || ((TRIGGER) == EXTI_Trigger_Falling) || ((TRIGGER) == EXTI_Trigger_Rising_Falling))
N/**
N * @brief EXTI Init Structure definition
N */
N
Ntypedef struct
N{
N uint32_t EXTI_Line;
N EXTIMode_TypeDef EXTI_Mode;
N EXTITrigger_TypeDef EXTI_Trigger;
N FunctionalState EXTI_LineCmd;
N} EXTI_InitTypeDef;
N
N/**
N * @}
N */
N
N/** @defgroup EXTI_Exported_Constants
N * @{
N */
N
N/** @defgroup EXTI_Lines
N * @{
N */
N
N#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */
N#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */
N#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */
N#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */
N#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */
N#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */
N#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */
N#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */
N#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */
N#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */
N#define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */
N#define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */
N#define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */
N#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */
N#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */
N#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */
N#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16
N Connected to the PVD Output */
N#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17
N Connected to the RTC Alarm event */
N#define EXTI_Line18 ((uint32_t)0x40000) /* External interrupt line 18
N Connected to the USB Wakeup from
N suspend event */
N
N#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF80000) == 0x00) && ((LINE) != (uint16_t)0x00))
N
N#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
N ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
N ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
N ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
N ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
N ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
N ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
N ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
N ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
N ((LINE) == EXTI_Line18))
X#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || ((LINE) == EXTI_Line18))
N
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/** @defgroup EXTI_Exported_Macros
N * @{
N */
N
N/**
N * @}
N */
N
N/** @defgroup EXTI_Exported_Functions
N * @{
N */
N
Nvoid EXTI_DeInit(void);
Nvoid EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct);
Nvoid EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct);
Nvoid EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
NFlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
Nvoid EXTI_ClearFlag(uint32_t EXTI_Line);
NITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
Nvoid EXTI_ClearITPendingBit(uint32_t EXTI_Line);
N
N#endif /* __STM32F10x_EXTI_H */
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
L 23 "..\src\STM32Lib\stm32f10x_exti.c" 2
N
N/** @addtogroup StdPeriph_Driver
N * @{
N */
N
N/** @defgroup EXTI
N * @brief EXTI driver modules
N * @{
N */
N
N/** @defgroup EXTI_Private_TypesDefinitions
N * @{
N */
N
N/**
N * @}
N */
N
N/** @defgroup EXTI_Private_Defines
N * @{
N */
N
N#define EXTI_LineNone ((uint32_t)0x00000) /* No interrupt selected */
N
N/**
N * @}
N */
N
N/** @defgroup EXTI_Private_Macros
N * @{
N */
N
N/**
N * @}
N */
N
N/** @defgroup EXTI_Private_Variables
N * @{
N */
N
N/**
N * @}
N */
N
N/** @defgroup EXTI_Private_FunctionPrototypes
N * @{
N */
N
N/**
N * @}
N */
N
N/** @defgroup EXTI_Private_Functions
N * @{
N */
N
N/**
N * @brief Deinitializes the EXTI peripheral registers to their default
N * reset values.
N * @param None
N * @retval : None
N */
Nvoid EXTI_DeInit(void)
N{
N EXTI->IMR = 0x00000000;
X ((EXTI_TypeDef *) ((((uint32_t)0x40000000) + 0x10000) + 0x0400))->IMR = 0x00000000;
N EXTI->EMR = 0x00000000;
X ((EXTI_TypeDef *) ((((uint32_t)0x40000000) + 0x10000) + 0x0400))->EMR = 0x00000000;
N EXTI->RTSR = 0x00000000;
X ((EXTI_TypeDef *) ((((uint32_t)0x40000000) + 0x10000) + 0x0400))->RTSR = 0x00000000;
N EXTI->FTSR = 0x00000000;
X ((EXTI_TypeDef *) ((((uint32_t)0x40000000) + 0x10000) + 0x0400))->FTSR = 0x00000000;
N EXTI->PR = 0x0007FFFF;
X ((EXTI_TypeDef *) ((((uint32_t)0x40000000) + 0x10000) + 0x0400))->PR = 0x0007FFFF;
N}
N
N/**
N * @brief Initializes the EXTI peripheral according to the specified
N * parameters in the EXTI_InitStruct.
N * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
N * that contains the configuration information for the EXTI
N * peripheral.
N * @retval : None
N */
Nvoid EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct)
N{
N /* Check the parameters */
N assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
X ((void)0);
N assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
X ((void)0);
N assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
X ((void)0);
N assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
X ((void)0);
N
N if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
N {
N /* Clear EXTI line configuration */
N EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
X ((EXTI_TypeDef *) ((((uint32_t)0x40000000) + 0x10000) + 0x0400))->IMR &= ~EXTI_InitStruct->EXTI_Line;
N EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
X ((EXTI_TypeDef *) ((((uint32_t)0x40000000) + 0x10000) + 0x0400))->EMR &= ~EXTI_InitStruct->EXTI_Line;
N
N *(__IO uint32_t *)(EXTI_BASE + (uint32_t)EXTI_InitStruct->EXTI_Mode) |= EXTI_InitStruct->EXTI_Line;
X *(volatile uint32_t *)(((((uint32_t)0x40000000) + 0x10000) + 0x0400) + (uint32_t)EXTI_InitStruct->EXTI_Mode) |= EXTI_InitStruct->EXTI_Line;
N /* Clear Rising Falling edge configuration */
N EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
X ((EXTI_TypeDef *) ((((uint32_t)0x40000000) + 0x10000) + 0x0400))->RTSR &= ~EXTI_InitStruct->EXTI_Line;
N EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
X ((EXTI_TypeDef *) ((((uint32_t)0x40000000) + 0x10000) + 0x0400))->FTSR &= ~EXTI_InitStruct->EXTI_Line;
N
N /* Select the trigger for the selected external interrupts */
N if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
N {
N /* Rising Falling edge */
N EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
X ((EXTI_TypeDef *) ((((uint32_t)0x40000000) + 0x10000) + 0x0400))->RTSR |= EXTI_InitStruct->EXTI_Line;
N EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
X ((EXTI_TypeDef *) ((((uint32_t)0x40000000) + 0x10000) + 0x0400))->FTSR |= EXTI_InitStruct->EXTI_Line;
N }
N else
N {
N *(__IO uint32_t *)(EXTI_BASE + (uint32_t)EXTI_InitStruct->EXTI_Trigger) |= EXTI_InitStruct->EXTI_Line;
X *(volatile uint32_t *)(((((uint32_t)0x40000000) + 0x10000) + 0x0400) + (uint32_t)EXTI_InitStruct->EXTI_Trigger) |= EXTI_InitStruct->EXTI_Line;
N }
N }
N else
N {
N /* Disable the selected external lines */
N *(__IO uint32_t *)(EXTI_BASE + (uint32_t)EXTI_InitStruct->EXTI_Mode) &= ~EXTI_InitStruct->EXTI_Line;
X *(volatile uint32_t *)(((((uint32_t)0x40000000) + 0x10000) + 0x0400) + (uint32_t)EXTI_InitStruct->EXTI_Mode) &= ~EXTI_InitStruct->EXTI_Line;
N }
N}
N
N/**
N * @brief Fills each EXTI_InitStruct member with its reset value.
N * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
N * which will be initialized.
N * @retval : None
N */
Nvoid EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct)
N{
N EXTI_InitStruct->EXTI_Line = EXTI_LineNone;
X EXTI_InitStruct->EXTI_Line = ((uint32_t)0x00000);
N EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
N EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
N EXTI_InitStruct->EXTI_LineCmd = DISABLE;
N}
N
N/**
N * @brief Generates a Software interrupt.
N * @param EXTI_Line: specifies the EXTI lines to be enabled or
N * disabled.
N * This parameter can be any combination of EXTI_Linex where
N * x can be (0..18).
N * @retval : None
N */
Nvoid EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
N{
N /* Check the parameters */
N assert_param(IS_EXTI_LINE(EXTI_Line));
X ((void)0);
N
N EXTI->SWIER |= EXTI_Line;
X ((EXTI_TypeDef *) ((((uint32_t)0x40000000) + 0x10000) + 0x0400))->SWIER |= EXTI_Line;
N}
N
N/**
N * @brief Checks whether the specified EXTI line flag is set or not.
N * @param EXTI_Line: specifies the EXTI line flag to check.
N * This parameter can be:
N * @arg EXTI_Linex: External interrupt line x where x(0..18)
N * @retval : The new state of EXTI_Line (SET or RESET).
N */
NFlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
N{
N FlagStatus bitstatus = RESET;
N /* Check the parameters */
N assert_param(IS_GET_EXTI_LINE(EXTI_Line));
X ((void)0);
N
N if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
X if ((((EXTI_TypeDef *) ((((uint32_t)0x40000000) + 0x10000) + 0x0400))->PR & EXTI_Line) != (uint32_t)RESET)
N {
N bitstatus = SET;
N }
N else
N {
N bitstatus = RESET;
N }
N return bitstatus;
N}
N
N/**
N * @brief Clears the EXTI’s line pending flags.
N * @param EXTI_Line: specifies the EXTI lines flags to clear.
N * This parameter can be any combination of EXTI_Linex where
N * x can be (0..18).
N * @retval : None
N */
Nvoid EXTI_ClearFlag(uint32_t EXTI_Line)
N{
N /* Check the parameters */
N assert_param(IS_EXTI_LINE(EXTI_Line));
X ((void)0);
N
N EXTI->PR = EXTI_Line;
X ((EXTI_TypeDef *) ((((uint32_t)0x40000000) + 0x10000) + 0x0400))->PR = EXTI_Line;
N}
N
N/**
N * @brief Checks whether the specified EXTI line is asserted or not.
N * @param EXTI_Line: specifies the EXTI line to check.
N * This parameter can be:
N * @arg EXTI_Linex: External interrupt line x where x(0..18)
N * @retval : The new state of EXTI_Line (SET or RESET).
N */
NITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
N{
N ITStatus bitstatus = RESET;
N uint32_t enablestatus = 0;
N /* Check the parameters */
N assert_param(IS_GET_EXTI_LINE(EXTI_Line));
X ((void)0);
N
N enablestatus = EXTI->IMR & EXTI_Line;
X enablestatus = ((EXTI_TypeDef *) ((((uint32_t)0x40000000) + 0x10000) + 0x0400))->IMR & EXTI_Line;
N if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
X if (((((EXTI_TypeDef *) ((((uint32_t)0x40000000) + 0x10000) + 0x0400))->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
N {
N bitstatus = SET;
N }
N else
N {
N bitstatus = RESET;
N }
N return bitstatus;
N}
N
N/**
N * @brief Clears the EXTI’s line pending bits.
N * @param EXTI_Line: specifies the EXTI lines to clear.
N * This parameter can be any combination of EXTI_Linex where
N * x can be (0..18).
N * @retval : None
N */
Nvoid EXTI_ClearITPendingBit(uint32_t EXTI_Line)
N{
N /* Check the parameters */
N assert_param(IS_EXTI_LINE(EXTI_Line));
X ((void)0);
N
N EXTI->PR = EXTI_Line;
X ((EXTI_TypeDef *) ((((uint32_t)0x40000000) + 0x10000) + 0x0400))->PR = EXTI_Line;
N}
N
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/**
N * @}
N */
N
N/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/