1 ; C Compiler for STM8 (COSMIC Software) 2 ; Parser V4.8.32 - 23 Mar 2010 3 ; Generator V4.3.4 - 23 Mar 2010 45 ; 49 void UART2_DeInit(void) 45 ; 50 { 47 .text: section .text,new 48 0000 _UART2_DeInit: 52 ; 53 (void) UART2->SR; 54 0000 c65240 ld a,21056 55 ; 54 (void)UART2->DR; 57 0003 c65241 ld a,21057 58 ; 56 UART2->BRR2 = UART2_BRR2_RESET_VALUE; /* Set UART2_BRR2 to reset value 0x00 */ 60 0006 725f5243 clr 21059 61 ; 57 UART2->BRR1 = UART2_BRR1_RESET_VALUE; /* Set UART2_BRR1 to reset value 0x00 */ 63 000a 725f5242 clr 21058 64 ; 59 UART2->CR1 = UART2_CR1_RESET_VALUE; /* Set UART2_CR1 to reset value 0x00 */ 66 000e 725f5244 clr 21060 67 ; 60 UART2->CR2 = UART2_CR2_RESET_VALUE; /* Set UART2_CR2 to reset value 0x00 */ 69 0012 725f5245 clr 21061 70 ; 61 UART2->CR3 = UART2_CR3_RESET_VALUE; /* Set UART2_CR3 to reset value 0x00 */ 72 0016 725f5246 clr 21062 73 ; 62 UART2->CR4 = UART2_CR4_RESET_VALUE; /* Set UART2_CR4 to reset value 0x00 */ 75 001a 725f5247 clr 21063 76 ; 63 UART2->CR5 = UART2_CR5_RESET_VALUE; /* Set UART2_CR5 to reset value 0x00 */ 78 001e 725f5248 clr 21064 79 ; 64 UART2->CR6 = UART2_CR6_RESET_VALUE; /* Set UART2_CR6 to reset value 0x00 */ 81 0022 725f5249 clr 21065 82 ; 66 } 85 0026 81 ret 396 .const: section .text 397 0000 L01: 398 0000 00000064 dc.l 100 399 ; 82 void UART2_Init(uint32_t BaudRate, UART2_WordLength_TypeDef WordLength, UART2_StopBits_TypeDef StopBits, UART2_Parity_TypeDef Parity, UART2_SyncMode_TypeDef SyncMode, UART2_Mode_TypeDef Mode) 399 ; 83 { 400 .text: section .text,new 401 0000 _UART2_Init: 403 0000 520e subw sp,#14 404 0000000e OFST: set 14 407 ; 84 uint8_t BRR2_1 = 0, BRR2_2 = 0; 411 ; 85 uint32_t BaudRate_Mantissa = 0, BaudRate_Mantissa100 = 0; 415 ; 88 assert_param(IS_UART2_BAUDRATE_OK(BaudRate)); 417 ; 89 assert_param(IS_UART2_WORDLENGTH_OK(WordLength)); 419 ; 90 assert_param(IS_UART2_STOPBITS_OK(StopBits)); 421 ; 91 assert_param(IS_UART2_PARITY_OK(Parity)); 423 ; 92 assert_param(IS_UART2_MODE_OK((uint8_t)Mode)); 425 ; 93 assert_param(IS_UART2_SYNCMODE_OK((uint8_t)SyncMode)); 427 ; 96 UART2->CR1 &= (uint8_t)(~UART2_CR1_M); 429 0002 72195244 bres 21060,#4 430 ; 98 UART2->CR1 |= (uint8_t)WordLength; 432 0006 c65244 ld a,21060 433 0009 1a15 or a,(OFST+7,sp) 434 000b c75244 ld 21060,a 435 ; 101 UART2->CR3 &= (uint8_t)(~UART2_CR3_STOP); 437 000e c65246 ld a,21062 438 0011 a4cf and a,#207 439 0013 c75246 ld 21062,a 440 ; 103 UART2->CR3 |= (uint8_t)StopBits; 442 0016 c65246 ld a,21062 443 0019 1a16 or a,(OFST+8,sp) 444 001b c75246 ld 21062,a 445 ; 106 UART2->CR1 &= (uint8_t)(~(UART2_CR1_PCEN | UART2_CR1_PS )); 447 001e c65244 ld a,21060 448 0021 a4f9 and a,#249 449 0023 c75244 ld 21060,a 450 ; 108 UART2->CR1 |= (uint8_t)Parity; 452 0026 c65244 ld a,21060 453 0029 1a17 or a,(OFST+9,sp) 454 002b c75244 ld 21060,a 455 ; 111 UART2->BRR1 &= (uint8_t)(~UART2_BRR1_DIVM); 457 002e 725f5242 clr 21058 458 ; 113 UART2->BRR2 &= (uint8_t)(~UART2_BRR2_DIVM); 460 0032 c65243 ld a,21059 461 0035 a40f and a,#15 462 0037 c75243 ld 21059,a 463 ; 115 UART2->BRR2 &= (uint8_t)(~UART2_BRR2_DIVF); 465 003a c65243 ld a,21059 466 003d a4f0 and a,#240 467 003f c75243 ld 21059,a 468 ; 118 BaudRate_Mantissa = ((uint32_t)CLK_GetClockFreq() / (BaudRate << 4)); 470 0042 96 ldw x,sp 471 0043 1c0011 addw x,#OFST+3 472 0046 cd0000 call c_ltor 474 0049 a604 ld a,#4 475 004b cd0000 call c_llsh 477 004e 96 ldw x,sp 478 004f 1c0001 addw x,#OFST-13 479 0052 cd0000 call c_rtol 481 0055 cd0000 call _CLK_GetClockFreq 483 0058 96 ldw x,sp 484 0059 1c0001 addw x,#OFST-13 485 005c cd0000 call c_ludv 487 005f 96 ldw x,sp 488 0060 1c000b addw x,#OFST-3 489 0063 cd0000 call c_rtol 491 ; 119 BaudRate_Mantissa100 = (((uint32_t)CLK_GetClockFreq() * 100) / (BaudRate << 4)); 493 0066 96 ldw x,sp 494 0067 1c0011 addw x,#OFST+3 495 006a cd0000 call c_ltor 497 006d a604 ld a,#4 498 006f cd0000 call c_llsh 500 0072 96 ldw x,sp 501 0073 1c0001 addw x,#OFST-13 502 0076 cd0000 call c_rtol 504 0079 cd0000 call _CLK_GetClockFreq 506 007c a664 ld a,#100 507 007e cd0000 call c_smul 509 0081 96 ldw x,sp 510 0082 1c0001 addw x,#OFST-13 511 0085 cd0000 call c_ludv 513 0088 96 ldw x,sp 514 0089 1c0007 addw x,#OFST-7 515 008c cd0000 call c_rtol 517 ; 123 BRR2_1 = (uint8_t)((uint8_t)(((BaudRate_Mantissa100 - (BaudRate_Mantissa * 100)) 517 ; 124 << 4) / 100) & (uint8_t)0x0F); 519 008f 96 ldw x,sp 520 0090 1c000b addw x,#OFST-3 521 0093 cd0000 call c_ltor 523 0096 a664 ld a,#100 524 0098 cd0000 call c_smul 526 009b 96 ldw x,sp 527 009c 1c0001 addw x,#OFST-13 528 009f cd0000 call c_rtol 530 00a2 96 ldw x,sp 531 00a3 1c0007 addw x,#OFST-7 532 00a6 cd0000 call c_ltor 534 00a9 96 ldw x,sp 535 00aa 1c0001 addw x,#OFST-13 536 00ad cd0000 call c_lsub 538 00b0 a604 ld a,#4 539 00b2 cd0000 call c_llsh 541 00b5 ae0000 ldw x,#L01 542 00b8 cd0000 call c_ludv 544 00bb b603 ld a,c_lreg+3 545 00bd a40f and a,#15 546 00bf 6b05 ld (OFST-9,sp),a 547 ; 125 BRR2_2 = (uint8_t)((BaudRate_Mantissa >> 4) & (uint8_t)0xF0); 549 00c1 96 ldw x,sp 550 00c2 1c000b addw x,#OFST-3 551 00c5 cd0000 call c_ltor 553 00c8 a604 ld a,#4 554 00ca cd0000 call c_lursh 556 00cd b603 ld a,c_lreg+3 557 00cf a4f0 and a,#240 558 00d1 b703 ld c_lreg+3,a 559 00d3 3f02 clr c_lreg+2 560 00d5 3f01 clr c_lreg+1 561 00d7 3f00 clr c_lreg 562 00d9 b603 ld a,c_lreg+3 563 00db 6b06 ld (OFST-8,sp),a 564 ; 127 UART2->BRR2 = (uint8_t)(BRR2_1 | BRR2_2); 566 00dd 7b05 ld a,(OFST-9,sp) 567 00df 1a06 or a,(OFST-8,sp) 568 00e1 c75243 ld 21059,a 569 ; 129 UART2->BRR1 = (uint8_t)BaudRate_Mantissa; 571 00e4 7b0e ld a,(OFST+0,sp) 572 00e6 c75242 ld 21058,a 573 ; 132 UART2->CR2 &= (uint8_t)~(UART2_CR2_TEN | UART2_CR2_REN); 575 00e9 c65245 ld a,21061 576 00ec a4f3 and a,#243 577 00ee c75245 ld 21061,a 578 ; 134 UART2->CR3 &= (uint8_t)~(UART2_CR3_CPOL | UART2_CR3_CPHA | UART2_CR3_LBCL); 580 00f1 c65246 ld a,21062 581 00f4 a4f8 and a,#248 582 00f6 c75246 ld 21062,a 583 ; 136 UART2->CR3 |= (uint8_t)((uint8_t)SyncMode & (uint8_t)(UART2_CR3_CPOL | \ 583 ; 137 UART2_CR3_CPHA | UART2_CR3_LBCL)); 585 00f9 7b18 ld a,(OFST+10,sp) 586 00fb a407 and a,#7 587 00fd ca5246 or a,21062 588 0100 c75246 ld 21062,a 589 ; 139 if ((uint8_t)(Mode & UART2_MODE_TX_ENABLE)) 591 0103 7b19 ld a,(OFST+11,sp) 592 0105 a504 bcp a,#4 593 0107 2706 jreq L171 594 ; 142 UART2->CR2 |= (uint8_t)UART2_CR2_TEN; 596 0109 72165245 bset 21061,#3 598 010d 2004 jra L371 599 010f L171: 600 ; 147 UART2->CR2 &= (uint8_t)(~UART2_CR2_TEN); 602 010f 72175245 bres 21061,#3 603 0113 L371: 604 ; 149 if ((uint8_t)(Mode & UART2_MODE_RX_ENABLE)) 606 0113 7b19 ld a,(OFST+11,sp) 607 0115 a508 bcp a,#8 608 0117 2706 jreq L571 609 ; 152 UART2->CR2 |= (uint8_t)UART2_CR2_REN; 611 0119 72145245 bset 21061,#2 613 011d 2004 jra L771 614 011f L571: 615 ; 157 UART2->CR2 &= (uint8_t)(~UART2_CR2_REN); 617 011f 72155245 bres 21061,#2 618 0123 L771: 619 ; 161 if ((uint8_t)(SyncMode & UART2_SYNCMODE_CLOCK_DISABLE)) 621 0123 7b18 ld a,(OFST+10,sp) 622 0125 a580 bcp a,#128 623 0127 2706 jreq L102 624 ; 164 UART2->CR3 &= (uint8_t)(~UART2_CR3_CKEN); 626 0129 72175246 bres 21062,#3 628 012d 200a jra L302 629 012f L102: 630 ; 168 UART2->CR3 |= (uint8_t)((uint8_t)SyncMode & UART2_CR3_CKEN); 632 012f 7b18 ld a,(OFST+10,sp) 633 0131 a408 and a,#8 634 0133 ca5246 or a,21062 635 0136 c75246 ld 21062,a 636 0139 L302: 637 ; 170 } 640 0139 5b0e addw sp,#14 641 013b 81 ret 696 ; 178 void UART2_Cmd(FunctionalState NewState) 696 ; 179 { 697 .text: section .text,new 698 0000 _UART2_Cmd: 702 ; 181 if (NewState != DISABLE) 704 0000 4d tnz a 705 0001 2706 jreq L332 706 ; 184 UART2->CR1 &= (uint8_t)(~UART2_CR1_UARTD); 708 0003 721b5244 bres 21060,#5 710 0007 2004 jra L532 711 0009 L332: 712 ; 189 UART2->CR1 |= UART2_CR1_UARTD; 714 0009 721a5244 bset 21060,#5 715 000d L532: 716 ; 191 } 719 000d 81 ret 847 ; 208 void UART2_ITConfig(UART2_IT_TypeDef UART2_IT, FunctionalState NewState) 847 ; 209 { 848 .text: section .text,new 849 0000 _UART2_ITConfig: 851 0000 89 pushw x 852 0001 89 pushw x 853 00000002 OFST: set 2 856 ; 210 uint8_t uartreg = 0, itpos = 0x00; 860 ; 213 assert_param(IS_UART2_CONFIG_IT_OK(UART2_IT)); 862 ; 214 assert_param(IS_FUNCTIONALSTATE_OK(NewState)); 864 ; 217 uartreg = (uint8_t)((uint16_t)UART2_IT >> 0x08); 866 0002 9e ld a,xh 867 0003 6b01 ld (OFST-1,sp),a 868 ; 220 itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)UART2_IT & (uint8_t)0x0F)); 870 0005 9f ld a,xl 871 0006 a40f and a,#15 872 0008 5f clrw x 873 0009 97 ld xl,a 874 000a a601 ld a,#1 875 000c 5d tnzw x 876 000d 2704 jreq L61 877 000f L02: 878 000f 48 sll a 879 0010 5a decw x 880 0011 26fc jrne L02 881 0013 L61: 882 0013 6b02 ld (OFST+0,sp),a 883 ; 222 if (NewState != DISABLE) 885 0015 0d07 tnz (OFST+5,sp) 886 0017 273a jreq L313 887 ; 225 if (uartreg == 0x01) 889 0019 7b01 ld a,(OFST-1,sp) 890 001b a101 cp a,#1 891 001d 260a jrne L513 892 ; 227 UART2->CR1 |= itpos; 894 001f c65244 ld a,21060 895 0022 1a02 or a,(OFST+0,sp) 896 0024 c75244 ld 21060,a 898 0027 2066 jra L133 899 0029 L513: 900 ; 229 else if (uartreg == 0x02) 902 0029 7b01 ld a,(OFST-1,sp) 903 002b a102 cp a,#2 904 002d 260a jrne L123 905 ; 231 UART2->CR2 |= itpos; 907 002f c65245 ld a,21061 908 0032 1a02 or a,(OFST+0,sp) 909 0034 c75245 ld 21061,a 911 0037 2056 jra L133 912 0039 L123: 913 ; 233 else if (uartreg == 0x03) 915 0039 7b01 ld a,(OFST-1,sp) 916 003b a103 cp a,#3 917 003d 260a jrne L523 918 ; 235 UART2->CR4 |= itpos; 920 003f c65247 ld a,21063 921 0042 1a02 or a,(OFST+0,sp) 922 0044 c75247 ld 21063,a 924 0047 2046 jra L133 925 0049 L523: 926 ; 239 UART2->CR6 |= itpos; 928 0049 c65249 ld a,21065 929 004c 1a02 or a,(OFST+0,sp) 930 004e c75249 ld 21065,a 931 0051 203c jra L133 932 0053 L313: 933 ; 245 if (uartreg == 0x01) 935 0053 7b01 ld a,(OFST-1,sp) 936 0055 a101 cp a,#1 937 0057 260b jrne L333 938 ; 247 UART2->CR1 &= (uint8_t)(~itpos); 940 0059 7b02 ld a,(OFST+0,sp) 941 005b 43 cpl a 942 005c c45244 and a,21060 943 005f c75244 ld 21060,a 945 0062 202b jra L133 946 0064 L333: 947 ; 249 else if (uartreg == 0x02) 949 0064 7b01 ld a,(OFST-1,sp) 950 0066 a102 cp a,#2 951 0068 260b jrne L733 952 ; 251 UART2->CR2 &= (uint8_t)(~itpos); 954 006a 7b02 ld a,(OFST+0,sp) 955 006c 43 cpl a 956 006d c45245 and a,21061 957 0070 c75245 ld 21061,a 959 0073 201a jra L133 960 0075 L733: 961 ; 253 else if (uartreg == 0x03) 963 0075 7b01 ld a,(OFST-1,sp) 964 0077 a103 cp a,#3 965 0079 260b jrne L343 966 ; 255 UART2->CR4 &= (uint8_t)(~itpos); 968 007b 7b02 ld a,(OFST+0,sp) 969 007d 43 cpl a 970 007e c45247 and a,21063 971 0081 c75247 ld 21063,a 973 0084 2009 jra L133 974 0086 L343: 975 ; 259 UART2->CR6 &= (uint8_t)(~itpos); 977 0086 7b02 ld a,(OFST+0,sp) 978 0088 43 cpl a 979 0089 c45249 and a,21065 980 008c c75249 ld 21065,a 981 008f L133: 982 ; 262 } 985 008f 5b04 addw sp,#4 986 0091 81 ret 1043 ; 269 void UART2_IrDAConfig(UART2_IrDAMode_TypeDef UART2_IrDAMode) 1043 ; 270 { 1044 .text: section .text,new 1045 0000 _UART2_IrDAConfig: 1049 ; 271 assert_param(IS_UART2_IRDAMODE_OK(UART2_IrDAMode)); 1051 ; 273 if (UART2_IrDAMode != UART2_IRDAMODE_NORMAL) 1053 0000 4d tnz a 1054 0001 2706 jreq L573 1055 ; 275 UART2->CR5 |= UART2_CR5_IRLP; 1057 0003 72145248 bset 21064,#2 1059 0007 2004 jra L773 1060 0009 L573: 1061 ; 279 UART2->CR5 &= ((uint8_t)~UART2_CR5_IRLP); 1063 0009 72155248 bres 21064,#2 1064 000d L773: 1065 ; 281 } 1068 000d 81 ret 1103 ; 289 void UART2_IrDACmd(FunctionalState NewState) 1103 ; 290 { 1104 .text: section .text,new 1105 0000 _UART2_IrDACmd: 1109 ; 292 assert_param(IS_FUNCTIONALSTATE_OK(NewState)); 1111 ; 294 if (NewState != DISABLE) 1113 0000 4d tnz a 1114 0001 2706 jreq L714 1115 ; 297 UART2->CR5 |= UART2_CR5_IREN; 1117 0003 72125248 bset 21064,#1 1119 0007 2004 jra L124 1120 0009 L714: 1121 ; 302 UART2->CR5 &= ((uint8_t)~UART2_CR5_IREN); 1123 0009 72135248 bres 21064,#1 1124 000d L124: 1125 ; 304 } 1128 000d 81 ret 1187 ; 313 void UART2_LINBreakDetectionConfig(UART2_LINBreakDetectionLength_TypeDef UART2_LINBreakDetectionLength) 1187 ; 314 { 1188 .text: section .text,new 1189 0000 _UART2_LINBreakDetectionConfig: 1193 ; 316 assert_param(IS_UART2_LINBREAKDETECTIONLENGTH_OK(UART2_LINBreakDetectionLength)); 1195 ; 318 if (UART2_LINBreakDetectionLength != UART2_LINBREAKDETECTIONLENGTH_10BITS) 1197 0000 4d tnz a 1198 0001 2706 jreq L154 1199 ; 320 UART2->CR4 |= UART2_CR4_LBDL; 1201 0003 721a5247 bset 21063,#5 1203 0007 2004 jra L354 1204 0009 L154: 1205 ; 324 UART2->CR4 &= ((uint8_t)~UART2_CR4_LBDL); 1207 0009 721b5247 bres 21063,#5 1208 000d L354: 1209 ; 326 } 1212 000d 81 ret 1333 ; 338 void UART2_LINConfig(UART2_LinMode_TypeDef UART2_Mode, 1333 ; 339 UART2_LinAutosync_TypeDef UART2_Autosync, 1333 ; 340 UART2_LinDivUp_TypeDef UART2_DivUp) 1333 ; 341 { 1334 .text: section .text,new 1335 0000 _UART2_LINConfig: 1337 0000 89 pushw x 1338 00000000 OFST: set 0 1341 ; 343 assert_param(IS_UART2_SLAVE_OK(UART2_Mode)); 1343 ; 344 assert_param(IS_UART2_AUTOSYNC_OK(UART2_Autosync)); 1345 ; 345 assert_param(IS_UART2_DIVUP_OK(UART2_DivUp)); 1347 ; 347 if (UART2_Mode != UART2_LIN_MODE_MASTER) 1349 0001 9e ld a,xh 1350 0002 4d tnz a 1351 0003 2706 jreq L335 1352 ; 349 UART2->CR6 |= UART2_CR6_LSLV; 1354 0005 721a5249 bset 21065,#5 1356 0009 2004 jra L535 1357 000b L335: 1358 ; 353 UART2->CR6 &= ((uint8_t)~UART2_CR6_LSLV); 1360 000b 721b5249 bres 21065,#5 1361 000f L535: 1362 ; 356 if (UART2_Autosync != UART2_LIN_AUTOSYNC_DISABLE) 1364 000f 0d02 tnz (OFST+2,sp) 1365 0011 2706 jreq L735 1366 ; 358 UART2->CR6 |= UART2_CR6_LASE ; 1368 0013 72185249 bset 21065,#4 1370 0017 2004 jra L145 1371 0019 L735: 1372 ; 362 UART2->CR6 &= ((uint8_t)~ UART2_CR6_LASE ); 1374 0019 72195249 bres 21065,#4 1375 001d L145: 1376 ; 365 if (UART2_DivUp != UART2_LIN_DIVUP_LBRR1) 1378 001d 0d05 tnz (OFST+5,sp) 1379 001f 2706 jreq L345 1380 ; 367 UART2->CR6 |= UART2_CR6_LDUM; 1382 0021 721e5249 bset 21065,#7 1384 0025 2004 jra L545 1385 0027 L345: 1386 ; 371 UART2->CR6 &= ((uint8_t)~ UART2_CR6_LDUM); 1388 0027 721f5249 bres 21065,#7 1389 002b L545: 1390 ; 373 } 1393 002b 85 popw x 1394 002c 81 ret 1429 ; 381 void UART2_LINCmd(FunctionalState NewState) 1429 ; 382 { 1430 .text: section .text,new 1431 0000 _UART2_LINCmd: 1435 ; 383 assert_param(IS_FUNCTIONALSTATE_OK(NewState)); 1437 ; 385 if (NewState != DISABLE) 1439 0000 4d tnz a 1440 0001 2706 jreq L565 1441 ; 388 UART2->CR3 |= UART2_CR3_LINEN; 1443 0003 721c5246 bset 21062,#6 1445 0007 2004 jra L765 1446 0009 L565: 1447 ; 393 UART2->CR3 &= ((uint8_t)~UART2_CR3_LINEN); 1449 0009 721d5246 bres 21062,#6 1450 000d L765: 1451 ; 395 } 1454 000d 81 ret 1489 ; 402 void UART2_SmartCardCmd(FunctionalState NewState) 1489 ; 403 { 1490 .text: section .text,new 1491 0000 _UART2_SmartCardCmd: 1495 ; 405 assert_param(IS_FUNCTIONALSTATE_OK(NewState)); 1497 ; 407 if (NewState != DISABLE) 1499 0000 4d tnz a 1500 0001 2706 jreq L706 1501 ; 410 UART2->CR5 |= UART2_CR5_SCEN; 1503 0003 721a5248 bset 21064,#5 1505 0007 2004 jra L116 1506 0009 L706: 1507 ; 415 UART2->CR5 &= ((uint8_t)(~UART2_CR5_SCEN)); 1509 0009 721b5248 bres 21064,#5 1510 000d L116: 1511 ; 417 } 1514 000d 81 ret 1550 ; 425 void UART2_SmartCardNACKCmd(FunctionalState NewState) 1550 ; 426 { 1551 .text: section .text,new 1552 0000 _UART2_SmartCardNACKCmd: 1556 ; 428 assert_param(IS_FUNCTIONALSTATE_OK(NewState)); 1558 ; 430 if (NewState != DISABLE) 1560 0000 4d tnz a 1561 0001 2706 jreq L136 1562 ; 433 UART2->CR5 |= UART2_CR5_NACK; 1564 0003 72185248 bset 21064,#4 1566 0007 2004 jra L336 1567 0009 L136: 1568 ; 438 UART2->CR5 &= ((uint8_t)~(UART2_CR5_NACK)); 1570 0009 72195248 bres 21064,#4 1571 000d L336: 1572 ; 440 } 1575 000d 81 ret 1632 ; 448 void UART2_WakeUpConfig(UART2_WakeUp_TypeDef UART2_WakeUp) 1632 ; 449 { 1633 .text: section .text,new 1634 0000 _UART2_WakeUpConfig: 1638 ; 450 assert_param(IS_UART2_WAKEUP_OK(UART2_WakeUp)); 1640 ; 452 UART2->CR1 &= ((uint8_t)~UART2_CR1_WAKE); 1642 0000 72175244 bres 21060,#3 1643 ; 453 UART2->CR1 |= (uint8_t)UART2_WakeUp; 1645 0004 ca5244 or a,21060 1646 0007 c75244 ld 21060,a 1647 ; 454 } 1650 000a 81 ret 1686 ; 462 void UART2_ReceiverWakeUpCmd(FunctionalState NewState) 1686 ; 463 { 1687 .text: section .text,new 1688 0000 _UART2_ReceiverWakeUpCmd: 1692 ; 464 assert_param(IS_FUNCTIONALSTATE_OK(NewState)); 1694 ; 466 if (NewState != DISABLE) 1696 0000 4d tnz a 1697 0001 2706 jreq L107 1698 ; 469 UART2->CR2 |= UART2_CR2_RWU; 1700 0003 72125245 bset 21061,#1 1702 0007 2004 jra L307 1703 0009 L107: 1704 ; 474 UART2->CR2 &= ((uint8_t)~UART2_CR2_RWU); 1706 0009 72135245 bres 21061,#1 1707 000d L307: 1708 ; 476 } 1711 000d 81 ret 1734 ; 483 uint8_t UART2_ReceiveData8(void) 1734 ; 484 { 1735 .text: section .text,new 1736 0000 _UART2_ReceiveData8: 1740 ; 485 return ((uint8_t)UART2->DR); 1742 0000 c65241 ld a,21057 1745 0003 81 ret 1777 ; 493 uint16_t UART2_ReceiveData9(void) 1777 ; 494 { 1778 .text: section .text,new 1779 0000 _UART2_ReceiveData9: 1781 0000 89 pushw x 1782 00000002 OFST: set 2 1785 ; 495 uint16_t temp = 0; 1787 ; 497 temp = ((uint16_t)(((uint16_t)((uint16_t)UART2->CR1 & (uint16_t)UART2_CR1_R8)) << 1)); 1789 0001 c65244 ld a,21060 1790 0004 5f clrw x 1791 0005 a480 and a,#128 1792 0007 5f clrw x 1793 0008 02 rlwa x,a 1794 0009 58 sllw x 1795 000a 1f01 ldw (OFST-1,sp),x 1796 ; 499 return (uint16_t)((((uint16_t)UART2->DR) | temp) & ((uint16_t)0x01FF)); 1798 000c c65241 ld a,21057 1799 000f 5f clrw x 1800 0010 97 ld xl,a 1801 0011 01 rrwa x,a 1802 0012 1a02 or a,(OFST+0,sp) 1803 0014 01 rrwa x,a 1804 0015 1a01 or a,(OFST-1,sp) 1805 0017 01 rrwa x,a 1806 0018 01 rrwa x,a 1807 0019 a4ff and a,#255 1808 001b 01 rrwa x,a 1809 001c a401 and a,#1 1810 001e 01 rrwa x,a 1813 001f 5b02 addw sp,#2 1814 0021 81 ret 1846 ; 507 void UART2_SendData8(uint8_t Data) 1846 ; 508 { 1847 .text: section .text,new 1848 0000 _UART2_SendData8: 1852 ; 510 UART2->DR = Data; 1854 0000 c75241 ld 21057,a 1855 ; 511 } 1858 0003 81 ret 1890 ; 518 void UART2_SendData9(uint16_t Data) 1890 ; 519 { 1891 .text: section .text,new 1892 0000 _UART2_SendData9: 1894 0000 89 pushw x 1895 00000000 OFST: set 0 1898 ; 521 UART2->CR1 &= ((uint8_t)~UART2_CR1_T8); 1900 0001 721d5244 bres 21060,#6 1901 ; 524 UART2->CR1 |= (uint8_t)(((uint8_t)(Data >> 2)) & UART2_CR1_T8); 1903 0005 54 srlw x 1904 0006 54 srlw x 1905 0007 9f ld a,xl 1906 0008 a440 and a,#64 1907 000a ca5244 or a,21060 1908 000d c75244 ld 21060,a 1909 ; 527 UART2->DR = (uint8_t)(Data); 1911 0010 7b02 ld a,(OFST+2,sp) 1912 0012 c75241 ld 21057,a 1913 ; 529 } 1916 0015 85 popw x 1917 0016 81 ret 1940 ; 536 void UART2_SendBreak(void) 1940 ; 537 { 1941 .text: section .text,new 1942 0000 _UART2_SendBreak: 1946 ; 538 UART2->CR2 |= UART2_CR2_SBK; 1948 0000 72105245 bset 21061,#0 1949 ; 539 } 1952 0004 81 ret 1984 ; 546 void UART2_SetAddress(uint8_t UART2_Address) 1984 ; 547 { 1985 .text: section .text,new 1986 0000 _UART2_SetAddress: 1988 0000 88 push a 1989 00000000 OFST: set 0 1992 ; 549 assert_param(IS_UART2_ADDRESS_OK(UART2_Address)); 1994 ; 552 UART2->CR4 &= ((uint8_t)~UART2_CR4_ADD); 1996 0001 c65247 ld a,21063 1997 0004 a4f0 and a,#240 1998 0006 c75247 ld 21063,a 1999 ; 554 UART2->CR4 |= UART2_Address; 2001 0009 c65247 ld a,21063 2002 000c 1a01 or a,(OFST+1,sp) 2003 000e c75247 ld 21063,a 2004 ; 555 } 2007 0011 84 pop a 2008 0012 81 ret 2040 ; 563 void UART2_SetGuardTime(uint8_t UART2_GuardTime) 2040 ; 564 { 2041 .text: section .text,new 2042 0000 _UART2_SetGuardTime: 2046 ; 566 UART2->GTR = UART2_GuardTime; 2048 0000 c7524a ld 21066,a 2049 ; 567 } 2052 0003 81 ret 2084 ; 591 void UART2_SetPrescaler(uint8_t UART2_Prescaler) 2084 ; 592 { 2085 .text: section .text,new 2086 0000 _UART2_SetPrescaler: 2090 ; 594 UART2->PSCR = UART2_Prescaler; 2092 0000 c7524b ld 21067,a 2093 ; 595 } 2096 0003 81 ret 2253 ; 603 FlagStatus UART2_GetFlagStatus(UART2_Flag_TypeDef UART2_FLAG) 2253 ; 604 { 2254 .text: section .text,new 2255 0000 _UART2_GetFlagStatus: 2257 0000 89 pushw x 2258 0001 88 push a 2259 00000001 OFST: set 1 2262 ; 605 FlagStatus status = RESET; 2264 ; 608 assert_param(IS_UART2_FLAG_OK(UART2_FLAG)); 2266 ; 611 if (UART2_FLAG == UART2_FLAG_LBDF) 2268 0002 a30210 cpw x,#528 2269 0005 2610 jrne L3211 2270 ; 613 if ((UART2->CR4 & (uint8_t)UART2_FLAG) != (uint8_t)0x00) 2272 0007 9f ld a,xl 2273 0008 c45247 and a,21063 2274 000b 2706 jreq L5211 2275 ; 616 status = SET; 2277 000d a601 ld a,#1 2278 000f 6b01 ld (OFST+0,sp),a 2280 0011 2039 jra L1311 2281 0013 L5211: 2282 ; 621 status = RESET; 2284 0013 0f01 clr (OFST+0,sp) 2285 0015 2035 jra L1311 2286 0017 L3211: 2287 ; 624 else if (UART2_FLAG == UART2_FLAG_SBK) 2289 0017 1e02 ldw x,(OFST+1,sp) 2290 0019 a30101 cpw x,#257 2291 001c 2611 jrne L3311 2292 ; 626 if ((UART2->CR2 & (uint8_t)UART2_FLAG) != (uint8_t)0x00) 2294 001e c65245 ld a,21061 2295 0021 1503 bcp a,(OFST+2,sp) 2296 0023 2706 jreq L5311 2297 ; 629 status = SET; 2299 0025 a601 ld a,#1 2300 0027 6b01 ld (OFST+0,sp),a 2302 0029 2021 jra L1311 2303 002b L5311: 2304 ; 634 status = RESET; 2306 002b 0f01 clr (OFST+0,sp) 2307 002d 201d jra L1311 2308 002f L3311: 2309 ; 637 else if ((UART2_FLAG == UART2_FLAG_LHDF) || (UART2_FLAG == UART2_FLAG_LSF)) 2311 002f 1e02 ldw x,(OFST+1,sp) 2312 0031 a30302 cpw x,#770 2313 0034 2707 jreq L5411 2315 0036 1e02 ldw x,(OFST+1,sp) 2316 0038 a30301 cpw x,#769 2317 003b 2614 jrne L3411 2318 003d L5411: 2319 ; 639 if ((UART2->CR6 & (uint8_t)UART2_FLAG) != (uint8_t)0x00) 2321 003d c65249 ld a,21065 2322 0040 1503 bcp a,(OFST+2,sp) 2323 0042 2706 jreq L7411 2324 ; 642 status = SET; 2326 0044 a601 ld a,#1 2327 0046 6b01 ld (OFST+0,sp),a 2329 0048 2002 jra L1311 2330 004a L7411: 2331 ; 647 status = RESET; 2333 004a 0f01 clr (OFST+0,sp) 2334 004c L1311: 2335 ; 665 return status; 2337 004c 7b01 ld a,(OFST+0,sp) 2340 004e 5b03 addw sp,#3 2341 0050 81 ret 2342 0051 L3411: 2343 ; 652 if ((UART2->SR & (uint8_t)UART2_FLAG) != (uint8_t)0x00) 2345 0051 c65240 ld a,21056 2346 0054 1503 bcp a,(OFST+2,sp) 2347 0056 2706 jreq L5511 2348 ; 655 status = SET; 2350 0058 a601 ld a,#1 2351 005a 6b01 ld (OFST+0,sp),a 2353 005c 20ee jra L1311 2354 005e L5511: 2355 ; 660 status = RESET; 2357 005e 0f01 clr (OFST+0,sp) 2358 0060 20ea jra L1311 2393 ; 695 void UART2_ClearFlag(UART2_Flag_TypeDef UART2_FLAG) 2393 ; 696 { 2394 .text: section .text,new 2395 0000 _UART2_ClearFlag: 2397 0000 89 pushw x 2398 00000000 OFST: set 0 2401 ; 697 assert_param(IS_UART2_CLEAR_FLAG_OK(UART2_FLAG)); 2403 ; 700 if (UART2_FLAG == UART2_FLAG_RXNE) 2405 0001 a30020 cpw x,#32 2406 0004 2606 jrne L7711 2407 ; 702 UART2->SR = (uint8_t)~(UART2_SR_RXNE); 2409 0006 35df5240 mov 21056,#223 2411 000a 201e jra L1021 2412 000c L7711: 2413 ; 705 else if (UART2_FLAG == UART2_FLAG_LBDF) 2415 000c 1e01 ldw x,(OFST+1,sp) 2416 000e a30210 cpw x,#528 2417 0011 2606 jrne L3021 2418 ; 707 UART2->CR4 &= (uint8_t)(~UART2_CR4_LBDF); 2420 0013 72195247 bres 21063,#4 2422 0017 2011 jra L1021 2423 0019 L3021: 2424 ; 710 else if (UART2_FLAG == UART2_FLAG_LHDF) 2426 0019 1e01 ldw x,(OFST+1,sp) 2427 001b a30302 cpw x,#770 2428 001e 2606 jrne L7021 2429 ; 712 UART2->CR6 &= (uint8_t)(~UART2_CR6_LHDF); 2431 0020 72135249 bres 21065,#1 2433 0024 2004 jra L1021 2434 0026 L7021: 2435 ; 717 UART2->CR6 &= (uint8_t)(~UART2_CR6_LSF); 2437 0026 72115249 bres 21065,#0 2438 002a L1021: 2439 ; 719 } 2442 002a 85 popw x 2443 002b 81 ret 2517 ; 734 ITStatus UART2_GetITStatus(UART2_IT_TypeDef UART2_IT) 2517 ; 735 { 2518 .text: section .text,new 2519 0000 _UART2_GetITStatus: 2521 0000 89 pushw x 2522 0001 89 pushw x 2523 00000002 OFST: set 2 2526 ; 736 ITStatus pendingbitstatus = RESET; 2528 ; 737 uint8_t itpos = 0; 2530 ; 738 uint8_t itmask1 = 0; 2532 ; 739 uint8_t itmask2 = 0; 2534 ; 740 uint8_t enablestatus = 0; 2536 ; 743 assert_param(IS_UART2_GET_IT_OK(UART2_IT)); 2538 ; 746 itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)UART2_IT & (uint8_t)0x0F)); 2540 0002 9f ld a,xl 2541 0003 a40f and a,#15 2542 0005 5f clrw x 2543 0006 97 ld xl,a 2544 0007 a601 ld a,#1 2545 0009 5d tnzw x 2546 000a 2704 jreq L27 2547 000c L47: 2548 000c 48 sll a 2549 000d 5a decw x 2550 000e 26fc jrne L47 2551 0010 L27: 2552 0010 6b01 ld (OFST-1,sp),a 2553 ; 748 itmask1 = (uint8_t)((uint8_t)UART2_IT >> (uint8_t)4); 2555 0012 7b04 ld a,(OFST+2,sp) 2556 0014 4e swap a 2557 0015 a40f and a,#15 2558 0017 6b02 ld (OFST+0,sp),a 2559 ; 750 itmask2 = (uint8_t)((uint8_t)1 << itmask1); 2561 0019 7b02 ld a,(OFST+0,sp) 2562 001b 5f clrw x 2563 001c 97 ld xl,a 2564 001d a601 ld a,#1 2565 001f 5d tnzw x 2566 0020 2704 jreq L67 2567 0022 L001: 2568 0022 48 sll a 2569 0023 5a decw x 2570 0024 26fc jrne L001 2571 0026 L67: 2572 0026 6b02 ld (OFST+0,sp),a 2573 ; 753 if (UART2_IT == UART2_IT_PE) 2575 0028 1e03 ldw x,(OFST+1,sp) 2576 002a a30100 cpw x,#256 2577 002d 261c jrne L5421 2578 ; 756 enablestatus = (uint8_t)((uint8_t)UART2->CR1 & itmask2); 2580 002f c65244 ld a,21060 2581 0032 1402 and a,(OFST+0,sp) 2582 0034 6b02 ld (OFST+0,sp),a 2583 ; 759 if (((UART2->SR & itpos) != (uint8_t)0x00) && enablestatus) 2585 0036 c65240 ld a,21056 2586 0039 1501 bcp a,(OFST-1,sp) 2587 003b 270a jreq L7421 2589 003d 0d02 tnz (OFST+0,sp) 2590 003f 2706 jreq L7421 2591 ; 762 pendingbitstatus = SET; 2593 0041 a601 ld a,#1 2594 0043 6b02 ld (OFST+0,sp),a 2596 0045 2064 jra L3521 2597 0047 L7421: 2598 ; 767 pendingbitstatus = RESET; 2600 0047 0f02 clr (OFST+0,sp) 2601 0049 2060 jra L3521 2602 004b L5421: 2603 ; 770 else if (UART2_IT == UART2_IT_LBDF) 2605 004b 1e03 ldw x,(OFST+1,sp) 2606 004d a30346 cpw x,#838 2607 0050 261c jrne L5521 2608 ; 773 enablestatus = (uint8_t)((uint8_t)UART2->CR4 & itmask2); 2610 0052 c65247 ld a,21063 2611 0055 1402 and a,(OFST+0,sp) 2612 0057 6b02 ld (OFST+0,sp),a 2613 ; 775 if (((UART2->CR4 & itpos) != (uint8_t)0x00) && enablestatus) 2615 0059 c65247 ld a,21063 2616 005c 1501 bcp a,(OFST-1,sp) 2617 005e 270a jreq L7521 2619 0060 0d02 tnz (OFST+0,sp) 2620 0062 2706 jreq L7521 2621 ; 778 pendingbitstatus = SET; 2623 0064 a601 ld a,#1 2624 0066 6b02 ld (OFST+0,sp),a 2626 0068 2041 jra L3521 2627 006a L7521: 2628 ; 783 pendingbitstatus = RESET; 2630 006a 0f02 clr (OFST+0,sp) 2631 006c 203d jra L3521 2632 006e L5521: 2633 ; 786 else if (UART2_IT == UART2_IT_LHDF) 2635 006e 1e03 ldw x,(OFST+1,sp) 2636 0070 a30412 cpw x,#1042 2637 0073 261c jrne L5621 2638 ; 789 enablestatus = (uint8_t)((uint8_t)UART2->CR6 & itmask2); 2640 0075 c65249 ld a,21065 2641 0078 1402 and a,(OFST+0,sp) 2642 007a 6b02 ld (OFST+0,sp),a 2643 ; 791 if (((UART2->CR6 & itpos) != (uint8_t)0x00) && enablestatus) 2645 007c c65249 ld a,21065 2646 007f 1501 bcp a,(OFST-1,sp) 2647 0081 270a jreq L7621 2649 0083 0d02 tnz (OFST+0,sp) 2650 0085 2706 jreq L7621 2651 ; 794 pendingbitstatus = SET; 2653 0087 a601 ld a,#1 2654 0089 6b02 ld (OFST+0,sp),a 2656 008b 201e jra L3521 2657 008d L7621: 2658 ; 799 pendingbitstatus = RESET; 2660 008d 0f02 clr (OFST+0,sp) 2661 008f 201a jra L3521 2662 0091 L5621: 2663 ; 805 enablestatus = (uint8_t)((uint8_t)UART2->CR2 & itmask2); 2665 0091 c65245 ld a,21061 2666 0094 1402 and a,(OFST+0,sp) 2667 0096 6b02 ld (OFST+0,sp),a 2668 ; 807 if (((UART2->SR & itpos) != (uint8_t)0x00) && enablestatus) 2670 0098 c65240 ld a,21056 2671 009b 1501 bcp a,(OFST-1,sp) 2672 009d 270a jreq L5721 2674 009f 0d02 tnz (OFST+0,sp) 2675 00a1 2706 jreq L5721 2676 ; 810 pendingbitstatus = SET; 2678 00a3 a601 ld a,#1 2679 00a5 6b02 ld (OFST+0,sp),a 2681 00a7 2002 jra L3521 2682 00a9 L5721: 2683 ; 815 pendingbitstatus = RESET; 2685 00a9 0f02 clr (OFST+0,sp) 2686 00ab L3521: 2687 ; 819 return pendingbitstatus; 2689 00ab 7b02 ld a,(OFST+0,sp) 2692 00ad 5b04 addw sp,#4 2693 00af 81 ret 2729 ; 848 void UART2_ClearITPendingBit(UART2_IT_TypeDef UART2_IT) 2729 ; 849 { 2730 .text: section .text,new 2731 0000 _UART2_ClearITPendingBit: 2733 0000 89 pushw x 2734 00000000 OFST: set 0 2737 ; 850 assert_param(IS_UART2_CLEAR_IT_OK(UART2_IT)); 2739 ; 853 if (UART2_IT == UART2_IT_RXNE) 2741 0001 a30255 cpw x,#597 2742 0004 2606 jrne L7131 2743 ; 855 UART2->SR = (uint8_t)~(UART2_SR_RXNE); 2745 0006 35df5240 mov 21056,#223 2747 000a 2011 jra L1231 2748 000c L7131: 2749 ; 858 else if (UART2_IT == UART2_IT_LBDF) 2751 000c 1e01 ldw x,(OFST+1,sp) 2752 000e a30346 cpw x,#838 2753 0011 2606 jrne L3231 2754 ; 860 UART2->CR4 &= (uint8_t)~(UART2_CR4_LBDF); 2756 0013 72195247 bres 21063,#4 2758 0017 2004 jra L1231 2759 0019 L3231: 2760 ; 865 UART2->CR6 &= (uint8_t)(~UART2_CR6_LHDF); 2762 0019 72135249 bres 21065,#1 2763 001d L1231: 2764 ; 867 } 2767 001d 85 popw x 2768 001e 81 ret 2781 xdef _UART2_ClearITPendingBit 2782 xdef _UART2_GetITStatus 2783 xdef _UART2_ClearFlag 2784 xdef _UART2_GetFlagStatus 2785 xdef _UART2_SetPrescaler 2786 xdef _UART2_SetGuardTime 2787 xdef _UART2_SetAddress 2788 xdef _UART2_SendBreak 2789 xdef _UART2_SendData9 2790 xdef _UART2_SendData8 2791 xdef _UART2_ReceiveData9 2792 xdef _UART2_ReceiveData8 2793 xdef _UART2_ReceiverWakeUpCmd 2794 xdef _UART2_WakeUpConfig 2795 xdef _UART2_SmartCardNACKCmd 2796 xdef _UART2_SmartCardCmd 2797 xdef _UART2_LINCmd 2798 xdef _UART2_LINConfig 2799 xdef _UART2_LINBreakDetectionConfig 2800 xdef _UART2_IrDACmd 2801 xdef _UART2_IrDAConfig 2802 xdef _UART2_ITConfig 2803 xdef _UART2_Cmd 2804 xdef _UART2_Init 2805 xdef _UART2_DeInit 2806 xref _CLK_GetClockFreq 2807 xref.b c_lreg 2808 xref.b c_x 2827 xref c_lursh 2828 xref c_lsub 2829 xref c_smul 2830 xref c_ludv 2831 xref c_rtol 2832 xref c_llsh 2833 xref c_ltor 2834 end