1 ; C Compiler for STM8 (COSMIC Software) 2 ; Parser V4.12.9 - 19 Apr 2023 3 ; Generator (Limited) V4.5.6 - 18 Jul 2023 44 ; 43 void TIM4_DeInit(void) 44 ; 44 { 46 .text: section .text,new 47 0000 _TIM4_DeInit: 51 ; 45 TIM4->CR1 = TIM4_CR1_RESET_VALUE; 53 0000 725f5340 clr 21312 54 ; 46 TIM4->IER = TIM4_IER_RESET_VALUE; 56 0004 725f5341 clr 21313 57 ; 47 TIM4->CNTR = TIM4_CNTR_RESET_VALUE; 59 0008 725f5344 clr 21316 60 ; 48 TIM4->PSCR = TIM4_PSCR_RESET_VALUE; 62 000c 725f5345 clr 21317 63 ; 49 TIM4->ARR = TIM4_ARR_RESET_VALUE; 65 0010 35ff5346 mov 21318,#255 66 ; 50 TIM4->SR1 = TIM4_SR1_RESET_VALUE; 68 0014 725f5342 clr 21314 69 ; 51 } 72 0018 81 ret 176 ; 59 void TIM4_TimeBaseInit(TIM4_Prescaler_TypeDef TIM4_Prescaler, uint8_t TIM4_Period) 176 ; 60 { 177 .text: section .text,new 178 0000 _TIM4_TimeBaseInit: 182 ; 62 assert_param(IS_TIM4_PRESCALER_OK(TIM4_Prescaler)); 184 ; 64 TIM4->PSCR = (uint8_t)(TIM4_Prescaler); 186 0000 9e ld a,xh 187 0001 c75345 ld 21317,a 188 ; 66 TIM4->ARR = (uint8_t)(TIM4_Period); 190 0004 9f ld a,xl 191 0005 c75346 ld 21318,a 192 ; 67 } 195 0008 81 ret 250 ; 77 void TIM4_Cmd(FunctionalState NewState) 250 ; 78 { 251 .text: section .text,new 252 0000 _TIM4_Cmd: 256 ; 80 assert_param(IS_FUNCTIONALSTATE_OK(NewState)); 258 ; 83 if (NewState != DISABLE) 260 0000 4d tnz a 261 0001 2706 jreq L311 262 ; 85 TIM4->CR1 |= TIM4_CR1_CEN; 264 0003 72105340 bset 21312,#0 266 0007 2004 jra L511 267 0009 L311: 268 ; 89 TIM4->CR1 &= (uint8_t)(~TIM4_CR1_CEN); 270 0009 72115340 bres 21312,#0 271 000d L511: 272 ; 91 } 275 000d 81 ret 333 ; 103 void TIM4_ITConfig(TIM4_IT_TypeDef TIM4_IT, FunctionalState NewState) 333 ; 104 { 334 .text: section .text,new 335 0000 _TIM4_ITConfig: 337 0000 89 pushw x 338 00000000 OFST: set 0 341 ; 106 assert_param(IS_TIM4_IT_OK(TIM4_IT)); 343 ; 107 assert_param(IS_FUNCTIONALSTATE_OK(NewState)); 345 ; 109 if (NewState != DISABLE) 347 0001 9f ld a,xl 348 0002 4d tnz a 349 0003 2709 jreq L741 350 ; 112 TIM4->IER |= (uint8_t)TIM4_IT; 352 0005 9e ld a,xh 353 0006 ca5341 or a,21313 354 0009 c75341 ld 21313,a 356 000c 2009 jra L151 357 000e L741: 358 ; 117 TIM4->IER &= (uint8_t)(~TIM4_IT); 360 000e 7b01 ld a,(OFST+1,sp) 361 0010 43 cpl a 362 0011 c45341 and a,21313 363 0014 c75341 ld 21313,a 364 0017 L151: 365 ; 119 } 368 0017 85 popw x 369 0018 81 ret 405 ; 127 void TIM4_UpdateDisableConfig(FunctionalState NewState) 405 ; 128 { 406 .text: section .text,new 407 0000 _TIM4_UpdateDisableConfig: 411 ; 130 assert_param(IS_FUNCTIONALSTATE_OK(NewState)); 413 ; 133 if (NewState != DISABLE) 415 0000 4d tnz a 416 0001 2706 jreq L171 417 ; 135 TIM4->CR1 |= TIM4_CR1_UDIS; 419 0003 72125340 bset 21312,#1 421 0007 2004 jra L371 422 0009 L171: 423 ; 139 TIM4->CR1 &= (uint8_t)(~TIM4_CR1_UDIS); 425 0009 72135340 bres 21312,#1 426 000d L371: 427 ; 141 } 430 000d 81 ret 488 ; 151 void TIM4_UpdateRequestConfig(TIM4_UpdateSource_TypeDef TIM4_UpdateSource) 488 ; 152 { 489 .text: section .text,new 490 0000 _TIM4_UpdateRequestConfig: 494 ; 154 assert_param(IS_TIM4_UPDATE_SOURCE_OK(TIM4_UpdateSource)); 496 ; 157 if (TIM4_UpdateSource != TIM4_UPDATESOURCE_GLOBAL) 498 0000 4d tnz a 499 0001 2706 jreq L322 500 ; 159 TIM4->CR1 |= TIM4_CR1_URS; 502 0003 72145340 bset 21312,#2 504 0007 2004 jra L522 505 0009 L322: 506 ; 163 TIM4->CR1 &= (uint8_t)(~TIM4_CR1_URS); 508 0009 72155340 bres 21312,#2 509 000d L522: 510 ; 165 } 513 000d 81 ret 570 ; 175 void TIM4_SelectOnePulseMode(TIM4_OPMode_TypeDef TIM4_OPMode) 570 ; 176 { 571 .text: section .text,new 572 0000 _TIM4_SelectOnePulseMode: 576 ; 178 assert_param(IS_TIM4_OPM_MODE_OK(TIM4_OPMode)); 578 ; 181 if (TIM4_OPMode != TIM4_OPMODE_REPETITIVE) 580 0000 4d tnz a 581 0001 2706 jreq L552 582 ; 183 TIM4->CR1 |= TIM4_CR1_OPM; 584 0003 72165340 bset 21312,#3 586 0007 2004 jra L752 587 0009 L552: 588 ; 187 TIM4->CR1 &= (uint8_t)(~TIM4_CR1_OPM); 590 0009 72175340 bres 21312,#3 591 000d L752: 592 ; 190 } 595 000d 81 ret 663 ; 212 void TIM4_PrescalerConfig(TIM4_Prescaler_TypeDef Prescaler, TIM4_PSCReloadMode_TypeDef TIM4_PSCReloadMode) 663 ; 213 { 664 .text: section .text,new 665 0000 _TIM4_PrescalerConfig: 669 ; 215 assert_param(IS_TIM4_PRESCALER_RELOAD_OK(TIM4_PSCReloadMode)); 671 ; 216 assert_param(IS_TIM4_PRESCALER_OK(Prescaler)); 673 ; 219 TIM4->PSCR = (uint8_t)Prescaler; 675 0000 9e ld a,xh 676 0001 c75345 ld 21317,a 677 ; 222 TIM4->EGR = (uint8_t)TIM4_PSCReloadMode; 679 0004 9f ld a,xl 680 0005 c75343 ld 21315,a 681 ; 223 } 684 0008 81 ret 720 ; 231 void TIM4_ARRPreloadConfig(FunctionalState NewState) 720 ; 232 { 721 .text: section .text,new 722 0000 _TIM4_ARRPreloadConfig: 726 ; 234 assert_param(IS_FUNCTIONALSTATE_OK(NewState)); 728 ; 237 if (NewState != DISABLE) 730 0000 4d tnz a 731 0001 2706 jreq L133 732 ; 239 TIM4->CR1 |= TIM4_CR1_ARPE; 734 0003 721e5340 bset 21312,#7 736 0007 2004 jra L333 737 0009 L133: 738 ; 243 TIM4->CR1 &= (uint8_t)(~TIM4_CR1_ARPE); 740 0009 721f5340 bres 21312,#7 741 000d L333: 742 ; 245 } 745 000d 81 ret 794 ; 254 void TIM4_GenerateEvent(TIM4_EventSource_TypeDef TIM4_EventSource) 794 ; 255 { 795 .text: section .text,new 796 0000 _TIM4_GenerateEvent: 800 ; 257 assert_param(IS_TIM4_EVENT_SOURCE_OK(TIM4_EventSource)); 802 ; 260 TIM4->EGR = (uint8_t)(TIM4_EventSource); 804 0000 c75343 ld 21315,a 805 ; 261 } 808 0003 81 ret 840 ; 270 void TIM4_SetCounter(uint8_t Counter) 840 ; 271 { 841 .text: section .text,new 842 0000 _TIM4_SetCounter: 846 ; 273 TIM4->CNTR = (uint8_t)(Counter); 848 0000 c75344 ld 21316,a 849 ; 274 } 852 0003 81 ret 884 ; 283 void TIM4_SetAutoreload(uint8_t Autoreload) 884 ; 284 { 885 .text: section .text,new 886 0000 _TIM4_SetAutoreload: 890 ; 286 TIM4->ARR = (uint8_t)(Autoreload); 892 0000 c75346 ld 21318,a 893 ; 287 } 896 0003 81 ret 919 ; 294 uint8_t TIM4_GetCounter(void) 919 ; 295 { 920 .text: section .text,new 921 0000 _TIM4_GetCounter: 925 ; 297 return (uint8_t)(TIM4->CNTR); 927 0000 c65344 ld a,21316 930 0003 81 ret 954 ; 305 TIM4_Prescaler_TypeDef TIM4_GetPrescaler(void) 954 ; 306 { 955 .text: section .text,new 956 0000 _TIM4_GetPrescaler: 960 ; 308 return (TIM4_Prescaler_TypeDef)(TIM4->PSCR); 962 0000 c65345 ld a,21317 965 0003 81 ret 1044 ; 318 FlagStatus TIM4_GetFlagStatus(TIM4_FLAG_TypeDef TIM4_FLAG) 1044 ; 319 { 1045 .text: section .text,new 1046 0000 _TIM4_GetFlagStatus: 1048 0000 88 push a 1049 00000001 OFST: set 1 1052 ; 320 FlagStatus bitstatus = RESET; 1054 ; 323 assert_param(IS_TIM4_GET_FLAG_OK(TIM4_FLAG)); 1056 ; 325 if ((TIM4->SR1 & (uint8_t)TIM4_FLAG) != 0) 1058 0001 c45342 and a,21314 1059 0004 2706 jreq L174 1060 ; 327 bitstatus = SET; 1062 0006 a601 ld a,#1 1063 0008 6b01 ld (OFST+0,sp),a 1066 000a 2002 jra L374 1067 000c L174: 1068 ; 331 bitstatus = RESET; 1070 000c 0f01 clr (OFST+0,sp) 1072 000e L374: 1073 ; 333 return ((FlagStatus)bitstatus); 1075 000e 7b01 ld a,(OFST+0,sp) 1078 0010 5b01 addw sp,#1 1079 0012 81 ret 1114 ; 343 void TIM4_ClearFlag(TIM4_FLAG_TypeDef TIM4_FLAG) 1114 ; 344 { 1115 .text: section .text,new 1116 0000 _TIM4_ClearFlag: 1120 ; 346 assert_param(IS_TIM4_GET_FLAG_OK(TIM4_FLAG)); 1122 ; 349 TIM4->SR1 = (uint8_t)(~TIM4_FLAG); 1124 0000 43 cpl a 1125 0001 c75342 ld 21314,a 1126 ; 351 } 1129 0004 81 ret 1189 ; 360 ITStatus TIM4_GetITStatus(TIM4_IT_TypeDef TIM4_IT) 1189 ; 361 { 1190 .text: section .text,new 1191 0000 _TIM4_GetITStatus: 1193 0000 88 push a 1194 0001 89 pushw x 1195 00000002 OFST: set 2 1198 ; 362 ITStatus bitstatus = RESET; 1200 ; 364 uint8_t itstatus = 0x0, itenable = 0x0; 1204 ; 367 assert_param(IS_TIM4_IT_OK(TIM4_IT)); 1206 ; 369 itstatus = (uint8_t)(TIM4->SR1 & (uint8_t)TIM4_IT); 1208 0002 c45342 and a,21314 1209 0005 6b01 ld (OFST-1,sp),a 1211 ; 371 itenable = (uint8_t)(TIM4->IER & (uint8_t)TIM4_IT); 1213 0007 c65341 ld a,21313 1214 000a 1403 and a,(OFST+1,sp) 1215 000c 6b02 ld (OFST+0,sp),a 1217 ; 373 if ((itstatus != (uint8_t)RESET ) && (itenable != (uint8_t)RESET )) 1219 000e 0d01 tnz (OFST-1,sp) 1220 0010 270a jreq L145 1222 0012 0d02 tnz (OFST+0,sp) 1223 0014 2706 jreq L145 1224 ; 375 bitstatus = (ITStatus)SET; 1226 0016 a601 ld a,#1 1227 0018 6b02 ld (OFST+0,sp),a 1230 001a 2002 jra L345 1231 001c L145: 1232 ; 379 bitstatus = (ITStatus)RESET; 1234 001c 0f02 clr (OFST+0,sp) 1236 001e L345: 1237 ; 381 return ((ITStatus)bitstatus); 1239 001e 7b02 ld a,(OFST+0,sp) 1242 0020 5b03 addw sp,#3 1243 0022 81 ret 1279 ; 391 void TIM4_ClearITPendingBit(TIM4_IT_TypeDef TIM4_IT) 1279 ; 392 { 1280 .text: section .text,new 1281 0000 _TIM4_ClearITPendingBit: 1285 ; 394 assert_param(IS_TIM4_IT_OK(TIM4_IT)); 1287 ; 397 TIM4->SR1 = (uint8_t)(~TIM4_IT); 1289 0000 43 cpl a 1290 0001 c75342 ld 21314,a 1291 ; 398 } 1294 0004 81 ret 1307 xdef _TIM4_ClearITPendingBit 1308 xdef _TIM4_GetITStatus 1309 xdef _TIM4_ClearFlag 1310 xdef _TIM4_GetFlagStatus 1311 xdef _TIM4_GetPrescaler 1312 xdef _TIM4_GetCounter 1313 xdef _TIM4_SetAutoreload 1314 xdef _TIM4_SetCounter 1315 xdef _TIM4_GenerateEvent 1316 xdef _TIM4_ARRPreloadConfig 1317 xdef _TIM4_PrescalerConfig 1318 xdef _TIM4_SelectOnePulseMode 1319 xdef _TIM4_UpdateRequestConfig 1320 xdef _TIM4_UpdateDisableConfig 1321 xdef _TIM4_ITConfig 1322 xdef _TIM4_Cmd 1323 xdef _TIM4_TimeBaseInit 1324 xdef _TIM4_DeInit 1343 end