Example description
This example for the RH850/F1H dual core shows how the two cores can be synchronized during initializing and thereafter execute different code paths.
Only core 0 is doing the complete hardware initialization. The other core (core 1) only initializes its own GP, TP and SP registers and then waits for core 0 to complete its initialization. The synchronization is handled by using the PFSSG0MEV0 register as a semaphore together with the SNOOZE instruction.
SNOOZE temporarily halts operation of the CPU for the period defined by the hardware specifications or when the CPU enters a specific state. When the specified period has elapsed or the CPU exits the specified state, CPU operation automatically resumes and instruction execution begins from the next instruction. The SNOOZE state is released either under the conditions that the predefined period of time passes or that a terminating exception occurs.
By starting the application and view the Live Watch window, you will see the two variables count1 and count2 that are incremented by one CPU core each.