/******************************************************************************* * DISCLAIMER * This software is supplied by Renesas Electronics Corporation and is only * intended for use with Renesas products. No other uses are authorized. This * software is owned by Renesas Electronics Corporation and is protected under * all applicable laws, including copyright laws. * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. * Renesas reserves the right, without notice, to make changes to this software * and to discontinue the availability of this software. By using this software, * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer * (c) 2014 Renesas Electronics Corporation All rights reserved. *******************************************************************************/ /****************************************************************************** * File Name : r_taud_tpwmd.c * Version : 1.0 * Device(s) : R7F701007 RH850/F1L * Tool-Chain : IAR Embedded Workbench 1.30.1 * Description : This file is a sample of the Triangle wave PWM output function with the dead time (TAUD). * Operation : - ******************************************************************************* ******************************************************************************* * History : DD.MM.YYYY Version Description * : 20.03.2014 1.00 First Release ******************************************************************************/ /****************************************************************************** Includes ******************************************************************************/ #include "r_typedefs.h" #include "iodefine.h" #ifdef __ghs__ #include "device.h" #endif #ifdef __IAR_SYSTEMS_ICC__ #include #endif /****************************************************************************** Imported global variables and functions (from other files) ******************************************************************************/ /****************************************************************************** Macro definitions ******************************************************************************/ /****************************************************************************** Exported global variables and functions (to be accessed by other files) ******************************************************************************/ void R_TAUD_Init( void ); void R_TAUD_Start( void ); /****************************************************************************** Private global variables and functions ******************************************************************************/ /****************************************************************************** * Function Name : void R_TAUD_Init( void ) * Description : This function initializes the TAUD ch.6,8,9. (Triangle wave PWM output function with the dead time) * Argument : none * Return Value : none ******************************************************************************/ void R_TAUD_Init( void ) { /* TAUD0.6 port settings (PWM master) */ /* P0_2 (TAUD0O6) - CN2B-36pin */ PFCAE0 &= 0xFFFBU; PFCE0 &= 0xFFFBU; PFC0 &= 0xFFFBU; PM0 &= 0xFFFBU; PMC0 |= 0x0004U; /* TAUD0.8 port settings (PWM slave) */ /* P0_3 (TAUD0O8) - CN2B-35pin */ PFCAE0 &= 0xFFF7U; PFCE0 &= 0xFFF7U; PFC0 &= 0xFFF7U; PM0 &= 0xFFF7U; PMC0 |= 0x0008U; /* TAUD0.9 port settings (PWM slave) */ /* P10_4 (TAUD0O9) - CN2A-21pin */ PFCAE10 &= 0xFFEFU; PFCE10 &= 0xFFEFU; PFC10 &= 0xFFEFU; PM10 &= 0xFFEFU; PMC10 |= 0x0010U; /* Set interrupt flags */ MKTAUD0I6 = 1U; RFTAUD0I6 = 0U; TBTAUD0I6 = 0U; MKTAUD0I8 = 1U; RFTAUD0I8 = 0U; TBTAUD0I8 = 0U; MKTAUD0I9 = 1U; RFTAUD0I9 = 0U; TBTAUD0I9 = 0U; /* Specifies the CK3 , CK2 , CK1 and CK0 clock TAUDnTPS - TAUDn Prescaler Clock Select Register b15:b12 TAUDnPRS3 - Specifies CK3_PRE clock - PCLK / 1 b11:b 8 TAUDnPRS2 - Specifies CK2_PRE clock - PCLK / 1 b 7:b 4 TAUDnPRS1 - Specifies CK1_PRE clock - PCLK / 1 b 3:b 0 TAUDnPRS0 - Specifies CK0_PRE clock - PCLK / 16 */ TAUD0.TPS = 0x0004U; /* PCLK(80MHz) / 16 */ /* Data register for the capture/compare value TAUDnCDRm - TAUDn Channel Data Register b15:b 0 TAUDnCDR - Data register for capture/compare values - 1ms(master) , 600us(slave2) , 1msus(slave3) */ TAUD0.CDR6 = 5000U - 1U; /* ch.6 1ms. */ TAUD0.CDR8 = 3000U; /* ch.8 600us */ TAUD0.CDR9 = 1000U - 1U; /* ch.9 1ms */ /* Controls master channel operation TAUDnCMORm - TAUDn Channel Mode OS Register b15:b14 TAUDnCKS - Selects an operation clock. - Selected Operation CK0 b13:b12 TAUDnCCS0 - Selects a count clock for TAUDnCNTm counter. - Uses an operation clock as a count clock. Set to 00'b b11 TAUDnMAS - Specifies whether the channel is a master channe or slave channel during synchronous channel operation. - Master channel. Set to 1'b b10:b 8 TAUDnSTS - Selects an external start trigger. - Triggers the counter by software. Set to 000'b b 7:b 6 TAUDnCOS - Specifies the timing for updating capture register TAUDnCDRm and overflow flag TAUDnCSRm.TAUDnOVF of channel m. - Unused. Set to 00'b. b 5 - Reserved set to 0 b 4:b 1 TAUDnMD - Specifies an operating mode. - Interval timer mode. Set to 0000'b b 0 TAUDnMD0 - Specifies whether INTTAUDnIm is generated at the beginning of count operation (when a start trigger is entered) or not. - INTTAUDnIm generated at the beginning of operation. Set to 1'b*/ TAUD0.CMOR6 = 0x0801U; /* Controls slave channel operation TAUDnCMORm - TAUDn Channel Mode OS Register b15:b14 TAUDnCKS - Selects an operation clock. - Selected Operation CK0 b13:b12 TAUDnCCS0 - Selects a count clock for TAUDnCNTm counter. - Uses an operation clock as a count clock. Set to 00'b b11 TAUDnMAS - Specifies whether the channel is a master channe or slave channel during synchronous channel operation. - Slave channel. Set to 0'b b10:b 8 TAUDnSTS - Selects an external start trigger. - Up/down output trigger signal of master channel. Set to 111'b b 7:b 6 TAUDnCOS - Specifies the timing for updating capture register TAUDnCDRm and overflow flag TAUDnCSRm.TAUDnOVF of channel m. - Unused. Set to 00'b. b 5 - Reserved set to 0 b 4:b 1 TAUDnMD - Specifies an operating mode. - Count-up/-down mode. Set to 1001'b b 0 TAUDnMD0 - Specifies whether INTTAUDnIm is generated at the beginning of count operation (when a start trigger is entered) or not. - INTTAUDnIm not generated at the beginning of operation. Set to 0'b */ TAUD0.CMOR8 = 0x0712U; /* Controls slave channel operation TAUDnCMORm - TAUDn Channel Mode OS Register b15:b14 TAUDnCKS - Selects an operation clock. - Selected Operation CK0 b13:b12 TAUDnCCS0 - Selects a count clock for TAUDnCNTm counter. - Uses an operation clock as a count clock. Set to 00'b b11 TAUDnMAS - Specifies whether the channel is a master channe or slave channel during synchronous channel operation. - Slave channel. Set to 0'b b10:b 8 TAUDnSTS - Selects an external start trigger. - The up/down output trigger signal TAUDnTUDSm of the master channel is the start trigger. Set to 110'b b 7:b 6 TAUDnCOS - Specifies the timing for updating capture register TAUDnCDRm and overflow flag TAUDnCSRm.TAUDnOVF of channel m. - Unused. Set to 00'b. b 5 - Reserved set to 0 b 4:b 1 TAUDnMD - Specifies an operating mode. - One-count mode. Set to 0100'b b 0 TAUDnMD0 - Specifies whether INTTAUDnIm is generated at the beginning of count operation (when a start trigger is entered) or not. - Enables start trigger detection while counting. Set to 1'b */ TAUD0.CMOR9 = 0x0609U; /* Specifies the type of valid edge detection used for the TAUDTTINm input. TAUDnCMURm - TAUDn Channel Mode User Register b 7:b 2 - Reserved set to 0 b 1:b 0 TAUDnTIS - Specifies a valid edge of TAUDTTINm input signal. - Unused. Set to 00'b. */ TAUD0.CMUR6 = 0x00U; TAUD0.CMUR8 = 0x00U; TAUD0.CMUR9 = 0x00U; /* Specifies the output mode of each channel. TAUDnTOM - TAUDn Channel Output Mode Register b15:b 0 TAUDnTOMm - Specifies an output mode. - Independent channel output Set to 0. (master channel) - Synchronous channel operation Set to 1. (slave channel) */ TAUD0.TOM &= 0xFCBFU; TAUD0.TOM |= 0x0300U; /* Specifies the output mode of each channel in combination with TAUDnTOMm. TAUDnTOC - TAUDn Channel Output Configuration Register b15:b 0 TAUDnTOCm - Specifies an output mode. - Operating mode 1 Set to 0. (master channel) - Operating mode 2 Set to 1. (slave channel) */ TAUD0.TOC &= 0xFCBFU; TAUD0.TOC |= 0x0300U; /* Specifies the output mode of each channel in combination with TAUDnTOMm. TAUDnTOL - TAUDn Channel Output Level Register b15:b 0 TAUDnTOLm - Specifies the output logic of channel m output bit (TAUDnTO.TAUDnTOm). - The setting is disabled in toggle mode Set to 0. (master channel) - Positive logic (active high). Set to 0. (slave channel) */ TAUD0.TOL &= 0xFCBFU; /* Enable deadtime operation TAUDnTDE - TAUDn Channel Dead Time Output Enable Register b15:b 0 TAUDnTDEm - Enables/disables the dead time control operation of channel m. - Disables dead time operation Set to 0. (master channel) - Enables dead time operation Set to 1. (slave channel) */ TAUD0.TDE &= 0xFCBFU; TAUD0.TDE |= 0x0300U; /* Enable deadtime operation TAUDnTDM - TAUDn Channel Dead Time Output Mode Register b15:b 0 TAUDnTDMm - Specifies the timing to add dead time during dead time output. - When dead time operation is disabled Set to 0. (master channel) - Adds dead time if an interrupt is detected on an even upper channel and the conditions set by TAUDnTDL.TAUDnTDLm are satisfied. Set to 0. (slave channel) */ TAUD0.TDM &= 0xFCBFU; /* Selects a phase in which dead time is added. TAUDnTDL - TAUDn Channel Dead Time Output Level Register b15:b 0 TAUDnTDLm - Selects a phase in which dead time is added. - When dead time operation is disabled Set to 0. (master channel) - Adds dead time to normal phase Set to 0. (slave2 channel) - Adds dead time to reverse phase. Set to 1. (slave3 channel) */ TAUD0.TDL &= 0xFCBFU; TAUD0.TDL |= 0x0200U; /* The simultaneous rewrite registers (TAUDnTRE, TAUDnTRO, TAUDnTRC, and TAUDnTME). Both the master and slave channels should have the same simultaneous rewrite settings. Unused with the sample programs. Therefore, these registers set to 0. */ TAUD0.TRE &= 0xFCBFU; TAUD0.TRC &= 0xFCBFU; TAUD0.TRO &= 0xFCBFU; TAUD0.TME &= 0xFCBFU; /* Enable the channel output TAUDnTOE - TAUDn Channel Output Enable Register b15:b 0 TAUDnTOEm - Enables/disables the independent channel output function. - Enables the independent timer output function. Set to 1. */ TAUD0.TOE &= 0xFCBFU; TAUD0.TOE |= 0x0340U; /* Enables simultaneous rewrite of TAUDnCDRm/TAUDnTOLm data register. TAUDnRDE - TAUDn Channel Reload Data Enable Register b15:b 0 TAUDnRDEm - Enables/disables simultaneous rewrite of the data register of channel m. - Enables simultaneous rewrite. Set to 1. */ TAUD0.RDE &= 0xFCBFU; TAUD0.RDE |= 0x0340U; /* Selects a channel that controls simultaneous rewrite. TAUDnRDS - TAUDn Channel Reload Data Control Channel Select Register b15:b 0 TAUDnRDSm - Selects a channel that controls a simultaneous rewrite trigger. - Selects master channel for simultaneous rewrite triggers. Set to 0. */ TAUD0.RDS &= 0xFCBFU; /* Selects the timing for generating a simultaneous rewrite control signal. TAUDnRDM - TAUDn Channel Reload Data Mode Register b15:b 0 TAUDnRDMm - Selects the timing for generating a simultaneous rewrite trigger signal. - A simultaneous rewrite trigger signal is generated when master channel starts to count and the corresponding slave channel is at the peak of a triangular wave cycle. Set to 1. */ TAUD0.RDM &= 0xFCBFU; TAUD0.RDM |= 0x0340U; /* Channel which generates an INTTAUDnlm signal to trigger simultaneous rewrite. TAUDnRDC - TAUDn Channel Reload Data Control Register b15:b 0 TAUDnRDCm - Specifies whether the channel generates a simultaneous rewrite trigger signal or not. - Does not operate as a simultaneous rewrite trigger generation channel. Set to 0. */ TAUD0.RDC &= 0xFCBFU; MKTAUD0I6 = 0U; /* Enable INTTAUD0I6 interrupt */ MKTAUD0I8 = 0U; /* Enable INTTAUD0I8 interrupt */ MKTAUD0I9 = 0U; /* Enable INTTAUD0I9 interrupt */ } /****************************************************************************** * Function Name : void R_TAUD_Start( void ) * Description : This function start the TAUD ch.6 , ch.8 and ch.9 . * Argument : none * Return Value : none ******************************************************************************/ void R_TAUD_Start( void ) { /* Enables the counter for each channel TAUDnTS - TAUDn Channel Start Trigger Register b15:b 0 TAUDnTSm - Enables the counter operation of channel m. - Enables the ch.6,8,9 counter */ TAUD0.TS = 0x0340U; }