/******************************************************************************* * DISCLAIMER * This software is supplied by Renesas Electronics Corporation and is only * intended for use with Renesas products. No other uses are authorized. This * software is owned by Renesas Electronics Corporation and is protected under * all applicable laws, including copyright laws. * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. * Renesas reserves the right, without notice, to make changes to this software * and to discontinue the availability of this software. By using this software, * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer * (c) 2014 Renesas Electronics Corporation All rights reserved. *******************************************************************************/ /****************************************************************************** * File Name : r_pwmdiag.c * Version : 1.0 * Device(s) : R7F701007 RH850/F1L * Tool-Chain : IAR Embedded Workbench 1.30.1 * Description : This file is a sample of the PWM-Diag. * Operation : - ******************************************************************************* ******************************************************************************* * History : DD.MM.YYYY Version Description * : 20.03.2014 1.00 First Release ******************************************************************************/ /****************************************************************************** Includes ******************************************************************************/ #include "r_typedefs.h" #include "iodefine.h" #ifdef __ghs__ #include "device.h" #endif #ifdef __IAR_SYSTEMS_ICC__ #include #endif /****************************************************************************** Imported global variables and functions (from other files) ******************************************************************************/ /****************************************************************************** Macro definitions ******************************************************************************/ /****************************************************************************** Exported global variables and functions (to be accessed by other files) ******************************************************************************/ void R_PWMD_Init( void ); void R_PWMD_Start( void ); void R_PWMD_Stop( void ); void R_PWMD_Update( void ); /****************************************************************************** Private global variables and functions ******************************************************************************/ /****************************************************************************** * Function Name : void R_PWMD_Init( void ) * Description : This function initialize PWM-Diag. * Argument : none * Return Value : none ******************************************************************************/ void R_PWMD_Init( void ) { /* Set interrupt flags */ MKPWGA25 = 1U; RFPWGA25 = 0U; TBPWGA25 = 0U; /* PWGA25O (P11_0:CN1C-80pin) */ PFCAE11 &= 0xFFFEU; PFCE11 &= 0xFFFEU; PFC11 |= 0x0001U; PM11 &= 0xFFFEU; PMC11 |= 0x0001U; /* Setting of the ADCA corresponding to each channel. PWSAnPVCRx_y - PWSAnPVCRx_y Register b31:b29 - Reserved set to 0 b28 PWSAnSLADy - ADCTL Select (odd-numbered channel) - Output to ADCTL0. b27 PWSAnVRDTy - This bit indicates the setting value of the ADCAnPWDVCR.MPXE bit (oddnumbered channel). - The use of MPX is prohibited. b26:b24 PWSAnVRDTy - This bit indicates the setting value of the ADCAnPWDVCR.MPXV[2:0] bits (oddnumbered channel). - Unused. Set to 000'b. b23:b22 PWSAnVRDTy - This bit indicates the setting value of the ADCAnPWDVCR.ULS[1:0] bits (oddnumbered channel). - Upper limit and lower limit are checked for ADCAnULLMTBR0. Set to 01'b. b21:b16 PWSAnVRDTy - This bit indicates the setting value of the ADCAnPWDVCR.GCTRL[5:0] bits (odd-numbered channel). - Select ANI000 b15:b13 - Reserved set to 0 b12 PWSAnSLADx - ADCTL Select (even-numbered channel) - Unused. Set to 0'b. b11 PWSAnVRDTx - This bit indicates the setting value of the ADCAnPWDVCR.MPXE bit. (evennumbered channel) - Unused. Set to 0'b. b10:b 8 PWSAnVRDTx - These bits indicate the setting value of the ADCAnPWDVCR.MPXV[2:0] bits. (even-numbered channel) - Unused. Set to 0'b. b 7:b 6 PWSAnVRDTx - These bits indicate the setting value of the ADCAnPWDVCR.ULS[1:0] bits. (even-numbered channel) - Unused. Set to 0'b. b 5:b 0 PWSAnVRDTx - These bits indicate the setting value of the ADCAnPWDVCR.GCTRL[5:0] bits. (even-numbered channel) - Unused. Set to 0'b. */ PWSA0.PVCR24_25 = 0x00400000UL; /* Setting of the clock cycle of PWMCLKm. PWBAnBRSm - PWBAnBRSm Register b15:b11 - Reserved set to 0 b10:b 0 PWBAnBRSm - Register for setting the clock cycle of PWMCLKm. - PWMCLKm = PCLK / 2 * 8 */ PWBA0.BRS0 = 0x0008U; /* PWMCLK0 = PCLK / ( 2 * 8 ) = 2.5MHz , (PCLK = 40MHz) */ /* Sets the setting condition for PWGA_TOUTn output. PWGAnCSDR - PWM Output Set Condition Register b15:b12 - Reserved set to 0 b11:b 0 PWGAnCSDR - Setting condition for PWM output. */ /* PWM period = ( 1 / PWMCLK0 ) * (4095+1) = 0.0016384s (TRGOUT0) , (PWMCLK0 = 2.5MHz) */ /* High Level = (PWGAnCRDR - PWGAnCSDR) * ( 1 / PWMCLK0 ) */ PWGA25.CSDR = 0x0FFFU / 2U; /* Sets the reset condition for PWGA_TOUTn output. PWGAnCRDR - PWM Output Set Condition Register b15:b12 - Reserved set to 0 b11:b 0 PWGAnCRDR - Reset condition for PWM output. */ PWGA25.CRDR = 0x0FFFU; /* Sets the generation condition for PWGA_TRGOUTn. PWGAnCTDR - PWGA_TRGOUTn Generation Condition Register b15:b12 - Reserved set to 0 b11:b 0 PWGAnCTDR - A/D conversion trigger generation condition for PWSAn. */ /* A/D trigger position = PWGA25CTDR * ( 1 / PWMCLK0 ) */ PWGA25.CTDR = 0x0FFFU / 2U + 0x400U; /* Select the count clock from PWBA. PWGAnCTL - PWGA Control Register b 7:b 6 - Reserved set to 0 b 0 PWGAnCKS - Count Clock Enable Input PWMCLK3 to PWMCLK0 Select - Uses PWMCLK0 as count clock */ PWGA25.CTL = 0x00U; } /****************************************************************************** * Function Name : void R_PWMD_Start( void ) * Description : This function start the PWM-diag. ch.25. * Argument : none * Return Value : none ******************************************************************************/ void R_PWMD_Start( void ) { /* Control operations of PWSA. PWSAnCTL - PWSAnCTL Register b 7:b 6 - Reserved set to 0 b 0 PWSAnENBL - Operation Permission Control - Operation is enabled. */ PWSA0.CTL = 0x01U; MKPWGA25 = 0U; /* Enable INTPWGA25 */ /* Start for PWMCLKm. PWBAnTS - PWBAnTS Register b 7:b 4 - Reserved set to 0 b 3 PWBAnTS3 - Start trigger bit for PWMCLK3 - Unused. set to 0'b b 2 PWBAnTS2 - Start trigger bit for PWMCLK2 - Unused. set to 0'b b 1 PWBAnTS1 - Start trigger bit for PWMCLK1 - Unused. set to 0'b b 0 PWBAnTS0 - Start trigger bit for PWMCLK0 - Starts the output of PWMCLK0. */ PWBA0.TS = 0x01U; while( (PWBA0.TE & 0x01U) != 0x01U ) { /* Waiting for PWBA0TE to set. */ } /* Start for respective channels simultaneously. PWBAnTS - PWBAnTS Register b31:b 0 SLPWGA - Trigger start and stop to multiple channels simultaneously. - Starts the corresponding ch.25 */ SLPWGA0 = 0x02000000UL; } /****************************************************************************** * Function Name : void R_PWMD_Stop( void ) * Description : This function stop the PWM-diag. ch.25. * Argument : none * Return Value : none ******************************************************************************/ void R_PWMD_Stop( void ) { MKPWGA25 = 1U; /* Disable INTPWGA25 */ /* Stop for respective channels simultaneously. PWBAnTS - PWBAnTS Register b31:b 0 SLPWGA - Trigger start and stop to multiple channels simultaneously. - Stops the corresponding ch.25 */ SLPWGA0 &= 0xFDFFFFFFUL; /* Falling edge of PWGA_TOUTn detected. */ while( !RFPWGA25 ) { /* Waiting for RFPWGA25 to set. */ } RFPWGA25 = 0U; /* clear INTPWGA25 interrupt request flag */ /* Stop for PWMCLKm. PWBAnTT - PWBAnTT Register b 7:b 4 - Reserved set to 0 b 3 PWBAnTT3 - Stop trigger bit for PWMCLK3 - Unused. set to 0'b b 2 PWBAnTT2 - Stop trigger bit for PWMCLK2 - Unused. set to 0'b b 1 PWBAnTT1 - Stop trigger bit for PWMCLK1 - Unused. set to 0'b b 0 PWBAnTT0 - Stop trigger bit for PWMCLK0 - Stops the output of PWMCLK0. */ PWBA0.TT = 0x01U; while( (PWBA0.TE & 0x01U) == 0x01U ) { /* Waiting for PWBA0TE to reset. */ } /* Control operations of PWSA. PWSAnCTL - PWSAnCTL Register b 7:b 6 - Reserved set to 0 b 0 PWSAnENBL - Operation Permission Control - Operation is disabled. */ PWSA0.CTL = 0x00U; } /****************************************************************************** * Function Name : void R_PWMD_Update( void ) * Description : This function update the PWM-Diag. ch.25 * Argument : none * Return Value : none ******************************************************************************/ void R_PWMD_Update( void ) { if ( (PWGA25.RSF & 0x01U) == 0x00U ) { /* Sets the setting condition for PWGA_TOUTn output. PWGAnCSDR - PWM Output Set Condition Register b15:b12 - Reserved set to 0 b11:b 0 PWGAnCSDR - Setting condition for PWM output. */ /* PWM period = ( 1 / PWMCLK0 ) * (4095+1) = 0.0016384s (TRGOUT0) , (PWMCLK0 = 2.5MHz) */ /* High Level = (PWGAnCRDR - PWGAnCSDR) * ( 1 / PWMCLK0 ) */ if ( PWGA25.CSDR == (0x0FFFU / 2U) ) { PWGA25.CSDR = 0x0FFFU / 4U; } else if ( PWGA25.CSDR == (0x0FFFU / 4U) ) { PWGA25.CSDR = 0U; } else { PWGA25.CSDR = 0x0FFFU / 2U; } /* Sets the reset condition for PWGA_TOUTn output. PWGAnCRDR - PWM Output Set Condition Register b15:b12 - Reserved set to 0 b11:b 0 PWGAnCRDR - Reset condition for PWM output. */ if ( PWGA25.CRDR == 0x0FFFU ) { PWGA25.CRDR = 0x0FFFU / 2U + 0x400U; } else if ( PWGA25.CRDR == (0x0FFFU / 2U + 0x400U) ) { PWGA25.CRDR = 0x0FFFU / 2U; } else { PWGA25.CRDR = 0x0FFFU; } /* Sets the generation condition for PWGA_TRGOUTn. PWGAnCTDR - PWGA_TRGOUTn Generation Condition Register b15:b12 - Reserved set to 0 b11:b 0 PWGAnCTDR - A/D conversion trigger generation condition for PWSAn. */ /* A/D trigger position = PWGA25CTDR * ( 1 / PWMCLK0 ) */ if ( PWGA25.CTDR == (0x0FFFU / 2U + 0x400U) ) { PWGA25.CTDR = 0x0FFFU / 4U + 0x400U; } else if ( PWGA25.CTDR == (0x0FFFU / 4U + 0x400U) ) { PWGA25.CTDR = 0U + 0x400U; } else { PWGA25.CTDR = 0x0FFFU / 2U + 0x400U; } /* Stop for PWMCLKm. PWGAnRDT - Buffer Register Reload Trigger Register b7:b1 - Reserved set to 0 b0 PWGAnRDT - Simultaneous Rewrite Request Trigger - Triggers the simultaneous rewrite request for the compare registers. */ PWGA25.RDT = 0x01U; } else { #if !defined(__IAR_SYSTEMS_ICC__) __nop(); #endif #ifdef __IAR_SYSTEMS_ICC__ __asm( "nop"); #endif } }