| Peripheral function | Macro | SubMacro | Setting | Status |
|---|---|---|---|---|
| Common/Clock Controller | Used | |||
| CGC | Used | |||
| Main Oscillator (MainOSC) setting | OSC mode | |||
| Main Oscillator (MainOSC) setting - Frequency | 16(MHz) | |||
| Main Oscillator (MainOSC) setting - Oscillation stabilization time | 2.2(ms)(Actual value: 2.2) | |||
| Main Oscillator (MainOSC) setting - Stop request in Stand-by Mode | Stop operation | |||
| Sub Oscillator (SubOSC) setting | Operation | |||
| Sub Oscillator (SubOSC) setting - Frequency | 32.768(kHz) | |||
| Sub Oscillator (SubOSC) setting - Oscillation stabilization time | 2.2(s)(Actual value: 2.2) | |||
| High Speed Internal Oscillator (HS IntOSC) setting | Operation | |||
| High Speed Internal Oscillator (HS IntOSC) setting - Frequency | 8(MHz) | |||
| High Speed Internal Oscillator (HS IntOSC) setting - Stop request in Stand-by Mode | Stop operation | |||
| Low Speed Internal Oscillator (LS IntOSC) setting - Frequency | 240(kHz) | |||
| PLL setting | Operation | |||
| PLL setting - Source clock | MainOSC | |||
| PPLLOUT frequency | 80.0(MHz) | |||
| CPLLOUT frequency | 120.0(MHz) | |||
| PPLLCLK setting - Source clock | PPLLOUT(Actual value: 80MHz) | |||
| Frequency output setting | Unused | |||
| WDTA0 clock setting - Clock source | LS IntOSC(Actual value: 240kHz) | |||
| WDTA0 clock setting - Stop request in Stand-by Mode | Stop operation | |||
| TAUJ0 clock setting - Clock source | MainOSC | |||
| TAUJ0 clock setting - Divide clock | MainOSC(Actual value: 16MHz) | |||
| TAUJ0 clock setting - Stop request in Stand-by Mode | Stop operation | |||
| ADCA0 clock setting - Clock source | PPLLCLK2 | |||
| ADCA0 clock setting - Divide clock | PPLLCLK2 / 2(Actual value: 20MHz) | |||
| ADCA0 clock setting - Stop request in Stand-by Mode | Stop operation | |||
| RTCA clock setting - Clock source | SubOSC | |||
| RTCA clock setting - Divide clock | SubOSC(Actual value: 0.03277MHz) | |||
| RTCA clock setting - Stop request in Stand-by Mode | Stop operation | |||
| CPU clock setting - Clock source | EMCLK | |||
| CPU clock setting - Divide clock | EMCLK(Actual value: 8MHz) | |||
| RLIN clock setting - Clock source | MainOSC | |||
| RLIN clock setting - Divide clock | MainOSC(Actual value: 16MHz) | |||
| RLIN clock setting - Stop request in Stand-by Mode | Stop operation | |||
| PERI1 clock source | PPLLCLK(Actual value: 80MHz) | |||
| PERI2 clock source | PPLLCLK2(Actual value: 40MHz) | |||
| ADCA1 clock setting - Clock source | Disabled | |||
| RS-CANn(pclk) clock source | PPLLCLK(Actual value: 80MHz) | |||
| RS-CANn(pclk)Stop request in Stand-by Mode | Stop operation | |||
| RS-CANn(clk_xincan) clock source | Disabled(Actual value: xxxMHz) | |||
| RS-CANn(clk_xincan)Stop request in Stand-by Mode | Stop operation | |||
| CSI clock setting - Clock source | PPLLCLK(Actual value: 80MHz) | |||
| IIC clock setting - Clock source | PPLLCLK2(Actual value: 40MHz) | |||
| Operating mode setting | Normal operating mode | |||
| Debug interface setting | Unused | |||
| Exception handler setting | Table referencing method | |||
| Port Function | Used | |||
| Port0 | Used | |||
| P00 | Used | |||
| Mode | Out | |||
| Drive strength selection | Lower drive strength | |||
| Output 1 | Used | |||
| P03 | Used | |||
| Port8 | Used | |||
| P85 | Used | |||
| Mode | Out | |||
| Port10 | Used | |||
| P101 | Used | |||
| P103 | Used | |||
| Mode | Out | |||
| Drive strength selection | High drive strength | |||
| Interrupt | Unused | |||
| Stand-By Controller | Unused | |||
| DMA Controller | Unused | |||
| Clocked Serial Interface G | Unused | |||
| Clocked Serial Interface H | Unused | |||
| UART Interface | Used | |||
| UART0 | Used | |||
| Transfer mode | Transmit/receive function | |||
| RLIN30RX pin | P10_9 (7th) | |||
| RLIN30TX pin | P10_10 | |||
| Data length setting | 8 bits | |||
| Transfer direction setting | LSB | |||
| Parity setting | None | |||
| Stop bit length setting (for transmit data only) | 1 bit | |||
| Receive data noise filter setting | Enable | |||
| Transmit data level setting | Normal output | |||
| Receive data level setting | Normal input | |||
| Baudrate | 1000000(bps)(Current error: +0.000%) | |||
| Transmission interrupt priority (INTLT) | Lowest | |||
| Status interrupt priority (INTLS) | Level 14 | |||
| Reception end interrupt priority (INTLR) | Lowest | |||
| Transmission end(Callback function setting) | Used | |||
| Reception error(Callback function setting) | Used | |||
| Reception end(Callback function setting) | Used | |||
| I2C Bus Interface | Unused | |||
| Window Watchdog Timer | Used | |||
| WDTA0 | Used | |||
| Watchdog timer operation setting | Used (Software trigger start mode) | |||
| Overflow interval time | 2^9/WDTATCKI,2.13(ms) | |||
| Error mode | NMI request mode | |||
| Window open period | 100(%) | |||
| Enable interval interrupt when 75% of overflow time (INTWDTA0) | Used | |||
| Priority | Lowest | |||
| WDTA1 | Used | |||
| Watchdog timer operation setting | Used (Software trigger start mode) | |||
| Overflow interval time | 2^16/WDTATCKI,273.07(ms) | |||
| Error mode | NMI request mode | |||
| Window open period | 100(%) | |||
| Enable interval interrupt when 75% of overflow time (INTWDTA1) | Used | |||
| Priority | Lowest | |||
| OS Timer | Used | |||
| OSTM0 | Used | |||
| OS timer 0 operation setting | Used | |||
| OSTM0 mode setting | Interval timer mode | |||
| Comparing value | 100ms | |||
| OSTM0 interrupt enable(INTOSTM0) | Used | |||
| Enables the interrupts when counting starts | Unused | |||
| Priority | Lowest | |||
| Timer Array Unit B | Unused | |||
| Timer Array Unit D | Unused | |||
| Timer Array Unit J | Unused | |||
| Real-Time Clock | Unused | |||
| A/D Converter | Unused | |||
| Key Interrupt Function | Unused | |||
| Data CRC | Unused |