Page 1 objs\release\startup.s Command Line: C:\ghs\comp_202114\asarm.exe -annotate_call_return -elf -b0 -IGenerated\inc\ -I..\Generated\inc -I..\Src -I..\Generated\inc\ -I..\..\..\MCAL\Platform_ZX_K14xM\Inc -I..\..\..\MCAL\Platform_ZX_K14xM\StartUp\Inc -I..\..\..\MCAL\McalLib_ZX_K14xM\Inc\Devices -I..\..\..\MCAL\McalLib_ZX_K14xM\Inc -I..\..\..\MCAL\Mcu_ZX_K14xM\Inc -I..\..\..\MCAL\Adc_ZX_K14xM\Inc -I..\..\..\MCAL\Dem_ZX_K14xM\Inc -I..\..\..\MCAL\Det_ZX_K14xM\Inc -I..\..\..\MCAL\Dio_ZX_K14xM\Inc -I..\..\..\MCAL\Base_ZX_K14xM\Inc -I..\..\..\MCAL\Wdg_ZX_K14xM\Inc -I..\..\..\MCAL\Port_ZX_K14xM\Inc -I..\..\..\MCAL\Rte_ZX_K14xM\Inc -I..\..\..\MCAL\Base_ZX_K14xM\Inc\MemMap -I..\..\..\MCAL\WdgIf_ZX_K14xM\Inc -I..\..\..\MCAL\Can_ZX_K14xM\Inc -I..\..\..\MCAL\Gpt_ZX_K14xM\Inc -I..\..\..\MCAL\Dma_ZX_K14xM\Inc -I..\..\..\MCAL\Pwm_ZX_K14xM\Inc -I..\..\..\MCAL\EcuM_ZX_K14xM\Inc -I..\..\..\MCAL\CanIf_ZX_K14xM\Inc -I..\..\..\mcal\Icu_ZX_K14xM\Inc -I..\..\..\MCAL\Ecum_ZX_K14xM\Inc -I..\..\..\MCAL\Fls_ZX_K14xM\Inc -I..\..\..\MCAL\MemIf_ZX_K14xM\Inc -I..\..\..\mcal\Spi_ZX_K14xM\Inc -I..\..\..\Package\OS\Task -I..\..\..\Package\OS\Task\cpu_port\Zhixin -I..\..\..\Package\cm_backtrace -I..\..\..\Package\Cdd -I..\..\..\Package\Cdd\CddBuck\Gen -I..\..\..\Package\Cdd\CddSbc\Api -I..\..\..\Package\Cdd\CddSbc\Cfg -I..\..\..\Package\Cdd\CddTle94x1\Cfg -I..\..\..\Package\Cdd\CddTle94x1\Api -I..\..\..\Package\Cdd\CddTle94x1\Gen -I..\..\..\Package\Cdd\CddBoost\Api -IC:\ghs\comp_202114\lib\thumb2 -cpu=cortexm4f -fpu=vfpv3_d16 -fpu=single -hardware_divide -source=startup.c -o objs\release\startup.o -list=objs\release\startup.lst objs\release\startup.s Original File: objs\release\startup.s Source File: startup.c Directory: D:\AUTOMFL\AutoSAR\ZHIXIN\MCAL_Capri(1.2.0)\Project\Capri\MultiProject Host OS: Windows EASE: Copyright (C) 1983-2021 Green Hills Software. All Rights Reserved. Release: Compiler v2021.1.4 Build Directory: [Directory] COMP-VAL-WIN1:C:/autoval2/v2021.1-2021-04-25/win64-comp Revision: [VCInfo] http://toolsvc/branches/release-branch-2021-1-comp/src@696881 (built by auto-compiler) Revision Date: Mon Apr 26 12:33:25 2021 Release Date: Mon Apr 26 08:01:05 2021 1 ;Driver Command: ccarm -c -MD -IGenerated\inc\ -I..\Generated\inc -I..\Src 2 ; -I..\Src -I..\Generated\inc\ -I..\Src 3 ; -I..\..\..\MCAL\Platform_ZX_K14xM\Inc 4 ; -I..\..\..\MCAL\Platform_ZX_K14xM\StartUp\Inc 5 ; -I..\..\..\MCAL\McalLib_ZX_K14xM\Inc\Devices 6 ; -I..\..\..\MCAL\McalLib_ZX_K14xM\Inc 7 ; -I..\..\..\MCAL\Mcu_ZX_K14xM\Inc -I..\..\..\MCAL\Adc_ZX_K14xM\Inc 8 ; -I..\..\..\MCAL\Dem_ZX_K14xM\Inc -I..\..\..\MCAL\Det_ZX_K14xM\Inc 9 ; -I..\..\..\MCAL\Dio_ZX_K14xM\Inc 10 ; -I..\..\..\MCAL\Base_ZX_K14xM\Inc 11 ; -I..\..\..\MCAL\Wdg_ZX_K14xM\Inc 12 ; -I..\..\..\MCAL\Port_ZX_K14xM\Inc 13 ; -I..\..\..\MCAL\Rte_ZX_K14xM\Inc 14 ; -I..\..\..\MCAL\Base_ZX_K14xM\Inc\MemMap 15 ; -I..\..\..\MCAL\WdgIf_ZX_K14xM\Inc 16 ; -I..\..\..\MCAL\Can_ZX_K14xM\Inc -I..\..\..\MCAL\Gpt_ZX_K14xM\Inc 17 ; -I..\..\..\MCAL\Dma_ZX_K14xM\Inc -I..\..\..\MCAL\Pwm_ZX_K14xM\Inc 18 ; -I..\..\..\MCAL\EcuM_ZX_K14xM\Inc 19 ; -I..\..\..\MCAL\Can_ZX_K14xM\Inc 20 ; -I..\..\..\MCAL\CanIf_ZX_K14xM\Inc 21 ; -I..\..\..\mcal\Icu_ZX_K14xM\Inc 22 ; -I..\..\..\MCAL\Ecum_ZX_K14xM\Inc 23 ; -I..\..\..\MCAL\Fls_ZX_K14xM\Inc 24 ; -I..\..\..\MCAL\MemIf_ZX_K14xM\Inc 25 ; -I..\..\..\mcal\Icu_ZX_K14xM\Inc -I..\..\..\mcal\Spi_ZX_K14xM\Inc 26 ; -I..\..\..\Package\OS\Task 27 ; -I..\..\..\Package\OS\Task\cpu_port\Zhixin 28 ; -I..\..\..\Package\cm_backtrace -I..\..\..\Package\Cdd 29 ; -I..\..\..\Package\Cdd\CddBuck\Gen 30 ; -I..\..\..\Package\Cdd\CddBuck\Gen 31 ; -I..\..\..\Package\Cdd\CddSbc\Api 32 ; -I..\..\..\Package\Cdd\CddSbc\Cfg 33 ; -I..\..\..\Package\Cdd\CddTle94x1\Cfg 34 ; -I..\..\..\Package\Cdd\CddTle94x1\Api 35 ; -I..\..\..\Package\Cdd\CddTle94x1\Gen 36 ; -I..\..\..\Package\Cdd\CddBoost\Api -cpu=cortexm4f -Wshadow 37 ; -Wtrigraphs -keeptempfiles -Wundef -Wimplicit-int -dual_debug 38 ; --no_commons --no_exceptions --gnu_asm 39 ; --incorrect_pragma_warnings --prototype_errors -list 40 ; --misra_2004=2.1 -ignore_debug_references 41 ; -preprocess_assembly_files -thumb_lib -thumb --hardware_divide 42 ; -c99 -no_japanese_automotive_c --std --stdl --slash_comment 43 ; -Ospeed --no_debug -object_dir=objs\release -filetype.c 44 ; ..\..\..\mcal\Platform_ZX_K14xM\StartUp\Src\Ghs\startup.c -o 45 ; objs\release\startup.o 46 ;Source File: ..\..\..\mcal\Platform_ZX_K14xM\StartUp\Src\Ghs\startup.c 47 ;Directory: 48 ; D:\AUTOMFL\AutoSAR\ZHIXIN\MCAL_Capri(1.2.0)\Project\Capri\MultiProject 49 ;Compile Date: Mon Dec 18 00:01:43 2023 50 ;Host OS: Win64 Page 2 objs\release\startup.s 51 ;Version: C-ARM 2021.1.4 RELEASE VERSION 52 ;Release: Compiler v2021.1.4 53 ;Revision Date: Mon Apr 26 12:37:23 2021 54 ;Release Date: Mon Apr 26 08:01:05 2021 55 ; ecom -w -OLM 56 .text 57 .align 2 58 ..gh.f.f.1.a.1.e.0: 59 .endo ..gh.f.f.1.a.1.e.0 60 .thumb2 61 SetVTOR:: 00000000 f2400000* 62 movw r0,%lo(__RAM_INTERRUPT_START) 00000004 f2c00000* 63 movt r0,%hi(__RAM_INTERRUPT_START) 00000008 f64e5108 64 movw r1,0xed08 0000000c f2ce0100 65 movt r1,7<<13 00000010 6008 66 str r0,[r1] 67 .L81: 68 00000012 4770 69 ret 70 .endf SetVTOR 71 72 .section ".bss","awb" 73 .L64: 74 .endo .L64 75 .section ".ghrettbl","" 76 .align 4 00000000 00000000* 77 .L82: .data.w .L81 78 .endo .L82 79 .text 80 ..gh.f.f.1.a.1.e.1: 81 .endo ..gh.f.f.1.a.1.e.1 82 SetSTACK:: 83 ..gh.beginasm.2: 84 .endo ..gh.beginasm.2 00000014 f3808808 85 MSR MSP,r0 86 87 ..gh.endasm.3: 88 .endo ..gh.endasm.3 89 90 .L145: 91 00000018 4770 92 ret 93 .endf SetSTACK 94 95 .section ".bss","awb" 96 .L128: 97 .endo .L128 98 .section ".ghrettbl","" 00000004 00000000* 99 .L146: .data.w .L145 100 .endo .L146 101 .text 102 ..gh.f.f.1.a.1.e.4: 103 .endo ..gh.f.f.1.a.1.e.4 104 EnableFPU:: 0000001a f64e5188 105 movw r1,0xed88 0000001e f2ce0100 106 movt r1,7<<13 00000022 6808 107 ldr r0,[r1] 00000024 f4400070 108 orr r0,r0,15<<20 00000028 6008 109 str r0,[r1] 110 .L212: 111 Page 3 objs\release\startup.s 0000002a 4770 112 ret 113 .endf EnableFPU 114 ;value r0 local 115 116 .section ".bss","awb" 117 .L195: 118 .endo .L195 119 .section ".ghrettbl","" 00000008 00000000* 120 .L213: .data.w .L212 121 .endo .L213 122 .text 123 ..gh.f.f.1.a.1.e.5: 124 .endo ..gh.f.f.1.a.1.e.5 125 FillStack:: 0000002c f2400100* 126 movw r1,%lo(__STACK_END) 00000030 f2c00100* 127 movt r1,%hi(__STACK_END) 00000034 f2400000* 128 movw r0,%lo(__STACK_TOP) 00000038 f2c00000* 129 movt r0,%hi(__STACK_TOP) 0000003c 4281 130 cmp r1,r0 0000003e bf08 131 it eq 132 .L457: 133 00000040 4770 134 ret 00000042 f64b62ef 135 movw r2,0xbeef 00000046 f6cd62ad 136 movt r2,0xdead 137 .L216: 0000004a f8412b04 138 str r2,[r1],4 0000004e 4281 139 cmp r1,r0 00000050 d1fb* 140 bne .L216 141 .L459: 142 00000052 4770 143 ret 144 .endf FillStack 145 ;sp r1 local 146 147 .section ".bss","awb" 148 .L413: 149 .endo .L413 150 .section ".ghrettbl","" 0000000c 00000000* 151 .L458: .data.w .L457 152 .endo .L458 00000010 00000000* 153 .L460: .data.w .L459 154 .endo .L460 155 .text 156 ..gh.f.f.1.a.1.e.6: 157 .endo ..gh.f.f.1.a.1.e.6 158 FillSRAM:: 00000054 f2400000* 159 movw r0,%lo(__SRAM_INIT_FLAG) 00000058 f2c00000* 160 movt r0,%hi(__SRAM_INIT_FLAG) 0000005c 2801 161 cmp r0,1 0000005e bf18 162 it ne 163 .L751: 164 00000060 4770 165 ret 00000062 f2400100* 166 movw r1,%lo(__SRAM_START) 00000066 f2c00100* 167 movt r1,%hi(__SRAM_START) 0000006a f2400000* 168 movw r0,%lo(__SRAM_END) 0000006e f2c00000* 169 movt r0,%hi(__SRAM_END) 00000072 4281 170 cmp r1,r0 00000074 bf18 171 it ne 00000076 2200 172 mov r2,0 Page 4 objs\release\startup.s 173 .L465: 00000078 bf1c 174 itt ne 0000007a f8412b04 175 str r2,[r1],4 0000007e 4281 176 cmp r1,r0 00000080 d1fa* 177 bne .L465 178 .L461: 179 .L753: 180 00000082 4770 181 ret 182 .endf FillSRAM 183 ;pMem r1 local 184 185 .section ".bss","awb" 186 .L701: 187 .endo .L701 188 .section ".ghrettbl","" 00000014 00000000* 189 .L752: .data.w .L751 190 .endo .L752 00000018 00000000* 191 .L754: .data.w .L753 192 .endo .L754 193 .text 194 ..gh.f.f.1.a.1.e.7: 195 .endo ..gh.f.f.1.a.1.e.7 196 CopyRomToRam:: 00000084 f2400200* 197 movw r2,%lo(__RAM_RAM_CODE_INIT_START) 00000088 f2c00200* 198 movt r2,%hi(__RAM_RAM_CODE_INIT_START) 0000008c f2400100* 199 movw r1,%lo(__ROM_RAM_CODE_INIT_START) 00000090 f2c00100* 200 movt r1,%hi(__ROM_RAM_CODE_INIT_START) 00000094 f2400000* 201 movw r0,%lo(__ROM_RAM_CODE_INIT_END) 00000098 f2c00000* 202 movt r0,%hi(__ROM_RAM_CODE_INIT_END) 0000009c 4281 203 cmp r1,r0 0000009e d02f* 204 beq .L848 000000a0 1a43 205 subs r3,r0,r1 000000a2 1e5b 206 subs r3,r3,1 000000a4 089b 207 lsrs r3,r3,2 000000a6 1c5b 208 adds r3,r3,1 000000a8 08db 209 lsrs r3,r3,3 000000aa d023* 210 beq .L846 211 .L843: 000000ac f851cb20 212 ldr.w r12,[r1],32 000000b0 f842cb20 213 str r12,[r2],32 000000b4 f851cc1c 214 ldr.w r12,[r1,-28] 000000b8 f842cc1c 215 str r12,[r2,-28] 000000bc f851cc18 216 ldr.w r12,[r1,-24] 000000c0 f842cc18 217 str r12,[r2,-24] 000000c4 f851cc14 218 ldr.w r12,[r1,-20] 000000c8 f842cc14 219 str r12,[r2,-20] 000000cc f851cc10 220 ldr.w r12,[r1,-16] 000000d0 f842cc10 221 str r12,[r2,-16] 000000d4 f851cc0c 222 ldr.w r12,[r1,-12] 000000d8 f842cc0c 223 str r12,[r2,-12] 000000dc f851cc08 224 ldr.w r12,[r1,-8] 000000e0 f842cc08 225 str r12,[r2,-8] 000000e4 f851cc04 226 ldr.w r12,[r1,-4] 000000e8 1e5b 227 subs r3,r3,1 000000ea f842cc04 228 str r12,[r2,-4] 000000ee d1dd* 229 bne .L843 000000f0 4281 230 cmp r1,r0 000000f2 d005* 231 beq .L848 232 .L846: 000000f4 f8513b04 233 ldr.w r3,[r1],4 Page 5 objs\release\startup.s 000000f8 4281 234 cmp r1,r0 000000fa f8423b04 235 str r3,[r2],4 000000fe d1f9* 236 bne .L846 237 .L848: 00000100 f2400200* 238 movw r2,%lo(__RAM_DATA_INIT_START) 00000104 f2c00200* 239 movt r2,%hi(__RAM_DATA_INIT_START) 00000108 f2400100* 240 movw r1,%lo(__ROM_DATA_INIT_START) 0000010c f2c00100* 241 movt r1,%hi(__ROM_DATA_INIT_START) 00000110 f2400000* 242 movw r0,%lo(__ROM_DATA_INIT_END) 00000114 f2c00000* 243 movt r0,%hi(__ROM_DATA_INIT_END) 00000118 4281 244 cmp r1,r0 0000011a d02f* 245 beq .L856 0000011c 1a43 246 subs r3,r0,r1 0000011e 1e5b 247 subs r3,r3,1 00000120 089b 248 lsrs r3,r3,2 00000122 1c5b 249 adds r3,r3,1 00000124 08db 250 lsrs r3,r3,3 00000126 d023* 251 beq .L854 252 .L851: 00000128 f851cb20 253 ldr.w r12,[r1],32 0000012c f842cb20 254 str r12,[r2],32 00000130 f851cc1c 255 ldr.w r12,[r1,-28] 00000134 f842cc1c 256 str r12,[r2,-28] 00000138 f851cc18 257 ldr.w r12,[r1,-24] 0000013c f842cc18 258 str r12,[r2,-24] 00000140 f851cc14 259 ldr.w r12,[r1,-20] 00000144 f842cc14 260 str r12,[r2,-20] 00000148 f851cc10 261 ldr.w r12,[r1,-16] 0000014c f842cc10 262 str r12,[r2,-16] 00000150 f851cc0c 263 ldr.w r12,[r1,-12] 00000154 f842cc0c 264 str r12,[r2,-12] 00000158 f851cc08 265 ldr.w r12,[r1,-8] 0000015c f842cc08 266 str r12,[r2,-8] 00000160 f851cc04 267 ldr.w r12,[r1,-4] 00000164 1e5b 268 subs r3,r3,1 00000166 f842cc04 269 str r12,[r2,-4] 0000016a d1dd* 270 bne .L851 0000016c 4281 271 cmp r1,r0 0000016e d005* 272 beq .L856 273 .L854: 00000170 f8513b04 274 ldr.w r3,[r1],4 00000174 4281 275 cmp r1,r0 00000176 f8423b04 276 str r3,[r2],4 0000017a d1f9* 277 bne .L854 278 .L856: 0000017c f2400200* 279 movw r2,%lo(__RAM_MCAL_DATA_INIT_START) 00000180 f2c00200* 280 movt r2,%hi(__RAM_MCAL_DATA_INIT_START) 00000184 f2400100* 281 movw r1,%lo(__ROM_MCAL_DATA_INIT_START) 00000188 f2c00100* 282 movt r1,%hi(__ROM_MCAL_DATA_INIT_START) 0000018c f2400000* 283 movw r0,%lo(__ROM_MCAL_DATA_INIT_END) 00000190 f2c00000* 284 movt r0,%hi(__ROM_MCAL_DATA_INIT_END) 00000194 4281 285 cmp r1,r0 00000196 d02f* 286 beq .L864 00000198 1a43 287 subs r3,r0,r1 0000019a 1e5b 288 subs r3,r3,1 0000019c 089b 289 lsrs r3,r3,2 0000019e 1c5b 290 adds r3,r3,1 000001a0 08db 291 lsrs r3,r3,3 000001a2 d023* 292 beq .L862 293 .L859: 000001a4 f851cb20 294 ldr.w r12,[r1],32 Page 6 objs\release\startup.s 000001a8 f842cb20 295 str r12,[r2],32 000001ac f851cc1c 296 ldr.w r12,[r1,-28] 000001b0 f842cc1c 297 str r12,[r2,-28] 000001b4 f851cc18 298 ldr.w r12,[r1,-24] 000001b8 f842cc18 299 str r12,[r2,-24] 000001bc f851cc14 300 ldr.w r12,[r1,-20] 000001c0 f842cc14 301 str r12,[r2,-20] 000001c4 f851cc10 302 ldr.w r12,[r1,-16] 000001c8 f842cc10 303 str r12,[r2,-16] 000001cc f851cc0c 304 ldr.w r12,[r1,-12] 000001d0 f842cc0c 305 str r12,[r2,-12] 000001d4 f851cc08 306 ldr.w r12,[r1,-8] 000001d8 f842cc08 307 str r12,[r2,-8] 000001dc f851cc04 308 ldr.w r12,[r1,-4] 000001e0 1e5b 309 subs r3,r3,1 000001e2 f842cc04 310 str r12,[r2,-4] 000001e6 d1dd* 311 bne .L859 000001e8 4281 312 cmp r1,r0 000001ea d005* 313 beq .L864 314 .L862: 000001ec f8513b04 315 ldr.w r3,[r1],4 000001f0 4281 316 cmp r1,r0 000001f2 f8423b04 317 str r3,[r2],4 000001f6 d1f9* 318 bne .L862 319 .L864: 000001f8 f2400200* 320 movw r2,%lo(__RAM_INTERRUPT_START) 000001fc f2c00200* 321 movt r2,%hi(__RAM_INTERRUPT_START) 00000200 f2400100* 322 movw r1,%lo(__ROM_INTERRUPT_START) 00000204 f2c00100* 323 movt r1,%hi(__ROM_INTERRUPT_START) 00000208 f2400000* 324 movw r0,%lo(__ROM_INTERRUPT_END) 0000020c f2c00000* 325 movt r0,%hi(__ROM_INTERRUPT_END) 00000210 4281 326 cmp r1,r0 00000212 bf08 327 it eq 328 .L1689: 329 00000214 4770 330 ret 00000216 1a43 331 subs r3,r0,r1 00000218 1e5b 332 subs r3,r3,1 0000021a 089b 333 lsrs r3,r3,2 0000021c 1c5b 334 adds r3,r3,1 0000021e 08db 335 lsrs r3,r3,3 00000220 d024* 336 beq .L870 337 .L867: 00000222 f851cb20 338 ldr.w r12,[r1],32 00000226 f842cb20 339 str r12,[r2],32 0000022a f851cc1c 340 ldr.w r12,[r1,-28] 0000022e f842cc1c 341 str r12,[r2,-28] 00000232 f851cc18 342 ldr.w r12,[r1,-24] 00000236 f842cc18 343 str r12,[r2,-24] 0000023a f851cc14 344 ldr.w r12,[r1,-20] 0000023e f842cc14 345 str r12,[r2,-20] 00000242 f851cc10 346 ldr.w r12,[r1,-16] 00000246 f842cc10 347 str r12,[r2,-16] 0000024a f851cc0c 348 ldr.w r12,[r1,-12] 0000024e f842cc0c 349 str r12,[r2,-12] 00000252 f851cc08 350 ldr.w r12,[r1,-8] 00000256 f842cc08 351 str r12,[r2,-8] 0000025a f851cc04 352 ldr.w r12,[r1,-4] 0000025e 1e5b 353 subs r3,r3,1 00000260 f842cc04 354 str r12,[r2,-4] 00000264 d1dd* 355 bne .L867 Page 7 objs\release\startup.s 00000266 4281 356 cmp r1,r0 00000268 bf08 357 it eq 358 .L1691: 359 0000026a 4770 360 ret 361 .L870: 0000026c f8513b04 362 ldr.w r3,[r1],4 00000270 4281 363 cmp r1,r0 00000272 f8423b04 364 str r3,[r2],4 00000276 d1f9* 365 bne .L870 366 .L1693: 367 00000278 4770 368 ret 369 .endf CopyRomToRam 370 ;dst r2 local 371 ;src r1 local 372 373 .section ".bss","awb" 374 .L1431: 375 .endo .L1431 376 .section ".ghrettbl","" 0000001c 00000000* 377 .L1690: .data.w .L1689 378 .endo .L1690 00000020 00000000* 379 .L1692: .data.w .L1691 380 .endo .L1692 00000024 00000000* 381 .L1694: .data.w .L1693 382 .endo .L1694 383 .text 384 ..gh.f.f.1.a.1.e.8: 385 .endo ..gh.f.f.1.a.1.e.8 386 InitBSS:: 0000027a f2400100* 387 movw r1,%lo(__BSS_SRAM_START) 0000027e f2c00100* 388 movt r1,%hi(__BSS_SRAM_START) 00000282 f2400000* 389 movw r0,%lo(__BSS_SRAM_END) 00000286 f2c00000* 390 movt r0,%hi(__BSS_SRAM_END) 0000028a 4281 391 cmp r1,r0 0000028c bf08 392 it eq 393 .L2094: 394 0000028e 4770 395 ret 00000290 1e42 396 subs r2,r0,1 00000292 1a52 397 subs r2,r2,r1 00000294 0892 398 lsrs r2,r2,2 00000296 1c52 399 adds r2,r2,1 00000298 08d3 400 lsrs r3,r2,3 0000029a d00f* 401 beq .L1769 0000029c f04f0200 402 mov r2,0 403 .L1772: 000002a0 4694 404 mov r12,r2 000002a2 e8a11004 405 stm r1!,{r2,r12} 000002a6 e8a11004 406 stm r1!,{r2,r12} 000002aa e8a11004 407 stm r1!,{r2,r12} 000002ae e8a11004 408 stm r1!,{r2,r12} 000002b2 1e5b 409 subs r3,r3,1 000002b4 d1f4* 410 bne .L1772 000002b6 4281 411 cmp r1,r0 000002b8 bf08 412 it eq 413 .L2096: 414 000002ba 4770 415 ret 416 .L1769: Page 8 objs\release\startup.s 000002bc f8413b04 417 str r3,[r1],4 000002c0 4281 418 cmp r1,r0 000002c2 d1fb* 419 bne .L1769 420 .L2098: 421 000002c4 4770 422 ret 423 .endf InitBSS 424 ;pMem r1 local 425 426 .section ".bss","awb" 427 .L2020: 428 .endo .L2020 429 .section ".ghrettbl","" 00000028 00000000* 430 .L2095: .data.w .L2094 431 .endo .L2095 0000002c 00000000* 432 .L2097: .data.w .L2096 433 .endo .L2097 00000030 00000000* 434 .L2099: .data.w .L2098 435 .endo .L2099 436 .text 437 ..gh.f.f.1.a.1.e.9: 438 .endo ..gh.f.f.1.a.1.e.9 439 Reset_Handler:: 000002c6 b500 440 push {lr} 441 ..gh.beginasm.10: 442 .endo ..gh.beginasm.10 000002c8 b672 443 cpsid i 444 445 ..gh.endasm.11: 446 .endo ..gh.endasm.11 447 448 .L2166: 449 000002ca f000f800* 450 bl Watchdog_Disable 451 .L2168: 452 000002ce f7fffea1* 453 bl SetSTACK 454 .L2170: 455 000002d2 f7fffe95* 456 bl SetVTOR 457 .L2172: 458 000002d6 f7fffea0* 459 bl EnableFPU 460 .L2174: 461 000002da f7fffebb* 462 bl FillSRAM 463 .L2176: 464 000002de f7fffea5* 465 bl FillStack 466 .L2178: 467 000002e2 f7fffecf* 468 bl CopyRomToRam 469 .L2180: 470 000002e6 f7ffffc8* 471 bl InitBSS 472 ..gh.beginasm.12: 473 .endo ..gh.beginasm.12 000002ea b662 474 cpsie i 475 476 ..gh.endasm.13: 477 .endo ..gh.endasm.13 Page 9 objs\release\startup.s 478 479 .L2182: 480 000002ec f000f800* 481 bl main 482 .L2184: 483 000002f0 bd00 484 pop {pc} 485 .endf Reset_Handler 486 487 .section ".bss","awb" 488 .L2144: 489 .endo .L2144 490 .section ".ghcalltbl","" 491 .align 4 00000000 00000000* 492 .L2167: .data.w .L2166 493 .endo .L2167 00000004 00000000* 494 .L2169: .data.w .L2168 495 .endo .L2169 00000008 00000000* 496 .L2171: .data.w .L2170 497 .endo .L2171 0000000c 00000000* 498 .L2173: .data.w .L2172 499 .endo .L2173 00000010 00000000* 500 .L2175: .data.w .L2174 501 .endo .L2175 00000014 00000000* 502 .L2177: .data.w .L2176 503 .endo .L2177 00000018 00000000* 504 .L2179: .data.w .L2178 505 .endo .L2179 0000001c 00000000* 506 .L2181: .data.w .L2180 507 .endo .L2181 00000020 00000000* 508 .L2183: .data.w .L2182 509 .endo .L2183 510 .section ".ghrettbl","" 00000034 00000000* 511 .L2185: .data.w .L2184 512 .endo .L2185 513 .text 514 ;__STACK_TOP __STACK_TOP import 515 ;__STACK_END __STACK_END import 516 ;__SRAM_INIT_FLAG __SRAM_INIT_FLAG import 517 ;__SRAM_START __SRAM_START import 518 ;__SRAM_END __SRAM_END import 519 ;__RAM_RAM_CODE_INIT_START __RAM_RAM_CODE_INIT_START import 520 ;__ROM_RAM_CODE_INIT_START __ROM_RAM_CODE_INIT_START import 521 ;__ROM_RAM_CODE_INIT_END __ROM_RAM_CODE_INIT_END import 522 ;__RAM_DATA_INIT_START __RAM_DATA_INIT_START import 523 ;__ROM_DATA_INIT_START __ROM_DATA_INIT_START import 524 ;__ROM_DATA_INIT_END __ROM_DATA_INIT_END import 525 ;__RAM_MCAL_DATA_INIT_START __RAM_MCAL_DATA_INIT_START import 526 ;__ROM_MCAL_DATA_INIT_START __ROM_MCAL_DATA_INIT_START import 527 ;__ROM_MCAL_DATA_INIT_END __ROM_MCAL_DATA_INIT_END import 528 ;__RAM_INTERRUPT_START __RAM_INTERRUPT_START import 529 ;__ROM_INTERRUPT_START __ROM_INTERRUPT_START import 530 ;__ROM_INTERRUPT_END __ROM_INTERRUPT_END import 531 ;__BSS_SRAM_START __BSS_SRAM_START import 532 ;__BSS_SRAM_END __BSS_SRAM_END import 533 ;INIT_TABLE INIT_TABLE export 534 ;ZERO_TABLE ZERO_TABLE export 535 536 .section ".zero_table","a" 537 .align 4 00000000 00000000* 538 ZERO_TABLE:: .data.w __BSS_SRAM_START Page 10 objs\release\startup.s 00000004 00000000* 539 .data.w __BSS_SRAM_END 540 .endo ZERO_TABLE 541 .section ".init_table","a" 542 .align 4 00000000 00000000* 543 INIT_TABLE:: .data.w __RAM_RAM_CODE_INIT_START 00000004 00000000* 544 .data.w __ROM_RAM_CODE_INIT_START 00000008 00000000* 545 .data.w __ROM_RAM_CODE_INIT_END 0000000c 00000000* 546 .data.w __RAM_DATA_INIT_START 00000010 00000000* 547 .data.w __ROM_DATA_INIT_START 00000014 00000000* 548 .data.w __ROM_DATA_INIT_END 00000018 00000000* 549 .data.w __RAM_MCAL_DATA_INIT_START 0000001c 00000000* 550 .data.w __ROM_MCAL_DATA_INIT_START 00000020 00000000* 551 .data.w __ROM_MCAL_DATA_INIT_END 00000024 00000000* 552 .data.w __RAM_INTERRUPT_START 00000028 00000000* 553 .data.w __ROM_INTERRUPT_START 0000002c 00000000* 554 .data.w __ROM_INTERRUPT_END 555 .endo INIT_TABLE 556 .global __STACK_TOP 557 558 .global __STACK_END 559 560 .global __SRAM_INIT_FLAG 561 562 .global __SRAM_START 563 564 .global __SRAM_END 565 566 .global __RAM_RAM_CODE_INIT_START 567 568 .global __ROM_RAM_CODE_INIT_START 569 570 .global __ROM_RAM_CODE_INIT_END 571 572 .global __RAM_DATA_INIT_START 573 574 .global __ROM_DATA_INIT_START 575 576 .global __ROM_DATA_INIT_END 577 578 .global __RAM_MCAL_DATA_INIT_START 579 580 .global __ROM_MCAL_DATA_INIT_START 581 582 .global __ROM_MCAL_DATA_INIT_END 583 584 .global __RAM_INTERRUPT_START 585 586 .global __ROM_INTERRUPT_START 587 588 .global __ROM_INTERRUPT_END 589 590 .global __BSS_SRAM_START 591 592 .global __BSS_SRAM_END 593 594 .ghsnote info, 27, 8195, 640 595 .text