/*===========================================================================*/ /* Module = dr7f701018_irq.h */ /* Version = V1.40 */ /* extracted from device file dr7f701018.dvf */ /* generated by DeFiXRH850 0.7.7.3 */ /*===========================================================================*/ /* COPYRIGHT */ /*===========================================================================*/ /* Copyright (c) 2015 by Renesas Electronics Europe GmbH, */ /* a company of the Renesas Electronics Corporation */ /*===========================================================================*/ /* Purpose: Declarations of Interrupt Vector Table */ /* */ /*===========================================================================*/ /* */ /* Warranty Disclaimer */ /* */ /* Because the Product(s) is licensed free of charge, there is no warranty */ /* of any kind whatsoever and expressly disclaimed and excluded by Renesas, */ /* either expressed or implied, including but not limited to those for */ /* non-infringement of intellectual property, merchantability and/or */ /* fitness for the particular purpose. */ /* Renesas shall not have any obligation to maintain, service or provide bug */ /* fixes for the supplied Product(s) and/or the Application. */ /* */ /* Each User is solely responsible for determining the appropriateness of */ /* using the Product(s) and assumes all risks associated with its exercise */ /* of rights under this Agreement, including, but not limited to the risks */ /* and costs of program errors, compliance with applicable laws, damage to */ /* or loss of data, programs or equipment, and unavailability or */ /* interruption of operations. */ /* */ /* Limitation of Liability */ /* */ /* In no event shall Renesas be liable to the User for any incidental, */ /* consequential, indirect, or punitive damage (including but not limited */ /* to lost profits) regardless of whether such liability is based on breach */ /* of contract, tort, strict liability, breach of warranties, failure of */ /* essential purpose or otherwise and even if advised of the possibility of */ /* such damages. Renesas shall not be liable for any services or products */ /* provided by third party vendors, developers or consultants identified or */ /* referred to the User by Renesas in connection with the Product(s) and/or */ /* the Application. */ /* */ /*===========================================================================*/ /* Environment: */ /* Device: R7F701018xAFP */ /* IDE: GHS Multi for V800 V6.xx or later */ /*===========================================================================*/ #ifndef __R7F701018xAFP_IRQ_H #define __R7F701018xAFP_IRQ_H #define IRQ_TABLE_START 0x00000200u #define RESET_ENABLE 0x00000001u // #define SYSERR_ENABLE 0x00000010u // #define FETRAPEX_ENABLE 0x00000030u // #define EITRAP0_ENABLE 0x00000040u // #define EITRAP1_ENABLE 0x00000050u // #define RIEX_ENABLE 0x00000060u // #define UCPOP_ENABLE 0x00000080u // #define MIP_MDP_ENABLE 0x00000090u // #define PIE_ENABLE 0x000000A0u // #define MAE_ENABLE 0x000000C0u // #define FENMI_ENABLE 0x000000E0u // #define FEINT_ENABLE 0x000000F0u // #define EINTPRIO_0_ENABLE 0x00000100u // #define EINTPRIO_1_ENABLE 0x00000110u // #define EINTPRIO_2_ENABLE 0x00000120u // #define EINTPRIO_3_ENABLE 0x00000130u // #define EINTPRIO_4_ENABLE 0x00000140u // #define EINTPRIO_5_ENABLE 0x00000150u // #define EINTPRIO_6_ENABLE 0x00000160u // #define EINTPRIO_7_ENABLE 0x00000170u // #define EINTPRIO_8_ENABLE 0x00000180u // #define EINTPRIO_9_ENABLE 0x00000190u // #define EINTPRIO_10_ENABLE 0x000001A0u // #define EINTPRIO_11_ENABLE 0x000001B0u // #define EINTPRIO_12_ENABLE 0x000001C0u // #define EINTPRIO_13_ENABLE 0x000001D0u // #define EINTPRIO_14_ENABLE 0x000001E0u // #define EINTPRIO_15_ENABLE 0x000001F0u // #define INTTAUD0I0_ENABLE (IRQ_TABLE_START + 0x00000000u) // #define INTCSIH2IC_1_ENABLE (IRQ_TABLE_START + 0x00000000u) #ifndef INTTAUD0I0_ENABLE #define INTTAUD0I0_ENABLE 0x00000000u #endif #ifndef INTCSIH2IC_1_ENABLE #define INTCSIH2IC_1_ENABLE 0x00000000u #endif // #define INTTAUD0I2_ENABLE (IRQ_TABLE_START + 0x00000004u) // #define INTTAUD0I4_ENABLE (IRQ_TABLE_START + 0x00000008u) // #define INTTAUD0I6_ENABLE (IRQ_TABLE_START + 0x0000000Cu) // #define INTTAUD0I8_ENABLE (IRQ_TABLE_START + 0x00000010u) // #define INTTAUD0I10_ENABLE (IRQ_TABLE_START + 0x00000014u) // #define INTTAUD0I12_ENABLE (IRQ_TABLE_START + 0x00000018u) // #define INTTAUD0I14_ENABLE (IRQ_TABLE_START + 0x0000001Cu) // #define INTCSIH1IC_1_ENABLE (IRQ_TABLE_START + 0x00000020u) // #define INTTAPA0IPEK0_ENABLE (IRQ_TABLE_START + 0x00000020u) #ifndef INTCSIH1IC_1_ENABLE #define INTCSIH1IC_1_ENABLE 0x00000000u #endif #ifndef INTTAPA0IPEK0_ENABLE #define INTTAPA0IPEK0_ENABLE 0x00000000u #endif // #define INTTAPA0IVLY0_ENABLE (IRQ_TABLE_START + 0x00000024u) // #define INTCSIH1IR_1_ENABLE (IRQ_TABLE_START + 0x00000024u) #ifndef INTTAPA0IVLY0_ENABLE #define INTTAPA0IVLY0_ENABLE 0x00000000u #endif #ifndef INTCSIH1IR_1_ENABLE #define INTCSIH1IR_1_ENABLE 0x00000000u #endif // #define INTADCA0I0_ENABLE (IRQ_TABLE_START + 0x00000028u) // #define INTADCA0I1_ENABLE (IRQ_TABLE_START + 0x0000002Cu) // #define INTADCA0I2_ENABLE (IRQ_TABLE_START + 0x00000030u) // #define INTDCUTDI_ENABLE (IRQ_TABLE_START + 0x00000034u) // #define INTRCANGERR_ENABLE (IRQ_TABLE_START + 0x00000038u) // #define INTRCANGRECC_ENABLE (IRQ_TABLE_START + 0x0000003Cu) // #define INTRCAN0ERR_ENABLE (IRQ_TABLE_START + 0x00000040u) // #define INTRCAN0REC_ENABLE (IRQ_TABLE_START + 0x00000044u) // #define INTRCAN0TRX_ENABLE (IRQ_TABLE_START + 0x00000048u) // #define INTCSIG0IC_ENABLE (IRQ_TABLE_START + 0x0000004Cu) // #define INTCSIH1IRE_1_ENABLE (IRQ_TABLE_START + 0x0000004Cu) #ifndef INTCSIG0IC_ENABLE #define INTCSIG0IC_ENABLE 0x00000000u #endif #ifndef INTCSIH1IRE_1_ENABLE #define INTCSIH1IRE_1_ENABLE 0x00000000u #endif // #define INTCSIG0IR_ENABLE (IRQ_TABLE_START + 0x00000050u) // #define INTCSIH1IJC_1_ENABLE (IRQ_TABLE_START + 0x00000050u) #ifndef INTCSIG0IR_ENABLE #define INTCSIG0IR_ENABLE 0x00000000u #endif #ifndef INTCSIH1IJC_1_ENABLE #define INTCSIH1IJC_1_ENABLE 0x00000000u #endif // #define INTCSIH0IC_ENABLE (IRQ_TABLE_START + 0x00000054u) // #define INTCSIH0IR_ENABLE (IRQ_TABLE_START + 0x00000058u) // #define INTCSIH0IRE_ENABLE (IRQ_TABLE_START + 0x0000005Cu) // #define INTCSIH0IJC_ENABLE (IRQ_TABLE_START + 0x00000060u) // #define INTRLIN30_ENABLE (IRQ_TABLE_START + 0x00000064u) // #define INTRLIN30UR0_ENABLE (IRQ_TABLE_START + 0x00000068u) // #define INTRLIN30UR1_ENABLE (IRQ_TABLE_START + 0x0000006Cu) // #define INTRLIN30UR2_ENABLE (IRQ_TABLE_START + 0x00000070u) // #define INTP0_ENABLE (IRQ_TABLE_START + 0x00000074u) // #define INTCSIH2IR_1_ENABLE (IRQ_TABLE_START + 0x00000074u) #ifndef INTP0_ENABLE #define INTP0_ENABLE 0x00000000u #endif #ifndef INTCSIH2IR_1_ENABLE #define INTCSIH2IR_1_ENABLE 0x00000000u #endif // #define INTP1_ENABLE (IRQ_TABLE_START + 0x00000078u) // #define INTCSIH2IRE_1_ENABLE (IRQ_TABLE_START + 0x00000078u) #ifndef INTP1_ENABLE #define INTP1_ENABLE 0x00000000u #endif #ifndef INTCSIH2IRE_1_ENABLE #define INTCSIH2IRE_1_ENABLE 0x00000000u #endif // #define INTP2_ENABLE (IRQ_TABLE_START + 0x0000007Cu) // #define INTCSIH2IJC_1_ENABLE (IRQ_TABLE_START + 0x0000007Cu) #ifndef INTP2_ENABLE #define INTP2_ENABLE 0x00000000u #endif #ifndef INTCSIH2IJC_1_ENABLE #define INTCSIH2IJC_1_ENABLE 0x00000000u #endif // #define INTWDTA0_ENABLE (IRQ_TABLE_START + 0x00000080u) // #define INTWDTA1_ENABLE (IRQ_TABLE_START + 0x00000084u) // #define INTP3_ENABLE (IRQ_TABLE_START + 0x00000088u) // #define INTP4_ENABLE (IRQ_TABLE_START + 0x0000008Cu) // #define INTP5_ENABLE (IRQ_TABLE_START + 0x00000090u) // #define INTP10_ENABLE (IRQ_TABLE_START + 0x00000094u) // #define INTP11_ENABLE (IRQ_TABLE_START + 0x00000098u) // #define INTTAUD0I1_ENABLE (IRQ_TABLE_START + 0x0000009Cu) // #define INTTAUD0I3_ENABLE (IRQ_TABLE_START + 0x000000A0u) // #define INTTAUD0I5_ENABLE (IRQ_TABLE_START + 0x000000A4u) // #define INTTAUD0I7_ENABLE (IRQ_TABLE_START + 0x000000A8u) // #define INTTAUD0I9_ENABLE (IRQ_TABLE_START + 0x000000ACu) // #define INTTAUD0I11_ENABLE (IRQ_TABLE_START + 0x000000B0u) // #define INTTAUD0I13_ENABLE (IRQ_TABLE_START + 0x000000B4u) // #define INTTAUD0I15_ENABLE (IRQ_TABLE_START + 0x000000B8u) // #define INTADCA0ERR_ENABLE (IRQ_TABLE_START + 0x000000BCu) // #define INTCSIG0IRE_ENABLE (IRQ_TABLE_START + 0x000000C4u) // #define INTRLIN20_ENABLE (IRQ_TABLE_START + 0x000000C8u) // #define INTRLIN21_ENABLE (IRQ_TABLE_START + 0x000000CCu) // #define INTDMA0_ENABLE (IRQ_TABLE_START + 0x000000D0u) // #define INTDMA1_ENABLE (IRQ_TABLE_START + 0x000000D4u) // #define INTDMA2_ENABLE (IRQ_TABLE_START + 0x000000D8u) // #define INTDMA3_ENABLE (IRQ_TABLE_START + 0x000000DCu) // #define INTDMA4_ENABLE (IRQ_TABLE_START + 0x000000E0u) // #define INTDMA5_ENABLE (IRQ_TABLE_START + 0x000000E4u) // #define INTDMA6_ENABLE (IRQ_TABLE_START + 0x000000E8u) // #define INTDMA7_ENABLE (IRQ_TABLE_START + 0x000000ECu) // #define INTDMA8_ENABLE (IRQ_TABLE_START + 0x000000F0u) // #define INTDMA9_ENABLE (IRQ_TABLE_START + 0x000000F4u) // #define INTDMA10_ENABLE (IRQ_TABLE_START + 0x000000F8u) // #define INTDMA11_ENABLE (IRQ_TABLE_START + 0x000000FCu) // #define INTDMA12_ENABLE (IRQ_TABLE_START + 0x00000100u) // #define INTDMA13_ENABLE (IRQ_TABLE_START + 0x00000104u) // #define INTDMA14_ENABLE (IRQ_TABLE_START + 0x00000108u) // #define INTDMA15_ENABLE (IRQ_TABLE_START + 0x0000010Cu) // #define INTRIIC0TI_ENABLE (IRQ_TABLE_START + 0x00000110u) // #define INTRIIC0TEI_ENABLE (IRQ_TABLE_START + 0x00000114u) // #define INTRIIC0RI_ENABLE (IRQ_TABLE_START + 0x00000118u) // #define INTRIIC0EE_ENABLE (IRQ_TABLE_START + 0x0000011Cu) // #define INTTAUJ0I0_ENABLE (IRQ_TABLE_START + 0x00000120u) // #define INTTAUJ0I1_ENABLE (IRQ_TABLE_START + 0x00000124u) // #define INTTAUJ0I2_ENABLE (IRQ_TABLE_START + 0x00000128u) // #define INTTAUJ0I3_ENABLE (IRQ_TABLE_START + 0x0000012Cu) // #define INTOSTM0_ENABLE (IRQ_TABLE_START + 0x00000130u) // #define INTENCA0IOV_ENABLE (IRQ_TABLE_START + 0x00000134u) // #define INTPWGA4_ENABLE (IRQ_TABLE_START + 0x00000134u) #ifndef INTENCA0IOV_ENABLE #define INTENCA0IOV_ENABLE 0x00000000u #endif #ifndef INTPWGA4_ENABLE #define INTPWGA4_ENABLE 0x00000000u #endif // #define INTENCA0IUD_ENABLE (IRQ_TABLE_START + 0x00000138u) // #define INTPWGA5_ENABLE (IRQ_TABLE_START + 0x00000138u) #ifndef INTENCA0IUD_ENABLE #define INTENCA0IUD_ENABLE 0x00000000u #endif #ifndef INTPWGA5_ENABLE #define INTPWGA5_ENABLE 0x00000000u #endif // #define INTENCA0I0_ENABLE (IRQ_TABLE_START + 0x0000013Cu) // #define INTPWGA6_ENABLE (IRQ_TABLE_START + 0x0000013Cu) #ifndef INTENCA0I0_ENABLE #define INTENCA0I0_ENABLE 0x00000000u #endif #ifndef INTPWGA6_ENABLE #define INTPWGA6_ENABLE 0x00000000u #endif // #define INTENCA0I1_ENABLE (IRQ_TABLE_START + 0x00000140u) // #define INTPWGA7_ENABLE (IRQ_TABLE_START + 0x00000140u) #ifndef INTENCA0I1_ENABLE #define INTENCA0I1_ENABLE 0x00000000u #endif #ifndef INTPWGA7_ENABLE #define INTPWGA7_ENABLE 0x00000000u #endif // #define INTENCA0IEC_ENABLE (IRQ_TABLE_START + 0x00000144u) // #define INTKR0_ENABLE (IRQ_TABLE_START + 0x00000148u) // #define INTQFULL_ENABLE (IRQ_TABLE_START + 0x0000014Cu) // #define INTPWGA0_ENABLE (IRQ_TABLE_START + 0x00000150u) // #define INTPWGA1_ENABLE (IRQ_TABLE_START + 0x00000154u) // #define INTPWGA2_ENABLE (IRQ_TABLE_START + 0x00000158u) // #define INTPWGA3_ENABLE (IRQ_TABLE_START + 0x0000015Cu) // #define INTPWGA8_ENABLE (IRQ_TABLE_START + 0x00000160u) // #define INTPWGA9_ENABLE (IRQ_TABLE_START + 0x00000164u) // #define INTPWGA10_ENABLE (IRQ_TABLE_START + 0x00000168u) // #define INTPWGA11_ENABLE (IRQ_TABLE_START + 0x0000016Cu) // #define INTPWGA12_ENABLE (IRQ_TABLE_START + 0x00000170u) // #define INTPWGA13_ENABLE (IRQ_TABLE_START + 0x00000174u) // #define INTPWGA14_ENABLE (IRQ_TABLE_START + 0x00000178u) // #define INTPWGA15_ENABLE (IRQ_TABLE_START + 0x0000017Cu) // #define INTFLERR_ENABLE (IRQ_TABLE_START + 0x00000198u) // #define INTFLENDNM_ENABLE (IRQ_TABLE_START + 0x0000019Cu) // #define INTCWEND_ENABLE (IRQ_TABLE_START + 0x000001A0u) // #define INTRCAN1ERR_ENABLE (IRQ_TABLE_START + 0x000001A4u) // #define INTRCAN1REC_ENABLE (IRQ_TABLE_START + 0x000001A8u) // #define INTRCAN1TRX_ENABLE (IRQ_TABLE_START + 0x000001ACu) // #define INTTAPA0IPEK0_2_ENABLE (IRQ_TABLE_START + 0x000001B0u) // #define INTCSIH1IC_ENABLE (IRQ_TABLE_START + 0x000001B0u) #ifndef INTTAPA0IPEK0_2_ENABLE #define INTTAPA0IPEK0_2_ENABLE 0x00000000u #endif #ifndef INTCSIH1IC_ENABLE #define INTCSIH1IC_ENABLE 0x00000000u #endif // #define INTTAPA0IVLY0_2_ENABLE (IRQ_TABLE_START + 0x000001B4u) // #define INTCSIH1IR_ENABLE (IRQ_TABLE_START + 0x000001B4u) #ifndef INTTAPA0IVLY0_2_ENABLE #define INTTAPA0IVLY0_2_ENABLE 0x00000000u #endif #ifndef INTCSIH1IR_ENABLE #define INTCSIH1IR_ENABLE 0x00000000u #endif // #define INTCSIH1IRE_ENABLE (IRQ_TABLE_START + 0x000001B8u) // #define INTCSIG0IC_2_ENABLE (IRQ_TABLE_START + 0x000001B8u) #ifndef INTCSIH1IRE_ENABLE #define INTCSIH1IRE_ENABLE 0x00000000u #endif #ifndef INTCSIG0IC_2_ENABLE #define INTCSIG0IC_2_ENABLE 0x00000000u #endif // #define INTCSIH1IJC_ENABLE (IRQ_TABLE_START + 0x000001BCu) // #define INTCSIG0IR_2_ENABLE (IRQ_TABLE_START + 0x000001BCu) #ifndef INTCSIH1IJC_ENABLE #define INTCSIH1IJC_ENABLE 0x00000000u #endif #ifndef INTCSIG0IR_2_ENABLE #define INTCSIG0IR_2_ENABLE 0x00000000u #endif // #define INTRLIN31_ENABLE (IRQ_TABLE_START + 0x000001C0u) // #define INTRLIN31UR0_ENABLE (IRQ_TABLE_START + 0x000001C4u) // #define INTRLIN31UR1_ENABLE (IRQ_TABLE_START + 0x000001C8u) // #define INTRLIN31UR2_ENABLE (IRQ_TABLE_START + 0x000001CCu) // #define INTPWGA20_ENABLE (IRQ_TABLE_START + 0x000001D0u) // #define INTPWGA21_ENABLE (IRQ_TABLE_START + 0x000001D4u) // #define INTPWGA22_ENABLE (IRQ_TABLE_START + 0x000001D8u) // #define INTPWGA23_ENABLE (IRQ_TABLE_START + 0x000001DCu) // #define INTP6_ENABLE (IRQ_TABLE_START + 0x000001E0u) // #define INTP7_ENABLE (IRQ_TABLE_START + 0x000001E4u) // #define INTP8_ENABLE (IRQ_TABLE_START + 0x000001E8u) // #define INTP12_ENABLE (IRQ_TABLE_START + 0x000001ECu) // #define INTCSIH2IC_ENABLE (IRQ_TABLE_START + 0x000001F0u) // #define INTTAUD0I0_2_ENABLE (IRQ_TABLE_START + 0x000001F0u) #ifndef INTCSIH2IC_ENABLE #define INTCSIH2IC_ENABLE 0x00000000u #endif #ifndef INTTAUD0I0_2_ENABLE #define INTTAUD0I0_2_ENABLE 0x00000000u #endif // #define INTCSIH2IR_ENABLE (IRQ_TABLE_START + 0x000001F4u) // #define INTP0_2_ENABLE (IRQ_TABLE_START + 0x000001F4u) #ifndef INTCSIH2IR_ENABLE #define INTCSIH2IR_ENABLE 0x00000000u #endif #ifndef INTP0_2_ENABLE #define INTP0_2_ENABLE 0x00000000u #endif // #define INTP1_2_ENABLE (IRQ_TABLE_START + 0x000001F8u) // #define INTCSIH2IRE_ENABLE (IRQ_TABLE_START + 0x000001F8u) #ifndef INTP1_2_ENABLE #define INTP1_2_ENABLE 0x00000000u #endif #ifndef INTCSIH2IRE_ENABLE #define INTCSIH2IRE_ENABLE 0x00000000u #endif // #define INTCSIH2IJC_ENABLE (IRQ_TABLE_START + 0x000001FCu) // #define INTP2_2_ENABLE (IRQ_TABLE_START + 0x000001FCu) #ifndef INTCSIH2IJC_ENABLE #define INTCSIH2IJC_ENABLE 0x00000000u #endif #ifndef INTP2_2_ENABLE #define INTP2_2_ENABLE 0x00000000u #endif // #define INTPWGA16_ENABLE (IRQ_TABLE_START + 0x00000224u) // #define INTPWGA17_ENABLE (IRQ_TABLE_START + 0x0000022Cu) // #define INTPWGA18_ENABLE (IRQ_TABLE_START + 0x00000234u) // #define INTPWGA19_ENABLE (IRQ_TABLE_START + 0x0000023Cu) // #define INTRLIN32_ENABLE (IRQ_TABLE_START + 0x00000270u) // #define INTRLIN32UR0_ENABLE (IRQ_TABLE_START + 0x00000274u) // #define INTRLIN32UR1_ENABLE (IRQ_TABLE_START + 0x00000278u) // #define INTRLIN32UR2_ENABLE (IRQ_TABLE_START + 0x0000027Cu) // #define INTRCAN2ERR_ENABLE (IRQ_TABLE_START + 0x00000344u) // #define INTRCAN2REC_ENABLE (IRQ_TABLE_START + 0x00000348u) // #define INTRCAN2TRX_ENABLE (IRQ_TABLE_START + 0x0000034Cu) #endif /* __R7F701018xAFP_IRQ_H */