GHS Config Option Descriptions

Port Mode

Selects the ETM clocking mode used on the target system.

There are three choices for ETMv1.x and ETMv2.x targets:

Normal — Most targets only support this mode.
Multiplexed — Uses half as many pins to output trace information, but twice the clock rate.
Demultiplexed — Uses twice as many pins and half the clock rate. This mode typically requires a special adapter with dual Mictor connectors.

Multiplexed and Demultiplexed modes were eliminated with ETMv3.x. However, many ETMv3.x targets support several ETM clock multipliers relative to the processor core clock. All of the ETMv3.x clocking modes are listed below. Note that the ratios are of ETM data rate to core clock speed. The ETM data rate is twice the ETM clock speed because ETMv3.x always outputs data on both clock edges.

2:1
1:1
1:2
1:3
1:4
Implementation Defined
Dynamic

Port Size/CoreSight Port Size

Selects the ETM port size. This corresponds to the number of bits that will be drained from the ETMFIFO each cycle. Larger port sizes mean that more data can be generated without causing an overflow. It is generally desirable to use the largest port size supported by the target system.

For CoreSight targets, this option displays as CoreSight Port Size.

Data Capture

Selects the data access information that will be traced. The ETM can either trace data access addresses and values, addresses only, or values only.

Note: To reduce the number of ETMFIFO overflows in your trace data, you can set this option to Address Only. However, this setting reduces the effectiveness of TimeMachine by preventing reconstruction of register and memory values. For more information, see the documentation about incomplete trace data.

Cycle Accurate

Enables ETM cycle-accurate mode. For ETMv1.x and ETMv2.x targets, the ETM normally outputs one trace packet every cycle when trace is enabled. Often many of these packets contain no useful information and can be discarded by the trace collection device. When this option is enabled on those targets, no packets will be discarded. For ETMv3.x targets, this option enables cycle-accurate mode in the ETM, which then outputs cycle count data. This allows the trace tools to determine the number of cycles spent executing each instruction, but requires extra space in the trace buffer.

Note: For ETMv1.x and ETMv2.x targets, the ETM continues to output trace packets even when the processor is stopped at a breakpoint. Therefore it is generally not a good idea to enable Cycle Accurate mode if you will be hitting breakpoints while collecting trace data from an ETMv1.x or ETMv2.x target.

Break On Trigger

Enables halting of the target processor when the trigger event occurs. There is some slip between when the trigger occurs and where the target halts. For more information about configuring a trigger event, see the documentation about configuring trace collection.

This option does not support external triggers.

Filter Trace of Coprocessor Registers

Enables ETM trace filtering of coprocessor register accesses. For more information about trace filtering, see the documentation about configuring trace collection.

This option is only available when the Trace Coprocessor Registers option is enabled.

Half Rate Clocking

Enables ETM half rate clocking mode. In this mode trace packets are output on both the rising and falling edges of the trace clock. This allows the trace clock to run at half the speed of the core clock.

Note: Some targets do not support half rate clocking and some targets only support half rate clocking. If your target only supports one clocking mode, the Half Rate Clocking option is disabled and the appropriate clocking mode is selected automatically.

Note: This option is not available with ETMv3.x targets because trace data is always output on both clock edges with ETMv3.x.

Timestamps

Enables timestamps. When timestamps are enabled, the trace collection device records a timestamp with each packet. Timestamps are displayed in the Trace List and are used by the MULTI Profile window, PathAnalyzer, and EventAnalyzer.

Overflow Threshold

Some ETM targets can stall the CPU or suppress data trace to prevent a FIFO overflow when the ETM FIFO is close to full. This option specifies the number of bytes remaining in the FIFO when that action will be done. Setting this option to 0 disables overflow prevention.

For more information, see the Prevent Overflow by option.

Prevent Overflow by

Enables the ETMFIFOFull mechanism. The amount of data output by the ETM varies depending on the code being executed and the trace configuration. Code with a large number of indirect branches and data accesses (if data trace is enabled) may generate so much data that the ETMFIFO overflows. Trace data is lost when this happens. If this option is enabled, the ETM attempts to prevent FIFO overflows by using the selected method:

Stalling CPU — Attempts to stall the target processor when the FIFO is close to overflowing. This slows execution of code on the target, but can be very helpful in reducing the number of gaps in the trace data.
Suppressing Data Trace — Suppresses data trace when the FIFO is close to overflowing. This method is only available with ETMv3.x targets. Suppressing data trace is less effective at preventing the FIFO from overflowing than stalling the CPU, but has no impact on the speed of execution.

To configure the overflow threshold, see the Overflow Threshold option.

For more information, see the documentation about incomplete trace data.

Note: The ETMFIFOFull mechanism is not supported by some targets.

Use Embedded Trace Buffer

Enables use of the Embedded Trace Buffer (ETB). This option may only be changed if you use a SuperTrace Probe to connect to a target that has an ETB. If you use a normal Green Hills Probe to connect to a target with an ETB, the ETB must be used to collect trace data.

Trace Through Power-on Reset

Enables trace collection through power-on reset. This is implemented by trapping power-on reset on the SuperTrace Probe and restoring the ETM register configuration. This may not work properly on some targets and is only available with the SuperTrace Probe.

CoreSight Source ID

The CoreSight trace source ID of the ETM. Each CoreSight trace source on a system must have a unique ID between 0x1 and 0x6f.

Infer Branch Target

Controls the circumstances in which the target emits a branch's target address instead of requiring the decompressor to infer the address. Trace data is more compact when the decompressor infers more branch targets, while the decompressor is more resilient to errors in the collected trace data when fewer branches must be inferred. There are three choices:

Never — The PTM emits the target address for all branches, and the decompressor never needs to infer the target.
Direct Branches — The PTM does not emit the target address for direct branches; the decompressor must infer them instead.
Direct Branches and Return Addresses — The PTM does not emit the target address for direct branches or for some indirect branches that return from a function; the decompressor must infer them instead. Use this option if you are uncertain which option is most appropriate.

Cycle Accurate

Enables cycle-accurate mode. Often many trace packets contain no useful information and can be discarded by the trace collection device. When this option is enabled, no packets will be discarded. This allows the trace tools to determine the number of cycles spent executing each instruction, but requires extra space in the trace buffer.

INTEGRITY Interrupts at Address

Specifies the address that the interrupt vectors are copied to. For most ColdFire cores, this option should be set to 0x0.

INTEGRITY Interrupts at Other Location

Enable this option if you are tracing INTEGRITY and the BSP copies the interrupt handlers to a different address than the .vector section is mapped to.

Timestamps

Enable/Disable program trace with MSR[PMM]

When used in conjunction with a mechanism in target software that sets and clears the MSR[PMM] bit, this option aids in determining which sections of code are traced. The MSR[PMM] bit is the performance monitor mark bit, used for Nexus to provide execution context filtering.

Stall Processor to Avoid Overflows

Enables processor stalling to prevent FIFO overflows. The amount of trace data output by the target varies depending on the code being executed and the trace configuration. Code with a large number of indirect branches and data accesses (if data trace is enabled) may generate so much data that the FIFO overflows. Trace data is lost when this happens. If this option is enabled, the processor stalls when the FIFO starts to fill. This is very effective at preventing FIFO overflows, but does not prevent all overflows. For more information, see the documentation about incomplete trace data.

Note: OS-awareness in TimeMachine requires specific parts of OS execution to be reconstructed. If kernel trace data is lost due to FIFO overflows, MULTI may discard trace data for some tasks. In this case, enabling Stall Processor to Avoid Overflows may improve OS-awareness.

Timestamps

QorIQ targets buffer Nexus trace data before sending it out over high-speed serial trace (HSST). The buffer creates a variation in the time delta between when the packet is emitted by the core and when it actually sends over HSST. The size of the delta is inversely proportional to the HSST bandwidth, and varies depending on how full the buffer is. At minimum bandwidth (1 Aurora lane at 2.5 Gpbs), the maximum error is approximately 65 us.

Timestamps

Cycle Accurate

Enables IBM cycle-accurate mode. Often many trace packets contain no useful information and can be discarded by the trace collection device. When this option is enabled, no packets will be discarded. This allows the trace tools to determine the number of cycles spent executing each instruction, but requires extra space in the trace buffer.

MDO Data Port Width

Selects the number of pins used to output trace data. Some targets support multiple MDO data port widths. Using a larger port width reduces the chance of a processor stall and/or FIFO overflow. We recommend using the largest port width that your target supports. If you specify an unsupported port width, you may get invalid trace data.

Trace Clock Multiplier

Specifies the divisor for the trace clock. Not all targets support all divisors listed. In general, a faster trace collect (smaller divisor) allows for more data to be collected and results in fewer FIFO overflows. If you specify a divisor that your target does not support, you may get invalid trace data.

Stall Processor to Avoid Overflows

Use Branch History Messages

Enables branch history messaging. Most Nexus targets are capable of generating 2 different types of Nexus program trace messages. Traditional Nexus program trace messages are generated each time a branch is taken (direct or indirect). Branch history messaging only generates a message when 31 direct branch instructions have been executed (taken or not) or when an indirect branch is taken.

Advantages of Branch History Messages:

More compact trace data
- Less chance of overflow
- Better utilization of trace buffer space

Disadvantages of Branch History Messages:

More likely to have uncorrelated data trace
More data is lost as a result of an overflow
- Less likely that the tools will be able to reconstruct missing instructions
Less precise filtering
Less accurate timestamps
Less precise reporting of trigger locations

Note: ARM mode instructions on Nexus ARM targets (MAC71xx) are always traced with branch history messages.

Timestamps

This option is only supported with SuperTrace Probe v3.