general { version = 3 bit_0_is_msb = true } %define _DESC0_ \ desc += "CMU Control Status Register. " %define _DESC1_ \ desc += "The software can only set this bit to start a clock frequency measure. It is\n"\ desc += "reset by hardware when the measure is ready in the CMU_FDR." %define _DESC2_ \ desc += "CKSEL1 selects the clock to be measured by the frequency meter. This only\n"\ desc += "affects CMU instances that utilizes clock metering.\n\n"\ desc += "Not all CMU blocks will utilize this feature. See the 'Clocking' chapter for\n"\ desc += "device specific CMU implementation details." %define _DESC3_ \ desc += "These bits specify the CLKMT0_RMN division factor. The output clock frequency\n"\ desc += "is f CLKMT0_RMN / 2 RCDIV . This output clock is used as reference clock to\n"\ desc += "compare with CLKMN0_RMT for crystal clock monitor feature." %define _DESC4_ \ desc += "CMU Frequency Display Register. The FDR is used to determine the measured\n"\ desc += "frequency being monitored by the CMU." %define _DESC5_ \ desc += "This register displays the measured frequency ( f sel ) with respect to the\n"\ desc += "reference clock ( f CLKMN0_RMT ). The measured value is given by the following\n"\ desc += "formula:\n\n"\ desc += "f sel = ( f CLKMN0_RMT x CMU_MDR[MD]) / CMU_FDR[FD]" %define _DESC6_ \ desc += "CMU High Frequency Reference Register CLKMN1. The HFREFR is configured for the\n"\ desc += "high frequency reference that the CMU will use for comparing against the\n"\ desc += "monitored clock.The figure and table below show the HFREFR register." %define _DESC7_ \ desc += "These bits determine the high reference value for the CLKMN1 frequency. The\n"\ desc += "reference value is given by: (HFREF / 16) x ( f CLKMT0_RMN / 164)." %define _DESC8_ \ desc += "CMU Low Frequency Reference Register CLKMN1. The LFREFR is configured for the\n"\ desc += "low frequency reference that the CMU will use for comparing against the\n"\ desc += "monitored clock. The figure and table below show the LFREFR register." %define _DESC9_ \ desc += "Reserved" %define _DESC10_ \ desc += "These bits determine the low reference value for the CLKMN1 frequency. The\n"\ desc += "reference value is given by: (LFREF / 16) x ( f CLKMT0_RMN / 4)." %define _DESC11_ \ desc += "CMU Interrupt Status Register. All the flags in CMU_ISR register set\n"\ desc += "asynchronously. This register must be read only after an interrupt (safe mode\n"\ desc += "entry) is triggered by the CMU as confirmed by MC_RGM. Otherwise, the read\n"\ desc += "access on this register may fetch an incorrect value. Before entering\n"\ desc += "low-power stop modes, all clock frequency measurements in CMU should be\n"\ desc += "disabled. Failing to do so may result in spurious interrupts." %define _DESC12_ \ desc += "This bit is set by hardware when CLKMN1 frequency becomes higher than HFREF\n"\ desc += "value and CLKMN1 is 'ON' . It can be cleared by software by writing '1'." %define _DESC13_ \ desc += "This bit is set by hardware when CLKMN1 frequency becomes lower than LFREF\n"\ desc += "value, and CLKMN1 is 'ON' . Software clears this field by writing a '1'." %define _DESC14_ \ desc += "This bit is set by hardware when the f CLKMN0_RMT is less than f CLKMT0_RMN /\n"\ desc += "2 RCDIV frequency and CLKMN0_RMT is 'ON' . It can be cleared by software by\n"\ desc += "writing '1'." %define _DESC15_ \ desc += "CMU Measurement Duration Register. " %define _DESC16_ \ desc += "This field displays the measurement duration in terms of selected clock\n"\ desc += "(CLKMT0_RMN) cycles. This value is loaded in the frequency meter down-counter.\n"\ desc += "The down-counter starts counting when CMU_CSR [SFM] = 1." %define _DESC17_ \ desc += "Module Configuration Register. The Decimation Filter module configuration\n"\ desc += "register provides configuration control bits for the Decimation Filter internal\n"\ desc += "logic.\n\n"\ desc += "One must not modify this register contents when the status bit BSY is set,\n"\ desc += "except for fields FREN, FRZ, and IDIS. To guarantee that BSY does not set\n"\ desc += "during the read-modify-write operation, it is advisable to set IDIS=1 and wait\n"\ desc += "for BSY=0 beforehand." %define _DESC18_ \ desc += "The MDIS bit puts the Decimation Filter in low power mode. Writes to the\n"\ desc += "configuration register are allowed with the exception of writes to the FREN and\n"\ desc += "SRES bits, which are ignored. Writes to the Coefficient registers are also\n"\ desc += "allowed. The Decimation Filter cannot enter Freeze mode once in disable mode." %define _DESC19_ \ desc += "The FREN bit enables the Decimation Filter to enter freeze mode if the signal\n"\ desc += "or the FRZ bit is asserted. See Freeze Mode Description for more details." %define _DESC20_ \ desc += "The FRZ bit controls the freeze mode of the Decimation Filter. For this bit to\n"\ desc += "take effect the FREN freeze enable bit also needs to be asserted. While in\n"\ desc += "freeze mode the MAC operations are halted. See Freeze Mode Description for more\n"\ desc += "details." %define _DESC21_ \ desc += "The SRES is a self-negated bit which provides the CPU with the capability to\n"\ desc += "initialize the Decimation Filter through the interface. This bit always reads\n"\ desc += "as zero. See Soft-Reset Command Description for more details." %define _DESC22_ \ desc += "The IDEN bit enables the Decimation Filter to generate interrupt requests on\n"\ desc += "all new input data written to the Interface Input Buffer register or\n"\ desc += "Input/Output Buffers register." %define _DESC23_ \ desc += "The ODEN bit enables the Decimation Filter to generate interrupt requests on\n"\ desc += "all new data written to the filter Output buffer. It is independent of how ISEL\n"\ desc += "set." %define _DESC24_ \ desc += "The ERREN bit enables the Decimation Filter to generate interrupt requests\n"\ desc += "based on the assertion of the DECFILTER_MSR register error flags OVF, DIVR,\n"\ desc += "SVR, OVR, or IVR." %define _DESC25_ \ desc += "The FTYPE[1:0] bits select the filter type. Bypass must not be configured in\n"\ desc += "cascade mode (see field CASCD)." %define _DESC26_ \ desc += "The SCAL[1:0] bit field selects the scaling factor used by the filter\n"\ desc += "algorithm." %define _DESC27_ \ desc += "The IDIS bit disables the block input, so that writes to the input buffer have\n"\ desc += "no effect (from the ), and input DMA or interrupt requests are not issued.\n"\ desc += "Input disabling is needed to change the block configuration to or from cascade\n"\ desc += "mode. IDIS resets in 1 (hardware reset only), and the module configuration\n"\ desc += "procedures for previous versions (without IDIS bit) are upward compatible\n"\ desc += "provided that the DECFILTER_MCR register is written with 0 into the IDIS\n"\ desc += "position (previously reserved)." %define _DESC28_ \ desc += "The SAT bit enables the saturation of the filter output. See Saturation for\n"\ desc += "more details." %define _DESC29_ \ desc += "The ISEL bit selects the source of input data to the Filter." %define _DESC30_ \ desc += "The DEC_RATE[3:0] field selects the decimation rate used by the Decimation\n"\ desc += "Filter. The decimation rate defines the number of data samples from the master\n"\ desc += "block that is required to generate one decimated result in the Decimation\n"\ desc += "Filter output." %define _DESC31_ \ desc += "The SDIE field enables output buffer interrupts due to integrator data result\n"\ desc += "being ready (at registers DECFILTER_FINTVAL and DECFILTER_FINTCNT):" %define _DESC32_ \ desc += "The DSEL bit determines whether the data transfers -- to the input buffer\n"\ desc += "(write to) and from the output buffer (read from) -- are performed by DMA\n"\ desc += "requests or by interrupt requests." %define _DESC33_ \ desc += "The IBIE bit enables the Decimation Filter to generate interrupt requests when:\n"\ desc += "input is selected (ISEL=1) and DSEL=0 when the input buffer is available to\n"\ desc += "receive new data;" %define _DESC34_ \ desc += "The OBIE bit enables the Decimation Filter interrupt requests when outputs are\n"\ desc += "directed to the and DMA is not selected (DSEL=0)." %define _DESC35_ \ desc += "Module Status Register. " %define _DESC36_ \ desc += "The BSY bit indicates that the Decimation Filter is processing new input data\n"\ desc += "from the master block in normal mode or from the core in standalone mode. BSY\n"\ desc += "is not asserted when the filter is disabled (FTYPE = 00). However, the BSY bit\n"\ desc += "is asserted when the soft reset is executed." %define _DESC37_ \ desc += "The DEC_COUNTER[3:0] field indicates the current value of the DEC_COUNTER\n"\ desc += "Decimation Counter (see ), which counts the number of input data samples\n"\ desc += "received by the Decimation Filter. When the value of this counter matches the\n"\ desc += "DEC_RATE[3:0] Configuration Register field, one decimated result is generated\n"\ desc += "and the DEC_COUNTER counter is re-initialized at zero. This register is cleared\n"\ desc += "by a soft reset or a flush command." %define _DESC38_ \ desc += "The IDFC bit clears the IDF Flag bit in the Status Register. This bit is self\n"\ desc += "negated, therefore it is always read as zero." %define _DESC39_ \ desc += "The ODFC bit clears the ODF Flag bit in the Status Register. This bit is self\n"\ desc += "negated, therefore it is always read as zero." %define _DESC40_ \ desc += "The IBIC bit clears the IBIF Flag bit in the Status Register. This bit is self\n"\ desc += "negated, therefore it is always read as zero." %define _DESC41_ \ desc += "The OBIC bit clears the OBIF Flag bit in the Status Register. This bit is self\n"\ desc += "negated, therefore it is always read as zero." %define _DESC42_ \ desc += "The OVFC bit clears the OVF Output Overflow bit in the Status Register. This\n"\ desc += "bit is self negated, therefore it is always read as zero." %define _DESC43_ \ desc += "The OVRC bit clears the OVR Output Overrun bit in the Status Register. This bit\n"\ desc += "is self negated, therefore it is always read as zero." %define _DESC44_ \ desc += "The IVRC bit clears the IVR Filter Input Overrun indication bit in the Status\n"\ desc += "Register. This bit is self negated, therefore it is always read as zero." %define _DESC45_ \ desc += "The IDF bit flag indicates when new data is available at the DECFILTER_IB\n"\ desc += "register or at the DECFILTER_IOB register. This flag generates an Interrupt\n"\ desc += "Request if enabled by the IDEN bit in the Configuration Register. This Flag is\n"\ desc += "cleared by the IDFC Status bit or by a soft reset of the decimation filter.\n"\ desc += "OBS: This flag is not used for read / write requests. It is used only to\n"\ desc += "announce the input data event. For read / write request flag, refer to IBIF." %define _DESC46_ \ desc += "The ODF bit flag indicates when a new decimated sample is available at the\n"\ desc += "DECFILTER_OB register or at the DECFILTER_IOB register. This flag generates an\n"\ desc += "Interrupt Request if enabled by the ODEN bit in the Configuration Register.\n"\ desc += "This Flag is cleared by the ODFC Status bit or by a soft reset of the\n"\ desc += "decimation filter. OBS: This flag is not used for read requests. It is used\n"\ desc += "only to announce the output data event. For read request flag, refer to OBIF." %define _DESC47_ \ desc += "The IBIF bit flag indicates that the input buffer DECFILTER_IB is available to\n"\ desc += "be filled with new data, when Enhanced Debug Monitor is off. In Enhanced Debug\n"\ desc += "Monitor, it indicates the input buffer DECFILTER_IB was filled with a new\n"\ desc += "sample and is ready to be read. IBIF assertion also asserts the interrupt\n"\ desc += "signal when enabled by the IBIE bit in the Configuration Register when DMA is\n"\ desc += "not selected (DSEL=0) and the input buffer requires access from the (ISEL !=\n"\ desc += "EDME). This Flag is cleared by the IBIC Status bit or by a soft reset of the\n"\ desc += "decimation filter." %define _DESC48_ \ desc += "The OBIF bit flag indicates that a new decimated sample is available at the\n"\ desc += "DECFILTER_OB register. This flag generates an Interrupt Request if enabled by\n"\ desc += "the OBIE bit in the Configuration Register and with DSEL=0. This Flag is\n"\ desc += "cleared by the OBIC Status bit or by a soft reset of the decimation filter." %define _DESC49_ \ desc += "The OVF bit indicates that an overflow occurred in the filtered sample result.\n"\ desc += "This flag generates an Interrupt Request if enabled by the ERREN bit in the\n"\ desc += "Configuration Register. This Flag is cleared by the OVFC Status bit or by a\n"\ desc += "soft reset of the decimation filter." %define _DESC50_ \ desc += "The OVR bit indicates that a decimated sample was overwritten by a new sample\n"\ desc += "in the Interface Output Buffer Register. This flag generates an Interrupt\n"\ desc += "Request if enabled by the ERREN bit in the Configuration Register. This Flag is\n"\ desc += "cleared by the OVRC Status bit or by a soft reset of the decimation filter." %define _DESC51_ \ desc += "The IVR bit indicates that a received sample in the Filter Interface Input\n"\ desc += "Register was overwritten by a new sample. This was probably caused by a\n"\ desc += "violation of the Decimation Filter maximum throughput. This flag generates an\n"\ desc += "Interrupt Request if enabled by the ERREN bit in the Configuration Register.\n"\ desc += "This Flag is cleared by the IVRC Status bit or by a soft reset of the\n"\ desc += "decimation filter. IVR does not set due to input register writes when input is\n"\ desc += "disabled (DECFILTER_MCR bit IDIS=1)." %define _DESC52_ \ desc += "Module Extended Config Register. " %define _DESC53_ \ desc += "The SDMAE bit enables the DMA request when an integrator output is requested\n"\ desc += "(see Integrator Outputs ). The DMA channel used is the same one used for filter\n"\ desc += "outputs, and any configuration that generates DMA requests from both of those\n"\ desc += "sources is not allowed." %define _DESC54_ \ desc += "The SSIG bit defines how the filtered data signal is treated for integration:" %define _DESC55_ \ desc += "The SSAT bit defines how the integrator accumulator behaves in case of an\n"\ desc += "overflow. In saturated operation the overflown integration sum holds the value\n"\ desc += "0xFFFFFFFF for absolute integration (SSIG=0), or values 0x7FFFFFFF (positive\n"\ desc += "saturation) and 0x80000000 (negative saturation) for signaled integration\n"\ desc += "(SSIG=1). Non-saturated mode is not supported with signaled integration,\n"\ desc += "therefore one must not configure SSIG=1 and SSAT=0." %define _DESC56_ \ desc += "The SCSAT bit defines how the integrator sample counter behaves in case of an\n"\ desc += "overflow." %define _DESC57_ \ desc += "The SRQ bit is used to command the update of the integrator output, reflected\n"\ desc += "in the registers DECFILTER_FINTVAL and DECFILTER_FINTCNT. It may also cause a\n"\ desc += "DMAor interrupt request, depending on the DECFILTER_MCR bit SDIE and\n"\ desc += "DECFILTER_MXCR bit SDMAE. This is a write-only bit, so reads always return 0.\n"\ desc += "For more details see Integrator Reset ." %define _DESC58_ \ desc += "The SZRO bit is used to zero the integrator sum. This is a write-only bit,\n"\ desc += "reads always return 0. For more details see Integrator Reset . If bits SRQ and\n"\ desc += "SZRO are both written 1 at the same time, the integrator is reset only after\n"\ desc += "the registers DECFILTER_FINTVAL and DECFILTER_FINTCNT are updated." %define _DESC59_ \ desc += "The SISEL bit selects the input of the integrator. For more details see\n"\ desc += "Integrator Inputs ." %define _DESC60_ \ desc += "The SZROSEL field defines the use of the integrator zero hardware input signal.\n"\ desc += "For more details see Integrator Reset ." %define _DESC61_ \ desc += "The SHLTSEL field defines the integrator halting mechanism. When the integrator\n"\ desc += "is halted, the integration accumulator remains unaltered on filter outputs\n"\ desc += "independently of the enabling selected by SENSEL. For more details see\n"\ desc += "Integrator Enabling and Halting ." %define _DESC62_ \ desc += "The SRQSEL field defines the use of the integrator output request hardware\n"\ desc += "input signal. An integrator output request updates the registers\n"\ desc += "DECFILTER_FINTVAL and DECFILTER_FINTCNT, also causing a DMA or interrupt\n"\ desc += "request. Note that DMA or interrupt requests due to integrator output updates\n"\ desc += "depend on the DECFILTER_MXCR bit SDMAE and DECFILTER_MCR bit SDIE.\n\n"\ desc += "When continuous output is on, an integrator output request is issued whenever a\n"\ desc += "new filter output is accumulated. For more details see Integrator Outputs ." %define _DESC63_ \ desc += "The SENSEL field defines the integrator enabling mechanism. When the integrator\n"\ desc += "is enabled, filter outputs selected by the SISEL bit are added to the\n"\ desc += "integration accumulator. When the integrator is disabled, the integration\n"\ desc += "accumulator remains unaltered on filter outputs. For more details see\n"\ desc += "Integrator Enabling and Halting ." %define _DESC64_ \ desc += "Module Extended Status Register. " %define _DESC65_ \ desc += "The SDFC bit clears the SDF Flag bit in the Status Register. This bit is self\n"\ desc += "negated, therefore it is always read as zero." %define _DESC66_ \ desc += "The SSEC bit clears the SSE flag bit in the Status Register. This bit is self\n"\ desc += "negated, therefore it is always read as zero." %define _DESC67_ \ desc += "The SCEC bit clears the SCE flag bit in the Status Register. This bit is self\n"\ desc += "negated, therefore it is always read as zero." %define _DESC68_ \ desc += "The SSOVFC bit clears the SSOVF Flag bit in the Status Register. This bit is\n"\ desc += "self negated, therefore it is always read as zero." %define _DESC69_ \ desc += "The SCOVFC bit clears the SCOVF Flag bit in the Status Register. This bit is\n"\ desc += "self negated, therefore it is always read as zero." %define _DESC70_ \ desc += "The SVRC bit clears the SVR Integrator Data Overrun indication bit in the\n"\ desc += "Status Register. This bit is self negated, therefore it is always read as zero." %define _DESC71_ \ desc += "The SDF bit flag indicates when a new integrator result is available at the\n"\ desc += "DECFILTER_FINTVAL register. This flag generates an Interrupt Request if enabled\n"\ desc += "by the SDIE bit in the Configuration Register. This flag is cleared by the SDFC\n"\ desc += "Status bit or by a soft reset of the decimation filter." %define _DESC72_ \ desc += "The SSE bit indicates an exceptional condition of the integrator accumulator.\n"\ desc += "This flag generates an Interrupt Request if enabled by the DECFILTER_MCR bit\n"\ desc += "ERREN, and it is cleared by the SSEC bit or by a soft reset. Integrator\n"\ desc += "exceptions are defined in Section 1.6.15.5, 'Integrator Exceptions'." %define _DESC73_ \ desc += "The SCE bit indicates an exceptional condition of the integrator counter. This\n"\ desc += "flag generates an Interrupt Request if enabled by the DECFILTER_MCR bit ERREN,\n"\ desc += "and it is cleared by the SCEC bit or by a soft reset. Integrator exceptions are\n"\ desc += "defined in Section 1.6.15.5, 'Integrator Exceptions'." %define _DESC74_ \ desc += "The SSOVF bit indicates an overflow of the integrator accumulator. This flag is\n"\ desc += "cleared by the SSOVFC bit or by a soft reset. The SSOVF bit samples the\n"\ desc += "integrator accumulator overflow condition when and only when either registers\n"\ desc += "DECFILTER_FINTVAL or DECFILTER_CINTCNT are updated. Therefore, only one of the\n"\ desc += "register pairs (DECFILTER_FINTVAL/DECFILTER_FINTCNT and\n"\ desc += "DECFILTER_CINTVAL/DECFILTER_CINTCNT) must be used by the application, in order\n"\ desc += "to avoid races." %define _DESC75_ \ desc += "The SCOVF bit flag indicates an overflow of the internal integrated sample\n"\ desc += "counter. This flag is cleared by the SCOVFC bit or by a soft reset. The SCOVF\n"\ desc += "bit samples the integrator accumulator overflow condition when and only when\n"\ desc += "either registers DECFILTER_FINTVAL or DECFILTER_CINTCNT are updated. Therefore,\n"\ desc += "only one of the register pairs (DECFILTER_FINTVAL/DECFILTER_FINTCNT and\n"\ desc += "DECFILTER_CINTVAL/DECFILTER_CINTCNT) must be used by the application, in order\n"\ desc += "to avoid races." %define _DESC76_ \ desc += "The SVR bit indicates that an integration value and count in the registers\n"\ desc += "DECFILTER_FINTVAL and DECFILTER_FINTCNT was overwritten by a new integrator\n"\ desc += "output request and was not read by the CPU or DMA. This flag generates an\n"\ desc += "Interrupt Request if enabled by the ERREN bit in the Configuration Register.\n"\ desc += "This Flag is cleared by the SVRC bit or by a soft reset." %define _DESC77_ \ desc += "Interface Input Buffer. The Input Buffer Register provides access to the Input\n"\ desc += "buffer of the decimation filter when the filter is in the standalone of\n"\ desc += "operation. Writes to this register are interpreted as requests to the\n"\ desc += "Decimation Filter to process new sample data." %define _DESC78_ \ desc += "The INTAG[3:0] bit field is defined as a selector signal and it is used to\n"\ desc += "identify different destinations for the INPBUF[15:0] data." %define _DESC79_ \ desc += "The PREFILL bit selects the Decimation Filter operation mode. For more details,\n"\ desc += "see Filter Prefill Control Description" %define _DESC80_ \ desc += "Assertion of the FLUSH bit initializes the Decimation Filter to a initial\n"\ desc += "state, as defined in Flush Command Description . This bit is self negated and\n"\ desc += "it is cleared only when the data is read and the flush is executed." %define _DESC81_ \ desc += "The INPBUF[15:0] bit field carries the sample data to be filtered. See Input\n"\ desc += "Buffer Description for more details." %define _DESC82_ \ desc += "Interface Output Buffer. " %define _DESC83_ \ desc += "The OUTTAG[3:0] bit field is defined as a selector signal and it is used to\n"\ desc += "identify different destinations for the OUTBUF[15:0] data." %define _DESC84_ \ desc += "The OUTPBUF[15:0] bit field is the result data in the decimation filter Output\n"\ desc += "Buffer. It represents a fixed point signed number in two's complement format\n"\ desc += "and is updated only when a decimated result is ready to be transmitted, meaning\n"\ desc += "it contains the last decimated result from the filter." %define _DESC85_ \ desc += "Filter Coefficient. " %define _DESC86_ \ desc += "Bit COEFn[23] is repeated 8 times." %define _DESC87_ \ desc += "The COEFn[23:0] bit fields are the digital filter coefficients registers. The\n"\ desc += "coefficients are fractional signed values in two's complement format, in the\n"\ desc += "range (coef is greater than or equal to -1 and less than 1).\n\n"\ desc += "Reads to this register are sign-extended, meaning the coefficient's sign bit is\n"\ desc += "copied to all 8 most significant register bits. Writing to these fields when\n"\ desc += "BSY=1 is not allowed." %define _DESC88_ \ desc += "Filter TAP. The TAP register stores, on each filter node, the input sample data\n"\ desc += "and, for the IIR type, the filter intermediary results." %define _DESC89_ \ desc += "Bit TAPn[23] is repeated 8 times." %define _DESC90_ \ desc += "The read-only TAPn[23:0] bit fields shows the contents of the digital filter\n"\ desc += "tap registers, as fractional signed values in two's complement format, in the\n"\ desc += "range (coef is greater than or equal to -1 and less than 1).\n\n"\ desc += "Reads to this register are sign-extended, meaning the coefficient's sign bit is\n"\ desc += "copied to all 8 most significant register bits.\n\n"\ desc += "The content of these registers is meaningless when BSY=1." %define _DESC91_ \ desc += "Final Integer Value Register. " %define _DESC92_ \ desc += "The SUM_VALUE[31:0] field holds the sum of filtered output values. The 17 most\n"\ desc += "significant bits hold the integer part, and the 15 least significant ones the\n"\ desc += "fractional part of the integration value. The control of the integration sum\n"\ desc += "and update of this register is determined by the register DECFILTER_MXCR. The\n"\ desc += "register is updated only upon an integration output request.\n\n"\ desc += "SUM_VALUE should be taken as an unsigned number when the integrator is\n"\ desc += "configured for absolute operation (DECFILTER_MXCR bit SSIG=0), and a two's\n"\ desc += "complement signed number otherwise.\n\n"\ desc += "If the DEFILTER_MXCR bit SSAT=1, the integration sum is saturated, so that if\n"\ desc += "the accumulation overflows DECFILTER_FINTVAL holds the value 0xFFFFFFFF for\n"\ desc += "absolute integration (SSIG=0), or values 0x7FFFFFFF (positive saturation) and\n"\ desc += "0x80000000 (negative saturation) for signaled integration (SSIG=1).\n\n"\ desc += "If SSAT=0, DECFILTER_FINTVAL holds the integration sum modulo 2 17 (considering\n"\ desc += "the 15-bit fractional part)." %define _DESC93_ \ desc += "Final Integer Count Register. " %define _DESC94_ \ desc += "The COUNT field holds the count of filtered outputs integrated. The control of\n"\ desc += "the integration sum and update of this register is determined by the register\n"\ desc += "DECFILTER_MXCR. The register is updated together with DECFILTER_FINTVAL, only\n"\ desc += "upon an integration output request." %define _DESC95_ \ desc += "Current Integer Value Register. " %define _DESC96_ \ desc += "The SUM_VALUE[31:0] field holds an unsigned number representing the sum of\n"\ desc += "filtered output values, continuously updated as the integration proceeds. The\n"\ desc += "control of the integration sum is determined by the register DECFILTER_MXCR. If\n"\ desc += "the DEFILTER_MXCR bit SSAT=1, the integration sum is saturated, so that if the\n"\ desc += "accumulation overflows DECFILTER_CINTVAL holds the value 0xFFFFFFFF for\n"\ desc += "absolute integration (SSIG=0), or values 0x7FFFFFFF (positive saturation) and\n"\ desc += "0x80000000 (negative saturation) for signaled integration (SSIG=1).\n\n"\ desc += "If SSAT=0, DECFILTER_FINTVAL holds the integration sum modulo 217 (considering\n"\ desc += "the 15-bit fractional part).\n\n"\ desc += "A read on this register automatically commands an update of the register\n"\ desc += "DECFILTER_CINTCNT." %define _DESC97_ \ desc += "Current Integer Count Register. " %define _DESC98_ \ desc += "The COUNT field holds the count of filtered outputs integrated. The value is\n"\ desc += "updated only when register DECFILTER_CINTVAL is read, to keep the coherency\n"\ desc += "between the integration and count values." %define _DESC99_ \ desc += "Channel Configuration register. Each of the DMA channels can be independently\n"\ desc += "enabled/disabled and associated with one of the DMA slots (peripheral slots or\n"\ desc += "always-on slots) in the system.\n\n"\ desc += "Setting multiple CHCFG registers with the same Source value will result in\n"\ desc += "unpredictable behavior. Before changing the trigger or source settings a DMA\n"\ desc += "channel must be disabled via the CHCFGn[ENBL] bit." %define _DESC100_ \ desc += "Specifies which DMA source, if any, is routed to a particular DMA channel. See\n"\ desc += "your device's chip configuration details for information about the peripherals\n"\ desc += "and their slot numbers." %define _DESC101_ \ desc += "Enables the periodic trigger capability for the triggered DMA channel." %define _DESC102_ \ desc += "Enables the DMA channel." %define _DESC103_ \ desc += "DSPI Module Configuration Register. The DSPI_MCR contains bits to configure\n"\ desc += "various attributes associated with DSPI operations. The HALT and MDIS bits can\n"\ desc += "be changed at any time, but they only take effect on the next frame boundary.\n"\ desc += "Only the HALT and MDIS bits in the MCR can be changed while the DSPI is in the\n"\ desc += "Running state." %define _DESC104_ \ desc += "Master/Slave Mode Select\n\n"\ desc += "Configures the DSPI for either master mode or slave mode." %define _DESC105_ \ desc += "Continuous SCK Enable\n\n"\ desc += "Enables the Serial Communication Clock (SCK) to run continuously." %define _DESC106_ \ desc += "DSPI Configuration\n\n"\ desc += "Selects among the different configurations of the DSPI." %define _DESC107_ \ desc += "Freeze\n\n"\ desc += "Enables the DSPI transfers to be stopped on the next frame boundary when the\n"\ desc += "device enters Debug mode." %define _DESC108_ \ desc += "Modified Timing Format Enable\n\n"\ desc += "Enables a modified transfer format to be used." %define _DESC109_ \ desc += "Peripheral Chip Select Strobe Enable\n\n"\ desc += "Enables the PCS[5]/ PCSS to operate as a PCS Strobe output signal." %define _DESC110_ \ desc += "Receive FIFO Overflow Overwrite Enable\n\n"\ desc += "In the RX FIFO overflow condition, configures the DSPI to ignore the incoming\n"\ desc += "serial data or overwrite existing data. If the RX FIFO is full and new data is\n"\ desc += "received, the data from the transfer, generating the overflow, is ignored or\n"\ desc += "shifted into the shift register." %define _DESC111_ \ desc += "Peripheral Chip Select x Inactive State\n\n"\ desc += "Determines the inactive state of PCSx when DSPI is in Master Mode. This field\n"\ desc += "has no effect when DSPI is in Slave Mode. The Slave Select input to DSPI in\n"\ desc += "slave mode is always Active Low." %define _DESC112_ \ desc += "Doze Enable\n\n"\ desc += "Provides support for an externally controlled Doze mode power-saving\n"\ desc += "mechanism." %define _DESC113_ \ desc += "Module Disable\n\n"\ desc += "Allows the clock to be stopped to the non-memory-mapped logic in the DSPI\n"\ desc += "effectively putting the DSPI in a software controlled power-saving state. The\n"\ desc += "reset value of the MDIS bit is parameterized, with a default reset value of \n"\ desc += ".\n\n"\ desc += "When DSPI is used in Slave Mode, it is recommended to leave this bit set to 0,\n"\ desc += "since a slave doesn't have control over master transactions." %define _DESC114_ \ desc += "Disable Transmit FIFO\n\n"\ desc += "When the TX FIFO is disabled, the transmit part of the DSPI (both TXFIFO and\n"\ desc += "CMD FIFO) operates as a simplified double-buffered SPI. This bit can only be\n"\ desc += "written when the MDIS bit is cleared." %define _DESC115_ \ desc += "Disable Receive FIFO\n\n"\ desc += "When the RX FIFO is disabled, the receive part of the DSPI operates as a\n"\ desc += "simplified double-buffered SPI. This bit can only be written when the MDIS bit\n"\ desc += "is cleared." %define _DESC116_ \ desc += "Clear TX FIFO\n\n"\ desc += "Flushes the TX FIFO and the CMD FIFO. Writing a '1' to CLR_TXF clears the TX\n"\ desc += "FIFO and CMD FIFO Counters. The CLR_TXF bit is always read as zero." %define _DESC117_ \ desc += "Flushes the RX FIFO. Writing a '1' to CLR_RXF clears the RX Counter. The\n"\ desc += "CLR_RXF bit is always read as zero." %define _DESC118_ \ desc += "Sample Point\n\n"\ desc += "Controls when the DSPI master samples SIN in Modified Transfer Format. This\n"\ desc += "field is valid only when CPHA bit in CTAR is 0." %define _DESC119_ \ desc += "Extended SPI Mode\n\n"\ desc += "This bit enables usage of CTARE (Command and Transfer Attribute Register\n"\ desc += "Extended) Registers.\n\n"\ desc += "CTARE registers allow the user to send up to 32-bit SPI frames. Command Cycling\n"\ desc += "is also enabled\n\n"\ desc += "which allows the user to send multiple Data Frames using a single Command\n"\ desc += "Frame.\n\n"\ desc += "When MCR[DIS_TXF] is asserted, the Extended SPI Mode cannot be used to transmit\n"\ desc += "SPI frames which are more than 16 bits in size." %define _DESC120_ \ desc += "Fast Continuous PCS Mode.\n\n"\ desc += "This bit enables the masking of 'After SCK (t ASC )' and 'PCS to SCK (t CSC )'\n"\ desc += "delays when operating in Continuous PCS mode. This masking is not available if\n"\ desc += "Continuous SCK mode is enabled. The individual delay masks are selected via\n"\ desc += "bits MASC and MCSC of the PUSHR. The firmware should select appropriate masks\n"\ desc += "when providing continuous frames via the PUSHR." %define _DESC121_ \ desc += "Parity Error Stop\n\n"\ desc += "Controls SPI operation when a parity error is detected in a received SPI\n"\ desc += "frame." %define _DESC122_ \ desc += "Halt\n\n"\ desc += "Starts and stops DSPI transfers." %define _DESC123_ \ desc += "DSPI Transfer Count Register. The DSPI_TCR contains a counter that indicates\n"\ desc += "the number of SPI transfers made. The transfer counter is intended to assist in\n"\ desc += "queue management. Do not write the TCR when the DSPI is in the Running state." %define _DESC124_ \ desc += "SPI Transfer Counter\n\n"\ desc += "Counts the number of SPI transfers the DSPI makes. The SPI_TCNT field\n"\ desc += "increments every time the last bit of a SPI frame is transmitted. A value\n"\ desc += "written to SPI_TCNT presets the counter to that value. SPI_TCNT is reset to\n"\ desc += "zero at the beginning of the frame when the CTCNT field is set in the executing\n"\ desc += "SPI command. The Transfer Counter wraps around; incrementing the counter past\n"\ desc += "65535 resets the counter to zero." %define _DESC125_ \ desc += "DSPI Clock and Transfer Attributes Register 0 in Master Mode. CTARs are used to\n"\ desc += "define different transfer attributes. Do not write to the CTARs while the DSPI\n"\ desc += "is in the Running state.\n\n"\ desc += "In master mode, the CTARs define combinations of transfer attributes such as\n"\ desc += "frame size, clock phase and polarity, data bit ordering, baud rate, and various\n"\ desc += "delays. In slave mode, a subset of the bitfields in CTAR0 and CTAR1 are used to\n"\ desc += "set the slave transfer attributes.\n\n"\ desc += "When the DSPI is configured as an SPI master, the CTAS field in the command\n"\ desc += "portion of the TX FIFO entry selects which of the CTARs is used. When the DSPI\n"\ desc += "is configured as an SPI bus slave, the CTAR0 register is used.\n\n"\ desc += "When the DSPI is configured as a DSI master, the DSICTAS field in the DSPI DSI\n"\ desc += "Configuration Register 0 (DSICR0), selects which of the CTARs is used. When the\n"\ desc += "DSPI is configured as a DSI bus slave, the CTAR1 register is used.\n\n"\ desc += "In CSI Configuration, the transfer attributes are selected based on whether the\n"\ desc += "current frame is SPI data or DSI data. SPI transfers in CSI Configuration\n"\ desc += "follow the protocol described for SPI Configuration, and DSI transfers in CSI\n"\ desc += "Configuration follow the protocol described for DSI Configuration. CSI\n"\ desc += "Configuration is valid only in conjunction with master mode.\n\n"\ desc += "TSB mode sets some limitations on transfer attributes:\n\n"\ desc += "Clock phase is forced to be CPHA = 1 and the CPHA bit setting has no effect. \n"\ desc += "PCS lines are driven at the driving edge of the SCK clock together with SOUT,\n"\ desc += "so PCS assertion and negation delays control is unavailable and PCSSCK, PASC,\n"\ desc += "CSSCK and ASC fields have no effect. Delay after transfer can be set from 1 to\n"\ desc += "64 serial clocks with help of PDT and DT fields [DSPI SCK duty cycle]:\n"\ desc += " DBR CPHA PBR SCK duty cycle\n"\ desc += " --- ---- --- --------------\n"\ desc += " 0 any any 50/50\n"\ desc += " 1 0 00 50/50\n"\ desc += " 1 0 01 33/66\n"\ desc += " 1 0 10 40/60\n"\ desc += " 1 0 11 43/57\n"\ desc += " 1 1 00 50/50\n"\ desc += " 1 1 01 66/33\n"\ desc += " 1 1 10 60/40\n"\ desc += " 1 1 11 57/43\n"\ desc += "[Delay scaler encoding]:\n"\ desc += " Field value Delay scaler value\n"\ desc += " ----------- ------------------\n"\ desc += " 0000 2\n"\ desc += " 0001 4\n"\ desc += " 0010 8\n"\ desc += " 0011 16\n"\ desc += " 0100 32\n"\ desc += " 0101 64\n"\ desc += " 0110 128\n"\ desc += " 0111 256\n"\ desc += " 1000 512\n"\ desc += " 1001 1024\n"\ desc += " 1010 2048\n"\ desc += " 1011 4096\n"\ desc += " 1100 8192\n"\ desc += " 1101 16384\n"\ desc += " 1110 32768\n"\ desc += " 1111 65536\n"\ desc += "[DSPI baud rate scaler]:\n"\ desc += " CTARn[BR] Baud rate scaler value\n"\ desc += " --------- ----------------------\n"\ desc += " 0000 2\n"\ desc += " 0001 4\n"\ desc += " 0010 6\n"\ desc += " 0011 8\n"\ desc += " 0100 16\n"\ desc += " 0101 32\n"\ desc += " 0110 64\n"\ desc += " 0111 128\n"\ desc += " 1000 256\n"\ desc += " 1001 512\n"\ desc += " 1010 1024\n"\ desc += " 1011 2048\n"\ desc += " 1100 4096\n"\ desc += " 1101 8192\n"\ desc += " 1110 16384\n"\ desc += " 1111 32768\n" %define _DESC126_ \ desc += "Double Baud Rate\n\n"\ desc += "Doubles the effective baud rate of the Serial Communications Clock (SCK). This\n"\ desc += "field is used only in master mode. It effectively halves the Baud Rate division\n"\ desc += "ratio, supporting faster frequencies, and odd division ratios for the Serial\n"\ desc += "Communications Clock (SCK). When the DBR bit is set, the duty cycle of the\n"\ desc += "Serial Communications Clock (SCK) depends on the value in the Baud Rate\n"\ desc += "Prescaler and the Clock Phase bit as listed in\n"\ desc += "#id_dspi_sck_duty_cycle_2013-01-25_1716 . See the BR field description for\n"\ desc += "details on how to compute the baud rate. Refer to\n"\ desc += "#id_dspi_sck_duty_cycle_2013-01-25_1716 for DSPI SCK duty cycle values." %define _DESC127_ \ desc += "Frame Size\n\n"\ desc += "The number of bits transferred per frame is equal to the FMSZ field value plus\n"\ desc += "1. The minimum valid FMSZ field value is 3.\n\n"\ desc += "There is a constraint on the minimum allowable Frame size, which depends on the\n"\ desc += "Register Read/Write clock to the Protocol Clock Ratio. The minimum Frame size\n"\ desc += "(FMSZ + 1) is decided by the following equation. Upper Ceiling must be applied\n"\ desc += "for non-integer values.\n\n"\ desc += "Min. Frame Size = ((4 x fp) + (3 x fr)) / (n x fr)\n\n"\ desc += "fp = Protocol Clock Frequency\n\n"\ desc += "fr = Register Read/Write Clock Frequency\n\n"\ desc += "n = Multiple of protocol clock required to get Baud Clock - Given by (PBR x BR)\n"\ desc += "/ (1 + DBR)\n\n"\ desc += "However, the minimum frame size can never be less than 4. There is no\n"\ desc += "constraint on the maximum programmable frame size. Note that 'fp' can be equal\n"\ desc += "to, less than or greater than 'fr' purely based on user requirement.\n\n"\ desc += "When the DSPI operates in TSB mode, the FMSZ field value plus 1 is equal to the\n"\ desc += "data frame bit number, where control of the PCS assertion switches from the\n"\ desc += "DSICR0 to the DSICR1 register. If TSB Mode is operated when DSI is used in 64\n"\ desc += "bit mode, then DSICR0[FMSZ4] also comes into picture while switching PCS\n"\ desc += "assertion control." %define _DESC128_ \ desc += "Clock Polarity\n\n"\ desc += "Selects the inactive state of the Serial Communications Clock (SCK). This bit\n"\ desc += "is used in both master and slave mode. For successful communication between\n"\ desc += "serial devices, the devices must have identical clock polarities. When the\n"\ desc += "Continuous Selection Format is selected, switching between clock polarities\n"\ desc += "without stopping the DSPI can cause errors in the transfer due to the\n"\ desc += "peripheral device interpreting the switch of clock polarity as a valid clock\n"\ desc += "edge." %define _DESC129_ \ desc += "Clock Phase or TSB mode\n\n"\ desc += "Selects which edge of SCK causes data to change and which edge causes data to\n"\ desc += "be captured. This bit is used in both master and slave mode. For successful\n"\ desc += "communication between serial devices, the devices must have identical clock\n"\ desc += "phase settings. In Continuous SCK mode or TSB mode, the bit value is ignored\n"\ desc += "and the transfers are done as if the CPHA bit is set to 1." %define _DESC130_ \ desc += "LSB First\n\n"\ desc += "Specifies whether the LSB or MSB of the frame is transferred first. When the\n"\ desc += "DSPI operates in TSB configuration, this bit should be set to be compliant to\n"\ desc += "the MSC specification." %define _DESC131_ \ desc += "PCS to SCK Delay Prescaler\n\n"\ desc += "Selects the prescaler value for the delay between assertion of PCS and the\n"\ desc += "first edge of the SCK. See the CSSCK field description for information on how\n"\ desc += "to compute the PCS to SCK Delay. Refer to the 'PCS to SCK delay (t CSC )'\n"\ desc += "section for more details.\n\n"\ desc += "In the TSB mode, the PCSSCK field has no effect." %define _DESC132_ \ desc += "After SCK Delay Prescaler\n\n"\ desc += "Selects the prescaler value for the delay between the last edge of SCK and the\n"\ desc += "negation of PCS. See the ASC field description for information on how to\n"\ desc += "compute the After SCK Delay.\n\n"\ desc += "In the TSB mode, the PASC field has no effect. Refer to the 'After SCK delay (t\n"\ desc += "ASC )' section for more details." %define _DESC133_ \ desc += "Delay after Transfer Prescaler\n\n"\ desc += "Selects the prescaler value for the delay between the negation of the PCS\n"\ desc += "signal at the end of a frame and the assertion of PCS at the beginning of the\n"\ desc += "next frame. The PDT field is only used in master mode.\n\n"\ desc += "In the TSB mode the PDT field defines two MSB bits of the Delay after\n"\ desc += "Transfer.\n\n"\ desc += "See the DT field description for details on how to compute the Delay after\n"\ desc += "Transfer. Refer to the 'Delay after transfer (t DT )' section for more\n"\ desc += "details." %define _DESC134_ \ desc += "Baud Rate Prescaler\n\n"\ desc += "Selects the prescaler value for the baud rate. This field is used only in\n"\ desc += "master mode. The baud rate is the frequency of the SCK. The protocol clock is\n"\ desc += "divided by the prescaler value before the baud rate selection takes place. See\n"\ desc += "the BR field description for details on how to compute the baud rate." %define _DESC135_ \ desc += "PCS to SCK Delay Scaler\n\n"\ desc += "Selects the scaler value for the PCS to SCK delay. This field is used only in\n"\ desc += "master mode.\n\n"\ desc += "In the TSB mode the field has no effect.\n\n"\ desc += "The PCS to SCK Delay is the delay between the assertion of PCS and the first\n"\ desc += "edge of the SCK. The delay is a multiple of the protocol clock period, and it\n"\ desc += "is computed according to the following equation:\n\n"\ desc += "t CSC = (1/f P ) x PCSSCK x CSSCK\n\n"\ desc += "#id_delay_scaler_encoding_2013-01-25_1719 lists the delay scaler values. Refer\n"\ desc += "to the 'PCS to SCK delay (t CSC )' section for more details." %define _DESC136_ \ desc += "After SCK Delay Scaler\n\n"\ desc += "Selects the scaler value for the After SCK Delay. This field is used only in\n"\ desc += "master mode. The After SCK Delay is the delay between the last edge of SCK and\n"\ desc += "the negation of PCS. The delay is a multiple of the protocol clock period, and\n"\ desc += "it is computed according to the following equation:\n\n"\ desc += "t ASC = (1/f P ) x PASC x ASC\n\n"\ desc += "See Delay Scaler Encoding table in CTARn[CSSCK] bit field description for\n"\ desc += "scaler values. Refer to the 'After SCK delay (t ASC )' section for more\n"\ desc += "details." %define _DESC137_ \ desc += "Delay After Transfer Scaler\n\n"\ desc += "Selects the Delay after Transfer Scaler. This field is used only in master\n"\ desc += "mode. The Delay after Transfer is the time between the negation of the PCS\n"\ desc += "signal at the end of a frame and the assertion of PCS at the beginning of the\n"\ desc += "next frame.\n\n"\ desc += "In the Continuous Serial Communications Clock operation, the DT value is fixed\n"\ desc += "to one SCK clock period, The Delay after Transfer is a multiple of the protocol\n"\ desc += "clock period, and it is computed according to the following equation:\n\n"\ desc += "t DT = (1/f P ) x PDT x DT\n\n"\ desc += "See Delay Scaler Encoding table in CTARn[CSSCK] bit field description for\n"\ desc += "scaler values.\n\n"\ desc += "In the TSB mode, the Delay after Transfer is equal to a number formed by\n"\ desc += "concatenation of the PDT and DT fields plus 1 of the SCK clock periods. Refer\n"\ desc += "to the 'PCS to SCK delay (t CSC )' section for more details." %define _DESC138_ \ desc += "Baud Rate Scaler\n\n"\ desc += "Selects the scaler value for the baud rate. This field is used only in master\n"\ desc += "mode. The prescaled protocol clock is divided by the Baud Rate Scaler to\n"\ desc += "generate the frequency of the SCK. The baud rate is computed according to\n"\ desc += "the following equation:\n\n"\ desc += "SCK baud rate = (f P /PBR) x [(1+DBR)/BR]\n\n"\ desc += "#id_dspi_baud_rate_scaler_2013-01-25_1722 lists the baud rate scaler values." %define _DESC139_ \ desc += "DSPI Clock and Transfer Attributes Register 0 in Slave Mode. When the DSPI is\n"\ desc += "configured as an SPI bus slave, the CTAR0 register is used.\n\n"\ desc += "When the DSPI is configured as a DSI master, the DSICTAS field in the DSPI DSI\n"\ desc += "Configuration Register 0 (DSICR0), selects which of the CTARs is used. When the\n"\ desc += "DSPI is configured as a DSI bus slave, the CTAR1 register is used.\n\n"\ desc += "In CSI Configuration, the transfer attributes are selected based on whether the\n"\ desc += "current frame is SPI data or DSI data. SPI transfers in CSI Configuration\n"\ desc += "follow the protocol described for SPI Configuration, and DSI transfers in CSI\n"\ desc += "Configuration follow the protocol described for DSI Configuration. CSI\n"\ desc += "Configuration is valid only in conjunction with master mode.\n\n"\ desc += "TSB mode sets some limitations on transfer attributes:\n\n"\ desc += "Clock phase is forced to be CPHA = 1 and the CPHA bit setting has no effect. \n"\ desc += "PCS lines are driven at the driving edge of the SCK clock together with SOUT,\n"\ desc += "so PCS assertion and negation delays control is unavailable and PCSSCK, PASC,\n"\ desc += "CSSCK and ASC fields have no effect. Delay after transfer can be set from 1 to\n"\ desc += "64 serial clocks with help of PDT and DT fields." %define _DESC140_ \ desc += "Frame Size\n\n"\ desc += "The number of bits transferred per frame is equal to the concatenated field\n"\ desc += "{CTARn_SLAVE[FMSZ5], CTARn_SLAVE[FMSZ]} value plus 1. The minimum valid FMSZ\n"\ desc += "field value is 3 (when FMSZ6 is 0)." %define _DESC141_ \ desc += "Clock Polarity\n\n"\ desc += "Selects the inactive state of the Serial Communications Clock (SCK)." %define _DESC142_ \ desc += "Clock Phase or TSB mode\n\n"\ desc += "Selects which edge of SCK causes data to change and which edge causes data to\n"\ desc += "be captured. This bit is used in both master and slave mode. For successful\n"\ desc += "communication between serial devices, the devices must have identical clock\n"\ desc += "phase settings. In Continuous SCK mode or TSB mode, the bit value is ignored\n"\ desc += "and the transfers are done as the CPHA bit is set to 1." %define _DESC143_ \ desc += "Parity Enable\n\n"\ desc += "Enables parity bit transmission and reception for the frame." %define _DESC144_ \ desc += "Parity Polarity\n\n"\ desc += "Controls polarity of the parity bit transmitted and checked." %define _DESC145_ \ desc += "MSB of Frame Size when DSI is used in 64-bit Mode\n\n"\ desc += "The number of bits transferred per frame is equal to the concatenated field\n"\ desc += "{CTARn_SLAVE[FMSZ5], CTARn_SLAVE[FMSZ]} value plus 1." %define _DESC146_ \ desc += "DSPI Status Register. SR contains status and flag bits. The bits reflect the\n"\ desc += "status of the DSPI and indicate the occurrence of events that can generate\n"\ desc += "interrupt or DMA requests. Software can clear most of the flag bits in the SR\n"\ desc += "by writing a '1' to them. Writing a 0 to a flag bit has no effect. This\n"\ desc += "register may not be writable in module disable mode due to the use of power\n"\ desc += "saving mechanisms." %define _DESC147_ \ desc += "Transfer Complete Flag\n\n"\ desc += "Indicates that all bits in a frame have been shifted out. TCF remains set\n"\ desc += "until it is cleared by writing a '1' to it." %define _DESC148_ \ desc += "TX and RX Status\n\n"\ desc += "Reflects the run status of the DSPI." %define _DESC149_ \ desc += "SPI Frame Transfer Complete Flag.\n\n"\ desc += "This bit functions similar to TCF except that this bit is asserted only on SPI\n"\ desc += "frame transmission completion in CSI Mode. This includes the ITSB Mode and\n"\ desc += "'TSB in CSI' Mode as well. This flag will not be asserted when DSPI is used in\n"\ desc += "SPI or DSI Modes." %define _DESC150_ \ desc += "End of Queue Flag\n\n"\ desc += "Indicates that the last entry in a queue has been transmitted when the DSPI is\n"\ desc += "in master mode. The EOQF bit is set when the TX FIFO entry has the EOQ bit set\n"\ desc += "in the command halfword and the end of the transfer is reached. The EOQF bit\n"\ desc += "remains set until cleared by writing a '1' to it. When the EOQF bit is set, the\n"\ desc += "TXRXS bit is automatically cleared." %define _DESC151_ \ desc += "Transmit FIFO Underflow Flag\n\n"\ desc += "Indicates an underflow condition in the TX FIFO. The transmit underflow\n"\ desc += "condition is detected only for DSPI blocks operating in slave mode and SPI\n"\ desc += "configuration. TFUF is set when the TX FIFO of a DSPI operating in SPI slave\n"\ desc += "mode is empty and an external SPI master initiates a transfer. The TFUF bit\n"\ desc += "remains set until cleared by writing '1' to it." %define _DESC152_ \ desc += "DSI Frame Transfer Complete Flag.\n\n"\ desc += "This bit functions similar to TCF except that this bit is asserted only on DSI\n"\ desc += "frame transmission completion in CSI Mode. This includes the ITSB Mode and\n"\ desc += "'TSB in CSI' Mode as well. This flag will not be asserted when DSPI is used in\n"\ desc += "SPI or DSI Modes." %define _DESC153_ \ desc += "Transmit FIFO Fill Flag\n\n"\ desc += "Provides a method for the DSPI to request more entries to be added to the TX\n"\ desc += "FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be\n"\ desc += "cleared by writing '1' to it or by acknowledgement from the DMA controller to\n"\ desc += "the TX FIFO full request." %define _DESC154_ \ desc += "Busy Flag\n\n"\ desc += "This bit is valid only when DSPI_MCR[XSPI] is enabled.\n\n"\ desc += "Indicates that the current Command Frame is being used for transmitting\n"\ desc += "multiple data frames. This bit is not set for the last Data Frame of a Cyclic\n"\ desc += "command Transfer or when DSPI_CTARE[DTCP] = 1. Refer to the 'Command First In\n"\ desc += "First Out (CMD FIFO) buffering mechanism' section for more details." %define _DESC155_ \ desc += "Command Transfer Complete Flag\n\n"\ desc += "Indicates that the last Data frame for the current Cyclic Command has been\n"\ desc += "transmitted. Hence this bit is set only for the last Data Frame of a Cyclic\n"\ desc += "Command Transfer or when DSPI_CTARE[DTCP] = 1.\n\n"\ desc += "CMDTCF remains set until it is cleared by writing a '1' to it." %define _DESC156_ \ desc += "DSI Parity Error Flag\n\n"\ desc += "Indicates that a DSI frame with parity error had been received. The bit remains\n"\ desc += "set until it is cleared by writing a '1' to it." %define _DESC157_ \ desc += "SPI Parity Error Flag\n\n"\ desc += "Indicates that a SPI frame with parity error had been received. The bit remains\n"\ desc += "set until it is cleared by writing a '1' to it." %define _DESC158_ \ desc += "DSI Data Received with Active Bits\n\n"\ desc += "Indicates that a DSI frame had been received with bits selected by DIMR with\n"\ desc += "active polarity, defined by the DPIR. The bit remains set until it is cleared\n"\ desc += "by writing a '1' to it." %define _DESC159_ \ desc += "Receive FIFO Overflow Flag\n\n"\ desc += "Indicates an overflow condition in the RX FIFO. The bit is set when the RX FIFO\n"\ desc += "and shift register are full and a transfer is initiated. The bit remains set\n"\ desc += "until it is cleared by writing a '1' to it." %define _DESC160_ \ desc += "Transmit FIFO Invalid Write Flag\n\n"\ desc += "Indicates Data Write on TX FIFO while CMD FIFO is empty. Without a Command, the\n"\ desc += "Data entries present in TXFIFO are invalid." %define _DESC161_ \ desc += "Receive FIFO Drain Flag\n\n"\ desc += "Provides a method for the DSPI to request that entries be removed from the RX\n"\ desc += "FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be\n"\ desc += "cleared by writing 1 to it or by acknowledgement from the DMA controller when\n"\ desc += "the RX FIFO is empty." %define _DESC162_ \ desc += "Command FIFO Fill Flag\n\n"\ desc += "Provides a method for the DSPI to request more entries to be added to the CMD\n"\ desc += "FIFO. The CMDFFF bit is set while the CMD FIFO is not full. The CMDFFF is\n"\ desc += "cleared by writing a '1' to it or by acknowledgement from the DMA controller to\n"\ desc += "the CMD FIFO full request." %define _DESC163_ \ desc += "TX FIFO Counter\n\n"\ desc += "Indicates the number of valid entries in the TX FIFO. The TXCTR is incremented\n"\ desc += "every time the data part of PUSHR is written. The TXCTR is decremented every\n"\ desc += "time the SPI data is transferred to the shift register." %define _DESC164_ \ desc += "Transmit Next Pointer\n\n"\ desc += "Indicates which TX FIFO Entry is transmitted during the next transfer. The\n"\ desc += "TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO\n"\ desc += "to the shift register." %define _DESC165_ \ desc += "RX FIFO Counter\n\n"\ desc += "Indicates the number of entries in the RX FIFO. The RXCTR is decremented every\n"\ desc += "time the POPR is read. The RXCTR is incremented every time data is transferred\n"\ desc += "from the shift register to the RX FIFO." %define _DESC166_ \ desc += "Pop Next Pointer\n\n"\ desc += "Contains a pointer to the RX FIFO entry to be returned when the POPR is read.\n"\ desc += "The POPNXTPTR is updated when the POPR is read." %define _DESC167_ \ desc += "DSPI DMA/Interrupt Request Select and Enable Register. The DSPI_RSER controls\n"\ desc += "DMA and interrupt requests. Do not write to the RSER while the DSPI is in the\n"\ desc += "Running state." %define _DESC168_ \ desc += "Transmission Complete Request Enable\n\n"\ desc += "Enables TCF flag in the SR to generate an interrupt request." %define _DESC169_ \ desc += "Command FIFO Fill Flag Request Enable\n\n"\ desc += "Enables the CMDFFF flag in the SR to generate a request. The CMDFFF_DIRS bit\n"\ desc += "selects between generating an interrupt request or a DMA request." %define _DESC170_ \ desc += "SPI Frame Transmission Complete Request Enable.\n\n"\ desc += "The SPITCF_RE bit enables SPITCF flag in the SR to generate an interrupt\n"\ desc += "request." %define _DESC171_ \ desc += "DSPI Finished Request Enable\n\n"\ desc += "Enables the EOQF flag in the SR to generate an interrupt request." %define _DESC172_ \ desc += "Transmit FIFO Underflow Request Enable\n\n"\ desc += "Enables the TFUF flag in the SR to generate an interrupt request." %define _DESC173_ \ desc += "DSI Frame Transmission Complete Request Enable.\n\n"\ desc += "The DSITCF_RE bit enables DSITCF flag in the SR to generate an interrupt\n"\ desc += "request." %define _DESC174_ \ desc += "Transmit FIFO Fill Request Enable\n\n"\ desc += "Enables the TFFF flag in the SR to generate a request. The TFFF_DIRS bit\n"\ desc += "selects between generating an interrupt request or a DMA request." %define _DESC175_ \ desc += "Transmit FIFO Fill DMA or Interrupt Request Select\n\n"\ desc += "Selects between generating a DMA request or an interrupt request. When the\n"\ desc += "TFFF flag bit in the SR is set and the TFFF_RE bit in the RSER is set, this bit\n"\ desc += "selects between generating an interrupt request or a DMA request." %define _DESC176_ \ desc += "Command Transmission Complete Request Enable.\n\n"\ desc += "The CMDTCF_RE bit enables CMDTCF flag in the SR to generate an interrupt\n"\ desc += "request." %define _DESC177_ \ desc += "DSI Parity Error Request Enable\n\n"\ desc += "Enables the DPEF flag in the SR to generate an interrupt request." %define _DESC178_ \ desc += "SPI Parity Error Request Enable\n\n"\ desc += "Enables the SPEF flag in the SR to generate an interrupt request." %define _DESC179_ \ desc += "DSI data received with active bits Request Enable\n\n"\ desc += "Enables the DDIF flag in the SR to generate an interrupt requests." %define _DESC180_ \ desc += "Receive FIFO Overflow Request Enable\n\n"\ desc += "Enables the RFOF flag in the SR to generate an interrupt request." %define _DESC181_ \ desc += "Transmit FIFO Invalid Write Request Enable\n\n"\ desc += "Enables the TFIWF flag in the SR to generate an interrupt request." %define _DESC182_ \ desc += "Receive FIFO Drain Request Enable\n\n"\ desc += "Enables the RFDF flag in the SR to generate a request. The RFDF_DIRS bit\n"\ desc += "selects between generating an interrupt request or a DMA request." %define _DESC183_ \ desc += "Receive FIFO Drain DMA or Interrupt Request Select.\n\n"\ desc += "Selects between generating a DMA request or an interrupt request. When the\n"\ desc += "RFDF flag bit in the SR is set, and the RFDF_RE bit in the RSER is set, the\n"\ desc += "RFDF_DIRS bit selects between generating an interrupt request or a DMA\n"\ desc += "request." %define _DESC184_ \ desc += "Command FIFO FIll DMA or Interrupt Request Select.\n\n"\ desc += "Selects between generating a DMA request or an interrupt request. When the\n"\ desc += "CMDFFF flag bit in the SR is set, and the CMDFFF_RE bit in the RSER is set, the\n"\ desc += "CMDFFF_DIRS bit selects between generating an interrupt request or a DMA\n"\ desc += "request." %define _DESC185_ \ desc += "DSI data received with active bits - DMA or Interrupt Request Select.\n\n"\ desc += "Selects between generating a DMA request or an interrupt request. When the DDIF\n"\ desc += "flag bit in the SR is set, and the DDIF_RE bit in the RSER is set, the\n"\ desc += "DDIF_DIRS bit selects between generating an interrupt request or a DMA\n"\ desc += "request." %define _DESC186_ \ desc += "DSPI PUSH FIFO Register in Master Mode. PUSHR provides the means to write to\n"\ desc += "the TX FIFO and CMD FIFO. Data written to this register is transferred to the\n"\ desc += "TX FIFO and/or CMD FIFO. Eight- or sixteen-bit write accesses to the Data Field\n"\ desc += "of PUSHR transfers the 16-bit Data field of PUSHR to the TX FIFO. Write\n"\ desc += "accesses to the Command Field of PUSHR transfers the 16-bit Command Field of\n"\ desc += "PUSHR to the CMD FIFO. The register structure is different in master and slave\n"\ desc += "modes. In master mode, the register provides 16-bit command to the CMD FIFO and\n"\ desc += "16-bit data to the TX FIFO. In slave mode, CMD FIFO is unused and hence the\n"\ desc += "16-bit Command Field of PUSHR is reserved.\n\n"\ desc += "Unless Extended SPI Mode is being used, the TX FIFO and CMD FIFO must be filled\n"\ desc += "simultaneously. In other words, write accesses must be given to both Data and\n"\ desc += "Command fields of PUSHR for every PUSHR operation performed when MCR[XSPI] is\n"\ desc += "0. When Extended SPI Mode is disabled, since both TX FIFO and CMD FIFO are\n"\ desc += "written to and read from simultaneously, they can be thought of as a single\n"\ desc += "32-bit FIFO.\n\n"\ desc += "When Extended SPI Mode is enabled, TX FIFO and CMD FIFO can be written\n"\ desc += "independently. A PUSHR Read Operation returns the topmost TX FIFO and CMD FIFO\n"\ desc += "entries concatenated.\n\n"\ desc += "When DSPI Module is disabled, any writes to this register will not update the\n"\ desc += "FIFO. Hence any reads performed during Module disable mode will return the last\n"\ desc += "PUSHR write performed when Module was enabled." %define _DESC187_ \ desc += "Continuous Peripheral Chip Select Enable\n\n"\ desc += "Selects a Continuous Selection Format. The bit is used in SPI master mode. The\n"\ desc += "bit enables the selected PCS signals to remain asserted between transfers.\n"\ desc += "PUSHR[EOQ] and PUSHR[CONT] bits cannot be asserted together in any Command\n"\ desc += "Frame, since EOQ signifies the last frame in a queue and the Last frame in a\n"\ desc += "Continuous Transfer must have PUSHR[CONT] as 0." %define _DESC188_ \ desc += "Clock and Transfer Attributes Select.\n\n"\ desc += "Selects which CTAR (and corresponding CTARE register) to use in master mode to\n"\ desc += "specify the transfer attributes for the associated SPI frame. In SPI slave\n"\ desc += "mode, CTAR0 is used. See the Chip Configuration chapter to determine how many\n"\ desc += "CTARs this device has. You should not program a value in this field for a\n"\ desc += "register that is not present." %define _DESC189_ \ desc += "End Of Queue\n\n"\ desc += "Host software uses this bit to signal to the DSPI that the current SPI transfer\n"\ desc += "is the last in a queue. At the end of the transfer, the EOQF bit in the SR is\n"\ desc += "set." %define _DESC190_ \ desc += "Clear Transfer Counter.\n\n"\ desc += "Clears the SPI_TCNT field in the TCR. The SPI_TCNT field is cleared before the\n"\ desc += "DSPI starts transmitting the current SPI frame. Hence the current SPI frame\n"\ desc += "will cause this counter to increment by 1." %define _DESC191_ \ desc += "Parity Enable or Mask t ASC delay in the current frame\n\n"\ desc += "PE - This bit enables parity bit transmission and parity reception check for\n"\ desc += "the SPI frame.\n\n"\ desc += "MASC - The current frame has the 'after SCK' delay masked if this bit is\n"\ desc += "asserted. See the 'Fast Continuous Selection Format' section for more\n"\ desc += "details.\n\n"\ desc += "This bit is used as Mask t ASC in the Fast Continuous PCS mode when MCR[FCPCS]\n"\ desc += "is set." %define _DESC192_ \ desc += "Parity Polarity or Mask t CSC delay in the next frame\n\n"\ desc += "PP - It controls the polarity of the parity bit transmitted and checked.\n\n"\ desc += "MCSC - The next frame has the 'PCS to SCK' delay masked if this bit is\n"\ desc += "asserted. See the 'Fast Continuous Selection Format' section for more\n"\ desc += "details.\n\n"\ desc += "This bit is used as Mask t CSC in the Fast Continuous PCS mode when MCR[FCPCS]\n"\ desc += "is set." %define _DESC193_ \ desc += "Select which PCS signals are to be asserted for the transfer. Refer to the chip\n"\ desc += "configuration chapter for the number of PCS signals used in this MCU." %define _DESC194_ \ desc += "Transmit Data\n\n"\ desc += "Holds SPI data to be transferred according to the associated SPI command." %define _DESC195_ \ desc += "DSPI PUSH FIFO Register in Slave Mode. PUSHR provides the means to write to the\n"\ desc += "TX FIFO. Data written to this register is transferred to the TX FIFO. Eight or\n"\ desc += "16-bit write accesses to the Data Field of PUSHR transfers the 16-bit Data\n"\ desc += "Field of PUSHR to the TX FIFO. The register structure is different in master\n"\ desc += "and slave modes. In master mode, the register provides 16-bit command to the\n"\ desc += "CMD FIFO and 16-bit data to the TX FIFO. In slave mode, CMD FIFO is unused and\n"\ desc += "hence the 16-bit Command Field of PUSHR is reserved.\n\n"\ desc += "In Slave mode, up to 32-bit SPI frames may be queued for transmission/reception\n"\ desc += "by enabling MCR[XSPI] mode." %define _DESC196_ \ desc += "Transmit Data\n\n"\ desc += "Holds SPI data to be transferred." %define _DESC197_ \ desc += "DSPI POP FIFO Register. POPR is used to read the RX FIFO. Eight- or sixteen-bit\n"\ desc += "read accesses to the POPR have the same effect on the RX FIFO as 32-bit read\n"\ desc += "accesses. A write to this register will generate a Transfer Error." %define _DESC198_ \ desc += "Received Data\n\n"\ desc += "Contains the SPI data from the RX FIFO entry to which the Pop Next Data Pointer\n"\ desc += "points." %define _DESC199_ \ desc += "DSPI Transmit FIFO Register 0. TXFRn provide visibility into the TX FIFO for\n"\ desc += "debugging purposes. Each register is an entry in the TX FIFO. The registers are\n"\ desc += "read-only and cannot be modified. Reading the TXFRn registers does not alter\n"\ desc += "the state of the TX FIFO. Reading DSPI_TXFRn registers is invalid for a DSPI\n"\ desc += "Master when being used in the Extended SPI (XSPI) Mode." %define _DESC200_ \ desc += "Transmit Command or Transmit Data\n\n"\ desc += "In master mode, the TXCMD field contains the command that sets the transfer\n"\ desc += "attributes for the SPI data. In slave mode, the TXDATA contains 16 MSB bits of\n"\ desc += "the SPI data to be shifted out." %define _DESC201_ \ desc += "Transmit Data\n\n"\ desc += "Contains the SPI data to be shifted out." %define _DESC202_ \ desc += "DSPI Receive FIFO Register 0. RXFRn provide visibility into the RX FIFO for\n"\ desc += "debugging purposes. Each register is an entry in the RX FIFO. The RXFRs are\n"\ desc += "read-only. Reading the RXFRn registers does not alter the state of the RX FIFO.\n"\ desc += "The field MCR[MDIS] must be 0 when RXFR is read." %define _DESC203_ \ desc += "Receive Data\n\n"\ desc += "Contains the received SPI data." %define _DESC204_ \ desc += "DSPI DSI Configuration Register 0. DSICR0 selects various attributes associated\n"\ desc += "with DSI and CSI Configurations. Do not write to the DSICR0 while the DSPI is\n"\ desc += "in the Running state." %define _DESC205_ \ desc += "MSB of the frame size in master mode when DSI is used in 32-bit mode.\n\n"\ desc += "If the bit is set, 16 is added to the frame size, as defined by the CTARn[FMSZ]\n"\ desc += "field. The CTARx register is selected by the DSICTAS field." %define _DESC206_ \ desc += "MSB of the frame size in master mode when DSI is used in 64-bit mode.\n\n"\ desc += "If the bit is set, 32 is added to the frame size, as defined by the\n"\ desc += "concatenation of {DSICR0[FMSZ4], CTARn[FMSZ]} fields. The CTARx register is\n"\ desc += "selected by the DSICTAS field. Hence the final concatenated frame size using\n"\ desc += "this bit would be {DSICR0[FMSZ5], DSICR0[FMSZ4], CTARn[FMSZ]}.\n\n"\ desc += "This field is only valid when DSICR1[DSI64] is enabled." %define _DESC207_ \ desc += "Interleaved TSB mode.\n\n"\ desc += "This bit enables the Interleaved TSB mode of operation. When enabled, there is\n"\ desc += "no priority among frames from the SPI/DSI. DSI frames are always sent when\n"\ desc += "either the previous transmission was a SPI frame or if the TX_FIFO is empty.\n"\ desc += "Frames are transmitted on every trigger whose source is selected by the TRG bit\n"\ desc += "setting. The ITSB mode requires the DSICR0[TSBC] bit to be set and should be\n"\ desc += "written only when MCR[HALT] bit is asserted. If ITSB bit is set without setting\n"\ desc += "DSICR0[TSBC], then the DSPI operates in the Normal Mode depending on MCR[DCONF]\n"\ desc += "bit.\n\n"\ desc += "See Section 48.4.10, Interleaved TSB (ITSB) Mode for more details." %define _DESC208_ \ desc += "Timed Serial Bus Configuration.\n\n"\ desc += "Enables the Timed Serial Bus Configuration, which allows up to 64-bit data to\n"\ desc += "be used. It also allows t DT to be programmable." %define _DESC209_ \ desc += "Transmit Data Source Select.\n\n"\ desc += "Selects the source of data to be serialized. The source can be either data from\n"\ desc += "host software written to the DSPI DSI Alternate Serialization Data Register\n"\ desc += "(ASDR1/0) or parallel input pin states latched into the DSPI DSI Serialization\n"\ desc += "Data Register (SDR1/0)." %define _DESC210_ \ desc += "Trigger Polarity\n\n"\ desc += "Selects the active edge of the hardware trigger input signal (HT), initiating\n"\ desc += "DSI frames transfer." %define _DESC211_ \ desc += "Trigger Reception Enable\n\n"\ desc += "Enables the DSPI to initiate a DSI frames transfer with an external trigger\n"\ desc += "signal." %define _DESC212_ \ desc += "Change In Data Transfer Enable\n\n"\ desc += "Enables a change in serialization data to initiate a DSI frames transfer in DSI\n"\ desc += "and CSI configurations. When the CID bit is set, DSI frames are initiated when\n"\ desc += "the current DSI data differs from the previous DSI data shifted out." %define _DESC213_ \ desc += "DSI Continuous Peripheral Chip Select Enable\n\n"\ desc += "Enables the PCS signals to remain asserted between transfers. The DCONT bit\n"\ desc += "affects the PCS signals only in DSI master mode. When the TSBC bit is set,\n"\ desc += "DCONT has no effect." %define _DESC214_ \ desc += "DSI Clock and Transfer Attributes Select\n\n"\ desc += "Selects the CTAR to use to provide transfer attributes for DSI frames. The\n"\ desc += "DSICTAS field is used in DSI master mode. In DSI slave mode, CTAR1 is always\n"\ desc += "selected." %define _DESC215_ \ desc += "Data Match Stop\n\n"\ desc += "If set, stops DSI frame transmissions if DDIF flag is set in the SR." %define _DESC216_ \ desc += "Parity Error Stop\n\n"\ desc += "If set, stops DSI operation if the parity error happened in the received DSI\n"\ desc += "frame." %define _DESC217_ \ desc += "Parity Enable\n\n"\ desc += "Enables parity bit transmission and parity reception check for the DSI\n"\ desc += "frames." %define _DESC218_ \ desc += "Parity Polarity\n\n"\ desc += "Controls the polarity of the parity bit transmitted and checked." %define _DESC219_ \ desc += "DSI Peripheral Chip Select 0-7\n\n"\ desc += "Selects which of the PCS signals to assert during a DSI master mode transfer." %define _DESC220_ \ desc += "DSPI DSI Serialization Data Register 0. SDR0 contains the states of the 32 LSB\n"\ desc += "parallel input signals. The states of these parallel input signals are latched\n"\ desc += "into the SDR0 on the rising edge of every protocol clock. The SDR0 is\n"\ desc += "read-only. When the TXSS bit in the DSICR0 is cleared, the data in the SDR0 is\n"\ desc += "used as the source of the DSI frames. When DSICR1[DSI64E] is enabled, SDR1\n"\ desc += "forms the MSB half and SDR0 forms the LSB half of the 64-bit Serialization Data\n"\ desc += "Register." %define _DESC221_ \ desc += "Serialized Data\n\n"\ desc += "Contains the signal states of the 32 LSB parallel input signals." %define _DESC222_ \ desc += "DSPI DSI Alternate Serialization Data Register 0. ASDR0 is used by host\n"\ desc += "software to write the 32 LSB of the data to be serialized. When the TXSS bit in\n"\ desc += "the DSICR0 is set, the data in the ASDR0 is the source of the DSI frames.\n"\ desc += "Writes to the ASDR0 take effect on the next frame boundary. When DSICR1[DSI64E]\n"\ desc += "is enabled, ASDR1 forms the MSB half while ASDR0 forms the LSB half of the\n"\ desc += "64-bit Alternate Serialization Data Register." %define _DESC223_ \ desc += "Alternate Serialized Data\n\n"\ desc += "Holds the alternate 32 LSB of data to be serialized." %define _DESC224_ \ desc += "DSPI DSI Transmit Comparison Register 0. COMPR0 holds a copy of the 32 LSB of\n"\ desc += "last transmitted DSI data. COMPR0 is read-only. DSI data is transferred to this\n"\ desc += "register as it is loaded into the TX Shift Register. When DSICR1[DSI64E] is\n"\ desc += "enabled, COMPR1 forms the MSB half while COMPR0 forms the LSB half of the\n"\ desc += "64-bit Transmit Comparison Register" %define _DESC225_ \ desc += "Compare Data\n\n"\ desc += "Holds the 32 LSB of last serialized DSI data." %define _DESC226_ \ desc += "DSPI DSI Deserialization Data Register 0. DDR0 holds the 32 LSB signal states\n"\ desc += "for the Parallel Output signals. The DDR0 is read-only and host software can\n"\ desc += "read data from incoming DSI frames. When DSICR1[DSI64E] is enabled, DDR1 forms\n"\ desc += "the MSB half while DDR0 forms the LSB half of the 64-bit Deserialization Data\n"\ desc += "Register." %define _DESC227_ \ desc += "Deserialized Data\n\n"\ desc += "Holds 32 LSB of deserialized data that is presented as signal states to the\n"\ desc += "Parallel Output signals." %define _DESC228_ \ desc += "DSPI DSI Configuration Register 1. DSICR1 selects various attributes associated\n"\ desc += "with TSB (and ITSB) Configuration. The user must not write to the DSICR1 while\n"\ desc += "the DSPI is in the Running state." %define _DESC229_ \ desc += "Timed Serial Bus Operation Count\n\n"\ desc += "When TSBC is set, TSBCNT defines the length of the data frame. The TSBCNT field\n"\ desc += "valid value is from 3 to 63. The TSBCNT field selects the number of data bits\n"\ desc += "to be shifted out during a transfer in TSB mode. The number of data bits in the\n"\ desc += "data frame is one more than the value in the TSBCNT field." %define _DESC230_ \ desc += "DSI 64-bit Mode Enable\n\n"\ desc += "When DSI64E is set, DSI Mode operates in 64-bit configuration allowing\n"\ desc += "serialization and deserialization of Data frames up to 64 bits in size. The\n"\ desc += "Extended Registers DSPI_SDR1, DSPI_ASDR1, DSPI_COMPR1, DSPI_DDR1, DSPI_SSR1,\n"\ desc += "DSPI_PISR4-7, DSPI_DIMR1, DSPI_DPIR1 are only valid when this Mode is\n"\ desc += "enabled." %define _DESC231_ \ desc += "Data Select Enable 1\n\n"\ desc += "When DSICR0[TBSC] bit is set, the DSE1 bit controls insertion of the zero bit\n"\ desc += "(Data Select) in the middle of the data frame. The insertion bit position is\n"\ desc += "defined by the FMSZ field of CTARn register, selected by the DSICR0[DSICTAS]\n"\ desc += "field. If DSICR1[DSI64] is enabled, then the insertion bit position is defined\n"\ desc += "by concatenation of {DSICR0[FMSZ4], CTAR[FMSZ]} fields. The TSBCNT field value\n"\ desc += "must be greater than the FMSZ field value plus one for proper operation of the\n"\ desc += "DSE1 bit." %define _DESC232_ \ desc += "Data Select Enable 0\n\n"\ desc += "When DSICR0[TSBC] bit is set, the DSE0 bit controls insertion of the zero bit\n"\ desc += "(Data Select) in the beginning of the Data frame." %define _DESC233_ \ desc += "Internal Trigger Period for the ITSB mode.\n\n"\ desc += "When DSICR0[TRG] bit is cleared and ITSB Mode is enabled, this field determines\n"\ desc += "the trigger period for the internal trigger in number of baud rate clock\n"\ desc += "cycles. The trigger period should be calculated as:\n\n"\ desc += "Trigger Period = 64 bits (DSI frame maximum size) + 2 selection bits (maximum)\n"\ desc += "+ t PF (passive frame time)\n\n"\ desc += "When DSICR1[DSI64E] is disabled, DSI frame maximum size is 32. Refer CTAR[FMSZ]\n"\ desc += "field for minimum frame size allowed.\n\n"\ desc += "See Interleaved TSB (ITSB) Mode for more details.\n\n"\ desc += "0 - 4 These values are invalid since minimum Command frame size is 5. (i.e. 1\n"\ desc += "selection bit + minimum frame size which is 4)\n\n"\ desc += "5 - 255 Number of baud rate clock cycles to be used as the trigger period. The\n"\ desc += "trigger period implemented is equal to TRGPRD + 1." %define _DESC234_ \ desc += "DSI Peripheral Chip Select 0-7\n\n"\ desc += "These bits define the PCSs to assert for the second part of the DSI frame when\n"\ desc += "operating in TSB (and ITSB) configuration with dual receiver. The DPCS1 bits\n"\ desc += "select which of the PCS signals to assert during the second part of the DSI\n"\ desc += "frame. The DPCS1 bits control the assertions of the PCS signals only in TSB and\n"\ desc += "ITSB mode." %define _DESC235_ \ desc += "DSPI DSI Serialization Source Select Register 0. SSR0 is used to create a\n"\ desc += "combined frame for transmission that contains bits from ASDR0 and from SDR0.\n"\ desc += "Each bit in the SSR0 register selects a corresponding bit to be serialized.\n"\ desc += "When DSICR0[TXSS] is set, the SSR0 register value has no effect. When\n"\ desc += "DSICR1[DSI64E] is enabled, SSR1 forms the MSB half while SSR0 forms the LSB\n"\ desc += "half of the 64-bit Serialization Source Select Register." %define _DESC236_ \ desc += "Source Select\n\n"\ desc += "Select the serialization source for the 32 LSB of DSI frame. Each SS bit\n"\ desc += "selects data for a corresponded bit in the transmitted frame." %define _DESC237_ \ desc += "DSPI DSI Parallel Input Select Register 0. PISR0-3 are used to select each data\n"\ desc += "bit for the transmitted frame from 16 parallel input pins. Each Input Pin\n"\ desc += "Select (IPS) field controls one bit in the transmitted frame. Each register\n"\ desc += "contains control fields for 8 bits in the frame. The select field value is\n"\ desc += "defined as a 4-bit signed integer number. The selected parallel input pin\n"\ desc += "number is defined as a difference between the sum of the field number and the\n"\ desc += "field value.\n\n"\ desc += "For example, if IPS16 is equal to the binary number 1111 (minus 1 decimal),\n"\ desc += "then bit 16 in the frame is taken from parallel input pin number 15. When the\n"\ desc += "IPS0 is equal to -1, then bit 0 in the frame is taken from parallel input 31\n"\ desc += "(bit 0 is taken from parallel input 63 if DSICR1[DSI64E] is enabled). When the\n"\ desc += "IPS0 is equal to +1, then bit 0 in the frame is taken from parallel input 1 and\n"\ desc += "so on.\n\n"\ desc += "Note that PISR0-3 only preselect the parallel input pins. The final selection\n"\ desc += "to the transmitted frame is made with the DSPI_SSR1/0 register bits or the\n"\ desc += "DSICR0[TXSS] bit.\n\n"\ desc += "When DSICR1[DSI64E] is enabled, PISR4-7 Registers are used to handle the extra\n"\ desc += "32 bits (32 MSB pins of the 64 parallel input pins)." %define _DESC238_ \ desc += "Input Pin Select 7\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 7." %define _DESC239_ \ desc += "Input Pin Select 6\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 6." %define _DESC240_ \ desc += "Input Pin Select 5\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 5." %define _DESC241_ \ desc += "Input Pin Select 5\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 4." %define _DESC242_ \ desc += "Input Pin Select 3\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 3." %define _DESC243_ \ desc += "Input Pin Select 2\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 2." %define _DESC244_ \ desc += "Input Pin Select 1\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 1." %define _DESC245_ \ desc += "Input Pin Select 0\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 0." %define _DESC246_ \ desc += "DSPI DSI Parallel Input Select Register 1. " %define _DESC247_ \ desc += "Input Pin Select 15\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 15." %define _DESC248_ \ desc += "Input Pin Select 14\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 14." %define _DESC249_ \ desc += "Input Pin Select 13\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 13." %define _DESC250_ \ desc += "Input Pin Select 12\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 12." %define _DESC251_ \ desc += "Input Pin Select 11\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 11." %define _DESC252_ \ desc += "Input Pin Select 10\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 10." %define _DESC253_ \ desc += "Input Pin Select 9\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 9." %define _DESC254_ \ desc += "Input Pin Select 8\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 8." %define _DESC255_ \ desc += "DSPI DSI Parallel Input Select Register 2. " %define _DESC256_ \ desc += "Input Pin Select 23\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 23." %define _DESC257_ \ desc += "Input Pin Select 22\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 22." %define _DESC258_ \ desc += "Input Pin Select 21\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 21." %define _DESC259_ \ desc += "Input Pin Select 20\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 20." %define _DESC260_ \ desc += "Input Pin Select 19\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 19." %define _DESC261_ \ desc += "Input Pin Select 18\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 18." %define _DESC262_ \ desc += "Input Pin Select 17\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 17." %define _DESC263_ \ desc += "Input Pin Select 16\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 16." %define _DESC264_ \ desc += "DSPI DSI Parallel Input Select Register 3. " %define _DESC265_ \ desc += "Input Pin Select 31\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 31." %define _DESC266_ \ desc += "Input Pin Select 30\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 30." %define _DESC267_ \ desc += "Input Pin Select 29\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 29." %define _DESC268_ \ desc += "Input Pin Select 28\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 28." %define _DESC269_ \ desc += "Input Pin Select 27\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 27." %define _DESC270_ \ desc += "Input Pin Select 26\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 26." %define _DESC271_ \ desc += "Input Pin Select 25\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 25." %define _DESC272_ \ desc += "Input Pin Select 24\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 24." %define _DESC273_ \ desc += "DSPI DSI Deserialized Data Interrupt Mask Register 0. DIMR0 selects bits in the\n"\ desc += "32 LSB of received DSI frame to be checked to generate the DDI interrupt. When\n"\ desc += "DSICR1[DSI64E] is enabled, DIMR1 forms the MSB half while DIMR0 forms the LSB\n"\ desc += "half of the 64-bit Deserialized Data Interrupt Mask Register." %define _DESC274_ \ desc += "Mask\n\n"\ desc += "Defines which bits in the 32 LSB of received deserialization data should be\n"\ desc += "checked to produce the Deserialized Data Interrupt (DDI)." %define _DESC275_ \ desc += "DSPI DSI Deserialized Data Polarity Interrupt Register 0. DPIR0 defines which\n"\ desc += "data bit value in the 32 LSB of received DSI frame generates the DDI interrupt.\n"\ desc += "When DSICR1[DSI64E] is enabled, DPIR1 forms the MSB half while DPIR0 forms the\n"\ desc += "LSB half of the 64-bit Deserialized Data Polarity Interrupt Register." %define _DESC276_ \ desc += "Data Polarity\n\n"\ desc += "Defines which value of the 32 LSB of received deserialization data sets the\n"\ desc += "SR[DDIF] bit." %define _DESC277_ \ desc += "DSPI DSI Serialization Data Register 1. SDR1 contains the states of the 32 MSB\n"\ desc += "parallel input signals. The states of these parallel input signals are latched\n"\ desc += "into the SDR1 on the rising edge of every protocol clock. The SDR1 is\n"\ desc += "read-only. When the TXSS bit in the DSICR0 is cleared, the data in the SDR1 and\n"\ desc += "SDR0 is used as the source of the DSI frames. The concatenation of {DSPI_SDR1,\n"\ desc += "DSPI_SDR0} provides the 64-bit data to be serialized. This register is valid\n"\ desc += "only when DSICR1[DSI64E] is enabled." %define _DESC278_ \ desc += "Serialized Data\n\n"\ desc += "Contains the 32 MSB signal states of the 64 parallel input signals. This field\n"\ desc += "is valid only when DSICR1[DSI64E] is set. The concatenation of {DSPI_SDR1,\n"\ desc += "DSPI_SDR0} provides the 64-bit data to be serialized." %define _DESC279_ \ desc += "DSPI DSI Alternate Serialization Data Register 1. ASDR1 is used by host\n"\ desc += "software to write the 32 MSB of the 64-bit data to be serialized. When the TXSS\n"\ desc += "bit in the DSICR0 is set, the data in the ASDR1 and ASDR0 is the source of the\n"\ desc += "DSI frames. Writes to the ASDR1 take effect on the next frame boundary. The\n"\ desc += "concatenation of {DSPI_ASDR1, DSPI_ASDR0} provides the 64-bit alternate\n"\ desc += "serialization data. This register is valid only when DSICR1[DSI64E] is\n"\ desc += "enabled." %define _DESC280_ \ desc += "Alternate Serialized Data\n\n"\ desc += "Holds the 32 MSB of the 64-bit alternate data to be serialized. This field is\n"\ desc += "valid only when DSICR1[DSI64E] is set. The concatenation of {DSPI_ASDR1,\n"\ desc += "DSPI_ASDR0} provides the 64-bit alternate serialization data." %define _DESC281_ \ desc += "DSPI DSI Transmit Comparison Register 1. COMPR1 holds a copy of the 32 MSB of\n"\ desc += "the last transmitted 64-bit DSI data. COMPR1 is read-only. The upper 32 bits of\n"\ desc += "the 64-bit DSI data is transferred to this register as it is loaded into the TX\n"\ desc += "Shift Register. The concatenation of {DSPI_COMPR1, DSPI_COMPR0} provides the\n"\ desc += "64-bit transmit comparison data. This register is valid only when\n"\ desc += "DSICR1[DSI64E] is enabled." %define _DESC282_ \ desc += "Compare Data\n\n"\ desc += "Holds the 32 MSB of the last serialized 64-bit DSI data. This field is valid\n"\ desc += "only when DSICR1[DSI64E] is set. The concatenation of {DSPI_COMPR1,\n"\ desc += "DSPI_COMPR0} provides the last serialized 64-bit DSI data." %define _DESC283_ \ desc += "DSPI DSI Deserialization Data Register 1. DDR1 holds the 32 MSB signal states\n"\ desc += "for the 64 Parallel Output signals. The DDR1 is read-only and host software can\n"\ desc += "read data from incoming DSI frames.\n\n"\ desc += "The concatenation of {DSPI_DDR1, DSPI_DDR0} provides the 64-bit Deserialized\n"\ desc += "data. This register is valid only when DSICR1[DSI64E] is enabled." %define _DESC284_ \ desc += "Deserialized Data\n\n"\ desc += "Holds 32 MSB of the deserialized data that is presented as signal states to the\n"\ desc += "64 Parallel Output signals. This field is valid only when DSICR1[DSI64E] is\n"\ desc += "set. The concatenation of {DSPI_DDR1, DSPI_DDR0} provides the 64-bit\n"\ desc += "deserialized data." %define _DESC285_ \ desc += "DSPI DSI Serialization Source Select Register 1. SSR1 is used to create a\n"\ desc += "combined frame for transmission that contains bits from ASDR1 and from SDR1.\n"\ desc += "Each bit in the SSR1 register selects a corresponding bit to be serialized.\n"\ desc += "When DSICR0[TXSS] is set, the SSR1 register value has no effect. The\n"\ desc += "concatenation of {DSPI_SSR1, DSPI_SSR0} provides the 64-bit Serialization\n"\ desc += "Source Select Value. This register is valid only when DSICR1[DSI64E] is\n"\ desc += "enabled." %define _DESC286_ \ desc += "Source Select\n\n"\ desc += "Select the serialization source for the 32 MSB of the 64-bit DSI frame. Each SS\n"\ desc += "bit selects data for a corresponded bit in the transmitted frame. This field is\n"\ desc += "valid only when DSICR1[DSI64E] is set. The concatenation of {DSPI_SSR1,\n"\ desc += "DSPI_SSR0} provides the 64-bit serialization source select value." %define _DESC287_ \ desc += "DSPI DSI Parallel Input Select Register 4. PISR4-7 are used to select each data\n"\ desc += "bit for the transmitted frame from 16 parallel input pins. Each Input Pin\n"\ desc += "Select (IPS) field controls one bit in the transmitted frame. Each register\n"\ desc += "contains control fields for 8 bits in the frame. The select field value is\n"\ desc += "defined as a 4-bit signed integer number. The selected parallel input pin\n"\ desc += "number is defined as a difference between the sum of the field number and the\n"\ desc += "field value.\n\n"\ desc += "For example, if IPS16 is equal to the binary number 1111 (minus 1 decimal),\n"\ desc += "then bit 16 in the frame is taken from parallel input pin number 15. When the\n"\ desc += "IPS0 is equal to -1, then bit 0 in the frame is taken from parallel input 31\n"\ desc += "(bit 0 is taken from parallel input 63 when DSICR1[DSI64E] is enabled). When\n"\ desc += "the IPS0 is equal to +1, then bit 0 in the frame is taken fro2m parallel input\n"\ desc += "1 and so on.\n\n"\ desc += "Note that PISR0-7 only preselect the parallel input pins. The final selection\n"\ desc += "to the transmitted frame is made with the SSR0 and SSR1 register bits or the\n"\ desc += "DSICR0[TXSS] bit.\n\n"\ desc += "When 64-bit DSI mode is enabled, PISR4-7 Registers are used to handle the extra\n"\ desc += "32 bits (32 MSB pins of the 64 parallel input pins). If DSICR1[DSI64E] is\n"\ desc += "disabled, then DSPI_PISR4-7 Registers are invalid." %define _DESC288_ \ desc += "Input Pin Select 39\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 39." %define _DESC289_ \ desc += "Input Pin Select 38\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 38." %define _DESC290_ \ desc += "Input Pin Select 37\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 37." %define _DESC291_ \ desc += "Input Pin Select 36\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 36." %define _DESC292_ \ desc += "Input Pin Select 35\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 35." %define _DESC293_ \ desc += "Input Pin Select 34\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 34." %define _DESC294_ \ desc += "Input Pin Select 33\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 33." %define _DESC295_ \ desc += "Input Pin Select 32\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 32." %define _DESC296_ \ desc += "DSPI DSI Parallel Input Select Register 5. " %define _DESC297_ \ desc += "Input Pin Select 47\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 47." %define _DESC298_ \ desc += "Input Pin Select 46\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 46." %define _DESC299_ \ desc += "Input Pin Select 45\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 45." %define _DESC300_ \ desc += "Input Pin Select 44\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 44." %define _DESC301_ \ desc += "Input Pin Select 43\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 43." %define _DESC302_ \ desc += "Input Pin Select 42\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 42." %define _DESC303_ \ desc += "Input Pin Select 41\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 41." %define _DESC304_ \ desc += "Input Pin Select 40\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 40." %define _DESC305_ \ desc += "DSPI DSI Parallel Input Select Register 6. " %define _DESC306_ \ desc += "Input Pin Select 55\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 55." %define _DESC307_ \ desc += "Input Pin Select 54\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 54." %define _DESC308_ \ desc += "Input Pin Select 53\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 53." %define _DESC309_ \ desc += "Input Pin Select 52\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 52." %define _DESC310_ \ desc += "Input Pin Select 51\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 51." %define _DESC311_ \ desc += "Input Pin Select 50\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 50." %define _DESC312_ \ desc += "Input Pin Select 49\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 49." %define _DESC313_ \ desc += "Input Pin Select 48\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 48." %define _DESC314_ \ desc += "DSPI DSI Parallel Input Select Register 7. " %define _DESC315_ \ desc += "Input Pin Select 63\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 63" %define _DESC316_ \ desc += "Input Pin Select 62\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 62" %define _DESC317_ \ desc += "Input Pin Select 61\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 61" %define _DESC318_ \ desc += "Input Pin Select 60\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 60" %define _DESC319_ \ desc += "Input Pin Select 59\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 59" %define _DESC320_ \ desc += "Input Pin Select 58\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 58" %define _DESC321_ \ desc += "Input Pin Select 57\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 57" %define _DESC322_ \ desc += "Input Pin Select 56\n\n"\ desc += "Selects the parallel input pin for transmitted frame bit 56" %define _DESC323_ \ desc += "DSPI DSI Deserialized Data Interrupt Mask Register 1. DIMR1 selects bits from\n"\ desc += "the 32 MSB in the received 64-bit DSI frame to be checked to generate the DDI\n"\ desc += "interrupt. The concatenation of {DSPI_DIMR1, DSPI_DIMR0} provides the 64-bit\n"\ desc += "Deserialized Data Interrupt Mask Value. This register is valid only when\n"\ desc += "DSICR1[DSI64E] is enabled." %define _DESC324_ \ desc += "Mask\n\n"\ desc += "Defines which of the 32 MSB in the received 64-bit deserialization data should\n"\ desc += "be checked to produce the Deserialized Data Interrupt (DDI)." %define _DESC325_ \ desc += "DSPI DSI Deserialized Data Polarity Interrupt Register 1. DPIR1 defines which\n"\ desc += "of the 32 MSB value in the received 64-bit DSI frame generates the DDI\n"\ desc += "interrupt. The concatenation of {DSPI_DPIR1, DSPI_DPIR0} provides the 64-bit\n"\ desc += "Deserialized Data Polarity Value. This register is valid only when\n"\ desc += "DSICR1[DSI64E] is enabled." %define _DESC326_ \ desc += "Data Polarity\n\n"\ desc += "Defines which of the 32 MSB of the received 64-bit deserialization data sets\n"\ desc += "the SR[DDIF] bit." %define _DESC327_ \ desc += "DSPI Clock and Transfer Attributes Register Extended 0. CTARE registers are\n"\ desc += "used to define the extended transfer attributes for an SPI frame. These\n"\ desc += "registers are valid only when DSPI_MCR[XSPI] is set.\n\n"\ desc += "When the DSPI is configured as an SPI master, the CTAS field in CMD FIFO entry\n"\ desc += "selects which of the CTARE registers is used. When the DSPI is configured as an\n"\ desc += "SPI bus slave, the CTARE0 register is used." %define _DESC328_ \ desc += "Frame Size Extended\n\n"\ desc += "This field is valid only when DSPI_MCR[XSPI] is set. This field concatenated\n"\ desc += "with DSPI_CTAR[FMSZ] defines the frame size of the SPI frames to be\n"\ desc += "transmitted. Effective frame size is the concatenation of {DSPI_CTAR[FMSZ],\n"\ desc += "DSPI_CTARE[FMSZE]} plus 1." %define _DESC329_ \ desc += "Data Transfer Count Preload\n\n"\ desc += "This field is valid only when DSPI_MCR[XSPI] is set. This field defines the\n"\ desc += "number of data frames (whose size is defined by CTARE[FMSZE] and CTAR[FMSZ]) to\n"\ desc += "be transmitted using the Command frame that selected this DSPI_CTARE register.\n"\ desc += "The value 0 is reserved and should not be written in this field. The default\n"\ desc += "value of this field is 1." %define _DESC330_ \ desc += "DSPI Status Register Extended. The DSPI_SREX contains status fields. The fields\n"\ desc += "reflect the status of the DSPI and indicate the occurrence of events. This\n"\ desc += "register is not writable." %define _DESC331_ \ desc += "CMD FIFO Counter\n\n"\ desc += "Indicates the number of entries in the CMD FIFO. The CMDCTR is incremented\n"\ desc += "every time the command part of PUSHR is written. The CMDCTR is decremented\n"\ desc += "every time a SPI command is executed (all data frames due to current command\n"\ desc += "frame have been transmitted)." %define _DESC332_ \ desc += "Command Next Pointer\n\n"\ desc += "Indicates which CMD FIFO Entry is used during the next transfer. The CMDNXTPTR\n"\ desc += "field is updated every time SPI data due to current command have been\n"\ desc += "transmitted." %define _DESC333_ \ desc += "Output Enable Register. The DTS_ENABLE register controls the DTS Trigger Output\n"\ desc += "( DTO ) and whether DTO is active on the EVTO output pin of the device. The\n"\ desc += "DTS_ENABLE register can be read by the core, but can only be written by a Nexus\n"\ desc += "Read Write Access (RWA).\n\n"\ desc += "Access to the DTS_SEMAPHORE and DTS_STARTUP registers are unaffected by the\n"\ desc += "state of this register." %define _DESC334_ \ desc += "DTS Enable. Controls whether the DTO signal is routed to the EVTO pin. The DTS\n"\ desc += "Enable bit is cleared by a device reset (either the assertion of the external\n"\ desc += "RESET or by an internally generated reset). A Nexus reset does not change the\n"\ desc += "state of this register." %define _DESC335_ \ desc += "DTS Enable B. Controls whether the DTO signal is routed to the EVTO pin. The\n"\ desc += "DTS Enable bit is cleared by a device reset (either the assertion of the\n"\ desc += "external RESET or by an internally generated reset). A Nexus reset does not\n"\ desc += "change the state of this register." %define _DESC336_ \ desc += "Startup Register. The DTS_STARTUP register is used for tool detection and\n"\ desc += "startup information exchange between external data acquisition tool and the\n"\ desc += "embedded controller. DTS_STARTUP register can be read by the core, the eDMA\n"\ desc += "module and Nexus but can only be updated by a Nexus Read Write Access (RWA)." %define _DESC337_ \ desc += "Application Dependent register bits. The bits have no defined meaning to the\n"\ desc += "microcontroller. They are used to by an external tool to pass information (for\n"\ desc += "example, application options and status) to application software running on\n"\ desc += "target microcontroller at startup time. Use a Nexus RWA 32-bit write access to\n"\ desc += "update the contents of this register.\n\n"\ desc += "A device reset (either from the RESET pin or an internally generated reset)\n"\ desc += "clears all bits in the register. A Nexus reset does not change the contents of\n"\ desc += "the register.\n\n"\ desc += "" %define _DESC338_ \ desc += "Semaphore Register. The DTS_SEMAPHORE register is used by software to assert\n"\ desc += "the DTO signal on the device EVTO pin. A one in any bit of this register causes\n"\ desc += "the DTO signal on the EVTO pin to be driven low. The intended use of this\n"\ desc += "register is for the DTO signal to notify tools that data is available.\n"\ desc += "Individual bits are used to identify the specific data." %define _DESC339_ \ desc += "Semaphore Trigger. When a core or eDMA writes a logical '1' to a bit, the bit\n"\ desc += "is set. A write of '0' by the core or DMA does not change the state of the\n"\ desc += "bit.\n\n"\ desc += "All register bits are set to '1' by a device reset. A Nexus reset does not\n"\ desc += "change the state of this register. The register can be accessed, with\n"\ desc += "restrictions, by any core, DMA or any Nexus RWA. For the core or DMA, only\n"\ desc += "32-bit write or read accesses are valid. A core or DMA valid read access\n"\ desc += "returns the current value of the register and leaves the register unchanged. \n"\ desc += "" %define _DESC340_ \ desc += "Semaphore Extension. The DTS_SEMAPHORE_B register is used by software to assert\n"\ desc += "the DTO signal on the device EVTO pin. A one in any bit of this register causes\n"\ desc += "the DTO signal on the EVTO pin to be driven low. The intended use of this\n"\ desc += "register is for the DTO signal to notify tools that data is available.\n"\ desc += "Individual bits are used to identify the specific data." %define _DESC341_ \ desc += "Semaphore Trigger Extension. When a core or eDMA writes a logical '1' to a bit,\n"\ desc += "the bit is set. A write of '0' by the core or DMA does not change the state of\n"\ desc += "the bit.\n\n"\ desc += "All register bits are set to '1' by a device reset. A Nexus reset does not\n"\ desc += "change the state of this register. The register can be accessed, with\n"\ desc += "restrictions, by any core, DMA or any Nexus RWA. For the core or DMA, only\n"\ desc += "32-bit write or read accesses are valid. A core or DMA valid read access\n"\ desc += "returns the current value of the register and leaves the register unchanged. \n"\ desc += "" %define _DESC342_ \ desc += "Error Injection Module Configuration Register. The EIM Configuration Register\n"\ desc += "is used to globally enable/disable the error injection function" %define _DESC343_ \ desc += "This bit globally enables or disables the error injection function of the EIM.\n"\ desc += ".This field is initialized by hardware reset." %define _DESC344_ \ desc += "Error Injection Channel Enable register. The Error Injection Channel Enable\n"\ desc += "register (EICHEN) is used to enable or disable the individual error injection\n"\ desc += "channels. Note that there is a global error injection enable (EIMCR[GEIEN])\n"\ desc += "also that must be asserted in conjunction with the individual EICHnEN flags to\n"\ desc += "enable a given error injection channel." %define _DESC345_ \ desc += "This bit enables the corresponding error injection channel. The global error\n"\ desc += "injection enable (EIMCR[GEIEN]) must also be asserted to enable error\n"\ desc += "injection. Once error injection is enabled, all subsequent read accesses will\n"\ desc += "incur bit inversion(s) as defined in Error Injection Descriptor0 registers\n"\ desc += "(EICHD0) until the error injection channel is manually disabled via software.\n"\ desc += "Any write to the corresponding EICHDn registers clears the corresponding\n"\ desc += "EICHEN[EICHnEN] bit, leaving the error injection channel disabled. This bit is\n"\ desc += "cleared by power-on reset and unaffected by other types of system reset." %define _DESC346_ \ desc += "Error Injection Channel Descriptor, Word0. The first word of the Error\n"\ desc += "Injection Channel n Descriptor defines an 8-bit mask (CHKBIT_MASK). Each bit of\n"\ desc += "CHKBIT_MASK specifies if the corresponding bit of the checkbit bus from the\n"\ desc += "target RAM should be inverted or left unmodified on read accesses. Successful\n"\ desc += "writes to this word clear the corresponding error injection channel valid bit,\n"\ desc += "EICHEN[EICHnEN]." %define _DESC347_ \ desc += "This field defines a bit-mapped mask that specifies if the corresponding bit of\n"\ desc += "the checkbit bus from the target RAM should be inverted or left unmodified." %define _DESC348_ \ desc += "Error Injection Channel Descriptor, Word1. The second word of the Error\n"\ desc += "Injection Channel n Descriptor defines the 32-bit mask (UDATA_MASK). Each bit\n"\ desc += "of UDATA_MASK specifies if the corresponding bit of the upper word on the\n"\ desc += "64-bit read data bus from the target RAM should be inverted or left unmodified\n"\ desc += "on read accesses. The upper word corresponds to bits 0-3 of the 64-bit read\n"\ desc += "data bus. Successful writes to this word clear the corresponding error\n"\ desc += "injection channel valid bit, EICHEN[EICHnEN]." %define _DESC349_ \ desc += "This field defines a bit-mapped mask that specifies if the corresponding bit of\n"\ desc += "the upper word on the read data bus from the target RAM should be inverted or\n"\ desc += "left unmodified." %define _DESC350_ \ desc += "Error Injection Channel Descriptor, Word2. The third word of the Error\n"\ desc += "Injection Channel n Descriptor defines a 32-bit mask (LDATA_MASK). Each bit of\n"\ desc += "LDATA_MASK specifies if the corresponding bit of the lower word on the 64-bit\n"\ desc += "read data bus from the target RAM should be inverted or left unmodified on read\n"\ desc += "accesses.The lower word corresponds to bits 4-7 of the 64-bit read data bus.\n"\ desc += "Successful writes to this word clear the corresponding error injection channel\n"\ desc += "valid bit, EICHEN[EICHnEN]." %define _DESC351_ \ desc += "This field defines a bit-mapped mask that specifies if the corresponding bit of\n"\ desc += "the lower word on the read data bus from the target RAM should be inverted or\n"\ desc += "left unmodified." %define _DESC352_ \ desc += "ERM Configuration Register. The ERM Configuration Register is a 32-bit control\n"\ desc += "register for configuring the interrupt notification capability for each memory\n"\ desc += "channel." %define _DESC353_ \ desc += "Enable Memory0 Single Correction Interrupt Notification\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory0 mapping." %define _DESC354_ \ desc += "Enable Memory0 Non-Correctable Interrupt Notification\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory0 mapping." %define _DESC355_ \ desc += "Enable Memory1 Single Correction Interrupt Notification\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory0 mapping." %define _DESC356_ \ desc += "Enable Memory1 Non-Correctable Interrupt Notification\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory0 mapping." %define _DESC357_ \ desc += "Enable Memory2 Single Correction Interrupt Notification\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory0 mapping." %define _DESC358_ \ desc += "Enable Memory2 Non-Correctable Interrupt Notification\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory0 mapping." %define _DESC359_ \ desc += "Enable Memory3 Single Correction Interrupt Notification\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory0 mapping." %define _DESC360_ \ desc += "Enable Memory3 Non-Correctable Interrupt Notification\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory0 mapping." %define _DESC361_ \ desc += "Enable Memory4 Single Correction Interrupt Notification\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory0 mapping." %define _DESC362_ \ desc += "Enable Memory4 Non-Correctable Interrupt Notification\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory0 mapping." %define _DESC363_ \ desc += "Enable Memory5 Single Correction Interrupt Notification\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory0 mapping." %define _DESC364_ \ desc += "Enable Memory5 Non-Correctable Interrupt Notification\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory0 mapping." %define _DESC365_ \ desc += "Enable Memory6 Single Correction Interrupt Notification\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory0 mapping." %define _DESC366_ \ desc += "Enable Memory6 Non-Correctable Interrupt Notification\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory0 mapping." %define _DESC367_ \ desc += "Enable Memory7 Single Correction Interrupt Notification\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory0 mapping." %define _DESC368_ \ desc += "Enable Memory7 Non-Correctable Interrupt Notification\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory0 mapping." %define _DESC369_ \ desc += "ERM Status Register. The ERM Status Register is a 32-bit control register for\n"\ desc += "signaling which types of ECC events have been detected for each memory channel.\n"\ desc += "The ERM_SR signals the last memory event to be detected for each memory\n"\ desc += "channel." %define _DESC370_ \ desc += "Memory0 Single-Bit Correction Event\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Write '1' to clear this field.\n\n"\ desc += "Write '1' to clear this field also deasserts the corresponding interrupt\n"\ desc += "notification if ERM_CR[ESCIE0] is enabled.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory0 mapping." %define _DESC371_ \ desc += "Memory0 Non-Correctable Error Event\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Write '1' to clear this field also deasserts the corresponding interrupt\n"\ desc += "notification if ERM_CR[ENCIE0] is enabled.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory0 mapping." %define _DESC372_ \ desc += "Memory1 Single-Bit Correction Event\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Write '1' to clear this field.\n\n"\ desc += "Write '1' to clear this field also deasserts the corresponding interrupt\n"\ desc += "notification if ERM_CR[ESCIE1] is enabled.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory1 mapping." %define _DESC373_ \ desc += "Memory1 Non-Correctable Error Event\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Write '1' to clear this field also deasserts the corresponding interrupt\n"\ desc += "notification if ERM_CR[ENCIE1] is enabled.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory1 mapping." %define _DESC374_ \ desc += "Memory2 Single-Bit Correction Event\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Write '1' to clear this field.\n\n"\ desc += "Write '1' to clear this field also deasserts the corresponding interrupt\n"\ desc += "notification if ERM_CR[ESCIE2] is enabled.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory2 mapping." %define _DESC375_ \ desc += "Memory2 Non-Correctable Error Event\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Write '1' to clear this field also deasserts the corresponding interrupt\n"\ desc += "notification if ERM_CR[ENCIE2] is enabled.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory2 mapping." %define _DESC376_ \ desc += "Memory3 Single-Bit Correction Event\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Write '1' to clear this field.\n\n"\ desc += "Write '1' to clear this field also deasserts the corresponding interrupt\n"\ desc += "notification if ERM_CR[ESCIE3] is enabled.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory2 mapping." %define _DESC377_ \ desc += "Memory3 Non-Correctable Error Event\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Write '1' to clear this field also deasserts the corresponding interrupt\n"\ desc += "notification if ERM_CR[ENCIE3] is enabled.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory2 mapping." %define _DESC378_ \ desc += "Memory4 Single-Bit Correction Event\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Write '1' to clear this field.\n\n"\ desc += "Write '1' to clear this field also deasserts the corresponding interrupt\n"\ desc += "notification if ERM_CR[ESCIE4] is enabled.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory4 mapping." %define _DESC379_ \ desc += "Memory4 Non-Correctable Error Event\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Write '1' to clear this field also deasserts the corresponding interrupt\n"\ desc += "notification if ERM_CR[ENCIE4] is enabled.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory4 mapping." %define _DESC380_ \ desc += "Memory5 Single-Bit Correction Event\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Write '1' to clear this field.\n\n"\ desc += "Write '1' to clear this field also deasserts the corresponding interrupt\n"\ desc += "notification if ERM_CR[ESCIE5] is enabled.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory5 mapping." %define _DESC381_ \ desc += "Memory5 Non-Correctable Error Event\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Write '1' to clear this field also deasserts the corresponding interrupt\n"\ desc += "notification if ERM_CR[ENCIE5] is enabled.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory5 mapping." %define _DESC382_ \ desc += "Memory6 Single-Bit Correction Event\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Write '1' to clear this field.\n\n"\ desc += "Write '1' to clear this field also deasserts the corresponding interrupt\n"\ desc += "notification if ERM_CR[ESCIE6] is enabled.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory6 mapping." %define _DESC383_ \ desc += "Memory6 Non-Correctable Error Event\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Write '1' to clear this field also deasserts the corresponding interrupt\n"\ desc += "notification if ERM_CR[ENCIE6] is enabled.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory6 mapping." %define _DESC384_ \ desc += "Memory7 Single-Bit Correction Event\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Write '1' to clear this field.\n\n"\ desc += "Write '1' to clear this field also deasserts the corresponding interrupt\n"\ desc += "notification if ERM_CR[ESCIE7] is enabled.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory7 mapping." %define _DESC385_ \ desc += "Memory7 Non-Correctable Error Event\n\n"\ desc += "This field is initialized by hardware reset.\n\n"\ desc += "Write '1' to clear this field also deasserts the corresponding interrupt\n"\ desc += "notification if ERM_CR[ENCIE7] is enabled.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory7 mapping." %define _DESC386_ \ desc += "ERM Memory n Error Address Register. The ERM_EARn is a 32-bit register for\n"\ desc += "capturing the address of the last ECC event in Memory n , where n denotes the\n"\ desc += "memory channel. Any attempted write to ERM_EARn is ignored." %define _DESC387_ \ desc += "Memory n Error Address - This field contains the faulting system address of the\n"\ desc += "last recorded ECC event on Memory n.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory n mapping." %define _DESC388_ \ desc += "ERM Memory n Syndrome Register. The ERM_SYN n is a 32-bit register for\n"\ desc += "capturing the calculated syndrome of the last ECC event on Memory n , where n\n"\ desc += "denotes the memory channel. Any attempted write to ERM_SYN n is ignored. The\n"\ desc += "syndrome value identifies the pertinent bit position on a correctable,\n"\ desc += "single-bit data inversion or a non-correctable, single-bit address inversion.\n"\ desc += "The syndrome value does not provide any additional diagnostic information on\n"\ desc += "non-correctable, multi-bit inversions." %define _DESC389_ \ desc += "Memory n Syndrome - This field contains the ECC syndrome associated with the\n"\ desc += "last recorded ECC event on Memory n.\n\n"\ desc += "Refer to the device-specific integration guide for details on Memory n mapping." %define _DESC390_ \ desc += "Interrupt Event Register. When an event occurs that sets a bit in EIR, an\n"\ desc += "interrupt occurs if the corresponding bit in the interrupt mask register (EIMR)\n"\ desc += "is also set. Writing a 1 to an EIR bit clears it; writing 0 has no effect. This\n"\ desc += "register is cleared upon hardware reset.\n\n"\ desc += "These interrupts can be divided into operational interrupts,\n"\ desc += "transceiver/network error interrupts, and internal error interrupts. Interrupts\n"\ desc += "which may occur in normal operation are GRA, TXF, TXB, RXF, RXB, and MII.\n"\ desc += "Interrupts resulting from errors/problems detected in the network or\n"\ desc += "transceiver are HBERR, BABR, BABT, LC, and RL. Interrupts resulting from\n"\ desc += "internal errors are HBERR and UN.\n\n"\ desc += "Some of the error interrupts are independently counted in the MIB block\n"\ desc += "counters:\n\n"\ desc += "HBERR - IEEE_T_SQE BABR - RMON_R_OVERSIZE (good CRC), RMON_R_JAB (bad CRC) \n"\ desc += "BABT - RMON_T_OVERSIZE (good CRC), RMON_T_JAB (bad CRC) LATE_COL - IEEE_T_LCOL\n"\ desc += "COL_RETRY_LIM - IEEE_T_EXCOL XFIFO_UN - IEEE_T_MACERR Software may choose to\n"\ desc += "mask off these interrupts because these errors are visible to network\n"\ desc += "management via the MIB counters." %define _DESC391_ \ desc += "Heartbeat error. Indicates TCR[HBC] is set and that the COL input was not\n"\ desc += "asserted within the heartbeat window following a transmission." %define _DESC392_ \ desc += "Babbling receive error. Indicates a frame was received with length in excess of\n"\ desc += "RCR[MAX_FL] bytes." %define _DESC393_ \ desc += "Babbling transmit error. Indicates the transmitted frame length exceeds\n"\ desc += "RCR[MAX_FL] bytes. Usually this condition is caused by a frame that is too long\n"\ desc += "is placed into the transmit data buffer(s). Truncation does not occur." %define _DESC394_ \ desc += "Graceful stop complete. Indicates the graceful stop is complete. During\n"\ desc += "graceful stop the transmitter is placed into a pause state after completion of\n"\ desc += "the frame currently being transmitted. This bit is set by one of these\n"\ desc += "conditions:\n\n"\ desc += "A graceful stop initiated by the setting of the TCR[GTS] bit is now complete. \n"\ desc += "A graceful stop initiated by the setting of the TCR[TFC_PAUSE] bit is now\n"\ desc += "complete. A graceful stop initiated by the reception of a valid full duplex\n"\ desc += "flow control pause frame is now complete. See Full duplex flow control ." %define _DESC395_ \ desc += "Transmit frame interrupt. Indicates a frame has been transmitted and the last\n"\ desc += "corresponding buffer descriptor has been updated." %define _DESC396_ \ desc += "Transmit buffer interrupt. Indicates a transmit buffer descriptor has been\n"\ desc += "updated." %define _DESC397_ \ desc += "Receive frame interrupt. Indicates a frame has been received and the last\n"\ desc += "corresponding buffer descriptor has been updated." %define _DESC398_ \ desc += "Receive buffer interrupt. Indicates a receive buffer descriptor not the last in\n"\ desc += "the frame has been updated." %define _DESC399_ \ desc += "MII interrupt. Indicates the MII has completed the data transfer requested." %define _DESC400_ \ desc += "Ethernet bus error. Indicates a system bus error occurred when a DMA\n"\ desc += "transaction is underway. When the EBERR bit is set, ECR[ETHER_EN] is cleared,\n"\ desc += "halting frame processing by the FEC. When this occurs, software needs to ensure\n"\ desc += "that the FIFO controller and DMA also soft reset." %define _DESC401_ \ desc += "Late collision. Indicates a collision occurred beyond the collision window\n"\ desc += "(slot time) in half duplex mode. The frame truncates with a bad CRC and the\n"\ desc += "remainder of the frame is discarded." %define _DESC402_ \ desc += "Collision retry limit. Indicates a collision occurred on each of 16 successive\n"\ desc += "attempts to transmit the frame. The frame is discarded without being\n"\ desc += "transmitted and transmission of the next frame commences. This error can only\n"\ desc += "occur in half duplex mode." %define _DESC403_ \ desc += "Transmit FIFO underrun. Indicates the transmit FIFO became empty before the\n"\ desc += "complete frame was transmitted. A bad CRC is appended to the frame fragment and\n"\ desc += "the remainder of the frame is discarded." %define _DESC404_ \ desc += "Interrupt Mask Register. The EIMR register controls which interrupt events are\n"\ desc += "allowed to generate actual interrupts. A hardware reset clears this register.\n"\ desc += "If the corresponding bits in the EIR and EIMR registers are set, an interrupt\n"\ desc += "is generated. The interrupt signal remains asserted until a 1 is written to the\n"\ desc += "EIR bit (write 1 to clear) or a 0 is written to the EIMR bit.\n\n"\ desc += "Each bit in this register corresponds to an interrupt source defined by the EIR\n"\ desc += "register. The corresponding EIMR bit determines whether an interrupt condition\n"\ desc += "can generate an interrupt. At every processor clock, the EIR samples the signal\n"\ desc += "generated by the interrupting source. The corresponding EIR bit reflects the\n"\ desc += "state of the interrupt signal even if the corresponding EIMR bit is set." %define _DESC405_ \ desc += "Heartbeat error interrupt mask." %define _DESC406_ \ desc += "Babbling receive error interrupt mask." %define _DESC407_ \ desc += "Babbling transmit error interrupt mask." %define _DESC408_ \ desc += "Graceful stop complete interrupt mask." %define _DESC409_ \ desc += "Transmit frame interrupt mask." %define _DESC410_ \ desc += "Transmit buffer interrupt mask." %define _DESC411_ \ desc += "Receive frame interrupt mask." %define _DESC412_ \ desc += "Receive buffer interrupt mask." %define _DESC413_ \ desc += "MII interrupt mask." %define _DESC414_ \ desc += "Ethernet bus error interrupt mask." %define _DESC415_ \ desc += "Late collision interrupt mask." %define _DESC416_ \ desc += "Collision retry limit interrupt mask." %define _DESC417_ \ desc += "Transmit FIFO underrun interrupt mask." %define _DESC418_ \ desc += "Receive Descriptor Active Register. RDAR is a command register, written by the\n"\ desc += "user, indicating the receive descriptor ring is updated (the driver produced\n"\ desc += "empty receive buffers with the empty bit set).\n\n"\ desc += "When the register is written, the RDAR bit is set. This is independent of the\n"\ desc += "data actually written by the user. When set, the FEC polls the receive\n"\ desc += "descriptor ring and processes receive frames (if ECR[ETHER_EN] is also set).\n"\ desc += "After the FEC polls a receive descriptor whose empty bit is not set, FEC clears\n"\ desc += "the RDAR bit and ceases receive descriptor ring polling until the user sets the\n"\ desc += "bit again, signifying that additional descriptors are placed into the receive\n"\ desc += "descriptor ring.\n\n"\ desc += "The RDAR register is cleared at reset and when ECR[ETHER_EN] is cleared." %define _DESC419_ \ desc += "Set to 1 when this register is written, regardless of the value written.\n"\ desc += "Cleared by the FEC when no additional empty descriptors remain in the receive\n"\ desc += "ring. Also cleared when ECR[ETHER_EN] is cleared." %define _DESC420_ \ desc += "Transmit Descriptor Active Register. The TDAR is a command register which the\n"\ desc += "user writes to indicate the transmit descriptor ring is updated (transmit\n"\ desc += "buffers have been produced by the driver with the ready bit set in the buffer\n"\ desc += "descriptor).\n\n"\ desc += "When the register is written, the TDAR field is set. This value is independent\n"\ desc += "of the data actually written by the user. When set, the FEC polls the transmit\n"\ desc += "descriptor ring and processes transmit frames (provided ECR[ETHER_EN] is also\n"\ desc += "set). After the FEC polls a transmit descriptor that is a ready bit not set,\n"\ desc += "FEC clears the TDAR field and ceases transmit descriptor ring polling until the\n"\ desc += "user sets the bit again, signifying additional descriptors are placed into the\n"\ desc += "transmit descriptor ring.\n\n"\ desc += "The TDAR field is cleared when any of the following events occur:\n\n"\ desc += "Chip reset When ECR[ETHER_EN] is cleared When ECR[RESET] is set" %define _DESC421_ \ desc += "Set to 1 when this register is written, regardless of the value written.\n"\ desc += "Cleared by the FEC device when no additional ready descriptors remain in the\n"\ desc += "transmit ring. Also cleared when ECR[ETHER_EN] is cleared." %define _DESC422_ \ desc += "Ethernet Control Register. ECR is a read/write user register, though hardware\n"\ desc += "may alter fields in this register as well. The ECR enables/disables the FEC." %define _DESC423_ \ desc += "When this bit is set, FEC is enabled, and reception and transmission are\n"\ desc += "possible. When this bit is cleared, reception immediately stops and\n"\ desc += "transmission stops after a bad CRC is appended to any currently transmitted\n"\ desc += "frame. The buffer descriptor(s) for an aborted transmit frame are not updated\n"\ desc += "after clearing this bit. When ETHER_EN is cleared, the DMA, buffer descriptor,\n"\ desc += "and FIFO control logic are reset, including the buffer descriptor and FIFO\n"\ desc += "pointers. Hardware alters the ETHER_EN bit under the following conditions:\n\n"\ desc += "ECR[RESET] is set by software, in which case ETHER_EN is cleared. An error\n"\ desc += "condition causes the EIR[EBERR] bit to set, in which case ETHER_EN is cleared." %define _DESC424_ \ desc += "When this bit is set, the equivalent of a hardware reset is performed but it is\n"\ desc += "local to the FEC. ECR[ETHER_EN] is cleared and all other FEC registers take\n"\ desc += "their reset values. Also, any transmission/reception currently in progress is\n"\ desc += "abruptly aborted. This bit is automatically cleared by hardware during the\n"\ desc += "reset sequence. The reset sequence takes approximately eight internal bus clock\n"\ desc += "cycles after this bit is set." %define _DESC425_ \ desc += "MII Management Frame Register. The MMFR is used to communicate with the\n"\ desc += "attached MII compatible PHY device(s), providing read/write access to their MII\n"\ desc += "registers. Performing a write to the MMFR causes a management frame to be\n"\ desc += "sourced unless the MSCR is programmed to 0. If MSCR is cleared while MMFR is\n"\ desc += "written and then MSCR is written with a non-zero value, an MII frame is\n"\ desc += "generated with the data previously written to the MMFR. This allows MMFR and\n"\ desc += "MSCR to be programmed in either order if MSCR is currently zero.\n\n"\ desc += "The MMFR does not reset to any predefined value.\n\n"\ desc += "To perform a read or write operation on the MII Management Interface, write the\n"\ desc += "MMFR. To generate a valid read or write management frame, ST field must be\n"\ desc += "written with a 01 pattern, and the TA field must be written with a 10. If other\n"\ desc += "patterns are written to these fields, a frame is generated, but does not comply\n"\ desc += "with the IEEE 802.3 MII definition.\n\n"\ desc += "To generate an IEEE 802.3-compliant MII Management Interface write frame (write\n"\ desc += "to a PHY register), write {01 01 PHYAD REGAD 10 DATA} to the MMFR. Writing this\n"\ desc += "pattern causes the control logic to shift out the data in the MMFR register\n"\ desc += "following a preamble generated by the control state machine. During this time,\n"\ desc += "contents of the MMFR register are altered as the contents are serially shifted\n"\ desc += "and are unpredictable if read by the user. After the write management frame\n"\ desc += "operation completes, the MII interrupt is generated. At this time, contents of\n"\ desc += "the MMFR match the original value written.\n\n"\ desc += "To generate an MII management interface read frame (read a PHY register), write\n"\ desc += "{01 10 PHYAD REGAD 10 XXXX} to the MMFR (the content of the DATA field is\n"\ desc += "unimportant). Writing this pattern causes the control logic to shift out the\n"\ desc += "data in the MMFR register following a preamble generated by the control state\n"\ desc += "machine. During this time, contents of the MMFR register are altered as the\n"\ desc += "contents are serially shifted and are unpredictable if read by the user. After\n"\ desc += "the read management frame operation completes, the MII interrupt is generated.\n"\ desc += "At this time, the contents of the MMFR register match the original value\n"\ desc += "written except for the DATA field whose contents are replaced by the value read\n"\ desc += "from the PHY register.\n\n"\ desc += "If the MMFR register is written while frame generation is in progress, the\n"\ desc += "frame contents are altered. Software must use the MII interrupt to avoid\n"\ desc += "writing to the MMFR while frame generation is in progress." %define _DESC426_ \ desc += "Start of frame delimiter. These bits must be programmed to 0b01 for a valid MII\n"\ desc += "management frame." %define _DESC427_ \ desc += "Operation code." %define _DESC428_ \ desc += "PHY address. This field specifies one of up to 32 attached PHY devices." %define _DESC429_ \ desc += "Register address. This field specifies one of up to 32 registers within the\n"\ desc += "specified PHY device." %define _DESC430_ \ desc += "Turn around. This field must be programmed to 10 to generate a valid MII\n"\ desc += "management frame." %define _DESC431_ \ desc += "Management frame data. This is the field for data to be written to or read from\n"\ desc += "the PHY register." %define _DESC432_ \ desc += "MII Speed Control Register. The MSCR:\n\n"\ desc += "Provides control of the MII clock (FEC_MDC pin) frequency Allows a preamble\n"\ desc += "drop on the MII management frame The MII_SPEED field must be programmed with a\n"\ desc += "value to provide an FEC_MDC frequency of less than or equal to 2.5 MHz to be\n"\ desc += "compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set to a\n"\ desc += "non-zero value to source a read or write management frame. After the management\n"\ desc += "frame is complete, the MSCR register may optionally be set to 0 to turn off the\n"\ desc += "FEC_MDC. The FEC_MDC generated has a 50% duty cycle except when MII_SPEED\n"\ desc += "changes during operation (change takes effect following a rising or falling\n"\ desc += "edge of FEC_MDC).\n\n"\ desc += "If the internal bus clock is 25 MHz, programming this register to 0000_0005h\n"\ desc += "results in an FEC_MDC as stated the equation below.\n\n"\ desc += "#ProgExampForMSCR shows optimum values for MII_SPEED as a function of internal\n"\ desc += "bus clock frequency.\n\n"\ desc += "[Programming examples for MSCR]:\n"\ desc += " Internal FEC clock frequency MSCR[MII_SPEED] FEC_MDC frequency\n"\ desc += " ---------------------------- --------------- -----------------\n"\ desc += " 25 MHz 5h 2.50 MHz\n"\ desc += " 33 MHz 7h 2.36 MHz\n"\ desc += " 40 MHz 8h 2.50 MHz\n"\ desc += " 50 MHz Ah 2.50 MHz\n"\ desc += " 66 MHz Eh 2.36 MHz\n"\ desc += " 80 MHz 10h 2.50 MHz\n"\ desc += " 83 MHz 10h 2.59 MHz\n" %define _DESC433_ \ desc += "Setting this bit causes the preamble (32 ones) not to be prepended to the MII\n"\ desc += "management frame. The MII standard allows the preamble to be dropped if the\n"\ desc += "attached PHY device(s) does not require it." %define _DESC434_ \ desc += "Controls the frequency of the MII management interface clock (FEC_MDC) relative\n"\ desc += "to the internal bus clock. A value of 0 in this field turns off the FEC_MDC and\n"\ desc += "leaves it in low voltage state. Any non-zero value results in the FEC_MDC\n"\ desc += "frequency of 1/(MII_SPEED x 2) of the internal bus frequency." %define _DESC435_ \ desc += "MIB Control Register. The MIBC is a read/write register controlling and\n"\ desc += "observing the state of the MIB block. User software accesses this register if\n"\ desc += "there is a need to disable the MIB block operation. For example, to clear all\n"\ desc += "MIB counters in RAM:\n\n"\ desc += "Disable the MIB block Clear all the MIB RAM locations Enable the MIB block \n"\ desc += "The MIB_DIS bit is reset to 1. See the memory map for the locations of the MIB\n"\ desc += "counters." %define _DESC436_ \ desc += "If MIB_DIS = 1, the MIB logic halts and not update any MIB counters." %define _DESC437_ \ desc += "If MIB_IDLE = 1, the MIB block is not currently updating any MIB counters." %define _DESC438_ \ desc += "Receive Control Register. RCR controls the operational mode of the receive\n"\ desc += "block and must be written only when ECR[ETHER_EN] is cleared (initialization\n"\ desc += "time)." %define _DESC439_ \ desc += "Maximum frame length. Length is measured starting at DA and includes the CRC at\n"\ desc += "the end of the frame. Transmit frames longer than MAX_FL causes the BABT\n"\ desc += "interrupt to occur. Receive frames longer than MAX_FL causes the BABR interrupt\n"\ desc += "to occur and sets the LG bit in the end of frame receive buffer descriptor.\n\n"\ desc += "The recommended default value to be programmed is 1518 or 1522 if VLAN tags are\n"\ desc += "supported." %define _DESC440_ \ desc += "RMII Echo. Enables RMII echo mode. RMII 2-bit receive data is processed through\n"\ desc += "the RMII receive logic to the FEC and also routes through the RMII's transmit\n"\ desc += "logic to become RMII 2-bit transmit data out." %define _DESC441_ \ desc += "RMII loopback. Enables RMII loopback mode. Causes the MII transmit outputs from\n"\ desc += "the Ethernet controller to loop back to the Ethernet controllers's MII receive\n"\ desc += "inputs through the RMII transmit/receive logic." %define _DESC442_ \ desc += "RMII 10-Base T. Enables 10Mbps mode of the RMII. Determines the clock frequency\n"\ desc += "of the clock source to the FEC logic to support 10/100Mbps operations." %define _DESC443_ \ desc += "RMII Mode. Indicates if the FEC is in RMII or MII/7-wire mode. See the chip\n"\ desc += "configuration chapter for more details.\n\n"\ desc += "Interface selection is chip-specific; see the chapter that describes how\n"\ desc += "modules are configured and connected." %define _DESC444_ \ desc += "Flow control enable. If asserted, the receiver detects PAUSE frames. Upon PAUSE\n"\ desc += "frame detection, the transmitter stops transmitting data frames for a given\n"\ desc += "duration." %define _DESC445_ \ desc += "Broadcast frame reject. If asserted, frames with DA (destination address) equal\n"\ desc += "to FFFF_FFFF_FFFF are rejected unless the PROM bit is set. If BC_REJ and PROM\n"\ desc += "are set, frames with broadcast DA are accepted and the M (MISS) is set in the\n"\ desc += "receive buffer descriptor." %define _DESC446_ \ desc += "Promiscuous mode. All frames are accepted regardless of address matching." %define _DESC447_ \ desc += "Media independent interface mode. Selects the external interface mode for\n"\ desc += "transmit and receive blocks.\n\n"\ desc += "Interface selection is chip-specific; see the chapter that describes how\n"\ desc += "modules are configured and connected." %define _DESC448_ \ desc += "Disable receive on transmit." %define _DESC449_ \ desc += "Internal loopback. If set, transmitted frames are looped back internal to the\n"\ desc += "device and transmit output signals are not asserted. The internal bus clock\n"\ desc += "substitutes for the FEC_TXCLK when LOOP is asserted. DRT must be set to 0 when\n"\ desc += "setting LOOP." %define _DESC450_ \ desc += "Transmit Control Register. The TCR configures the transmit block." %define _DESC451_ \ desc += "Receive frame control pause. This read-only status bit is asserted when a full\n"\ desc += "duplex flow control pause frame is received and the transmitter pauses for the\n"\ desc += "duration defined in this pause frame. This bit automatically clears when the\n"\ desc += "pause duration is complete." %define _DESC452_ \ desc += "Transmit frame control pause. Transmits a PAUSE frame when asserted. When this\n"\ desc += "bit is set, the MAC stops transmission of data frames after the current\n"\ desc += "transmission is complete. At this time, GRA interrupt in the EIR is asserted.\n"\ desc += "With transmission of data frames stopped, MAC transmits a MAC Control PAUSE\n"\ desc += "frame. Next, the MAC clears the TFC_PAUSE bit and resumes transmitting data\n"\ desc += "frames. If the transmitter pauses due to user assertion of GTS or reception of\n"\ desc += "a PAUSE frame, the MAC may continue transmitting a MAC Control PAUSE frame." %define _DESC453_ \ desc += "Full duplex enable. If set, frames transmit independent of carrier sense and\n"\ desc += "collision inputs. This field must be modified only when ECR[ETHER_EN] = 0." %define _DESC454_ \ desc += "Heartbeat control. If set, the heartbeat check performs following end of\n"\ desc += "transmission and the HB bit in the status register is set if the collision\n"\ desc += "input does not assert within the heartbeat window. This field must be modified\n"\ desc += "only when ECR[ETHER_EN] = 0." %define _DESC455_ \ desc += "Graceful transmit stop. When this bit is set, MAC stops transmission after any\n"\ desc += "frame currently transmitted is complete and GRA interrupt in the EIR is\n"\ desc += "asserted. If frame transmission is not currently underway, the GRA interrupt is\n"\ desc += "asserted immediately. After transmission finishes, clear GTS to restart. The\n"\ desc += "next frame in the transmit FIFO is then transmitted. If an early collision\n"\ desc += "occurs during transmission when GTS is set, transmission stops after the\n"\ desc += "collision. The frame is transmitted again after GTS is cleared. There may be\n"\ desc += "old frames in the transmit FIFO that transmit when GTS is reasserted. To avoid\n"\ desc += "this situation, program ECR[ETHER_EN] = 0 following the GRA interrupt." %define _DESC456_ \ desc += "Physical Address Low Register. PALR contains the lower 32 bits (bytes 0, 1, 2,\n"\ desc += "3) of the 48-bit address used in the address recognition process to compare\n"\ desc += "with the DA (destination address) field of receive frames with an individual\n"\ desc += "DA. In addition, this register is used in bytes 0 through 3 of the 6-byte\n"\ desc += "source address field when transmitting PAUSE frames.\n\n"\ desc += "This register is not reset and you must initialize it." %define _DESC457_ \ desc += "Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the\n"\ desc += "6-byte individual address are used for exact match and the source address field\n"\ desc += "in PAUSE frames." %define _DESC458_ \ desc += "Physical Address High Register and Type Field. PAUR contains the upper 16 bits\n"\ desc += "(bytes 4 and 5) of the 48-bit address used in the address recognition process\n"\ desc += "to compare with the DA (destination address) field of receive frames with an\n"\ desc += "individual DA. In addition, this register is used in bytes 4 and 5 of the\n"\ desc += "6-byte Source Address field when transmitting PAUSE frames. Bits 15:0 of PAUR\n"\ desc += "contain a constant type field (8808h) for transmission of PAUSE frames. The\n"\ desc += "upper 16 bits of this register are not reset and you must initialize them." %define _DESC459_ \ desc += "Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used\n"\ desc += "for exact match, and the source address field in PAUSE frames." %define _DESC460_ \ desc += "Type field in PAUSE frames. These 16 read-only bits are a constant value of\n"\ desc += "8808h." %define _DESC461_ \ desc += "Opcode/Pause Duration. The OPD contains the 16-bit opcode and 16-bit pause\n"\ desc += "duration fields used in transmission of a PAUSE frame. The opcode field is a\n"\ desc += "constant value, 0001h. When another node detects a PAUSE frame, that node\n"\ desc += "pauses transmission for the duration specified in the pause duration field.\n\n"\ desc += "The lower 16 bits of this register are not reset and you must initialize\n"\ desc += "them." %define _DESC462_ \ desc += "Opcode field used in PAUSE frames. These read-only bits are a constant,\n"\ desc += "0001h." %define _DESC463_ \ desc += "Pause Duration field used in PAUSE frames." %define _DESC464_ \ desc += "Descriptor Individual Upper Address Register. IAUR contains the upper 32 bits\n"\ desc += "of the 64-bit individual address hash table. The address recognition process\n"\ desc += "uses this table to check for a possible match with the destination address (DA)\n"\ desc += "field of receive frames with an individual DA.\n\n"\ desc += "This register is not reset and you must initialize it." %define _DESC465_ \ desc += "The upper 32 bits of the 64-bit hash table used in the address recognition\n"\ desc += "process for receive frames with a unicast address. Bit 31 of IADDR1 contains\n"\ desc += "hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32." %define _DESC466_ \ desc += "Descriptor Individual Lower Address Register. IALR contains the lower 32 bits\n"\ desc += "of the 64-bit individual address hash table. The address recognition process\n"\ desc += "uses this table to check for a possible match with the DA field of receive\n"\ desc += "frames with an individual DA.\n\n"\ desc += "This register is not reset and you must initialize it." %define _DESC467_ \ desc += "The lower 32 bits of the 64-bit hash table used in the address recognition\n"\ desc += "process for receive frames with a unicast address. Bit 31 of IADDR2 contains\n"\ desc += "hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0." %define _DESC468_ \ desc += "Descriptor Group Upper Address Register. GAUR contains the upper 32 bits of the\n"\ desc += "64-bit hash table used in the address recognition process for receive frames\n"\ desc += "with a multicast address.\n\n"\ desc += "This register is not reset and you must initialize it." %define _DESC469_ \ desc += "The GADDR1 register contains the upper 32 bits of the 64-bit hash table used in\n"\ desc += "the address recognition process for receive frames with a multicast address.\n"\ desc += "Bit 31 of GADDR1 contains hash index bit 63. Bit 0 of GADDR1 contains hash\n"\ desc += "index bit 32." %define _DESC470_ \ desc += "Descriptor Group Lower Address Register. GALR contains the lower 32 bits of the\n"\ desc += "64-bit hash table used in the address recognition process for receive frames\n"\ desc += "with a multicast address.\n\n"\ desc += "This register is not reset and you must initialize it." %define _DESC471_ \ desc += "The GADDR2 register contains the lower 32 bits of the 64-bit hash table used in\n"\ desc += "the address recognition process for receive frames with a multicast address.\n"\ desc += "Bit 31 of GADDR2 contains hash index bit 31. Bit 0 of GADDR2 contains hash\n"\ desc += "index bit 0." %define _DESC472_ \ desc += "Transmit FIFO Watermark. The TFWR controls the amount of data required in the\n"\ desc += "transmit FIFO before transmission of a frame can begin. This allows you to\n"\ desc += "minimize transmit latency (TFWR = 00 or 01) or allow for larger bus access\n"\ desc += "latency (TFWR = 11) due to contention for the system bus. Setting the watermark\n"\ desc += "to a high value minimizes the risk of transmit FIFO underrun due to contention\n"\ desc += "for the system bus. The byte counts associated with the TFWR field may need to\n"\ desc += "be modified to match a given system requirement (worst case bus access latency\n"\ desc += "by the transmit data DMA channel)." %define _DESC473_ \ desc += "Number of bytes written to transmit FIFO before transmission of a frame\n"\ desc += "begins" %define _DESC474_ \ desc += "FIFO Receive Bound Register. FRBR indicates the upper address bound of the FIFO\n"\ desc += "RAM. Drivers can use this value, along with the FRSR, to appropriately divide\n"\ desc += "the available FIFO RAM between the transmit and receive data paths." %define _DESC475_ \ desc += "Highest valid FIFO RAM address." %define _DESC476_ \ desc += "FIFO Receive Start Register. FRSR indicates the starting address of the receive\n"\ desc += "FIFO. FRSR marks the boundary between the transmit and receive FIFOs. The\n"\ desc += "transmit FIFO uses addresses from the start of the FIFO to the location four\n"\ desc += "bytes before the address programmed into the FRSR. The receive FIFO uses\n"\ desc += "addresses from FRSR to FRBR inclusive.\n\n"\ desc += "Hardware initializes the FRSR at reset. FRSR only needs to be written to change\n"\ desc += "the default value." %define _DESC477_ \ desc += "Address of first receive FIFO location. Acts as delimiter between receive and\n"\ desc += "transmit FIFOs.\n\n"\ desc += "For proper operation, ensure that R_FSTART is set to 48h or greater." %define _DESC478_ \ desc += "Receive Descriptor Ring Start Register. ERDSR points to the start of the\n"\ desc += "circular receive buffer descriptor queue in external memory. This pointer must\n"\ desc += "be 32-bit aligned; however, it is recommended it be made 128-bit aligned\n"\ desc += "(evenly divisible by 16). You should write zeros to bits 1 and 0. Hardware\n"\ desc += "ignores non-zero values in these two bit positions.\n\n"\ desc += "This register is undefined at reset and must be initialized prior to\n"\ desc += "operation." %define _DESC479_ \ desc += "Pointer to start of receive buffer descriptor queue." %define _DESC480_ \ desc += "Transmit Buffer Descriptor Ring Start Register. ETSDR provides a pointer to the\n"\ desc += "start of the circular transmit buffer descriptor queue in external memory. This\n"\ desc += "pointer must be 32-bit aligned; however, it is recommended it be made 128-bit\n"\ desc += "aligned (evenly divisible by 16). You should write zeros to bits 1 and 0.\n"\ desc += "Hardware ignores non-zero values in these two bit positions.\n\n"\ desc += "This register is undefined at reset and must be initialized prior to\n"\ desc += "operation." %define _DESC481_ \ desc += "Pointer to start of transmit buffer descriptor queue." %define _DESC482_ \ desc += "Receive Buffer Size Register. The EMRBR dictates the maximum size of all\n"\ desc += "receive buffers. This value should take into consideration that the receive CRC\n"\ desc += "is always written into the last receive buffer. To allow one maximum size frame\n"\ desc += "per buffer, EMRBR must be set to RCR[MAX_FL] or larger. To properly align the\n"\ desc += "buffer, EMRBR must be evenly divisible by 16. To ensure this, bits 3-0 are\n"\ desc += "forced low.\n\n"\ desc += "To minimize bus utilization (descriptor fetches), it is recommended that EMRBR\n"\ desc += "be greater than or equal to 256 bytes.\n\n"\ desc += "The EMRBR register is undefined at reset and must be initialized by the user." %define _DESC483_ \ desc += "Maximum size of receive buffer size in bytes. To minimize bus utilization\n"\ desc += "(descriptor fetches), set this field to 256 bytes (10h) or larger.\n\n"\ desc += "10h: 256 + 15 bytes (minimum size recommended)\n\n"\ desc += "11h: 272 + 15 bytes\n\n"\ desc += "...\n\n"\ desc += "7Fh: 2032 + 15 bytes. The FEC writes up to 2047 bytes in the receive buffer. If\n"\ desc += "data larger than 2047 is received, the FEC truncates it and shows 7FFh in the\n"\ desc += "receive descriptor" %define _DESC484_ \ desc += "Count of frames not counted correctly. " %define _DESC485_ \ desc += "Count of frames not counted correctly" %define _DESC486_ \ desc += "RMON Tx packet count. " %define _DESC487_ \ desc += "RMON Tx packet count" %define _DESC488_ \ desc += "RMON Tx broadcast packets. " %define _DESC489_ \ desc += "RMON Tx broadcast packets" %define _DESC490_ \ desc += "RMON Tx multicast packets. " %define _DESC491_ \ desc += "RMON Tx multicast packets" %define _DESC492_ \ desc += "RMON Tx packets with CRC/align error. " %define _DESC493_ \ desc += "RMON Tx packets with CRC/align error" %define _DESC494_ \ desc += "RMON Tx packets < 64 bytes, good CRC. " %define _DESC495_ \ desc += "RMON Tx packets < 64 bytes, good CRC" %define _DESC496_ \ desc += "RMON Tx packets > MAX_FL bytes, good CRC. " %define _DESC497_ \ desc += "RMON Tx packets > MAX_FL bytes, good CRC" %define _DESC498_ \ desc += "RMON Tx packets < 64 bytes, bad CRC. " %define _DESC499_ \ desc += "RMON Tx packets < 64 bytes, bad CRC" %define _DESC500_ \ desc += "RMON Tx packets > MAX_FL bytes, bad CRC. " %define _DESC501_ \ desc += "RMON Tx packets > MAX_FL bytes, bad CRC" %define _DESC502_ \ desc += "RMON Tx collision count. " %define _DESC503_ \ desc += "RMON Tx collision count" %define _DESC504_ \ desc += "RMON Tx 64 byte packets. " %define _DESC505_ \ desc += "RMON Tx 64 byte packets" %define _DESC506_ \ desc += "RMON Tx 65 to 127 byte packets. " %define _DESC507_ \ desc += "RMON Tx 65 to 127 byte packets" %define _DESC508_ \ desc += "RMON Tx 128 to 255 byte packets. " %define _DESC509_ \ desc += "RMON Tx 128 to 255 byte packets" %define _DESC510_ \ desc += "RMON Tx 256 to 511 byte packets. " %define _DESC511_ \ desc += "RMON Tx 256 to 511 byte packets" %define _DESC512_ \ desc += "RMON Tx 512 to 1023 byte packets. " %define _DESC513_ \ desc += "RMON Tx 512 to 1023 byte packets" %define _DESC514_ \ desc += "RMON Tx 1024 to 2047 byte packets. " %define _DESC515_ \ desc += "RMON Tx 1024 to 2047 byte packets" %define _DESC516_ \ desc += "RMON Tx packets with > 2048 bytes. " %define _DESC517_ \ desc += "RMON Tx packets with > 2048 bytes" %define _DESC518_ \ desc += "RMON Tx Octets. " %define _DESC519_ \ desc += "RMON Tx Octets" %define _DESC520_ \ desc += "Count of transmitted frames not counted correctly. " %define _DESC521_ \ desc += "Count of transmitted frames not counted correctly" %define _DESC522_ \ desc += "Frames transmitted OK. " %define _DESC523_ \ desc += "Frames transmitted OK" %define _DESC524_ \ desc += "Frames transmitted with single collision. " %define _DESC525_ \ desc += "Frames transmitted with single collision" %define _DESC526_ \ desc += "Frames transmitted with multiple collisions. " %define _DESC527_ \ desc += "Frames transmitted with multiple collisions" %define _DESC528_ \ desc += "Frames transmitted after deferral delay. " %define _DESC529_ \ desc += "Frames transmitted after deferral delay" %define _DESC530_ \ desc += "Frames transmitted with late collision. " %define _DESC531_ \ desc += "Frames transmitted with late collision" %define _DESC532_ \ desc += "Frames transmitted with excessive collisions. " %define _DESC533_ \ desc += "Frames transmitted with excessive collisions" %define _DESC534_ \ desc += "Frames transmitted with Tx FIFO underrun. " %define _DESC535_ \ desc += "Frames transmitted with Tx FIFO underrun" %define _DESC536_ \ desc += "Frames transmitted with carrier sense error. " %define _DESC537_ \ desc += "Frames transmitted with carrier sense error" %define _DESC538_ \ desc += "Frames transmitted with SQE error. " %define _DESC539_ \ desc += "Frames transmitted with SQE error" %define _DESC540_ \ desc += "Flow control pause frames transmitted. " %define _DESC541_ \ desc += "Flow control pause frames transmitted" %define _DESC542_ \ desc += "Octet count for frames transmitted without error. " %define _DESC543_ \ desc += "Octet count for frames transmitted without error" %define _DESC544_ \ desc += "Count of received frames not counted correctly. " %define _DESC545_ \ desc += "Count of received frames not counted correctly" %define _DESC546_ \ desc += "RMON Rx packet count. " %define _DESC547_ \ desc += "RMON Rx packet count" %define _DESC548_ \ desc += "RMON Rx broadcast packets. " %define _DESC549_ \ desc += "RMON Rx broadcast packets" %define _DESC550_ \ desc += "RMON Rx multicast packets. " %define _DESC551_ \ desc += "RMON Rx multicast packets" %define _DESC552_ \ desc += "RMON Rx packets with CRC/Align error. " %define _DESC553_ \ desc += "RMON Rx packets with CRC/Align error" %define _DESC554_ \ desc += "RMON Rx packets < 64 bytes, good CRC. " %define _DESC555_ \ desc += "RMON Rx packets < 64 bytes, good CRC" %define _DESC556_ \ desc += "RMON Rx packets > MAX_FL bytes, good CRC. " %define _DESC557_ \ desc += "RMON Rx packets > MAX_FL bytes, good CRC" %define _DESC558_ \ desc += "RMON Rx packets < 64 bytes, bad CRC. " %define _DESC559_ \ desc += "RMON Rx packets < 64 bytes, bad CRC" %define _DESC560_ \ desc += "RMON Rx packets > MAX_FL bytes, bad CRC. " %define _DESC561_ \ desc += "RMON Rx packets > MAX_FL bytes, bad CRC" %define _DESC562_ \ desc += "Reserved. " %define _DESC563_ \ desc += "RMON Rx 64 byte packets. " %define _DESC564_ \ desc += "RMON Rx 64 byte packets" %define _DESC565_ \ desc += "RMON Rx 65 to 127 byte packets. " %define _DESC566_ \ desc += "RMON Rx 65 to 127 byte packets" %define _DESC567_ \ desc += "RMON Rx 128 to 255 byte packets. " %define _DESC568_ \ desc += "RMON Rx 128 to 255 byte packets" %define _DESC569_ \ desc += "RMON Rx 256 to 511 byte packets. " %define _DESC570_ \ desc += "RMON Rx 256 to 511 byte packets" %define _DESC571_ \ desc += "RMON Rx 512 to 1023 byte packets. " %define _DESC572_ \ desc += "RMON Rx 512 to 1023 byte packets" %define _DESC573_ \ desc += "RMON Rx 1024 to 2047 byte packets. " %define _DESC574_ \ desc += "RMON Rx 1024 to 2047 byte packets" %define _DESC575_ \ desc += "RMON Rx packets with > 2048 bytes. " %define _DESC576_ \ desc += "RMON Rx packets with > 2048 bytes" %define _DESC577_ \ desc += "RMON Rx octets. " %define _DESC578_ \ desc += "RMON Rx octets" %define _DESC579_ \ desc += "Frames received OK. " %define _DESC580_ \ desc += "Frames received OK" %define _DESC581_ \ desc += "Frames received with CRC error. " %define _DESC582_ \ desc += "Frames received with CRC error" %define _DESC583_ \ desc += "Frames received with alignment error. " %define _DESC584_ \ desc += "Frames received with alignment error" %define _DESC585_ \ desc += "Receive FIFO overflow count. " %define _DESC586_ \ desc += "Receive FIFO overflow count" %define _DESC587_ \ desc += "Flow control pause frames received. " %define _DESC588_ \ desc += "Flow control pause frames received" %define _DESC589_ \ desc += "Octet count for frames received without error. " %define _DESC590_ \ desc += "Octet count for frames received without error" %define _DESC591_ \ desc += "GTM Module Configuration Register. The GTMMCR contains the control bits to\n"\ desc += "configure the general operation of the GTMINT and GTM-IP Module.\n\n"\ desc += ".\n\n"\ desc += "GTMMCR register functions are as shown in the following table." %define _DESC592_ \ desc += "Saf1276 - Safety-criticalMDIS\n\n"\ desc += "Module Disable. The MDIS bit puts the GTMINT Module in stop/disabled mode.\n"\ desc += "Communication through the slave-bus Interface is ignored in this mode except\n"\ desc += "reads/writes to the GTMMCR and reads from other integration registers which are\n"\ desc += "allowed." %define _DESC593_ \ desc += "Saf1276 - Safety-relevantAEISREN\n\n"\ desc += "AEI interface soft-reset control enable. The AEISREN bit enables the soft-reset\n"\ desc += "of the AEI interface that is controlled by AEISRST bit in the GTMMAEICR. Please\n"\ desc += "refer to #Rcy86050 for more details." %define _DESC594_ \ desc += "Saf1276 - Safety-latent STPS\n\n"\ desc += "Stop Mode Status. The STPS bit indicates the GTM-IP Module is in stop mode, or\n"\ desc += "by MDIS bit field setting or by stop line request. Please refer to #Rcy55044\n"\ desc += "for more details." %define _DESC595_ \ desc += "GTM Interrupts Clear Register. The GTMINTCLR contains the control bits to clear\n"\ desc += "some specific interrupt request output.\n\n"\ desc += ".\n\n"\ desc += "GTMINTCLR register functions are as shown in the following table." %define _DESC596_ \ desc += "Saf1276 - Safety-relevantINTCLR_PTR\n\n"\ desc += "Interrupt Clear Pointer. This field value indicates / selects which interrupt\n"\ desc += "will be cleared. The correspondence between the number and the interrupt is\n"\ desc += "given in #Rcy22726 . Please refer to #Rcy85244 for more details." %define _DESC597_ \ desc += "GTM AEI Control Register. The GTMMAEICR contains the control bits to the AEI\n"\ desc += "interface in GTM-IP.\n\n"\ desc += ".\n\n"\ desc += "GTMMAEICR register functions are as shown in the following table." %define _DESC598_ \ desc += "Saf1276 - Safety-relevantAEISRST\n\n"\ desc += "AEI interface soft-reset control. The AEISRST bit when set applies a reset on\n"\ desc += "the GTM-IP AEI interface. The set is enabled by the AEISREN bit in the GTMMCR.\n"\ desc += "This is a self clear bit and is always read as 0. Please refer to #Rcy86050\n"\ desc += "for more details." %define _DESC599_ \ desc += "INTC Block Configuration Register. The Block Configuration Register is used to\n"\ desc += "configure options of the INTC." %define _DESC600_ \ desc += "Hardware vector enable. Controls whether the INTC is in hardware vector mode or\n"\ desc += "software vector mode. See Modes of operation for the details of the handshaking\n"\ desc += "with the processor in each mode." %define _DESC601_ \ desc += "INTC Current Priority Register for Processor n. The INTC_CPRn masks any\n"\ desc += "peripheral or software-settable interrupt request that is set at the same or\n"\ desc += "lower priority as the current value of the INTC_CPR n [PRI] field from\n"\ desc += "generating an interrupt request to the processor . When the INTC Interrupt\n"\ desc += "Acknowledge register (INTC_IACKR n ) is read in software vector mode or the\n"\ desc += "interrupt acknowledge signal from the processor is asserted in hardware vector\n"\ desc += "mode, the value of PRI is pushed onto the LIFO, and PRI is updated with the\n"\ desc += "priority of the preempting interrupt request. When the INTC end-of-interrupt\n"\ desc += "register (INTC_EOIR n ) is written, the LIFO is popped into the INTC_CPR n PRI\n"\ desc += "field. An exception case in hardware vector mode to this behavior is described\n"\ desc += "in Hardware vector mode .\n\n"\ desc += "The masking priority can be raised or lowered by writing to the PRI field,\n"\ desc += "supporting the priority ceiling protocol. See Priority ceiling protocol .\n\n"\ desc += "A store to modify the PRI field that closely precedes or follows an access to a\n"\ desc += "shared resource may result in a non-coherent access to that resource. See\n"\ desc += "Ensuring coherency for example code to ensure coherency." %define _DESC602_ \ desc += "Priority of the currently executing ISR, according to the field values 63\n"\ desc += "(highest priority) down to 0 (lowest priority)." %define _DESC603_ \ desc += "INTC Interrupt Acknowledge Register for Processor n. The Interrupt Acknowledge\n"\ desc += "Register for Processor n provides a value which can be used to load the address\n"\ desc += "of an ISR from a vector table. The vector table can be composed of addresses of\n"\ desc += "the ISRs specific to their respective interrupt vectors.\n\n"\ desc += "Also, in software vector mode, the INTC_IACKR n has side effects from reads.\n"\ desc += "Therefore, it must not be read speculatively while in this mode. The side\n"\ desc += "effects are the same regardless of the size of the read. Reading the\n"\ desc += "INTC_IACKRn does not have side effects in hardware vector mode.\n\n"\ desc += "When the corresponding INTC_BCR[HVENn] = 1, a read of the INTC_IACKR has no\n"\ desc += "side effects." %define _DESC604_ \ desc += "Vector table base address. Can be the base address of a vector table of\n"\ desc += "addresses of ISRs." %define _DESC605_ \ desc += "Interrupt vector. Vector of the peripheral or software-settable interrupt\n"\ desc += "request that caused the interrupt request to the processor. When the interrupt\n"\ desc += "request to the processor asserts, the INTVEC is updated, whether the INTC is in\n"\ desc += "software or hardware vector mode." %define _DESC606_ \ desc += "INTC End Of Interrupt Register for Processor n. Writing to the INTC_EOIR n\n"\ desc += "signals the end of the servicing of the interrupt request. When the INTC_EOIR n\n"\ desc += "is written, the priority last pushed on the LIFO is popped into INTC_CPR n .\n"\ desc += "The values and size of data written to the INTC_EOIR n are ignored. Those\n"\ desc += "values and sizes written to this register neither update the INTC_EOIR n\n"\ desc += "contents nor affect whether the LIFO pops. When you write to this register,\n"\ desc += "write four all-zero bytes." %define _DESC607_ \ desc += "End of Interrupt. Write four all-zero bytes to this field to signal the end of\n"\ desc += "the servicing of an interrupt request." %define _DESC608_ \ desc += "INTC Software Set/Clear Interrupt Register. The INTC_SSCIR registers support\n"\ desc += "the setting or clearing of software-settable interrupt requests. These\n"\ desc += "registers contain independent sets of bits to set and clear a corresponding\n"\ desc += "flag bit by software. Unlike the SWT bit in the PSRs, the INTC_SSCIR registers\n"\ desc += "do not require a read-modify-write. With the exception of being set by\n"\ desc += "software, this flag bit behaves the same as a flag bit set within a peripheral.\n"\ desc += "This flag bit generates an interrupt request within the INTC just like a\n"\ desc += "peripheral interrupt request. Writing a 1 to SETn will leave SETn unchanged at\n"\ desc += "0 but will set CLRn. Writing a 0 to SETn will have no effect. CLRn is the flag\n"\ desc += "bit. Writing a 1 to CLRn will clear it. Writing a 0 to CLRn will have no\n"\ desc += "effect. If a 1 is written to a pair of SETn and CLRn bits at the same time,\n"\ desc += "CLRn is asserted, regardless of whether CLRn was asserted before the write." %define _DESC609_ \ desc += "Set flag bits. Writing a 1 will set the corresponding CLRn bit. Writing a 0\n"\ desc += "will have no effect. Each SETn is always read as a 0." %define _DESC610_ \ desc += "Clear flag bits. CLRn is the flag bit. Writing a 1 to CLRn will clear it\n"\ desc += "provided that a 1 is not written simultaneously to its corresponding SETn bit.\n"\ desc += "Writing a 0 to CLRn will have no effect." %define _DESC611_ \ desc += "INTC Priority Select Register. The Priority Select Registers support the\n"\ desc += "selection of an individual priority for each source of interrupt request, and\n"\ desc += "the routing of the request to one or more processors. The unique vector of\n"\ desc += "each peripheral or software-settable interrupt request determines which\n"\ desc += "INTC_PSRn is assigned to that interrupt request. The peripheral interrupt\n"\ desc += "requests are assigned vectors 32-1023, and their priorities are configured in\n"\ desc += "INTC_PSR32-1023, respectively.\n\n"\ desc += "Unlike the peripheral interrupt request PSRs, there is no SWT bit in the PSRs\n"\ desc += "corresponding to the software-settable interrupt requests. Interrupts are not\n"\ desc += "detected while the PSRs are being written." %define _DESC612_ \ desc += "Processor select bits. If an interrupt source is enabled, PRC_SEL n [3:0]\n"\ desc += "selects whether the interrupt request is to be sent to processor 0, processor\n"\ desc += "1, processor 2, processor 3, or any combination." %define _DESC613_ \ desc += "This bit is only available in PSRs that do not correspond to the SSCIRs. The\n"\ desc += "SWT bit supports triggering an interrupt by software rather than hardware. This\n"\ desc += "is an alternative to setting a flag bit in a peripheral. This flag bit\n"\ desc += "generates an interrupt request within the INTC just like a peripheral interrupt\n"\ desc += "request. Writing a '1' to SWT n sets the bit. On the interrupt acknowledge\n"\ desc += "cycle, the SWT n bit is cleared. The SWT function works both in hardware and\n"\ desc += "software vector mode. It is only cleared by the enabled Processor(s) defined in\n"\ desc += "the PRC_SEL n field of the PSR." %define _DESC614_ \ desc += "Priority select. Selects the priority for the interrupt requests. PRI has\n"\ desc += "values 63 (highest priority) down to 0 (lowest priority)." %define _DESC615_ \ desc += "IRCOSC Control Register. The IRCOSC_CTL contains user programmable parameters\n"\ desc += "for user frequency trim, output IRCOSC divider and dynamic element matching in\n"\ desc += "the IRCOSC.\n\n"\ desc += "IRCOSC_CTL is writable only in supervisor mode." %define _DESC616_ \ desc += "This bit can be written with any value, but writes are ignored. A read returns\n"\ desc += "last written value." %define _DESC617_ \ desc += "User trimming bits with respect to nominal factory frequency\n\n"\ desc += "The MSB of the USER_TRIM bits is used to determine whether the frequency will\n"\ desc += "be increased or decreased. If MSB = 0 then a change in USER_TRIM[3:0] will\n"\ desc += "decrease the frequency, and likewise, if MSB = 1 then a change in\n"\ desc += "USER_TRIM[3:0] will increase the frequency. Frequency trimming calculation\n"\ desc += "shows how RCOSC_CTL[USER_TRIM] field is used to trim the IRCOSC frequency." %define _DESC618_ \ desc += "This field can be written at any time, but writes have no effect. Reads return\n"\ desc += "the previously written value." %define _DESC619_ \ desc += "This field may sometimes have the value of 1, and can be cleared by writing a 1\n"\ desc += "to this bit. However, this field has no effect on the IRCOSC or chip behavior." %define _DESC620_ \ desc += "IRCOSC Native Trimming Register. The IRCOSC_NT register contains trim values\n"\ desc += "loaded from TEST flash memory for the RC oscillator. Its status is enabled for\n"\ desc += "voltage regulator and temperature sensor. This register is read only." %define _DESC621_ \ desc += "Enables voltage regulator-trimming value for safety check" %define _DESC622_ \ desc += "Enables temperature sensor-trimming value for safety check" %define _DESC623_ \ desc += "IRCOSC trimming value for safety check" %define _DESC624_ \ desc += "IRCOSC Temperature Trimming Register. The IRCOSC_TT registers contains system\n"\ desc += "trimming values for the IRCOSC that are loaded from TEST flash memory during\n"\ desc += "reset. IRCOSC_TT is a read only register." %define _DESC625_ \ desc += "Cold temperature trimming value for safety check" %define _DESC626_ \ desc += "Hot temperature trimming value for safety check" %define _DESC627_ \ desc += "Ambient temperature reference code value for safety check" %define _DESC628_ \ desc += "LFAST Mode Configuration Register. " %define _DESC629_ \ desc += "LFAST Master or Slave mode Enable. This bit selects either the LFAST master or\n"\ desc += "slave functionality. This bit can be written only once after the asynchronous\n"\ desc += "reset." %define _DESC630_ \ desc += "Control bit to enable support for IPG Debug mode. This mode is indicated by\n"\ desc += "assertion of IPG debug mode signal." %define _DESC631_ \ desc += "Selects the fraction of sysclk in Low Speed Select mode. Refer to #Rdb75385\n"\ desc += "for more detailed description." %define _DESC632_ \ desc += "LFAST Enable. This bit enables/disables the reception and transfer of LFAST\n"\ desc += "device." %define _DESC633_ \ desc += "LFAST Receiver Enable. This bit controls the reception of the frames and\n"\ desc += "decoding on the LFAST device. This bit also disables the Rx LVDS LR." %define _DESC634_ \ desc += "LFAST Transmitter Enable. This bit controls the transmission of frames from the\n"\ desc += "LFAST device and disables the Tx LVDS LD. This bit can also be set and cleared\n"\ desc += "by LFAST slave H/W on reception of an ICLC command frame." %define _DESC635_ \ desc += "Tx Arbiter Disable. This bit enables/disables the Tx block arbiter. Current\n"\ desc += "frame transfer is completed, but new frame requests are ignored." %define _DESC636_ \ desc += "CTS Enable. This bit defines the Push-Pull mode of the LFAST devices receiver.\n"\ desc += "This bit is used to enable/disable CTS mode of the Tx block. It is only\n"\ desc += "writable when MCR[DRFEN] = 0." %define _DESC637_ \ desc += "LFAST Soft Reset. This bit is automatically cleared after reset." %define _DESC638_ \ desc += "DATA Frame Enable. This bit enables/disables the transmission and reception of\n"\ desc += "data frames between the LFAST master and slave devices." %define _DESC639_ \ desc += "LFAST Speed Control Register. The SCR is used to configure the Rx and Tx data\n"\ desc += "rate of the LFAST." %define _DESC640_ \ desc += "Data Rate Controller mode. Defines the mode setting for LFAST slave device by\n"\ desc += "S/W or LFAST master.\n\n"\ desc += "In LFAST Master the SCR[DRMD] should be 0.\n\n"\ desc += "Only writable when MCR[DRFEN] = 0." %define _DESC641_ \ desc += "Receiver Data Rate. This bit defines the receiver data rate.\n\n"\ desc += "For LFAST Master:\n\n"\ desc += "S/W should program this bit only after transmission of an ICLC frame changing\n"\ desc += "the speed mode of the slaves Tx interface. For LFAST Slave:\n\n"\ desc += "When SCR[DRMD] = 1, the H/W programs this bit on reception of ICLC frame for\n"\ desc += "changing speed mode of Slaves Rx interface. The S/W can program this bit when\n"\ desc += "SCR[DRMD] = 0. This bit is cleared on MCR[DRFEN] negation." %define _DESC642_ \ desc += "Transmit Data Rate. This bit defines the transmitter data rate.\n\n"\ desc += "For LFAST Master:\n\n"\ desc += "The S/W should program this bit only after transmission of an ICLC frame\n"\ desc += "changing the speed mode of the slaves Rx interface. For LFAST Slave:\n\n"\ desc += "When SCR[DRMD] = 1, the H/W writes this bit on receipt of an ICLC frame\n"\ desc += "changing the speed mode of the slaves Tx interface. The S/W can program this\n"\ desc += "bit when SCR[DRMD] = 0. This bit is cleared on MCR[DRFEN] = 0." %define _DESC643_ \ desc += "LFAST Correlator Control Register. The COCR is used to select the sampler data\n"\ desc += "path and the number of bits of correlation to be used.\n\n"\ desc += "The fields in this register are only writable only when MCR[RXEN] = 0" %define _DESC644_ \ desc += "Sampler Data Path Selector (overrides the correlator selection). Defines the\n"\ desc += "sampler data path to be activated at all the times. All the bits should be 0\n"\ desc += "(00h) for Sampler Data Path to be selected by the correlator. In Low Speed mode\n"\ desc += "only Sampler Data Paths 0-3 are valid.\n\n"\ desc += "00h: Sampler Data Path selected by correlator\n\n"\ desc += "01h: Sampler Data Path 0 selected\n\n"\ desc += "02h: Sampler Data Path 1 selected\n\n"\ desc += "04h: Sampler Data Path 2 selected\n\n"\ desc += "08h: Sampler Data Path 3 selected\n\n"\ desc += "10h: Sampler Data Path 4 selected\n\n"\ desc += "20h: Sampler Data Path 5 selected\n\n"\ desc += "40h: Sampler Data Path 6 selected\n\n"\ desc += "others: Sampler Data Path 7 selected" %define _DESC645_ \ desc += "Correlator threshold level. Defines the correlation threshold level.\n\n"\ desc += "000: 9 Bits of correlation\n\n"\ desc += "001: 10 Bits of correlation\n\n"\ desc += "...\n\n"\ desc += "110: 15 Bits of correlation\n\n"\ desc += "111: 16 Bits of correlation" %define _DESC646_ \ desc += "LFAST Test Mode Control Register. The TMCR enables and configures the LFAST\n"\ desc += "clock test and loopback modes\n\n"\ desc += "." %define _DESC647_ \ desc += "Clock Test mode. S/W can define when the clock test mode is enabled. This bit\n"\ desc += "can also be set and cleared by LFAST slave H/W on reception of an ICLC\n"\ desc += "command." %define _DESC648_ \ desc += "Loopback mode Logic Enable. S/W can define when the loopback logic is enabled.\n"\ desc += "This bit can also be written by LFAST slave H/W on reception of an ICLC\n"\ desc += "command." %define _DESC649_ \ desc += "Loopback mode. Defines the type of loopback mode enabled.\n\n"\ desc += "000: Rx loopback\n\n"\ desc += "001: Rx LVDS loopback\n\n"\ desc += "010: Tx loopback without automatic frame generation\n\n"\ desc += "011: Tx loopback with automatic frame generation\n\n"\ desc += "100: Tx LVDS loopback (external) with automatic frame generation\n\n"\ desc += "Others - Reserved (should not be written by S/W)\n\n"\ desc += "Writable only when TMCR[LPON] = 0." %define _DESC650_ \ desc += "Loopback check mode valid pass frames threshold value. Defines the number of\n"\ desc += "frames to verify before setting GCR[LPFPDV] when running in Automatic Loopback\n"\ desc += "Frame mode. The loopback frame is considered pass when the payload is CBh,\n"\ desc += "header is 13h and sync is valid. This mode is valid only when TMCR[LPMOD] =\n"\ desc += "011b or TMCR[LPMOD] = 100b.\n\n"\ desc += "0000h: Reserved.(Not to be used)\n\n"\ desc += "0001h: Check 1 frame have correct sync, header and payload.\n\n"\ desc += "...\n\n"\ desc += "FFFEh: Check 65534 frames have correct sync, header and payload.\n\n"\ desc += "FFFFh: Check 65535 frames have correct sync, header and payload.\n\n"\ desc += "Writable only when TMCR[LPON] = 0." %define _DESC651_ \ desc += "LFAST Auto Loopback Control Register. The fields in this register are writable\n"\ desc += "only when TMCR[LPON] = 0." %define _DESC652_ \ desc += "Auto Loopback Frame Transmission Count Enable. Enables fixed number of auto\n"\ desc += "predefined loopback frame transmission." %define _DESC653_ \ desc += "Auto Loopback Frame Transmission Count. Defines the number of predefined auto\n"\ desc += "loopback frames to be sent. The predefined loopback frame has payload CBh,\n"\ desc += "header 13h and valid sync. This mode is valid if TMCR[LPMOD] = 011b or\n"\ desc += "TMCR[LPMOD] = 100b.\n\n"\ desc += "0000h: Reserved.(Not to be used)\n\n"\ desc += "0001h: Send 1 frame with correct sync, header and payload\n\n"\ desc += "...\n\n"\ desc += "FFFEh: Send 65534 frames with correct sync, header and payload\n\n"\ desc += "FFFFh: Send 65535 frames with correct sync, header and payload" %define _DESC654_ \ desc += "LFAST Rate Change Delay Control Register. " %define _DESC655_ \ desc += "Data Rate Controller Counter Value. Defines the number of cycles of Phase 0\n"\ desc += "clock needed by the Tx interface Data rate change controller to switch from one\n"\ desc += "speed mode to another. The arbitrator ignores all requests during this\n"\ desc += "period.\n\n"\ desc += "0h: 0 cycles\n\n"\ desc += "1h: 1 cycles\n\n"\ desc += "...\n\n"\ desc += "Eh: 14 cycles\n\n"\ desc += "Fh: 15 cycles\n\n"\ desc += "Only writable when MCR[DRFEN] = 1." %define _DESC656_ \ desc += "LFAST Wakeup Delay Control Register. The fields in this register are only\n"\ desc += "writable when MCR[DRFEN] = 0." %define _DESC657_ \ desc += "High Speed Sleep mode Exit Time. Defines 1/4 of the number of the high speed\n"\ desc += "clock cycle wait after the negation of the LVDS LD sleep signal, and before the\n"\ desc += "start of new frame. This wait is the summation of settling time of the Line\n"\ desc += "Driver (LD) after negation of its sleep signal, and the wakeup time of the LR\n"\ desc += "of the peer LFAST.\n\n"\ desc += "00h: 0 cycle\n\n"\ desc += "01h: 1 cycle\n\n"\ desc += "?\n\n"\ desc += "12h: 18 cycles (200 ns + 8 cycles of High speed clock)\n\n"\ desc += "...\n\n"\ desc += "FEh: 254 cycles\n\n"\ desc += "FFh: 255 cycles" %define _DESC658_ \ desc += "Low Speed Sleep mode Exit Time. Defines 1/4 of the number of Low speed clock\n"\ desc += "cycle wait after the negation of LVDS LD sleep signal, and before the start of\n"\ desc += "new frame. This wait is the summation of settling time of LD after negation of\n"\ desc += "LVDS LD sleep signal, and the wakeup time of the LR of the peer LFAST.\n\n"\ desc += "0h: 0 cycle\n\n"\ desc += "1h: 1 cycle (200ns + 1 cycle of Low speed clock)\n\n"\ desc += "...\n\n"\ desc += "Eh: 14 cycles\n\n"\ desc += "Fh: 15 cycles" %define _DESC659_ \ desc += "Wake Up time for the LD. Defines the 1/4 of the number of High speed clock\n"\ desc += "cycles used during the wakeup of the LD from shutdown mode. This is time\n"\ desc += "required by the LD to move from moving from Shutdown to Normal State in High\n"\ desc += "speed mode.\n\n"\ desc += "00h: 0 cycles\n\n"\ desc += "01h: 1 cycle\n\n"\ desc += "...\n\n"\ desc += "5Fh: 95 cycles (1.18 us)\n\n"\ desc += "?\n\n"\ desc += "FFh: 255 cycles Maximum" %define _DESC660_ \ desc += "Wake Up time for the LD. Defines the 1/4 of the number Low speed clock used\n"\ desc += "during the wakeup of the LD from shutdown mode. This is time required by the LD\n"\ desc += "to move from Shutdown to Normal State in Low speed mode.\n\n"\ desc += "0h: 0 cycle\n\n"\ desc += "1h: 1 cycle\n\n"\ desc += "2h: 2 cycles (1.18 us)\n\n"\ desc += "...\n\n"\ desc += "Eh: 14 cycles\n\n"\ desc += "Fh: 15 cycles" %define _DESC661_ \ desc += "LFAST ICLC Control Register. " %define _DESC662_ \ desc += "ICLC enabled. This bit should be set whenever the S/W is performing a series of\n"\ desc += "ICLC frame transfers. This bit ensures only ICLC frame transmission request is\n"\ desc += "serviced, other pending frames request are ignored." %define _DESC663_ \ desc += "ICLC frame request. This bit is set to initiate the transfer of ICLC frame by\n"\ desc += "LFAST master. This bit should be set (ICR[SNDICLC] = 1) after writing the\n"\ desc += "required ICLC payload to be transmitted in the ICLCPLD field of the register.\n"\ desc += "This bit is self clearing, which will be cleared when ICLC frame transfer is\n"\ desc += "complete." %define _DESC664_ \ desc += "ICLC Payload. This field is used to program the payload of the ICLC frame to be\n"\ desc += "transmitted. New ICLC payload should be set when ICR[SNDICLC] = 0.\n\n"\ desc += "Refer to #Rdb45431 for supported ICLC payloads." %define _DESC665_ \ desc += "LFAST Ping Control Register. " %define _DESC666_ \ desc += "Ping Response Frame Request. This bit is set to initiate the transfer of Ping\n"\ desc += "response frame. Cleared after transmission of Ping response frame." %define _DESC667_ \ desc += "Ping Response Enable. Defines when ping response should be automatically sent\n"\ desc += "on reception of Ping ICLC frame from LFAST master\n\n"\ desc += "Only writable when MCR[DRFEN] = 0." %define _DESC668_ \ desc += "LFAST Slave: Defines the LFAST slaves ping reply frame payload content.\n\n"\ desc += "LFAST Master: Defines the expected payload of ping response frame. Used for\n"\ desc += "comparison with ping frame received.\n\n"\ desc += "Only writable when MCR[DRFEN] = 0." %define _DESC669_ \ desc += "LFAST Rx FIFO CTS Control Register. The fields in this register are only\n"\ desc += "writable when MCR[DRFEN] = 0." %define _DESC670_ \ desc += "Rx FIFO Maximum Threshold. Defines the condition for CTS bit of frames to be\n"\ desc += "negated." %define _DESC671_ \ desc += "Rx FIFO Minimum Threshold. Defines the condition for CTS bit of frames to be\n"\ desc += "set." %define _DESC672_ \ desc += "LFAST Tx Interrupt Enable Register. " %define _DESC673_ \ desc += "Tx Data Interface Not Enabled - (Mask) Enables or disables the interrupt. Tx\n"\ desc += "Data Interface not enabled and a frame is ready to be transmitted" %define _DESC674_ \ desc += "Transmit Data FIFO Overflow Interrupt Enable." %define _DESC675_ \ desc += "Ping Response Frame Transmitted Interrupt Enable." %define _DESC676_ \ desc += "Unsolicited Frame transmitted Interrupt Enable" %define _DESC677_ \ desc += "ICLC Frame transmitted Interrupt Enable" %define _DESC678_ \ desc += "Data Frame transmitted Interrupt Enable" %define _DESC679_ \ desc += "LFAST Rx Interrupt Enable Register. " %define _DESC680_ \ desc += "Unsolicited frame register overflow. Indicates existing unsolicited frame has\n"\ desc += "not been read and a new unsolicited frame has arrived." %define _DESC681_ \ desc += "Rx Data FIFO Min Threshold reached" %define _DESC682_ \ desc += "Rx Data FIFO Max Threshold reached" %define _DESC683_ \ desc += "Rx Data FIFO Underflow" %define _DESC684_ \ desc += "Rx Data FIFO Overflow" %define _DESC685_ \ desc += "Frame with unsupported frame size received. Valid frame sizes are defined in \n"\ desc += "#Rdb17314 ." %define _DESC686_ \ desc += "Invalid ICLC code Received" %define _DESC687_ \ desc += "Invalid Logical Channel Type" %define _DESC688_ \ desc += "Frame with CTS bit Low Received" %define _DESC689_ \ desc += "Data frame received" %define _DESC690_ \ desc += "Unsolicited Frame received" %define _DESC691_ \ desc += "LFAST Rx ICLC Interrupt Enable Register. " %define _DESC692_ \ desc += "Ping Frame Response failed" %define _DESC693_ \ desc += "Ping Frame Response successful" %define _DESC694_ \ desc += "ICLC frame for Ping Frame Request received" %define _DESC695_ \ desc += "ICLC frame for Test mode off received" %define _DESC696_ \ desc += "ICLC frame for Loopback On received" %define _DESC697_ \ desc += "ICLC frame for Clk Test mode on received" %define _DESC698_ \ desc += "ICLC frame for LFAST Slaves Tx Interface Disable received" %define _DESC699_ \ desc += "ICLC frame for LFAST Slaves Tx Interface Enable received" %define _DESC700_ \ desc += "ICLC frame for LFAST Slaves Rx Interface fast mode switch received" %define _DESC701_ \ desc += "ICLC frame for LFAST Slaves Rx Interface slow mode switch received" %define _DESC702_ \ desc += "ICLC frame for LFAST Slaves Tx Interface fast mode switch received" %define _DESC703_ \ desc += "ICLC frame for LFAST Slaves Tx Interface slow mode switch received" %define _DESC704_ \ desc += "ICLC frame for PLL OFF received" %define _DESC705_ \ desc += "ICLC frame for PLL ON received" %define _DESC706_ \ desc += "LFAST LVDS Control Register. " %define _DESC707_ \ desc += "SW signal to take LVDS LD out of Sleep mode. This bit can be changed only when\n"\ desc += "DRFEN is high. Set by user software and cleared by system hardware." %define _DESC708_ \ desc += "SW signal to put LVDS LD into Sleep mode. This bit can be changed only when\n"\ desc += "DRFEN is high. Set by user software and cleared by system hardware." %define _DESC709_ \ desc += "SW signal to take LVDS LR out of Sleep mode. This bit can be changed only when\n"\ desc += "DRFEN is high. Set by user software and cleared by system hardware." %define _DESC710_ \ desc += "SW signal to put LVDS LR into Sleep mode. This bit can be changed only when\n"\ desc += "DRFEN is high. Set by user software and cleared by system hardware." %define _DESC711_ \ desc += "SW signal to turn OFF the LVDS LD. This bit can be changed only when DRFEN is\n"\ desc += "high. Set by user software and cleared by system hardware." %define _DESC712_ \ desc += "SW signal to turn ON the LVDS LD. This bit can be changed only when DRFEN is\n"\ desc += "high. Set by user software and cleared by system hardware." %define _DESC713_ \ desc += "SW signal to turn OFF the LVDS LR. This bit can be changed only when DRFEN is\n"\ desc += "high. Set by user software and cleared by system hardware." %define _DESC714_ \ desc += "SW signal to turn ON the LVDS LR. This bit can be changed only when DRFEN is\n"\ desc += "high. Set by user software and cleared by system hardware." %define _DESC715_ \ desc += "Indicates the value driven onto LVDS LR output when in shutdown mode" %define _DESC716_ \ desc += "LVDS LD output buffer enable." %define _DESC717_ \ desc += "Tx and Clock Mux. The bit can be used to bring out PLL Phase 0 clock on Tx LVDS\n"\ desc += "pad." %define _DESC718_ \ desc += "LVDS pad reference enable" %define _DESC719_ \ desc += "Tx LVDS internal loopback enable. The internal loopback is not intended for\n"\ desc += "board level functionality, so this feature should not be implemented." %define _DESC720_ \ desc += "LVRXOP[2]: Termination resistance\n\n"\ desc += "LVRXOP[1]:Not used\n\n"\ desc += "LVRXOP[0]:Defines the LVDS LR Bias current reference" %define _DESC721_ \ desc += "Control signal for LFAST and Micro-Second Bus selection." %define _DESC722_ \ desc += "LVDS Data select. This bit is used for selecting use of clock sampled data or\n"\ desc += "normal data in LVDS." %define _DESC723_ \ desc += "LVDS clock select. This bit is used for selecting use of direct pll clock or\n"\ desc += "inverted pll clock in LVDS." %define _DESC724_ \ desc += "LFAST Unsolicited Tx Control Register. " %define _DESC725_ \ desc += "Tx Unsolicited send request.\n\n"\ desc += "Set by user software and cleared by system hardware." %define _DESC726_ \ desc += "Tx Unsolicited message header.\n\n"\ desc += "Only writable when UNSTCR[USNDRQ] = 0" %define _DESC727_ \ desc += "LFAST Unsolicited Tx Data Register. " %define _DESC728_ \ desc += "Unsolicited Transmit Data 8-0. This represents 9 registers for Unsolicited\n"\ desc += "transmit data.\n\n"\ desc += "The first bit to transmitted as part of the payload will be from UNTXD8[31],\n"\ desc += "second bit from UNTXD8[30], and so on. So the last bit transmitted will be from\n"\ desc += "UNTXD0[0] in case of 288 bit payload.\n\n"\ desc += "Only writable when UNSTCR[USNDRQ] = 0" %define _DESC729_ \ desc += "LFAST Global Status Register. " %define _DESC730_ \ desc += "Indicates the LFAST module is in Dual mode" %define _DESC731_ \ desc += "Indicates if the Rx Controller is idle/active and that the Rx clocks are\n"\ desc += "enabled. In functional mode this will always be active." %define _DESC732_ \ desc += "Transmit Interface Data Rate Status. Indicates the current speed rate of the Tx\n"\ desc += "controller" %define _DESC733_ \ desc += "Recieve Interface Data Rate Status. Indicates the current speed rate of the Rx\n"\ desc += "controller" %define _DESC734_ \ desc += "Auto loopback frame transmission count reached. The Count of frame is defined\n"\ desc += "by ALCR LPFMCNT." %define _DESC735_ \ desc += "Loopback frame pass threshold reached." %define _DESC736_ \ desc += "Valid payload received during loopback check mode. Indicates whether the Loop\n"\ desc += "back frame received payload is CBh." %define _DESC737_ \ desc += "Valid header received during loopback check mode. Indicates whether the Loop\n"\ desc += "back frame received header is 13h." %define _DESC738_ \ desc += "Valid synchronization received." %define _DESC739_ \ desc += "LFAST Ping Status Register. " %define _DESC740_ \ desc += "Ping Data Register. In LFAST Master mode the Ping response ICLC frame received\n"\ desc += "is stored into this register." %define _DESC741_ \ desc += "LFAST Data Frame Status Register. " %define _DESC742_ \ desc += "Unread Rx Frame Data Count. Indicates the number of unread data stored in the\n"\ desc += "Rx Data FIFO." %define _DESC743_ \ desc += "Unread Rx Frame Count. Indicates the number of unread data frames stored in the\n"\ desc += "Rx Data FIFO." %define _DESC744_ \ desc += "Unread Tx Frame Data Count. Indicates the number of unread data stored in the\n"\ desc += "Tx Data FIFO." %define _DESC745_ \ desc += "Unread Tx Frame Count.Count of pending Data Frames programed by System Side\n"\ desc += "Module." %define _DESC746_ \ desc += "LFAST Tx Interrupt Status Register. " %define _DESC747_ \ desc += "TxData Interface not enabled. Tx Data Interface not enabled and a frame is\n"\ desc += "ready to be transmitted" %define _DESC748_ \ desc += "Transmit Data FIFO Overflow Interrupt" %define _DESC749_ \ desc += "Ping response frame transmitted interrupt" %define _DESC750_ \ desc += "Unsolicited Frame transmitted Interrupt" %define _DESC751_ \ desc += "ICLC Frame transmitted Interrupt" %define _DESC752_ \ desc += "Data Frame transmitted Interrupt" %define _DESC753_ \ desc += "LFAST Rx Interrupt Status Register. e" %define _DESC754_ \ desc += "Rx Data FIFO Min Threshold reached." %define _DESC755_ \ desc += "Rx Data FIFO Max Threshold reached." %define _DESC756_ \ desc += "Rx Data FIFO Underflow." %define _DESC757_ \ desc += "Rx Data FIFO Overflow." %define _DESC758_ \ desc += "Frame with unsupported frame size received." %define _DESC759_ \ desc += "Invalid ICLC code Received." %define _DESC760_ \ desc += "Invalid Logical Channel Type." %define _DESC761_ \ desc += "Frame with CTS bit Low Received." %define _DESC762_ \ desc += "Data frame received." %define _DESC763_ \ desc += "Unsolicited Frame received." %define _DESC764_ \ desc += "LFAST Rx ICLC Interrupt Status Register. " %define _DESC765_ \ desc += "ICLC Ping Frame Request received" %define _DESC766_ \ desc += "ICLC frame for Clk Test mode received" %define _DESC767_ \ desc += "LFAST PLL and LVDS Status Register. " %define _DESC768_ \ desc += "This bit indicates the real time status of the LR sleep signal." %define _DESC769_ \ desc += "This bit indicates the real time status of LD sleep signal." %define _DESC770_ \ desc += "This bit indicates the real time status of LD power down signal. When asserted,\n"\ desc += "LD is put in the power down state." %define _DESC771_ \ desc += "This bit indicates the real time status of LR power down signal. When asserted,\n"\ desc += "LR is put in the power down state." %define _DESC772_ \ desc += "LFAST Unsolicited Rx Status Register. " %define _DESC773_ \ desc += "Unsolicited data valid. Indicates a valid frame exists in the Unsolicited Data\n"\ desc += "registers." %define _DESC774_ \ desc += "Rx Unsolicited payload. Indicates the number of bytes of valid Rx unsolicited\n"\ desc += "data payload present in the UNSRDR . The bitfield coding is same as b7-b5 in\n"\ desc += "#Rdb21869 ." %define _DESC775_ \ desc += "LFAST Unsolicited Rx Data Register. " %define _DESC776_ \ desc += "Unsolicited Receive Data. This represents 9 registers for Unsolicited received\n"\ desc += "data.It is read only register.\n\n"\ desc += "The first bit received as part of the payload will be stored at UNRXD8[31],\n"\ desc += "second bit at UNRXD8[30], and so on. So the last bit will be stored at\n"\ desc += "UNRXD0[0] in case of 288 bit payload." %define _DESC777_ \ desc += "LIN Control Register 1. LINCR1 consists of control bits used to configure\n"\ desc += "features of the LINFlexD." %define _DESC778_ \ desc += "Checksum Calculation disable\n\n"\ desc += "This bit can be written during Initialization mode only. It is read-only in\n"\ desc += "Normal mode." %define _DESC779_ \ desc += "Checksum field disable\n\n"\ desc += "This bit can be configured during Initialization mode only. It is read-only in\n"\ desc += "Normal mode." %define _DESC780_ \ desc += "LIN Auto Synchronization Enable\n\n"\ desc += "This bit can be programmed in Initialization mode only. It is read-only in\n"\ desc += "Normal mode. (Note: If generic auto_sync = 0, then this bit will always read a\n"\ desc += "0)." %define _DESC781_ \ desc += "Auto Wakeup\n\n"\ desc += "This bit can be configured during Initialization mode only. This bit is\n"\ desc += "utilized in UART mode also." %define _DESC782_ \ desc += "Master Break Length\n\n"\ desc += "These bits choose the length of the Sync break to be generated by the master.\n\n"\ desc += "These bits can be programmed in Initialization mode only. They are read-only in\n"\ desc += "Normal mode." %define _DESC783_ \ desc += "By-pass filter\n\n"\ desc += "This bit can be programmed during Initialization mode only.\n\n"\ desc += "If generic slave = 0 or no_of_filters = 0, then this bit will always read a 1,\n"\ desc += "and cannot be programmed." %define _DESC784_ \ desc += "Loop Back mode\n\n"\ desc += "Refer to 'Loop back mode' in Test mode . Note that this bit can be programmed\n"\ desc += "only in Initialization mode. This bit is utilized in UART mode also." %define _DESC785_ \ desc += "Master mode enable\n\n"\ desc += "This bit can be programmed in Initialization mode only. It is read-only in\n"\ desc += "Normal mode.\n\n"\ desc += "If generic slave = 0, then this bit will read a '1' always, and cannot be\n"\ desc += "programmed." %define _DESC786_ \ desc += "Slave Mode Sync Break Length\n\n"\ desc += "This bit can be programmed in Initialization mode only. It is read only in\n"\ desc += "Normal mode." %define _DESC787_ \ desc += "Receiver Buffer Locked mode\n\n"\ desc += "This bit can be programmed in Initialization mode only. It is read-only in\n"\ desc += "Normal mode. This bit is utilized in UART mode also." %define _DESC788_ \ desc += "Sleep Mode Request\n\n"\ desc += "This bit is set by software to request LINFlexD to enter Sleep mode. This bit\n"\ desc += "is cleared by software or hardware (if AUTOWU bit in LINCR1 and WUF bit in\n"\ desc += "LINSR are set) to exit sleep mode. This bit is utilized in UART mode also." %define _DESC789_ \ desc += "Initialization Mode Request\n\n"\ desc += "The software sets this bit to switch the hardware into Initialization mode. On\n"\ desc += "clearing this bit (and if SLEEP bit is also zero) LINFlexD enters normal mode.\n"\ desc += "This bit is utilized in UART mode also." %define _DESC790_ \ desc += "LIN Interrupt enable register. " %define _DESC791_ \ desc += "Stuck at zero Interrupt Enable\n\n"\ desc += "An interrupt is generated if this bit is set and the Stuck at Zero Flag (SZF)\n"\ desc += "in LINESR or UARTSR is set." %define _DESC792_ \ desc += "Output Compare Interrupt Enable" %define _DESC793_ \ desc += "Bit Error Interrupt Enable" %define _DESC794_ \ desc += "Checksum Error Interrupt Enable\n\n"\ desc += "An interrupt is generated if this bit is set and the Checksum Error Flag (CEF)\n"\ desc += "is set in LINESR." %define _DESC795_ \ desc += "Header Error Interrupt Enable\n\n"\ desc += "An interrupt is generated when this bit is set and either of the following\n"\ desc += "flags are set SFEF, SDEF, IDPEF in LINESR are set.\n\n"\ desc += "If generic slave = 0, then this bit will always read a 0 and cannot be\n"\ desc += "programmed." %define _DESC796_ \ desc += "Frame Error Interrupt Enable" %define _DESC797_ \ desc += "Buffer Overrun Error Interrupt Enable\n\n"\ desc += "An interrupt is generated if this bit is set and the Buffer Overrun Flag (BOF)\n"\ desc += "is set in LINESR or UARTSR." %define _DESC798_ \ desc += "LIN state Interrupt enable\n\n"\ desc += "Interrupt is generated only when entering the above fields. This interrupt can\n"\ desc += "mainly be used for debugging purposes. The interrupt has no status flag." %define _DESC799_ \ desc += "Wakeup interrupt enable\n\n"\ desc += "If this bit is set and the WUF in LINSR or UARTSR is set then an interrupt is\n"\ desc += "generated." %define _DESC800_ \ desc += "Data Buffer Full Interrupt enable\n\n"\ desc += "An interrupt is generated if this bit is set and the DBFF bit in LINSR is also\n"\ desc += "set." %define _DESC801_ \ desc += "Data Buffer Empty Interrupt enable/Timeout Interrupt Enable\n\n"\ desc += "An interrupt is generated if this bit is set and LINSR[DBEF] status bit is set\n"\ desc += "(in LIN mode) or if this bit is set and UARTSR[TO] status bit is set (in UART\n"\ desc += "mode)." %define _DESC802_ \ desc += "Data Reception complete Interrupt enable\n\n"\ desc += "An interrupt is generated when this bit is set and Data Received flag (DRF) in\n"\ desc += "LINSR or UARTSR is set." %define _DESC803_ \ desc += "Data Transmitted Interrupt enable\n\n"\ desc += "An interrupt is generated when this bit is set and Data Transmitted flag (DTF)\n"\ desc += "in LINSR or UARTSR is set." %define _DESC804_ \ desc += "Header Received Interrupt\n\n"\ desc += "An interrupt is generated when this bit is set and the Header Received flag\n"\ desc += "(HRF) in LINSR is set.\n\n"\ desc += "If generic slave = 0, then this bit will always read a 0, and cannot be\n"\ desc += "programmed." %define _DESC805_ \ desc += "LIN Status Register. This register consists of status bits indicating the state\n"\ desc += "of the LINFlexD hardware.\n\n"\ desc += "" %define _DESC806_ \ desc += "AUTOSYNC_COMP\n\n"\ desc += "This bit is set after autosynchronization is complete and when the LASE bit in\n"\ desc += "LINCR1 register is enabled. Only after this bit is set, the contents of LINIBRR\n"\ desc += "and LINFBRR registers can be read in autosynchronization mode.\n\n"\ desc += "If autosynchronization is disabled, this bit is reserved." %define _DESC807_ \ desc += "Receive Data Byte Count\n\n"\ desc += "RDC contains the number of entries (bytes) in the Receive data buffer in LIN\n"\ desc += "mode. RDCx is a read-only field available for debug purposes." %define _DESC808_ \ desc += "LIN state" %define _DESC809_ \ desc += "Release Message Buffer" %define _DESC810_ \ desc += "Data Reception Buffer Not Empty Flag\n\n"\ desc += "This bit is set by hardware as soon as the first byte of response has been\n"\ desc += "received and stored in BDRL (when there is at least one data byte in reception\n"\ desc += "buffer). Software should clear it after reading all the buffers. This bit is\n"\ desc += "also reset by hardware in Initialization mode.\n\n"\ desc += "This flag could be checked by software in case of a response timeout event." %define _DESC811_ \ desc += "Receiver Busy flag\n\n"\ desc += "In Slave mode after header reception, if DIR bit is reset and reception starts,\n"\ desc += "then this bit is set. In this case user cannot set the DTRQ bit." %define _DESC812_ \ desc += "LIN Receive signal\n\n"\ desc += "This bit reflects the current status of the Rx pin.\n\n"\ desc += "After reset is released, RDI reflects the actual value of Rx pin." %define _DESC813_ \ desc += "Wakeup flag\n\n"\ desc += "This bit is set by hardware when a falling edge is detected on the Rx pin.\n\n"\ desc += "1. When slave is in Sleep mode\n\n"\ desc += "2. When master is in Sleep mode or Idle mode\n\n"\ desc += "It can be cleared by software. It gets reset by hardware in Initialization\n"\ desc += "mode." %define _DESC814_ \ desc += "Data Buffer full flag\n\n"\ desc += "This bit is set by hardware when the buffer is full (8 bytes received) and DFL\n"\ desc += "> 7. It should be cleared by software. This bit is also reset by hardware in\n"\ desc += "Initialization mode." %define _DESC815_ \ desc += "Data Buffer empty flag\n\n"\ desc += "This bit is set by hardware when the buffer is empty (8 bytes have been\n"\ desc += "transmitted) and DFL > 7. It should be cleared by software after data buffer is\n"\ desc += "refilled by software. Transmission of next 8 bytes will not start unless this\n"\ desc += "bit is reset by software. This bit is also reset by hardware in Initialization\n"\ desc += "mode." %define _DESC816_ \ desc += "Data Reception Completed flag\n\n"\ desc += "This bit is set by hardware and indicates that data reception has been\n"\ desc += "completed. This flag should be cleared by software. This bit is also reset by\n"\ desc += "hardware in Initialization mode.\n\n"\ desc += "In case framing error or checksum error occurs then this flag is not set." %define _DESC817_ \ desc += "Data Transmission Completed flag\n\n"\ desc += "This bit is set by hardware and indicates that data transmission is completed.\n"\ desc += "This flag should be cleared by software. This bit is also reset by hardware in\n"\ desc += "Initialization mode.\n\n"\ desc += "For LIN mode, in case a bit error occurs (and IOBE is reset) then this flag is\n"\ desc += "not set." %define _DESC818_ \ desc += "Header Received flag\n\n"\ desc += "This bit is set when the header reception is completed. It should be cleared by\n"\ desc += "software.\n\n"\ desc += "This bit is set only when:\n\n"\ desc += "a) All filters are inactive and Bypass filter (BF) bit is set\n\n"\ desc += "b) No match in any filter and Bypass filter (BF) bit is set\n\n"\ desc += "c) TX filter match\n\n"\ desc += "At end of frame or frame aborted, if HRF is still set, it gets reset by\n"\ desc += "hardware. This bit is also reset by hardware in Initialization mode.\n\n"\ desc += "If generic slave = 0, then this bit will always read a 0, and cannot be\n"\ desc += "programmed." %define _DESC819_ \ desc += "LIN Error Status Register. Refer to Errors for detailed description of all\n"\ desc += "errors." %define _DESC820_ \ desc += "Stuck at Zero flag\n\n"\ desc += "This bit is set when there is a stuck-at-zero timeout error. It should be reset\n"\ desc += "by software." %define _DESC821_ \ desc += "Output Compare Flag\n\n"\ desc += "0: No output compare event occurred\n\n"\ desc += "1: The content of the counter has matched the content of OCR1 or OCR2\n\n"\ desc += "This bit should be cleared by software. If this bit is set and the IOT bit of\n"\ desc += "LINTCSR is set, then LINFlexD moves to Idle state.\n\n"\ desc += "If the MODE bit in LINTCSR is clear, then OCF gets reset by hardware in\n"\ desc += "Initialization mode; if the MODE bit is set, then OCF maintains its status\n"\ desc += "irrespective of the LIN state." %define _DESC822_ \ desc += "Bit Error flag\n\n"\ desc += "This bit is set by hardware when there is a bit error. It should be cleared by\n"\ desc += "software.\n\n"\ desc += "Reset by hardware in Initialization mode." %define _DESC823_ \ desc += "Checksum Error flag\n\n"\ desc += "This bit is set by hardware if the received checksum does not match the\n"\ desc += "hardware-calculated checksum. It should be cleared by software. This error will\n"\ desc += "never occur if CCD or CFD bit of LINCR1 is set.\n\n"\ desc += "Reset by hardware in Initialization mode." %define _DESC824_ \ desc += "Sync Field Error flag\n\n"\ desc += "This bit is set by hardware when the received Sync Field is inconsistent. It\n"\ desc += "should be cleared by software.\n\n"\ desc += "Reset by hardware in Initialization mode.\n\n"\ desc += "If generic slave = 0, then this bit will always read a 0, and cannot be\n"\ desc += "programmed." %define _DESC825_ \ desc += "Sync Delimiter Error flag\n\n"\ desc += "This bit is set by hardware when the delimiter is too short (in other words,\n"\ desc += "less than one bit time). It should be cleared by software.\n\n"\ desc += "Reset by hardware in Initialization mode.\n\n"\ desc += "If generic slave = 0, then this bit will always read a 0, and cannot be\n"\ desc += "programmed." %define _DESC826_ \ desc += "ID Parity Error flag\n\n"\ desc += "This bit is set by hardware when there is an error in the ID parity. It should\n"\ desc += "be cleared by software.\n\n"\ desc += "Header Error Interrupt is triggered for SFEF or SDEF or IDPEF flag is set and\n"\ desc += "HEIE is set. If generic slave = 0, then this bit will always read a 0, and\n"\ desc += "cannot be programmed. For generic slave = 1,this bit is reset by hardware in\n"\ desc += "Initialization mode." %define _DESC827_ \ desc += "Framing Error flag\n\n"\ desc += "This bit is set by hardware when there is a framing error (invalid stop bit).\n"\ desc += "It should be cleared by software.\n\n"\ desc += "Reset by hardware in initialization mode." %define _DESC828_ \ desc += "Buffer overrun flag\n\n"\ desc += "This bit is set by hardware when there is a new byte received and RMB bit is\n"\ desc += "not cleared. It can be cleared by software.\n\n"\ desc += "Reset by hardware in initialization mode." %define _DESC829_ \ desc += "Noise flag\n\n"\ desc += "This bit is set by hardware when noise is detected in the received character.\n"\ desc += "It should be cleared by software. Reset by hardware in Initialization mode." %define _DESC830_ \ desc += "UART Mode Control Register. " %define _DESC831_ \ desc += "Number of expected frame\n\n"\ desc += "These bits are used to configure the number of expected frames in UART\n"\ desc += "reception mode. If the DTU bit is set, then the UART timeout counter will be\n"\ desc += "reset after the configured number of frames have been received." %define _DESC832_ \ desc += "Disable Timeout in UART mode\n\n"\ desc += "This bit can be programmed in Initialization mode only when the UART bit is\n"\ desc += "set.\n\n"\ desc += "There is an internal counter that gives the number of frames received.\n\n"\ desc += "In Buffer mode:\n\n"\ desc += "This timer gets reset whenever the number of bytes received (rec_byte_cnt) is\n"\ desc += "equal to RDFL. At this point the DRF bit is also set and num_of_frames (number\n"\ desc += "of frames received), rec_byte_cnt are reset.\n\n"\ desc += "When num_of_frames equals NEF, Disable Timeout is generated. But this clears\n"\ desc += "num_of_frames also. Thus the timer restarts again. The value of counter is 0\n"\ desc += "when it restarts.\n\n"\ desc += "In FIFO mode:\n\n"\ desc += "When num_of_frames equals NEF, Disable Timeout is generated which clears\n"\ desc += "num_of_frames and causes the timer to restart again. The value of counter is 0\n"\ desc += "when it restarts.\n\n"\ desc += "Notes:\n\n"\ desc += "Disable Timeout causes only the Timer to restart which enables Timeout again. \n"\ desc += "Timer reset means it resets and starts counting again and the Timeout is\n"\ desc += "enabled." %define _DESC833_ \ desc += "Stop bits in UART reception mode\n\n"\ desc += "When the UART is used for transmission and reception we have to set the same\n"\ desc += "number of stop bits in GCR and SBUR. When the UART is used only as receiver, it\n"\ desc += "is enough to set SBUR bits only.\n\n"\ desc += "This bit can be programmed in the initialization mode only, when the UART bit\n"\ desc += "is set." %define _DESC834_ \ desc += "Special Word Length in UART mode\n\n"\ desc += "This bit can be programmed in initialization mode only when the UART bit is\n"\ desc += "set. If this bit is set, setting WL and PCE bits has no effect in UART\n"\ desc += "reception although parity check is enabled by default in this mode and PC0/1\n"\ desc += "bits can be used to select the parity control. This bit is given the highest\n"\ desc += "priority in UART reception mode." %define _DESC835_ \ desc += "Transmitter Data Field Length/TX FIFO Counter\n\n"\ desc += "TDFL defines the number of bytes to be transmitted in UART buffer mode (TFBM =\n"\ desc += "0). TDFL is a read/write field. Bit 15 is reserved and not implemented. When\n"\ desc += "the UART data length is configured as halfword (WL = 10 or WL = 10), only the\n"\ desc += "configurations TDFL = x01 or TDFL = x11 are allowed.\n\n"\ desc += "x00 : 1 byte\n\n"\ desc += "x01 : 2 bytes\n\n"\ desc += "x10 : 3 bytes\n\n"\ desc += "x11 : 4 bytes\n\n"\ desc += "Register bit is a read/write field.\n\n"\ desc += "TFC contains the number of entries (bytes) of the Tx FIFO in UART FIFO mode\n"\ desc += "(TFBM = 1). TFCx is a read-only field available for debug purposes.\n\n"\ desc += "000 : empty\n\n"\ desc += "001 : 1 byte\n\n"\ desc += "010 : 2 bytes\n\n"\ desc += "011 : 3 bytes\n\n"\ desc += "100 : 4 bytes\n\n"\ desc += "Others : reserved\n\n"\ desc += "TDFLTFC can be programmed and are significative only when the UART bit is\n"\ desc += "set.\n\n"\ desc += "Register bit can be read in any mode, written only in Initialization mode.\n\n"\ desc += "When in_ps_bit_remap = 1, these bits always reflect the value of\n"\ desc += "in_ps_tdfl_port." %define _DESC836_ \ desc += "Reception Data Field Length /RX FIFO Counter\n\n"\ desc += "RDFL defines the number of bytes to be received in UART buffer mode (RFBM = 0).\n"\ desc += "RDFL is a read/write field. Bit 19 is reserved and not implemented. When the\n"\ desc += "UART data length is configured as halfword (WL = 10 or WL = 11), only the\n"\ desc += "configurations RDFL = x01 or RDFL = x11 are allowed.\n\n"\ desc += "x00 : 1 byte\n\n"\ desc += "x01 : 2 bytes\n\n"\ desc += "x10 : 3 bytes\n\n"\ desc += "x11 : 4 bytes\n\n"\ desc += "RFC contains the number of entries (bytes) of the Rx FIFO in UART FIFO mode\n"\ desc += "(RFBM = 1). RFCx is a read-only field available for debug purposes.\n\n"\ desc += "000 : empty\n\n"\ desc += "001 : 1 byte\n\n"\ desc += "010 : 2 bytes/1.5 byte in case of WLS bit setting\n\n"\ desc += "011 : 3 bytes\n\n"\ desc += "100 : 4 bytes/2x1.5 byte in case of WLS bit setting\n\n"\ desc += "Others - reserved\n\n"\ desc += "RDFLRFC can be programmed and are significative only when the UART bit is\n"\ desc += "set.\n\n"\ desc += "In buffer mode, RDFL should be programmed to be greater than or equal to NEF\n"\ desc += "(number of expected frames). In FIFO mode, there is no such constraint." %define _DESC837_ \ desc += "RFBM Rx Fifo/Buffer mode\n\n"\ desc += "This bit can be programmed in Initialization mode, only when the UART bit is\n"\ desc += "set.\n\n"\ desc += "Register bit can be read in any mode, written only in initialization mode." %define _DESC838_ \ desc += "Tx Fifo/Buffer mode\n\n"\ desc += "This bit can be programmed in initialization mode, only when the UART bit is\n"\ desc += "set.\n\n"\ desc += "Register bit can be read in any mode, written only in initialization mode." %define _DESC839_ \ desc += "Word Length in UART mode\n\n"\ desc += "This bit can be programmed in Initialization mode only, when the UART bit is\n"\ desc += "set.\n\n"\ desc += "Register bit can be read in any mode, written only in initialization mode." %define _DESC840_ \ desc += "Parity Control\n\n"\ desc += "This bit can be programmed in Initialization mode, only when UART bit is set.\n\n"\ desc += "Register bit can be read in any mode, written only in initialization mode." %define _DESC841_ \ desc += "Receiver Enable\n\n"\ desc += "This bit can be programmed only when the UART bit is set." %define _DESC842_ \ desc += "Transmitter Enable\n\n"\ desc += "This bit can be programmed only when UART bit is set." %define _DESC843_ \ desc += "Parity Control Enable\n\n"\ desc += "This bit can be programmed in Initialization mode only, when the UART bit is\n"\ desc += "set.\n\n"\ desc += "Register bit can be read in any mode, written only in initialization mode." %define _DESC844_ \ desc += "Word Length in UART mode\n\n"\ desc += "This bit can be programmed in Initialization mode only, when UART bit is set.\n\n"\ desc += "Register bit can be read in any mode, written only in initialization mode." %define _DESC845_ \ desc += "UART Mode\n\n"\ desc += "This bit can be programmed in Initialization mode only.\n\n"\ desc += "Register bit can be read in any mode, written only in initialization mode." %define _DESC846_ \ desc += "UART Mode Status Register. " %define _DESC847_ \ desc += "Stuck at Zero flag\n\n"\ desc += "This bit is set by hardware when 100 dominant bits are detected. It should be\n"\ desc += "cleared by software. An interrupt will be generated if the SZIE bit in LINIER\n"\ desc += "is set.\n\n"\ desc += "This bit will reflect the same value as in LINESR, when in Initialization mode\n"\ desc += "and the UART bit is set." %define _DESC848_ \ desc += "Output Compare Flag\n\n"\ desc += "An interrupt will be generated if the OCIE bit in LINIER is set.\n\n"\ desc += "This bit will reflect the same value as in LINESR, when in Initialization mode\n"\ desc += "and the UART bit is set.\n\n"\ desc += "For Baud rate above 1 Mbps, this flag is not usable." %define _DESC849_ \ desc += "Parity Error flag\n\n"\ desc += "These bits indicate if there is a Parity Error in the corresponding byte. No\n"\ desc += "interrupt is generated if this error occurs.\n\n"\ desc += "This bit will reflect the same value as in LINESR, when in initialization mode\n"\ desc += "and UART bit set.\n\n"\ desc += "Parity is checked only after complete frame is received. Following are the\n"\ desc += "conditions when WL bits = 01 or 11 (either PE0 or PE2 is only set). When PE0 is\n"\ desc += "set, it indicates Parity error in either first or second byte received When\n"\ desc += "PE2 is set, it indicates Parity error in either third or fourth byte received" %define _DESC850_ \ desc += "Release Message Buffer\n\n"\ desc += "This bit should be cleared by software.\n\n"\ desc += "This bit will reflect the same value as in LINESR, when in Initialization mode\n"\ desc += "and the UART bit is set." %define _DESC851_ \ desc += "Framing Error flag\n\n"\ desc += "This bit is set by hardware when there is a framing error (invalid stop bit).\n"\ desc += "It should be cleared by software. It will generate an interrupt if the FEIE bit\n"\ desc += "of LINIER is set.\n\n"\ desc += "This bit will reflect the same value as in LINESR, when in Initialization mode\n"\ desc += "and the UART bit is set." %define _DESC852_ \ desc += "FIFO/Buffer overrun flag\n\n"\ desc += "This bit is set by hardware when there is a new byte received and the RMB bit\n"\ desc += "is not cleared in UART buffer mode. In UART FIFO mode this bit is set when\n"\ desc += "there is a new byte and the Rx FIFO is full. In UART FIFO mode, once Rx FIFO is\n"\ desc += "full, the new received message will be discarded irrespective of the new value\n"\ desc += "of the RBLM bit. In UART Rx Buffer mode, if RBLM is set then the new message\n"\ desc += "received will be discarded; if RBLM is reset then the new message will\n"\ desc += "overwrite the buffer. It can be cleared by software writing a 1. An interrupt\n"\ desc += "is generated if the BOIE bit of LINIER is set.\n\n"\ desc += "This bit will reflect the same value as in LINESR, when in Initialization mode\n"\ desc += "and the UART bit is set." %define _DESC853_ \ desc += "Receiver Data Input signal\n\n"\ desc += "This bit reflects the current status of the RX pin." %define _DESC854_ \ desc += "Wakeup flag\n\n"\ desc += "This bit is set by hardware when a falling edge is detected on the RX pin in\n"\ desc += "sleep mode. It should be cleared by software. An interrupt will be generated if\n"\ desc += "the WUIE bit in LINIER is set.\n\n"\ desc += "This bit will reflect the same value as in LINESR when in Initialization mode\n"\ desc += "and the UART bit is set." %define _DESC855_ \ desc += "Receive FIFO Not Empty\n\n"\ desc += "RFNE bit is set by hardware in UART FIFO mode (RFBM = 1), when there is at\n"\ desc += "least one data byte present in the receive FIFO. RFNE is a read-only bit for\n"\ desc += "debugging purposes. This flag can be used by software in case of a timeout\n"\ desc += "event." %define _DESC856_ \ desc += "Timeout\n\n"\ desc += "This bit is set by hardware when a UART timeout occurs -- in other words, the\n"\ desc += "value of UARTCTO becomes equal to the preset value of the timeout (UARTPTO\n"\ desc += "register setting). TO should be cleared by software. The SR bit should be used\n"\ desc += "to reset the receiver fsm to Idle state in case of UART TIMEOUT for UART\n"\ desc += "reception, depending on the application, in both buffer and FIFO mode.\n\n"\ desc += "An interrupt will be generated when LINIER.DBEIE/TOIE bit is set on the Error\n"\ desc += "interrupt line in UART mode." %define _DESC857_ \ desc += "Data Reception Completed Flag /Rx FIFO Empty Flag\n\n"\ desc += "DRF is set by hardware in UART buffer mode (RFBM = 0) and indicates that the\n"\ desc += "number of bytes programmed in RDFL have been received. DRF should be cleared by\n"\ desc += "software. An interrupt will be generated if the DRIE bit in LINIER is set.\n\n"\ desc += "DRF bit is set only when the configured number of stop bits are received for\n"\ desc += "the last frame (number of frames is configurable by RDFL bits).\n\n"\ desc += "DRF is set irrespective of framing error, parity error or overrun error. This\n"\ desc += "bit will reflect the same value as in LINESR when in Initialization mode and\n"\ desc += "the UART bit is set.\n\n"\ desc += "Register bit can be read/cleared by software. Writing 1 clears contents.\n\n"\ desc += "RFE is set by hardware in UART FIFO mode (RFBM = 1) when the RX FIFO is empty.\n"\ desc += "RFE is a read-only bit for debugging purposes. It is internally used by the DMA\n"\ desc += "RX interface.\n\n"\ desc += "Register bit is read-only field." %define _DESC858_ \ desc += "Data Transmission Completed Flag/ TX FIFO Full Flag\n\n"\ desc += "DTF is set by hardware in UART buffer mode (TFBM = 0) and indicates that data\n"\ desc += "transmission is completed. DTF should be cleared by software. An interrupt will\n"\ desc += "be generated if the DTIE bit in LINIER is set. This bit will reflect the same\n"\ desc += "value as in LINESR when in Initialization mode and the UART bit is set.\n\n"\ desc += "Register bit can be read/cleared by software. Writing 1 clears contents.\n\n"\ desc += "TFF is set by hardware in UART FIFO mode (TFBM = 1) when TX FIFO is full. TFF\n"\ desc += "is a read-only bit for debugging purposes. It is internally used by the DMA TX\n"\ desc += "interface.\n\n"\ desc += "Register bit is read-only field." %define _DESC859_ \ desc += "Noise flag\n\n"\ desc += "This bit is set by hardware when noise is detected in the received character.\n"\ desc += "It should be cleared by software. This bit will reflect the same value as in\n"\ desc += "LINESR when in Initialization mode and the UART bit is set. During reduced\n"\ desc += "oversampling (ROSE bit = 1), it is enabled only when OSR = 8." %define _DESC860_ \ desc += "LIN Time-Out Control Status Register. This register contains control and status\n"\ desc += "bits for timeout feature." %define _DESC861_ \ desc += "Time-out counter mode\n\n"\ desc += "This bit can be configured only during initialization.\n\n"\ desc += "Register bit can be read in any mode, written only in initialization mode." %define _DESC862_ \ desc += "Idle on timeout\n\n"\ desc += "Register bit can be read in any mode, written only in initialization mode." %define _DESC863_ \ desc += "Time-out counter enable\n\n"\ desc += "TOCE is always configurable by software in Initialization mode. If LIN state is\n"\ desc += "other than INIT and if timer is configured in LIN mode, then hardware takes\n"\ desc += "control of TOCE." %define _DESC864_ \ desc += "Counter Value\n\n"\ desc += "These bits reflect the value of a free-running counter used for timeout." %define _DESC865_ \ desc += "LIN Output Compare Register. This register contains the value to be compared to\n"\ desc += "the LINTOCR value. This register is writable by software only in Output Compare\n"\ desc += "Mode." %define _DESC866_ \ desc += "Output compare value 2" %define _DESC867_ \ desc += "Output compare value 1" %define _DESC868_ \ desc += "LIN Time-Out Control Register. " %define _DESC869_ \ desc += "Response timeout value\n\n"\ desc += "This is the response timeout duration (in bit time) for 1 byte.\n\n"\ desc += "The reset value is 0Eh = 14, corresponding to T Response_Maximum = 1.4 x T\n"\ desc += "Response_Nominal" %define _DESC870_ \ desc += "Header timeout value\n\n"\ desc += "This register contains the header timeout duration (in bit time). This register\n"\ desc += "can be written only for Slave mode. The reset value is the 2Ch = 455,\n"\ desc += "corresponding to T Header_Maximum in the LIN specification.\n\n"\ desc += "If Master mode is enabled then these bits will always reflect 28 (1.4 x 10 bits\n"\ desc += "of sync + 1.4 x 10 bits of ID). For slave, these bits should be programmed\n"\ desc += "without considering 11 bits of break." %define _DESC871_ \ desc += "LIN Fractional Baud Rate Register. This register consists of bits that decide\n"\ desc += "the fractional part of the LIN Baud Rate. It can be programmed only in\n"\ desc += "Initialization mode.\n\n"\ desc += "When LASE bit is set, this register should be read only after AUTOSYNC_COMP bit\n"\ desc += "in LINSR register is set to obtain the correct value. This register cannot be\n"\ desc += "used when reduced oversampling is enabled (ROSE bit = 1)" %define _DESC872_ \ desc += "Fractional Baud rates\n\n"\ desc += "Register bit can be read in any mode, written only in initialization mode." %define _DESC873_ \ desc += "LIN Integer Baud Rate Register. This register consists of control bits that\n"\ desc += "decide the baud rate along with the LINFBRR. It can be programmed only in\n"\ desc += "Initialization mode.\n\n"\ desc += "When LASE bit is set, this register should be read only after AUTOSYNC_COMP bit\n"\ desc += "in LINSR register is set to obtain the correct value." %define _DESC874_ \ desc += "Integer Baud rates\n\n"\ desc += "These bits along with the fractional baud rate bits decide the LIN baud rate.\n\n"\ desc += "IBR = 0h: LIN clock disabled\n\n"\ desc += "IBR = 1h: Mantissa (LDIV) = 1\n\n"\ desc += "...\n\n"\ desc += "IBR = FFFFEh: Mantissa (LDIV) = 1048574\n\n"\ desc += "IBR = FFFFFh: Mantissa (LDIV) = 1048575\n\n"\ desc += "Register bit can be read in any mode, written only in initialization mode." %define _DESC875_ \ desc += "LIN Checksum Field Register. There is a delay between 4 to 6 clock cycles of\n"\ desc += "PBRIDGEx_CLK for the internal checksum's value (which is clocked with\n"\ desc += "LIN_CLK/16 * LDIV) to reflect on LINCFR. This register consists of checksum\n"\ desc += "bits.\n\n"\ desc += " CFD CCD LINCHKSUM Read/write Checksum sent\n"\ desc += " --- --- -------------------- -------------------\n"\ desc += " 1 1 read/write None\n"\ desc += " 1 0 read-only None\n"\ desc += " 0 1 read/write Programmed checksum\n"\ desc += " 0 0 read-only Calculated checksum\n" %define _DESC876_ \ desc += "Checksum bits\n\n"\ desc += "When the CCD bit is reset these bits are read-only and are calculated by\n"\ desc += "hardware. When the CCD bit is set, these bits can be written by software." %define _DESC877_ \ desc += "LIN Control Register 2. This register includes control status bits related to\n"\ desc += "buffer operations." %define _DESC878_ \ desc += "Two Bit delimiter bit\n\n"\ desc += "This bit can be set in Initialization mode only.\n\n"\ desc += "Register bit can be read in any mode, written only in initialization mode." %define _DESC879_ \ desc += "Idle on Bit Error\n\n"\ desc += "This bit can be set in Initialization mode only.\n\n"\ desc += "Register bit can be read in any mode, written only in initialization mode." %define _DESC880_ \ desc += "Idle on Identifier Parity Error\n\n"\ desc += "This bit can be set in Initialization mode only.\n\n"\ desc += "Register bit can be read in any mode, written only in initialization mode.\n\n"\ desc += "If generic slave = 0, then this bit will always read a 0, and cannot be\n"\ desc += "programmed." %define _DESC881_ \ desc += "Wakeup Generate Request\n\n"\ desc += "Setting this bit will generate a wakeup pulse. It is reset by hardware when the\n"\ desc += "wakeup character has been transmitted. The character sent during wakeup is\n"\ desc += "copied from BDRL (DATA0). Note that this bit cannot be set in Sleep mode --\n"\ desc += "software has to exit Sleep mode before setting this bit.\n\n"\ desc += "Bit Error is not checked when transmitting the wakeup request.\n\n"\ desc += "Register bit can be read/set by software" %define _DESC882_ \ desc += "Data Discard request\n\n"\ desc += "Set by software to stop data reception if the frame does not concern the node.\n"\ desc += "This bit is reset by hardware once LINFlexD ignores the response and moves to\n"\ desc += "Idle state. For LIN slave this bit can be set only when HRF bit is set and\n"\ desc += "Identifier is software-filtered.\n\n"\ desc += "Register bit can be read/set by software" %define _DESC883_ \ desc += "Data Transmission Request\n\n"\ desc += "Set by software in slave mode to request the transmission of the LIN Data field\n"\ desc += "stored in the Buffer data register. This bit can be set only when the HRF bit\n"\ desc += "is set (to ensure that data transmission is requested only after a header\n"\ desc += "reception).\n\n"\ desc += "Cleared by hardware when the request has been completed, or on abort request or\n"\ desc += "error condition.\n\n"\ desc += "In Master mode, this bit is set by hardware when the DIR bit is set and header\n"\ desc += "transmission is complete.\n\n"\ desc += "Register bit can be read/set by software" %define _DESC884_ \ desc += "Abort Request\n\n"\ desc += "Set by software to abort the current transmission.\n\n"\ desc += "Cleared by hardware when the transmission has been aborted. LINFlexD aborts the\n"\ desc += "transmission at the end of the current bit. This bit can abort a wakeup request\n"\ desc += "also and can be used in UART mode also.\n\n"\ desc += "Register bit can be read/set by software\n\n"\ desc += "Register bit can be read/set by software" %define _DESC885_ \ desc += "Header Transmission Request\n\n"\ desc += "Set by software to request the transmission of the LIN Header.\n\n"\ desc += "Cleared by hardware when the request has been completed or on abort request.\n"\ desc += "This bit has no effect in UART mode.\n\n"\ desc += "In master mode, if both HTRQ and ABRQ are set at the same time then ABRQ has no\n"\ desc += "effect. Similarly, in slave mode after header reception, if DTRQ and ABRQ are\n"\ desc += "simultaneously set then ABRQ has no effect." %define _DESC886_ \ desc += "Buffer Identifier Register. This register contains the bits which provide\n"\ desc += "information about the identifier of the transaction and other related\n"\ desc += "information.\n\n"\ desc += "All the fields (ID, CSS, DIR, DFL) of the BIDR register must be updated when an\n"\ desc += "ID filter (enabled) in Slave mode (Tx or Rx) matches the ID received." %define _DESC887_ \ desc += "Data Field Length\n\n"\ desc += "Number of data bytes in the response part of the frame.\n\n"\ desc += "DFL = Number of data bytes - 1\n\n"\ desc += "DFL[5:3] is provided for extended frames. Normally LIN mode will use DFL[2:0].\n"\ desc += "Identifier filters are now compatible with DFL[5:0] also." %define _DESC888_ \ desc += "Direction\n\n"\ desc += "This bit controls the direction of the data field." %define _DESC889_ \ desc += "Classic Checksum\n\n"\ desc += "This bit controls the type of checksum applied on the current message." %define _DESC890_ \ desc += "Identifier\n\n"\ desc += "Identifier part of the identifier field without the identifier parity. This\n"\ desc += "field can be written only in Master mode (MME = '1')." %define _DESC891_ \ desc += "Buffer Data Register Least Significant. This register is a part of an 8-byte\n"\ desc += "data buffer." %define _DESC892_ \ desc += "Data Byte 3\n\n"\ desc += "Data byte 3 of the data field." %define _DESC893_ \ desc += "Data Byte 2\n\n"\ desc += "Data byte 2 of the data field." %define _DESC894_ \ desc += "Data Byte 1\n\n"\ desc += "Data byte 1of the data field." %define _DESC895_ \ desc += "Data Byte 0\n\n"\ desc += "Data byte 0 of the data field." %define _DESC896_ \ desc += "Buffer Data Register Most Significant. This register is a part of an 8-byte\n"\ desc += "data buffer." %define _DESC897_ \ desc += "Data Byte 7\n\n"\ desc += "Data byte 7 of the data field." %define _DESC898_ \ desc += "Data Byte 6\n\n"\ desc += "Data byte 6 of the data field." %define _DESC899_ \ desc += "Data Byte 5\n\n"\ desc += "Data byte 5of the data field." %define _DESC900_ \ desc += "Data Byte 4\n\n"\ desc += "Data byte 4 of the data field." %define _DESC901_ \ desc += "Identifier Filter Enable Register. This register enables/disables a particular\n"\ desc += "filter." %define _DESC902_ \ desc += "Filter active\n\n"\ desc += "The software sets the bit FACT[x] to activate the filter x in Identifier list\n"\ desc += "mode.\n\n"\ desc += "Register bit can be read in any mode, written only in initialization mode.\n\n"\ desc += "1. In Identifier mask mode, FACT (2n+1) have no effect on the corresponding\n"\ desc += "filters as they act as mask for the Identifier 2n.\n\n"\ desc += "2. The length of this field depends on the value of no_of_filters.\n\n"\ desc += "3. The register diagram depicts the maximum no_of_filters, which can be up to\n"\ desc += "16.\n\n"\ desc += "Refer to chip configuration details to see the number of filters used in the\n"\ desc += "device." %define _DESC903_ \ desc += "Identifier Filter Match Index. This register contains the index corresponding\n"\ desc += "to the received ID. It can be used to read or write the data directly in RAM." %define _DESC904_ \ desc += "Filter match index\n\n"\ desc += "Upon a filter match with xth filter - IFMI[4:0] = x+1. On no match IFMI is\n"\ desc += "equal to 00h.\n\n"\ desc += "This register contains the index corresponding to the received identifier. It\n"\ desc += "can be used to directly write or read the data in SRAM (see Slave mode for\n"\ desc += "more details)." %define _DESC905_ \ desc += "Identifier Filter Mode Register. This register configures the modes of\n"\ desc += "filters." %define _DESC906_ \ desc += "Filter mode\n\n"\ desc += "Register bit can be read in any mode, written only in initialization mode." %define _DESC907_ \ desc += "Identifier Filter Control Register. This register is read-only in normal mode\n"\ desc += "and can be programmed only in Initialization mode.\n\n"\ desc += "Even-numbered instances (IFCR0, IFCR2, IFCR4, ...) of this register act as\n"\ desc += "filters in both Identifier list and Identifier mask modes.\n\n"\ desc += "Odd-numbered instances (IFCR1, IFCR3, IFCR5, ...) of this register act:\n\n"\ desc += "As filters in Identifier list mode As a mask for the preceding-numbered\n"\ desc += "register in identifier mask mode Refer to chip configuration details to see\n"\ desc += "the number of filters used in the device." %define _DESC908_ \ desc += "Number of data bytes in the response part of the frame.\n\n"\ desc += "DFL[5:0] = Number of data bytes - 1\n\n"\ desc += "Register bit can be read in any mode, written only in initialization mode." %define _DESC909_ \ desc += "This bit controls the direction of the data field.\n\n"\ desc += "Register bit can be read in any mode, written only in initialization mode." %define _DESC910_ \ desc += "This bit controls the type of checksum applied on the current message.\n\n"\ desc += "Register bit can be read in any mode, written only in initialization mode." %define _DESC911_ \ desc += "Identifier part of the identifier field without the identifier parity.\n\n"\ desc += "Register bit can be read in any mode, written only in initialization mode." %define _DESC912_ \ desc += "Global Control Register. This register is read-only in Normal mode and can be\n"\ desc += "programmed only in Initialization mode. This is a global control register -- in\n"\ desc += "other words, the register configuration will be applied in LIN mode as well as\n"\ desc += "in UART mode.\n\n"\ desc += "The address offset depends on the no_of_filters. Refer to the chip\n"\ desc += "configuration details for the number of filters used in this device." %define _DESC913_ \ desc += "Transmit data first bit MSB\n\n"\ desc += "This bit controls the first bit of transmit data (payload only) as MSB/LSB in\n"\ desc += "both UART and LIN modes.\n\n"\ desc += "Register bit can be read in any mode, written only in initialization mode." %define _DESC914_ \ desc += "Received data first bit MSB\n\n"\ desc += "This bit controls the first bit of received data (payload only) as MSB/LSB both\n"\ desc += "in UART and LIN modes.\n\n"\ desc += "Register bit can be read in any mode, written only in initialization mode." %define _DESC915_ \ desc += "Transmit data level inversion selection\n\n"\ desc += "This bit controls the data inversion of transmitted data (payload only) in both\n"\ desc += "UART and LIN modes.\n\n"\ desc += "Register bit can be read in any mode, written only in initialization mode." %define _DESC916_ \ desc += "Received data level inversion selection\n\n"\ desc += "This bit controls the data inversion of received data (payload only) in both\n"\ desc += "UART and LIN modes.\n\n"\ desc += "Register bit can be read in any mode, written only in initialization mode." %define _DESC917_ \ desc += "1/2 stop bit configuration\n\n"\ desc += "This bit controls the number of stop bit transmitted data in both UART and LIN\n"\ desc += "modes.\n\n"\ desc += "The stop bit is configured for all the fields (Delimiter, Sync, ID, Checksum,\n"\ desc += "Payload).\n\n"\ desc += "Register bit can be read in any mode, written only in initialization mode." %define _DESC918_ \ desc += "Soft reset\n\n"\ desc += "SR executes a soft reset of the LINFlexD controller (FSMs, FIFO pointers,\n"\ desc += "counters, timers, status and error registers) without modifying the\n"\ desc += "configuration registers when a 1 write operation is performed. This bit should\n"\ desc += "be cleared by software to perform further operations (this bit is not cleared\n"\ desc += "by hardware).\n\n"\ desc += "Register bit can be written only be software in initialization mode. Bit is\n"\ desc += "always read 0 by software.\n\n"\ desc += "The following table describes the register fields reset by SR." %define _DESC919_ \ desc += "UART Preset Timeout Register. This register contains the preset value of the\n"\ desc += "timeout register in UART mode and is programmed according to the number of bits\n"\ desc += "to be received. . This register can be written by software any time.\n\n"\ desc += "The address offset depends on no_of_filters. Refer to the chip configuration\n"\ desc += "details to see the number of filters used in the device" %define _DESC920_ \ desc += "Preset Timeout\n\n"\ desc += "PTO defines the preset value of timeout counter. A zero-value is forbidden,\n"\ desc += "otherwise the UARTSR[TO] status bit is immediately set. Refer also to register\n"\ desc += "UARTCTO." %define _DESC921_ \ desc += "UART Current Timeout Register. This register contains the current timeout value\n"\ desc += "in UART mode, and is used in conjunction with the\n\n"\ desc += "UARTPTO register (see UARTPTO to monitor the number of bits received by UART.\n"\ desc += "UART timeout works in both CPU and DMA modes.\n\n"\ desc += "The timeout counter:\n\n"\ desc += "Starts at zero and counts upward\n\n"\ desc += "Is clocked with LIN_CLK / (16 * LDIV) synchronized to PBRIDGEx_CLK\n\n"\ desc += "Is automatically enabled when UARTCR[RXEN] = 1\n\n"\ desc += "It is reset when:\n\n"\ desc += "Number of frames received is equal to NEF bits\n\n"\ desc += "UARTCTO becomes equal to UARTPTO\n\n"\ desc += "Whenever UARTPTO is written\n\n"\ desc += "When DRF is set and DTU bit = 1\n\n"\ desc += "The address offset depends on no_of_filters. Refer to chip configuration\n"\ desc += "details to see the number of filters used in the device." %define _DESC922_ \ desc += "Current Timeout\n\n"\ desc += "CTO defines the current value of the timeout counter. CTO is a read-only field.\n"\ desc += "CTO is reset every time UARTPTO is re-initialized, or UARTCTO = UARTPTO, or by\n"\ desc += "hard/soft reset. When the CTO value matches the preset value (UARTPTO), the\n"\ desc += "status bit UARTSR[TO] is set." %define _DESC923_ \ desc += "DMA Tx Enable Register. This register enables the DMA TX interface. This\n"\ desc += "register can be written and read by software anytime.\n\n"\ desc += "The address offset depends on no_of_filters. Refer to chip configuration\n"\ desc += "details to see the number of filters used in the device." %define _DESC924_ \ desc += "Reserved\n\n"\ desc += "The number of reserved bits varies, and is equal to 2 TX_CH_NUM -1. Refer to\n"\ desc += "the chip configuration details for the value of TX_CH_NUM used in this device." %define _DESC925_ \ desc += "DMA Tx channel Y enable\n\n"\ desc += "The actual size of the register DMATXE depends on the value of the static\n"\ desc += "parameter TX_CH_NUM. When DMATXE = 0x00000000, the DMA TX interface FSM is\n"\ desc += "forced (soft reset) in Idle state. Refer to the chip configuration details for\n"\ desc += "the value of TX_CH_NUM used in this device." %define _DESC926_ \ desc += "DMA Rx Enable Register. This register enables the DMA RX interface. This\n"\ desc += "register can be written and read by software any time.\n\n"\ desc += "The address offset depends on no_of_filters. Refer to device configuration\n"\ desc += "chapter to see the number of filters used in the device." %define _DESC927_ \ desc += "Reserved\n\n"\ desc += "The number of reserved bits varies, and is equal to 2 RX_CH_NUM -1. Refer to\n"\ desc += "the device configuration chapter for the value of RX_CH_NUM used in this\n"\ desc += "device." %define _DESC928_ \ desc += "DMA Rx channel Y enable\n\n"\ desc += "The actual size of the register DMARXE depends on the value of the static\n"\ desc += "parameter RX_CH_NUM. When DMARXE = 0x00000000, the DMA RX interface FSM is\n"\ desc += "forced (soft reset) in Idle state. Refer to the device configuration chapter\n"\ desc += "for the value of RX_CH_NUM used in this device." %define _DESC929_ \ desc += "PCS Switch Duration Register. This register contains the progressive system\n"\ desc += "clock switching duration for each step. See #Rcz59308 for details on how to\n"\ desc += "set this value." %define _DESC930_ \ desc += "Switch Duration - This value defines the duration of one PCS clock switch step\n"\ desc += "in terms of 16 MHz internal RC oscillator (IRCOSC) cycles." %define _DESC931_ \ desc += "PCS Divider Change for external crystal oscillator Register. This register\n"\ desc += "defines the rate of frequency change and initial change value for the\n"\ desc += "progressive system clock switching when switching the system clock source to or\n"\ desc += "from the external crystal oscillator on ramp-up and ramp-down, respectively.\n"\ desc += "See #Rcz59308 for details on how to set these values.\n\n"\ desc += "Byte write accesses are not allowed for the INIT field of this register. Such\n"\ desc += "accesses do not result in an exception, but the value is not loaded with the\n"\ desc += "new value." %define _DESC932_ \ desc += "Divider Change Initial Value - This is initial change value of the clock\n"\ desc += "divider for the clock ramp-up phase when switching to the external crystal\n"\ desc += "oscillator." %define _DESC933_ \ desc += "Divider Change Rate - This value controls the change value of the clock divider\n"\ desc += "for the clock ramp-up and ramp-down phase when switching to/from the external\n"\ desc += "crystal oscillator." %define _DESC934_ \ desc += "PCS Divider Start for external crystal oscillator Register. This register\n"\ desc += "defines the initial division value for the progressive system clock switching\n"\ desc += "when switching the system clock source to the external crystal oscillator on\n"\ desc += "ramp-up. Register n corresponds to system clock source n . See #Rcz59308 for\n"\ desc += "details on how to set these values.\n\n"\ desc += "Byte and half-word write accesses are not allowed for this register. Such\n"\ desc += "accesses do not result in an exception, but the value is not loaded with the\n"\ desc += "new value." %define _DESC935_ \ desc += "Divider Start Value - This is the start value of the clock divider for the\n"\ desc += "clock ramp-up phase when switching to the external crystal oscillator." %define _DESC936_ \ desc += "PCS Divider End for external crystal oscillator Register. This register defines\n"\ desc += "the final division value for the progressive system clock switching when\n"\ desc += "switching the system clock source from the external crystal oscillator on\n"\ desc += "ramp-down. See #Rcz59308 for details on how to set This value.\n\n"\ desc += "Byte and half-word write accesses are not allowed for this register. Such\n"\ desc += "accesses do not result in an exception, but the value is not loaded with the\n"\ desc += "new value." %define _DESC937_ \ desc += "Divider End Value - This is the clock divider end value for the clock ramp-down\n"\ desc += "phase when switching from the external crystal oscillator." %define _DESC938_ \ desc += "PCS Divider Change for PLL0 PHI Register. This register defines the rate of\n"\ desc += "frequency change and initial change value for the progressive system clock\n"\ desc += "switching when switching the system clock source to or from the PLL0 PHI on\n"\ desc += "ramp-up and ramp-down, respectively. See #Rcz59308 for details on how to set\n"\ desc += "these values.\n\n"\ desc += "Byte write accesses are not allowed for the INIT field of this register. Such\n"\ desc += "accesses do not result in an exception, but the value is not loaded with the\n"\ desc += "new value." %define _DESC939_ \ desc += "Divider Change Initial Value - This is initial change value of the clock\n"\ desc += "divider for the clock ramp-up phase when switching to the PLL0 PHI." %define _DESC940_ \ desc += "Divider Change Rate - This value controls the change value of the clock divider\n"\ desc += "for the clock ramp-up and ramp-down phase when switching to/from the PLL0\n"\ desc += "PHI." %define _DESC941_ \ desc += "PCS Divider Start for PLL0 PHI Register. This register defines the initial\n"\ desc += "division value for the progressive system clock switching when switching the\n"\ desc += "system clock source to the PLL0 PHI on ramp-up. See #Rcz59308 for details on\n"\ desc += "how to set this value.\n\n"\ desc += "Byte and half-word write accesses are not allowed for this register. Such\n"\ desc += "accesses do not result in an exception, but the value is not loaded with the\n"\ desc += "new value." %define _DESC942_ \ desc += "Divider Start Value - This is the start value of the clock divider for the\n"\ desc += "clock ramp-up phase when switching to the PLL0 PHI." %define _DESC943_ \ desc += "PCS Divider End for PLL0 PHI Register. This register defines the final division\n"\ desc += "value for the progressive system clock switching when switching the system\n"\ desc += "clock source from the PLL0 PHI on ramp-down. See #Rcz59308 for details on how\n"\ desc += "to set This value.\n\n"\ desc += "Byte and half-word write accesses are not allowed for this register. Such\n"\ desc += "accesses do not result in an exception, but the value is not loaded with the\n"\ desc += "new value." %define _DESC944_ \ desc += "Divider End Value - This is the clock divider end value for the clock ramp-down\n"\ desc += "phase when switching from the PLL0 PHI." %define _DESC945_ \ desc += "PCS Divider Change for PLL0 PHI1 Register. This register defines the rate of\n"\ desc += "frequency change and initial change value for the progressive system clock\n"\ desc += "switching when switching the system clock source to or from the PLL0 PHI1 on\n"\ desc += "ramp-up and ramp-down, respectively. See #Rcz59308 for details on how to set\n"\ desc += "these values.\n\n"\ desc += "Byte write accesses are not allowed for the INIT field of this register. Such\n"\ desc += "accesses do not result in an exception, but the value is not loaded with the\n"\ desc += "new value." %define _DESC946_ \ desc += "Divider Change Initial Value - This is initial change value of the clock\n"\ desc += "divider for the clock ramp-up phase when switching to the reserved." %define _DESC947_ \ desc += "Divider Change Rate - This value controls the change value of the clock divider\n"\ desc += "for the clock ramp-up and ramp-down phase when switching to/from the\n"\ desc += "reserved." %define _DESC948_ \ desc += "PCS Divider Start for PLL0 PHI1 Register. This register defines the initial\n"\ desc += "division value for the progressive system clock switching when switching the\n"\ desc += "system clock source to the PLL0 PHI1 on ramp-up. See #Rcz59308 for details on\n"\ desc += "how to set this value.\n\n"\ desc += "Byte and half-word write accesses are not allowed for this register. Such\n"\ desc += "accesses do not result in an exception, but the value is not loaded with the\n"\ desc += "new value." %define _DESC949_ \ desc += "Divider Start Value - This is the start value of the clock divider for the\n"\ desc += "clock ramp-up phase when switching to the reserved." %define _DESC950_ \ desc += "PCS Divider End for PLL0 PHI1 Register. This register defines the final\n"\ desc += "division value for the progressive system clock switching when switching the\n"\ desc += "system clock source from the PLL0 PHI1 on ramp-down. See #Rcz59308 for details\n"\ desc += "on how to set This value.\n\n"\ desc += "Byte and half-word write accesses are not allowed for this register. Such\n"\ desc += "accesses do not result in an exception, but the value is not loaded with the\n"\ desc += "new value." %define _DESC951_ \ desc += "Divider End Value - This is the clock divider end value for the clock ramp-down\n"\ desc += "phase when switching from the reserved." %define _DESC952_ \ desc += "System Clock Select Status Register. This register provides the current system\n"\ desc += "clock source selection." %define _DESC953_ \ desc += "System Clock Source Selection Status - This value indicates the current source\n"\ desc += "for the system clock." %define _DESC954_ \ desc += "Switch Trigger cause - This value indicates the cause for the latest clock\n"\ desc += "source switch." %define _DESC955_ \ desc += "Switch In Progress" %define _DESC956_ \ desc += "System Clock Divider Configuration 0 Register. This register controls system\n"\ desc += "clock divider 0. See #Rcz24362 for details on division value limitations.\n\n"\ desc += "Byte and half-word write accesses are not allowed for this register. Such\n"\ desc += "accesses do not result in an exception, however the value is not loaded with\n"\ desc += "the new value." %define _DESC957_ \ desc += "Divider 1 Enable - This divider is always enabled. Therefore, this bit is\n"\ desc += "read-only and always returns a value of '1'." %define _DESC958_ \ desc += "Divider 1 Division Value - The resultant core clock will have a period 'DIV +\n"\ desc += "1' times that of the system clock. If DE is set to '0' (divider 1 is disabled),\n"\ desc += "any write access to the DIV field is ignored and the core clock remains\n"\ desc += "disabled." %define _DESC959_ \ desc += "System Clock Divider Configuration 1 Register. This register controls system\n"\ desc += "clock divider 1. See #Rcz24362 for details on division value limitations.\n\n"\ desc += "Byte and half-word write accesses are not allowed for this register. Such\n"\ desc += "accesses do not result in an exception, but the value is not loaded with the\n"\ desc += "new value." %define _DESC960_ \ desc += "Divider 1 Division Value - The resultant AIPS clock will have a period 'DIV +\n"\ desc += "1' times that of the system clock. If DE is set to '0' (divider 1 is disabled),\n"\ desc += "any write access to the DIV field is ignored and the AIPS clock remains\n"\ desc += "disabled." %define _DESC961_ \ desc += "Aux Clock 0 Select Control Register. This register is used to select the\n"\ desc += "current clock source for the following clocks:\n\n"\ desc += "undivided: (unused) divided by auxiliary clock 0 divider 0: peripheral clock \n"\ desc += "divided by auxiliary clock 0 divider 1: Sigma-Delta ADC clock divided by\n"\ desc += "auxiliary clock 0 divider 2: SAR ADC clock See #Rcz65889 for details." %define _DESC962_ \ desc += "Auxiliary Clock 0 Source Selection Control - Selects the source for auxiliary\n"\ desc += "clock 0." %define _DESC963_ \ desc += "Aux Clock 0 Select Status Register. This register provides the current\n"\ desc += "auxiliary clock 0 source selection." %define _DESC964_ \ desc += "Auxiliary Clock 0 Source Selection Status - This value indicates the current\n"\ desc += "source for auxiliary clock 0." %define _DESC965_ \ desc += "Aux Clock 0 Divider Configuration 0 Register. This register controls auxiliary\n"\ desc += "clock 0 divider 0.\n\n"\ desc += "Byte and half-word write accesses are not allowed for this register. Such\n"\ desc += "accesses do not result in an exception, but the value is not loaded with the\n"\ desc += "new value." %define _DESC966_ \ desc += "Divider Enable" %define _DESC967_ \ desc += "Divider Division Value - The resultant peripheral clock will have a period 'DIV\n"\ desc += "+ 1' times that of auxiliary clock 0. If DE is set to 0 (divider 0 is\n"\ desc += "disabled), any write access to the DIV field is ignored and the peripheral\n"\ desc += "clock remains disabled." %define _DESC968_ \ desc += "Aux Clock 0 Divider Configuration 1 Register. This register controls auxiliary\n"\ desc += "clock 0 divider 1.\n\n"\ desc += "Byte and half-word write accesses are not allowed for this register. Such\n"\ desc += "accesses do not result in an exception, but the value is not loaded with the\n"\ desc += "new value." %define _DESC969_ \ desc += "Divider Division Value - The resultant Sigma-Delta ADC clock will have a period\n"\ desc += "'DIV + 1' times that of auxiliary clock 0. If DE is set to 0 (divider 1 is\n"\ desc += "disabled), any write access to the DIV field is ignored and the Sigma-Delta ADC\n"\ desc += "clock remains disabled." %define _DESC970_ \ desc += "Aux Clock 0 Divider Configuration 2 Register. This register controls auxiliary\n"\ desc += "clock 0 divider 2.\n\n"\ desc += "Byte and half-word write accesses are not allowed for this register. Such\n"\ desc += "accesses do not result in an exception, but the value is not loaded with the\n"\ desc += "new value." %define _DESC971_ \ desc += "Divider Division Value - The resultant SAR ADC clock will have a period 'DIV +\n"\ desc += "1' times that of auxiliary clock 0. If DE is set to 0 (divider 2 is disabled),\n"\ desc += "any write access to the DIV field is ignored and the SAR ADC clock remains\n"\ desc += "disabled." %define _DESC972_ \ desc += "Aux Clock 1 Select Control Register. This register is used to select the\n"\ desc += "current clock source for the following clocks:\n\n"\ desc += "undivided: (unused) divided by auxiliary clock 1 divider 0: LFAST clock See \n"\ desc += "#Rcz50871 for details." %define _DESC973_ \ desc += "Auxiliary Clock 1 Source Selection Control - This value selects the current\n"\ desc += "source for auxiliary clock 1." %define _DESC974_ \ desc += "Aux Clock 1 Select Status Register. This register provides the current\n"\ desc += "auxiliary clock 1 source selection." %define _DESC975_ \ desc += "Auxiliary Clock 1 Source Selection Status - This value indicates the current\n"\ desc += "source for auxiliary clock 1." %define _DESC976_ \ desc += "Aux Clock 1 Divider Configuration 0 Register. This register controls auxiliary\n"\ desc += "clock 1 divider 0.\n\n"\ desc += "Byte and half-word write accesses are not allowed for this register. Such\n"\ desc += "accesses do not result in an exception, but the value is not loaded with the\n"\ desc += "new value." %define _DESC977_ \ desc += "Divider Division Value - The resultant LFAST clock will have a period 'DIV + 1'\n"\ desc += "times that of auxiliary clock 1. If DE is set to 0 (divider 0 is disabled), any\n"\ desc += "write access to the DIV field is ignored and the LFAST clock remains\n"\ desc += "disabled." %define _DESC978_ \ desc += "Aux Clock 2 Divider Configuration 0 Register. This register controls auxiliary\n"\ desc += "clock 2 divider 0 when the 'CAN jitter' feature is not enabled (see #Rcz19103\n"\ desc += ").\n\n"\ desc += "Byte and half-word write accesses are not allowed for this register. Such\n"\ desc += "accesses do not result in an exception, but the value is not loaded with the\n"\ desc += "new value." %define _DESC979_ \ desc += "Divider Division Value - The resultant SENT will have a period 'DIV + 1' times\n"\ desc += "that of auxiliary clock 2. If DE is set to 0 (divider 0 is disabled), any write\n"\ desc += "access to the DIV field is ignored and the SENT remains disabled." %define _DESC980_ \ desc += "Aux Clock 3 Select Control Register. [BLG_CGM_0002]This register is used to\n"\ desc += "select the current clock source for the PLL0 reference clock.[end]\n\n"\ desc += "See #Rcz85197 for details." %define _DESC981_ \ desc += "Auxiliary Clock 3 Source Selection Control - This value selects the current\n"\ desc += "source for auxiliary clock 3." %define _DESC982_ \ desc += "Aux Clock 3 Select Status Register. This register provides the current\n"\ desc += "auxiliary clock 3 source selection." %define _DESC983_ \ desc += "Auxiliary Clock 3 Source Selection Status - This value indicates the current\n"\ desc += "source for auxiliary clock 3." %define _DESC984_ \ desc += "Aux Clock 7 Select Control Register. This register is used to select the\n"\ desc += "current clock source for the following clocks:\n\n"\ desc += "undivided: (unused) divided by auxiliary clock 7 divider 0: SYSCLK1 pin clock \n"\ desc += "See #Rcz63657 for details." %define _DESC985_ \ desc += "Auxiliary Clock 7 Source Selection Control - This value selects the current\n"\ desc += "source for auxiliary clock 7." %define _DESC986_ \ desc += "Aux Clock 7 Select Status Register. This register provides the current\n"\ desc += "auxiliary clock 7 source selection." %define _DESC987_ \ desc += "Auxiliary Clock 7 Source Selection Status - This value indicates the current\n"\ desc += "source for auxiliary clock 7." %define _DESC988_ \ desc += "Aux Clock 7 Divider Configuration 0 Register. This register controls auxiliary\n"\ desc += "clock 7 divider 0.\n\n"\ desc += "Byte and half-word write accesses are not allowed for this register. Such\n"\ desc += "accesses do not result in an exception, but the value is not loaded with the\n"\ desc += "new value." %define _DESC989_ \ desc += "Divider Division Value - The resultant SYSCLK1 pin clock will have a period\n"\ desc += "'DIV + 1' times that of auxiliary clock 7. If DE is set to 0 (divider 0 is\n"\ desc += "disabled), any write access to the DIV field is ignored and the SYSCLK1 pin\n"\ desc += "clock remains disabled." %define _DESC990_ \ desc += "Aux Clock 8 Select Control Register. This register is used to select the\n"\ desc += "current clock source for the following clocks:\n\n"\ desc += "undivided: (unused) divided by auxiliary clock 8 divider 0: CCCU clock See \n"\ desc += "#Rcz76324 for details." %define _DESC991_ \ desc += "Auxiliary Clock 8 Source Selection Control - This value selects the current\n"\ desc += "source for auxiliary clock 8." %define _DESC992_ \ desc += "Aux Clock 8 Select Status Register. This register provides the current\n"\ desc += "auxiliary clock 8 source selection." %define _DESC993_ \ desc += "Auxiliary Clock 8 Source Selection Status - This value indicates the current\n"\ desc += "source for auxiliary clock 8." %define _DESC994_ \ desc += "Aux Clock 8 Divider Configuration 0 Register. This register controls auxiliary\n"\ desc += "clock 8 divider 0 when the 'CAN jitter' feature is not enabled (see #Rcz19103\n"\ desc += ").\n\n"\ desc += "Byte and half-word write accesses are not allowed for this register. Such\n"\ desc += "accesses do not result in an exception, but the value is not loaded with the\n"\ desc += "new value." %define _DESC995_ \ desc += "Divider Division Value - The resultant CCCU clock will have a period 'DIV + 1'\n"\ desc += "times that of auxiliary clock 8. If DE is set to 0 (divider 0 is disabled), any\n"\ desc += "write access to the DIV field is ignored and the CCCU clock remains disabled." %define _DESC996_ \ desc += "Aux Clock 10 Select Control Register. This register is used to select the\n"\ desc += "current clock source for the for the following clocks:\n\n"\ desc += "undivided: (unused) divided by auxiliary clock 10 divider 0: FEC reference\n"\ desc += "clock See #Rcz85098 for details." %define _DESC997_ \ desc += "Auxiliary Clock 10 Source Selection Control - This value selects the current\n"\ desc += "source for auxiliary clock 10." %define _DESC998_ \ desc += "Aux Clock 10 Select Status Register. This register provides the current\n"\ desc += "auxiliary clock 10 source selection." %define _DESC999_ \ desc += "Auxiliary Clock 10 Source Selection Status - This value indicates the current\n"\ desc += "source for auxiliary clock 10." %define _DESC1000_ \ desc += "Aux Clock 10 Divider Configuration 0 Register. This register controls auxiliary\n"\ desc += "clock 10 divider 0.\n\n"\ desc += "Byte and half-word write accesses are not allowed for this register. Such\n"\ desc += "accesses do not result in an exception, but the value is not be loaded with the\n"\ desc += "new value." %define _DESC1001_ \ desc += "Divider Division Value - The resultant FEC reference clock will have a period\n"\ desc += "'DIV + 1' times that of auxiliary clock 10. If DE is set to 0 (divider 0 is\n"\ desc += "disabled), any write access to the DIV field is ignored and the FEC reference\n"\ desc += "clock remains disabled." %define _DESC1002_ \ desc += "Aux Clock 11 Select Control Register. This register is used to select the\n"\ desc += "current clock source for the for the following clocks:\n\n"\ desc += "undivided: (unused) divided by auxiliary clock 11 divider 0: DSPI clock 0 \n"\ desc += "divided by auxiliary clock 11 divider 1: DSPI clock 1 See #Rcz76324 for\n"\ desc += "details." %define _DESC1003_ \ desc += "Auxiliary Clock 11 Source Selection Control - This value selects the current\n"\ desc += "source for auxiliary clock 11." %define _DESC1004_ \ desc += "Aux Clock 11 Select Status Register. This register provides the current\n"\ desc += "auxiliary clock 11 source selection." %define _DESC1005_ \ desc += "Auxiliary Clock 11 Source Selection Status - This value indicates the current\n"\ desc += "source for auxiliary clock 11." %define _DESC1006_ \ desc += "Aux Clock 11 Divider Configuration 0 Register. This register controls auxiliary\n"\ desc += "clock 11 divider 0. See #Rcz59362 for divider characteristics.\n\n"\ desc += "Byte and half-word write accesses are not allowed for this register. Such\n"\ desc += "accesses do not result in an exception, but the value is not loaded with the\n"\ desc += "new value." %define _DESC1007_ \ desc += "Divider Enable\n\n"\ desc += "0 Disable auxiliary clock 11 divider 0\n\n"\ desc += "1 Enable auxiliary clock 11 divider 0" %define _DESC1008_ \ desc += "Divider Division Value - The resultant DSPI clock 0 will have a period 'DIV +\n"\ desc += "1' times that of auxiliary clock 11. If DE is set to 0 (divider 0 is disabled),\n"\ desc += "any write access to the DIV field is ignored and the DSPI clock 0 remains\n"\ desc += "disabled." %define _DESC1009_ \ desc += "Divider Value Format - This falue indicates the format of the division value\n"\ desc += "for calculating the division factor" %define _DESC1010_ \ desc += "Aux Clock 11 Divider Configuration 1 Register. This register controls auxiliary\n"\ desc += "clock 11 divider 1.\n\n"\ desc += "Byte and half-word write accesses are not allowed for this register. Such\n"\ desc += "accesses do not result in an exception, but the value is not loaded with the\n"\ desc += "new value." %define _DESC1011_ \ desc += "Divider Division Value - The resultant DSPI clock 1 will have a period 'DIV +\n"\ desc += "1' times that of auxiliary clock 11. If DE is set to 0 (divider 0 is disabled),\n"\ desc += "any write access to the DIV field is ignored and the DSPI clock 1 remains\n"\ desc += "disabled." %define _DESC1012_ \ desc += "Global Status Register. \n\n"\ desc += "This register contains global mode status." %define _DESC1013_ \ desc += "Current chip mode status" %define _DESC1014_ \ desc += "Mode transition status" %define _DESC1015_ \ desc += "Output power-down status - This bit specifies output power-down status of I/Os.\n"\ desc += "This bit is asserted whenever outputs of pads are forced to high impedance\n"\ desc += "state or the pads power sequence driver is switched off." %define _DESC1016_ \ desc += "Main voltage regulator status" %define _DESC1017_ \ desc += "Flash availability status" %define _DESC1018_ \ desc += "primary PLL status" %define _DESC1019_ \ desc += "external crystal oscillator status" %define _DESC1020_ \ desc += "16 MHz internal RC oscillator status" %define _DESC1021_ \ desc += "System clock switch status - These bits specify the system clock currently used\n"\ desc += "by the system." %define _DESC1022_ \ desc += "Mode Control Register. This register is used to trigger software-controlled\n"\ desc += "mode changes. Depending on the modes as enabled by ME_ME register bits,\n"\ desc += "configurations corresponding to unavailable modes are reserved and access to\n"\ desc += "ME__MC registers must respect this for successful mode requests.\n\n"\ desc += "Byte and half-word write accesses are not allowed for this register as a\n"\ desc += "predefined key is required to change its value." %define _DESC1023_ \ desc += "[SCG23.001][Covers: ADD23.026][Covers: ADD23.032]Target chip mode - These bits\n"\ desc += "provide the target chip mode to be entered by software programming[end]. The\n"\ desc += "mechanism to enter into any mode by software requires the write operation\n"\ desc += "twice: first time with key, and second time with inverted key. These bits are\n"\ desc += "automatically updated by hardware while entering SAFE on hardware request.\n"\ desc += "Also, while exiting from the HALT0 and STOP0 modes on hardware exit events,\n"\ desc += "these are updated with the appropriate RUN0...3 mode value." %define _DESC1024_ \ desc += "Control key - These bits enable write access to this register. Any write access\n"\ desc += "to the register with a value different from the keys is ignored. Read access\n"\ desc += "will always return inverted key.\n\n"\ desc += "KEY: 0101101011110000 (0x5AF0)\n\n"\ desc += "INVERTED KEY: 1010010100001111 (0xA50F)" %define _DESC1025_ \ desc += "Mode Enable Register. This register allows a way to disable the chip modes\n"\ desc += "which are not required for a given chip. RESET_FUNC, SAFE, DRUN, RUN0, and\n"\ desc += "RESET_DEST modes are always enabled." %define _DESC1026_ \ desc += "'destructive' RESET mode enable" %define _DESC1027_ \ desc += "STOP0 mode enable" %define _DESC1028_ \ desc += "HALT0 mode enable" %define _DESC1029_ \ desc += "RUN3 mode enable" %define _DESC1030_ \ desc += "RUN2 mode enable" %define _DESC1031_ \ desc += "RUN1 mode enable" %define _DESC1032_ \ desc += "RUN0 mode enable" %define _DESC1033_ \ desc += "DRUN mode enable" %define _DESC1034_ \ desc += "SAFE mode enable" %define _DESC1035_ \ desc += "TEST mode enable" %define _DESC1036_ \ desc += "'functional' RESET mode enable" %define _DESC1037_ \ desc += "Interrupt Status Register. This register provides the current interrupt\n"\ desc += "status." %define _DESC1038_ \ desc += "Invalid mode configuration interrupt (core configuration) - This bit is set if\n"\ desc += "a write access to one of the ME_CCTLn registers is attempted while a mode\n"\ desc += "transition is in progress." %define _DESC1039_ \ desc += "Invalid mode configuration interrupt (Clock Usage) - This bit is set during a\n"\ desc += "mode transition if a clock which is required to be on by an enabled peripheral\n"\ desc += "is configured to be turned off. It is cleared by writing a '1' to this bit." %define _DESC1040_ \ desc += "Invalid mode configuration interrupt - This bit is set whenever a write\n"\ desc += "operation to ME__MC registers with invalid mode configuration is attempted. It\n"\ desc += "is cleared by writing a '1' to this bit." %define _DESC1041_ \ desc += "Invalid mode interrupt - This bit is set whenever an invalid mode transition is\n"\ desc += "requested. It is cleared by writing a '1' to this bit." %define _DESC1042_ \ desc += "SAFE mode interrupt - This bit is set whenever the chip enters SAFE mode on\n"\ desc += "hardware requests generated in the system. It is cleared by writing a '1' to\n"\ desc += "this bit." %define _DESC1043_ \ desc += "Mode transition complete interrupt - This bit is set whenever the mode\n"\ desc += "transition process completes (S_MTRANS transits from 1 to 0). It is cleared by\n"\ desc += "writing a '1' to this bit. This mode transition interrupt bit will not be set\n"\ desc += "while entering low-power modes HALT0, or STOP0." %define _DESC1044_ \ desc += "Interrupt Mask Register. This register controls whether an event generates an\n"\ desc += "interrupt or not." %define _DESC1045_ \ desc += "Invalid mode configuration (core configuration) interrupt mask" %define _DESC1046_ \ desc += "Invalid mode configuration (clock usage) interrupt mask" %define _DESC1047_ \ desc += "Invalid mode configuration interrupt mask" %define _DESC1048_ \ desc += "Invalid mode interrupt mask" %define _DESC1049_ \ desc += "SAFE mode interrupt mask" %define _DESC1050_ \ desc += "Mode transition complete interrupt mask" %define _DESC1051_ \ desc += "Invalid Mode Transition Status Register. This register provides the status bits\n"\ desc += "for the possible causes of an invalid mode interrupt." %define _DESC1052_ \ desc += "Mode Transition Illegal status - This bit is set whenever a new mode is\n"\ desc += "requested while some other mode transition process is active (S_MTRANS is '1').\n"\ desc += "Please refer to #Rdc18981 for the exceptions to this behavior. It is cleared\n"\ desc += "by writing a '1' to this bit." %define _DESC1053_ \ desc += "Mode Request Illegal status - This bit is set whenever the target mode\n"\ desc += "requested is not a valid mode with respect to current mode. It is cleared by\n"\ desc += "writing a '1' to this bit." %define _DESC1054_ \ desc += "Disabled Mode Access status - This bit is set whenever the target mode\n"\ desc += "requested is one of those disabled modes determined by ME_ME register. It is\n"\ desc += "cleared by writing a '1' to this bit." %define _DESC1055_ \ desc += "Non-existing Mode Access status - This bit is set whenever the target mode\n"\ desc += "requested is one of those non existing modes determined by ME_ME register. It\n"\ desc += "is cleared by writing a '1' to this bit." %define _DESC1056_ \ desc += "SAFE Event Active status - This bit is set whenever the chip is in SAFE mode,\n"\ desc += "SAFE event bit is pending and a new mode requested other than RESET/SAFE modes.\n"\ desc += "It is cleared by writing a '1' to this bit." %define _DESC1057_ \ desc += "Debug Mode Transition Status Register. This register provides the status of\n"\ desc += "different factors which influence mode transitions. It is used to give an\n"\ desc += "indication of why a mode transition indicated by ME_GS.S_MTRANS may be taking\n"\ desc += "longer than expected.\n\n"\ desc += "The ME_DMTS register does not indicate whether a mode transition is ongoing.\n"\ desc += "Therefore, some ME_DMTS bits may still be asserted after the mode transition\n"\ desc += "has completed." %define _DESC1058_ \ desc += "Previous chip mode - These bits show the mode in which the chip was prior to\n"\ desc += "the latest change to the current mode." %define _DESC1059_ \ desc += "MC_ME/MC_PCU Handshake Busy indicator - This bit is set if the MC_ME has\n"\ desc += "requested a mode change from the MC_PCU and the MC_PCU has not yet completed\n"\ desc += "its power-up/down sequencing. It is cleared when the MC_PCU has power-up/down\n"\ desc += "sequencing." %define _DESC1060_ \ desc += "MC_PCU Mode Change in Progress indicator - This bit is set if the MC_PCU is in\n"\ desc += "the process of powering up or down power domains. It is cleared when all\n"\ desc += "power-up/down processes have completed." %define _DESC1061_ \ desc += "Debug mode indicator - This bit is set while the chip is in debug mode." %define _DESC1062_ \ desc += "Core Clock Enable/Disable in Progress - This bit is set while any core's clock\n"\ desc += "is in the process of being enabled or disabled." %define _DESC1063_ \ desc += "Progressive System Clock Switching in Progress - This bit is set while the\n"\ desc += "progressive system clock switching process is in progress." %define _DESC1064_ \ desc += "SAFE mode request from MC_RGM is active indicator - This bit is set if a\n"\ desc += "hardware SAFE mode request has been triggered. It is cleared when the hardware\n"\ desc += "SAFE mode request has been cleared." %define _DESC1065_ \ desc += "Main VREG dependent Clock Source State Change during mode transition indicator\n"\ desc += "- This bit is set when a clock source which depends on the main voltage\n"\ desc += "regulator to be powered-up is requested to change its power up/down state. It\n"\ desc += "is cleared when the clock source has completed its state change." %define _DESC1066_ \ desc += "(Other) Clock Source dependent Clock Source State Change during mode transition\n"\ desc += "indicator - This bit is set when a clock source which depends on another clock\n"\ desc += "source to be powered-up is requested to change its power up/down state. It is\n"\ desc += "cleared when the clock source has completed its state change." %define _DESC1067_ \ desc += "IRC State Change during mode transition indicator - This bit is set when the 16\n"\ desc += "MHz internal RC oscillator is requested to change its power up/down state. It\n"\ desc += "is cleared when the 16 MHz internal RC oscillator has completed its state\n"\ desc += "change." %define _DESC1068_ \ desc += "Secondary Clock Sources State Change during mode transition indicator - This\n"\ desc += "bit is set when a secondary clock source is requested to change its power\n"\ desc += "up/down state. It is cleared when all secondary system clock sources have\n"\ desc += "completed their state changes. (A 'secondary clock source' is a clock source\n"\ desc += "other than IRC.)" %define _DESC1069_ \ desc += "System Clock Switching pending status -" %define _DESC1070_ \ desc += "FLASH State Change during mode transition indicator - This bit is set when the\n"\ desc += "FLASH is requested to change its power up/down state. It is cleared when the\n"\ desc += "DFLASH has completed its state change." %define _DESC1071_ \ desc += "Clock Disable Process Pending status for Peripherals 224...255 - This bit is\n"\ desc += "set when any peripheral has been requested to have its clock disabled. It is\n"\ desc += "cleared when all the peripherals which have been requested to have their clocks\n"\ desc += "disabled have entered the state in which their clocks may be disabled." %define _DESC1072_ \ desc += "Clock Disable Process Pending status for Peripherals 192...223 - This bit is\n"\ desc += "set when any peripheral appearing in ME_PS6 has been requested to have its\n"\ desc += "clock disabled. It is cleared when all these peripherals which have been\n"\ desc += "requested to have their clocks disabled have entered the state in which their\n"\ desc += "clocks may be disabled." %define _DESC1073_ \ desc += "Clock Disable Process Pending status for Peripherals 160...191 - This bit is\n"\ desc += "set when any peripheral appearing in ME_PS5 has been requested to have its\n"\ desc += "clock disabled. It is cleared when all these peripherals which have been\n"\ desc += "requested to have their clocks disabled have entered the state in which their\n"\ desc += "clocks may be disabled." %define _DESC1074_ \ desc += "Clock Disable Process Pending status for Peripherals 128...159 - This bit is\n"\ desc += "set when any peripheral appearing in ME_PS4 has been requested to have its\n"\ desc += "clock disabled. It is cleared when all these peripherals which have been\n"\ desc += "requested to have their clocks disabled have entered the state in which their\n"\ desc += "clocks may be disabled." %define _DESC1075_ \ desc += "Clock Disable Process Pending status for Peripherals 96...127 - This bit is set\n"\ desc += "when any peripheral appearing in ME_PS3 has been requested to have its clock\n"\ desc += "disabled. It is cleared when all these peripherals which have been requested to\n"\ desc += "have their clocks disabled have entered the state in which their clocks may be\n"\ desc += "disabled." %define _DESC1076_ \ desc += "Clock Disable Process Pending status for Peripherals 64...95 - This bit is set\n"\ desc += "when any peripheral appearing in ME_PS2 has been requested to have its clock\n"\ desc += "disabled. It is cleared when all these peripherals which have been requested to\n"\ desc += "have their clocks disabled have entered the state in which their clocks may be\n"\ desc += "disabled." %define _DESC1077_ \ desc += "Clock Disable Process Pending status for Peripherals 32...63 - This bit is set\n"\ desc += "when any peripheral appearing in ME_PS1 has been requested to have its clock\n"\ desc += "disabled. It is cleared when all these peripherals which have been requested to\n"\ desc += "have their clocks disabled have entered the state in which their clocks may be\n"\ desc += "disabled." %define _DESC1078_ \ desc += "Clock Disable Process Pending status for Peripherals 0...31 - This bit is set\n"\ desc += "when any peripheral appearing in ME_PS0 has been requested to have its clock\n"\ desc += "disabled. It is cleared when all these peripherals which have been requested to\n"\ desc += "have their clocks disabled have entered the state in which their clocks may be\n"\ desc += "disabled." %define _DESC1079_ \ desc += "RESET Mode Configuration Register. This register configures system behavior\n"\ desc += "during RESET mode.\n\n"\ desc += "The following configuration values are set according to the chip configuration:\n"\ desc += "XOSCON" %define _DESC1080_ \ desc += "Power level - These bits indicate the relative power consumption level of this\n"\ desc += "mode with respect to that of other modes. When switching between two modes with\n"\ desc += "differing power levels, system clock progressive switching is enabled." %define _DESC1081_ \ desc += "I/O output power-down control - This bit controls the output power-down of\n"\ desc += "I/Os." %define _DESC1082_ \ desc += "Main voltage regulator control - This bit specifies whether main voltage\n"\ desc += "regulator is switched off or not while entering this mode." %define _DESC1083_ \ desc += "Flash power-down control - This bit specifies the operating mode of the code\n"\ desc += "flash after entering this mode." %define _DESC1084_ \ desc += "primary PLL control" %define _DESC1085_ \ desc += "external crystal oscillator control" %define _DESC1086_ \ desc += "16 MHz internal RC oscillator control" %define _DESC1087_ \ desc += "System clock switch control - These bits specify the system clock to be used by\n"\ desc += "the system." %define _DESC1088_ \ desc += "TEST Mode Configuration Register. This register configures system behavior\n"\ desc += "during TEST mode.\n\n"\ desc += "Byte write accesses are not allowed to this register." %define _DESC1089_ \ desc += "SAFE Mode Configuration Register. This register configures system behavior\n"\ desc += "during SAFE mode.\n\n"\ desc += "Byte write accesses are not allowed to this register." %define _DESC1090_ \ desc += "DRUN Mode Configuration Register. This register configures system behavior\n"\ desc += "during DRUN mode.\n\n"\ desc += "Byte write accesses are not allowed to this register.\n\n"\ desc += "The XOSCON configuration value is set according to the chip configuration:" %define _DESC1091_ \ desc += "RUNn Mode Configuration Register. This register configures system behavior\n"\ desc += "during RUN0..3 modes.\n\n"\ desc += "Byte write accesses are not allowed to this register." %define _DESC1092_ \ desc += "HALT0 Mode Configuration Register. This register configures system behavior\n"\ desc += "during HALT0 mode.\n\n"\ desc += "Byte write accesses are not allowed to this register." %define _DESC1093_ \ desc += "STOP0 Mode Configuration Register. This register configures system behavior\n"\ desc += "during STOP0 mode.\n\n"\ desc += "Byte write accesses are not allowed to this register." %define _DESC1094_ \ desc += "Peripheral Status 0 Register. This register provides the status of the\n"\ desc += "peripherals." %define _DESC1095_ \ desc += "Peripheral status - These bits specify the current status of each peripheral\n"\ desc += "which is controlled by the MC_ME." %define _DESC1096_ \ desc += "Peripheral Status 1 Register. This register provides the status of the\n"\ desc += "peripherals." %define _DESC1097_ \ desc += "Peripheral Status 2 Register. This register provides the status of the\n"\ desc += "peripherals." %define _DESC1098_ \ desc += "Peripheral Status 3 Register. This register provides the status of the\n"\ desc += "peripherals." %define _DESC1099_ \ desc += "Peripheral Status 4 Register. This register provides the status of the\n"\ desc += "peripherals." %define _DESC1100_ \ desc += "Run Peripheral Configuration Register. These registers configure eight\n"\ desc += "different types of peripheral behavior during run modes." %define _DESC1101_ \ desc += "Peripheral control during RUN3" %define _DESC1102_ \ desc += "Peripheral control during RUN2" %define _DESC1103_ \ desc += "Peripheral control during RUN1" %define _DESC1104_ \ desc += "Peripheral control during RUN0" %define _DESC1105_ \ desc += "Peripheral control during DRUN" %define _DESC1106_ \ desc += "Peripheral control during SAFE" %define _DESC1107_ \ desc += "Peripheral control during TEST" %define _DESC1108_ \ desc += "Peripheral control during RESET" %define _DESC1109_ \ desc += "Low-Power Peripheral Configuration Register. These registers configure eight\n"\ desc += "different types of peripheral behavior during non-run modes." %define _DESC1110_ \ desc += "Peripheral control during STOP0" %define _DESC1111_ \ desc += "Peripheral control during HALT0" %define _DESC1112_ \ desc += "LFAST_0 Peripheral Control Register. Peripheral Control registers select the\n"\ desc += "configurations during run and non-run modes for each peripheral. Please refer\n"\ desc += "to the memory map for information on which ME_PCTLn locations are actually\n"\ desc += "occupied. The unoccupied locations contain a read-only byte value of 0x00." %define _DESC1113_ \ desc += "Peripheral control in debug mode - This bit controls the state of the\n"\ desc += "peripheral in debug mode\n\n"\ desc += "This feature is useful to freeze the peripheral state while entering debug. For\n"\ desc += "example, this may be used to prevent a reference timer from running while\n"\ desc += "making a debug accesses." %define _DESC1114_ \ desc += "Peripheral configuration select for non-run modes - These bits associate a\n"\ desc += "configuration as defined in the ME_LP_PC0...7 registers to the peripheral." %define _DESC1115_ \ desc += "Peripheral configuration select for run modes - These bits associate a\n"\ desc += "configuration as defined in the ME_RUN_PC0...7 registers to the peripheral." %define _DESC1116_ \ desc += "SIPI_0 Peripheral Control Register. " %define _DESC1117_ \ desc += "DECIFILTER Peripheral Control Register. " %define _DESC1118_ \ desc += "PIT_RTI_0 Peripheral Control Register. " %define _DESC1119_ \ desc += "PIT_RTI_1 Peripheral Control Register. " %define _DESC1120_ \ desc += "DMAMUX_0 Peripheral Control Register. " %define _DESC1121_ \ desc += "ADCSD_2 Peripheral Control Register. " %define _DESC1122_ \ desc += "MCAN_2 Peripheral Control Register. " %define _DESC1123_ \ desc += "MCAN_1 Peripheral Control Register. " %define _DESC1124_ \ desc += "CCCU Peripheral Control Register. " %define _DESC1125_ \ desc += "CAN_RAM_CTRL Peripheral Control Register. " %define _DESC1126_ \ desc += "LINFlexD_14 Peripheral Control Register. " %define _DESC1127_ \ desc += "LINFlexD_1 Peripheral Control Register. " %define _DESC1128_ \ desc += "LINFlexD_0 Peripheral Control Register. " %define _DESC1129_ \ desc += "DSPI_4 Peripheral Control Register. " %define _DESC1130_ \ desc += "DSPI_0 Peripheral Control Register. " %define _DESC1131_ \ desc += "SENT_0 Peripheral Control Register. " %define _DESC1132_ \ desc += "ADCSAR_b Peripheral Control Register. " %define _DESC1133_ \ desc += "ADCSAR_4 Peripheral Control Register. " %define _DESC1134_ \ desc += "ADCSAR_0 Peripheral Control Register. " %define _DESC1135_ \ desc += "GTMINT Peripheral Control Register. " %define _DESC1136_ \ desc += "Core Status Register. This register provides the status of each core." %define _DESC1137_ \ desc += "Core status 0 - This bits specifies the current status of core_0 which is\n"\ desc += "controlled by the ME_CCTL0 register." %define _DESC1138_ \ desc += "core_0 Control Register. This register controls whether core_0 is disabled or\n"\ desc += "running during run modes.\n\n"\ desc += "This register cannot be written after a mode change request has been made until\n"\ desc += "the mode transition has completed (i.e., while the S_MTRANS bit of the ME_GS\n"\ desc += "register = '1'). A write access to this register during this time will result\n"\ desc += "in the ICONF_CC flag in the ME_IS register being asserted." %define _DESC1139_ \ desc += "Core control during STOP0 - core_0 is always disabled during STOP0." %define _DESC1140_ \ desc += "Core control during HALT0 - core_0 is always disabled during HALT0." %define _DESC1141_ \ desc += "Core control during RUN3" %define _DESC1142_ \ desc += "Core control during RUN2" %define _DESC1143_ \ desc += "Core control during RUN1" %define _DESC1144_ \ desc += "Core control during RUN0" %define _DESC1145_ \ desc += "Core control during DRUN" %define _DESC1146_ \ desc += "Core control during SAFE" %define _DESC1147_ \ desc += "Core control during TEST" %define _DESC1148_ \ desc += "Core control during RESET - core_0 is always disabled during RESET." %define _DESC1149_ \ desc += "core_0 Address Register. This registers gives the boot address for core_0 and a\n"\ desc += "bit for controlling whether core_0 is to be reset on the next mode change that\n"\ desc += "has core_0 configured to be running in the target mode.\n\n"\ desc += "This register can be written only as a word and cannot be written after a mode\n"\ desc += "change request has been made until the mode transition has completed (i.e.,\n"\ desc += "while the S_MTRANS bit of the ME_GS register = '1'). A write access to this\n"\ desc += "register during this time will result in the ICONF_CC flag in the ME_IS\n"\ desc += "register being asserted.\n\n"\ desc += "The reset value of the ADDR field of the ME_CADDR0 is determined by the chip\n"\ desc += "configuration and boot mode." %define _DESC1150_ \ desc += "Core Address - This field is used by core_0 as the boot address (32-bit word\n"\ desc += "aligned) when core_0 next exits reset." %define _DESC1151_ \ desc += "Reset on Mode Change - core_0 will be reset on the next mode change that has\n"\ desc += "core_0 configured to be running in the target mode." %define _DESC1152_ \ desc += "Power Domain Status Register. This register reflects the power status of all\n"\ desc += "available power domains." %define _DESC1153_ \ desc += "Power status for power domain 0" %define _DESC1154_ \ desc += "'Destructive' Event Status Register. [BLG_RGM_0006][Covers: ADD13.012][Covers:\n"\ desc += "ADD23.031]This register contains the status of the 'destructive' reset sources,\n"\ desc += "including those configured to not generate a reset sequence. Supervisor and\n"\ desc += "test modes allow for read/write access, whereas read access only is allowed in\n"\ desc += "user mode. Register bits are cleared on write '1'. This register is reset only\n"\ desc += "on power-on.[end]\n\n"\ desc += "" %define _DESC1155_ \ desc += "Flag for voltage out of range 'destructive' reset" %define _DESC1156_ \ desc += "Flag for temperature sensor 'destructive' reset" %define _DESC1157_ \ desc += "Flag for SSCM 'destructive' reset request" %define _DESC1158_ \ desc += "Flag for JTAG 'destructive' reset request" %define _DESC1159_ \ desc += "Flag for 'functional' reset escalation" %define _DESC1160_ \ desc += "Flag for software 'destructive' reset" %define _DESC1161_ \ desc += "Flag for external power-on reset" %define _DESC1162_ \ desc += "Flag for Power-On reset" %define _DESC1163_ \ desc += "'Destructive' Event Reset Disable Register. This register provides dedicated\n"\ desc += "bits to disable particular 'destructive' reset sources. When a 'destructive'\n"\ desc += "reset source is disabled, the associated 'destructive' event will trigger\n"\ desc += "either a SAFE mode request or an interrupt request (see DEAR ). Supervisor and\n"\ desc += "test modes allow for read/write access, whereas read access only is allowed in\n"\ desc += "user mode. Each byte can be written only once after a 'destructive' or power-on\n"\ desc += "reset.\n\n"\ desc += "This register is reset only on power-on." %define _DESC1164_ \ desc += "Disable temperature sensor 'destructive' reset" %define _DESC1165_ \ desc += "Disable external power-on reset" %define _DESC1166_ \ desc += "'Destructive' Event Alternate Request Register. This register defines an\n"\ desc += "alternate request to be generated when a reset on a 'destructive' event has\n"\ desc += "been disabled. The alternate request can be either a SAFE mode request to MC_ME\n"\ desc += "or an interrupt request to the system. Supervisor and test modes allow for\n"\ desc += "read/write access, whereas read access only is allowed in user mode.\n\n"\ desc += "This register is reset only on power-on." %define _DESC1167_ \ desc += "Alternate Request for temperature sensor 'destructive' reset" %define _DESC1168_ \ desc += "Alternate Request for external power-on reset" %define _DESC1169_ \ desc += "'Destructive' Bidirectional Reset Enable Register. [SCG54.0201][Covers:\n"\ desc += "ADD13.023]This register enables the generation of an external reset on\n"\ desc += "'destructive' reset[end]. Supervisor and test modes allow for read/write\n"\ desc += "access, whereas read access only is allowed in user mode.\n\n"\ desc += "This register is reset only on power-on." %define _DESC1170_ \ desc += "Bidirectional Reset Enable for voltage out of range 'destructive' reset" %define _DESC1171_ \ desc += "Bidirectional Reset Enable for temperature sensor 'destructive' reset" %define _DESC1172_ \ desc += "Bidirectional Reset Enable for SSCM 'destructive' reset request" %define _DESC1173_ \ desc += "Bidirectional Reset Enable for JTAG 'destructive' reset request" %define _DESC1174_ \ desc += "Bidirectional Reset Enable for 'functional' reset escalation" %define _DESC1175_ \ desc += "Bidirectional Reset Enable for software 'destructive' reset" %define _DESC1176_ \ desc += "Bidirectional Reset Enable for external power-on reset" %define _DESC1177_ \ desc += "Bidirectional Reset Enable for Power-On reset" %define _DESC1178_ \ desc += "'Functional' Event Status Register. [BLG_RGM_0007][Covers: ADD13.012][Covers:\n"\ desc += "ADD23.031]This register contains the status of the 'functional' reset sources,\n"\ desc += "including those configured to not generate a reset sequence. Supervisor and\n"\ desc += "test modes allow for read/write access, whereas read access only is allowed in\n"\ desc += "user mode. Register bits are cleared on write '1' if the triggering event has\n"\ desc += "already been cleared at the source. This register is reset only on\n"\ desc += "power-on.[end]\n\n"\ desc += "If a 'functional' reset source is configured to generate a SAFE mode request or\n"\ desc += "an interrupt request, software needs to clear the event in the source module at\n"\ desc += "least three system clock cycles before it clears the associated RGM_FES status\n"\ desc += "bit in order to avoid multiple SAFE mode requests or interrupts for the same\n"\ desc += "event. In order to avoid having to count cycles, it is good practice for\n"\ desc += "software to check whether the RGM_FES has been properly cleared, and if not,\n"\ desc += "clear it again." %define _DESC1179_ \ desc += "Flag for Flash fatal error reset" %define _DESC1180_ \ desc += "Flag for voltage out of range 'functional' reset" %define _DESC1181_ \ desc += "Flag for temperature sensor 'functional' reset" %define _DESC1182_ \ desc += "Flag for PLL0 lock failure" %define _DESC1183_ \ desc += "Flag for system frequency out of range" %define _DESC1184_ \ desc += "Flag for oscillator failure" %define _DESC1185_ \ desc += "Flag for core debug reset" %define _DESC1186_ \ desc += "Flag for JTAG 'functional' reset request" %define _DESC1187_ \ desc += "Flag for Core Watchdog reset" %define _DESC1188_ \ desc += "Flag for System Watchdog reset" %define _DESC1189_ \ desc += "Flag for software 'functional' reset" %define _DESC1190_ \ desc += "Flag for ESR1 External Reset" %define _DESC1191_ \ desc += "Flag for ESR0 External Reset" %define _DESC1192_ \ desc += "'Functional' Event Reset Disable Register. This register provides dedicated\n"\ desc += "bits to disable 'functional' reset sources.When a 'functional' reset source is\n"\ desc += "disabled, the associated 'functional' event triggers either a SAFE mode request\n"\ desc += "or an interrupt request (see FEAR ). Supervisor and test modes allow for\n"\ desc += "read/write access, whereas read access only is allowed in user mode. Each byte\n"\ desc += "can be written only once after power-on reset.\n\n"\ desc += "This register is reset only on power-on and any 'destructive' reset.\n\n"\ desc += "It is important to clear the RGM_FES register before setting any of the bits in\n"\ desc += "the RGM_FERD register to '1'. Otherwise a redundant SAFE mode request or\n"\ desc += "interrupt request may occur." %define _DESC1193_ \ desc += "Disable Flash fatal error reset" %define _DESC1194_ \ desc += "Disable voltage out of range 'functional' reset" %define _DESC1195_ \ desc += "Disable temperature sensor 'functional' reset" %define _DESC1196_ \ desc += "Disable PLL0 lock failure" %define _DESC1197_ \ desc += "Disable system frequency out of range" %define _DESC1198_ \ desc += "Disable oscillator failure" %define _DESC1199_ \ desc += "Disable core debug reset" %define _DESC1200_ \ desc += "Disable System Watchdog reset" %define _DESC1201_ \ desc += "Disable Core Watchdog reset" %define _DESC1202_ \ desc += "Disable ESR1 External Reset" %define _DESC1203_ \ desc += "'Functional' Event Alternate Request Register. This register defines an\n"\ desc += "alternate request to be generated when a reset on a 'functional' event has been\n"\ desc += "disabled. The alternate request can be either a SAFE mode request to MC_ME or\n"\ desc += "an interrupt request to the system. Supervisor and test modes allow for\n"\ desc += "read/write access, whereas read access only is allowed in user mode.\n\n"\ desc += "This register is reset only on power-on and any 'destructive' reset." %define _DESC1204_ \ desc += "Alternate Request for Flash fatal error reset" %define _DESC1205_ \ desc += "Alternate Request for voltage out of range 'functional' reset" %define _DESC1206_ \ desc += "Alternate Request for temperature sensor 'functional' reset" %define _DESC1207_ \ desc += "Alternate Request for PLL0 lock failure" %define _DESC1208_ \ desc += "Alternate Request for system frequency out of range" %define _DESC1209_ \ desc += "Alternate Request for oscillator failure" %define _DESC1210_ \ desc += "Alternate Request for core debug reset" %define _DESC1211_ \ desc += "Alternate Request for Core Watchdog reset" %define _DESC1212_ \ desc += "Alternate Request for System Watchdog reset" %define _DESC1213_ \ desc += "Alternate Request for ESR1 External Reset" %define _DESC1214_ \ desc += "'Functional' Bidirectional Reset Enable Register. This register enables the\n"\ desc += "generation of an external reset on 'functional' reset. It can be accessed in\n"\ desc += "read/write in either supervisor mode or test mode. It can be accessed in read\n"\ desc += "in user mode.\n\n"\ desc += "This register is reset only on power-on and any 'destructive' reset." %define _DESC1215_ \ desc += "Bidirectional reset enable for Flash fatal error reset" %define _DESC1216_ \ desc += "Bidirectional Reset Enable for voltage out of range 'functional' reset" %define _DESC1217_ \ desc += "Bidirectional Reset Enable for temperature sensor 'functional' reset" %define _DESC1218_ \ desc += "Bidirectional Reset Enable for PLL0 'functional' reset" %define _DESC1219_ \ desc += "Bidirectional reset enable for system frequency out of range" %define _DESC1220_ \ desc += "Bidirectional reset enable for oscillator failure" %define _DESC1221_ \ desc += "Bidirectional reset enable for core debug reset" %define _DESC1222_ \ desc += "Bidirectional reset enable for JTAG 'functional' reset request" %define _DESC1223_ \ desc += "Bidirectional reset enable for Core Watchdog reset" %define _DESC1224_ \ desc += "Bidirectional reset enable for System Watchdog reset" %define _DESC1225_ \ desc += "Bidirectional Reset Enable for software 'functional' reset" %define _DESC1226_ \ desc += "Bidirectional Reset Enable for ESR1 External Reset" %define _DESC1227_ \ desc += "Bidirectional Reset Enable for ESR0 External Reset" %define _DESC1228_ \ desc += "'Functional' Event Short Sequence Register. This register defines which reset\n"\ desc += "sequence is followed when a 'functional' reset sequence is triggered. The\n"\ desc += "'functional' reset sequence can either start from PHASE1 or from PHASE3,\n"\ desc += "skipping PHASE1 and PHASE2. This is useful when a fast reset sequence is\n"\ desc += "desired, skipping flash reset, for example.\n\n"\ desc += "Supervisor and test modes allow for read/write access, whereas read access only\n"\ desc += "is allowed in user mode. This register is reset only on power-on and any\n"\ desc += "'destructive' reset." %define _DESC1229_ \ desc += "Short Sequence for Flash fatal error reset" %define _DESC1230_ \ desc += "Short Sequence for voltage out of range 'functional' reset" %define _DESC1231_ \ desc += "Short Sequence for temperature sensor 'functional' reset" %define _DESC1232_ \ desc += "Short Sequence for PLL0 lock failure" %define _DESC1233_ \ desc += "Short Sequence for system frequency out of range" %define _DESC1234_ \ desc += "Short Sequence for oscillator failure" %define _DESC1235_ \ desc += "Short Sequence for core debug reset" %define _DESC1236_ \ desc += "Short Sequence for JTAG 'functional' reset" %define _DESC1237_ \ desc += "Short Sequence for Core Watchdog reset" %define _DESC1238_ \ desc += "Short Sequence for System Watchdog reset" %define _DESC1239_ \ desc += "Short Sequence for software 'functional' reset" %define _DESC1240_ \ desc += "Short Sequence for ESR1 External Reset" %define _DESC1241_ \ desc += "Short Sequence for ESR0 External Reset" %define _DESC1242_ \ desc += "'Functional' Reset Threshold Register. This register sets the threshold for\n"\ desc += "'functional' reset escalation to a 'destructive' reset. Supervisor and test\n"\ desc += "modes allow for read/write access, whereas read access only is allowed in user\n"\ desc += "mode.\n\n"\ desc += "Writing a non-zero value to the FRET field enables the 'functional' reset\n"\ desc += "escalation function. Writing any value to this register resets the 'functional'\n"\ desc += "reset counter. See #Rdf10221 for details on the 'functional' reset escalation\n"\ desc += "function.\n\n"\ desc += "This register is reset only on power-on and any 'destructive' reset." %define _DESC1243_ \ desc += "'Functional' Reset Escalation Threshold\n\n"\ desc += "If the value of this field is 0, the 'functional' reset escalation function is\n"\ desc += "disabled. Any other value is the number of 'functional' resets which cause a\n"\ desc += "'destructive' reset if the RGM_FRET register isn't written to beforehand." %define _DESC1244_ \ desc += "'Destructive' Reset Threshold Register. This register sets the threshold for\n"\ desc += "'destructive' reset escalation, keeping the chip in the reset state until the\n"\ desc += "next power-on reset triggers a new reset sequence. Supervisor and test modes\n"\ desc += "allow for read/write access, whereas read access only is allowed in user\n"\ desc += "mode.\n\n"\ desc += "Writing a non-zero value to the DRET field enables the 'destructive'\n"\ desc += "resesoftwaret escalation function. Writing any value to this register resets\n"\ desc += "the 'destructive' reset counter. See #Rdf49500 for details on the\n"\ desc += "'destructive' reset escalation function.\n\n"\ desc += "This register is reset only on power-on." %define _DESC1245_ \ desc += "'Destructive' Reset Escalation Threshold\n\n"\ desc += "If the value of this field is 0, the 'destructive' reset escalation function is\n"\ desc += "disabled. Any other value is the number of 'destructive' resets which keep the\n"\ desc += "chip in the reset state until the next power-on reset triggers a new reset\n"\ desc += "sequence if the RGM_DRET register isn't written to beforehand." %define _DESC1246_ \ desc += "External Reset Output Assertion Control Register. This register controls the\n"\ desc += "assertion of the ESR0 pin after the reset sequence has completed. Supervisor\n"\ desc += "and test modes allow for read/write access, whereas read access only is allowed\n"\ desc += "in user mode. The register bit is cleared on write '1'.\n\n"\ desc += "Clearing the EROEC bit causes the MC_RGM to stop asserting the ESR0 pin within\n"\ desc += "two 16 MHz internal RC oscillator clock cycles. The ESR0 pin cannot be asserted\n"\ desc += "by writing to this register.\n\n"\ desc += "This register also provides the current value sampled on ESR0 via the ERIS bit.\n"\ desc += "This is useful for software to poll if, for example, ESR0 is used in the system\n"\ desc += "to synchronize the application software with an external event.\n\n"\ desc += "This register is reset only on power-on." %define _DESC1247_ \ desc += "External Reset Intput Status" %define _DESC1248_ \ desc += "External Reset Output Assertion Control" %define _DESC1249_ \ desc += "Peripheral Reset 0 Register. [BLG_RGM_0008][Covers: ADD13.014]This register\n"\ desc += "provides individual resets for various peripherals[end]. Supervisor and test\n"\ desc += "modes allow for read/write access, whereas read access only is allowed in user\n"\ desc += "mode. Please refer to #Rdf46407 for details.\n\n"\ desc += "Use the RGM_PRST0 register with care. See #Rdf88402 for the proper sequence to\n"\ desc += "prevent unexpected chip behavior." %define _DESC1250_ \ desc += "Peripheral reset - Writing a '1' to this bit will reset the corresponding\n"\ desc += "peripheral. Writing a '0' to this bit will release the reset to the\n"\ desc += "corresponding peripheral if the bit's current value is '1', otherwise it will\n"\ desc += "have no effect." %define _DESC1251_ \ desc += "Peripheral Reset 1 Register. This register provides individual resets for\n"\ desc += "various peripherals. Supervisor and test modes allow for read/write access,\n"\ desc += "whereas read access only is allowed in user mode. Please refer to #Rdf46407 for\n"\ desc += "details.\n\n"\ desc += "Use the RGM_PRST1 register with care. See #Rdf88402 for the proper sequence to\n"\ desc += "prevent unexpected chip behavior." %define _DESC1252_ \ desc += "Peripheral Reset 2 Register. This register provides individual resets for\n"\ desc += "various peripherals. Supervisor and test modes allow for read/write access,\n"\ desc += "whereas read access only is allowed in user mode. Please refer to #Rdf46407 for\n"\ desc += "details.\n\n"\ desc += "Use the RGM_PRST2 register with care. See #Rdf88402 for the proper sequence to\n"\ desc += "prevent unexpected chip behavior." %define _DESC1253_ \ desc += "Peripheral Reset 3 Register. This register provides individual resets for\n"\ desc += "various peripherals. Supervisor and test modes allow for read/write access,\n"\ desc += "whereas read access only is allowed in user mode. Please refer to #Rdf46407 for\n"\ desc += "details.\n\n"\ desc += "Use the RGM_PRST3 register with care. See #Rdf88402 for the proper sequence to\n"\ desc += "prevent unexpected chip behavior." %define _DESC1254_ \ desc += "Peripheral Reset 4 Register. This register provides individual resets for\n"\ desc += "various peripherals. Supervisor and test modes allow for read/write access,\n"\ desc += "whereas read access only is allowed in user mode. Please refer to #Rdf46407 for\n"\ desc += "details.\n\n"\ desc += "Use the RGM_PRST4 register with care. See #Rdf88402 for the proper sequence to\n"\ desc += "prevent unexpected chip behavior." %define _DESC1255_ \ desc += "Module Configuration Register. The Module Configuration Register is used to\n"\ desc += "enable and monitor all the Modify operations of the Flash Memory module.\n\n"\ desc += "A number of MCR bits are protected against Write when another bit, or set of\n"\ desc += "bits, is in a specific state. These Write locks are covered on a bit-by-bit\n"\ desc += "basis in the preceding description, but those locks do not consider the effects\n"\ desc += "of trying to write two or more bits simultaneously.\n\n"\ desc += "The Flash Memory module does not allow the user to write bits simultaneously\n"\ desc += "(which puts the device into an illegal state). This is implemented through a\n"\ desc += "priority mechanism among the bits. The bit changing priorities are detailed in\n"\ desc += "the following table.\n\n"\ desc += "[MCR Bits Set/Clear Priority Levels]:\n"\ desc += " Priority Level MCR Bits\n"\ desc += " -------------- ----------\n"\ desc += " 1 ERS\n"\ desc += " 2 PGM\n"\ desc += " 3 EHV\n"\ desc += " 4 ESUS, PSUS\n"\ desc += "If the user attempts to write two or more MCR bits simultaneously then only the\n"\ desc += "bit with the lowest priority level is written." %define _DESC1256_ \ desc += "ECC event Error (Read/Clear)\n\n"\ desc += "EER provides information on previous reads. If a ECC Double Error detection\n"\ desc += "occurred, the EER bit is set to 1. This bit must then be cleared, or a reset\n"\ desc += "must occur before this bit returns to a 0 state. This bit may not be set to 1\n"\ desc += "by the user. In the event of a ECC Single Error detection and correction, this\n"\ desc += "bit is not set. If EER is not set, or remains 0, this indicates that all\n"\ desc += "previous reads (from the last reset, or clearing of EER) were correct. Since\n"\ desc += "this bit is an error flag, it must be cleared to 0 by writing 1 to the register\n"\ desc += "location. A Write of 0 has no effect." %define _DESC1257_ \ desc += "Read-while-Write event Error (Read/Clear)\n\n"\ desc += "RWE provides information on previous reads when any Modify operation is on\n"\ desc += "going. If a RWW Error occurs, the RWE bit is set to 1. Read-While-Write Error\n"\ desc += "means that a Read access to the Flash Array partition has occurred while the\n"\ desc += "FPEC was performing a Program or Erase operation or an Array Integrity Check on\n"\ desc += "the same partition. This bit must then be cleared, or a reset must occur before\n"\ desc += "this bit returns to a 0 state. This bit may not be set to 1 by the user. If RWE\n"\ desc += "is not set, or remains 0, this indicates that all previous RWW reads (from the\n"\ desc += "last reset, or clearing of RWE) were correct. Since this bit is an error flag,\n"\ desc += "it must be cleared to 0 by writing 1 to the register location. A Write of 0 has\n"\ desc += "no effect." %define _DESC1258_ \ desc += "Single Bit Correction (Read/Clear)\n\n"\ desc += "SBC provides information on previous reads. If a ECC Single Error detection and\n"\ desc += "correction occurred, the SBC bit is set to 1. This bit must then be cleared, or\n"\ desc += "a reset must occur before this bit returns to a 0 state. This bit may not be\n"\ desc += "set to 1 by the user. In the event of a ECC Double Error detection, this bit is\n"\ desc += "not set. If SBC is not set, or remains 0, this indicates that all previous\n"\ desc += "reads (from the last reset, or clearing of SBC) were not corrected through ECC.\n"\ desc += "Since this bit is an error flag, it must be cleared to 0 by writing 1 to the\n"\ desc += "register location. A Write of 0 has no effect. The function of this bit is SoC\n"\ desc += "dependent and it can be configured to be disabled (through UT0.SBCE)." %define _DESC1259_ \ desc += "Program/Erase Access Space (read only)\n\n"\ desc += "PEAS is used to indicate which space is valid for Program and Erase operations:\n"\ desc += "main array space or UTEST section within TestFlash block. PEAS=0 indicates that\n"\ desc += "the main address space is active for all Flash Memory module Program and Erase\n"\ desc += "operations. PEAS=1 indicates that the UTEST section address space is active for\n"\ desc += "program. Erase is not possible for UTEST. The value in PEAS is captured and\n"\ desc += "held with the first Interlock Write done for Modify operations. The value of\n"\ desc += "PEAS is retained between sampling events (i.e. subsequent first interlock\n"\ desc += "writes). The value in PEAS is changed during erase-suspended program (when\n"\ desc += "program is in UTEST) and reverts back to its original state (related to erase\n"\ desc += "suspended operation) once the erase-suspended program is completed (at MCR.PGM\n"\ desc += "1->0 transition). PEAS is read only." %define _DESC1260_ \ desc += "Modify operation DONE (read only)\n\n"\ desc += "DONE indicates if the Flash Memory module is performing a high voltage\n"\ desc += "operation. DONE is set to 1 on termination of the Flash Memory module reset.\n"\ desc += "DONE is cleared to 0 just after a 0 to 1 transition of EHV, which initiates a\n"\ desc += "high voltage operation, or after resuming a suspended operation. DONE is set to\n"\ desc += "1 at the end of program and Erase High Voltage sequences. DONE is set to 1\n"\ desc += "(within tPABT or tEABT, equal to P/E Abort Latency) after a 1 to 0 transition\n"\ desc += "of EHV, which aborts a high voltage Program/Erase operation. DONE is set to 1\n"\ desc += "(within tESUS/t PSUS time equals to Erase/Program Suspend Latency) after a 0 to\n"\ desc += "1 transition of ESUS/PSUS, which suspends an Erase/Program operation." %define _DESC1261_ \ desc += "Program/Erase Good (read only)\n\n"\ desc += "The PEG bit indicates the completion status of the last flash Program or Erase\n"\ desc += "sequence for which high voltage operations were initiated. The value of PEG is\n"\ desc += "updated automatically during the Program and Erase high voltage operations.\n\n"\ desc += "In case of page program or quad-page program, some doubleword addresses have\n"\ desc += "not been interlocked (already programmed on intended to remain virgin). In this\n"\ desc += "case PEG is evaluated on the completion status only of the interlocked\n"\ desc += "doubleword.\n\n"\ desc += "Aborting a Program/Erase high voltage operation causes PEG to be cleared to 0,\n"\ desc += "indicating the sequence failed. PEG is set to 1 when the Flash Memory module is\n"\ desc += "reset, unless a Flash Initialization error has been detected. The value of PEG\n"\ desc += "is valid only when PGM=1 and/or ERS=1 and after DONE transitions from 0 to 1\n"\ desc += "due to an Abort or the completion of a Program/Erase operation. PEG is valid\n"\ desc += "until PGM/ERS makes a 1 to 0 transition or EHV makes a 0 to 1 transition. The\n"\ desc += "value in PEG is not valid after a 0 to 1 transition of DONE caused by ESUS/PSUS\n"\ desc += "being set to logic 1.\n\n"\ desc += "If Program or Erase are attempted on blocks that are locked, the response is\n"\ desc += "PEG=1, indicating that the operation was successful, and the content of the\n"\ desc += "block were properly protected from the Program or Erase operation. blocks can\n"\ desc += "be locked through LOCK0/1/2 registers OR with f90_plock0/1/2 sideband signals.\n"\ desc += "If a Program operation tries to program at '1' bits that are at '0', the\n"\ desc += "program operation is correctly executed on the new bits to be programmed at\n"\ desc += "'0', but PEG is cleared, indicating that the requested operation has failed.\n\n"\ desc += "If Programming during an Erase-Suspend a location that was under suspended\n"\ desc += "erase, program is not executed and PEG is set to 0.\n\n"\ desc += "[BLG_MP_0060] [end]\n\n"\ desc += "PEG behavior with blocks marked as OPP (though f90_otpen0/1/2 sidebands signal)\n"\ desc += "is the following: PEG=0 if the location to be programmed is not virgin, and\n"\ desc += "thus would not be over programmed. In Array Integrity Check or Margin Read PEG\n"\ desc += "is not altered when the operation is completed, regardless the occurrence of\n"\ desc += "any error, abort, break point or suspend. The presence of errors can be\n"\ desc += "detected only comparing checksum value stored in UMIRS0-9 and checking MCR\n"\ desc += "flags." %define _DESC1262_ \ desc += "Program/Erase Complete Interrupt Enable (Read/Write).\n\n"\ desc += "PECIE provides a mechanism to trigger an interrupt request upon the assertion\n"\ desc += "of the DONE flag." %define _DESC1263_ \ desc += "Factory Erase (Read/Write).\n\n"\ desc += "FERS is used for Erase and Program operations to enable a faster operation.\n"\ desc += "Factory Erase must be done following 'Initial Factory Conditions All Temps'\n"\ desc += "with respect to voltage conditions, Write/Erase cycling, and temperature which\n"\ desc += "can be from -40 C to 150 C. After setting the ERS or PGM bit, but prior to\n"\ desc += "setting EHV, FERS may be set to enable a Factory Erase or Program. FERS can be\n"\ desc += "written only when ERS or PGM are high, but EHV is still low. FERS can be\n"\ desc += "cleared only when EHV is low and DONE is high. Factory Erase may also be\n"\ desc += "disabled by writing a location in the UTEST Nonvolatile Memory space. Address\n"\ desc += "0x800020 in the UTEST Nonvolatile Memory space is checked at reset, and if\n"\ desc += "programmed with data that contains at least one zero, a Factory Erase is not\n"\ desc += "allowed, and FERS is locked. Writes attempted that violate the above cases\n"\ desc += "result in FERS remaining cleared. FERS is cleared on reset.\n\n"\ desc += "Factory erase feature cannot be used in conjunction with Read operation:\n"\ desc += "Factory Erase is not supported for Read-While-Write.\n\n"\ desc += "FERS is cleared on reset." %define _DESC1264_ \ desc += "Program (Read/Write)\n\n"\ desc += "PGM is used to setup the Flash Memory module for a Program operation. A 0 to 1\n"\ desc += "transition of PGM initiates a program sequence. A 1 to 0 transition of PGM ends\n"\ desc += "the program sequence. PGM can be set only under the following conditions: *\n"\ desc += "User Mode Read (ERS is low and UT0.AIE is low); * Erase Suspend (ERS and ESUS\n"\ desc += "high) with EHV low. PGM can be cleared by the user only when PSUS and EHV are\n"\ desc += "low and DONE is high. PGM is cleared on reset.\n\n"\ desc += "In an erase-suspended program, programming flash memory locations in blocks\n"\ desc += "which were being operated on in the Erase is forbidden. Command is not accepted\n"\ desc += "and PEG is set to 0" %define _DESC1265_ \ desc += "Program SUSpend (Read/Write) PSUS is used to indicate that the Flash Memory\n"\ desc += "module is in Program Suspend or in the process of entering a Suspend state. The\n"\ desc += "Flash Memory module is in Program Suspend when PSUS=1 and DONE=1. PSUS can be\n"\ desc += "set high only when PGM and EHV are high. A 0 to 1 transition of PSUS starts the\n"\ desc += "sequence which sets DONE and places the flash in Program Suspend. The Flash\n"\ desc += "Memory module enters Suspend within tPSUS of this transition. PSUS can be\n"\ desc += "cleared only when DONE and EHV are high. A 1 to 0 transition of PSUS with EHV=1\n"\ desc += "starts the sequence which clears DONE and returns the module to Program. The\n"\ desc += "Flash Memory module cannot exit Program Suspend and clear DONE while EHV is\n"\ desc += "low. In case of Program Suspend while in Erase Suspend (PSUS=1, ESUS=1), PSUS\n"\ desc += "has to be cleared first in order to resume currently higher level suspended\n"\ desc += "operation that is program. PSUS is cleared on reset." %define _DESC1266_ \ desc += "ERaSe (Read/Write)\n\n"\ desc += "ERS is used to setup the Flash Memory module for an Erase operation. A 0 to 1\n"\ desc += "transition of ERS initiates an Erase sequence. A 1 to 0 transition of ERS ends\n"\ desc += "the Erase sequence. ERS can be set only under User Mode Read (PGM is low and\n"\ desc += "UT0.AIE is low). ERS can be cleared by the user only when ESUS and EHV are low\n"\ desc += "and DONE is high. ERS is cleared on reset." %define _DESC1267_ \ desc += "Erase SUSpend (Read/Write)\n\n"\ desc += "ESUS is used to indicate that the Flash Memory module is in Erase Suspend or in\n"\ desc += "the process of entering a Suspend state. The Flash Memory module is in Erase\n"\ desc += "Suspend when ESUS=1 and DONE=1. ESUS can be set high only when ERS and EHV are\n"\ desc += "high and PGM is low. A 0 to 1 transition of ESUS starts the sequence which sets\n"\ desc += "DONE and places the flash in Erase Suspend. The Flash Memory module enters\n"\ desc += "Suspend within tESUS of this transition. ESUS can be cleared only when DONE and\n"\ desc += "EHV are high and PGM is low. A 1 to 0 transition of ESUS with EHV=1 starts the\n"\ desc += "sequence which clears DONE and returns the module to Erase. The Flash Memory\n"\ desc += "module cannot exit Erase Suspend and clear DONE while EHV is low. In case of\n"\ desc += "Program Suspend while in Erase Suspend (PSUS=1, ESUS=1), ESUS cannot be cleared\n"\ desc += "first. ESUS is cleared on reset." %define _DESC1268_ \ desc += "Enable High Voltage (Read/Write)\n\n"\ desc += "The EHV bit enables the Flash Memory module for a high voltage Program/Erase\n"\ desc += "operation. EHV is cleared on reset. EHV must be set after an Interlock Write to\n"\ desc += "start a Program/Erase sequence. EHV may be set under one of the following\n"\ desc += "conditions:\n\n"\ desc += "Erase (ERS=1, ESUS=0, UT0.AIE=0)\n\n"\ desc += "Program (ERS=0, ESUS=0, PGM=1, UT0.AIE=0)\n\n"\ desc += "Erase-suspended program (ERS = 1, ESUS = 1, PGM = 1, PSUS = 0, UT0.AIE=0).\n\n"\ desc += "If a program operation is to be initiated while an Erase is suspended, EHV must\n"\ desc += "be cleared while in Erase-Suspend (once DONE=1) before setting PGM.\n\n"\ desc += "In normal operation, a 1 to 0 transition of EHV with DONE high, PSUS and ESUS\n"\ desc += "low terminates the current Program/Erase high voltage operation. In an\n"\ desc += "erase-suspended program operation, a 1 to 0 transition of EHV with DONE, ESUS,\n"\ desc += "PGM and ERS high, while PSUS low terminates the program that is the current\n"\ desc += "high voltage operation. When an operation is aborted, there is a 1 to 0\n"\ desc += "transition of EHV with DONE low and the eventual Suspend bit for the current\n"\ desc += "program/erase operation low. An Abort causes the value of PEG to be cleared,\n"\ desc += "indicating a failing Program/Erase; address locations being operated on by the\n"\ desc += "aborted operation contain indeterminate data after an Abort. EHV cannot be\n"\ desc += "written to 1 after an Abort request (EHV being cleared) till the Abort sequence\n"\ desc += "is not completed (DONE transition to 1). Once the Abort sequence is completed\n"\ desc += "(DONE=1) a new operation, of the kind of the one aborted, can start, provided\n"\ desc += "that a new interlock is given and then EHV is set to again. A suspended\n"\ desc += "operation cannot be aborted. Aborting a high voltage operation leaves the Flash\n"\ desc += "Memory module addresses in an indeterminate data state. This may be recovered\n"\ desc += "by executing an Erase on the affected blocks. EHV may be written during\n"\ desc += "Suspend. EHV must be high to exit Suspend, resuming previously suspended\n"\ desc += "command. EHV cannot not be written during transition that brings into Suspend\n"\ desc += "state, that is after Suspend bit (ESUS or PSUS) is set high, till DONE\n"\ desc += "transitions to 1. EHV may not be written after ESUS is set and before DONE\n"\ desc += "transitions high. EHV may not be cleared after ESUS is cleared and before DONE\n"\ desc += "transitions low." %define _DESC1269_ \ desc += "Extended Module Configuration Register. The Extended Module Configuration\n"\ desc += "Register value is based on the size, blocks and address space configuration of\n"\ desc += "the Flash Memory module." %define _DESC1270_ \ desc += "Number of 8 KB blocks in high space. (read only)\n\n"\ desc += "n8K is read only.\n\n"\ desc += "00 Zero 8 KB blocks.\n\n"\ desc += "01 Two 8 KB blocks.\n\n"\ desc += "10 Four 8 KB blocks.\n\n"\ desc += "11 Six 8 KB blocks." %define _DESC1271_ \ desc += "Number of 256K blocks. (read only)\n\n"\ desc += "The value of the n256K field is dependent upon the size of the embedded flash\n"\ desc += "memory. n256K is read only.\n\n"\ desc += "n256K value represents in the number of blocks effectively available.\n\n"\ desc += "00000: Zero 256K blocks.\n\n"\ desc += "00001: One 256K block.\n\n"\ desc += "00010: Two 256K blocks.\n\n"\ desc += "00011: Three 256K blocks.\n\n"\ desc += "00100: Four 256K blocks.\n\n"\ desc += "00101: Five 256K blocks.\n\n"\ desc += "00110: Six 256K blocks.\n\n"\ desc += "00111: Seven 256K blocks\n\n"\ desc += "01000: Eight 256K blocks.\n\n"\ desc += "01001: Nine 256K blocks.\n\n"\ desc += "01010: Ten 256K blocks.\n\n"\ desc += "...\n\n"\ desc += "11100: Twenty-Eight 256K blocks (7.0 MB total).\n\n"\ desc += "11101: Twenty-Nine 256K blocks (7.25 MB total).\n\n"\ desc += "11110: Thirty 256K blocks (7.5 MB total).\n\n"\ desc += "11111: Thirty-one 256K blocks (7.75 MB total)." %define _DESC1272_ \ desc += "Number of 64 KB blocks in high space. (read only)\n\n"\ desc += "n64Kh is read only." %define _DESC1273_ \ desc += "Number of 32 KB blocks in high space. (read only)\n\n"\ desc += "n32K is read only." %define _DESC1274_ \ desc += "Number of 16 KB blocks in high space. (read only)\n\n"\ desc += "n16K is read only." %define _DESC1275_ \ desc += "Number of 64 KB blocks in mid space. (read only)\n\n"\ desc += "n64Kh is read only." %define _DESC1276_ \ desc += "Number of 32 KB blocks in mid space. (read only)\n\n"\ desc += "n32K is read only." %define _DESC1277_ \ desc += "Number of 16 KB blocks in mid space. (read only)\n\n"\ desc += "n16K is read only." %define _DESC1278_ \ desc += "Number of 64 KB blocks in low space. (read only)\n\n"\ desc += "n64Kh is read only." %define _DESC1279_ \ desc += "Number of 32 KB blocks in low space. (read only)\n\n"\ desc += "n32K is read only.\n\n"\ desc += "00 Zero 32 KB blocks." %define _DESC1280_ \ desc += "Number of 16 KB blocks in low space. (read only)\n\n"\ desc += "n16K is read only." %define _DESC1281_ \ desc += "Low/Mid address space block Locking 0 register. The LOCK0 Low/Mid Address Space\n"\ desc += "Block Locking register provides a means of protecting blocks from being\n"\ desc += "modified. These bits determine if the block is locked from Program or Erase.\n"\ desc += "LLK and MLK bits corresponding to non existent blocks on a given cut are read\n"\ desc += "as 1.\n\n"\ desc += "To determine the effective status of the Low/Mid Address Space, combine (Or)\n"\ desc += "LOCK0 with sidebands:\n\n"\ desc += "f90_plock0 - in order to evaluate protection against programming. f90_elock0 -\n"\ desc += "in order to evaluate protection against erase. The effect of\n"\ desc += "programming/erasing a block protected with LOCK0 is that no modification occurs\n"\ desc += "and PEG is set to 1." %define _DESC1282_ \ desc += "UTEST block LocK (Read/Write)\n\n"\ desc += "This bit is used to lock the UTEST from Program (Erase is any case forbidden\n"\ desc += "being UTEST a part of the TestFlash block). A value of 1 in the TSLOCK register\n"\ desc += "means that the UTEST is locked for Program. A value of 0 in the TSLOCK register\n"\ desc += "means that the UTEST is available to receive Program pulses. The TSLOCK\n"\ desc += "register is not writable once an Interlock Write is completed until MCR.DONE is\n"\ desc += "set at the completion of the requested operation. Likewise, the TSLOCK register\n"\ desc += "is not writable if a high voltage operation is suspended. The default value of\n"\ desc += "the TSLOCK bit is locked. The effective status of the UTEST protection is done\n"\ desc += "combining (Or-ed) LOCK0.TSLOCK with sidebands f90_plock0.31 in order to\n"\ desc += "evaluate protection against program." %define _DESC1283_ \ desc += "Low address space block LocK 13-0 (Read/Write)\n\n"\ desc += "These bits are used to lock the existing blocks of Low Address Space from\n"\ desc += "Program and Erase. A value of 1 in a bit of the LLK register signifies that the\n"\ desc += "corresponding block is locked for Program and Erase. A value of 0 in a bit of\n"\ desc += "the LLK register signifies that the corresponding block is available to receive\n"\ desc += "Program and Erase pulses. The LLK register is not writable once an Interlock\n"\ desc += "Write is completed until MCR.DONE is set at the completion of the requested\n"\ desc += "operation. Likewise, the LLK register is not writable if a high voltage\n"\ desc += "operation is suspended. The default value of the LLK bits is locked. In the\n"\ desc += "event that blocks are not present (due to configuration or total memory size),\n"\ desc += "the LLK bits default to locked, and are not writable. The reset value is\n"\ desc += "always1, and register writes have no effect." %define _DESC1284_ \ desc += "Mid address space block LocK 15-0 (Read/Write)\n\n"\ desc += "These bits are used to lock the blocks of Mid Address Space from Program and\n"\ desc += "Erase. A value of 1 in a bit of the MLK register signifies that the\n"\ desc += "corresponding block is locked for Program and Erase. A value of 0 in a bit of\n"\ desc += "the MLK register signifies that the corresponding block is available to receive\n"\ desc += "Program and Erase pulses. The MLK register is not writable once an Interlock\n"\ desc += "Write is completed until MCR.DONE is set at the completion of the requested\n"\ desc += "operation. Likewise, the MLK register is not writable if a high voltage\n"\ desc += "operation is suspended. The default value of the MLK bits is locked. In the\n"\ desc += "event that blocks are not present (due to configuration or total memory size),\n"\ desc += "the MLK bits default to locked, and are not writable. The reset value is always\n"\ desc += "1, and register writes have no effect." %define _DESC1285_ \ desc += "High address space Block Locking 1 register. The High/Data Address Space Block\n"\ desc += "Locking register provides a means of protecting blocks from being modified. HLK\n"\ desc += "bits corresponding to nonexistent blocks on a given cut are read as 1.\n\n"\ desc += "To determine the effective status of the High Address Space, combine (Or) LOCK1\n"\ desc += "with sidebands\n\n"\ desc += "f90_plock1 - in order to evaluate protection against program f90_elock1 - in\n"\ desc += "order to evaluate protection against erase. The effect of programming/erasing\n"\ desc += "a block protected with LOCK1 is that no modification occurs and PEG is set to\n"\ desc += "1." %define _DESC1286_ \ desc += "High address space block LocK 15-0 (Read/Write)\n\n"\ desc += "These bits are used to lock the blocks of High Address Space from Program and\n"\ desc += "Erase.\n\n"\ desc += "A value of 1 in a bit of the HLK register signifies that the corresponding\n"\ desc += "block is locked for Program and Erase.\n\n"\ desc += "A value of 0 in a bit of the HLK register signifies that the corresponding\n"\ desc += "block is available to receive Program and Erase pulses.\n\n"\ desc += "The HLK register is not writable once an Interlock Write is completed until\n"\ desc += "MCR.DONE is set at the completion of the requested operation. Likewise, the HLK\n"\ desc += "register is not writable if a high voltage operation is suspended.\n\n"\ desc += "The default value of the HLK bits is locked.\n\n"\ desc += "In the event that blocks are not present (due to configuration or total memory\n"\ desc += "size), the HLK bits default to locked, and are not writable. The reset value is\n"\ desc += "always 1, and register writes have no effect." %define _DESC1287_ \ desc += "256K address space Block Locking 2 register. The LOCK2 High Address Space Block\n"\ desc += "Locking register provides a means of protecting blocks from being modified.\n"\ desc += "These bits determine if the block is locked from Program or Erase. 256KLK bits\n"\ desc += "corresponding to nonexistent blocks on a given cut are read as 1.\n\n"\ desc += "To determine the effective status of the 256K Address Space, combine (Or) LOCK2\n"\ desc += "with sidebands:\n\n"\ desc += "f90_plock2 - in order to evaluate protection against program f90_elock2 - in\n"\ desc += "order to evaluate protection against erase. The effect of programming/erasing\n"\ desc += "a block protected with LOCK2 is that no modification occurs and PEG is set to\n"\ desc += "1." %define _DESC1288_ \ desc += "256K High address space block LocK 30-0 (Read/Write)\n\n"\ desc += "These bits are used to lock the existing blocks of Low Address Space from\n"\ desc += "Program and Erase. A value of 1 in a bit of the 256KLK register signifies that\n"\ desc += "the corresponding block is locked for Program and Erase. A value of 0 in a bit\n"\ desc += "of the 256KLK register signifies that the corresponding block is available to\n"\ desc += "receive Program and Erase pulses. The 256KLK register is not writable once an\n"\ desc += "Interlock Write is completed until MCR.DONE is set at the completion of the\n"\ desc += "requested operation. Likewise, the 256KLK register is not writable if a high\n"\ desc += "voltage operation is suspended. The default value of the 256KLK bits is locked.\n"\ desc += "In the event that blocks are not present (due to configuration or total memory\n"\ desc += "size), the 256KLK bits default to locked, and are not writable. The reset value\n"\ desc += "is always 1, and register writes have no effect." %define _DESC1289_ \ desc += "Select 0 register. The Low/Mid Address Space Block Select 0 register provides a\n"\ desc += "means to select blocks to be operated on during Erase or Array Integrity Check\n"\ desc += "- Margin Read.\n\n"\ desc += "Starting an Erase operation, SEL0 bits are latched and become non-alterable\n"\ desc += "from the first interlock cycle that follows the rising transition of MCR.ERS\n"\ desc += "(see step 4 in #Rda52842 ) until the completion of the Erase itself high\n"\ desc += "voltage operation (1 to 0 transition of MCR.EHV with MCR.ERS=1 and with\n"\ desc += "MCR.ESUS=0). Reading returns latched data (image of the SEL0 at the start of\n"\ desc += "the Erase operation) while writing has no effect." %define _DESC1290_ \ desc += "Low address space block SeLect 13-0 (Read/Write)\n\n"\ desc += "A value of 1 in the select register signifies that the block is selected for\n"\ desc += "Erase. A value of 0 in the select register signifies that the block is not\n"\ desc += "selected for Erase. The reset value for the select register is 0, or\n"\ desc += "unselected. The blocks must be selected (or unselected) before doing an Erase\n"\ desc += "Interlock Write as part of the Erase sequence. The select register is not\n"\ desc += "writable once an Interlock Write is completed until DONE is set at the\n"\ desc += "completion of the requested operation, or if a high voltage operation is\n"\ desc += "suspended. The select register is also not writable when UT0. AIE is high. In\n"\ desc += "the event that blocks are not present (due to configuration or total memory\n"\ desc += "size), the corresponding LSL bits default to unselected, and are not writable.\n"\ desc += "The reset value is always 0, and register writes have no effect" %define _DESC1291_ \ desc += "Mid address space block SeLect 15-0 (Read/Write)\n\n"\ desc += "A value of 1 in the select register signifies that the block is selected for\n"\ desc += "Erase. A value of 0 in the select register signifies that the block is not\n"\ desc += "selected for Erase. The reset value for the select register is 0, or\n"\ desc += "unselected. The blocks must be selected (or unselected) before doing an Erase\n"\ desc += "Interlock Write as part of the Erase sequence. The select register is not\n"\ desc += "writable once an Interlock Write is completed until DONE is set at the\n"\ desc += "completion of the requested operation, or if a high voltage operation is\n"\ desc += "suspended. The select register is also not writable when UT0.AIE is high. In\n"\ desc += "the event that blocks are not present (due to configuration or total memory\n"\ desc += "size), the corresponding MSL bits default to unselected, and are not writable.\n"\ desc += "The reset value is always 0, and register writes have no effect." %define _DESC1292_ \ desc += "Select 1 register. The High Address Space Block Select Register 1 provides a\n"\ desc += "means of selecting blocks to be operated on during Erase or Array Integrity\n"\ desc += "Check - Margin Read.\n\n"\ desc += "Starting an Erase operation, SEL1 bits are latched and become non-alterable\n"\ desc += "from the first interlock cycle that follows the rising transition of MCR.ERS\n"\ desc += "(see step 4 in #Rda52842 ) until the completion of the Erase High Voltage\n"\ desc += "operation (1 to 0 transition of MCR.EHV with MCR.ERS=1 and with MCR.ESUS=0).\n"\ desc += "Reading returns latched data (image of the SEL1 at the start of the Erase\n"\ desc += "operation) while writing has no effect." %define _DESC1293_ \ desc += "High/Data address space block SeLect 1 15-0 (Read/Write)\n\n"\ desc += "A value of 1 in the select register signifies that the block is selected for\n"\ desc += "Erase.\n\n"\ desc += "A value of 0 in the select register signifies that the block is not selected\n"\ desc += "for Erase. The reset value for the select register is 0, or unselected.\n\n"\ desc += "The blocks must be selected (or unselected) before doing an Erase Interlock\n"\ desc += "Write as part of the Erase sequence. The select register is not writable once\n"\ desc += "an Interlock Write is completed until DONE is set at the completion of the\n"\ desc += "requested operation, or if a high voltage operation is suspended.\n\n"\ desc += "The select register is also not writable when UT0.AIE is high.\n\n"\ desc += "In the event that blocks are not present (due to configuration or total memory\n"\ desc += "size), the corresponding HSL bits default to unselected, and are not writable.\n"\ desc += "The reset value is always 0, and register writes have no effect." %define _DESC1294_ \ desc += "Select 2 register. The 256K high Address Space Block Select 2 register provides\n"\ desc += "a means of selecting blocks to be operated on during Erase or Array Integrity\n"\ desc += "Check - Margin Read.\n\n"\ desc += "Starting an Erase operation, SEL2 bits are latched and become non-alterable\n"\ desc += "from the first interlock cycle that follows the rising transition of MCR.ERS\n"\ desc += "(see step 4 in #Rda52842 ) until the completion of the Erase itself high\n"\ desc += "voltage operation (1 to 0 transition of MCR.EHV with MCR.ERS=1 and with\n"\ desc += "MCR.ESUS=0). Reading returns latched data (image of the SEL2 at the start of\n"\ desc += "the Erase operation) while writing has no effect." %define _DESC1295_ \ desc += "256K High address space block SeLect 30-0 (Read/Write)\n\n"\ desc += "A value of 1 in the select register signifies that the block is selected for\n"\ desc += "Erase. A value of 0 in the select register signifies that the block is not\n"\ desc += "selected for Erase. The reset value for the select register is 0, or\n"\ desc += "unselected. The blocks must be selected (or unselected) before doing an Erase\n"\ desc += "Interlock Write as part of the Erase sequence. The select register is not\n"\ desc += "writable once an Interlock Write is completed until DONE is set at the\n"\ desc += "completion of the requested operation, or if a high voltage operation is\n"\ desc += "suspended. The select register is also not writable when UT0. AIE is high.\n\n"\ desc += "In the event that blocks are not present (due to configuration or total memory\n"\ desc += "size), the corresponding 256KSL bits default to unselected, and are not\n"\ desc += "writable. The reset value is always 0, and register writes have no effect." %define _DESC1296_ \ desc += "Address Register. The Address Register provides the first failing address in\n"\ desc += "the event module failures (ECC, RWW or FPEC) or the first address at which a\n"\ desc += "ECC single error correction occurs. ADR captures the first failing address,\n"\ desc += "with the below priority rule, under the following modes:\n\n"\ desc += "See reference manual for 'ADR update mode list' table. In case of Array\n"\ desc += "Integrity Check or Margin Read, with Break Point enabled (UT0.AIBPE=1), ADR\n"\ desc += "value matches Break Point address, whose location has triggered the Break, only\n"\ desc += "if the current run has been started with MCR.ERR and MCR.SBC flags cleared.\n"\ desc += "Current run is intended to be either the first start, either the re-start after\n"\ desc += "a breakpoint is encountered (NAIBP being cleared). Otherwise ADR priority rule\n"\ desc += "overrides Break Point.\n\n"\ desc += "[ADR content: priority list]:\n"\ desc += " Priority Level Error Flag ADR content\n"\ desc += " -------------- ----------- --------------------------------------------\n"\ desc += " 1 MCR.EER = 1 Address of first ECC Double Error\n"\ desc += " 2 MCR.RWE = 1 Address of first RWW Error\n"\ desc += " 3 MCR.PEG = 0 Address of first FPEC Error\n"\ desc += " 4 MCR.SBC = 1 Address of first ECC Single Error Correction\n" %define _DESC1297_ \ desc += "Test Address (read only) When this bit is high, the address indicated by AD23-3\n"\ desc += "belongs to the Test Block." %define _DESC1298_ \ desc += "ADdress 23-3 (read only)\n\n"\ desc += "The Address Register provides the first failing address in the event of ECC\n"\ desc += "error (MCR.EER set) or the first failing address in the event of RWW error\n"\ desc += "(MCR.RWE set), or the address of a failure that may have occurred in a FPEC\n"\ desc += "operation (MCR.PEG cleared). The Address Register provides also the first\n"\ desc += "address at which a ECC single error correction occurs (MCR.EDC set), if the SoC\n"\ desc += "is configured to show this feature (through UT0.SBCE). The ECC double error\n"\ desc += "detection takes the highest priority, followed by the RWW error, the FPEC error\n"\ desc += "and the ECC single error correction. When accessed, ADR provides the address\n"\ desc += "related to the first event occurred with the highest priority. The priorities\n"\ desc += "between these four possible events is summarized in the following table. This\n"\ desc += "address is always a doubleword address that selects 64 bits. In case of a\n"\ desc += "simultaneous ECC Double Error Detection on more than one doubleword of the same\n"\ desc += "page, bits AD4 and AD3 output 0. The same is valid for a simultaneous ECC\n"\ desc += "Single Error Correction on more than one doubleword of the same page. In User\n"\ desc += "mode the Address Register is read only. Address given is in flash format and\n"\ desc += "has to be intended as in the flash memory Map: offset respect to absolute\n"\ desc += "address." %define _DESC1299_ \ desc += "User Test register 0. The User Test feature gives the user of the Flash Memory\n"\ desc += "module the ability to perform test features on the flash.\n\n"\ desc += "The User Test 0 register allows control of the way the flash content check is\n"\ desc += "performed. Bits MRE, MRV, AIS and DSI7-0 of the User Test 0 register are not\n"\ desc += "accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate\n"\ desc += "data while writing has no effect." %define _DESC1300_ \ desc += "User Test Enable (Read/Clear)\n\n"\ desc += "This status bit gives indication when User Test is enabled. All bits in UT0 and\n"\ desc += "UMISR0-9 are locked when this bit is 0. This bit is not writable to a 1, but\n"\ desc += "may be cleared. The reset value is 0. The method to set this bit is to provide\n"\ desc += "a password, and if the password matches, the UTE bit is set to reflect the\n"\ desc += "status of enabled, and is enabled until it is cleared by a register Write. The\n"\ desc += "UTE password is only accepted if PGM = 0 and ERS = 0 (Program and Erase are not\n"\ desc += "being requested). UTE can only be cleared if AID = 1, MRE and AIE = 0. While\n"\ desc += "clearing UTE, writes to set AIE or MRE are ignored. For UTE the password\n"\ desc += "0xF9F99999 must be written to the UT0 register." %define _DESC1301_ \ desc += "Single Bit Correction Enable (Read/Clear)\n\n"\ desc += "This bit, when high, enables to flag the information about any eventual ECC\n"\ desc += "Single Bit Correction in the flash array (MCR.SBC and ADR). This is true in\n"\ desc += "read mode and in Array Integrity Check.\n\n"\ desc += "SBCE also is used as an Enable for interrupt signals created by the embedded\n"\ desc += "flash memory. ECC corrections that occur when SBCE is cleared are not logged." %define _DESC1302_ \ desc += "Next Array Integrity Break Point (Read/Clear)\n\n"\ desc += "If AIBPE is set, NAIBP is set once a single bit correction (if enabled) or\n"\ desc += "double bit detection is noted during the Array Integrity test. NAIBP is not\n"\ desc += "writable to 1, but may be cleared to 0.Clearing NAIBP to 0 enables the Array\n"\ desc += "Integrity operation to be re-started after a breakpoint is encountered. If the\n"\ desc += "Array Integrity operation completes without encountering another correction or\n"\ desc += "detection, AID is set with NAIBP remaining 0." %define _DESC1303_ \ desc += "Array Integrity Break Point Enable. (Read/Write)\n\n"\ desc += "To enable breakpoints during an Array Integrity test, AIBPE may be set. When\n"\ desc += "breakpoints are enabled, if the run has been started with MCR.ERR (and MCR.SBC,\n"\ desc += "if UT0.SBCE=1) flag cleared, on the eventual occurrence of a breakpoint\n"\ desc += "condition, MCR flags and ADR value may be updated. See NAIBP description for\n"\ desc += "more information about Array Integrity breakpoints." %define _DESC1304_ \ desc += "Array Integrity Suspend (Read/Write).\n\n"\ desc += "AISUS enables a Suspend of an Array Integrity - Margin Read Operation. Array\n"\ desc += "Integrity - Margin Read may be suspended by setting AISUS and resumed by\n"\ desc += "clearing AISUS. AISUS can be written to a 1 only when AID is low and setting\n"\ desc += "AISUS produces a 0->1 AID transition. AISUS can be written to a 0 only when AID\n"\ desc += "is high. Attempting to Write AISUS and AIE on the same clock cycle results in\n"\ desc += "only AIE being written." %define _DESC1305_ \ desc += "Margin Read Enable (Read/Write) MRE enables margin reads to be done. This bit,\n"\ desc += "combined with MRV, enables User Margin mode reads to be done. Margin reads is\n"\ desc += "run on block basis like with the Array Integrity Checks sequences: block or\n"\ desc += "blocks to be checked with Margin are selected by SEL0, SEL1 and SEL2. Margin\n"\ desc += "read run on blocks basis is following a linear address sequence. This bit is\n"\ desc += "not accessible whenever MCR.DONE or UT0.AID are low or if AISUS is high, or if\n"\ desc += "NAIBP is high: reading returns indeterminate data while writing has no\n"\ desc += "effect." %define _DESC1306_ \ desc += "Margin Read Value (Read/Write) If MRE is high, MRV selects the margin level\n"\ desc += "that is being checked. Margin can be checked to an erased level (MRV=1) or to a\n"\ desc += "programmed level (MRV=0). This bit is not accessible whenever MCR.DONE or\n"\ desc += "UT0.AID are low or if AISUS is high, or if NAIBP is high: reading returns\n"\ desc += "indeterminate data while writing has no effect." %define _DESC1307_ \ desc += "Array Integrity Sequence (Read/Write) AIS determines the address sequence to be\n"\ desc += "used during Array Integrity checks. The default sequence (AIS=0) is meant to\n"\ desc += "replicate sequences normal user code follows, and thoroughly checks the read\n"\ desc += "propagation paths. This sequence is proprietary. The alternative sequence\n"\ desc += "(AIS=1) is just logically sequential. It should be noted that the time to run a\n"\ desc += "sequential sequence is significantly shorter than the time to run the\n"\ desc += "proprietary sequence. AIS is not writeable if AIE is high. This bit is not\n"\ desc += "accessible whenever MCR.DONE or UT0.AID are low: reading returns indeterminate\n"\ desc += "data while writing has no effect." %define _DESC1308_ \ desc += "Array Integrity Enable (Read/Write) AIE set to 1 starts the Array Integrity\n"\ desc += "Check and the Margin Read on all selected blocks. The pattern is selected by\n"\ desc += "AIS, and the MISR (UMISR0-9) can be checked after the operation is complete, to\n"\ desc += "determine if a correct signature is obtained. AIE can be set only if MCR.ERS,\n"\ desc += "MCR.PGM and MCR.EHV are all low. AIE is not simultaneously writable to a 1 as\n"\ desc += "UTE is being cleared to a 0. Once an Array Integrity operation is requested\n"\ desc += "(AIE=1), it may be terminated by clearing AIE if the operation has finished\n"\ desc += "(AID = 1) or aborted by clearing AIE if the operation is ongoing (AID = 0). AIE\n"\ desc += "remains at 1 when the Array Integrity Check - Margin read are suspended or are\n"\ desc += "in breakpoint and cannot be cleared. (AIE can be cleared if NAIBP=0 and\n"\ desc += "AISU=0)" %define _DESC1309_ \ desc += "Array Integrity Done (read only) AID is cleared upon an Array Integrity Check -\n"\ desc += "Margin Read, being enabled (to signify the operation is on-going). Once\n"\ desc += "completed, AID is set to indicate that the Array Integrity Check - Margin Read\n"\ desc += "is complete. At this time the MISR (UMISR0-9) can be checked. AID may also\n"\ desc += "assert if breakpoints are enabled (AIBPE is set) and the breakpoint condition\n"\ desc += "is met. AID may also assert if Suspend is set (AISUS 0->1). AID can not be\n"\ desc += "written, and is status only.\n\n"\ desc += "0 Array Integrity Check is on-going.\n\n"\ desc += "1 Array Integrity Check is done." %define _DESC1310_ \ desc += "User Multiple Input Signature Register 0. UMISR0 represents bits 31-0 of the\n"\ desc += "whole 144-bit word (2 doublewords including ECC)." %define _DESC1311_ \ desc += "Multiple input Signature 031-000 (Read/Write) These bits represents the MISR\n"\ desc += "value obtained accumulating the bits 31-0 of all the pages read from the flash\n"\ desc += "memory. The MS can be seeded to any value by writing the UMISR0 register.\n"\ desc += "Writing the MISR register during an Array Integrity operation (including\n"\ desc += "Suspend or Breakpoint) although possible, is not recommended. A Write of the\n"\ desc += "MISR registers at this point may alter the final signature in an unpredictable\n"\ desc += "way." %define _DESC1312_ \ desc += "User Multiple Input Signature Register 1. UMISR1 represents bits 63-32 of the\n"\ desc += "whole 144-bit word (2 doublewords including ECC)." %define _DESC1313_ \ desc += "MS1[31:00]: Multiple input Signature 063-032 (Read/Write) These bits represents\n"\ desc += "the MISR value obtained accumulating the bits 63-32 of all the pages read from\n"\ desc += "the flash memory. The MS can be seeded to any value by writing the UMISR1\n"\ desc += "register. Writing the MISR register during an Array Integrity operation\n"\ desc += "(including Suspend or Breakpoint) although possible, is not recommended. A\n"\ desc += "Write of the MISR registers at this point may alter the final signature in an\n"\ desc += "unpredictable way." %define _DESC1314_ \ desc += "User Multiple Input Signature Register 2. UMISR2 represents bits 95-64 of the\n"\ desc += "whole 144-bit word (2 doublewords including ECC)." %define _DESC1315_ \ desc += "Multiple input Signature 095-064 (Read/Write)\n\n"\ desc += "These bits represents the MISR value obtained accumulating the bits 95-64 of\n"\ desc += "all the pages read from the flash memory.\n\n"\ desc += "The MS can be seeded to any value by writing the UMISR2 register. Writing the\n"\ desc += "MISR register during an Array Integrity operation (including Suspend or\n"\ desc += "Breakpoint) although possible, is not recommended. A Write of the MISR\n"\ desc += "registers at this point may alter the final signature in an unpredictable\n"\ desc += "way." %define _DESC1316_ \ desc += "User Multiple Input Signature Register 3. UMISR3 represents bits 127-96 of the\n"\ desc += "whole 144-bit word (2 doublewords including ECC)." %define _DESC1317_ \ desc += "Multiple input Signature 127-096 (Read/Write)\n\n"\ desc += "These bits represents the MISR value obtained accumulating the bits 127-96 of\n"\ desc += "all the pages read from the flash memory.\n\n"\ desc += "The MS can be seeded to any value by writing the UMISR3 register. Writing the\n"\ desc += "MISR register during an Array Integrity operation (including Suspend or\n"\ desc += "Breakpoint) although possible, is not recommended. A Write of the MISR\n"\ desc += "registers at this point may alter the final signature in an unpredictable\n"\ desc += "way." %define _DESC1318_ \ desc += "User Multiple Input Signature Register 8. UMISR8 represents the ECC parity bits\n"\ desc += "of the whole 144 bits word (8 parity bits for each of the 2 doublewords)." %define _DESC1319_ \ desc += "Multiple input Signature 287-256 (Read/Write)\n\n"\ desc += "These bits represents the MISR value obtained accumulating the 8 parity bits of\n"\ desc += "the 4 doubleword read from the flash memory.\n\n"\ desc += "The MS can be seeded to any value by writing the UMISR8 register. Writing the\n"\ desc += "MISR register during an Array Integrity operation (including Suspend or\n"\ desc += "Breakpoint) although possible, is not recommended. A Write of the MISR\n"\ desc += "registers at this point may alter the final signature in an unpredictable\n"\ desc += "way." %define _DESC1320_ \ desc += "User Multiple Input Signature Register 9. UMISR9 represents the ERR bits." %define _DESC1321_ \ desc += "MS9[31:00]: Multiple input Signature 319-288 (Read/Write)\n\n"\ desc += "These bits represents the MISR value obtained accumulating ERR from the flash\n"\ desc += "memory.\n\n"\ desc += "The MS can be seeded to any value by writing the UMISR9 register. Writing the\n"\ desc += "MISR register during an Array Integrity operation (including Suspend or\n"\ desc += "Breakpoint) although possible, is not recommended. A Write of the MISR\n"\ desc += "registers at this point may alter the final signature in an unpredictable\n"\ desc += "way." %define _DESC1322_ \ desc += "Over Program Protection Register 0. The Low/Mid Address Space is covered by the\n"\ desc += "Over Program Protection 0 (OPP0) register." %define _DESC1323_ \ desc += "Low address space Over Program Protection 13-0 (Read) A value of 1 in the\n"\ desc += "select register signifies that the block is over programming protected. A value\n"\ desc += "of 0 in the select register signifies that the block is not over programming\n"\ desc += "protected." %define _DESC1324_ \ desc += "Mid address space Over Program Protection15-0 (Read) A value of 1 in the select\n"\ desc += "register signifies that the block is over programming protected. A value of 0\n"\ desc += "in the select register signifies that the block is not over programming\n"\ desc += "protected." %define _DESC1325_ \ desc += "Over Program Protection Register 1. The High Address Space is covered by the\n"\ desc += "Over Program Protection 1 (OPP1) register." %define _DESC1326_ \ desc += "High address space Over Program Protection 15-0 (Read)\n\n"\ desc += "A value of 1 in the select register signifies that the block is over\n"\ desc += "programming protected.\n\n"\ desc += "A value of 0 in the select register signifies that the block is not over\n"\ desc += "programming protected." %define _DESC1327_ \ desc += "Over Program Protection Register 2. The 256K high Address Space is covered by\n"\ desc += "the Over Program Protection 2 (OPP2) register." %define _DESC1328_ \ desc += "256K High address space Over Program Protection 1-31 (Read)\n\n"\ desc += "A value of 1 in the select register signifies that the block is over\n"\ desc += "programming protected.\n\n"\ desc += "A value of 0 in the select register signifies that the block is not over\n"\ desc += "programming protected." %define _DESC1329_ \ desc += "Test Mode Disable Password Check Register. The Test Mode Disable Password Check\n"\ desc += "(TSMPC) register provides a means of entering the password to be matched with\n"\ desc += "the one stored in UTEST location (Test Mode Disable Override Passcode in 0x3DC8\n"\ desc += "address offset) in order to allow manufacturer access to Test mode blocks\n"\ desc += "(identified by TDMBS) that are protected by writing 0x5A4B_3C2D in the Test\n"\ desc += "Mode Disable Seal location." %define _DESC1330_ \ desc += "Test Mode Disable Password Check 31-0 (Read)\n\n"\ desc += "A value of 1 in the select register signifies that the block is over\n"\ desc += "programming protected.\n\n"\ desc += "A value of 0 in the select register signifies that the block is not over\n"\ desc += "programming protected." %define _DESC1331_ \ desc += "Core Release Register. " %define _DESC1332_ \ desc += "Core Release. One digit, BCD." %define _DESC1333_ \ desc += "Step of Core Release. One digit, BCD." %define _DESC1334_ \ desc += "Sub-step of Core Release. One digit, BCD." %define _DESC1335_ \ desc += "Time Stamp Year. One digit, BCD." %define _DESC1336_ \ desc += "Time Stamp Month. Two digits, BCD." %define _DESC1337_ \ desc += "Time Stamp Day. Two digits, BCD." %define _DESC1338_ \ desc += "Endian Register. " %define _DESC1339_ \ desc += "Endianness Test Value. The endianness test value is 0x87654321." %define _DESC1340_ \ desc += "Fast Bit Timing and Prescaler Register. The CAN bit time may be programed in\n"\ desc += "the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the\n"\ desc += "range of 1 to 1024 MCAN clock periods. tq = (FBRP + 1) MCAN clock period.\n"\ desc += "FTSEG1 is the sum of Prop_Seg and Phase_Seg1. FTSEG2 is Phase_Seg2. Therefore\n"\ desc += "the length of the bit time is (prog rammed values) [FTSEG1 + FTSEG2 + 3] tq or\n"\ desc += "(functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The\n"\ desc += "Information Processing Time (IPT) is zero, meaning the data for the next bit is\n"\ desc += "available at the first clock edge after the sample point. Protected write (P)\n"\ desc += "register which means that the write access to this register is possible only\n"\ desc += "when the CCCR[CCE] and CCCR[INIT] register fields are set to '1'. With a M_CAN\n"\ desc += "clock of 8 MHz, the reset value of 0x00000A33 configures the M_CAN for a fast\n"\ desc += "bit rate of 500 kbit/s." %define _DESC1341_ \ desc += "(0x0-0xF)- Offset value defining the distance between the measured delay from\n"\ desc += "M_CAN trasmit to M_CAN receive and the secondary sample point. Valid values are\n"\ desc += "0 to 15 MCAN clock periods." %define _DESC1342_ \ desc += "(0x000-0x3FF)- The value by which the oscillator frequency is divided for\n"\ desc += "generating the bit time quanta. The bit time is built up from a multiple of\n"\ desc += "this quanta. Valid values for the Baud Rate Prescaler are 0 to 1023. The actual\n"\ desc += "interpretation by the hardware of this value is such that one more than the\n"\ desc += "value prog rammed here is used." %define _DESC1343_ \ desc += "(0x1-0xF) Valid values are 1 to 15. The actual interpretation by the hardware\n"\ desc += "of this value is such that one more than the programmed value is used." %define _DESC1344_ \ desc += "(0x0-0x7) Valid values are 0 to 7. The actual interpretation by the hardware of\n"\ desc += "this value is such that one more than the programmed value is used." %define _DESC1345_ \ desc += "0x0-0x3 Valid values are 0 to 3. The actual interpretation by the hardware of\n"\ desc += "this value is such that one more than the value programmed here is used." %define _DESC1346_ \ desc += "Test Register. Write access to the Test Register has to be enabled by setting\n"\ desc += "CCCR[TEST] to '1'. All Test Register functions are set to their reset values\n"\ desc += "when CCCR[TEST] is reset. Loop Back mode and software control of MCAN Tx pin\n"\ desc += "are hardware test modes. Programming of TX other than'00' may disturb the\n"\ desc += "message transfer on the CAN bus." %define _DESC1347_ \ desc += "(0x00-0x1F) - Position of the secondary sample point, defined by the sum of the\n"\ desc += "measured delay from M_CAN transmit to M_CAN receive and FBTP[TDCO]. Valid\n"\ desc += "values are 0 to 31 M_CAN core clock periods." %define _DESC1348_ \ desc += "Receive Pin. Monitors the actual value of pin m_ can_rx\n\n"\ desc += "The reset value of this bit is undefined" %define _DESC1349_ \ desc += "Control of Transmit Pin\n\n"\ desc += "Protected write (P) bit(s) which means that the write access to this field is\n"\ desc += "possible only when the CCCR[CCE] and CCCR[INIT] register fields are set to '1'." %define _DESC1350_ \ desc += "Loop Back mode\n\n"\ desc += "Protected write (P) bit(s) which means that the write access to this field is\n"\ desc += "possible only when the CCCR[CCE] and CCCR[INIT] register fields are set to '1'." %define _DESC1351_ \ desc += "RAM Watchdog Register. The RAM Watchdog monitors the READY output of the\n"\ desc += "Message RAM . A Message RAM access via the M_CAN's Generic Master Interface\n"\ desc += "starts the Message RAM Watchdog Counter with the value configured by the WDC\n"\ desc += "bits. The counter is reloaded with WDC bits when the Message RAM signals\n"\ desc += "successful completion by activating its READY output. In case there is no\n"\ desc += "response from the Message RAM until the counter has counted down to zero, the\n"\ desc += "counter stops and interrupt flag WDI bit of the IR register is set. The RAM\n"\ desc += "Watchdog Counter is clocked by the Host clock .\n\n"\ desc += "Protected write (P) register which means that the write access to this register\n"\ desc += "is possible only when the CCCR[CCE] and CCCR[INIT] register fields are set to\n"\ desc += "'1'." %define _DESC1352_ \ desc += "Watchdog Value. Actual Message RAM Watchdog Counter Value" %define _DESC1353_ \ desc += "Watchdog Configuration. Start value of the Message RAM Watchdog Counter. With\n"\ desc += "the reset value of '00' the counter is disabled.\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1354_ \ desc += "CC Control Register. This section explains the CAN Control register.\n\n"\ desc += "Due to the synchronization mechanism between the two clock domains, there may\n"\ desc += "be a delay until the value written to INIT can be read back. Therefore the\n"\ desc += "programmer has to assure that the previous value written to INIT has been\n"\ desc += "accepted by reading INIT before setting INIT to a new value." %define _DESC1355_ \ desc += "Test Enable Mode\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1356_ \ desc += "DAR: Disable Automatic Retransmission\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1357_ \ desc += "Bus Monitoring Mode. Bit MON can only be set by the Host when both CCE and INIT\n"\ desc += "are set to '1'. The bit can be reset by the Host at any time.\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1358_ \ desc += "Clock Stop Request" %define _DESC1359_ \ desc += "Clock Stop Acknowledge" %define _DESC1360_ \ desc += "ASM Restricted Operation Mode. The Restricted Operation Mode is intended for\n"\ desc += "applications that adapt themselves to different CAN bit rates. The application\n"\ desc += "tests different bit rates and leaves the Restricted Operation Mode after it has\n"\ desc += "received a valid frame. In the optional Restricted Operation Mode the node is\n"\ desc += "able to transmit and receive data and remote frames and it gives acknowledge to\n"\ desc += "valid frames, but it does not send active error frames or overload frames. In\n"\ desc += "case of an error condition or overload condition, it does not send dominant\n"\ desc += "bits, instead it waits for the occurrence of bus idle condition to\n"\ desc += "resynchronize itself to the CAN communication. The error counters are not\n"\ desc += "incremented. Bit ASM can only be set by the Host when both CCE and INIT are set\n"\ desc += "to '1'. The bit can be reset by the Host at any time.\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1361_ \ desc += "Configuration Change Enable\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1362_ \ desc += "Initialization" %define _DESC1363_ \ desc += "Bit Timing and Prescaler Register. The CAN bit time may be programed in the\n"\ desc += "range of [4....81] time quanta. The CAN time quantum may be programmed in the\n"\ desc += "range of [1....1024] MCAN clock periods.\n\n"\ desc += "tq = (BRP + 1) MCAN clock period\n\n"\ desc += "TSEG1 is the sum of Prop_Seg and Phase_Seg1. TSEG2 is Phase_Seg2. Therefore the\n"\ desc += "length of the bit time is (programmed values) [TSEG1 + TSEG2 + 3] tq or\n"\ desc += "(functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq.\n\n"\ desc += "Protected write (P) register which means that the write access to this register\n"\ desc += "is possible only when the CCCR[CCE] and CCCR[INIT] register fields are set to\n"\ desc += "'1'. With a CAN clock of 8 MHz, the reset value of 0x00002301 configures the\n"\ desc += "M_CAN for a bit rate of 500 kBit/s. The Information Processing Time (IPT) of\n"\ desc += "the M_CAN is 0 tq. Therefore, to conform to the CAN protocol specification, the\n"\ desc += "lengths for phase segment 1 (Phase_Seg1) and phase segment 2 (Phase_Seg2) must\n"\ desc += "be equal." %define _DESC1364_ \ desc += "(0x000-0x3FF) The value by which the oscillator frequency is divided for\n"\ desc += "generating the bit time quanta. The bit time is built up from a multiple of\n"\ desc += "this quanta. Valid values for the Baud Rate Prescaler are 0 to 1023. The actual\n"\ desc += "interpretation by the hardware of this value is such that one more than the\n"\ desc += "value prog rammed here is used. Protected write (P) bit(s) which means that\n"\ desc += "write access by the bit(s) is possible only when the bit 1 [CCE] CCCR[INIT]\n"\ desc += "register fields are set to '1'." %define _DESC1365_ \ desc += "(0x01-0x3F) Valid values are 1 to 63. The actual interpretation by the hardware\n"\ desc += "of this value is such that one more than the prog rammed value is used.\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1366_ \ desc += "(0x0-0xF) Valid values are 0 to 15. The actual interpretation by the hardware\n"\ desc += "of this value is such that one more than the prog rammed value is used.\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1367_ \ desc += "(0x0-0xF) Valid values are 0 to 15. The actual interpretation by the hardware\n"\ desc += "of this value is such that one more than the value prog rammed here is used\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1368_ \ desc += "Timestamp Counter Configuration Register. " %define _DESC1369_ \ desc += "Timestamp Counter Prescaler\n\n"\ desc += "0x0-0xF Configures the timestamp and timeout counters time unit in multiples of\n"\ desc += "CAN bit times [1...16].\n\n"\ desc += "The actual interpretation by the hardware of this value is such that one more\n"\ desc += "than the value programmed here is used.\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1370_ \ desc += "Timestamp Select\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1371_ \ desc += "Timestamp Counter Value Register. " %define _DESC1372_ \ desc += "Timestamp Counter. The Timestamp Counter value is captured on start of frame\n"\ desc += "(both Rx and Tx).\n\n"\ desc += "When TSCC[TSS] = '01', the Timestamp Counter is incremented in multiples of CAN\n"\ desc += "bit times[1...16] depending on the configuration of TSCC[TCP]. A wrap around\n"\ desc += "sets interrupt flag IR[TSW]. Write access resets the counter to zero.\n\n"\ desc += "A 'wrap around' is a change of the Timestamp Counter value from non-zero to\n"\ desc += "zero not caused by write access to TSCV." %define _DESC1373_ \ desc += "Timeout Counter Configuration Register. For a description of the Timeout\n"\ desc += "Counter see Timeout counter .\n\n"\ desc += "Protected write (P) register which means that the write access to this register\n"\ desc += "is possible only when the CCCR[CCE] and CCCR[INIT] register fields are set to\n"\ desc += "'1'." %define _DESC1374_ \ desc += "Timeout Period. Start value of the Timeout Counter (down-counter). Configures\n"\ desc += "the Timeout Period.\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1375_ \ desc += "Timeout Select\n\n"\ desc += "When operating in Continuous mode, a write to TOCV presets the counter to the\n"\ desc += "value configured by TOCC[TOP] and continues down-counting. When the Timeout\n"\ desc += "Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to\n"\ desc += "the value configured by TOCC[TOP]. Down-counting is started when the first FIFO\n"\ desc += "element is stored.\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1376_ \ desc += "Enable Timeout Counter\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1377_ \ desc += "Timeout Counter Value Register. " %define _DESC1378_ \ desc += "The Timeout Counter is decremented in multiples of CAN bit times [1...16]\n"\ desc += "depending on the configuration of TSCC.TCP. When decremented to zero, interrupt\n"\ desc += "flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart\n"\ desc += "conditions are configured via TOCC.TOS." %define _DESC1379_ \ desc += "Error Counter Register. " %define _DESC1380_ \ desc += "CAN Error Logging. The counter is incremented each time when a CAN protocol\n"\ desc += "error causes the Transmit Error Counter or the Receive Error Counter to be\n"\ desc += "incremented. It is reset by read access to CEL. The counter stops at 0xFF; the\n"\ desc += "next increment of TEC or REC sets interrupt flag ELO bit of the IR register." %define _DESC1381_ \ desc += "Receive Error Passive" %define _DESC1382_ \ desc += "Receive Error Counter\n\n"\ desc += "Actual state of the Receive Error Counter, values between 0 and 127" %define _DESC1383_ \ desc += "Transmit Error Counter. Actual state of the Transmit Error Counter, values\n"\ desc += "between 0 and 255." %define _DESC1384_ \ desc += "Protocol Status Register. When a frame in CAN FD format has reached the data\n"\ desc += "phase with BRS flag set, the next CAN event (error or valid frame) will be\n"\ desc += "shown in FLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC\n"\ desc += "sequence will be shown as a Form Error, not Stuff Error . The Bus_Off recovery\n"\ desc += "sequence (see CAN Specification Rev. 2.0 or ISO11898-1) cannot be shortened by\n"\ desc += "setting or resetting CCCR[INIT.] If the device goes Bus_Off, it will set\n"\ desc += "CCCR[INIT] of its own accord, stopping all bus activities. Once CCCR[INIT] has\n"\ desc += "been cleared by the CPU, the device will then wait for 129 occurrences of Bus\n"\ desc += "Idle (129 x 11 consecutive recessive bits) before resuming normal operation. At\n"\ desc += "the end of the Bus_Off recovery sequence, the Error Management Counters will be\n"\ desc += "reset. During the waiting time after the resetting of CCCR[INIT], each time a\n"\ desc += "sequence of 11 recessive bits has been monitored, a Bit 0 Error code is written\n"\ desc += "to PSR[LEC], enabling the CPU to readily check up whether the CAN bus is stuck\n"\ desc += "at dominant or continuously disturbed and to monitor the Bus_Off recovery\n"\ desc += "sequence. ECR[REC] is used to count these sequences." %define _DESC1385_ \ desc += "This field is reset by a read operation." %define _DESC1386_ \ desc += "This bit is set together with REDL, independent of acceptance filtering. This\n"\ desc += "field is reset by a read operation." %define _DESC1387_ \ desc += "Type of last error that occurred in the data phase of a CAN FD format frame\n"\ desc += "with its BRS flag set. Coding is the same as for LEC. This field will be\n"\ desc += "cleared to zero when a CAN FD format frame with its BRS flag set has been\n"\ desc += "transferred (reception or transmission) without error. This field is set by a\n"\ desc += "read operation." %define _DESC1388_ \ desc += "Bus_Off Status" %define _DESC1389_ \ desc += "Warning Status" %define _DESC1390_ \ desc += "Error Passive" %define _DESC1391_ \ desc += "Activity\n\n"\ desc += "Monitors the module's CAN communication state." %define _DESC1392_ \ desc += "Last Error Code\n\n"\ desc += "The LEC indicates the type of the last error to occur on the CAN bus. This\n"\ desc += "field will be cleared to '0' when a message has been transferred (reception or\n"\ desc += "transmission) without error.\n\n"\ desc += "000 No Error: No error occurred since LEC has been reset by successful\n"\ desc += "reception or transmission.\n\n"\ desc += "001 Stuff Error: More than 5 equal bits in a sequence have occurred in a part\n"\ desc += "of a received message where this is not allowed.\n\n"\ desc += "010: Form Error: A fixed format part of a received frame has the wrong\n"\ desc += "format.\n\n"\ desc += "011: AckError: The message transmitted by the M_CAN was not acknowledged by\n"\ desc += "another node.\n\n"\ desc += "100: Bit1Error: During the transmission of a message (with the exception of the\n"\ desc += "arbitration field), the device wanted to send a recessive level (bit of logical\n"\ desc += "value '1'), but the monitored bus value was dominant.\n\n"\ desc += "101: Bit0Error: During the transmission of a message (or acknowledge bit, or\n"\ desc += "active error flag, or overload flag), the device wanted to send a dominant\n"\ desc += "level (data or identifier bit logical value '0'), but the monitored bus value\n"\ desc += "was recessive. During Bus_Off recovery this status is set each time a sequence\n"\ desc += "of11 recessive bits has been monitored. This enables the CPU to monitor the\n"\ desc += "proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at\n"\ desc += "dominant or continuously disturbed).\n\n"\ desc += "110: CRCError: The CRC check sum of a received message was incorrect. The CRC\n"\ desc += "of an incoming message does not match with the CRC calculated from the received\n"\ desc += "data.\n\n"\ desc += "111: NoChange: Any read access to the Protocol Status Register re-initializes\n"\ desc += "the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected\n"\ desc += "since the last CPU read access to the Protocol Status Register.\n\n"\ desc += "This field is set by a read operation." %define _DESC1393_ \ desc += "Interrupt Register. The flags are set when one of the listed conditions is\n"\ desc += "detected (edge-sensitive). The flags remain set until the Host clears them. A\n"\ desc += "flag is cleared by writing a '1' to the corresponding bit position. Writing a\n"\ desc += "'0' has no effect. A hard reset will clear the register. The configuration of\n"\ desc += "IE controls whether an interrupt is generated. The configuration of ILS\n"\ desc += "controls on which interrupt line an interrupt is signaled." %define _DESC1394_ \ desc += "Stuff Error" %define _DESC1395_ \ desc += "Format Error" %define _DESC1396_ \ desc += "Acknowledge Error" %define _DESC1397_ \ desc += "Bit Error" %define _DESC1398_ \ desc += "CRC Error" %define _DESC1399_ \ desc += "Watchdog Interrupt" %define _DESC1400_ \ desc += "Error Logging Overflow" %define _DESC1401_ \ desc += "Bit Error Uncorrected. Message RAM bit error detected, uncorrected. Controlled\n"\ desc += "by Message RAM bit error input signal generated by an optional external parity\n"\ desc += "/ ECC logic attached to the Message RAM. An uncorrected Message RAM bit error\n"\ desc += "sets CCCR[INIT] to '1'. This is done to avoid transmission of corrupted data." %define _DESC1402_ \ desc += "Bit Error Corrected. Message RAM bit error detected and corrected. Controlled\n"\ desc += "by Message RAM bit error input signal generated by an optional external parity\n"\ desc += "/ ECC logic attached to the Message RAM." %define _DESC1403_ \ desc += "The flag is set whenever a received message has been stored into a dedicated Rx\n"\ desc += "Buffer." %define _DESC1404_ \ desc += "Timeout Occurred" %define _DESC1405_ \ desc += "Unprocessed Message Discarded. When a new message is received while the\n"\ desc += "acceptance filtering process for the previously received message has not yet\n"\ desc += "completed, this message is discarded." %define _DESC1406_ \ desc += "Timestamp Wraparound" %define _DESC1407_ \ desc += "Tx Event FIFO Event Lost" %define _DESC1408_ \ desc += "Tx Event FIFO Full" %define _DESC1409_ \ desc += "Tx Event FIFO Watermark Reached" %define _DESC1410_ \ desc += "Tx Event FIDO New Entry" %define _DESC1411_ \ desc += "Tx FIFO Empty" %define _DESC1412_ \ desc += "Transmission Cancellation Finished" %define _DESC1413_ \ desc += "Transmission Completed" %define _DESC1414_ \ desc += "High Priority Message" %define _DESC1415_ \ desc += "Rx FIFO 1 Message Lost" %define _DESC1416_ \ desc += "Rx FIFO 1 Full" %define _DESC1417_ \ desc += "Rx FIFO 1 Watermark Reached" %define _DESC1418_ \ desc += "Rx FIFO 1 New Message" %define _DESC1419_ \ desc += "Rx FIFO 0 Message Lost" %define _DESC1420_ \ desc += "Rx FIFO 0 Full" %define _DESC1421_ \ desc += "Rx FIFO 0 Watermark Reached" %define _DESC1422_ \ desc += "Rx FIFO 0 New Message" %define _DESC1423_ \ desc += "Interrupt Enable Register. The settings in the Interrupt Enable register\n"\ desc += "determine which status changes in the Interrupt Register will be signaled on an\n"\ desc += "interrupt line" %define _DESC1424_ \ desc += "Stuff Error Interrupt Enable" %define _DESC1425_ \ desc += "Format Error Interrupt Enable" %define _DESC1426_ \ desc += "Acknowledge Error Interrupt Enable" %define _DESC1427_ \ desc += "CRC Error Interrupt Enable" %define _DESC1428_ \ desc += "Watchdog Interrupt Enable" %define _DESC1429_ \ desc += "Bus_Off Status Interrupt Enable" %define _DESC1430_ \ desc += "Warning Status Interrupt Enable" %define _DESC1431_ \ desc += "Error Passive Interrupt Enable" %define _DESC1432_ \ desc += "Error Logging Overflow Interrupt Enable" %define _DESC1433_ \ desc += "Bit Error Uncorrected Interrupt Enable" %define _DESC1434_ \ desc += "Bit Error Corrected Interrupt Enable" %define _DESC1435_ \ desc += "Timeout Occurred Interrupt Enable" %define _DESC1436_ \ desc += "Unprocessed Message Discarded Interrupt Enable" %define _DESC1437_ \ desc += "Timestamp Wraparound Interrupt Enable" %define _DESC1438_ \ desc += "Tx Event FIFO Event Lost Interrupt Enable" %define _DESC1439_ \ desc += "Tx Event FIFO Full Interrupt Enable" %define _DESC1440_ \ desc += "Tx Event FIFO Watermark Reached Interrupt Enable" %define _DESC1441_ \ desc += "Tx Event FIFO New Entry Interrupt Enable" %define _DESC1442_ \ desc += "Tx FIFO Empty Interrupt Enable" %define _DESC1443_ \ desc += "Transmission Cancellation Finished Interrupt Enable" %define _DESC1444_ \ desc += "Transmission Completed Interrupt Enable" %define _DESC1445_ \ desc += "High Priority Message Interrupt Enable" %define _DESC1446_ \ desc += "Rx FIFO 1 Message Lost Interrupt Enable" %define _DESC1447_ \ desc += "Rx FIFO 1 Full Interrupt Enable" %define _DESC1448_ \ desc += "Rx FIFO 1 Watermark Reached Interrupt Enable" %define _DESC1449_ \ desc += "Rx FIFO 1 New Message Interrupt Enable" %define _DESC1450_ \ desc += "Rx FIFO 0 Message Lost Interrupt Enable" %define _DESC1451_ \ desc += "Rx FIFO 0 Full Interrupt Enable" %define _DESC1452_ \ desc += "Rx FIFO 0 Watermark Reached Interrupt Enable" %define _DESC1453_ \ desc += "Rx FIFO 0 New Message Interrupt Enable" %define _DESC1454_ \ desc += "Interrupt Line Select Register. The Interrupt Line Select register assigns an\n"\ desc += "interrupt generated by a specific interrupt flag from the Interrupt Register to\n"\ desc += "one of the two module interrupt lines." %define _DESC1455_ \ desc += "Stuff Error Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1456_ \ desc += "Format Error Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1457_ \ desc += "Acknowledge Error Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1458_ \ desc += "Bit Error Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1459_ \ desc += "CRC Error Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1460_ \ desc += "Watchdog Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1461_ \ desc += "Bus_Off Status Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1462_ \ desc += "Warning Status Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1463_ \ desc += "Error Passive Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1464_ \ desc += "Error Logging Overflow Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1465_ \ desc += "Bit Error Uncorrected Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1466_ \ desc += "Bit Error Corrected Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1467_ \ desc += "Timeout Occurred Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1468_ \ desc += "UMDL: Unprocessed Message Discarded Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1469_ \ desc += "TSWL: Timestamp Wraparound Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1470_ \ desc += "Tx Event FIFO Event Lost Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1471_ \ desc += "Tx Event FIFO Full Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1472_ \ desc += "Tx Event FIFO Watermark Reached Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1473_ \ desc += "Tx Event FIFO New Entry Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1474_ \ desc += "Tx FIFO Empty Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1475_ \ desc += "Transmission Cancellation Finished Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1476_ \ desc += "Transmission Completed Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1477_ \ desc += "High Priority Message Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1478_ \ desc += "Rx FIFO 1 Message Lost Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1479_ \ desc += "Rx FIFO 1 Full Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1480_ \ desc += "Rx FIFO 1 Watermark Reached Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1481_ \ desc += "Rx FIFO 1 New Message Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1482_ \ desc += "Rx FIFO 0 Message Lost Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1483_ \ desc += "Rx FIFO 0 Full Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1484_ \ desc += "Rx FIFO 0 Watermark Reached Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1485_ \ desc += "Rx FIFO 0 New Message Interrupt Line\n\n"\ desc += "0 Interrupt assigned to interrupt line MCAN INT0\n\n"\ desc += "1 Interrupt assigned to interrupt line MCAN INT1" %define _DESC1486_ \ desc += "Interrupt Line Enable Register. Each of the two interrupt lines to the CPU can\n"\ desc += "be enabled /disabled separately by programming bits EINT0 and EINT1." %define _DESC1487_ \ desc += "Enable Interrupt Line 1" %define _DESC1488_ \ desc += "Enable Interrupt Line 0" %define _DESC1489_ \ desc += "Global Filter Configuration Register. Global settings for Message ID filtering.\n"\ desc += "The Global Filter Configuration controls the filter path for standard and\n"\ desc += "extended messages as described in the Message RAM and Extended message ID\n"\ desc += "filtering .\n\n"\ desc += "Protected write (P) register which means that the write access to this register\n"\ desc += "is possible only when the CCCR[CCE] and CCCR[INIT] register fields are set to\n"\ desc += "'1'." %define _DESC1490_ \ desc += "Accept Non-matching Frames Standard. Defines how received messages with 11-bit\n"\ desc += "IDs that do not match any element of the filter list are\n\n"\ desc += "treated.\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1491_ \ desc += "ANFE[1:0]: Accept Non-matching Frames Extended\n\n"\ desc += "Defines how received messages with 29-bit IDs that do not match any element of\n"\ desc += "the filter list are\n\n"\ desc += "treated.\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1492_ \ desc += "Reject Remote Frames Standard\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1493_ \ desc += "Reject Remote Frames Extended\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1494_ \ desc += "Standard ID Filter Configuration Register. Settings for 11-bit standard Message\n"\ desc += "ID filtering. The Standard ID Filter Configuration controls the filter path for\n"\ desc += "the standard messages.\n\n"\ desc += "Protected write (P) register which means that the write access to this register\n"\ desc += "is possible only when the CCCR[CCE] and CCCR[INIT] register fields are set to\n"\ desc += "'1'." %define _DESC1495_ \ desc += "List Size Standard\n\n"\ desc += "0 No standard Message ID filter\n\n"\ desc += "1-128 Number of standard Message ID filter elements\n\n"\ desc += ">128 Values greater than 128 are interpreted as 128\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1496_ \ desc += "Filter List Standard Start Address\n\n"\ desc += "Start address of standard Message ID filter list (32-bit word address, see \n"\ desc += "Message RAM .\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1497_ \ desc += "Extended ID Filter Configuration Register. Settings for 29-bit extended Message\n"\ desc += "ID filtering. The Extended ID Filter Configuration controls the filter path for\n"\ desc += "the standard messages.\n\n"\ desc += "Protected write (P) register which means that the write access to this register\n"\ desc += "is possible only when the CCCR[CCE] and CCCR[INIT] register fields are set to\n"\ desc += "'1'." %define _DESC1498_ \ desc += "List Size Extended\n\n"\ desc += "0 No extended Message ID filter\n\n"\ desc += "1-64 Number of extended Message ID filter elements\n\n"\ desc += ">64 Values greater than 64 are interpreted as 64\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1499_ \ desc += "Filter List Extended Start Address\n\n"\ desc += "Start address of extended Message ID filter list (32-bit word address, see \n"\ desc += "Message RAM ).\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1500_ \ desc += "Extended ID and Mask Register. " %define _DESC1501_ \ desc += "Extended ID Mask\n\n"\ desc += "For acceptance filtering of extended frames the Extended ID AND Mask is ANDed\n"\ desc += "with the Message ID of a received frame. Intended for masking of 29-bit IDs in\n"\ desc += "SAE J1939. With the reset value of all\n\n"\ desc += "bits set to one the mask is not active.\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1502_ \ desc += "High Priority Message Status Register. This register is updated every time a\n"\ desc += "Message ID filter element configured to generate a priority event matches. This\n"\ desc += "can be used to monitor the status of incoming high priority messages and to\n"\ desc += "enable fast access to these messages." %define _DESC1503_ \ desc += "Filter List\n\n"\ desc += "Indicates the filter list of the matching filter element." %define _DESC1504_ \ desc += "Filter Index\n\n"\ desc += "Index of matching filter element. Range is 0 to SIDFC[LSS] - 1 resp. XIDFC[LSE]\n"\ desc += "- 1." %define _DESC1505_ \ desc += "Message Storage Indicator" %define _DESC1506_ \ desc += "Buffer Index\n\n"\ desc += "Index of Rx FIFO element to which the message was stored. Only valid when\n"\ desc += "MSI[1] = '1'." %define _DESC1507_ \ desc += "New Data 1 Register. " %define _DESC1508_ \ desc += "The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set\n"\ desc += "when the respective Rx Buffer has been updated from a received frame. The flags\n"\ desc += "remain set until the Host clears them. A flag is cleared by writing a '1' to\n"\ desc += "the corresponding bit position. Writing a '0' has no effect. A hard reset will\n"\ desc += "clear the register." %define _DESC1509_ \ desc += "New Data 2 Register. " %define _DESC1510_ \ desc += "The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set\n"\ desc += "when the respective Rx Buffer has been updated from a received frame. The flags\n"\ desc += "remain set until the Host clears them. A flag is cleared by writing a '1' to\n"\ desc += "the corresponding bit position. Writing a '0' has no effect. A hard reset will\n"\ desc += "clear the register." %define _DESC1511_ \ desc += "Rx FIFO 0 Configuration. Protected write (P) register which means that the\n"\ desc += "write access to this register is possible only when the CCCR[CCE] and\n"\ desc += "CCCR[INIT] register fields are set to '1'." %define _DESC1512_ \ desc += "Rx FIFO 0 Watermark\n\n"\ desc += "0 Watermark interrupt disabled\n\n"\ desc += "1-64 Level for Rx FIFO 0 watermark interrupt (IR[RF0W])\n\n"\ desc += ">64 Watermark interrupt disabled\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1513_ \ desc += "Rx FIFO 0 Size\n\n"\ desc += "0 No Rx FIFO 0\n\n"\ desc += "1-64 Number of Rx FIFO 0 elements\n\n"\ desc += ">64 Values greater than 64 are interpreted as 64\n\n"\ desc += "The Rx FIFO 0 elements are indexed from 0 to F0S-1\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1514_ \ desc += "Rx FIFO 0 Start Address\n\n"\ desc += "Start address of Rx FIFO 0 in Message RAM (32-bit word address, Message RAM\n"\ desc += ").\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1515_ \ desc += "Rx FIFO 0 Status Register. " %define _DESC1516_ \ desc += "Rx FIFO 0 Message Lost\n\n"\ desc += "This bit is a copy of interrupt flag IR[RF0L]. When IR[RF0L] is reset, this bit\n"\ desc += "is also reset." %define _DESC1517_ \ desc += "Rx FIFO 0 write index pointer, range 0 to 63" %define _DESC1518_ \ desc += "Rx FIFO 0 Get Index\n\n"\ desc += "Rx FIFO 0 read index pointer, range 0 to 63." %define _DESC1519_ \ desc += "Rx FIFO 0 Fill Level\n\n"\ desc += "Number of elements stored in Rx FIFO 0, range 0 to 64." %define _DESC1520_ \ desc += "Rx FIFO 0 Acknowledge Register. " %define _DESC1521_ \ desc += "Rx FIFO 0 Acknowledge Index. After the Host has read a message or a sequence of\n"\ desc += "messages from Rx FIFO 0 it has to write the buffer index of the last element\n"\ desc += "read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S[F0GI]\n"\ desc += "to F0AI + 1 and update the FIFO 0 Fill Level RXF0S[F0FL]." %define _DESC1522_ \ desc += "Rx Buffer Configuration Register. " %define _DESC1523_ \ desc += "Configures the start address of the Rx Buffers section in the Message RAM\n"\ desc += "(32-bit word address). Also used to reference debug messages A,B,C. Protected\n"\ desc += "write (P) bit(s) which means that the write access to this field is possible\n"\ desc += "only when the CCCR[CCE] and CCCR[INIT] register fields are set to '1'." %define _DESC1524_ \ desc += "Rx FIFO 1 Configuration Register. Protected write (P) register which means that\n"\ desc += "the write access to this register is possible only when the CCCR[CCE] and\n"\ desc += "CCCR[INIT] register fields are set to '1'." %define _DESC1525_ \ desc += "Rx FIFO 1 Watermark\n\n"\ desc += "0 Watermark interrupt disabled\n\n"\ desc += "1-64 Level for Rx FIFO 1 watermark interrupt IR[RF1W]\n\n"\ desc += ">64 Watermark interrupt disabled\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1526_ \ desc += "F1S [6:0]. Rx FIFO 1 Size\n\n"\ desc += "0 No Rx FIFO 1\n\n"\ desc += "1-64 Number of Rx FIFO 1 elements\n\n"\ desc += ">64 Values greater than 64 are interpreted as 64\n\n"\ desc += "The Rx FIFO 1 elements are indexed from 0 to F1S - 1\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1527_ \ desc += "Rx FIFO 1 Start Address\n\n"\ desc += "Start address of Rx FIFO 1 in Message RAM (32-bit word address, see Message\n"\ desc += "RAM ).\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1528_ \ desc += "Rx FIFO 1 Status Register. " %define _DESC1529_ \ desc += "Debug Message Status" %define _DESC1530_ \ desc += "Rx FIFO 1 Message Lost. This bit is a copy of interrupt flag IR[RF1L]. When\n"\ desc += "IR[RF1L] is reset, this bit is also reset." %define _DESC1531_ \ desc += "Rx FIFO 1 write index pointer, range 0 to 63." %define _DESC1532_ \ desc += "Rx FIFO 1 Get Index. Rx FIFO 1 read index pointer, range 0 to 63." %define _DESC1533_ \ desc += "Rx FIFO 1 Fill Level. Number of elements stored in Rx FIFO 1, range 0 to 64." %define _DESC1534_ \ desc += "Rx FIFO 1 Acknowledge Register. " %define _DESC1535_ \ desc += "Rx FIFO 1 Acknowledge Index. After the Host has read a message or a sequence of\n"\ desc += "messages from Rx FIFO 1 it has to write the buffer index of the last element\n"\ desc += "read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S[F1GI]\n"\ desc += "to F1AI + 1 and update the FIFO 1 Fill Level RXF1S[F1FL]." %define _DESC1536_ \ desc += "Tx Buffer Configuration Register. Be aware that the sum of TFQS and NDTB may be\n"\ desc += "not greater than 32. There is no check for erroneous configurations. The Tx\n"\ desc += "Buffers section in the Message RAM starts with the dedicated Tx Buffers. \n"\ desc += "Protected write (P) register which means that the write access to this register\n"\ desc += "is possible only when the CCCR[CCE] and CCCR[INIT] register fields are set to\n"\ desc += "'1'." %define _DESC1537_ \ desc += "Tx FIFO/Queue Mode\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1538_ \ desc += "Tx FIFO/Queue Size\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1539_ \ desc += "Number of Dedicated Transmit Buffers\n\n"\ desc += "0 No Dedicated Tx Buffers\n\n"\ desc += "1-32 Number of Dedicated Tx Buffers\n\n"\ desc += ">32 Values greater than 32 are interpreted as 32\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1540_ \ desc += "Tx Buffers Start Address\n\n"\ desc += "Start address of Tx Buffers section in Message RAM (32-bit word address, see \n"\ desc += "Message RAM ).\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1541_ \ desc += "Tx FIFO/Queue Status Register. In case of mixed configurations where dedicated\n"\ desc += "Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices\n"\ desc += "indicate the number of the Tx Buffer starting with the first dedicated Tx\n"\ desc += "Buffers. Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO\n"\ desc += "of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO." %define _DESC1542_ \ desc += "Tx FIFO/Queue Full" %define _DESC1543_ \ desc += "Tx FIFO/Queue Put Index. Tx FIFO/Queue write index pointer, range 0 to 31." %define _DESC1544_ \ desc += "Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation\n"\ desc += "is configured (TXBC[TFQM] = '1')." %define _DESC1545_ \ desc += "Tx FIFO Free Level. Number of consecutive free Tx FIFO elements , range 0 to\n"\ desc += "32. Read as zero when Tx Queue operation is configured (TXBC[TFQM] = '1')" %define _DESC1546_ \ desc += "Tx Buffer Request Pending Register. TXBRP bits which are set while a Tx scan is\n"\ desc += "in progress are not considered during this particular Tx scan. In case a\n"\ desc += "cancellation is requested for such a Tx Buffer, this Add Request is cancelled\n"\ desc += "immediately, the corresponding TXBRP bit is reset." %define _DESC1547_ \ desc += "Each Tx Buffer has its own Transmission Request Pending bit. The bits are set\n"\ desc += "via register TXBAR. The bits are reset after a requested transmission has\n"\ desc += "completed or has been cancelled via register TXBCR.\n\n"\ desc += "TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP\n"\ desc += "bit has been set, a Tx scan (see Tx handling ) is started to check for the\n"\ desc += "pending Tx request with the highest priority (Tx Buffer with lowest Message\n"\ desc += "ID).\n\n"\ desc += "A cancellation request resets the corresponding transmission request pending\n"\ desc += "bit of register TXBRP. In case a transmission has already been started when a\n"\ desc += "cancellation is requested, this is done at the end of the transmission,\n"\ desc += "regardless whether the transmission was successful or not. The cancellation\n"\ desc += "request bits are reset directly after the corresponding TXBRP bit has been\n"\ desc += "reset.\n\n"\ desc += "After a cancellation has been requested, a finished cancellation is signalled\n"\ desc += "via TXBCF\n\n"\ desc += "after successful transmission together with the corresponding TXBTO bit when\n"\ desc += "the transmission has not yet been started at the point of cancellation when\n"\ desc += "the transmission has been aborted due to lost arbitration when an error\n"\ desc += "occurred during frame transmission In DAR mode all transmissions are\n"\ desc += "automatically cancelled if they are not successful. The corresponding TXBCF bit\n"\ desc += "is set for all unsuccessful transmissions." %define _DESC1548_ \ desc += "Tx Buffer Add Request register. If an add request is applied for a Tx Buffer\n"\ desc += "with pending transmission request (corresponding TXBRP bit already set), this\n"\ desc += "add request is ignored. " %define _DESC1549_ \ desc += "Each Tx Buffer has its own Add Request bit. Writing a '1' will set the\n"\ desc += "corresponding Add Request bit; writing a '0' has no impact. This enables the\n"\ desc += "Host to set transmission requests for multiple Tx Buffers with one write to\n"\ desc += "TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. When\n"\ desc += "no Tx scan is running, the bits are reset immediately, else the bits remain set\n"\ desc += "until the Tx scan process has completed." %define _DESC1550_ \ desc += "Tx Buffer Cancellation Request register. " %define _DESC1551_ \ desc += "Each Tx Buffer has its own Cancellation Request bit. Writing a '1' will set the\n"\ desc += "corresponding Cancellation Request bit; writing a '0' has no impact. This\n"\ desc += "enables the Host to set cancellation requests for multiple Tx Buffers with one\n"\ desc += "write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via\n"\ desc += "TXBC. The bits remain set until the corresponding bit of TXBRP is reset." %define _DESC1552_ \ desc += "Tx Buffer Transmission Occurred register. " %define _DESC1553_ \ desc += "Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the\n"\ desc += "corresponding TXBRP bit is cleared after a successful transmission. The bits\n"\ desc += "are reset when a new transmission is requested by writing a '1' to the\n"\ desc += "corresponding bit of register TXBAR." %define _DESC1554_ \ desc += "Tx Buffer Cancellation Finished register. " %define _DESC1555_ \ desc += "\n\n"\ desc += "Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the\n"\ desc += "corresponding TXBRP bit is cleared after a cancellation was requested via\n"\ desc += "TXBCR. In case the corresponding TXBRP bit was not set at the point of\n"\ desc += "cancellation, CF is set immediately. The bits are reset when a new transmission\n"\ desc += "is requested by writing a '1' to the corresponding bit of register TXBAR." %define _DESC1556_ \ desc += "Tx Buffer Transmission Interrupt Enable register. " %define _DESC1557_ \ desc += "Transmission Interrupt Enable.\n\n"\ desc += "Each Tx Buffer has its own Transmission Interrupt Enable bit." %define _DESC1558_ \ desc += "Tx Buffer Cancellation Finished Interrupt Enable register. " %define _DESC1559_ \ desc += "Cancellation Finished Interrupt Enable.\n\n"\ desc += "Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." %define _DESC1560_ \ desc += "Tx Event FIFO Configuration Register. Protected write (P) register which means\n"\ desc += "that the write access to this register is possible only when the CCCR[CCE] and\n"\ desc += "CCCR[INIT] register fields are set to '1'." %define _DESC1561_ \ desc += "Event FIFO Watermark.\n\n"\ desc += "0 Watermark interrupt disabled\n\n"\ desc += "1-32 Level for Tx Event FIFO watermark interrupt (IR[TEFW])\n\n"\ desc += ">32 Watermark interrupt disabled\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1562_ \ desc += "Event FIFO Size.\n\n"\ desc += "0 Tx Event FIFO disabled\n\n"\ desc += "1-32 Number of Tx Event FIFO elements\n\n"\ desc += ">32 Values greater than 32 are interpreted as 32\n\n"\ desc += "The Tx Event FIFO elements are indexed from 0 to EFS - 1\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1563_ \ desc += "Event FIFO Start Address.\n\n"\ desc += "Start address of Tx Event FIFO in Message RAM (32-bit word address, Message\n"\ desc += "RAM ).\n\n"\ desc += "Protected write (P) bit(s) which means that write access by the bit(s) is\n"\ desc += "possible only when the bit 1 [CCE] CCCR[INIT] register fields are set to '1'." %define _DESC1564_ \ desc += "Tx Event FIFO Status register. " %define _DESC1565_ \ desc += "Tx Event FIFO Element Lost. This bit is a copy of interrupt flag IR[TEFL]. When\n"\ desc += "IR[TEFL] is reset, this bit is also reset." %define _DESC1566_ \ desc += "Event FIFO Full." %define _DESC1567_ \ desc += "Event FIFO Put Index. Tx Event FIFO write index pointer, range 0 to 31." %define _DESC1568_ \ desc += "Event FIFO Get Index.\n\n"\ desc += "Tx Event FIFO read index pointer, range 0 to 31." %define _DESC1569_ \ desc += "Event FIFO Fill Level.\n\n"\ desc += "Number of elements stored in Tx Event FIFO, range 0 to 32." %define _DESC1570_ \ desc += "Tx Event FIFO Acknowledge register. " %define _DESC1571_ \ desc += "Event FIFO Acknowledge Index. After the Host has read an element or a sequence\n"\ desc += "of elements from the Tx Event FIFO it has to write the index of the last\n"\ desc += "element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get\n"\ desc += "Index TXEFS[EFGI] to EFAI + 1 and update the FIFO 0 Fill Level TXEFS[ EFFL]." %define _DESC1572_ \ desc += "Life Cycle Status Register. The Life Cycle Status Register reflects the\n"\ desc += "production status and censorship status of the device. It is possible to mature\n"\ desc += "the device (move the device life cycle forward), but never to revert the life\n"\ desc += "cycle to an earlier state.\n\n"\ desc += "Reset value depends on life cycle status.\n\n"\ desc += "The reset value for the LCSTAT register LIFE field is defined by a DCF client\n"\ desc += "that is automatically pre-loaded during reset from data in Flash UTEST region.\n"\ desc += "The DCF client is 0xFF by default and configured such that bits can only be\n"\ desc += "written from '1' to '0'. Subsequent DCF records can move the LIFE field through\n"\ desc += "the Lifecycle states.\n\n"\ desc += "The effects of life cycle on security is described in Life cycle and security\n"\ desc += ".\n\n"\ desc += "." %define _DESC1573_ \ desc += "This field indicates the System Censoring Status.\n\n"\ desc += "The bit can be set (or cleared) via DCF Record in UTest Flash.\n\n"\ desc += "See section Censoring and uncensoring the device ." %define _DESC1574_ \ desc += "This field indicates whether the device has been temporarily uncensored.\n"\ desc += "Successful transmission of the JTAG password sets this bit to '1', otherwise it\n"\ desc += "will be 0.\n\n"\ desc += "Unsuccessful transmission clears this bit.\n\n"\ desc += "" %define _DESC1575_ \ desc += "This field shows the value of the life cycle DCF Record. The field can not be\n"\ desc += "written directly, but is determined by the Life cycle records which have been\n"\ desc += "written into the UTest Flash.\n\n"\ desc += "011 is Customer Delivery\n\n"\ desc += "010 is OEM Production\n\n"\ desc += "111 is In Field\n\n"\ desc += "000 is Failure Analysis mode\n\n"\ desc += "\n\n"\ desc += "" %define _DESC1576_ \ desc += "Challenge Selector Register. This register determines which password group is\n"\ desc += "challenged via the Challenge Input Register. When a master accesses this\n"\ desc += "register, the PASS module stores the number of the master in the LOCK3_PGn\n"\ desc += "register of the selected passgroup and sets the PGL bit in that register.\n\n"\ desc += "The ID of the accessing master sets the CMST field of the Challenge Status\n"\ desc += "register.\n\n"\ desc += "." %define _DESC1577_ \ desc += "Password Group to unlock" %define _DESC1578_ \ desc += "Challenge Status Register. This register provides status information for the\n"\ desc += "password challenge. Only the master shown in this register can access the CINn\n"\ desc += "registers - access by other masters result in a comparison fail, regardless of\n"\ desc += "the values written.\n\n"\ desc += "." %define _DESC1579_ \ desc += "ID of the master which has last written the CHSEL register" %define _DESC1580_ \ desc += "Challenge Input Register. This register is used to provide the Challenge word n\n"\ desc += "for a password group as selected by the Challenge Selector Register.\n\n"\ desc += "After programming the Challenge Selector Register, the password challenge needs\n"\ desc += "to be written with eight 32-bit writes from CIN0 to CIN7 in that order . The\n"\ desc += "most significant 32 bits of the password challenge must be written to CIN0 .\n"\ desc += "Once CIN7 is written, the password is compared . The write access only\n"\ desc += "completes after the comparison has been executed .\n\n"\ desc += "All accesses to these registers need to be made by the bus master that wrote\n"\ desc += "the CHSEL register previously. If another master writes any of the CIN\n"\ desc += "registers before the original master has written CIN7, the comparison fails.\n\n"\ desc += "" %define _DESC1581_ \ desc += "32 bits of the 256-bit password challenge. Only 32-bit writes may be used." %define _DESC1582_ \ desc += "Lock 0 Status Register. Each Password Group has one Lock 0 Status register.\n"\ desc += "This register shows the current lock state for the Flash blocks. Each time a\n"\ desc += "password group is unlocked the register becomes writable . For additional\n"\ desc += "details of the LOCK bits, refer to the Flash memory description.\n\n"\ desc += "The LOCK bits do not come into effect before the life cycle has matured to OEM\n"\ desc += "Production or older.\n\n"\ desc += "Lock registers can only be accessed with 32-bit operations. The initial value\n"\ desc += "of the lock bits is set via DCF records stored in UTEST Flash block and copied\n"\ desc += "over during reset. The default value before any DCF record is written is '1',\n"\ desc += "which indicates a block is locked. If no DCF records have been written to\n"\ desc += "change the lock state, the bits will reset to '1'.\n\n"\ desc += "During the Customer Delivery life cycle, the user must program a valid password\n"\ desc += "or a DCF record that writes to this register to unprotect the UTEST for each\n"\ desc += "password group in order to prevent permanent and irreversible locking of Fflash\n"\ desc += "blocks.\n\n"\ desc += "Failure to program valid passwords or DCF records for all password groups\n"\ desc += "before the life cycle mature to OEM Production renders the part unusable. Once\n"\ desc += "a password group is unlocked, software can set or clear any of the lock bits in\n"\ desc += "the group, by writing to the registers.\n\n"\ desc += "The resulting lock status of a Flash block is determined by the combination of\n"\ desc += "the lock bits of all password groups. If a block is locked in multiple groups,\n"\ desc += "then all lock bits for the block need to be cleared before program and erase is\n"\ desc += "possible.\n\n"\ desc += "However, unless the life cycle is older than OEM Production, the Flash blocks\n"\ desc += "are always unlocked, regardless of the values in the password groups.\n\n"\ desc += "When Production Disable register bit[1](BAF Plock Hardware Interlock enable) is\n"\ desc += "asserted and life cycle is In Field, then the external signal is OR'ed with\n"\ desc += "BAF_plock(low_lock[0]) of LOCK0_PGx.\n\n"\ desc += "The BAF_plock signal can only be deasserted when external BAF PLock is\n"\ desc += "deasserted and correct password is driven to deassert BAF_plock(low_lock[0]) of\n"\ desc += "LOCK0_PGx.\n\n"\ desc += ".\n\n"\ desc += "LOCK0_PG n register functions are as shown in this table." %define _DESC1583_ \ desc += "UTest NVM Lock. This bit is used to lock the UTest NVM block from programs\n"\ desc += "(erase protection not needed since UTest NVM is OTP and not erasable)." %define _DESC1584_ \ desc += "Alternate Interface UTest NVM Lock. This bit is used to lock the UTest NVM\n"\ desc += "block from programs on the alternate interface (erase protection not needed\n"\ desc += "since UTest NVM is OTP and not erasable)." %define _DESC1585_ \ desc += "Low Block Lock. A value of 1 in a bit of the lock register signifies that the\n"\ desc += "corresponding block is locked for program and erase." %define _DESC1586_ \ desc += "Mid Block Lock. A value of 1 in a bit of the lock register signifies that the\n"\ desc += "corresponding block is locked for program and erase." %define _DESC1587_ \ desc += "Lock 1 Status Register. Each Password Group has one Lock 1 Status Register.\n"\ desc += "This register shows the current lock state for the Flash blocks. Each time a\n"\ desc += "password group is unlocked, the register becomes writable . For additional\n"\ desc += "details of the LOCK bits, refer to the Flash description.\n\n"\ desc += "The LOCK bits do not come into effect before the life cycle matures to OEM\n"\ desc += "Production or older.\n\n"\ desc += "Lock registers can only be accessed with 32-bit operations. The initial value\n"\ desc += "of the lock bits is set via DCF records stored in UTEST Flash block and copied\n"\ desc += "over during reset . The default value before any DCF record is written is '1',\n"\ desc += "which indicates a block is locked. If no DCF records have been written to\n"\ desc += "change the lock state, the bits will reset to '1'.\n\n"\ desc += "During the Customer Delivery life cycle, the user must program a valid password\n"\ desc += "or a DCF record that writes this register to unprotect the UTEST for each\n"\ desc += "password group to prevent permanent and irreversible locking of Flash blocks.\n\n"\ desc += "Failure to program valid passwords or DCF records for all password groups\n"\ desc += "before the life cycle matures to OEM Production renders the part unusable.\n"\ desc += "However, additional DCF Records can be written to UTEST to change the initial\n"\ desc += "value of this register. Once a password group is unlocked, software can set or\n"\ desc += "clear any of the lock bits in the group by writing to the registers.\n\n"\ desc += "The resulting lock status of a Flash block is determined by the combination of\n"\ desc += "the lock bits of all password groups. If a block is locked in multiple groups,\n"\ desc += "then all lock bits for the block need to be cleared before program and erase is\n"\ desc += "possible.\n\n"\ desc += "However, unless the life cycle is older than OEM Production, the Flash blocks\n"\ desc += "are always unlocked, regardless of the values in the password groups.\n\n"\ desc += ".\n\n"\ desc += "LOCK1_PG n register functions are as shown in this table." %define _DESC1588_ \ desc += "High Block Lock. A value of 1 in a bit of the lock register signifies that the\n"\ desc += "corresponding block is locked for program and erase." %define _DESC1589_ \ desc += "Lock 2 Status Register. Each Password Group has one Lock 2 Status Register.\n"\ desc += "This register shows the current lock state for the Flash blocks. Each time a\n"\ desc += "password group is unlocked, the register becomes writable . For additional\n"\ desc += "details of the LOCK bits, refer to the Flash description.\n\n"\ desc += "The LOCK bits do not come into effect before the life cycle is matured to OEM\n"\ desc += "Production or older.\n\n"\ desc += "The initial value of the lock bits is set via DCF records stored in UTEST Flash\n"\ desc += "block and copied over during reset . The default value before any DCF record is\n"\ desc += "written is '1', which indicates a block is locked. If no DCF records have been\n"\ desc += "written to change the lock state, the bit resets to '1'.\n\n"\ desc += "During the Customer Delivery life cycle the user must program a valid password\n"\ desc += "or a DCF record that writes this register to unprotect the UTEST for each\n"\ desc += "password group in order to prevent permanent and irreversible locking of fFlash\n"\ desc += "blocks.\n\n"\ desc += "Failure to program valid passwords or DCF records for all password groups\n"\ desc += "before the life cycle matures to OEM Production renders the part unusable.\n"\ desc += "However, additional DCF Records can be written to UTEST to change the initial\n"\ desc += "value of this register. Once a password group is unlocked, software can set or\n"\ desc += "clear any of the lock bits in the group, by writing to the registers.\n\n"\ desc += "The resulting lock status of a Flash block is determined by the combination of\n"\ desc += "the lock bits of all password groups. If a block is locked in multiple groups,\n"\ desc += "then all lock bits for the block need to be cleared before program and erase is\n"\ desc += "possible.\n\n"\ desc += "However, unless the life cycle is older than OEM Production, the Flash blocks\n"\ desc += "are always unlocked, regardless of the values in the password groups.\n\n"\ desc += "Lock registers can only be accessed with 32-bit operations. .\n\n"\ desc += "LOCK2_PG n register functions are as shown in this table." %define _DESC1590_ \ desc += "Lower 256KByte Block Lock. A value of 1 in a bit of the lock register signifies\n"\ desc += "that the corresponding block is locked for program and erase." %define _DESC1591_ \ desc += "Lock 3 Status Register. Each Password Group has one Lock 3 Status Register.\n"\ desc += "This register shows the current lock state for the Flash blocks. Each time a\n"\ desc += "password group is unlocked, the PGL bit is cleared and the Lock registers\n"\ desc += "become writable .\n\n"\ desc += "The LOCK bits do not come into effect before the life cycle matures to OEM\n"\ desc += "Production or older.\n\n"\ desc += "Lock registers can only be accessed with 32-bit operations. The initial value\n"\ desc += "of the lock bits is set via DCF records stored in UTEST Flash block and copied\n"\ desc += "over during reset . The default value before any DCF record is written is '1',\n"\ desc += "which indicates a block is locked. Reset value depends on life cycle. If life\n"\ desc += "cycle is Customer delivery or earlier, the value will be 0, otherwise 1. If no\n"\ desc += "DCF records have been written to change the lock state, the bit will reset to\n"\ desc += "'1'.\n\n"\ desc += "During the Customer Delivery life cycle, the user must program a valid password\n"\ desc += "or a DCF record that writes this register to unprotect the UTEST for each\n"\ desc += "password group in order to prevent permanent and irreversible locking of Flash\n"\ desc += "blocks.\n\n"\ desc += "Failure to program valid passwords or DCF records for all password groups\n"\ desc += "before the life cycle matures to OEM Production renders the part unusable.\n"\ desc += "However, additional DCF Records can be written to UTEST to change the initial\n"\ desc += "value of this register. Once a password group is unlocked, software can set or\n"\ desc += "clear any of the lock bits in the group, by writing to the registers.\n\n"\ desc += "The resulting lock status of a Flash block is determined by the combination of\n"\ desc += "the lock bits of all password groups. If a block is locked in multiple groups,\n"\ desc += "then all lock bits for the block need to be cleared before program and erase is\n"\ desc += "possible.\n\n"\ desc += "However, unless the life cycle is older than OEM Production, the Flash blocks\n"\ desc += "are always unlocked, regardless of the values in the password groups.\n\n"\ desc += "For operation of the region read protect feature, refer to table.\n\n"\ desc += "\n\n"\ desc += "Once a censored device enters the Failure Analysis life cycle, read protection\n"\ desc += "is active regardless whether the system is in debug mode or not. It is still\n"\ desc += "possible to unlock Flash regions with the correct passwords, however\n\n"\ desc += "\n\n"\ desc += "\n\n"\ desc += "\n\n"\ desc += "\n\n"\ desc += "." %define _DESC1592_ \ desc += "Password Group Lock.\n\n"\ desc += "This bit may be set in software to lock the password group, when the device is\n"\ desc += "older than Customer Delivery. Before that the value of the bit is always 0.\n\n"\ desc += "This bit can be cleared by writing a valid password to the Password Challenge\n"\ desc += "Input Registers." %define _DESC1593_ \ desc += "Debug Interface Lock." %define _DESC1594_ \ desc += "Master Only." %define _DESC1595_ \ desc += "Master Access.\n\n"\ desc += "Only the Master with this matching master ID can change the passgroup settings.\n"\ desc += "This field is loaded with the ID of the master which unlocked the passgroup\n"\ desc += "once the correct password is provided." %define _DESC1596_ \ desc += "Region 4 is protected." %define _DESC1597_ \ desc += "Region 3 is protected." %define _DESC1598_ \ desc += "Region 2 is protected." %define _DESC1599_ \ desc += "Region 1 is protected." %define _DESC1600_ \ desc += "Region 0 is protected." %define _DESC1601_ \ desc += "Upper 256 KB Block Lock. A value of 1 in a bit of the lock register signifies\n"\ desc += "that the corresponding block is locked for program and erase." %define _DESC1602_ \ desc += "Master Privilege Register A. Each MPR specifies eight 4-bit fields defining the\n"\ desc += "access privilege level associated with a bus master in the device to the\n"\ desc += "various peripherals. The register provides one field per bus master. Each\n"\ desc += "master is assigned depending on its logical master number. See\n"\ desc += "./McKinley_RM_Device_Configuration#Rcs37364 for details about the master\n"\ desc += "assignments to these registers.\n\n"\ desc += "The MPROT n field is defined as shown in #id_mprot_fields_2013-01-25_0926 and\n"\ desc += "#id_mprot_field_descriptions_2013-01-25_0927 .\n\n"\ desc += "MPROT n fields See reference manual for 'MPROT n field descriptions' table." %define _DESC1603_ \ desc += "Access privilege level associated with bus master 0" %define _DESC1604_ \ desc += "Access privilege level associated with bus master 1" %define _DESC1605_ \ desc += "Access privilege level associated with bus master 2" %define _DESC1606_ \ desc += "Access privilege level associated with bus master 3" %define _DESC1607_ \ desc += "Access privilege level associated with bus master 4" %define _DESC1608_ \ desc += "Access privilege level associated with bus master 5" %define _DESC1609_ \ desc += "Access privilege level associated with bus master 6" %define _DESC1610_ \ desc += "Access privilege level associated with bus master 7" %define _DESC1611_ \ desc += "Peripheral Access Control Register. Each of the on-platform peripherals has a\n"\ desc += "four-bit PACR n field which defines the access levels supported by the given\n"\ desc += "module. Eight PACR fields are grouped together to form a 32-bit PACR x\n"\ desc += "register.\n\n"\ desc += "The peripheral assignments to each PACR field are defined by the memory map\n"\ desc += "slot to which the peripherals are assigned. See ./McKinley_RM_MemMap#Rct51788\n"\ desc += "for the assignments for your particular device. If a peripheral is absent, the\n"\ desc += "corresponding PACR field is not implemented. Reads to the location return\n"\ desc += "zeroes, and writes are ignored.\n\n"\ desc += "Each PACR n field is defined as shown in #id_pacr_fields_2013-01-25_0932 .\n\n"\ desc += "PACR n fields The following table shows the top-level structure of the\n"\ desc += "PACRs.\n\n"\ desc += "[PACR memory map]:\n"\ desc += " Offset Register [0:3] [4:7] [8:11] [12:15] [16:19] [20:23] [24:27] [28:31]\n"\ desc += " ------ -------- ------ ------ ------ ------- ------- ------- ------- -------\n"\ desc += " 0x0100 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7\n"\ desc += " 0x0104 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15\n"\ desc += " 0x0108 PACRC PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23\n"\ desc += " 0x010C PACRD PACR24 PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31\n"\ desc += " 0x0110 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 PACR38 PACR39\n"\ desc += " 0x0114 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47\n"\ desc += " 0x0118 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55\n"\ desc += " 0x011C PACRH PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63\n"\ desc += "See reference manual for 'PACR n field descriptions' table. The reset value of\n"\ desc += "PACR0 is 0101b." %define _DESC1612_ \ desc += "Access level associated with module a" %define _DESC1613_ \ desc += "Access level associated with module b" %define _DESC1614_ \ desc += "Access level associated with module c" %define _DESC1615_ \ desc += "Access level associated with module d" %define _DESC1616_ \ desc += "Access level associated with module e" %define _DESC1617_ \ desc += "Access level associated with module f" %define _DESC1618_ \ desc += "Access level associated with module g" %define _DESC1619_ \ desc += "Access level associated with module h" %define _DESC1620_ \ desc += "Off-platform Peripheral Access Control Register. Each of the off-platform\n"\ desc += "peripherals has a four-bit OPACR n field which defines the access levels\n"\ desc += "supported by the given module. Eight OPACRs are grouped together to form a\n"\ desc += "32-bit OPACR x register.\n\n"\ desc += "The peripheral assignments to each OPACR field are defined by the memory map\n"\ desc += "slot to which the peripherals are assigned. See ./McKinley_RM_MemMap#Rct51788\n"\ desc += "for the assignments for your particular device. If a peripheral is absent, the\n"\ desc += "corresponding OPACR is not implemented. Reads to the location return zeroes and\n"\ desc += "writes are ignored.\n\n"\ desc += "The following table shows the top-level structure of the OPACR registers.\n\n"\ desc += "See reference manual for 'OPACR n field descriptions' table. See reference\n"\ desc += "manual for 'OPACR memory map' table. The OPACR n field is defined as in the\n"\ desc += "following figure.\n\n"\ desc += "OPACR n fields" %define _DESC1621_ \ desc += "Platform Flash Configuration Register 1. The PFlash Configuration Register 1\n"\ desc += "(PFCR1) is used to specify operation Port p0 of the flash memory controller.\n\n"\ desc += "." %define _DESC1622_ \ desc += "Port0 Master 15 Prefetch enable. This bit controls whether prefetching may be\n"\ desc += "triggered by AHB master 15. This bit is cleared by hardware reset." %define _DESC1623_ \ desc += "Port0 Master 14 Prefetch enable. This bit controls whether prefetching may be\n"\ desc += "triggered by AHB master 14. This bit is cleared by hardware reset." %define _DESC1624_ \ desc += "Port0 Master 13 Prefetch enable. This bit controls whether prefetching may be\n"\ desc += "triggered by AHB master 13. This bit is cleared by hardware reset." %define _DESC1625_ \ desc += "Port0 Master 12 Prefetch enable. This bit controls whether prefetching may be\n"\ desc += "triggered by AHB master 12. This bit is cleared by hardware reset." %define _DESC1626_ \ desc += "Port0 Master 11 Prefetch enable. This bit controls whether prefetching may be\n"\ desc += "triggered by AHB master 11. This bit is cleared by hardware reset." %define _DESC1627_ \ desc += "Port0 Master 10 Prefetch enable. This bit controls whether prefetching may be\n"\ desc += "triggered by AHB master 10. This bit is cleared by hardware reset." %define _DESC1628_ \ desc += "Port0 Master 9 Prefetch enable. This bit controls whether prefetching may be\n"\ desc += "triggered by AHB master 9. This bit is cleared by hardware reset." %define _DESC1629_ \ desc += "Port0 Master 8 Prefetch enable. This bit controls whether prefetching may be\n"\ desc += "triggered by AHB master 8. This bit is cleared by hardware reset." %define _DESC1630_ \ desc += "Port0 Master 7 Prefetch enable. This bit controls whether prefetching may be\n"\ desc += "triggered by AHB master 7. This bit is cleared by hardware reset." %define _DESC1631_ \ desc += "Port0 Master 6 Prefetch enable. This bit controls whether prefetching may be\n"\ desc += "triggered by AHB master 6. This bit is cleared by hardware reset." %define _DESC1632_ \ desc += "Port0 Master 5 Prefetch enable. This bit controls whether prefetching may be\n"\ desc += "triggered by AHB master 5. This bit is cleared by hardware reset." %define _DESC1633_ \ desc += "Port0 Master 4 Prefetch enable. This bit controls whether prefetching may be\n"\ desc += "triggered by AHB master 4. This bit is cleared by hardware reset." %define _DESC1634_ \ desc += "Port0 Master 3 Prefetch enable. This bit controls whether prefetching may be\n"\ desc += "triggered by AHB master 3. This bit is cleared by hardware reset." %define _DESC1635_ \ desc += "Port0 Master 2 Prefetch enable. This bit controls whether prefetching may be\n"\ desc += "triggered by AHB master 2. This bit is cleared by hardware reset." %define _DESC1636_ \ desc += "Port0 Master 1 Prefetch enable. This bit controls whether prefetching may be\n"\ desc += "triggered by AHB master 1. This bit is cleared by hardware reset." %define _DESC1637_ \ desc += "Port0 Master 0 Prefetch enable. This bit controls whether prefetching may be\n"\ desc += "triggered by AHB master 0. This bit is cleared by hardware reset." %define _DESC1638_ \ desc += "Read Wait State Control. This field controls the number of wait-states to be\n"\ desc += "added to the best-case flash array access time for reads. The best-case flash\n"\ desc += "array access time for reads is one cycle.\n\n"\ desc += "This field must be set to a value corresponding to the operating frequency of\n"\ desc += "the and the actual read access time of the . The required settings are\n"\ desc += "documented in the SoC specification. Higher operating frequencies require\n"\ desc += "non-zero settings for this field for proper flash operation.\n\n"\ desc += "Shown below are the maximum operating frequencies for legal RWSC settings based\n"\ desc += "on specified access times at 150 C. The integrator is strongly encourage to\n"\ desc += "verify these settings based on actual silicon results.\n\n"\ desc += "RWSC = 0: 0 MHz < fsys < 29.4 MHz\n\n"\ desc += "RWSC = 1: 29.4 MHz < fsys < 58.8 MHz\n\n"\ desc += "RWSC = 2: 58.8 MHz < fsys < 88.2 MHz\n\n"\ desc += "RWSC = 3: 88.2 MHz < fsys < 117.6 MHz\n\n"\ desc += "RWSC = 4: 117.6 MHz < fsys < 147.0 MHz\n\n"\ desc += "RWSC = 5: 147.0 MHz < fsys < 176.5 MHz\n\n"\ desc += "RWSC = 6: 176.5 MHz < fsys < 205.9 MHz\n\n"\ desc += "RWSC = 7: 205.9 MHz < fsys < 235.5 MHz\n\n"\ desc += "This field is set to 5'b00110 by hardware reset.\n\n"\ desc += "This field applies to the configuration of Port0 and Port1.\n\n"\ desc += "00000: No additional wait-states are added\n\n"\ desc += "00001: One additional wait-state is added\n\n"\ desc += "...\n\n"\ desc += "11111: Thirty-one additional wait-states are added" %define _DESC1639_ \ desc += "Port0 Data Prefetch Enable. This field enables or disables prefetching\n"\ desc += "initiated by a data read access. This field is cleared by hardware reset." %define _DESC1640_ \ desc += "This read-only field is reserved and always has the value zero." %define _DESC1641_ \ desc += "Port0 Instruction Prefetch Enable. This bit enables or disables prefetching\n"\ desc += "initiated by an instruction read access. This field is cleared by hardware\n"\ desc += "reset." %define _DESC1642_ \ desc += "Port0 PFlash Prefetch Limit. This field controls the prefetch algorithm used by\n"\ desc += "the prefetch controller. This field defines a limit on the maximum number of\n"\ desc += "sequential prefetches which will be attempted between buffer misses. In all\n"\ desc += "situations when enabled, only a single prefetch is initiated on each buffer\n"\ desc += "miss or hit.\n\n"\ desc += "This field is cleared by hardware reset.\n\n"\ desc += "00 No prefetching or buffering is performed.\n\n"\ desc += "01 The referenced line is prefetched on a buffer miss, that is, prefetch on\n"\ desc += "miss.\n\n"\ desc += "1x The referenced line is prefetched on a buffer miss, or the next sequential\n"\ desc += "line is prefetched on a buffer hit (if not already present), that is, prefetch\n"\ desc += "on miss or hit." %define _DESC1643_ \ desc += "Port0 PFlash Line Read Buffers Enable. This bit enables or disables line read\n"\ desc += "buffer hits. It is also used to invalidate the buffers. This bit can only be\n"\ desc += "updated while PFCR3[BAF_DIS] = 0. After execution of the boot code, as\n"\ desc += "indicated by PFCR3[BAF_DIS] = 1, this bit becomes read-only until the next\n"\ desc += "hardware reset." %define _DESC1644_ \ desc += "Platform Flash Configuration Register 3. ." %define _DESC1645_ \ desc += "Port0 Way Configuration. This field controls the configuration of the line\n"\ desc += "buffers for a given set across all four ways in the controller cache. The\n"\ desc += "indexed set can be organized as a 'pool' of available resources, or with a\n"\ desc += "fixed partition between instruction and data buffers.\n\n"\ desc += "In all cases, when a buffer miss occurs, the flash page is assigned a location\n"\ desc += "within the controller cache. Within the indexed set, the way is selected using\n"\ desc += "a least-recently-used replacement policy, and the entry is then marked as\n"\ desc += "most-recently-used for that set. If the flash access is for the next-sequential\n"\ desc += "line (prefetch), the buffer is not marked as most-recently-used until the given\n"\ desc += "address produces a buffer hit.\n\n"\ desc += "This field is initialized by hardware reset." %define _DESC1646_ \ desc += "BAF Disable. This field controls executable access to the BAF (Boot Assist\n"\ desc += "Flash) region of the flash, where the access type is detected by evaluating\n"\ desc += "{p0,p1}_hprot[0]. Once this field is set, attempted instruction access attempts\n"\ desc += "targeting the BAF region are aborted and terminated with a system bus error.\n\n"\ desc += "The affect of this field applies to system bus transfers through both, Port0\n"\ desc += "and Port1.\n\n"\ desc += "Data-type accesses to the BAF region are not affected by this field.\n\n"\ desc += "Once this field is set, it becomes a read-only field and can only be cleared by\n"\ desc += "hardware reset. Once this field is set, any subsequent write attempts to modify\n"\ desc += "this field are ignored with an error-free data transfer termination.\n\n"\ desc += "This field is initialized by hardware reset." %define _DESC1647_ \ desc += "Platform Flash Access Protection Register. The PFlash Access Protection\n"\ desc += "Register (PFAPR) is used to control read and write accesses to the flash\n"\ desc += "array.\n\n"\ desc += "." %define _DESC1648_ \ desc += "Master 0 Access Protection. This field controls whether read and write accesses\n"\ desc += "to the flash are allowed based on the master ID of a requesting master. These\n"\ desc += "fields are initialized by hardware reset." %define _DESC1649_ \ desc += "Master 1 Access Protection. This field controls whether read and write accesses\n"\ desc += "to the flash are allowed based on the master ID of a requesting master. These\n"\ desc += "fields are initialized by hardware reset." %define _DESC1650_ \ desc += "Master 2 Access Protection. This field controls whether read and write accesses\n"\ desc += "to the flash are allowed based on the master ID of a requesting master. These\n"\ desc += "fields are initialized by hardware reset." %define _DESC1651_ \ desc += "Master 3 Access Protection. This field controls whether read and write accesses\n"\ desc += "to the flash are allowed based on the master ID of a requesting master. These\n"\ desc += "fields are initialized by hardware reset." %define _DESC1652_ \ desc += "Master 4 Access Protection. This field controls whether read and write accesses\n"\ desc += "to the flash are allowed based on the master ID of a requesting master. These\n"\ desc += "fields are initialized by hardware reset." %define _DESC1653_ \ desc += "Master 5 Access Protection. This field controls whether read and write accesses\n"\ desc += "to the flash are allowed based on the master ID of a requesting master. These\n"\ desc += "fields are initialized by hardware reset." %define _DESC1654_ \ desc += "Master 6 Access Protection. This field controls whether read and write accesses\n"\ desc += "to the flash are allowed based on the master ID of a requesting master. These\n"\ desc += "fields are initialized by hardware reset." %define _DESC1655_ \ desc += "Master 7 Access Protection. This field controls whether read and write accesses\n"\ desc += "to the flash are allowed based on the master ID of a requesting master. These\n"\ desc += "fields are initialized by hardware reset." %define _DESC1656_ \ desc += "Master 8 Access Protection. This field controls whether read and write accesses\n"\ desc += "to the flash are allowed based on the master ID of a requesting master. These\n"\ desc += "fields are initialized by hardware reset." %define _DESC1657_ \ desc += "Master 9 Access Protection. This field controls whether read and write accesses\n"\ desc += "to the flash are allowed based on the master ID of a requesting master. These\n"\ desc += "fields are initialized by hardware reset." %define _DESC1658_ \ desc += "Master 10 Access Protection. This field controls whether read and write\n"\ desc += "accesses to the flash are allowed based on the master ID of a requesting\n"\ desc += "master. These fields are initialized by hardware reset." %define _DESC1659_ \ desc += "Master 11 Access Protection. This field controls whether read and write\n"\ desc += "accesses to the flash are allowed based on the master ID of a requesting\n"\ desc += "master. These fields are initialized by hardware reset." %define _DESC1660_ \ desc += "Master 12 Access Protection. This field controls whether read and write\n"\ desc += "accesses to the flash are allowed based on the master ID of a requesting\n"\ desc += "master. These fields are initialized by hardware reset." %define _DESC1661_ \ desc += "Master 13 Access Protection. This field controls whether read and write\n"\ desc += "accesses to the flash are allowed based on the master ID of a requesting\n"\ desc += "master. These fields are initialized by hardware reset." %define _DESC1662_ \ desc += "Master 14 Access Protection. This field controls whether read and write\n"\ desc += "accesses to the flash are allowed based on the master ID of a requesting\n"\ desc += "master. These fields are initialized by hardware reset." %define _DESC1663_ \ desc += "Master 15 Access Protection. This field controls whether read and write\n"\ desc += "accesses to the flash are allowed based on the master ID of a requesting\n"\ desc += "master. These fields are initialized by hardware reset." %define _DESC1664_ \ desc += "Platform Flash Calibration Remap Control Register. The PFCRCR is used to\n"\ desc += "globally enable/disable the calibration remap function.\n\n"\ desc += "." %define _DESC1665_ \ desc += "Safe Calibration. This bit facilitates the use of safety-critical calibration\n"\ desc += "data. When this bit is enabled, the flash memory controller is configured to\n"\ desc += "perform redundancy checking on the calibration remap function and reduce the\n"\ desc += "total number of potential calibration regions from 32 to 16. This field is\n"\ desc += "initialized by hardware reset." %define _DESC1666_ \ desc += "Instruction Remap. This bit enables calibration remapping evaluation on\n"\ desc += "instruction fetches. When PFCRCR[GRMEN] is disabled, this bit is ignored.\n\n"\ desc += "This field is initialized by hardware reset." %define _DESC1667_ \ desc += "Global Remap Enable. This bit globally enables or disables the calibration\n"\ desc += "remapping evaluation on system flash accesses.\n\n"\ desc += "This field is initialized by hardware reset." %define _DESC1668_ \ desc += "Platform Flash Calibration Remap Descriptor Enable Register. The PFlash\n"\ desc += "Calibration Remap Descriptor Enable Register (PFCRDE) is used to enable or\n"\ desc += "disable up to 32 calibration remap descriptors. Note there is also a global\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted in conjunction with the\n"\ desc += "individual CRDnEN flags to enable a given remap descriptor.\n\n"\ desc += "." %define _DESC1669_ \ desc += "Calibration Remap Descriptor 0 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1670_ \ desc += "Calibration Remap Descriptor 1 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1671_ \ desc += "Calibration Remap Descriptor 2 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1672_ \ desc += "Calibration Remap Descriptor 3 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1673_ \ desc += "Calibration Remap Descriptor 4 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1674_ \ desc += "Calibration Remap Descriptor 5 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1675_ \ desc += "Calibration Remap Descriptor 6 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1676_ \ desc += "Calibration Remap Descriptor 7 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1677_ \ desc += "Calibration Remap Descriptor 8 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1678_ \ desc += "Calibration Remap Descriptor 9 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1679_ \ desc += "Calibration Remap Descriptor 10 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1680_ \ desc += "Calibration Remap Descriptor 11 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1681_ \ desc += "Calibration Remap Descriptor 12 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1682_ \ desc += "Calibration Remap Descriptor 13 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1683_ \ desc += "Calibration Remap Descriptor 14 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1684_ \ desc += "Calibration Remap Descriptor 15 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1685_ \ desc += "Calibration Remap Descriptor 16 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1686_ \ desc += "Calibration Remap Descriptor 17 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1687_ \ desc += "Calibration Remap Descriptor 18 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1688_ \ desc += "Calibration Remap Descriptor 19 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1689_ \ desc += "Calibration Remap Descriptor 20 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1690_ \ desc += "Calibration Remap Descriptor 21 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1691_ \ desc += "Calibration Remap Descriptor 22 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1692_ \ desc += "Calibration Remap Descriptor 23 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1693_ \ desc += "Calibration Remap Descriptor 24 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1694_ \ desc += "Calibration Remap Descriptor 25 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1695_ \ desc += "Calibration Remap Descriptor 26 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1696_ \ desc += "Calibration Remap Descriptor 27 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1697_ \ desc += "Calibration Remap Descriptor 28 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1698_ \ desc += "Calibration Remap Descriptor 29 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1699_ \ desc += "Calibration Remap Descriptor 30 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1700_ \ desc += "Calibration Remap Descriptor 31 Enable. This bit indicates whether the\n"\ desc += "corresponding remap descriptor is valid. There is also a global calibration\n"\ desc += "remap enable (PFCRCR[GRMEN]) that also must be asserted to enable any remap\n"\ desc += "functionality. Any write to PFCRDn.Word{0,1,2} clears the corresponding\n"\ desc += "PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid. This bit\n"\ desc += "is cleared by power-on reset and unaffected by other types of system reset." %define _DESC1701_ \ desc += "Platform Flash Calibration Region Descriptor. Each 96-bit (12 byte) region\n"\ desc += "descriptor specifies an overlay region where a flash access can be remapped\n"\ desc += "during calibration and debug. The calibration remap descriptors are organized\n"\ desc += "sequentially as 128-bit (16 byte) structures in the Platform Flash Controller's\n"\ desc += "programming model.\n\n"\ desc += "The first word of the overlay region descriptor defines the 0-modulo-size\n"\ desc += "logical start (byte) address of the calibration remap region. It is software's\n"\ desc += "responsibility to guarantee the low-order bits of the address, as defined by\n"\ desc += "the remap descriptor size, are zeroed to enable the remap descriptor hit logic\n"\ desc += "to function correctly. Successful writes to this word clear the calibration\n"\ desc += "remap descriptor's valid bit.\n\n"\ desc += "The second word of the calibration region descriptor defines the 0-modulo-size\n"\ desc += "byte physical start (byte) address of the calibration remap region. The\n"\ desc += "contents of this word define the targeted destination overlay memory. It is\n"\ desc += "software's responsibility to guarantee the low-order bits of the address, as\n"\ desc += "defined by the remap descriptor size, are zeroed to enable the remap descriptor\n"\ desc += "hit logic to function correctly. Successful writes to this word clear the\n"\ desc += "calibration remap descriptor's valid bit.\n\n"\ desc += "The third word of the calibration region descriptor defines a per-master\n"\ desc += "calibration remap enable and the remap region size. For cacheable spaces being\n"\ desc += "remapped, the minimum region size is 32 bytes to match the flash page and cache\n"\ desc += "line sizes. Writes to this word clear the calibration remap descriptor's valid\n"\ desc += "bit.\n\n"\ desc += "The fourth word is unused.\n\n"\ desc += "." %define _DESC1702_ \ desc += "Logical Start Address. This field defines the most significant bits of the\n"\ desc += "0-modulo-size logical start address of the overlay remap region. It corresponds\n"\ desc += "to the logical system address which maps to the flash memory space. Any write\n"\ desc += "to PFCRDn.Word{0,1,2} clears the corresponding PFCRDE[CRDnEN] bit, leaving the\n"\ desc += "calibration remap descriptor invalid." %define _DESC1703_ \ desc += "Calibration Remap Descriptor n Physical Start Address - This field defines the\n"\ desc += "most significant bits of the 0-modulo-size physical start byte address of the\n"\ desc += "calibration remap descriptor. This address corresponds to the physical address\n"\ desc += "which maps to the destination calibration overlay memory. Any write to\n"\ desc += "PFCRDn.Word{0,1,2} clears the corresponding PFCRDE[CRDnEN] bit, leaving the\n"\ desc += "calibration remap descriptor invalid." %define _DESC1704_ \ desc += "Calibration Remap Descriptor n Master 0 Enable - These bits determine whether\n"\ desc += "calibration remapping is performed as defined by this descriptor based on the\n"\ desc += "logical master ID of the requesting AHB master.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, and\n"\ desc += "the M0EN field which corresponds to the requesting AHB master is asserted, then\n"\ desc += "calibration remapping is performed and data is fetched from the overlay RAM.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, but\n"\ desc += "the M0EN field which corresponds to the requesting AHB master is deasserted,\n"\ desc += "then calibration remapping is not performed and data is fetched from the\n"\ desc += "flash." %define _DESC1705_ \ desc += "Calibration Remap Descriptor n Master 1 Enable - These bits determine whether\n"\ desc += "calibration remapping is performed as defined by this descriptor based on the\n"\ desc += "logical master ID of the requesting AHB master.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, and\n"\ desc += "the M1EN field which corresponds to the requesting AHB master is asserted, then\n"\ desc += "calibration remapping is performed and data is fetched from the overlay RAM.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, but\n"\ desc += "the M1EN field which corresponds to the requesting AHB master is deasserted,\n"\ desc += "then calibration remapping is not performed and data is fetched from the\n"\ desc += "flash." %define _DESC1706_ \ desc += "Calibration Remap Descriptor n Master 2 Enable - These bits determine whether\n"\ desc += "calibration remapping is performed as defined by this descriptor based on the\n"\ desc += "logical master ID of the requesting AHB master.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, and\n"\ desc += "the M2EN field which corresponds to the requesting AHB master is asserted, then\n"\ desc += "calibration remapping is performed and data is fetched from the overlay RAM.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, but\n"\ desc += "the M2EN field which corresponds to the requesting AHB master is deasserted,\n"\ desc += "then calibration remapping is not performed and data is fetched from the\n"\ desc += "flash." %define _DESC1707_ \ desc += "Calibration Remap Descriptor n Master 3 Enable - These bits determine whether\n"\ desc += "calibration remapping is performed as defined by this descriptor based on the\n"\ desc += "logical master ID of the requesting AHB master.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, and\n"\ desc += "the M3EN field which corresponds to the requesting AHB master is asserted, then\n"\ desc += "calibration remapping is performed and data is fetched from the overlay RAM.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, but\n"\ desc += "the M3EN field which corresponds to the requesting AHB master is deasserted,\n"\ desc += "then calibration remapping is not performed and data is fetched from the\n"\ desc += "flash." %define _DESC1708_ \ desc += "Calibration Remap Descriptor n Master 4 Enable - These bits determine whether\n"\ desc += "calibration remapping is performed as defined by this descriptor based on the\n"\ desc += "logical master ID of the requesting AHB master.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, and\n"\ desc += "the M4EN field which corresponds to the requesting AHB master is asserted, then\n"\ desc += "calibration remapping is performed and data is fetched from the overlay RAM.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, but\n"\ desc += "the M4EN field which corresponds to the requesting AHB master is deasserted,\n"\ desc += "then calibration remapping is not performed and data is fetched from the\n"\ desc += "flash." %define _DESC1709_ \ desc += "Calibration Remap Descriptor n Master 5 Enable - These bits determine whether\n"\ desc += "calibration remapping is performed as defined by this descriptor based on the\n"\ desc += "logical master ID of the requesting AHB master.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, and\n"\ desc += "the M5EN field which corresponds to the requesting AHB master is asserted, then\n"\ desc += "calibration remapping is performed and data is fetched from the overlay RAM.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, but\n"\ desc += "the M5EN field which correspond s to the requesting AHB master is deasserted,\n"\ desc += "then calibration remapping is not performed and data is fetched from the\n"\ desc += "flash." %define _DESC1710_ \ desc += "Calibration Remap Descriptor n Master 6 Enable - These bits determine whether\n"\ desc += "calibration remapping is performed as defined by this descriptor based on the\n"\ desc += "logical master ID of the requesting AHB master.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, and\n"\ desc += "the M6EN field which corresponds to the requesting AHB master is asserted, then\n"\ desc += "calibration remapping is performed and data is fetched from the overlay RAM.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, but\n"\ desc += "the M6EN field which corresponds to the requesting AHB master is deasserted,\n"\ desc += "then calibration remapping is not performed and data is fetched from the\n"\ desc += "flash." %define _DESC1711_ \ desc += "Calibration Remap Descriptor n Master 7 Enable - These bits determine whether\n"\ desc += "calibration remapping is performed as defined by this descriptor based on the\n"\ desc += "logical master ID of the requesting AHB master.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, and\n"\ desc += "the M7EN field which corresponds to the requesting AHB master is asserted, then\n"\ desc += "calibration remapping is performed and data is fetched from the overlay RAM.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, but\n"\ desc += "the M7EN field which corresponds to the requesting AHB master is deasserted,\n"\ desc += "then calibration remapping is not performed and data is fetched from the\n"\ desc += "flash." %define _DESC1712_ \ desc += "Calibration Remap Descriptor n Master 8 Enable - These bits determine whether\n"\ desc += "calibration remapping is performed as defined by this descriptor based on the\n"\ desc += "logical master ID of the requesting AHB master.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, and\n"\ desc += "the M8EN field which corresponds to the requesting AHB master is asserted, then\n"\ desc += "calibration remapping is performed and data is fetched from the overlay RAM.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, but\n"\ desc += "the M8EN field which corresponds to the requesting AHB master is deasserted,\n"\ desc += "then calibration remapping is not performed and data is fetched from the\n"\ desc += "flash." %define _DESC1713_ \ desc += "Calibration Remap Descriptor n Master 9 Enable - These bits determine whether\n"\ desc += "calibration remapping is performed as defined by this descriptor based on the\n"\ desc += "logical master ID of the requesting AHB master.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, and\n"\ desc += "the M9EN field which corresponds to the requesting AHB master is asserted, then\n"\ desc += "calibration remapping is performed and data is fetched from the overlay RAM.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, but\n"\ desc += "the M9EN field which corresponds to the requesting AHB master is deasserted,\n"\ desc += "then calibration remapping is not performed and data is fetched from the\n"\ desc += "flash." %define _DESC1714_ \ desc += "Calibration Remap Descriptor n Master 10 Enable - These bits determine whether\n"\ desc += "calibration remapping is performed as defined by this descriptor based on the\n"\ desc += "logical master ID of the requesting AHB master.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, and\n"\ desc += "the M10EN field which corresponds to the requesting AHB master is asserted,\n"\ desc += "then calibration remapping is performed and data is fetched from the overlay\n"\ desc += "RAM.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, but\n"\ desc += "the M10EN field which corresponds to the requesting AHB master is deasserted,\n"\ desc += "then calibration remapping is not performed and data is fetched from the\n"\ desc += "flash." %define _DESC1715_ \ desc += "Calibration Remap Descriptor n Master 11 Enable - These bits determine whether\n"\ desc += "calibration remapping is performed as defined by this descriptor based on the\n"\ desc += "logical master ID of the requesting AHB master.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, and\n"\ desc += "the M11EN field which corresponds to the requesting AHB master is asserted,\n"\ desc += "then calibration remapping is performed and data is fetched from the overlay\n"\ desc += "RAM.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, but\n"\ desc += "the M11EN field which corresponds to the requesting AHB master is deasserted,\n"\ desc += "then calibration remapping is not performed and data is fetched from the\n"\ desc += "flash." %define _DESC1716_ \ desc += "Calibration Remap Descriptor n Master 12 Enable - These bits determine whether\n"\ desc += "calibration remapping is performed as defined by this descriptor based on the\n"\ desc += "logical master ID of the requesting AHB master.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, and\n"\ desc += "the M12EN field which corresponds to the requesting AHB master is asserted,\n"\ desc += "then calibration remapping is performed and data is fetched from the overlay\n"\ desc += "RAM.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, but\n"\ desc += "the M12EN field which corresponds to the requesting AHB master is deasserted,\n"\ desc += "then calibration remapping is not performed and data is fetched from the\n"\ desc += "flash." %define _DESC1717_ \ desc += "Calibration Remap Descriptor n Master 13 Enable - These bits determine whether\n"\ desc += "calibration remapping is performed as defined by this descriptor based on the\n"\ desc += "logical master ID of the requesting AHB master.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, and\n"\ desc += "the M13EN field which corresponds to the requesting AHB master is asserted,\n"\ desc += "then calibration remapping is performed and data is fetched from the overlay\n"\ desc += "RAM.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, but\n"\ desc += "the M13EN field which corresponds to the requesting AHB master is deasserted,\n"\ desc += "then calibration remapping is not performed and data is fetched from the\n"\ desc += "flash." %define _DESC1718_ \ desc += "Calibration Remap Descriptor n Master 14 Enable - These bits determine whether\n"\ desc += "calibration remapping is performed as defined by this descriptor based on the\n"\ desc += "logical master ID of the requesting AHB master.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, and\n"\ desc += "the M14EN field which corresponds to the requesting AHB master is asserted,\n"\ desc += "then calibration remapping is performed and data is fetched from the overlay\n"\ desc += "RAM.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, but\n"\ desc += "the M14EN field which corresponds to the requesting AHB master is deasserted,\n"\ desc += "then calibration remapping is not performed and data is fetched from the\n"\ desc += "flash." %define _DESC1719_ \ desc += "Calibration Remap Descriptor n Master 15 Enable - These bits determine whether\n"\ desc += "calibration remapping is performed as defined by this descriptor based on the\n"\ desc += "logical master ID of the requesting AHB master.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, and\n"\ desc += "the M15EN field which corresponds to the requesting AHB master is asserted,\n"\ desc += "then calibration remapping is performed and data is fetched from the overlay\n"\ desc += "RAM.\n\n"\ desc += "If the current access hits in the remap region defined by this descriptor, but\n"\ desc += "the M15EN field which corresponds to the requesting AHB master is deasserted,\n"\ desc += "then calibration remapping is not performed and data is fetched from the\n"\ desc += "flash." %define _DESC1720_ \ desc += "Calibration Remap Descriptor n Size - This field specifies the size of the\n"\ desc += "calibration remap region." %define _DESC1721_ \ desc += "PIT Module Control Register. The PIT Module Control Register (PIT x _MCR)\n"\ desc += "controls whether the timer clocks should be enabled and whether the timers\n"\ desc += "should run in debug mode." %define _DESC1722_ \ desc += "Module Disable\n\n"\ desc += "This is used to disable the module clock. The RTI timer is not affected by this\n"\ desc += "bit. This bit must be enabled before any other setup is done." %define _DESC1723_ \ desc += "Freeze\n\n"\ desc += "Allows the timers to be stopped when the device enters debug mode." %define _DESC1724_ \ desc += "PIT Upper Lifetime Timer Register. The PIT Module x Upper Lifetime Timer\n"\ desc += "Register (PIT x _LTMR64H) is intended for applications that chain timer 0 and\n"\ desc += "timer 1 to build a 64-bit life timer." %define _DESC1725_ \ desc += "Life Timer value\n\n"\ desc += "Shows the timer value of timer 1. If this register is read at a time t1,\n"\ desc += "LTMR64L shows the value of timer 0 at time t1." %define _DESC1726_ \ desc += "PIT Lower Lifetime Timer Register. The PIT Module x Lower Lifetime Timer\n"\ desc += "Register (PIT x _LTMR64L) is intended for applications that chain timer 0 and\n"\ desc += "timer 1 to build a 64-bit life timer.\n\n"\ desc += "To use LTMR64H and LTMR64L, timer 0 and timer 1 need to be chained. To obtain\n"\ desc += "the correct value, first read LTMR64H and then LTMR64L. LTMR64H will have the\n"\ desc += "value of CVAL1 at the time of the first access, LTMR64L will have the value of\n"\ desc += "CVAL0 at the time of the first access, therefore the application does not need\n"\ desc += "to worry about carry-over effects of the running counter." %define _DESC1727_ \ desc += "Life Timer value\n\n"\ desc += "Shows the value of timer 0 at the time LTMR64H was last read. It will only\n"\ desc += "update if LTMR64H is read." %define _DESC1728_ \ desc += "PIT Timer Load Value Register n. " %define _DESC1729_ \ desc += "Timer Start Value Bits\n\n"\ desc += "These bits set the timer start value. The timer will count down until it\n"\ desc += "reaches 0, then it will generate an interrupt and load this register value\n"\ desc += "again. Writing a new value to this register will not restart the timer, instead\n"\ desc += "the value will be loaded once the timer expires. To abort the current cycle and\n"\ desc += "start a timer period with the new value, the timer must be disabled and enabled\n"\ desc += "again." %define _DESC1730_ \ desc += "PIT Current Timer Value Register n. " %define _DESC1731_ \ desc += "Current Timer Value\n\n"\ desc += "If the timer is enabled, these bits represent the current timer value. If the\n"\ desc += "timer is disabled, do not use this field as its value is unreliable.\n\n"\ desc += "The timer uses a down counter. The timer values are frozen in debug mode if the\n"\ desc += "MCR[FRZ] bit is set." %define _DESC1732_ \ desc += "PIT Timer Control Register n. " %define _DESC1733_ \ desc += "Chain Mode Bit\n\n"\ desc += "When activated, timer n-1 needs to expire before timer n can decrement by 1.\n\n"\ desc += "Timer 0 cannot be changed." %define _DESC1734_ \ desc += "Timer Interrupt Enable Bit" %define _DESC1735_ \ desc += "Timer Enable Bit\n\n"\ desc += "This bit enables or disables the timer." %define _DESC1736_ \ desc += "PIT Timer Flag Register n. " %define _DESC1737_ \ desc += "This read-only bitfield is reserved and always has the value zero." %define _DESC1738_ \ desc += "Timer Interrupt Flag\n\n"\ desc += "TIF is set to 1 at the end of the timer period. This flag can be cleared only\n"\ desc += "by writing it with 1. Writing 0 has no effect. If enabled (TIE = 1), TIF causes\n"\ desc += "an interrupt request." %define _DESC1739_ \ desc += "PLLDIG PLL Control Register. The PLLCR is shown in the following table." %define _DESC1740_ \ desc += "This field indicates the operational state of the PLL. This field can be used\n"\ desc += "to change the operating mode. Normal mode must be entered once PLL has achieved\n"\ desc += "LOCK.\n\n"\ desc += "When the PLL externally powered down, the CLKCFG field changes to 00b. When\n"\ desc += "the external power down is removed, these bits will read 01b. The user software\n"\ desc += "must ensure that the PLL has attained lock (PLLSR[LOCK] = 1) before switching\n"\ desc += "this field to Normal mode, 11b." %define _DESC1741_ \ desc += "Loss-of-lock interrupt enable. The LOLIE bit enables a loss-of-lock interrupt\n"\ desc += "request when PLLSR[LOLF] = 1. If PLLSR[LOLF] = 0 or PLLCR[LOLIE] = 0, the\n"\ desc += "interrupt request is ignored. The interrupt request only occurs in normal\n"\ desc += "mode." %define _DESC1742_ \ desc += "The PLLCR[LOLRE] bit determines whether system reset is asserted or not upon a\n"\ desc += "loss-of-lock indication from PLL." %define _DESC1743_ \ desc += "PLLDIG PLL Status Register. " %define _DESC1744_ \ desc += "Loss-of-lock flag. This bit provides the interrupt request flag for the\n"\ desc += "loss-of-lock condition. Software must write 1 to LOLF to clear it, writing 0\n"\ desc += "has no effect. This flag bit is sticky in the sense that if lock is reacquired,\n"\ desc += "the bit will remain set until cleared by either writing 1 or asserting reset." %define _DESC1745_ \ desc += "Lock status bit. Indicates whether PLL has acquired lock." %define _DESC1746_ \ desc += "PLLDIG PLL Divider Register. The PLLDV register provides the PHI/PHI1 output\n"\ desc += "clock reduced frequency dividers, pre-divider, and loop divider. The values of\n"\ desc += "PREDIV and MFD should not be changed when the PLL is on and locked (working in\n"\ desc += "Normal mode). If these fields are changed without powering down the PLL, the\n"\ desc += "PLL will lose lock and generate either a reset or interrupt based on which is\n"\ desc += "enabled. The reduced frequency divider bitfields (RFDPHI, RFDPHI1) can be\n"\ desc += "modified at anytime, but the changes only become effective when PLL is\n"\ desc += "disabled, then reenabled." %define _DESC1747_ \ desc += "This 4-bit field determines the VCO/2 clock post divider for driving the PHI1\n"\ desc += "output clock. Divider = RFDPHI1, where RFDPHI1 has a range 4..15 (4h..Fh). All\n"\ desc += "other values are reserved." %define _DESC1748_ \ desc += "This 6-bit field determines the VCO clock post divider for driving the PHI\n"\ desc += "output clock." %define _DESC1749_ \ desc += "This field controls the value of the divider on the input clock. The output of\n"\ desc += "the predivider circuit generates the reference clock to the PLL analog loop.\n"\ desc += "The PREDIV value 000b causes the input clock to be inhibited." %define _DESC1750_ \ desc += "This field controls the value of the divider in the feedback loop. The value\n"\ desc += "specified by the MFD bits establishes the multiplication factor applied to the\n"\ desc += "reference frequency." %define _DESC1751_ \ desc += "Supply Gauge Status Register. This status register contains the gauge of the\n"\ desc += "indicated supply (or temperature sensor value). This indicates the present\n"\ desc += "state of the voltage (temperature) detect events for each of the supplies. Each\n"\ desc += "of the voltage detect signals for a given voltage are combined to form a single\n"\ desc += "bit." %define _DESC1752_ \ desc += "VD14 low-voltage detect flag. This read-only bit is the low-voltage status flag\n"\ desc += "associated with the voltage level detect for the high voltage 4 V supplies. It\n"\ desc += "is asserted when any of the supplies fall below the corresponding LVD\n"\ desc += "threshold, and clears when all the supplies rise above the corresponding LVD\n"\ desc += "threshold. All the 4.00 V supplies are combined to form this bit." %define _DESC1753_ \ desc += "VD10 low-voltage detect flag. This read-only bit is the low-voltage status flag\n"\ desc += "associated with the voltage level detect for the high voltage 3 V supply. It is\n"\ desc += "asserted when the supply falls below its corresponding LVD threshold, and\n"\ desc += "clears when the supply rises above its corresponding LVD threshold." %define _DESC1754_ \ desc += "VD9 low-voltage detect flag. This read-only bit is the low-voltage status flag\n"\ desc += "associated with the voltage level detect for the high voltage 2.8 V supplies.\n"\ desc += "It is asserted when any of the supplies fall below the corresponding LVD\n"\ desc += "threshold, and clears when all the supplies rise above the corresponding LVD\n"\ desc += "threshold. All of the 2.8 V LVDs are combined to form this bit." %define _DESC1755_ \ desc += "VD3 low-voltage detect flag. This read-only bit is the low-voltage status flag\n"\ desc += "associated with the voltage level detect for the low voltage 1.14 V supply\n"\ desc += "associated with the core logic. It is asserted when any of the VD3 supplies\n"\ desc += "fall below the corresponding LVD threshold, and clears when the supplies rise\n"\ desc += "above the corresponding LVD threshold. All the 1.08 V LVDs are combined to form\n"\ desc += "this bit." %define _DESC1756_ \ desc += "VD2 low-voltage detect flag. This read-only bit is the low-voltage status flag\n"\ desc += "associated with the\n\n"\ desc += "voltage level detect for the low voltage 0.98 V supply. It is asserted when any\n"\ desc += "of the LVD2 supplies fall\n\n"\ desc += "below the corresponding VD threshold, and clears when the supplies rise above\n"\ desc += "the corresponding\n\n"\ desc += "LVD threshold. The 0.98 V Core LVD forms this bit." %define _DESC1757_ \ desc += "Pending Gauge Status Register. This configuration register contains a mirror of\n"\ desc += "the contents of the Event Pending Registers, but in a format that includes one\n"\ desc += "bit for each voltage detect signal. These bits indicate the state of the\n"\ desc += "voltage detect events including whether a voltage level event has occurred at\n"\ desc += "any time in the past but has not been cleared (via the EPR register). These\n"\ desc += "bits are read only, and they are cleared by writing a one to the corresponding\n"\ desc += "EPR register.\n\n"\ desc += "The Pending registers are only set on an active edge of an event, so a\n"\ desc += "transition must be seen before they will become set.\n\n"\ desc += "The raw analog block voltage detect signals are also synchronized to the bus\n"\ desc += "clock before being used for the pending registers." %define _DESC1758_ \ desc += "VD14_A low-voltage detect flag. This read-only bit is the low-voltage status\n"\ desc += "flag associated with the voltage level detect for the high voltage 4 V ADC\n"\ desc += "supply. It is asserted when the supply falls below its corresponding LVD\n"\ desc += "threshold, and clears when the EPR_VD14[LVD14_A] is cleared." %define _DESC1759_ \ desc += "VD14_IM low-voltage detect flag. This read-only bit is the low-voltage status\n"\ desc += "flag associated with the voltage level detect for the high voltage 4 V I/O main\n"\ desc += "supply. It is asserted when the supply falls below its corresponding LVD\n"\ desc += "threshold, and clears when the EPR_VD14[LVD14_IM] is cleared." %define _DESC1760_ \ desc += "VD10_F low-voltage detect flag. This read-only bit is the low-voltage status\n"\ desc += "flag associated with the voltage level detect for the high voltage 3 V flash\n"\ desc += "supply. It is asserted when the supply falls below its corresponding LVD\n"\ desc += "threshold, and clears when the EPR_VD10[LVD10_F] is cleared." %define _DESC1761_ \ desc += "VD10_C low-voltage detect flag. This read-only bit is the low-voltage status\n"\ desc += "flag associated with the voltage level detect for the high voltage 2.9 V CORE\n"\ desc += "supply. It is asserted when the supply falls below its corresponding LVD\n"\ desc += "threshold, and clears when the EPR_VD10[LVD10_C] is cleared." %define _DESC1762_ \ desc += "VD10_IF low-voltage detect flag. This read-only bit is the low-voltage status\n"\ desc += "flag associated with the voltage level detect for the high voltage 2.9 V I/O\n"\ desc += "Ethernet supply. It is asserted when the supply falls below its corresponding\n"\ desc += "LVD threshold, and clears when the EPR_VD10[LVD10_IF] is cleared." %define _DESC1763_ \ desc += "VD10_IJ low-voltage detect flag. This read-only bit is the low-voltage status\n"\ desc += "flag associated with the voltage level detect for the high voltage 2.9 V I/O\n"\ desc += "JTAG supply. It is asserted when the supply falls below its corresponding LVD\n"\ desc += "threshold, and clears when the EPR_VD10[LVD10_IJ] is cleared." %define _DESC1764_ \ desc += "VD9_C low-voltage detect flag. This read-only bit is the low-voltage status\n"\ desc += "flag associated with the voltage level detect for the high voltage 2.7 V cold\n"\ desc += "point supply. It is asserted when the supply falls below its corresponding LVD\n"\ desc += "threshold, and clears when the EPR_VD9[LVD9_C] is cleared." %define _DESC1765_ \ desc += "VD3_C low-voltage detect flag. This read-only bit is the low-voltage status\n"\ desc += "flag associated with the voltage level detect for the core low voltage 1.08 V\n"\ desc += "supply. It is asserted when the supply falls below its corresponding LVD\n"\ desc += "threshold, and clears when the EPR_VD3[LVD3_C] is cleared." %define _DESC1766_ \ desc += "VD2_C low-voltage detect flag. This read-only bit is the low-voltage status\n"\ desc += "flag associated with the voltage level detect for the low voltage 0.98 V hot\n"\ desc += "point supply. It is asserted when the supply falls below its corresponding LVD\n"\ desc += "threshold, and clears when the EPR_VD2[LVD2_C] is cleared." %define _DESC1767_ \ desc += "Interrupt Enable Pending Register. This configuration register contains a set\n"\ desc += "of Interrupt Enable bits that correspond to each of the Event Pending Registers\n"\ desc += "(EPR_XX), but in a format similar to the Pending Gauge Status register (GR_P).\n"\ desc += "These bits indicate whether an interrupt occurs when the voltage event is seen.\n"\ desc += "A '0' indicates that no interrupt is to be sent, and a '1' indicates that an\n"\ desc += "interrupt is to occur when the voltage detect event occurs. Writing '1' to the\n"\ desc += "MSB of this register (IE_EN) enables all of the voltage detect bits in the\n"\ desc += "register to be read or written at any time." %define _DESC1768_ \ desc += "IE_EN. Interrupt Enable. This bit determines whether any of the Interrupt\n"\ desc += "Enable bits can be written." %define _DESC1769_ \ desc += "VD14IE_A Interrupt Enable. This bit determines whether an interrupt is seen by\n"\ desc += "the system when the voltage detect event occurs." %define _DESC1770_ \ desc += "VD14IE_IM Interrupt Enable. This bit determines whether an interrupt is seen by\n"\ desc += "the system when the voltage detect event occurs." %define _DESC1771_ \ desc += "VD10IE_F Interrupt Enable. This bit determines whether an interrupt is seen by\n"\ desc += "the system when the voltage detect event occurs." %define _DESC1772_ \ desc += "VD10IE_C Interrupt Enable. This bit determines whether an interrupt is seen by\n"\ desc += "the system when the voltage detect event occurs." %define _DESC1773_ \ desc += "VD10IE_IF Interrupt Enable. This bit determines whether an interrupt is seen by\n"\ desc += "the system when the voltage detect event occurs." %define _DESC1774_ \ desc += "VD10IE_IJ Interrupt Enable. This bit determines whether an interrupt is seen by\n"\ desc += "the system when the voltage detect event occurs." %define _DESC1775_ \ desc += "VD9IE_C Interrupt Enable. This bit determines whether an interrupt is seen by\n"\ desc += "the system when the voltage detect event occurs." %define _DESC1776_ \ desc += "VD3IE_C Interrupt Enable. This bit determines whether an interrupt is seen by\n"\ desc += "the system when the voltage detect event occurs." %define _DESC1777_ \ desc += "VD2IE_C Interrupt Enable. This bit determines whether an interrupt is seen by\n"\ desc += "the system when the voltage detect event occurs." %define _DESC1778_ \ desc += "LVD108 Event Pending register VD3. This Event Pending Register indicates the\n"\ desc += "present and past state of the voltage detect signals. If the voltage detect\n"\ desc += "event crosses the trigger threshold after the last clearing event, the flag bit\n"\ desc += "is set asynchronously. To clear the flag, a '1' must be written to the flag bit\n"\ desc += "that needs to be cleared." %define _DESC1779_ \ desc += "LVD3_C flag. This bit is the low-voltage status flag associated with the\n"\ desc += "voltage level detect for the low voltage core 1.08 V hot point supply. It is\n"\ desc += "asserted asynchronously when the supply falls below its corresponding LVD\n"\ desc += "threshold, and clears when a one is written to this bit location.\n\n"\ desc += "If the VD3IE_C bit is also asserted, a low-voltage interrupt is sent to the\n"\ desc += "CPU. If REE_VD3[LVD3_C] is also asserted, a system reset is generated which\n"\ desc += "clears VD3IE_C and negate the interrupt request. If REE_VD3[LVD3_C] is\n"\ desc += "asserted and a destructive reset is selected (via RES_VD3[LVD3_C] being 0),\n"\ desc += "then a destructive reset is generated. If RES_VD3[LVD3_C] is set, then a\n"\ desc += "functional reset is generated." %define _DESC1780_ \ desc += "Reset Event Enable VD3. This Reset Event Enable Register controls whether the\n"\ desc += "voltage detect signal event causes a reset. If the desired flag bit is enabled,\n"\ desc += "the voltage detect event causes a reset to be generated when the selected\n"\ desc += "voltage passes the trigger event. These bits are loaded from the flash during\n"\ desc += "the boot sequence. If the flash loaded bits are programmed to be enabled (set),\n"\ desc += "these bits cannot be disabled (cleared)." %define _DESC1781_ \ desc += "LVD3_C reset enable. This bit defines whether an LVD assertion on the supply of\n"\ desc += "the low voltage core 1.08 V hot point supply generates a system reset. The\n"\ desc += "RES_VD3[LVD3_C] bit determines whether the reset is functional or\n"\ desc += "destructive." %define _DESC1782_ \ desc += "Reset Event Selection VD3. This Reset Event Select Register controls whether\n"\ desc += "the voltage detect signal event causes a destructive or functional reset. If\n"\ desc += "the desired flag bit is enabled, the voltage detect event causes either a\n"\ desc += "destructive or functional reset to be generated when the selected voltage\n"\ desc += "passes the trigger event. These bits are loaded from the flash during the boot\n"\ desc += "sequence." %define _DESC1783_ \ desc += "LVD3_C reset event select. This bit defines whether an LVD assertion on the\n"\ desc += "supply of the low voltage core 1.08 V hot point supply generates a destructive\n"\ desc += "reset or a functional reset. The REE_VD3[LVD3_C] bit determines whether the\n"\ desc += "reset event is enabled." %define _DESC1784_ \ desc += "LVD270 Event Pending register VD9. This Event Pending Register indicates the\n"\ desc += "present and past state of the voltage detect signals. If the voltage detect\n"\ desc += "event crosses the trigger threshold after the last clearing event, the flag bit\n"\ desc += "is set asynchronously. In order to clear the flag, a '1' must be written to the\n"\ desc += "flag bit that needs to be cleared." %define _DESC1785_ \ desc += "LVD9_C flag. This bit is the low-voltage status flag associated with the\n"\ desc += "voltage level detect for the high voltage 2.8 V hot point supply. It is\n"\ desc += "asserted asynchronously when the supply falls below its corresponding LVD\n"\ desc += "threshold, and clears when a one is written to this bit location.\n\n"\ desc += "When the VD9IE_C bit is asserted, a system reset is generated." %define _DESC1786_ \ desc += "LVD290 Event Pending register VD10. This Event Pending Register indicates the\n"\ desc += "present and past state of the voltage detect signals. If the voltage detect\n"\ desc += "event crosses the trigger threshold after the last clearing event, the flag bit\n"\ desc += "is set asynchronously. In order to clear the flag, a '1' must be written to the\n"\ desc += "flag bit that needs to be cleared." %define _DESC1787_ \ desc += "LVD10_F flag. This bit is the low-voltage status flag associated with the\n"\ desc += "voltage level detect for the high voltage 2.90V flash supply. It is asserted\n"\ desc += "when the supply falls below its corresponding LVD threshold, and clears when\n"\ desc += "the supply rises above its corresponding LVD threshold and a one is written to\n"\ desc += "this bit location. If the VD10IE_F bit is also asserted, a low-voltage\n"\ desc += "interrupt is sent to the CPU. If REE_VD10[LVD10_F] is also asserted, a system\n"\ desc += "reset is generated, which clears VD10IE_F and negate the interrupt request. If\n"\ desc += "REE_VD10[LVD10_F] is asserted and a destructive reset is selected (via\n"\ desc += "RES_VD10[LVD10_F] being 0), then a destructive reset is generated. If\n"\ desc += "RES_VD10[LVD10_F] is set, then a functional reset is generated.\n\n"\ desc += "0 Currently no occurrence.\n\n"\ desc += "1 LVD occurrence detected on the high voltage flash supply." %define _DESC1788_ \ desc += "LVD10_C flag. This bit is the low-voltage status flag associated with the\n"\ desc += "voltage level detect for the high voltage 2.90V CPU supply. It is asserted when\n"\ desc += "the supply falls below its corresponding LVD threshold, and clears when the\n"\ desc += "supply rises above its corresponding LVD threshold and a one is written to this\n"\ desc += "bit location. If the VD10IE_C bit is also asserted, a low-voltage interrupt is\n"\ desc += "sent to the CPU. If REE_VD10[LVD10_C] is also asserted, a system reset is\n"\ desc += "generated, which clears VD10IE_C and negate the interrupt request. If\n"\ desc += "REE_VD10[LVD10_C] is asserted and a destructive reset is selected (via\n"\ desc += "RES_VD10[LVD10_C] being 0), then a destructive reset is generated. If\n"\ desc += "RES_VD10[LVD10_C] is set, then a functional reset is generated." %define _DESC1789_ \ desc += "LVD10_IF flag. This bit is the low-voltage status flag associated with the\n"\ desc += "voltage level detect for the high voltage 2.90V Ethernet supply. It is asserted\n"\ desc += "when the supply falls below its corresponding LVD threshold, and clears when\n"\ desc += "the supply rises above its corresponding LVD threshold and a one is written to\n"\ desc += "this bit location. If the VD10IE_IF bit is also asserted, a low-voltage\n"\ desc += "interrupt is sent to the CPU. If REE_VD10[LVD10_IF] is also asserted, a system\n"\ desc += "reset is generated, which clears VD10IE_F and negate the interrupt request. If\n"\ desc += "REE_VD10[LVD10_IF] is asserted and a destructive reset is selected (via\n"\ desc += "RES_VD10[LVD10_IF] being 0), then a destructive reset is generated. If\n"\ desc += "RES_VD10[LVD10_IF] is set, then a functional reset is generated." %define _DESC1790_ \ desc += "LVD10_IJ flag. This bit is the low-voltage status flag associated with the\n"\ desc += "voltage level detect for the high voltage 2.90V IO/JTAG supply. It is asserted\n"\ desc += "when the supply falls below its corresponding LVD threshold, and clears when\n"\ desc += "the supply rises above its corresponding LVD threshold and a one is written to\n"\ desc += "this bit location. If the VD10IE_C bit is also asserted, a low-voltage\n"\ desc += "interrupt is sent to the CPU. If REE_VD10[LVD10_IJ] is also asserted, a system\n"\ desc += "reset is generated, which clears VD10IE_IJ and negate the interrupt request. If\n"\ desc += "REE_VD10[LVD10_IF] is asserted and a destructive reset is selected (via\n"\ desc += "RES_VD10[LVD10_IJ] being 0), then a destructive reset is generated. If\n"\ desc += "RES_VD10[LVD10_IJ] is set, then a functional reset is generated." %define _DESC1791_ \ desc += "Reset Event Enable VD10. This Reset Event Enable Register controls whether the\n"\ desc += "voltage detect signal event causes a reset. If the desired flag bit is enabled,\n"\ desc += "the voltage detect event causes a reset to be generated when the selected\n"\ desc += "voltage passes the trigger event. These bits are loaded from the flash during\n"\ desc += "the boot sequence. If the flash loaded bits are programmed to be enabled (set),\n"\ desc += "these bits cannot be disabled (cleared)." %define _DESC1792_ \ desc += "LVD10_F reset enable. This bit defines whether an LVD assertion on the supply\n"\ desc += "of the flash generates a system reset. The RES_VD10[LVD10_F] bit determines\n"\ desc += "whether the reset is functional or destructive." %define _DESC1793_ \ desc += "LVD10_C reset enable. This bit defines whether an LVD assertion on the supply\n"\ desc += "of the core generates a system reset. The RES_VD10[LVD10_C] bit determines\n"\ desc += "whether the reset is functional or destructive." %define _DESC1794_ \ desc += "LVD10_IF reset disable. This bit defines whether an LVD assertion on the supply\n"\ desc += "of the Ethernet generates a system reset. The RES_VD10[LVD10_IF] bit determines\n"\ desc += "whether the reset is functional or destructive." %define _DESC1795_ \ desc += "LVD10_IJ reset enable. This bit defines whether an LVD assertion on the supply\n"\ desc += "of the JTAG generates a system reset. The RES_VD10[LVD10_IJ] bit determines\n"\ desc += "whether the reset is functional or destructive." %define _DESC1796_ \ desc += "Reset Event Selection VD10. This Reset Event Select Register controls whether\n"\ desc += "the voltage detect signal event causes a destructive or functional reset. If\n"\ desc += "the desired flag bit is enabled, the voltage detect event causes either a\n"\ desc += "destructive or functional reset to be generated when the selected voltage\n"\ desc += "passes the trigger event. These bits are loaded from the flash during the boot\n"\ desc += "sequence." %define _DESC1797_ \ desc += "LVD400 Event Pending register VD14. This Event Pending Register indicates the\n"\ desc += "present and past state of the voltage detect signals. If the voltage detect\n"\ desc += "event crosses the trigger threshold after the last clearing event, the flag bit\n"\ desc += "is set asynchronously. In order to clear the flag, a '1' must be written to the\n"\ desc += "flag bit that needs to be cleared." %define _DESC1798_ \ desc += "LVD14_A flag. This bit is the low-voltage status flag associated with the\n"\ desc += "voltage level detect for the high voltage 4 V ADC supply. It is asserted\n"\ desc += "asynchronously when the supply falls below its corresponding LVD threshold, and\n"\ desc += "clears when a one is written to this bit location. If the VD14IE_A bit is also\n"\ desc += "asserted, a low-voltage interrupt is sent to the CPU. If REE_VD14[LVD14_A] is\n"\ desc += "also asserted, a system reset is generated, which clears VD14IE_A and negates\n"\ desc += "the interrupt request. If REE_VD14[LVD14_A] is asserted and a destructive reset\n"\ desc += "is selected (via RES_VD14[LVD14_A] being 0), then a destructive reset is\n"\ desc += "generated. If RES_VD14[LVD14_A] is set, then a functional reset is generated." %define _DESC1799_ \ desc += "LVD14_IM flag. This bit is the low-voltage status flag associated with the\n"\ desc += "voltage level detect for the high voltage 4 V I/O Main supply. It is asserted\n"\ desc += "asynchronously when the supply falls below its corresponding LVD threshold, and\n"\ desc += "clears when a one is written to this bit location. If the VD14IE_IM bit is also\n"\ desc += "asserted, a low-voltage interrupt is sent to the CPU. If REE_VD14[LVD14_IM] is\n"\ desc += "also asserted, a system reset is generated, which clears VD14IE_IM and negate\n"\ desc += "the interrupt request. If REE_VD14[LVD14_IM] is asserted and a destructive\n"\ desc += "reset is selected (via RES_VD14[LVD14_IM] being 0), then a destructive reset is\n"\ desc += "generated. If RES_VD14[LVD14_IM] is set, then a functional reset is\n"\ desc += "generated." %define _DESC1800_ \ desc += "Reset Event Enable VD14. This Reset Event Enable Register controls whether the\n"\ desc += "voltage detect signal event causes a reset. If the desired flag bit is enabled,\n"\ desc += "the voltage detect event causes a reset to be generated when the selected\n"\ desc += "voltage passes the trigger event. These bits are loaded from the flash during\n"\ desc += "the boot sequence. If the flash loaded bits are programmed to be enabled (set),\n"\ desc += "these bits cannot be disabled (cleared)" %define _DESC1801_ \ desc += "LVD14_A reset enable. This bit defines whether an LVD assertion on the supply\n"\ desc += "of the ADC generates a system reset. The RES_VD14[LVD14_A] bit determines\n"\ desc += "whether the reset is functional or destructive." %define _DESC1802_ \ desc += "LVD14_IM reset enable. This bit defines whether an LVD assertion on the supply\n"\ desc += "of the I/O Main generates a system reset. The RES_VD14[LVD14_IM] bit determines\n"\ desc += "whether the reset is functional or destructive." %define _DESC1803_ \ desc += "Reset Event Selection VD14. This Reset Event Select Register controls whether\n"\ desc += "the voltage detect signal event causes a destructive or functional reset. If\n"\ desc += "the desired flag bit is enabled, the voltage detect event causes either a\n"\ desc += "destructive or functional reset to be generated when the selected voltage\n"\ desc += "passes the trigger event. These bits are loaded from the flash during the boot\n"\ desc += "sequence." %define _DESC1804_ \ desc += "LVD14_A reset event select. This bit defines whether an LVD assertion on the\n"\ desc += "supply of the ADC generates a destructive reset or a functional reset. The\n"\ desc += "REE_VD14[LVD14_A] bit determines whether the reset event is enabled." %define _DESC1805_ \ desc += "LVD14_IM reset event select. This bit defines whether an LVD assertion on the\n"\ desc += "supply of the IO Main generates a destructive reset or a functional reset. The\n"\ desc += "REE_VD14[LVD14_IM] bit determines whether the reset event is enabled." %define _DESC1806_ \ desc += "Voltage Selection for I/O Segment. The Voltage Supply for I/O Segments (VSIO)\n"\ desc += "register indicates if a particular I/O segment uses a 3.3V or 5.0V supply.\n"\ desc += "These bits all reset to use a 5.0V supply." %define _DESC1807_ \ desc += "VSIO_IF control. This bit is used to control the supply levels used by the\n"\ desc += "Ethernet I/O segment." %define _DESC1808_ \ desc += "VSIO_IJ control. This bit is used to control the supply levels used by the JTAG\n"\ desc += "I/O segment." %define _DESC1809_ \ desc += "VSIO_IM control. This bit is used to control the supply levels used by the Main\n"\ desc += "I/O segment." %define _DESC1810_ \ desc += "Main Regulator Control register. This Control Register controls and indicates\n"\ desc += "the state of the Main Regulator for Lavaredo. If the MREG_ENB signal is low,\n"\ desc += "the main regulator for Lavaredo is enabled. If the MREG_ENB signal is high, the\n"\ desc += "main regulator is disabled." %define _DESC1811_ \ desc += "MREG_ENB. This bit controls the enable for the Main Regulator for Lavaredo." %define _DESC1812_ \ desc += "Temperature Event Pending register. This Event Pending Register indicates the\n"\ desc += "present and past state of the temperature sensor signals. If the temperature\n"\ desc += "event has ever passed the trigger event since the last clearing event, the flag\n"\ desc += "bit is set. In order to clear the flag, a '1' must be written to the flag bit\n"\ desc += "that needs to be cleared." %define _DESC1813_ \ desc += "TEMP_2 flag. This bit is the temperature status flag associated with the\n"\ desc += "temperature for the temperature sensor point (150C). It is asserted when the\n"\ desc += "temperature exceeds its corresponding threshold, and clears when a one is\n"\ desc += "written to this bit location. If the IETD_2 bit is also asserted, an interrupt\n"\ desc += "is sent to the CPU. If REE_TD[TEMP_2 is also asserted, a system reset is\n"\ desc += "generated, which clears IETD_2 and negate the interrupt request. If\n"\ desc += "REE_TD[TEMP_2] is asserted and a destructive reset is selected (via\n"\ desc += "RES_TD[TEMP_2] being 0), then a destructive reset is generated. If\n"\ desc += "RES_TD[TEMP_2] is set, then a functional reset is generated." %define _DESC1814_ \ desc += "TEMP_1 flag. This bit is the temperature status flag associated with the\n"\ desc += "temperature for the temperature\n\n"\ desc += "sensor point (150C). It is asserted when the temperature exceeds its\n"\ desc += "corresponding threshold, and clears when the temperature falls below its\n"\ desc += "corresponding threshold and a one is written to this bit location. If the\n"\ desc += "IETD_1 bit is also asserted, an interrupt is sent to the CPU. If REE_TD[TEMP_1\n"\ desc += "is also asserted, a system reset is generated, which clears IETD_1 and negate\n"\ desc += "the interrupt request. If REE_TD[TEMP_1] is asserted and a destructive reset is\n"\ desc += "selected (via RES_TD[TEMP_1] being 0), then a destructive reset is generated.\n"\ desc += "If RES_TD[TEMP_1] is set, then a functional reset is generated." %define _DESC1815_ \ desc += "TEMP_0 flag. This bit is the temperature status flag associated with the\n"\ desc += "temperature for the cold temperature sensor point. It is asserted when the\n"\ desc += "temperature exceeds its corresponding threshold, and clears when a one is\n"\ desc += "written to this bit location. If the IETD_0 bit is also asserted, an interrupt\n"\ desc += "is sent to the CPU. If REE_TD[TEMP_0] is also asserted, a system reset is\n"\ desc += "generated, which clears IETD_0 and negate the interrupt request. If\n"\ desc += "REE_TD[TEMP_0] is asserted and a destructive reset is selected (via\n"\ desc += "RES_TD[TEMP_0] being 0), then a destructive reset is generated. If\n"\ desc += "RES_TD[TEMP_0] is set, then a functional reset is generated." %define _DESC1816_ \ desc += "Temperature Reset Event Enable register. This Reset Event Enable Register\n"\ desc += "controls whether the temperature detect signal event causes a reset. If the\n"\ desc += "desired flag bit is enabled, the temperature detect event causes a reset to be\n"\ desc += "generated when the selected temperature passes the trigger event.\n\n"\ desc += "If the Temperature Sensor REE and RES bits are set to cause a destructive\n"\ desc += "reset, then during that process the TS REE and RES bits are also cleared by the\n"\ desc += "destructive reset." %define _DESC1817_ \ desc += "TEMP_2 reset enable. This bit defines whether a temperature detect assertion\n"\ desc += "generates a system reset. The RES_TD[TEMP_2] bit determines whether the reset\n"\ desc += "is functional or destructive." %define _DESC1818_ \ desc += "TEMP_1 reset enable. This bit defines whether a temperature detect assertion\n"\ desc += "generates a systemreset. The RES_TD[TEMP_1] bit determines whether the reset is\n"\ desc += "functional or destructive." %define _DESC1819_ \ desc += "TEMP_0 reset enable. This bit defines whether a temperature detect assertion\n"\ desc += "generates a system reset. The RES_TD[TEMP_0] bit determines whether the reset\n"\ desc += "is functional or destructive." %define _DESC1820_ \ desc += "Temperature Reset Event Selection register. This Reset Event Select Register\n"\ desc += "controls whether the temperature sensor detect signal event causes a\n"\ desc += "destructive or functional reset. If the desired flag bit is enabled, the\n"\ desc += "temperature sensor event causes either a destructive or functional reset to be\n"\ desc += "generated when the selected temperature passes the trigger event.\n\n"\ desc += "If the Temperature Sensor REE and RES bits are set to cause a destructive\n"\ desc += "reset, then during that process the TS REE and RES bits are also cleared by the\n"\ desc += "destructive reset." %define _DESC1821_ \ desc += "TEMP_2 reset event select. This bit defines whether a temperature detect\n"\ desc += "assertion generates a destructive reset or a functional reset. The\n"\ desc += "REE_TD[TEMP_2] bit determines whether the reset event is enabled." %define _DESC1822_ \ desc += "TEMP_1 reset event select. This bit defines whether a temperature detect\n"\ desc += "assertion generates a destructive reset or a functional reset. The\n"\ desc += "REE_TD[TEMP_1] bit determines whether the reset event is enabled." %define _DESC1823_ \ desc += "TEMP_0 reset event select. This bit defines whether an temperature detect\n"\ desc += "assertion generates a destructive reset or a functional reset. The\n"\ desc += "REE_TD[TEMP_0] bit determines whether the reset event is enabled." %define _DESC1824_ \ desc += "Temperature detector configuration register. The Temperature Sensor Register\n"\ desc += "(CTL_TD) contains two enables that must both be enabled in order for the\n"\ desc += "Temperature Sensor to be operable. It also includes two 4-bit signed trim\n"\ desc += "adjustment register bits that are used to modify both TS trim values (one bus\n"\ desc += "for over temp and one bus for under temp). Finally, this register includes\n"\ desc += "Interrupt Enables (IE) for each of the Temp Sensor EPR bits.\n\n"\ desc += "The use case for the TRIM_ADJ_OVER and _UNDER bits would be to introduce\n"\ desc += "additional hysteresis into the Temp Sensor events.\n\n"\ desc += "For instance, the TRIM_ADJ_OVER bits could be written to 11111 (-7) and the\n"\ desc += "Temp Sensor event set to be an interrupt. When this interrupt occurs, the\n"\ desc += "TRIM_ADJ_OVER bits could be updated to 0111 (+7), the interrupt cleared, and\n"\ desc += "the Temp Sensor event set to be a reset.\n\n"\ desc += "In this way, a 'warning' event (like an interrupt) could be detected as well as\n"\ desc += "a 'shutdown' event (at a higher temperature).\n\n"\ desc += "Care must be taken to include a timeout during the clearing of the interrupt\n"\ desc += "described in the example above. The Temp Sensor has hysteresis and a timeout\n"\ desc += "may be necessary to indicate if the interrupt flag has not cleared in a\n"\ desc += "reasonable amount of time. If this is the case, then an error should be\n"\ desc += "indicated." %define _DESC1825_ \ desc += "TS3IE Temperature Sensor input 3 Interrupt Enable. This bit determines whether\n"\ desc += "an interrupt is seen by the system when the voltage detect event occurs. The\n"\ desc += "MSB in IE_P must be set to access this bit." %define _DESC1826_ \ desc += "TS2IE Temperature Sensor input 2 Interrupt Enable. This bit determines whether\n"\ desc += "an interrupt is seen by the system when the voltage detect event occurs. The\n"\ desc += "MSB in IE_P must be set to access this bit." %define _DESC1827_ \ desc += "TS0IE Temperature Sensor input 0 Interrupt Enable. This bit determines whether\n"\ desc += "an interrupt is seen by the system when the voltage detect event occurs. The\n"\ desc += "MSB in IE_P must be set to access this bit." %define _DESC1828_ \ desc += "TRIM_ADJ_OVER[3:0]. Customer adjustable over trim register. These bits are a\n"\ desc += "signed binary number that is added to the over temperature trim (NT_TD2) value.\n"\ desc += "The TRIM value is protected from overflows and underflows due to this\n"\ desc += "addition." %define _DESC1829_ \ desc += "TRIM_ADJ_UNDER[3:0]. Customer adjustable under trim register. These bits are a\n"\ desc += "signed binary number that is added to the under temperature trim value\n"\ desc += "(NT_TD0). The TRIM value is protected from overflows and underflows due to this\n"\ desc += "addition." %define _DESC1830_ \ desc += "DOUT_EN. Digital Output Enable." %define _DESC1831_ \ desc += "AOUT_EN. Analog Output Enable." %define _DESC1832_ \ desc += "Platform RAM Configuration Register 1. The Platform RAM Configuration Register\n"\ desc += "1 (PRCR1) is used to specify operation of the RAM controller.\n\n"\ desc += "This register is accessible only in supervisor mode. Accesses in user mode\n"\ desc += "return a transfer error." %define _DESC1833_ \ desc += "The number of cycles taken for a RAM access can vary +-1 clock cycle depending\n"\ desc += "on the RAM speed relative to the PRAM controller clock frequency. If system RAM\n"\ desc += "is running at the same frequency as the PRAM controller, a random initial\n"\ desc += "access takes 2 clock cycles. If system RAM is running at a slower frequency, a\n"\ desc += "random initial access may take 3 clock cycles. Subsequent burst beats take\n"\ desc += "either 1 or 2 cycles depending on RAM speed relative to PRAM controller clock\n"\ desc += "frequency." %define _DESC1834_ \ desc += "This field defines the AHB response of the on reads. The state of this field\n"\ desc += "has no impact on the response latency on writes. This bit is cleared by\n"\ desc += "hardware reset." %define _DESC1835_ \ desc += "Main Configuration Register. " %define _DESC1836_ \ desc += "Overwrite enable\n\n"\ desc += "This bit enables or disables the functionality to overwrite unread converted\n"\ desc += "data in ICDR, TCDR, ECDR registers." %define _DESC1837_ \ desc += "Write left/right-aligned" %define _DESC1838_ \ desc += "One Shot/Scan" %define _DESC1839_ \ desc += "External Start Enable\n\n"\ desc += "This bit enables or disables the external start signal to initial a normal\n"\ desc += "conversion. This can be used to synchronize multiple SARADCs concurrently." %define _DESC1840_ \ desc += "Normal Start conversion\n\n"\ desc += "Setting this bit starts the chain or scan conversion. Resetting this bit during\n"\ desc += "scan mode causes the current chain conversion to finish, then stops the\n"\ desc += "operation." %define _DESC1841_ \ desc += "Normal trigger enable" %define _DESC1842_ \ desc += "Normal trigger edge selection" %define _DESC1843_ \ desc += "Injected Start conversion\n\n"\ desc += "Setting this bit will start the configured injected analog channels to be\n"\ desc += "converted by software. Resetting this bit has no effect, as the injected chain\n"\ desc += "conversion cannot be interrupted." %define _DESC1844_ \ desc += "Injection trigger enable" %define _DESC1845_ \ desc += "Injection trigger edge selection" %define _DESC1846_ \ desc += "Injection trigger sequence enable" %define _DESC1847_ \ desc += "Reserved\n\n"\ desc += "Write of any value has no effect; read value is always 0." %define _DESC1848_ \ desc += "Cross Trigger Unit Enable" %define _DESC1849_ \ desc += "Cross Trigger Unit Mode\n\n"\ desc += "This bit is present only if generic parameter CTSEN = 2, otherwise this bit is\n"\ desc += "a reserved bit and always read as 0." %define _DESC1850_ \ desc += "Injection Trigger Input Selection\n\n"\ desc += "This bitfield selects which trigger input to be selected to start injected\n"\ desc += "conversion." %define _DESC1851_ \ desc += "Abort Chain\n\n"\ desc += "When this bit is set, the ongoing Chain Conversion is aborted. This bit is\n"\ desc += "reset by hardware as soon as a new conversion is requested." %define _DESC1852_ \ desc += "Abort Conversion\n\n"\ desc += "When this bit is set, the ongoing conversion is aborted and a new conversion is\n"\ desc += "invoked. This bit is reset by hardware as soon as a new conversion is\n"\ desc += "invoked." %define _DESC1853_ \ desc += "Freeze\n\n"\ desc += "This bit enables to stop the SARADC conversions at the end of current channel\n"\ desc += "conversion when SoC enters debug mode." %define _DESC1854_ \ desc += "Power-down enable\n\n"\ desc += "When this bit is set, the analog module is requested to enter Power Down mode.\n"\ desc += "When SARADC status is PWDN, resetting this bit starts SARADC transition to IDLE\n"\ desc += "mode." %define _DESC1855_ \ desc += "Main Status Register. " %define _DESC1856_ \ desc += "This status bit is used to signal that a normal conversion is ongoing." %define _DESC1857_ \ desc += "This status bit is used to signal that a injected conversion is ongoing." %define _DESC1858_ \ desc += "This status bit is used to signal that an Injected conversion chain has been\n"\ desc += "aborted. This bit is reset when a new conversion starts." %define _DESC1859_ \ desc += "This status bit is used to signal that a CTU conversion is ongoing. This bit is\n"\ desc += "set when a CTU trigger pulse is received and the CTU conversion starts. When\n"\ desc += "CTU trigger mode is enabled this bit is automatically reset when the conversion\n"\ desc += "is completed. Otherwise, if Control Mode is enabled this bit can be reset only\n"\ desc += "when the CTU is disabled (CTUEN set to '0')." %define _DESC1860_ \ desc += "Channel under measure address (CHADDR[7:0])\n\n"\ desc += "This status bit is used to signal which channel is under measure." %define _DESC1861_ \ desc += "ADCSTATUS[2:0]. The value of this parameter depends on ADC status. While\n"\ desc += "requesting an external\n\n"\ desc += "channel conversion, SARADC digital interface needs to wait for a fixed time\n\n"\ desc += "determined by DSD bitfield of DSDR before proceeding to actual sampling\n"\ desc += "phase.\n\n"\ desc += "This is known as wait state." %define _DESC1862_ \ desc += "Interrupt Status Register. " %define _DESC1863_ \ desc += "End of CTU channel conversion interrupt flag\n\n"\ desc += "This bit indicates the end of conversion for a CTU injected channel." %define _DESC1864_ \ desc += "End of injected channel conversion interrupt flag\n\n"\ desc += "This bit indicates the end of conversion for an injected channel." %define _DESC1865_ \ desc += "End of injected chain conversion interrupt flag\n\n"\ desc += "This bit indicates the end of conversion for an injected chain." %define _DESC1866_ \ desc += "End of normal channel conversion interrupt flag\n\n"\ desc += "This bit indicates the end of conversion for a normal channel." %define _DESC1867_ \ desc += "End of normal chain conversion interrupt flag\n\n"\ desc += "This bit indicates the end of conversion for an normal chain." %define _DESC1868_ \ desc += "Internal channel Interrupt Pending Register. The interrupt channel register to\n"\ desc += "channel association is described below.\n\n"\ desc += "Note:\n\n"\ desc += "Parameter num_intch vector has positional inference for registers ICIPR0-2,\n"\ desc += "such that:\n\n"\ desc += "num_intch(i)(where i:0to31) corresponds to ICIPR0 bit [0to31],\n"\ desc += "num_intch(i)(where i:32to63) corresponds to ICIPR1 bit [0to31] and\n"\ desc += "num_intch(i)(where i:64to95) corresponds to ICIPR2 bit [0to31].\n\n"\ desc += "If any num_intch(i) value is '0', corresponding bit is not implemented and read\n"\ desc += "access returns '0' on that bit location.Thus, if num_intch[31:0] is all 0s,\n"\ desc += "then register ICIPR0 is not implemented. If num_intch[63:32] is all 0s, then\n"\ desc += "register ICIPR1 is not implemented. If num_intch[95:64] is all 0s, then\n"\ desc += "register ICIPR2 is not implemented. Each is treated as reserved space; any\n"\ desc += "access on this space generates transfer error.\n\n"\ desc += "[ICIPR0-2 Registers to channel association]:\n"\ desc += " Register Register Bits\n"\ desc += " ICIPR0 EOC_CH[31:0]\n"\ desc += " ICIPR1 EOC_CH[63:32]\n"\ desc += " ICIPR2 EOC_CH[95:64]\n" %define _DESC1869_ \ desc += "End of conversion interrupt pending bit for channel x" %define _DESC1870_ \ desc += "Interrupt Mask Register. The description of the Interrupt Mask Register is\n"\ desc += "given below." %define _DESC1871_ \ desc += "Mask bit for EOCTU" %define _DESC1872_ \ desc += "Mask bit for JEOC" %define _DESC1873_ \ desc += "Mask bit for JECH" %define _DESC1874_ \ desc += "Mask bit for NEOC" %define _DESC1875_ \ desc += "Mask bit for NECH" %define _DESC1876_ \ desc += "Internal Channel Interrupt Mask Register. The interrupt mask register to\n"\ desc += "channel association is described below.\n\n"\ desc += "Note: Parameter num_intch vector has positional inference for registers\n"\ desc += "ICIMR0-2 i.e. num_intch(i)(where i:0to31) corres. to ICIMR0 bit [0to31],\n"\ desc += "num_intch(i)(where i:32to63) corres. to ICIMR1 bit [0to31] and\n"\ desc += "num_intch(i)(where i:64to95) corres. to ICIMR2 bit [0to31]. if any of the\n"\ desc += "num_intch(i) value is '0' corresponding bit is not implemented and read access\n"\ desc += "would return '0' on that bit location. Thus if num_intch[31:0] is all 0's than\n"\ desc += "register ICIMR0 is not implemented, if num_intch[63:32] is all 0's than\n"\ desc += "register ICIMR1 is not implemented and similarly if num_intch[95:64] is all 0's\n"\ desc += "than register ICIMR2 is not implemented and treated as reserved space any\n"\ desc += "access on this space generates transfer error.\n\n"\ desc += "[Interrupt Mask Registers to Channel Association]:\n"\ desc += " Register Register Bits\n"\ desc += " -------- -------------\n"\ desc += " ICIMR0 IM_CH[31:0]\n"\ desc += " ICIMR1 IM_CH[63:32]\n"\ desc += " ICIMR2 IM_CH[95:64]\n" %define _DESC1877_ \ desc += "IM_CH[x]: Interrupt mask bit for channel x" %define _DESC1878_ \ desc += "Watchdog Threshold Interrupt Status Register. This register gives the interrupt\n"\ desc += "status information for the 16 possible upper/lower threshold limits which can\n"\ desc += "be selected for each channel.\n\n"\ desc += "Note: In case num_watchdog generic parameter is zero, this register is not\n"\ desc += "implemented." %define _DESC1879_ \ desc += "This corresponds to the interrupt generated on the converted value being higher\n"\ desc += "than the programmed higher threshold." %define _DESC1880_ \ desc += "This corresponds to the interrupt generated on the converted value being lower\n"\ desc += "than the programmed lower threshold." %define _DESC1881_ \ desc += "Watchdog Threshold Interrupt Mask Register. This register gives the interrupt\n"\ desc += "mask information for the 16 possible upper/lower threshold limits which can be\n"\ desc += "selected for each channel.\n\n"\ desc += "Note: In case num_watchdog generic parameter is zero, this register is not\n"\ desc += "implemented." %define _DESC1882_ \ desc += "This corresponds to the mask bit for the interrupt generated on the converted\n"\ desc += "value being higher than the programmed higher threshold." %define _DESC1883_ \ desc += "This corresponds to the mask bit for the interrupt generated on the converted\n"\ desc += "value being lower than the programmed lower threshold." %define _DESC1884_ \ desc += "DMA Enable Register. The DMA Enable (DMAE) register sets up the DMA for use\n"\ desc += "with the SARADC.\n\n"\ desc += "Note: In case dma_exist generic parameter is zero, this register are not\n"\ desc += "implemented." %define _DESC1885_ \ desc += "DMA clear sequence enable" %define _DESC1886_ \ desc += "DMA global enable" %define _DESC1887_ \ desc += "Internal Channel DMA Select Register. The DMA select registers to channel\n"\ desc += "association is described below.\n\n"\ desc += "[Internal Channel DMA Select Registers to Channel Association]:\n"\ desc += " Register Register Bits\n"\ desc += " -------- -------------\n"\ desc += " ICDSR0 DS_CH[31:0]\n"\ desc += " ICDSR1 DS_CH[63:32]\n"\ desc += " ICDSR2 DS_CH[95:64]\n"\ desc += "Note: In case dma_exist generic parameter is zero or num_intch is all zeros,\n"\ desc += "all these registers are not implemented and transfer error generated on\n"\ desc += "access.\n\n"\ desc += "As parameter num_intch vector has positional inference for registers ICDSR0-2,\n"\ desc += "such that:\n\n"\ desc += "num_intch(i)(where i:0to31) corresponds to ICDSR0 bit [0to31],\n"\ desc += "num_intch(i)(where i:32to63) corresponds to ICDSR1 bit [0to31] and\n"\ desc += "num_intch(i)(where i:64to95) corresponds to ICDSR2 bit [0to31].\n\n"\ desc += "If any num_intch(i) value is '0', the corresponding bit is not implemented and\n"\ desc += "read access would return '0' on that bit location. Thus, if num_intch[31:0] are\n"\ desc += "all 0s, then register ICDSR0 is not implemented. If num_intch[63:32] are all\n"\ desc += "0s, then register ICDSR1 is not implemented. If num_intch[95:64] are all 0s,\n"\ desc += "then register ICDSR2 is not implemented. Each is treated as reserved space; any\n"\ desc += "access on this space generates transfer error." %define _DESC1888_ \ desc += "DMA select for channel x" %define _DESC1889_ \ desc += "Watchdog Threshold Register. Note: The number of WTHRHLR registers depends on\n"\ desc += "num_watchdog generic parameter configuration.\n\n"\ desc += "In case num_watchdog is zero, these registers are not implemented.\n\n"\ desc += "The length of the threshold field depends on the generic resolution." %define _DESC1890_ \ desc += "High threshold value for channel x" %define _DESC1891_ \ desc += "Low threshold value for channel x" %define _DESC1892_ \ desc += "Conversion Timing Register. " %define _DESC1893_ \ desc += "Conversion Resolution select\n\n"\ desc += "This bit selects the conversion resolution for the conversion." %define _DESC1894_ \ desc += "Precharging phase duration\n\n"\ desc += "This bitfield defines the precharging phase duration to be applied when this\n"\ desc += "phase is enabled by PCE bit of channel data register. This duration is\n"\ desc += "calculated as (PRECHG X 1/Frequency of SARADC clock). Please refer to device\n"\ desc += "datasheet for the minimum duration required for precharging phase." %define _DESC1895_ \ desc += "Sampling phase duration\n\n"\ desc += "This bitfield defines the sampling phase duration to be applied. This duration\n"\ desc += "is calculated as (INPSAMP X 1/Frequency of SARADC clock). Please refer to\n"\ desc += "device datasheet for the minimum duration required for sampling phase." %define _DESC1896_ \ desc += "Internal Channel Normal Conversion Mask Register. The normal conversion mask\n"\ desc += "registers to channel association is described below.\n\n"\ desc += "[Internal Channel Normal Conversion Mask Registers to Channel Association]:\n"\ desc += " Register Register Bits\n"\ desc += " ICNCMR0 NCE_CH[31:0]\n"\ desc += " ICNCMR1 NCE_CH[63:32]\n"\ desc += " ICNCMR2 NCE_CH[95:64]\n"\ desc += "Parameter num_intch vector has positional inference for registers ICNCMR0-2\n"\ desc += "i.e. num_intch(i)(where i:0to31) corres. to ICNCMR0 bit [0to31],\n"\ desc += "num_intch(i)(where i:32to63) corresponds to ICNCMR1 bit [0to31] and\n"\ desc += "num_intch(i)(where i:64to95) corres. to ICNCMR2 bit [0to31]. if any of the\n"\ desc += "num_intch(i) value is '0' corresponding bit is not implemented and read access\n"\ desc += "would return '0' on that bit location. Thus if num_intch[31:0] is all 0's than\n"\ desc += "register ICNCMR0 is not implemented, if num_intch[63:32] is all 0's than\n"\ desc += "register ICNCMR1 is not implemented and similarly if num_intch[95:64] is all\n"\ desc += "0's than register ICNCMR2 is not implemented and treated as reserved space any\n"\ desc += "access on this space generates transfer error." %define _DESC1897_ \ desc += "Normal conversion enable for channel x" %define _DESC1898_ \ desc += "Internal Channel Injected Conversion Mask Register. The injected conversion\n"\ desc += "mask registers to channel association is described below.\n\n"\ desc += "[Internal Channel Normal Conversion Mask Registers to Channel Association]:\n"\ desc += " Register Register Bits\n"\ desc += " ICJCMR0 JCE_CH[31:0]\n"\ desc += " ICJCMR1 JCE_CH[63:32]\n"\ desc += " ICJCMR2 JCE_CH[95:64]\n"\ desc += "Parameter num_intch vector has positional inference for registers ICJCMR0-2\n"\ desc += "i.e. num_intch(i)(where i:0to31) corres. to ICJCMR0 bit [0to31],\n"\ desc += "num_intch(i)(where i:32to63) corresponds to ICJCMR1 bit [0to31] and\n"\ desc += "num_intch(i)(where i:64to95) corres. to ICJCMR2 bit [0to31]. if any of the\n"\ desc += "num_intch(i) value is '0' corresponding bit is not implemented and read access\n"\ desc += "would return '0' on that bit location. Thus if num_intch[31:0] is all 0's than\n"\ desc += "register ICJCMR0 is not implemented, if num_intch[63:32] is all 0's than\n"\ desc += "register ICJCMR1 is not implemented and similarly if num_intch[95:64] is all\n"\ desc += "0's than register ICJCMR2 is not implemented and treated as reserved space any\n"\ desc += "access on this space generates transfer error." %define _DESC1899_ \ desc += "JCE_CH[x]: Injected conversion enable for channel x" %define _DESC1900_ \ desc += "Power Down Exit Delay Register. " %define _DESC1901_ \ desc += "Power down exit delay duration.\n\n"\ desc += "Defines the delay between the power-down bit reset and the starting of\n"\ desc += "conversion. The power-down delay is calculated as [PDED x 1/(SARADC clock\n"\ desc += "frequency)]." %define _DESC1902_ \ desc += "Internal Channel Data Register. The conversion results for each channel is\n"\ desc += "loaded into data registers. Each data register will contain the conversion\n"\ desc += "result, status information related to ADC mode, data valid and some control\n"\ desc += "information to select the required reference voltage, timing parameter\n"\ desc += "selection for each channel.\n\n"\ desc += "Note: The length of the CDATA field depends on the generic resolution.\n\n"\ desc += "As each of ICDRx corresponds to an internal channel inferred through generic\n"\ desc += "num_intch. If any of the num_intch(i) is '0', the corresponding ICDRx is not\n"\ desc += "implemented and any access to it generates transfer error. This register should\n"\ desc += "be accessed 32-bit R/W.\n\n"\ desc += "The REFSEL bit implementation is dependent on parameter vector\n"\ desc += "altref_exists_ch[95:0]." %define _DESC1903_ \ desc += "Reference selection\n\n"\ desc += "This bit can be used to select the reference voltage for channel conversion." %define _DESC1904_ \ desc += "Reserved\n\n"\ desc += "Write of any value has no effect; read value is always zero." %define _DESC1905_ \ desc += "Precharge Enable\n\n"\ desc += "This bit enables the precharging phase during channel conversion." %define _DESC1906_ \ desc += "Reserved.\n\n"\ desc += "Write of any value has no effect; read value is always zero." %define _DESC1907_ \ desc += "This bitfield selects the conversion timing register for each channel to select\n"\ desc += "different precharge and sampling phase durations." %define _DESC1908_ \ desc += "Data valid flag\n\n"\ desc += "This bit is used to notify when the data is valid (a new value has been\n"\ desc += "written). It is automatically cleared when data is read." %define _DESC1909_ \ desc += "Data overwritten flag\n\n"\ desc += "This bit signals that the previous converted data has been overwritten by a new\n"\ desc += "conversion. This functionality depends on the value of MCR[OWREN]:\n\n"\ desc += "When OWREN = 0, OVERW is frozen to 0 and CDATA field is protected against being\n"\ desc += "overwritten until being read. When OWREN = 1, OVERW flags the CDATA field\n"\ desc += "overwrite status." %define _DESC1910_ \ desc += "Conversion result mode status\n\n"\ desc += "This bit reflects the mode of conversion for the corresponding channel." %define _DESC1911_ \ desc += "Channel converted data" %define _DESC1912_ \ desc += "Internal Channel Watchdog Selection Register. These registers contain\n"\ desc += "WSEL_CHx[3:0] bitfields to select the threshold register which provides the\n"\ desc += "values to be used for upper and lower bounds for channel x.\n\n"\ desc += "The Watchdog select registers to channel association is described below.\n\n"\ desc += "[Internal Channel Watchdog Enable Registers to Channel Association]:\n"\ desc += " Register Register Bits\n"\ desc += " ICWSELRx (x = 0 to 11) WSEL_CH[(8*x)+7] .. WSEL_CH[8*x]\n"\ desc += "Note: Each such nibble (i.e., WSEL_CHx) has positional correspondence to\n"\ desc += "num_intch parameter (each channel has a 1:1 nibble correspondence), so each\n"\ desc += "word ICWSELRx corresponds to eight internal channels, thus requiring total\n"\ desc += "twelve 32-bit registers to cover all 96 internal channels. If the value of any\n"\ desc += "num_intch(i) is `0', the corresponding WSEL_CHx nibble is not implmented.\n\n"\ desc += "If both nibbles in a byte-access, all four nibbles in a halfword-access, and\n"\ desc += "all eight nibbles in a word-access are unimplemented, a transfer error is\n"\ desc += "generated." %define _DESC1913_ \ desc += "Watchdog select for channel 7" %define _DESC1914_ \ desc += "Watchdog select for channel 6" %define _DESC1915_ \ desc += "Watchdog select for channel 5" %define _DESC1916_ \ desc += "Watchdog select for channel 4" %define _DESC1917_ \ desc += "Watchdog select for channel 3" %define _DESC1918_ \ desc += "Watchdog select for channel 2" %define _DESC1919_ \ desc += "Watchdog select for channel 1" %define _DESC1920_ \ desc += "Watchdog select for channel 0" %define _DESC1921_ \ desc += "Internal Channel Watchdog Enable Register. The Watchdog enable registers to\n"\ desc += "channel association is described below.\n\n"\ desc += "[Internal Channel Watchdog Enable Registers to Channel Association]:\n"\ desc += " Register Register Bits\n"\ desc += " ICWER0 WEN_CH[31:0]\n"\ desc += " ICWER1 WEN_CH[63:32]\n"\ desc += " ICWER2 WEN_CH[95:64]\n"\ desc += "Parameter num_intch vector has positional inference for registers ICWER0-2:\n\n"\ desc += "- num_intch(i) (where i = 0:31) corresponds to ICWER0 bit [0:31]\n\n"\ desc += "- num_intch(i) (where i = 32:63) corresponds to ICWER1 bit [0:31]\n\n"\ desc += "and\n\n"\ desc += "- num_intch(i) (where i = 64:95) corresponds to ICWER2 bit [0:31]\n\n"\ desc += "If any num_intch(i) value is `0', the corresponding bit is not implemented and\n"\ desc += "read access would return `0' on that bit location.\n\n"\ desc += "Thus,\n\n"\ desc += "- if num_intch[31:0] is all 0's, register ICWER0 is not implemented,\n\n"\ desc += "- if num_intch[63:32] is all 0's, register ICWER1 is not implemented\n\n"\ desc += "and similarly,\n\n"\ desc += "- if num_intch[95:64] is all 0's, register ICWER2 is not implemented and\n"\ desc += "treated as reserved space. Any access on this space generates a transfer\n"\ desc += "error." %define _DESC1922_ \ desc += "Watchdog enable for channel x" %define _DESC1923_ \ desc += "Internal Channel Analog Watchdog Out of Range register. Note: In case either\n"\ desc += "num_watchdog is zero, these registers are not implemented.\n\n"\ desc += "The analog watchdog registers to channel association is described below.\n\n"\ desc += "[Internal Channel Analog Watchdog Registers to Channel Association]:\n"\ desc += " Register Register Bits\n"\ desc += " -------- --------------\n"\ desc += " ICAWORR0 AWOR_CH[31:0]\n"\ desc += " ICAWORR1 AWOR_CH[63:32]\n"\ desc += " ICAWORR2 AWOR_CH[95:64]\n"\ desc += "Parameter num_intch vector has positional inference for registers ICAWORR0 -\n"\ desc += "ICAWORR2:\n\n"\ desc += "- num_intch(i) (where i = 0:31) corresponds to ICAWORR0 bit [0:31]\n\n"\ desc += "- num_intch(i) (where i = 32:63) corresponds to ICAWORR1 bit [0:31]\n\n"\ desc += "- num_intch(i) (where i = 64:95) corresponds to ICAWORR2 bit [0:31]\n\n"\ desc += "If any of the num_intch(i) value is '0', the corresponding bit is not\n"\ desc += "implemented and read access would return '0' on that bit location.\n\n"\ desc += "Thus,\n\n"\ desc += "- if num_intch[31:0] is all 0's, register ICAWORR0 is not implemented\n\n"\ desc += "- if num_intch[63:32] is all 0's, register ICAWORR1 is not implemented and\n"\ desc += "similarly,\n\n"\ desc += "- if num_intch[95:64] is all 0's, register ICAWORR2 is not implemented and\n"\ desc += "treated as reserved space. Any access on this space generates a transfer\n"\ desc += "error.\n\n"\ desc += "" %define _DESC1924_ \ desc += "AWOR_CH[x]: Analog watchdog out of range status for channel x" %define _DESC1925_ \ desc += "Test Channel Interrupt Pending Register. The interrupt channel register to\n"\ desc += "channel association is described below.\n\n"\ desc += "[TCIPR Register to Channel Association]:\n"\ desc += " Register Register Bits\n"\ desc += " TCIPR EOC_CH[127:96]\n"\ desc += "Parameter num_testch vector has positional inference for registers TCIPR:\n\n"\ desc += "- num_testch(i) (where i = 0:31) corresponds to TCIPR bit [0:31]\n\n"\ desc += "If any of the num_testch(i) value is '0', the corresponding bit is not\n"\ desc += "implemented and read access would return '0' on that bit location. Thus,\n\n"\ desc += "- if num_testch is all 0's, register TCIPR is not implemented and treated as\n"\ desc += "reserved space. Any access on this space generates a transfer error." %define _DESC1926_ \ desc += "Test Channel Interrupt Mask Register. The interrupt mask register to channel\n"\ desc += "association is described below.\n\n"\ desc += "[Test Channel Interrupt Mask Register to Channel Association]:\n"\ desc += " Register Register Bits\n"\ desc += " TCIMR IM_CH[127:96]\n"\ desc += "Parameter num_testch vector has positional inference for registers TCIMR:\n\n"\ desc += "- num_testch(i) (where i = 0:31) corresponds to TCIMR bit [0:31]\n\n"\ desc += "If any of the num_testch(i) value is '0', the corresponding bit is not\n"\ desc += "implemented and read access would return '0' on that bit location. Thus,\n\n"\ desc += "- if the complete num_testch is all 0's, TCIMR register is not implemented and\n"\ desc += "treated as reserved space. Any access on this space generates a transfer\n"\ desc += "error." %define _DESC1927_ \ desc += "Test Channel DMA Select Register. The DMA select registers to channel\n"\ desc += "association is described below.\n\n"\ desc += "[Test Channel DMA Select Registers to Channel Association]:\n"\ desc += " Register Register Bits 31 : 0\n"\ desc += " TCDSR DS_CH[127:96]\n"\ desc += "In case either dma_exist generic parameter is zero or num_testch is zero, these\n"\ desc += "registers are not implemented.\n\n"\ desc += "Note:\n\n"\ desc += "Parameter num_testch vector has positional inference for register TCDSR:\n\n"\ desc += "- num_testch(i) (where i = 0:31) corresponds to TCDSR bit [0:31]\n\n"\ desc += "If any of the num_testch(i) value is '0', the corresponding bit is not\n"\ desc += "implemented and read access would return '0' on that bit location. Thus,\n\n"\ desc += "- if the complete num_testch is all 0's, TCDSR register is not implemented and\n"\ desc += "treated as reserved space. Any access on this space generates a transfer\n"\ desc += "error." %define _DESC1928_ \ desc += "Test Channel Normal Conversion Mask Register. The normal conversion mask\n"\ desc += "register to channel association is described below.\n\n"\ desc += "[Test Channel Normal Conversion Mask Register to Channel Association]:\n"\ desc += " Register Register Bits 31 : 0\n"\ desc += " TCNCMR NCE_CH[127:96]\n"\ desc += "Parameter num_testch vector has positional inference for registers TCNCMR\n\n"\ desc += "- num_testch(i) (where i = 0:31) corresponds to TCNCMR bit [0:31]\n\n"\ desc += "If any of the num_testch(i) value is '0', the corresponding bit is not\n"\ desc += "implemented and read access would return '0' on that bit location. Thus,\n\n"\ desc += "- if the complete num_testch is all 0's, TCNCMR register is not implemented and\n"\ desc += "treated as reserved space. Any access on this space generates a transfer\n"\ desc += "error." %define _DESC1929_ \ desc += "Test Channel Injected Conversion Mask Register. The injected conversion mask\n"\ desc += "register to channel association is described below.\n\n"\ desc += "[Test Channel Normal Conversion Mask Register to Channel Association]:\n"\ desc += " Register Register Bits 31 : 0\n"\ desc += " TCJCMR JCE_CH[127:96]\n"\ desc += "Parameter num_testch vector has positional inference for registers TCJCMR\n\n"\ desc += "- num_testch(i) (where i = 0:31) corresponds to TCJCMR bit [0:31]\n\n"\ desc += "If any of the num_testch(i) value is '0', the corresponding bit is not\n"\ desc += "implemented and read access would return '0' on that bit location. Thus,\n\n"\ desc += "- if the complete num_testch is all 0's, TCJCMR register is not implemented and\n"\ desc += "treated as reserved space. Any access on this space generates a transfer\n"\ desc += "error." %define _DESC1930_ \ desc += "Test Channel Watchdog Selection Register. This register contains WSEL_CHx[3:0]\n"\ desc += "bitfields to select the threshold register which provides the values to be used\n"\ desc += "for upper and lower bounds for channel x.\n\n"\ desc += "The Watchdog select register to channel association is described below.\n\n"\ desc += "[Test Channel Watchdog Select Registers to Channel Association]:\n"\ desc += " Register Register Bits 31 : 0\n"\ desc += " TCWSELR0 WSEL_CH[103] .. WSEL_CH[96]\n"\ desc += " TCWSELR1 WSEL_CH[111] .. WSEL_CH[104]\n"\ desc += " TCWSELR2 WSEL_CH[119] .. WSEL_CH[112]\n"\ desc += " TCWSELR3 WSEL_CH[127] .. WSEL_CH[120]\n"\ desc += "Number of bits implemented for each WSEL_CHx depends on num_watchdog parameter.\n"\ desc += "If num_watchdog > 8, the number of bits implemented will be 4 (i.e.\n"\ desc += "WSEL_CHx[3:0]). If num_watchdog > 4 but 1 but <= 4, the number of bits\n"\ desc += "implemented will be 2 (i.e. WSEL_CHx[3:2] will be reserved).If num_watchdog =1,\n"\ desc += "only 1 bit is present.\n\n"\ desc += "Each such nibble(i.e., WSEL_CHx) has positional correspondance to num_testch\n"\ desc += "parameter (each channel has a 1:1 nibble correspondance), so each word TCWSELRx\n"\ desc += "corresponds to eight test Channels, thus requiring total four 32-bit registers\n"\ desc += "to cover all 32 test channels. If value of any num_testch(i) is '0', the\n"\ desc += "corresponding WSEL_CHx nibble is not implemented.\n\n"\ desc += "If both nibbles in a byte-access, all four nibbles in a halfword-access, and\n"\ desc += "all eight nibbles in a word-access are unimplemented, a transfer error is\n"\ desc += "generated." %define _DESC1931_ \ desc += "Watchdog select for channel a" %define _DESC1932_ \ desc += "Watchdog select for channel b" %define _DESC1933_ \ desc += "Watchdog select for channel c" %define _DESC1934_ \ desc += "Watchdog select for channel d" %define _DESC1935_ \ desc += "Watchdog select for channel e" %define _DESC1936_ \ desc += "Watchdog select for channel f" %define _DESC1937_ \ desc += "Watchdog select for channel g" %define _DESC1938_ \ desc += "Watchdog select for channel h" %define _DESC1939_ \ desc += "Test Channel Watchdog Enable Register. The Watchdog enable registers to channel\n"\ desc += "association is described below.\n\n"\ desc += "[Test Channel Watchdog Enable Registers to Channel Association]:\n"\ desc += " Register Register Bits 31 : 0\n"\ desc += " TCWENR WEN_CH[127:96]\n"\ desc += "Parameter num_testch vector has positional inference for registers TCWENR:\n\n"\ desc += "- num_testch(i) (where i = 0:31) corresponds to TCWENR bit [0:31].\n\n"\ desc += "If any of the num_testch(i) value is '0', the corresponding bit is not\n"\ desc += "implemented and read access would return '0' on that bit location. Thus,\n\n"\ desc += "- if the complete num_testch is all 0's, TCWENR register is not implemented and\n"\ desc += "treated as reserved space. Any access on this space generates a transfer\n"\ desc += "error." %define _DESC1940_ \ desc += "Test Channel Analog Watchdog Out of Range Register. The analog watchdog\n"\ desc += "registers to channel association is described below.\n\n"\ desc += "[Analog Watchdog Register to Channel Association]:\n"\ desc += " Register Register Bits 31 : 0\n"\ desc += " TCAWORR AWOR_CH[127:96]\n"\ desc += "Note: In case either of num_watchdog is zero, these registers are not\n"\ desc += "implemented.\n\n"\ desc += "Parameter num_testch vector has positional inference for registers TCAWORR:\n\n"\ desc += "- num_testch(i) (where i = 0:31) corresponds to TCAWORR bit [0:31].\n\n"\ desc += "If any of the num_testch(i) value is '0', the corresponding bit is not\n"\ desc += "implemented and read access would return '0' on that bit location. Thus,\n\n"\ desc += "- if the complete num_testch is all 0's, TCAWORR register is not implemented\n"\ desc += "and treated as reserved space. Any access on this space generates a transfer\n"\ desc += "error." %define _DESC1941_ \ desc += "Test Channel Connection with Analog Pin Register. Each test channel can be\n"\ desc += "shorted with any internal analog channel using the configuration programmed in\n"\ desc += "these registers.\n\n"\ desc += "Test channel short registers to channel association is described below.\n\n"\ desc += "\n\n"\ desc += "See reference manual for 'Test Channel Short Registers to Channel Association'\n"\ desc += "table. Parameter num_testch vector has positional inference for registers\n"\ desc += "TCCAPRx:\n\n"\ desc += "- num_testch(i) (where i = 0:3) corresponds to TCCAPR0,\n\n"\ desc += "- num_testch(i) (where i = 4:7) corresponds to TCCAPR1,\n\n"\ desc += "and so on through\n\n"\ desc += "- num_testch(i) (where i = 28:31) corresponds to TCCAPR7.\n\n"\ desc += "If all the num_testch[3:0] values are '0', the TCCAPR0 is not implemented, and\n"\ desc += "so on, up to if all num_testch[31:28] values are '0' TCCAPR7 is not implemented\n"\ desc += "and treated as reserved space. Any access on this space generates transfer\n"\ desc += "error." %define _DESC1942_ \ desc += "Enable short with internal channel for test channel 3" %define _DESC1943_ \ desc += "Internal channel selection for short with test channel 3" %define _DESC1944_ \ desc += "Enable short with internal channel for test channel 2" %define _DESC1945_ \ desc += "Internal channel selection for short with test channel 2" %define _DESC1946_ \ desc += "Enable short with internal channel for test channel 1" %define _DESC1947_ \ desc += "Internal channel selection for short with test channel 1" %define _DESC1948_ \ desc += "Enable short with internal channel for test channel 0" %define _DESC1949_ \ desc += "Internal channel selection for short with test channel 0" %define _DESC1950_ \ desc += "Test Channel Data Register. The conversion results for each channel is loaded\n"\ desc += "into data registers. Each data register will contain the conversion result,\n"\ desc += "status information related to ADC mode, data valid and some control information\n"\ desc += "to select the required reference voltage, timing parameter selection for each\n"\ desc += "channel.\n\n"\ desc += "The length of the CDATA field depends on the generic resolution. As each of\n"\ desc += "TCDRx corresponds to an test channel inferred through generic num_testch. If\n"\ desc += "any of the num_testch(i) is '0' than corresponding TCDRx is not implemented and\n"\ desc += "any access to it generates transfer error. These registers are accessed 32-bit\n"\ desc += "R/W.\n\n"\ desc += "The REFSEL bit implementation is dependent on parameter vector\n"\ desc += "altref_exists_ch[127:96]." %define _DESC1951_ \ desc += "Precharge Enable\n\n"\ desc += "This bit enables the precharging phase during channel conversion.\n\n"\ desc += "0 Precharge phase is disabled\n\n"\ desc += "1 Precharge phase is enabled" %define _DESC1952_ \ desc += "External Channel Decode Signals Delay Register. If parameter num_extch is all\n"\ desc += "0's, ECDSDR is not implemented, and treated as reserved space. Any access on\n"\ desc += "this space generates transfer error." %define _DESC1953_ \ desc += "Decode signals delay\n\n"\ desc += "This bitfield defines the delay between the external decode signals and the\n"\ desc += "start of the sampling phase. It is used to take into account of the settling\n"\ desc += "time required for the external mux. The decode signal delay is calculated as\n"\ desc += "(DSD X 1/Frequency of SARADC clock)." %define _DESC1954_ \ desc += "External Channel Interrupt Pending Register. The interrupt channel register to\n"\ desc += "channel association is described below.\n\n"\ desc += "[ECIPR0-3 Registers to Channel Association]:\n"\ desc += " Register Register Bits 31 : 0\n"\ desc += " ECIPR0 EOC_CH[159:128]\n"\ desc += " ECIPR1 EOC_CH[191:160]\n"\ desc += " ECIPR2 EOC_CH[223:192]\n"\ desc += " ECIPR3 EOC_CH[255:224]\n"\ desc += "Parameter num_extch vector has positional inference for registers ECIPR0-3\n\n"\ desc += "- num_extch(i) (where i = 0:31) corresponds to ECIPR0 bit [0:31]\n\n"\ desc += "- num_extch(i) (where i = 32:63) corresonds to ECIPR1 bit [0:31]\n\n"\ desc += "- num_extch(i) (where i = 64:95) corresponds to ECIPR2 bit [0:31] and\n\n"\ desc += "- num_extch(i) (where i = 96:127) corresponds to ECIPR3 bit [0:31].\n\n"\ desc += "If any of the num_extch(i) value is '0', the corresponding bit is not\n"\ desc += "implemented and read access would return '0' on that bit location.\n\n"\ desc += "Thus,\n\n"\ desc += "- if any/all of num_extch[31:0]/[63:32]/[95:64]/[127:96] is all '0's, the\n"\ desc += "access to corresponding register(s) i.e. ECIPR0/1/2/3 would generate transfer\n"\ desc += "error." %define _DESC1955_ \ desc += "External Channel Interrupt Mask Register. The interrupt mask register to\n"\ desc += "channel association is described below.\n\n"\ desc += "[External Channel Interrupt Mask Registers to Channel Association]:\n"\ desc += " Register Register Bits 31 : 0\n"\ desc += " ECIMR0 IM_CH[159:128]\n"\ desc += " ECIMR1 IM_CH[191:160]\n"\ desc += " ECIMR2 IM_CH[223:192]\n"\ desc += " ECIMR3 IM_CH[255:224]\n"\ desc += "Parameter num_extch vector has positional inference for registers ECIMR0-3\n\n"\ desc += "- num_extch(i) (where i = 0:31) corresponds to ECIMR0 bit [0:31]\n\n"\ desc += "- num_extch(i) (where i = 32:63) corresponds to ECIMR1 bit [0:31]\n\n"\ desc += "- num_extch(i) (where i = 64:95) corresponds to ECIMR2 bit [0:31] and\n\n"\ desc += "- num_extch(i) (where i = 96:127) corresponds to ECIMR3 bit [0:31].\n\n"\ desc += "If any of the num_extch(i) value is '0', the corresponding bit is not\n"\ desc += "implemented and read access would return '0' on that bit location.\n\n"\ desc += "Thus,\n\n"\ desc += "- if any/all of num_extch[31:0]/[63:32]/[95:64]/[127:96] is all '0's then\n"\ desc += "access to corresponding register(s) i.e. ECIMR0/1/2/3 would generate transfer\n"\ desc += "error." %define _DESC1956_ \ desc += "External Channel DMA Select Register. The DMA select registers to channel\n"\ desc += "association is described below.\n\n"\ desc += "[DMA Select Registers to Channel Association]:\n"\ desc += " Register Register Bits 31:0\n"\ desc += " -------- ------------------\n"\ desc += " ECDSR0 DS_CH[159:128]\n"\ desc += " ECDSR1 DS_CH[191:160]\n"\ desc += " ECDSR2 DS_CH[223:192]\n"\ desc += " ECDSR3 DS_CH[255:224]\n"\ desc += "Note: In case either dma_exist generic parameter is zero or num_extch is zero,\n"\ desc += "these registers are not implemented.\n\n"\ desc += "Parameter num_extch vector has positional inference for registers ECDSR0-3:\n\n"\ desc += "- num_extch(i) (where i = 0:31) corresponds to ECDSR0 bit [0:31]\n\n"\ desc += "- num_extch(i) (where i = 32:63) corresponds to ECDSR1 bit [0:31]\n\n"\ desc += "- num_extch(i) (where i = 64:95) corresponds to ECDSR2 bit [0:31] and\n\n"\ desc += "- num_extch(i) (where i = 96:127) corresponds to ECDSR3 bit [0to31].\n\n"\ desc += "If any of the num_extch(i) value is '0', the corresponding bit is not\n"\ desc += "implemented and read access would return '0' on that bit location.\n\n"\ desc += "Thus,\n\n"\ desc += "- if any/all of num_extch[31:0]/[63:32]/[95:64]/[127:96] is all '0's, the\n"\ desc += "access to corresponding register(s) i.e. ECDSR0/1/2/3 would generate transfer\n"\ desc += "error." %define _DESC1957_ \ desc += "External Channel Normal Conversion Mask Register. The normal conversion mask\n"\ desc += "registers to channel association is described below.\n\n"\ desc += "[External Channel Normal Conversion Mask Registers to Channel Association]:\n"\ desc += " Register Register Bits 31 : 0\n"\ desc += " ECNCMR0 NCE_CH[159:128]\n"\ desc += " ECNCMR1 NCE_CH[191:160]\n"\ desc += " ECNCMR2 NCE_CH[223:192]\n"\ desc += " ECNCMR3 NCE_CH[255:224]\n"\ desc += "Parameter num_extch vector has positional inference for registers ECNCMR0-3:\n\n"\ desc += "- num_extch(i) (where i = 0:31) corresponds to ECNCMR0 bit [0:31]\n\n"\ desc += "- num_extch(i) (where i = 32:63) corresponds to ECNCMR1 bit [0:31]\n\n"\ desc += "- num_extch(i) (where i = 64:95) corresponds to ECNCMR2 bit [0:31] and\n\n"\ desc += "- num_extch(i) (where i = 96:127) corresponds to ECNCMR3 bit [0to31].\n\n"\ desc += "If any of the num_extch(i) value is '0', the corresponding bit is not\n"\ desc += "implemented and read access would return '0' on that bit location.\n\n"\ desc += "Thus,\n\n"\ desc += "- if any/all of num_extch[31:0]/[63:32]/[95:64]/[127:96] is all '0's, the\n"\ desc += "access to corresponding register(s) i.e. ECNCMR0/1/2/3 would generate transfer\n"\ desc += "error." %define _DESC1958_ \ desc += "External Channel Injected Conversion Mask Register. The injected conversion\n"\ desc += "mask registers to channel association is described below.\n\n"\ desc += "[External Channel Normal Conversion Mask Registers to Channel Association]:\n"\ desc += " Register Register Bits 31:0\n"\ desc += " -------- ------------------\n"\ desc += " ECJCMR0 JCE_CH[159:128]\n"\ desc += " ECJCMR1 JCE_CH[191:160]\n"\ desc += " ECJCMR2 JCE_CH[223:192]\n"\ desc += " ECJCMR3 JCE_CH[255:224]\n"\ desc += "Parameter num_extch vector has positional inference for registers ECJCMR0-3:\n\n"\ desc += "- num_extch(i) (where i = 0:31) corresponds to ECJCMR0 bit [0:31]\n\n"\ desc += "- num_extch(i) (where i = 32:63) corresponds to ECJCMR1 bit [0:31]\n\n"\ desc += "- num_extch(i) (where i = 64:95) corresponds to ECJCMR2 bit [0:31] and\n\n"\ desc += "- num_extch(i) (where i = 96:127) corresponds to ECJCMR3 bit [0:31].\n\n"\ desc += "If any of the num_extch(i) value is '0', the corresponding bit is not\n"\ desc += "implemented and read access would return '0' on that bit location.\n\n"\ desc += "If any/all of num_extch[31:0]/[63:32]/[95:64]/[127:96] are all '0's, the access\n"\ desc += "to the corresponding register(s) i.e. ECJCMR0/1/2/3 would generate transfer\n"\ desc += "error." %define _DESC1959_ \ desc += "External Channel Watchdog Selection Register. These registers contain\n"\ desc += "WSEL_CHx[3:0] bitfields to select the threshold register which provides the\n"\ desc += "values to be used for upper and lower bounds for channel x.\n\n"\ desc += "The Watchdog select registers to channel association is described below.\n\n"\ desc += "[External Channel Watchdog Enable Registers to Channel Association]:\n"\ desc += " Register Register Bits 31 : 0\n"\ desc += " ECWSELRx (x = 0 to 15) WSEL_CH[(8*x)+135] .. WSEL_CH[(8*x)+128]]\n"\ desc += "Number of bits implemented for each WSEL_CHx depends on num_watchdog\n"\ desc += "parameter:\n\n"\ desc += "If num_watchdog > 8, the number of bits implemented will be 4 (i.e.\n"\ desc += "WSEL_CHx[3:0]).\n\n"\ desc += "If num_watchdog > 4 but <= 8, the number of bits implemented will be 3 (i.e.\n"\ desc += "WSEL_CHx[3] will be reserved).\n\n"\ desc += "Similarly, if num_watchdog >1 but <= 4, then number of bits implemented will be\n"\ desc += "2 (i.e. WSEL_CHx[3:2] will be reserved).\n\n"\ desc += "If num_watchdog =1, then only 1 bit is present.\n\n"\ desc += "Each such nibble (i.e. WSEL_CHx) has positional correspondence to num_extch\n"\ desc += "parameter (each channel has a 1:1 nibble correspondance), so each word ECWSELRx\n"\ desc += "corresponds to eight external channels, thus requiring a total sixteen 32-bit\n"\ desc += "registers to cover all 128 external channels. If value of any num_extch(i) is\n"\ desc += "'0', the corresponding WSEL_CHx nibble is not implemented.\n\n"\ desc += "If both nibbles in a byte-access, all four nibbles in a halfword-access, and\n"\ desc += "all eight nibbles in a word-access are unimplemented, a transfer error is\n"\ desc += "generated." %define _DESC1960_ \ desc += "External Channel Watchdog Enable Register. The Watchdog enable registers to\n"\ desc += "channel association is described below.\n\n"\ desc += "[External Channel Watchdog Enable Registers to Channel Association]:\n"\ desc += " Register Register Bits 31:0\n"\ desc += " -------- ------------------\n"\ desc += " ECWER0 WEN_CH[159:128]\n"\ desc += " ECWER1 WEN_CH[191:160]\n"\ desc += " ECWER2 WEN_CH[223:192]\n"\ desc += " ECWER3 WEN_CH[255:224]\n"\ desc += "Parameter num_extch vector has positional inference for registers ECWER0-3:\n\n"\ desc += "- num_extch(i) (where i = 0:31) corresponds to ECWER0 bit [0:31]\n\n"\ desc += "- num_extch(i) (where i = 32:63) corresponds to ECWER1 bit [0:31]\n\n"\ desc += "- num_extch(i) (where i = 64:95) corresponds to ECWER2 bit [0:31], and\n\n"\ desc += "- num_extch(i) (where i = 96:127) corresponds to ECWER3 bit [0:31].\n\n"\ desc += "If any num_extch(i) value is '0', the corresponding bit is not implemented and\n"\ desc += "read access would return '0' on that bit location.\n\n"\ desc += "If any/all of num_extch[31:0]/[63:32]/[95:64]/[127:96] are '0', the access to\n"\ desc += "corresponding register(s) i.e. ECWER0/1/2/3 would generate transfer error." %define _DESC1961_ \ desc += "External Channel Analog Watchdog Out of Range register. The analog watchdog\n"\ desc += "registers to channel association is described below.\n\n"\ desc += "[External Channel Analog Watchdog Registers to Channel Association]:\n"\ desc += " Register Register Bits 31:0\n"\ desc += " -------- ------------------\n"\ desc += " ECAWORR0 AWOR_CH[159:128]\n"\ desc += " ECAWORR1 AWOR_CH[191:160]\n"\ desc += " ECAWORR2 AWOR_CH[223:192]\n"\ desc += " ECAWORR3 AWOR_CH[255:224]\n"\ desc += "Note: In case either num_watchdog is zero, these registers are not\n"\ desc += "implemented.\n\n"\ desc += "Parameter num_extch vector has positional inference for registers ECAWORR0-3:\n\n"\ desc += "- num_extch(i) (where i = 0:31) corresponds to ECAWORR0 bit [0:31]\n\n"\ desc += "- num_extch(i) (where i = 32:63) corresponds to ECAWORR1 bit [0:31]\n\n"\ desc += "- num_extch(i) (where i = 64:95) corresponds to ECAWOERR2 bit [0:31]\n\n"\ desc += "- num_extch(i) (where i = 96:127) corresponds to ECAWORR3 bit [0:31].\n\n"\ desc += "If any num_extch(i) value is '0', the corresponding bit is not implemented and\n"\ desc += "read access would return '0' on that bit location.\n\n"\ desc += "If any/all of num_extch[31:0]/[63:32]/[95:64]/[127:96] are '0', then access to\n"\ desc += "corresponding register(s) i.e. ECAWORR0/1/2/3 would generate transfer errorr." %define _DESC1962_ \ desc += "External Channel Mapping to Internal Channel Register. Each set of 8 external\n"\ desc += "channels can be mapped with any internal analog channel using the configuration\n"\ desc += "programmed in these registers.\n\n"\ desc += "See reference manual for 'Test Channel Short Registers to Channel Association'\n"\ desc += "table. Parameter num_extch vector has positional inference for registers\n"\ desc += "ECMICR0-3:\n\n"\ desc += "- num_extch(i) (where i = 0:31) corresponds to ECMICR0\n\n"\ desc += "- num_extch(i) (where i = 32:63) corresponds to ECMICR1\n\n"\ desc += "- num_extch(i) (where i = 64:95) corresponds to ECMICR2, and\n\n"\ desc += "- num_extch(i) (where i = 96:127) corresponds to ECMICR3.\n\n"\ desc += "If any/all of num_extch[31:0]/[63:32]/[95:64]/[127:96], these parameter slices\n"\ desc += "are all '0's, the access to corresponding register(s) i.e.ECMICR0/1/2/3 would\n"\ desc += "generatetransfer error." %define _DESC1963_ \ desc += "Internal channel selection for external channels (128 + 8x) to (135+8*x) where\n"\ desc += "x = 0,1,2..16" %define _DESC1964_ \ desc += "External Channel Data Register. The conversion results for each channel is\n"\ desc += "loaded into data registers. Each data register will contain the conversion\n"\ desc += "result, status information related to ADC mode, data valid and some control\n"\ desc += "information to select the required reference voltage, timing parameter\n"\ desc += "selection for each channel.\n\n"\ desc += "The length of the CDATA field depends on the generic resolution. As each of\n"\ desc += "ECDRx corresponds to an external channel inferred through generic num_extch. If\n"\ desc += "the value of any num_extch(i) is '0', the corresponding ECDRx is not\n"\ desc += "implemented. Any access on this space generates transfer error. This register\n"\ desc += "should be accessed 32-bit R/W.\n\n"\ desc += "The REFSEL bit implementation is dependent on parameter vector\n"\ desc += "altref_exists_ch[255:128]." %define _DESC1965_ \ desc += "Module Configuration Register. The Module Configuration register (MCR) consists\n"\ desc += "of different control bits to select the operating modes and various\n"\ desc += "configuration settings which define the behavior of the SDADC block." %define _DESC1966_ \ desc += "Programmable Decimation Rate\n\n"\ desc += "This field selects the over-sampling ratio to be applied to support different\n"\ desc += "passbands with a fixed input sampling clock. The output data rate f d is equal\n"\ desc += "to f s / (2xOSR), where fs is the input sampling clock frequency." %define _DESC1967_ \ desc += "Programmable Gain\n\n"\ desc += "This field selects the gain to be applied to the analog input stage of the\n"\ desc += "SDADC. The effective analog input becomes the input voltage level multiplied by\n"\ desc += "the gain factor." %define _DESC1968_ \ desc += "External Modulator Selection" %define _DESC1969_ \ desc += "High Pass Filter Enable" %define _DESC1970_ \ desc += "Watchdog Enable\n\n"\ desc += "This bit enables the WDG monitor." %define _DESC1971_ \ desc += "Trigger Edge Selection" %define _DESC1972_ \ desc += "Trigger Enable\n\n"\ desc += "This field enables the hardware trigger input to initiate a fresh conversion.\n"\ desc += "Upon receiving a trigger event, SDADC reset input is asserted and deasserted\n"\ desc += "synchronously with respect to the peripheral clock. The reset pulse width is\n"\ desc += "fixed to four peripheral clock cycles. The trigger event is ignored if the\n"\ desc += "SDADC internal modulator is not enabled (MCR[EN] = 0) ." %define _DESC1973_ \ desc += "Trigger Input Selection\n\n"\ desc += "This field selects which input will be used for hardware-triggered\n"\ desc += "conversions." %define _DESC1974_ \ desc += "Freeze\n\n"\ desc += "This field enables stopping the SDADC conversions at the end of the current\n"\ desc += "channel conversion when the chip enters debug mode.\n\n"\ desc += "When the chip enters debug mode, further conversions by the SDADC analog block\n"\ desc += "will be stopped, and converted data output from the SDADC analog block are\n"\ desc += "ignored. The ongoing channel conversion will be completed and the converted\n"\ desc += "data is stored. When the chip exits debug mode, SDADC resumes the job that was\n"\ desc += "left before halting the conversions." %define _DESC1975_ \ desc += "Common Voltage Bias Selection\n\n"\ desc += "This field selects the common voltage bias for the negative input terminal of\n"\ desc += "the SDADC during single-ended mode (MODE = 1)." %define _DESC1976_ \ desc += "Wrap-Around Mode\n\n"\ desc += "This bit selects the wraparound mechanism for conversion of programmed sequence\n"\ desc += "of channels." %define _DESC1977_ \ desc += "This bit selects the accurate gain error mode, and must be set during gain\n"\ desc += "error calibration as well as during conversions requiring accurate gain error\n"\ desc += "mode. It can be kept '0' if gain error calibration mode is not needed." %define _DESC1978_ \ desc += "Mode selection" %define _DESC1979_ \ desc += "Enable for SDADC block" %define _DESC1980_ \ desc += "Channel Selection Register. The Channel Selection Register (CSR) selects analog\n"\ desc += "inputs AN[0:7] to be connected to positive and negative terminals of the SDADC\n"\ desc += "and controls the biasing of analog inputs to half-scale bias through 100 kOhm\n"\ desc += "resistance." %define _DESC1981_ \ desc += "Bias enable\n\n"\ desc += "If BIASEN[i] = 1, analog input AN[i] (could be single-ended input or\n"\ desc += "differential analog input) is connected to half-scale bias through a 100 kOhm\n"\ desc += "resistor." %define _DESC1982_ \ desc += "Analog Channel Selection Wraparound Value (ANCHSEL_WRAP)\n\n"\ desc += "When in wraparound mode, this field indicates the maximum value of the\n"\ desc += "wraparound counter, after which it will wrap around back to initial value 000.\n"\ desc += "This value should be programmed before enabling wraparound mechanism\n"\ desc += "(MCR[WRMODE] = 1)." %define _DESC1983_ \ desc += "Analog Channel Selection(ANCHSEL)\n\n"\ desc += "Based on single-ended or differential mode of operation (MCR[MODE]), common\n"\ desc += "mode voltage selection (MCR[VCOMSEL]), this field defines the connectivity of\n"\ desc += "analog inputs to either positive or negative polarity terminals of the SDADC\n"\ desc += "according to the following table.\n\n"\ desc += "Wraparound Mode:\n\n"\ desc += "This field also indicates the initial entry value for the first loop of the\n"\ desc += "wraparound sequence from where the wraparound counter will start incrementing\n"\ desc += "when wraparound mode is entered (when wraparound mechanism enabled (MCR[WRMODE]\n"\ desc += "= 1)). If this field is written any time during wraparound mode (when\n"\ desc += "MCR[WRMODE] = 1), the present value of the wraparound counter will be updated\n"\ desc += "with the value of ANCHSEL - the next trigger will act on the updated channel,\n"\ desc += "and the next increment will be on the updated channel. Here, the value of\n"\ desc += "ANCHSEL chosen should be < ANCHSEL_WRAP; otherwise it will be ignored by\n"\ desc += "hardware. Wraparound will always be from initial counter value 000. \n"\ desc += "[Analog input AN[0:7] selection]:\n"\ desc += " MODE VCOMSEL ANCHSEL INP (positive terminal) INM (negative terminal)\n"\ desc += " ---- ------- ------- ----------------------- -----------------------\n"\ desc += " 1 0 000 AN[0] VREFN\n"\ desc += " 001 AN[1]\n"\ desc += " 010 AN[2]\n"\ desc += " 011 AN[3]\n"\ desc += " 100 AN[4]\n"\ desc += " 101 AN[5]\n"\ desc += " 110 AN[6]\n"\ desc += " 111 AN[7]\n"\ desc += " 1 000 AN[0] VREFP/2\n"\ desc += " 001 AN[1]\n"\ desc += " 010 AN[2]\n"\ desc += " 011 AN[3]\n"\ desc += " 100 AN[4]\n"\ desc += " 101 AN[5]\n"\ desc += " 110 AN[6]\n"\ desc += " 111 AN[7]\n"\ desc += " 0 0/1 000 AN[0] AN[1]\n"\ desc += " 001 AN[2] AN[3]\n"\ desc += " 010 AN[4] AN[5]\n"\ desc += " 011 AN[6] AN[7]\n"\ desc += " 100 VREFN VREFN\n"\ desc += " 101 VREFP/2 VREFP/2\n"\ desc += " 110 VREFP VREFN\n"\ desc += " 111 VREFN VREFP\n" %define _DESC1984_ \ desc += "Reset Key Register. The Reset Key Register (RKR) is the target for a predefined\n"\ desc += "key write operation used to reset the SDADC to start a fresh conversion." %define _DESC1985_ \ desc += "Reset Key\n\n"\ desc += "This field, when written with 0x5AF0, is used to generate the reset for the\n"\ desc += "SDADC block and to reload the internal counter with the start value programmed\n"\ desc += "in OSDR. Any write access to this register which is different from the\n"\ desc += "predefined key is ignored. Read access will always return the inverted key." %define _DESC1986_ \ desc += "Status Flag Register. The Status Flag Register (SFR) contains status and flag\n"\ desc += "bits. These bits are set by hardware and reflect the status of the SDADC and\n"\ desc += "indicate the occurrence of events that may generate an interrupt or a DMA\n"\ desc += "request. Software can clear some flags by writing '1' to those bits. Writing a\n"\ desc += "'0' to a flag has no effect." %define _DESC1987_ \ desc += "Analog Channel Selection Counter(ANCHSEL_CNT)\n\n"\ desc += "This field reflects the current value of the internal Analog Channel Selection\n"\ desc += "Counter. It indicates the present number of the channel selected through the\n"\ desc += "analog multiplexer." %define _DESC1988_ \ desc += "Data FIFO Empty Flag\n\n"\ desc += "This field is asserted when there is no dataword in the FIFO." %define _DESC1989_ \ desc += "Watchdog Upper Threshold Cross Over Event\n\n"\ desc += "This field is set when Converted Data crosses Upper Threshold of WDG. It can be\n"\ desc += "cleared by software writing '1' to clear." %define _DESC1990_ \ desc += "Watchdog Lower Threshold Cross Over Event\n\n"\ desc += "This field is set when Converted Data crosses Lower Threshold of WDG. It can be\n"\ desc += "cleared by software writing '1' to clear." %define _DESC1991_ \ desc += "Converted Data Valid Flag\n\n"\ desc += "This field gives the actual status of data coming from the SDADC block. The\n"\ desc += "converted data is not valid or is corrupted whenever there is a change in\n"\ desc += "configuration settings determined by MCR, channel selection programmed in CSR.\n"\ desc += "Any write access to the registers MCR and CSR will reset this flag. This flag\n"\ desc += "is set automatically after generating SDADC reset and internal timer counts OSD\n"\ desc += "cycles of output clock fd." %define _DESC1992_ \ desc += "Data FIFO Overrun Flag\n\n"\ desc += "This field indicates that software or DMA failed to prevent FIFO from\n"\ desc += "overflowing with converted datawords. Software can clear this bit by writing\n"\ desc += "'1' to it after reading the FIFO contents through CDR. This flag remains set if\n"\ desc += "software or DMA failed to clear the condition that caused this flag setting. If\n"\ desc += "DFORF is set, further datawords will not be received into FIFO even if\n"\ desc += "sufficient room exists." %define _DESC1993_ \ desc += "Data FIFO Full Flag\n\n"\ desc += "This bit is set when the number of converted datawords in the FIFO is equal to\n"\ desc += "or more than the number indicated by FCR[FTHLD]. Software can clear this bit by\n"\ desc += "writing '1' to it. This bit is also cleared by an acknowledgement from the DMA\n"\ desc += "controller when DMA request generation is selected. This bit remains set if\n"\ desc += "software or DMA failed to clear the condition that caused this flag setting.\n"\ desc += "Even if DFFF is set, datawords will continue to be received until an overrun\n"\ desc += "condition occurs. Datawords will not be received if the converted data is not\n"\ desc += "valid (CDVF = 0)." %define _DESC1994_ \ desc += "Request Select and Enable Register. The Request Select and Enable Register\n"\ desc += "(RSER) serves two purposes:\n\n"\ desc += "Enables the flag bits in SFR to generate DMA requests or interrupt requests. \n"\ desc += "Selects the type of request to generate. Refer to the field descriptions for\n"\ desc += "the type of requests that are supported." %define _DESC1995_ \ desc += "WDG Threshold Cross Over Event DMA/Interrupt Request Select\n\n"\ desc += "When SFR[WTHH/WTHL] and RSER[WTHDIRE] fields are set, this field selects\n"\ desc += "between generating a DMA request or an interrupt request." %define _DESC1996_ \ desc += "Data FIFO Full DMA/Interrupt Request Select\n\n"\ desc += "When the SFR[DFFF] and SFR[DFFDIRE] fields are set, this field selects between\n"\ desc += "generating a DMA request or an interrupt request." %define _DESC1997_ \ desc += "Global DMA/Interrupt Gating Enable\n\n"\ desc += "This field determines whether all module interrupts and DMA requests need to be\n"\ desc += "gated by an external gating signal or not." %define _DESC1998_ \ desc += "WDG Threshold Cross Over Event DMA/Interrupt Request Enable\n\n"\ desc += "This field enables the SFR[WTHH/WTHL] field to generate a request. The WTHDIRS\n"\ desc += "field determines which is selected, a DMA request or an interrupt request. The\n"\ desc += "final DMA/interrupt request also depends on the gating signal if enabled by the\n"\ desc += "GDIGE field." %define _DESC1999_ \ desc += "Conversion Data Valid Event Enable\n\n"\ desc += "This field enables the SFR[CDVF] field to generate a hardware event to be used\n"\ desc += "at SoC level. Once enabled, the event output will remain asserted as long as\n"\ desc += "valid data conversions are ongoing." %define _DESC2000_ \ desc += "Data FIFO Overrun Interrupt Enable\n\n"\ desc += "This bit enables the SFR[DFORF] field to generate an interrupt request. The\n"\ desc += "final interrupt request also depends on the gating signal if enabled by the\n"\ desc += "GDIGE field." %define _DESC2001_ \ desc += "Data FIFO Full DMA/Interrupt Request Enable\n\n"\ desc += "This field enables the SFR[DFFF] field to generate a request. The DFFDIRS field\n"\ desc += "determines which is selected, a DMA request or an interrupt request. The final\n"\ desc += "DMA/interrupt request also depends on the gating signal if enabled by the GDIGE\n"\ desc += "field." %define _DESC2002_ \ desc += "Output Settling Delay Register. The Output Settling Delay Register (OSDR)\n"\ desc += "provides a delay value to qualify the converted output data coming from the\n"\ desc += "SDADC." %define _DESC2003_ \ desc += "Output Settling Delay\n\n"\ desc += "This field defines the delay to qualify the conversion data stored in CDR.\n"\ desc += "Whenever the SDADC block is reset in order to start the conversion from a fresh\n"\ desc += "state, an internal timer is loaded with this start value. The counter counts\n"\ desc += "down with output clock f d until it reaches zero, and then it generates a flag\n"\ desc += "which qualifies the converted data. The output clock fd is equal to f s /\n"\ desc += "(2xOSR), where f s is the input sampling clock frequency. See the electrical\n"\ desc += "specifications for the settling delays." %define _DESC2004_ \ desc += "FIFO Control Register. The FIFO Control Register (FCR) provides the ability to\n"\ desc += "turn on and off the FIFO functionality . This register also provides the\n"\ desc += "ability to set the programmable threshold for notification of dataword removal\n"\ desc += "from the FIFO. This register may be read at any time, but should only be\n"\ desc += "written when SDADC is disabled (MCR[EN] = 0)." %define _DESC2005_ \ desc += "FIFO Threshold\n\n"\ desc += "When the number of datawords in the data FIFO is equal to or greater than the\n"\ desc += "value in FTHLD field, the FIFO full event is flagged. An interrupt or a DMA\n"\ desc += "request will be generated as determined by DFFDIRE and DFFDIRS fields of RSER.\n"\ desc += "For proper operation, the value in the FTHLD field must be set to be less than\n"\ desc += "or equal to the FIFO size as indicated by FSIZE." %define _DESC2006_ \ desc += "FIFO Size\n\n"\ desc += "The maximum number of converted datawords that can be stored in the data FIFO\n"\ desc += "before an overrun occurs. This field is read-only. The reset value of this\n"\ desc += "field depends on the implementation parameter to define the FIFO size." %define _DESC2007_ \ desc += "FIFO Enable\n\n"\ desc += "When this field is set the built-in FIFO structure is enabled. The size of the\n"\ desc += "FIFO structure is indicated by the FSIZE field. If this field is not set then\n"\ desc += "the FIFO depth is set to one dataword regardless of the value in the FSIZE\n"\ desc += "field." %define _DESC2008_ \ desc += "Software Trigger Key Register. The Software Trigger Key Register (STKR) allows\n"\ desc += "generating the trigger event output by a software write operation." %define _DESC2009_ \ desc += "Software Trigger Key\n\n"\ desc += "This bitfield, when written with 0xFFFF, is used to generate a trigger event\n"\ desc += "output which can be used to trigger conversions of multiple SDADC blocks\n"\ desc += "synchronously depending on the chip's implementation. Any write access to this\n"\ desc += "register which is different from the predefined key is ignored. Read access\n"\ desc += "will always return 0x0000." %define _DESC2010_ \ desc += "Converted Data Register. The Converted Data Register (CDR) stores the converted\n"\ desc += "data in the data FIFO.\n\n"\ desc += "The conversion result in the CDATA word is a 16-bit, signed value." %define _DESC2011_ \ desc += "Converted Data Register (CDATA[13:0])\n\n"\ desc += "The converted datawords can be read from FIFO by reading this register. The\n"\ desc += "data width is 16 bits which has actual 16-bit data (bits 15 down to 0) coming\n"\ desc += "from ADC." %define _DESC2012_ \ desc += "WDG Threshold Register. This is the Converted Data Range WDG Threshold\n"\ desc += "register.\n\n"\ desc += "A single WDG monitor will check for lower and upper threshold crossover events." %define _DESC2013_ \ desc += "WDG Upper Threshold Value\n\n"\ desc += "This indicates the upper threshold for the converted data on any channel, above\n"\ desc += "which threshold a crossover event wold be flagged through SFR[WTHH]." %define _DESC2014_ \ desc += "WDG Lower Threshold Value\n\n"\ desc += "This indicates the lower threshold for the converted data on any channel, below\n"\ desc += "which threshold cross over event wold be flagged through SFR[WTHL]." %define _DESC2015_ \ desc += "SIPI Channel Control Register 0. Back to back transactions are not supported on\n"\ desc += "a single channel (for example, if the channel busy bit, SIPI_CSR0[CB] = 1, is\n"\ desc += "configured for a channel, it cannot be triggered for another transfer until the\n"\ desc += "data buffers are empty and the channel is free, SIPI_CSR0[CB] = 0).\n\n"\ desc += "PRIORITY SCHEDULING: The channel whose SIPI_CAR n is written first will gain\n"\ desc += "access first irrespective of its priority at the start of the transfer. As more\n"\ desc += "transfers are requested, priority will be resolved as per the priority scheme\n"\ desc += "(for example, channel 2 - channel 0 - channel 1 - channel 3). Scheduling will\n"\ desc += "occur each time the LFAST is not ready to receive data and no channel is\n"\ desc += "pending for data transmission. The reason for the scheduling is that a common\n"\ desc += "CRC module is shared by all channels. If the LFAST is ready to receive data\n"\ desc += "during the entire process, it will happen only in the beginning and later on\n"\ desc += "priority will be resolved as per the priority scheme.\n\n"\ desc += "This register is only writable in Initialization mode (SIPI_MCR[INIT] = 1)." %define _DESC2016_ \ desc += "A Trigger Command requires that only this bit to be set by software, the\n"\ desc += "trigger does not depend on settings in SIPI_CAR0." %define _DESC2017_ \ desc += "For Streaming write, WL bits should be written 10." %define _DESC2018_ \ desc += "If all the channel enables are enabled simultaneously, channel 2 will be given\n"\ desc += "the highest priority for transmission. For channels 0, 1 and 3, the lowest\n"\ desc += "channel number is given highest priority." %define _DESC2019_ \ desc += "This bit is hard-coded to 0. It can only be written for channel 2 (SIPI_CCR2).\n"\ desc += "This bit can only be written when SIPI_CCR0[WRT] = 1.\n\n"\ desc += "Only transfers with channel 2 can write 1 to this bit. All other channels\n"\ desc += "forces SIPI_CCR n [ST] = 0. The SIPI_CCR2[WRT] and SIPI_CCR2[ST] bits must be\n"\ desc += "set for streaming." %define _DESC2020_ \ desc += "This request returns the value of the CHIP ID.\n\n"\ desc += "The order of priority for writing to IDT, WRT and RRT must be in this order:\n"\ desc += "IDT RRT WRT" %define _DESC2021_ \ desc += "The order of priority for writing to IDT, WRT and RRT must be in this order:\n"\ desc += "IDT RRT WRT" %define _DESC2022_ \ desc += "Only transfers with channel 2 can write 1 to this bit. All other channels\n"\ desc += "forces SIPI_CCR0[ST] = 0. The SIPI_CCR2[WRT] and SIPI_CCR2[ST] bits must be set\n"\ desc += "for streaming. The order of priority for writing to IDT, WRT and RRT must be\n"\ desc += "in this order: IDT RRT WRT" %define _DESC2023_ \ desc += "When enabling DMA mode, this bit should be set by software. It will then be\n"\ desc += "cleared by hardware after one major loop has completed." %define _DESC2024_ \ desc += "SIPI Channel Status Register 0. CSR0 contains the status bits for the current\n"\ desc += "transfer." %define _DESC2025_ \ desc += "Read Answer Reception." %define _DESC2026_ \ desc += "Transaction ID is a random number associated with every Tx frame to match the\n"\ desc += "received response/ack with the command." %define _DESC2027_ \ desc += "Acknowledge Received." %define _DESC2028_ \ desc += "Indicates channel 0 status." %define _DESC2029_ \ desc += "SIPI Channel Interrupt Register 0. SIPI_CIR0 contains the interrupt enable bits\n"\ desc += "for channel 0." %define _DESC2030_ \ desc += "SIPI Channel Timeout Register 0. SIPI_CTOR0 contains the timeout value for Tx\n"\ desc += "requests." %define _DESC2031_ \ desc += "Timeout counter runs on the prescaled peripheral clock. Prescaler is defined by\n"\ desc += "SIPI_MCR[PRSCLR].\n\n"\ desc += "Field can only be written during Initialization mode (SIPI_MCR[INIT] = 1)." %define _DESC2032_ \ desc += "SIPI Channel CRC Register 0. SIPI_CCRC0 is a read only which returns the CRC\n"\ desc += "calculated value on the header, address and data bits." %define _DESC2033_ \ desc += "Reflects received CRC value at initiator" %define _DESC2034_ \ desc += "Reflects received CRC value at target" %define _DESC2035_ \ desc += "SIPI Channel Address Register 0. SIPI_CAR0 is the address target for data\n"\ desc += "transmission." %define _DESC2036_ \ desc += "These bits contain the address of the target node." %define _DESC2037_ \ desc += "SIPI Channel Data Register 0. SIPI_CDR0 contains the data to be transmitted,\n"\ desc += "and can be written anytime by software or the DMA. The data can be written in\n"\ desc += "8, 16 or 32 bit formats." %define _DESC2038_ \ desc += "Data register bits. Contains the data that will be transmitted, or received." %define _DESC2039_ \ desc += "SIPI Channel Control Register 1. Back to back transactions are not supported on\n"\ desc += "a single channel (for example, if the channel busy bit, SIPI_CSR1[CB] = 1, is\n"\ desc += "configured for a channel, it cannot be triggered for another transfer until the\n"\ desc += "data buffers are empty and the channel is free, SIPI_CSR1[CB] = 0).\n\n"\ desc += "PRIORITY SCHEDULING: The channel whose SIPI_CAR n is written first will gain\n"\ desc += "access first irrespective of its priority at the start of the transfer. As more\n"\ desc += "transfers are requested, priority will be resolved as per the priority scheme\n"\ desc += "(for example, channel 2 - channel 0 - channel 1 - channel 3). Scheduling will\n"\ desc += "occur each time the LFAST is not ready to receive data and no channel is\n"\ desc += "pending for data transmission. The reason for the scheduling is that a common\n"\ desc += "CRC module is shared by all channels. If the LFAST is ready to receive data\n"\ desc += "during the entire process, it will happen only in the beginning and later on\n"\ desc += "priority will be resolved as per the priority scheme.\n\n"\ desc += "This register is only writable in Initialization mode (SIPI_MCR[INIT] = 1)." %define _DESC2040_ \ desc += "A Trigger Command requires that only this bit to be set by software, the\n"\ desc += "trigger does not depend on settings in SIPI_CAR1." %define _DESC2041_ \ desc += "For Streaming write WL bits should be written 10." %define _DESC2042_ \ desc += "Streaming Transfer. This bit is hard-coded to 0 for channels 0, 1 and 3. It can\n"\ desc += "only be written for channel 2 (SIPI_CCR2). This bit can only be written when\n"\ desc += "SIPI_CCR2[WRT] = 1.\n\n"\ desc += "Only transfers with channel 2 can write 1 to this bit. All other channels\n"\ desc += "forces SIPI_CCR n [ST] = 0. The SIPI_CCR2[WRT] and SIPI_CCR2[ST] bits must be\n"\ desc += "set for streaming." %define _DESC2043_ \ desc += "This request returns the value of the CHIP ID.\n\n"\ desc += "The order of priority for writing to IDT, WRT and RRT must be in this order:\n"\ desc += "IDT WRT RRT" %define _DESC2044_ \ desc += "Read Request Transfer.\n\n"\ desc += "The order of priority for writing to IDT, WRT and RRT must be in this order:\n"\ desc += "IDT WRT RRT" %define _DESC2045_ \ desc += "Write Request Transfer.\n\n"\ desc += "Only transfers with channel 2 can write 1 to this bit. All other channels\n"\ desc += "forces SIPI_CCR1[ST] = 0. The SIPI_CCR2[WRT] and SIPI_CCR2[ST] bits must be set\n"\ desc += "for streaming. The order of priority for writing to IDT, WRT and RRT must be\n"\ desc += "in this order: IDT WRT RRT" %define _DESC2046_ \ desc += "SIPI Channel Status Register 1. CSR1 contains the status bits for the current\n"\ desc += "transfer." %define _DESC2047_ \ desc += "Transaction ID of transmitted frame.\n\n"\ desc += "Transaction ID is a random number associated with every Tx frame to match the\n"\ desc += "received response/ack with the command." %define _DESC2048_ \ desc += "Indicates channel 1 status." %define _DESC2049_ \ desc += "SIPI Channel Interrupt Register 1. The CIR1 contains the interrupt enable bits\n"\ desc += "for channel 1." %define _DESC2050_ \ desc += "Write Acknowledge Interrupt Enable." %define _DESC2051_ \ desc += "Read Answer Interrupt Enable." %define _DESC2052_ \ desc += "Trigger Command Interrupt Enable." %define _DESC2053_ \ desc += "Timeout Error Interrupt Enabled." %define _DESC2054_ \ desc += "Transaction ID Error Interrupt Enable." %define _DESC2055_ \ desc += "Acknowledge Error Interrupt Enable." %define _DESC2056_ \ desc += "SIPI Channel Timeout Register 1. SIPI_CTOR1 contains the timeout value for Tx\n"\ desc += "requests." %define _DESC2057_ \ desc += "SIPI Channel CRC Register 1. SIPI_CCRC1 is a read only which returns the CRC\n"\ desc += "calculated value on the header, address and data bits." %define _DESC2058_ \ desc += "SIPI Channel Address Register 1. SIPI_CAR1 is the address target for data\n"\ desc += "transmission." %define _DESC2059_ \ desc += "SIPI Channel Data Register 1. SIPI_CDR1 contains the data to be transmitted,\n"\ desc += "and can be written anytime by software or the DMA. The data can be written in\n"\ desc += "8, 16 or 32 bit formats." %define _DESC2060_ \ desc += "SIPI Channel Control Register 2. Back to back transactions are not supported on\n"\ desc += "a single channel (for example, if the channel busy bit, SIPI_CSR2[CB] = 1, is\n"\ desc += "configured for a channel, it cannot be triggered for another transfer until the\n"\ desc += "data buffers are empty and the channel is free, SIPI_CSR2[CB] = 0).\n\n"\ desc += "PRIORITY SCHEDULING: The channel whose SIPI_CAR n is written first will gain\n"\ desc += "access first irrespective of its priority at the start of the transfer. As more\n"\ desc += "transfers are requested, priority will be resolved as per the priority scheme\n"\ desc += "(for example, channel 2 - channel 0 - channel 1 - channel 3). Scheduling will\n"\ desc += "occur each time the LFAST is not ready to receive data and no channel is\n"\ desc += "pending for data transmission. The reason for the scheduling is that a common\n"\ desc += "CRC module is shared by all channels. If the LFAST is ready to receive data\n"\ desc += "during the entire process, it will happen only in the beginning and later on\n"\ desc += "priority will be resolved as per the priority scheme.\n\n"\ desc += "This register is only writable in Initialization mode (MCR[INIT] = 1)." %define _DESC2061_ \ desc += "A Trigger Command requires that only this bit to be set by software, the\n"\ desc += "trigger does not depend on settings in SIPI_CAR2." %define _DESC2062_ \ desc += "Write Request Transfer.\n\n"\ desc += "Only transfers with channel 2 can write 1 to this bit. All other channels\n"\ desc += "forces SIPI_CCR2[ST] = 0. The SIPI_CCR2[WRT] and SIPI_CCR2[ST] bits must be set\n"\ desc += "for streaming. The order of priority for writing to IDT, WRT and RRT must be\n"\ desc += "in this order: IDT RRT WRT" %define _DESC2063_ \ desc += "DMA Enable. When enabling DMA mode, this bit should be set by software. It will\n"\ desc += "then be cleared by hardware after one major loop has completed." %define _DESC2064_ \ desc += "SIPI Channel Status Register 2. SIPI_CSR2 contains the status bits for the\n"\ desc += "current transfer." %define _DESC2065_ \ desc += "Indicates channel 2 status." %define _DESC2066_ \ desc += "SIPI Channel Interrupt Register 2. The SIPI_CIR2 contains the interrupt enable\n"\ desc += "bits for channel 2." %define _DESC2067_ \ desc += "SIPI Channel Timeout Register 2. SIPI_CTOR2 contains the timeout value for Tx\n"\ desc += "requests." %define _DESC2068_ \ desc += "Timeout value for transmitted requests. Timeout counter runs on the prescaled\n"\ desc += "peripheral clock. Prescaler is defined by SIPI_MCR[PRSCLR].\n\n"\ desc += "Field can only be written during Initialization mode (SIPI_MCR[INIT] = 1)." %define _DESC2069_ \ desc += "SIPI Channel CRC Register 2. SIPI_CCRC2 is a read only which returns the CRC\n"\ desc += "calculated value on the header, address and data bits." %define _DESC2070_ \ desc += "SIPI Channel Address Register 2. SIPI_CAR2 is the address target for data\n"\ desc += "transmission. For streaming operations this register is the start address." %define _DESC2071_ \ desc += "SIPI Channel Data Register 2. SIPI_CDR2_ n contains the data to be transmitted\n"\ desc += "and can be written anytime by software or the DMA. The data can be written in\n"\ desc += "8, 16 or 32 bit formats." %define _DESC2072_ \ desc += "SIPI Channel Control Register 3. Back to back transactions are not supported on\n"\ desc += "a single channel (for example, if the channel busy bit, SIPI_CSR3[CB] = 1, is\n"\ desc += "configured for a channel, it cannot be triggered for another transfer until the\n"\ desc += "data buffers are empty and the channel is free, SIPI_CSR3[CB] = 0). PRIORITY\n"\ desc += "SCHEDULING: The channel whose SIPI_CAR n is written first will gain access\n"\ desc += "first irrespective of its priority at the start of the transfer. As more\n"\ desc += "transfers are requested, priority will be resolved as per the priority scheme\n"\ desc += "(for example, channel 2 - channel 0 - channel 1 - channel 3). Scheduling will\n"\ desc += "occur each time the LFAST is not ready to receive data and no channel is\n"\ desc += "pending for data transmission. The reason for the scheduling is that a common\n"\ desc += "CRC module is shared by all channels. If the LFAST is ready to receive data\n"\ desc += "during the entire process, it will happen only in the beginning and later on\n"\ desc += "priority will be resolved as per the priority scheme." %define _DESC2073_ \ desc += "A Trigger Command requires that only this bit to be set by software, the\n"\ desc += "trigger does not depend on settings in the SIPI_CAR3." %define _DESC2074_ \ desc += "This bit is hard-coded to 0 for channels 0, 1 and 3. It can only be written for\n"\ desc += "channel 2 (SIPI_CCR2). This bit can only be written when SIPI_CCR2[WRT] = 1." %define _DESC2075_ \ desc += "This request returns the value of the CHIP ID." %define _DESC2076_ \ desc += "Read Request Transfer." %define _DESC2077_ \ desc += "Write Request Transfer." %define _DESC2078_ \ desc += "SIPI Channel Status Register 3. SIPI_CSR3 contains the status bits for the\n"\ desc += "current transfer." %define _DESC2079_ \ desc += "Indicates channel 3 status." %define _DESC2080_ \ desc += "SIPI Channel Interrupt Register 3. SIPI_CIR3 contains the interrupt enable bits\n"\ desc += "for channel 3." %define _DESC2081_ \ desc += "SIPI Channel Timeout Register 3. SIPI_CTOR3 contains the timeout value for Tx\n"\ desc += "requests." %define _DESC2082_ \ desc += "Timeout counter runs on the prescaled peripheral clock. Prescaler is defined by\n"\ desc += "SIPI_MCR[PRSCLR].\n\n"\ desc += "Can only be written during Initialization mode (SIPI_MCR[INIT] = 1)." %define _DESC2083_ \ desc += "SIPI Channel CRC Register 3. SIPI_CCRC3 is a read only which returns the CRC\n"\ desc += "calculated value on the header, address and data bits." %define _DESC2084_ \ desc += "SIPI Channel Address Register 3. SIPI_CAR3 is the address target for data\n"\ desc += "transmission." %define _DESC2085_ \ desc += "SIPI Channel Data Register 3. SIPI_CDR3 contains the data to be transmitted and\n"\ desc += "can be written anytime by software or the DMA. The data can be written in 8, 16\n"\ desc += "or 32 bit formats." %define _DESC2086_ \ desc += "SIPI Module Configuration Register. The SIPI_MCR is a global 32-bit\n"\ desc += "configuration register." %define _DESC2087_ \ desc += "The FRZ bit specifies the SIPI behavior when Debug mode is requested at the MCU\n"\ desc += "level. When FRZ is asserted, the SIPI is enabled to enter Freeze mode. Negation\n"\ desc += "of this bit field causes SIPI to exit Freeze mode.\n\n"\ desc += "Can only be written when SIPI_MCR[MOEN] = 1." %define _DESC2088_ \ desc += "This bit defines whether SIPI is allowed to enter low power mode when Doze mode\n"\ desc += "is requested at the MCU level.\n\n"\ desc += "Can only be written when SIPI_MCR[MOEN] = 1." %define _DESC2089_ \ desc += "Assertion of this bit puts SIPI into Freeze mode. No Rx or Tx is performed in\n"\ desc += "the SIPI until this bit is cleared. If this bit is enabled in during Tx or Rx\n"\ desc += "communications, the current activity will finish, then the SIPI will enter\n"\ desc += "Freeze mode.\n\n"\ desc += "Can only be written when SIPI_MCR[MOEN] = 1." %define _DESC2090_ \ desc += "The timeout counter runs on the prescaled system clock. Default value is 64\n"\ desc += "(040h). The allowed programmable values are (all other values are ignored):\n"\ desc += "040h 64 (default) 080h 128 100h 256 200h 512 400h 1024 This field should be\n"\ desc += "programmed by software during initialization mode, SIPI_MCR[INIT] = 1. Writes\n"\ desc += "during other times are ignored. Writes to SIPI_MCR[PRSCLR] can only be\n"\ desc += "accomplished with 16-bit or 32-bit writes." %define _DESC2091_ \ desc += "These bits define the type of address change at the target node.\n\n"\ desc += "This bits should be programmed by software in initialization mode,\n"\ desc += "SIPI_MCR[INIT] = 1. Writes during other times are ignored." %define _DESC2092_ \ desc += "Setting this bit enables the target functionality at SIPI. This bit can be read\n"\ desc += "or written anytime. This bit is automatically negated by hardware when target\n"\ desc += "detects an error in 'streaming without ACK' mode. This bit has to be enabled\n"\ desc += "for the transmission operations also." %define _DESC2093_ \ desc += "Setting this bit puts the module in initialization mode. This bit should be\n"\ desc += "cleared by software. Most register bits are configured using this bit. The\n"\ desc += "SIPI_MCR[MOEN] bit needs to be set first, and then the INIT bit can be set and\n"\ desc += "both bits can't be enabled together." %define _DESC2094_ \ desc += "This bit should be set or cleared by software. When this bit is negated, all\n"\ desc += "SIPI operations are immediately stopped." %define _DESC2095_ \ desc += "Setting this bit clears all status and error registers, and FSMs are moved to\n"\ desc += "idle state. This bit is automatically cleared by hardware once the reset\n"\ desc += "operation is complete." %define _DESC2096_ \ desc += "SIPI Status Register. The SIPI_SR is the global status register of SIPI." %define _DESC2097_ \ desc += "Freeze Mode Acknowledge. This read-only bit indicates that SIPI is in Freeze\n"\ desc += "mode. The Freeze mode request cannot be granted until current transmission or\n"\ desc += "reception processes have finished. The software can poll the FRZACK bit to find\n"\ desc += "when the SIPI has actually entered Freeze mode. If Freeze mode is requested\n"\ desc += "while SIPI is in any of the low power modes, then the FRZACK bit will only be\n"\ desc += "set when the low power mode is exited." %define _DESC2098_ \ desc += "This read-only bit indicates that SIPI is in Disable Mode . Either of these\n"\ desc += "low power modes can not be entered until all current transmission or reception\n"\ desc += "processes have finished, so the CPU can poll the LPMACK bit to know when SIPI\n"\ desc += "has actually entered low power mode ." %define _DESC2099_ \ desc += "Global CRC Error Bit." %define _DESC2100_ \ desc += "This bit will be set whenever SIPI_ACR[ADCNT] = SIPI_MAXCR[MXCNT]. An interrupt\n"\ desc += "will be generated when this bit is set only if SIPI_MCR[MCRIE] = 1. This it\n"\ desc += "should be cleared by software." %define _DESC2101_ \ desc += "Trigger Event on Respective Channels. This field enables interrupts for target\n"\ desc += "nodes." %define _DESC2102_ \ desc += "These bits reflect the transmit state machine status. They can be polled for\n"\ desc += "determination of state machine status." %define _DESC2103_ \ desc += "SIPI Max Count Register. SIPI_MAXCR contains the maximum address count value at\n"\ desc += "target node. It is programmed via direct write request through the initiator.\n"\ desc += "This register can be read or written by software anytime." %define _DESC2104_ \ desc += "This field contains the maximum address count value at the target node. It\n"\ desc += "should be programmed via direct write request through the initiator." %define _DESC2105_ \ desc += "SIPI Address Reload Register. The SIPI_ARR contains the reload value for the\n"\ desc += "address counter at the target node. It should be configured by direct write\n"\ desc += "request from the initiator. This register can be read or written anytime." %define _DESC2106_ \ desc += "ADRLD contains the reload value for the address counter at the target node. It\n"\ desc += "should be configured by direct write request from the initiator." %define _DESC2107_ \ desc += "SIPI Address Count Register. This register reflects the count value of address\n"\ desc += "counter at target node. It should be configured by direct write request from\n"\ desc += "initiator. This register can be read/written by software anytime.\n\n"\ desc += "SIPI_ARR, SIPI_ACR and SIPI_MAXCR will be configured by direct write operation\n"\ desc += "through the initiator. When a streaming write command is received, the target\n"\ desc += "will start the write operation from the address present in SIPI_ACR (address\n"\ desc += "count register). After each 32-bit write has occurred, SIPI_ACR[ADCNT] is\n"\ desc += "compared against SIPI_MAXCR[MXCNT]. If they are equal, SIPI_ACR[ADCNT] is\n"\ desc += "loaded with the value stored in SIPI_ARR[ADRLD]. If they are not equal, the\n"\ desc += "SIPI_ACR[ADCNT] will increment by 4, decrement by 4 or remain the same\n"\ desc += "(depending on configuration). In both cases, the SIPI_ACR[ADCNT] will contain\n"\ desc += "the address at which the next streaming write will occur." %define _DESC2108_ \ desc += "It should be configured by direct write request from the initiator. This\n"\ desc += "register can be read/written by software anytime. At the end of the streaming\n"\ desc += "operation, SIPI_ACR will point to the next address to be written." %define _DESC2109_ \ desc += "SIPI Error Register. This register contains the error bits for the last\n"\ desc += "transaction(s) for all the channels. Communication errors are generated only\n"\ desc += "for out of range address accesses, areas that are read only and where accesses\n"\ desc += "do not lead to generation of transfer errors. Also, writing to read only\n"\ desc += "registers will not generate errors." %define _DESC2110_ \ desc += "Timeout Error for Channel 3." %define _DESC2111_ \ desc += "Transaction ID Error for Channel 3." %define _DESC2112_ \ desc += "Acknowledge Error for Channel 3." %define _DESC2113_ \ desc += "Timeout Error for Channel 2." %define _DESC2114_ \ desc += "Transaction ID Error for Channel 2." %define _DESC2115_ \ desc += "Acknowledge Error for Channel 2." %define _DESC2116_ \ desc += "Timeout Error for Channel 1." %define _DESC2117_ \ desc += "Transaction ID Error for Channel 1." %define _DESC2118_ \ desc += "Acknowledge Error for Channel 1." %define _DESC2119_ \ desc += "Timeout Error for Channel 0." %define _DESC2120_ \ desc += "Transaction ID Error for Channel 0." %define _DESC2121_ \ desc += "Acknowledge Error for Channel 0." %define _DESC2122_ \ desc += "SIUL2 MCU ID Register #1. This register contains identification information\n"\ desc += "about the device." %define _DESC2123_ \ desc += "MCU Part Number-These digits identify the part number of the chip. Default is\n"\ desc += "5726." %define _DESC2124_ \ desc += "Package Settings-Can by read by software to determine the package type that is\n"\ desc += "used for the particular device:\n\n"\ desc += "0b00101: 80-pin QFP\n\n"\ desc += "0b01001: 100-pin QFP" %define _DESC2125_ \ desc += "Major Mask Revision" %define _DESC2126_ \ desc += "Minor Mask Revision" %define _DESC2127_ \ desc += "SIUL2 MCU ID Register #2. This register contains identification information\n"\ desc += "about the device.\n\n"\ desc += "The reset values of the FLASH_SIZE_1, FLASH_SIZE_2, and FAMILYNUM fields are\n"\ desc += "set at the factory and cannot be modified." %define _DESC2128_ \ desc += "Manufacturer:" %define _DESC2129_ \ desc += "Coarse granularity for Flash memory size. Needs to be combined with\n"\ desc += "FLASH_SIZE_2 to calculate the actual memory size:\n\n"\ desc += "0b0000 16 KB\n\n"\ desc += "0b0001 32 KB\n\n"\ desc += "0b0010 64 KB\n\n"\ desc += "0b0011 128 KB\n\n"\ desc += "0b0100 256 KB\n\n"\ desc += "0b0101 512 KB\n\n"\ desc += "0b0110 1 MB\n\n"\ desc += "...\n\n"\ desc += "0b1110 256 MB\n\n"\ desc += "0b1111 512 MB" %define _DESC2130_ \ desc += "Fine granularity for Flash memory size. Needs to be combined with FLASH_SIZE_1\n"\ desc += "to calculate the actual memory size:\n\n"\ desc += "0b0000 0 x (FLASH_SIZE_1 / 8)\n\n"\ desc += "0b0001 1 x (FLASH_SIZE_1 / 8)\n\n"\ desc += "0b0010 2 x (FLASH_SIZE_1 / 8)\n\n"\ desc += "0b0011 3 x (FLASH_SIZE_1 / 8)\n\n"\ desc += "0b0100 4 x (FLASH_SIZE_1 / 8)\n\n"\ desc += "...\n\n"\ desc += "0b1110 14 x (FLASH_SIZE_1 / 8)\n\n"\ desc += "0b1111 15 x (FLASH_SIZE_1 / 8)" %define _DESC2131_ \ desc += "All other values reserved for future use.\n\n"\ desc += "ASCII character in MCU Part Number:\n\n"\ desc += "0x4C L" %define _DESC2132_ \ desc += "SIUL2 DMA/Interrupt Status Flag Register 0. The DMA/Interrupt Status Register\n"\ desc += "contains flag bits that record an event on the external IRQ pins. When an event\n"\ desc += "as defined in IRQ Rising-Edge Event Enable Register (SIUL2_IREER0) and IRQ\n"\ desc += "Falling-Edge Event Enable Register (SIUL2_IFEER0) occurs, the corresponding\n"\ desc += "flag bit is set. The IRQ Flag bit is set irrespective of the corresponding\n"\ desc += "DMA/Interrupt Request Enable bit in DMA/Interrupt Request Enable Register\n"\ desc += "(SIUL2_DIRER0) is enabled. The EIF bit remains set until cleared by software or\n"\ desc += "through the servicing of a DMA request. The EIF bits are cleared by writing a\n"\ desc += "'1' to the bits. A write of '0' has no effect.\n\n"\ desc += "This register contains the interrupt flags." %define _DESC2133_ \ desc += "External Interrupt Status Flag x-This flag can be cleared only by writing 1.\n"\ desc += "Writing 0 has no effect. If enabled (SIUL2_DIRER[x]), EIF[x] causes an\n"\ desc += "interrupt or DMA request." %define _DESC2134_ \ desc += "SIUL2 DMA/Interrupt Request Enable Register 0. The DMA/Interrupt Request Enable\n"\ desc += "Register enables the assertion of DMA or interrupt request if the corresponding\n"\ desc += "External IRQ Flag bit is set in SIUL2 DMA/Interrupt Status Flag Register0\n"\ desc += "(SIUL2_DISR0). The type of request enabled is determined by the corresponding\n"\ desc += "DMA/Interrupt Request Select bit in SIUL2 DMA/Interrupt Request Select\n"\ desc += "Register0 (SIUL2_DIRSR0). This register enables the interrupt messaging to the\n"\ desc += "interrupt controller." %define _DESC2135_ \ desc += "External Interrupt or DMA Request Enable x" %define _DESC2136_ \ desc += "SIUL2 DMA/Interrupt Request Select Register 0. The DIRSR selects between the\n"\ desc += "DMA or interrupt request. If the corresponding bits are set in SIUL2\n"\ desc += "DMA/Interrupt Status Flag Register0 (SIUL2_DISR0) and SIUL2 DMA/Interrupt\n"\ desc += "Request Enable Register0 (SIUL2_DIRER0), then the DMA/Interrupt Request Select\n"\ desc += "bit determines whether DMA or an interrupt request is asserted. EIRQ are the\n"\ desc += "external interrupt package pins on the device." %define _DESC2137_ \ desc += "DMA/Interrupt Request Select Register-Selects between DMA request or external\n"\ desc += "interrupt request when an edge-triggered event occurs on the corresponding\n"\ desc += "pin." %define _DESC2138_ \ desc += "SIUL2 Interrupt Rising-Edge Event Enable Register 0. This register is used to\n"\ desc += "enable the rising-edge triggered events on the corresponding interrupt pads." %define _DESC2139_ \ desc += "Enable rising-edge events to cause the EIF[x] bit to be set." %define _DESC2140_ \ desc += "SIUL2 Interrupt Falling-Edge Event Enable Register 0. This register is used to\n"\ desc += "enable falling-edge triggered events on the corresponding interrupt pads.\n\n"\ desc += "If both IREE bit and IFEE bit are cleared for the same interrupt source, the\n"\ desc += "interrupt status flag for the corresponding external interrupt will never be\n"\ desc += "set." %define _DESC2141_ \ desc += "Enable falling-edge events to cause the EIF[x] bit to be set." %define _DESC2142_ \ desc += "SIUL2 Interrupt Filter Enable Register 0. This register is used to enable a\n"\ desc += "digital filter counter on the corresponding interrupt pads to filter out\n"\ desc += "glitches on the inputs." %define _DESC2143_ \ desc += "Enable digital glitch filter on the interrupt pad input." %define _DESC2144_ \ desc += "SIUL2 Interrupt Filter Maximum Counter Register. These registers are used to\n"\ desc += "configure the filter counter associated with each digital glitch filter." %define _DESC2145_ \ desc += "Maximum Interrupt Filter Counter setting\n\n"\ desc += "MAXCNTx can be 0 to 15\n\n"\ desc += "For MAXCNTx = 0, 1, 2, the filter behaves as ALL PASS filter\n\n"\ desc += "For MAXCNTx = 3, 4, 5, ... 15, filter period = TCK*MAXCNTx + n*TCK\n\n"\ desc += "(n = 0, 1, 2, 3, or 4)\n\n"\ desc += "TCK: Prescaled filter clock period, which is IRC clock prescaled to IFCP value,\n"\ desc += "specified in\n\n"\ desc += "SIUL2_IFCPR\n\n"\ desc += "TIRC: Basic filter clock period 62.5 ns (f = 16 MHz)\n\n"\ desc += "Note that filter delay is 2 TCK clock cycles more than filter period.\n\n"\ desc += "In general, TFILTER and TDELAY are not integer multiples of TCK because DIN\n\n"\ desc += "is asynchronous whereas DOUT is synchronous with respect to the CK clock, and\n"\ desc += "the factor n accounts for this uncertainty in filter period calculation." %define _DESC2146_ \ desc += "SIUL2 Interrupt Filter Clock Prescaler. This register is used to configure a\n"\ desc += "clock prescaler which is used to select the clock for all digital filters.\n"\ desc += "Prescaler is applied to the input clock to the SIUL2, which is the system\n"\ desc += "PBRIDGE clock counters in the SIUL2. ./McKinley_RM_Clocking#Rcb32698" %define _DESC2147_ \ desc += "Interrupt Filter Clock Prescaler setting\n\n"\ desc += "Prescaled Filter Clock Period = T(IRC) x (IFCP + 1)\n\n"\ desc += "T(IRC) is the internal oscillator period.\n\n"\ desc += "IFCP can be 0 to 15" %define _DESC2148_ \ desc += "I/O Pin Multiplexed Signal Configuration Registers. The I/O pin MSCR definition\n"\ desc += "is given in this section. These registers select the output function on the\n"\ desc += "associated I/O pin. The I/O MSCRs control the drive strength, output drive\n"\ desc += "circuit, pull up/down, input buffer enable, input hysteresis, input level\n"\ desc += "selection, safe-mode operation, and analog input enable of the associated I/O\n"\ desc += "pin.\n\n"\ desc += "Note that when an I/O pin is configured as a single-ended input, the input\n"\ desc += "buffer must be enabled for the pin using the MSCR[IBE] bit. This enables the\n"\ desc += "input to all input destinations connected to the pin, including the GPIO input.\n"\ desc += "In this way, the GPIO can be read at any time, regardless of the pin function.\n"\ desc += "For IP blocks that have multiple input sources, the input source is selected in\n"\ desc += "the multiplexed input selection MSCRs, and the associated I/O pin MSCR for the\n"\ desc += "selected input must have the MSCR[IBE] bit enabled.\n\n"\ desc += "All bits and fields in the I/O MSCRs are applicable for all GPIO ports on the\n"\ desc += "device. This includes all ports on the device with digital output function. For\n"\ desc += "ADC input ports with digital input only (no output), the OERC, ODC, SMC, INV,\n"\ desc += "and SSS bits/fields do not apply. The SSS is always 8b0 for input only ports,\n"\ desc += "enabling the general purpose input. The analog input path is enabled in the ADC\n"\ desc += "logic when the channel is selected for conversion.\n\n"\ desc += "The MSCR reset state given in the register figure applies to all GPIO pins on\n"\ desc += "the devices, which defaults to input/pull-up enabled. The exceptions to this\n"\ desc += "are documented in #id-2013-03-20_1626 . Only the SMC, HYS, WPDE, and WPUE bits\n"\ desc += "have exceptions to the default MSCR reset value.\n\n"\ desc += "[I/O MSCR reset state exceptions]:\n"\ desc += " Port Critical function SMC HYS SSS WPDE WPUE\n"\ desc += " --------- ----------------- --- --- ------ ---- ----\n"\ desc += " PA[4] NMI 1 0 - 1 0\n"\ desc += " PA[5] JCOMP 1 1 0x0001 1 0\n"\ desc += " PA[6] TCK 1 1 0x0001 1 0\n"\ desc += " PA[7] TMS 1 1 0x0001 1 0\n"\ desc += " PA[8] TDI 1 1 0x0001 0 1\n"\ desc += " PA[9] TDO 1 1 0x0001 0 0\n"\ desc += " PA[14] - 1 1 0 1\n"\ desc += " PC[10:15] - 1 1 0 1\n"\ desc += " PD[6:7] - 1 1 0 1\n"\ desc += " PE[12] - 1 1 0 1\n"\ desc += " PF[13] - 1 1 0 1\n" %define _DESC2149_ \ desc += "Output Edge Rate Control-Used only when the associated destination is a chip\n"\ desc += "pin. Specifies the driver strength of the associated pin.\n\n"\ desc += "Refer to the chip I/O Signal Description and Input Multiplexing Tables" %define _DESC2150_ \ desc += "Output Drive Control-used only when the associated destination is a chip pin.\n"\ desc += "Specifies the type of output drive control for the associated pin." %define _DESC2151_ \ desc += "Safe Mode Control-Used only when the associated destination is a chip pin.\n"\ desc += "Specifies whether the chip disables the pin's output buffer when the chip\n"\ desc += "enters Safe mode." %define _DESC2152_ \ desc += "Analog Pad Control-Used only when the associated destination is a chip pin that\n"\ desc += "supports analog I/O. Enables the pin's analog-input-path switch." %define _DESC2153_ \ desc += "Input Level Selection-Used only when the associated destination is a chip pin. \n"\ desc += "Specifies the logic family for the associated pin, which determines its logic\n"\ desc += "switching levels." %define _DESC2154_ \ desc += "Input Buffer Enable-Used only when the associated destination is a chip pin.\n"\ desc += "Enables the associated pin's input buffer." %define _DESC2155_ \ desc += "Input Hysteresis-Used only when the associated destination is a chip pin.\n"\ desc += "Enables input hysteresis for the associated pin." %define _DESC2156_ \ desc += "Weak Pulldown Enable-Used only when the associated destination is a chip pin.\n"\ desc += "Enables the associated pin's weak pulldown resistor. It is OK for both WPDE and\n"\ desc += "WPUE to be enabled." %define _DESC2157_ \ desc += "Weak Pullup Enable-Used only when the associated destination is a chip pin.\n"\ desc += "Enables the associated pin's weak pullup resistor. It is OK for both WPDE and\n"\ desc += "WPUE to be enabled." %define _DESC2158_ \ desc += "Invert-Inverts the signal selected by SSS before transmitting it to the\n"\ desc += "associated destination (chip pin or module port)." %define _DESC2159_ \ desc += "Source Signal Select-Selects which source signal is connected to the associated\n"\ desc += "destination (chip pin or module port). For a chip pin, the source signals are\n"\ desc += "outputs from module ports. For a module port, the source signals are either\n"\ desc += "outputs from module ports or inputs from chip pins. The meaning of each value\n"\ desc += "depends on the destination. See #Rdh74581 ' and #Rdh25513 .'" %define _DESC2160_ \ desc += "Multiplexed Signal Configuration Registers for Multiplexed Input Selection. The\n"\ desc += "multiplexed input selection MSCR definition is given in this section. These\n"\ desc += "registers select the input source for IP blocks on the device that have inputs\n"\ desc += "from multiple sources, both other IP blocks and I/O pins. It is possible to\n"\ desc += "configure the pad to be in input without having to connect it externally. This\n"\ desc += "is possible, either by enabling internal pull-up/pull-down or disabling the\n"\ desc += "input buffer (but in this case data is seen as 0 internally)." %define _DESC2161_ \ desc += "SIUL2 GPIO Pad Data Output Registers. These registers can be used to set or\n"\ desc += "clear a single GPIO pad with a byte access. See Signal Description chapter for\n"\ desc += "mapping of ports to GPDO registers." %define _DESC2162_ \ desc += "Pad Data Out-This bit stores the data to be driven out on the external GPIO pad\n"\ desc += "controlled by this register." %define _DESC2163_ \ desc += "SIUL2 GPIO Pad Data Input Registers. These registers can be used to read the\n"\ desc += "GPIO pad data with a byte access. See Signal Description chapter for mapping of\n"\ desc += "ports to GPDI registers." %define _DESC2164_ \ desc += "Pad Data In-This bit stores the value of the external GPIO pad associated with\n"\ desc += "this register." %define _DESC2165_ \ desc += "SIUL2 Parallel GPIO Pad Data Out Register. These registers are used to set or\n"\ desc += "clear the respective pads of the device. Parallel port registers for input\n"\ desc += "(PGPDI) and output (PGPDO) are provided to allow a complete port to be written\n"\ desc += "or read in one operation, dependent on the individual pad configuration. The\n"\ desc += "difference between PGPDO and GPDO is that PGPDO registers can be used to set\n"\ desc += "the values of all output pins assigned to a device port with a single 16-bit\n"\ desc += "register write vs. the GPDO registers, which are used to set the value on a\n"\ desc += "specific pin with a byte write." %define _DESC2166_ \ desc += "Parallel Pad Data Out-Write or read the data register that stores the value to\n"\ desc += "be driven on the pad in output mode. Access to this register location are\n"\ desc += "coherent with access to the bit-wise GPIO Pad Data Output Registers\n"\ desc += "(SIUL2_GPDO). The x and y bit index define which PPDO register bit is\n"\ desc += "equivalent to which PDO register bit according to the following equation:\n\n"\ desc += "PPDO[x #Rdh49722 ][y] = PDO[(x*16)+y]" %define _DESC2167_ \ desc += "SIUL2 Parallel GPIO Pad Data In Register. These registers hold the synchronized\n"\ desc += "input value from the pads. Parallel port registers for input (PGPDI) and output\n"\ desc += "(PGPDO) are provided to allow a complete port to be written or read in one\n"\ desc += "operation, dependent on the individual pad configuration. The difference\n"\ desc += "between PGPDI and GPDI registers is that PGPDI registers can be used to read\n"\ desc += "the values of all input pins assigned to a device port with a single 16-bit\n"\ desc += "register read vs. the GPDI registers, which are used to read the value on a\n"\ desc += "specific pin with a byte read." %define _DESC2168_ \ desc += "Parallel Pad Data In-Reads the current pad value. Access to this register\n"\ desc += "location are coherent with access to the bit-wise GPIO Pad Data Input Registers\n"\ desc += "(SIUL2_GPDI). The x and y bit index define which PPDI register bit is\n"\ desc += "equivalent to which PDI register bit according to the following equation:\n\n"\ desc += "PPDI[x][y] = PDI[(x*16)+y]" %define _DESC2169_ \ desc += "SIUL2 Masked Parallel GPIO Pad Data Out Register. This register can be used to\n"\ desc += "selectively modify the pad values associated to PPDO[x][0:15]. The MPGPDO[x]\n"\ desc += "register may only be accessed with 32-bit writes. 8-bit or 16-bit writes will\n"\ desc += "not modify any bits in the register and cause a transfer error response by the\n"\ desc += "module. Read access will return 0." %define _DESC2170_ \ desc += "Mask Field-Each bit corresponds to one data bit in the MPPDO[x] register at the\n"\ desc += "same bit location." %define _DESC2171_ \ desc += "Masked Parallel Pad Data Out-Write the data register that stores the value to\n"\ desc += "be driven on the pad in output mode. Access to this register location are\n"\ desc += "coherent with access to the bit-wise GPIO Pad Data Output Registers (PDO). The\n"\ desc += "x and bit index define which MPPDO register bit is equivalent to which PDO\n"\ desc += "register bit according to the following equation:\n\n"\ desc += "MPPDO[x][y] = PDO[(x*16)+y]" %define _DESC2172_ \ desc += "Control/Error Status Register 0. " %define _DESC2173_ \ desc += "Master n error, where the bus master number matches the bit number\n\n"\ desc += "Indicates a captured error in EARn and EDRn. A bit is set when the hardware\n"\ desc += "detects an error and records the faulting address and attributes. It is cleared\n"\ desc += "by writing '1' to it. If another error is captured at the exact same cycle as\n"\ desc += "the write, the flag remains set. A find-first-one instruction (or equivalent)\n"\ desc += "can detect the presence of a captured error." %define _DESC2174_ \ desc += "Hardware revision level\n\n"\ desc += "Specifies the SMPU's hardware and definition revision level. It can be read by\n"\ desc += "software to determine the functional definition of the module." %define _DESC2175_ \ desc += "Global Valid (global enable/disable for the SMPU)" %define _DESC2176_ \ desc += "Control/Error Status Register 1. " %define _DESC2177_ \ desc += "Master n error overrun, where the bus master number matches the bit number\n\n"\ desc += "Each bit in this field signals that another SMPU error for bus master n has\n"\ desc += "occurred before the previous error was processed. The details of the first\n"\ desc += "error are recorded in the EARn and EDRn registers, and no information on\n"\ desc += "subsequent errors is recorded until the associated CESR0[MERR] flag is\n"\ desc += "cleared." %define _DESC2178_ \ desc += "Number of region descriptors\n\n"\ desc += "Indicates the number of region descriptors implemented in the SMPU." %define _DESC2179_ \ desc += "Error Address Register, Bus Master n. When the SMPU detects an access error on\n"\ desc += "bus master n, the 32-bit reference address is captured in this read-only\n"\ desc += "register and the corresponding bit in CESR0[MERR] is set. Additional\n"\ desc += "information about the faulting access is captured in the corresponding EDRn at\n"\ desc += "the same time.\n\n"\ desc += "The corresponding EARn and EDRn registers contain information on the original\n"\ desc += "access error; subsequent errors associated with the given master are recorded\n"\ desc += "as overruns in the CESR1[MEOVR] field until the original error is processed." %define _DESC2180_ \ desc += "Error address\n\n"\ desc += "Indicates the reference address from bus master n that generated the access\n"\ desc += "error" %define _DESC2181_ \ desc += "Error Detail Register, Bus Master n. When the SMPU detects an access error\n"\ desc += "associated with bus master n, 32 bits of error detail are captured in this\n"\ desc += "read-only register and the corresponding bit in CESR0[MERR] is set. Information\n"\ desc += "on the faulting address is captured in the corresponding EARn register at the\n"\ desc += "same time.\n\n"\ desc += "The corresponding EARn and EDRn registers contain information on the original\n"\ desc += "access error; subsequent errors associated with the given master are recorded\n"\ desc += "as overruns in the CESR1[MEOVR] field until the original error is processed." %define _DESC2182_ \ desc += "Error access control detail\n\n"\ desc += "Indicates the region descriptor with the access error, where the region\n"\ desc += "descriptor number matches the bit number.\n\n"\ desc += "If EDRn contains a captured error and EACD is all zeroes, an access did not hit\n"\ desc += "in any region descriptor. If only a single EACD bit is set, the access error\n"\ desc += "was caused by a single non-overlapping region descriptor. If two or more EACD\n"\ desc += "bits are set, the access error was caused by an overlapping set of region\n"\ desc += "descriptors." %define _DESC2183_ \ desc += "This read-only bit is reserved and always has the value '1'." %define _DESC2184_ \ desc += "Error attributes\n\n"\ desc += "Indicates attribute information about the faulting reference." %define _DESC2185_ \ desc += "Error read/write\n\n"\ desc += "Indicates the access type of the faulting reference.\n\n"\ desc += "0 Read\n\n"\ desc += "1 Write" %define _DESC2186_ \ desc += "Error master number\n\n"\ desc += "Indicates the logical bus master number of the faulting reference. This field\n"\ desc += "is used to determine the bus master that generated the access error." %define _DESC2187_ \ desc += "Region Descriptor n, Word 0. " %define _DESC2188_ \ desc += "Start address\n\n"\ desc += "Defines the byte start address of the memory region." %define _DESC2189_ \ desc += "Region Descriptor n, Word 1. " %define _DESC2190_ \ desc += "End address\n\n"\ desc += "Defines the byte end address of the memory region.\n\n"\ desc += "The SMPU does not verify that ENDADDR >= SRTADDR." %define _DESC2191_ \ desc += "Region Descriptor n, Word 2 Format 0. RGD_WORD2 has two formats as determined\n"\ desc += "by the RGD_WORD3[FMT] field.\n\n"\ desc += "RGD_WORD2_FMT0 applies when RGD_WORD3[FMT] = 0. RGD_WORD2_FMT0 defines the\n"\ desc += "access control rights of the memory region on a per master basis. The access\n"\ desc += "control rights are defined by separate read and write permissions. For these\n"\ desc += "fields, the bus master number refers to the logical bus master number.\n\n"\ desc += "For the access control rights, there are two flags per logical bus master:\n\n"\ desc += "Read (r) permission refers to the ability to access the referenced memory\n"\ desc += "address using an operand (data) fetch or an instruction fetch. Write (w)\n"\ desc += "permission refers to the ability to update the referenced memory address using\n"\ desc += "a store (data) instruction. Each field consists of the two flags, with (r)\n"\ desc += "being in the more significant position. For example, M0P has (r) as bit 0 and\n"\ desc += "(w) as bit 1.\n\n"\ desc += "The bit settings are as follows:\n\n"\ desc += "If set, the corresponding flag allows the specific access type (r = memory\n"\ desc += "read, w = memory write). If cleared, the specific access type is not allowed. \n"\ desc += "Writes to this word clear the region descriptor's valid bit." %define _DESC2192_ \ desc += "Bus master 0 permissions" %define _DESC2193_ \ desc += "Bus master 1 permissions" %define _DESC2194_ \ desc += "Bus master 2 permissions" %define _DESC2195_ \ desc += "Bus master 3 permissions" %define _DESC2196_ \ desc += "Bus master 4 permissions" %define _DESC2197_ \ desc += "Bus master 5 permissions" %define _DESC2198_ \ desc += "Bus master 6 permissions" %define _DESC2199_ \ desc += "Bus master 7 permissions" %define _DESC2200_ \ desc += "Bus master 8 permissions" %define _DESC2201_ \ desc += "Bus master 9 permissions" %define _DESC2202_ \ desc += "Bus master 10 permissions" %define _DESC2203_ \ desc += "Bus master 11 permissions" %define _DESC2204_ \ desc += "Bus master 12 permissions" %define _DESC2205_ \ desc += "Bus master 13 permissions" %define _DESC2206_ \ desc += "Bus master 14 permissions" %define _DESC2207_ \ desc += "Bus master 15 permissions" %define _DESC2208_ \ desc += "Region Descriptor n, Word 2 Format 1. RGD_WORD2 has two formats as determined\n"\ desc += "by the RGD_WORD3[FMT] field.\n\n"\ desc += "RGD_WORD2_FMT1 applies when RGD_WORD3[FMT] = 1. A specific module instance of\n"\ desc += "the SMPU may support only the FMT0 format. If so, the FMT field is read-only\n"\ desc += "with a fixed value of 0 and only RGD_WORD2_FMT0 applies. RGD_WORD2_FMT1\n"\ desc += "defines pointers for each master to select access control flags contained in\n"\ desc += "Word3. For these fields, the bus master number refers to the logical bus master\n"\ desc += "number.\n\n"\ desc += "The bit settings are as follows:\n\n"\ desc += "00: RGDn cannot be accessed by this master, that is, SR = SW = SX = UR = UW =\n"\ desc += "UX = 0 (where 'S' is for supervisor permissions and 'U' is for user\n"\ desc += "permissions). 01: RGDn access flags are defined in RGDn_WORD3[ACCSET1]. 10:\n"\ desc += "RGDn access flags are defined in RGDn_WORD3[ACCSET2]. 11: RGDn access flags\n"\ desc += "are defined in RGDn_WORD3[ACCSET3]. Writes to this word clear the region\n"\ desc += "descriptor's valid bit." %define _DESC2209_ \ desc += "Bus master 0 permission select" %define _DESC2210_ \ desc += "Bus master 1 permission select" %define _DESC2211_ \ desc += "Bus master 2 permission select" %define _DESC2212_ \ desc += "Bus master 3 permission select" %define _DESC2213_ \ desc += "Bus master 4 permission select" %define _DESC2214_ \ desc += "Bus master 5 permission select" %define _DESC2215_ \ desc += "Bus master 6 permission select" %define _DESC2216_ \ desc += "Bus master 7 permission select" %define _DESC2217_ \ desc += "Bus master 8 permission select" %define _DESC2218_ \ desc += "Bus master 9 permission select" %define _DESC2219_ \ desc += "Bus master 10 permission select" %define _DESC2220_ \ desc += "Bus master 11 permission select" %define _DESC2221_ \ desc += "Bus master 12 permission select" %define _DESC2222_ \ desc += "Bus master 13 permission select" %define _DESC2223_ \ desc += "Bus master 14 permission select" %define _DESC2224_ \ desc += "Bus master 15 permission select" %define _DESC2225_ \ desc += "Region Descriptor n, Word 3. The final word of the SMPU region descriptor\n"\ desc += "contains the valid bit, the format select (FMT), three sets of access\n"\ desc += "permissions flags used when FMT = 1, plus other configuration bits.\n\n"\ desc += "For access permissions used when FMT = 1, there are three flags {read, write,\n"\ desc += "execute} for each operating mode (supervisor, user). These flags follow the\n"\ desc += "traditional definition:\n\n"\ desc += "Read (r) permission refers to the ability to access the referenced memory\n"\ desc += "address using an operand (data) fetch. Write (w) permission refers to the\n"\ desc += "ability to update the referenced memory address using a store (data)\n"\ desc += "instruction. Execute (x) permission refers to the ability to read the\n"\ desc += "referenced memory address using an instruction fetch. Each ACCSET field\n"\ desc += "consists of six independent bits, enabling supervisor read, write, and execute\n"\ desc += "permissions {SR, SW, SX} and user read, write, and execute permissions {UR, UW,\n"\ desc += "UX}. If set, the bit allows the given access type to occur; if cleared, an\n"\ desc += "attempted access of that mode may be terminated with an access error (if not\n"\ desc += "allowed by any other descriptor) and the access is not performed.\n\n"\ desc += "The ACCSET bits are in this order: {SR, SW, SX, UR, UW, UX} with SR being in\n"\ desc += "the most significant position. For example, the SR bit within the ACCSET1 field\n"\ desc += "is register bit 0.\n\n"\ desc += "When FMT = 0, the ACCSET fields are not writable." %define _DESC2226_ \ desc += "Access controls, Set 1\n\n"\ desc += "Defines a set of access control options for RGD_WORD2_FMT1." %define _DESC2227_ \ desc += "Access controls, Set 2\n\n"\ desc += "Defines a set of access control options for RGD_WORD2_FMT1." %define _DESC2228_ \ desc += "Access controls, Set 3\n\n"\ desc += "Defines a set of access control options for RGD_WORD2_FMT1." %define _DESC2229_ \ desc += "Region Descriptor Format\n\n"\ desc += "This bit selects the configuration format (FMT0 or FMT1) for this region\n"\ desc += "descriptor.\n\n"\ desc += "A specific module instance of the SMPU may support only the FMT0 format. If so,\n"\ desc += "the FMT field is read-only with a fixed value of 0 and only RGD_WORD2_FMT0\n"\ desc += "applies." %define _DESC2230_ \ desc += "Read-Only\n\n"\ desc += "This bit is intended to prevent accidental writes of an SMPU region\n"\ desc += "descriptor.\n\n"\ desc += "Setting RO in an RGD locks all four words of the RGD until a system reset; the\n"\ desc += "valid bit of the RGD and the global valid bit have no effect." %define _DESC2231_ \ desc += "Cache Inhibit\n\n"\ desc += "Defines the cacheability attribute of the memory region. This bit is returned\n"\ desc += "to the bus master that initiated the memory reference.\n\n"\ desc += "An address range specified in an SMPU region descriptor for a cacheable space\n"\ desc += "(that is, CI = 0) must be defined with a starting address aligned on a\n"\ desc += "0-modulo-32 byte address and with a multiple of the 32 byte cache line size." %define _DESC2232_ \ desc += "Valid\n\n"\ desc += "Signals the region descriptor is valid. Any write to RGDn_WORD0-2 clears this\n"\ desc += "bit." %define _DESC2233_ \ desc += "Global Control Register. This register provides the global control and setting\n"\ desc += "for the SENT Receiver Module. The SENT_EN bit must be programmed after all\n"\ desc += "other modules settings and control bits have been written to." %define _DESC2234_ \ desc += "Time Stamp Prescaler Value. Value in number of clock cycles of high frequency\n"\ desc += "receiver clock set in order to obtain a clock frequency for the time stamp\n"\ desc += "counter block.\n\n"\ desc += "0 Prescaler Bypassed. Time Stamp Clock = High Frequency Receiver Clock\n\n"\ desc += "1 to 255 Value set by user software to obtain a clock period of at least 1us\n"\ desc += "for the time stamp counter.\n\n"\ desc += "If the high frequency clock input is 75 MHz, then the value set in this field\n"\ desc += "would be 0x4B (or 75) to obtain a 1us clock.\n\n"\ desc += "Note: Since the time stamp clock is common for all channels, the timestamp\n"\ desc += "clock frequency must be at least twice the fastest receiver channel in the\n"\ desc += "application. This is to ensure that the time stamp clock is fast enough to show\n"\ desc += "change in timestamp from message to message." %define _DESC2235_ \ desc += "Fast Message DMA Underflow Interrupt Enable: Enables interrupt assertion when\n"\ desc += "there is an underflow condition on Fast Message DMA registers. Default value is\n"\ desc += "0." %define _DESC2236_ \ desc += "Slow Serial Message DMA Underflow Interrupt Enable: Enables interrupt assertion\n"\ desc += "when there is an underflow condition on Slow Message DMA registers. Default\n"\ desc += "value is 0." %define _DESC2237_ \ desc += "Fast Clearing Enable bit. Enables clearing of ready status (for both fast and\n"\ desc += "slow) bit automatically when corresponding message is read. Default value is 1.\n"\ desc += "See FMSG_RDY and SMSG_RDY for details on the ready status bits." %define _DESC2238_ \ desc += "Debug Freeze. This bit will enable the debug mode support. SENT Module will\n"\ desc += "freeze in debug mode if this bit is set. Default is 0." %define _DESC2239_ \ desc += "SENT Receiver Global Enable. This bit enables or disables the complete receiver\n"\ desc += "module irrespective of the setting of individual channel enable bits. User\n"\ desc += "software must program all channel parameters before setting this bit. Default\n"\ desc += "is 0." %define _DESC2240_ \ desc += "Channel Enable Register. This register is used to enable individual SENT\n"\ desc += "Receiver channels in the module. The user software must ensure all channel\n"\ desc += "parameters and control settings have been programmed before writing to this\n"\ desc += "bit. In case these parameters are changed while the channel is enabled, normal\n"\ desc += "operation is not guaranteed.\n\n"\ desc += "The following register figure and table shows the maximum possible\n"\ desc += "configuration but the exact number of valid register bits are dependent on\n"\ desc += "supported SENT channels on the device. Please see the device configuration\n"\ desc += "section for number of support SENT channels. Reads of bits beyond the supported\n"\ desc += "number of channels should be ignored and these bits must be written to 0." %define _DESC2241_ \ desc += "Enable bits for Channels 0 to 15. All channels are disabled after reset. User\n"\ desc += "software must program all channel parameters before setting this bit. Once set,\n"\ desc += "other channel parameters in registers should not be changed until this bit is\n"\ desc += "cleared. Only Interrupt Enable and Status bits can be written to." %define _DESC2242_ \ desc += "Global Status Register. This register provides the status of various conditions\n"\ desc += "in the module that are common across all channels." %define _DESC2243_ \ desc += "Fast Message DMA Underflow: Interrupt Status bit that indicates when there is\n"\ desc += "an underflow in Fast Message buffers in any channel which has DMA enabled. \n"\ desc += "Default value is 0." %define _DESC2244_ \ desc += "Slow Serial Message DMA Underflow: Interrupt Status bit that indicates when\n"\ desc += "there is an Underflow in Slow Serial Message DMA buffers on channel which has\n"\ desc += "DMA enabled. The bit is set when there is no message in the DMA buffers for\n"\ desc += "read and the software still reads the Slow Serial Message registers. Default\n"\ desc += "value is 0." %define _DESC2245_ \ desc += "Fast Message Ready Status Register. The bits of this register are asserted when\n"\ desc += "a Fast Message arrives on a corresponding channel that is not configured to be\n"\ desc += "read via DMA. If a channel is not configured for DMA (via FDMA_CTRL ), it is\n"\ desc += "assumed to be read via Interrupt or Polling this status bit. Even if the\n"\ desc += "Interrupt Enable bit for that channel is not set (via FRDY_IE ) and the channel\n"\ desc += "is enabled, the message ready status bit in this register will be asserted on\n"\ desc += "Fast Message reception. Software must ensure that if a channel is enabled;\n"\ desc += "either DMA or Interrupt must be enabled for that channel. Proper flow cannot be\n"\ desc += "guaranteed if neither is selected.\n\n"\ desc += "These bits can be configured to be cleared via 'Write 1 to Clear' or 'Fast\n"\ desc += "Clearing Mechanism'. The configuration is done by writing to the FAST_CLR bit\n"\ desc += "in the GBL_CTRL .\n\n"\ desc += "The following register figure and table shows the maximum possible\n"\ desc += "configuration but the exact number of valid register bits are dependent on\n"\ desc += "supported SENT channels on the device. Please see the device configuration\n"\ desc += "section for number of support SENT channels. Reads of bits beyond the supported\n"\ desc += "number of channels should be ignored and writes to these bits are unadvisable\n"\ desc += "and may cause unexpected behavior." %define _DESC2246_ \ desc += "Fast Message Data Ready Status Bit. Indicates that a Fast Message is ready to\n"\ desc += "be read by CPU from that specific channel. This bit is asserted only when DMA\n"\ desc += "is NOT enabled for that channel (from the DMA Control Register) and an error\n"\ desc += "free message is received, irrespective of the value of corresponding enable bit\n"\ desc += "in Message Ready Interrupt Control Register. Reading the message from the\n"\ desc += "corresponding memory-mapped Fast Message Read Registers would automatically\n"\ desc += "clear this bit (Fast Clearing Mechanism).\n\n"\ desc += "These bits are either 'write 1 to clear' (w1c) or self-clearing depending on\n"\ desc += "the value of the FAST_CLR BIT in the Global Control Register (GBL_CTRL). The\n"\ desc += "clearing mechanism is selected by user by programming the FAST_CLR bit in the\n"\ desc += "Global Control register. See Section GBL_CTRL for details on FAST_CLR bit.\n\n"\ desc += "When using the fast clearing option, these bits will not clear till the\n"\ desc += "complete message is read out which requires the CPU to read all 3 fast message\n"\ desc += "registers via 32-bit read accesses. For 8/16-bit accesses fast clearing\n"\ desc += "mechanism should not be used as it is not supported. When the fast clearing\n"\ desc += "option is not configured, the bits will be cleared only if 1 is written to\n"\ desc += "those bits. 0 No Fast Message is available to be read out via Interrupt\n\n"\ desc += "1 Fast Message is available to be read out via Interrupt" %define _DESC2247_ \ desc += "Slow Serial Message Ready Status Register. The bits of this register are\n"\ desc += "asserted when a Slow Serial Message arrives on a corresponding channel that is\n"\ desc += "not configured to be read via DMA. If a channel is not configured for DMA (via\n"\ desc += "FDMA_CTRL and SDMA_CTRL ), it is assumed to be read via Interrupt or Polling\n"\ desc += "this status bit. Even if the Interrupt Enable bit for that channel is not set\n"\ desc += "(via FRDY_IE and SRDY_IE ) and the channel is enabled, the message ready status\n"\ desc += "bit in this register will be asserted on Slow Message reception. Software must\n"\ desc += "ensure that if a channel is enabled; either DMA or Interrupt must be enabled\n"\ desc += "for that channel. Erroneous flow can happen if neither is selected.\n\n"\ desc += "These bits can be configured to be cleared via 'Write 1 to Clear' or 'Fast\n"\ desc += "Clearing Mechanism'. The configuration is done by writing to the FAST_CLR bit\n"\ desc += "in the GBL_CTRL .\n\n"\ desc += "The following register figure and table shows the maximum possible\n"\ desc += "configuration but the exact number of valid register bits are dependent on\n"\ desc += "supported SENT channels on the device. Please see the device configuration\n"\ desc += "section for number of support SENT channels. Reads of bits beyond the supported\n"\ desc += "number of channels should be ignored and writes to these bits are unadvisable\n"\ desc += "and may cause unexpected behavior." %define _DESC2248_ \ desc += "Slow Serial Message Data Ready Status Bit. Indicates that a Slow Serial Message\n"\ desc += "is ready to be read by CPU from that specific channel. This bit is asserted\n"\ desc += "only when DMA is NOT enabled for that channel (from the DMA Control Register)\n"\ desc += "and an error free message is received, irrespective of the value of\n"\ desc += "corresponding enable bit in Message Ready Interrupt Control Register. Reading\n"\ desc += "the message from the corresponding memory-mapped Serial Message Read Registers\n"\ desc += "would automatically clear this bit (Fast Clearing Mechanism).\n\n"\ desc += "These bits are either 'write 1 to clear' (w1c) or self-clearing depending on\n"\ desc += "the value of the FAST_CLR bit in the Global Control Register (GBL_CTRL). The\n"\ desc += "clearing mechanism is selected by user by programming the FAST_CLR bit in the\n"\ desc += "Global Control register. See Section GBL_CTRL for details on FAST_CLR bit.\n\n"\ desc += "When using the fast clearing option, these bits will not clear till the\n"\ desc += "complete message is read out which requires the CPU to read all 3 Fast Message\n"\ desc += "registers via 32-bit read accesses. For 8/16-bit accesses fast clearing\n"\ desc += "mechanism should not be used as it is not supported. When the fast clearing\n"\ desc += "option is not configured, the bits will be cleared only if 1 is written to\n"\ desc += "those bits. 0 No Slow Serial Message is available to be read out via\n"\ desc += "Interrupt\n\n"\ desc += "1 Slow Serial Message is available to be read out via Interrupt" %define _DESC2249_ \ desc += "Data Control Register 1. The Data Control Register 1 (DATA_CTRL1) is described\n"\ desc += "below." %define _DESC2250_ \ desc += "Number of Data Nibbles supported in Channel 0\n\n"\ desc += "0 and 7 Invalid value. Must not be used\n\n"\ desc += "1 to 6 Number of data nibbles to be supported by respective channel" %define _DESC2251_ \ desc += "Number of Data Nibbles supported in Channel 1\n\n"\ desc += "0 and 7 Invalid value. Must not be used\n\n"\ desc += "1 to 6 Number of data nibbles to be supported by respective channel" %define _DESC2252_ \ desc += "Number of Data Nibbles supported in Channel 2\n\n"\ desc += "0 and 7 Invalid value. Must not be used\n\n"\ desc += "1 to 6 Number of data nibbles to be supported by respective channel" %define _DESC2253_ \ desc += "Number of Data Nibbles supported in Channel 3\n\n"\ desc += "0 and 7 Invalid value. Must not be used\n\n"\ desc += "1 to 6 Number of data nibbles to be supported by respective channel" %define _DESC2254_ \ desc += "Number of Data Nibbles supported in Channel 4\n\n"\ desc += "0 and 7 Invalid value. Must not be used\n\n"\ desc += "1 to 6 Number of data nibbles to be supported by respective channel" %define _DESC2255_ \ desc += "Number of Data Nibbles supported in Channel 5\n\n"\ desc += "0 and 7 Invalid value. Must not be used\n\n"\ desc += "1 to 6 Number of data nibbles to be supported by respective channel" %define _DESC2256_ \ desc += "Number of Data Nibbles supported in Channel 6\n\n"\ desc += "0 and 7 Invalid value. Must not be used\n\n"\ desc += "1 to 6 Number of data nibbles to be supported by respective channel" %define _DESC2257_ \ desc += "Number of Data Nibbles supported in Channel 7\n\n"\ desc += "0 and 7 Invalid value. Must not be used\n\n"\ desc += "1 to 6 Number of data nibbles to be supported by respective channel" %define _DESC2258_ \ desc += "Data Control Register 2. " %define _DESC2259_ \ desc += "Number of Data Nibbles supported in Channel 8\n\n"\ desc += "0 and 7 Invalid value. Must not be used\n\n"\ desc += "1 to 6 Number of data nibbles to be supported by respective channel" %define _DESC2260_ \ desc += "Number of Data Nibbles supported in Channel 9\n\n"\ desc += "0 and 7 Invalid value. Must not be used\n\n"\ desc += "1 to 6 Number of data nibbles to be supported by respective channel" %define _DESC2261_ \ desc += "Number of Data Nibbles supported in Channel 10\n\n"\ desc += "0 and 7 Invalid value. Must not be used\n\n"\ desc += "1 to 6 Number of data nibbles to be supported by respective channel" %define _DESC2262_ \ desc += "Number of Data Nibbles supported in Channel 11\n\n"\ desc += "0 and 7 Invalid value. Must not be used\n\n"\ desc += "1 to 6 Number of data nibbles to be supported by respective channel" %define _DESC2263_ \ desc += "Number of Data Nibbles supported in Channel 12\n\n"\ desc += "0 and 7 Invalid value. Must not be used\n\n"\ desc += "1 to 6 Number of data nibbles to be supported by respective channel" %define _DESC2264_ \ desc += "Number of Data Nibbles supported in Channel 13\n\n"\ desc += "0 and 7 Invalid value. Must not be used\n\n"\ desc += "1 to 6 Number of data nibbles to be supported by respective channel" %define _DESC2265_ \ desc += "Number of Data Nibbles supported in Channel 14\n\n"\ desc += "0 and 7 Invalid value. Must not be used\n\n"\ desc += "1 to 6 Number of data nibbles to be supported by respective channel" %define _DESC2266_ \ desc += "Number of Data Nibbles supported in Channel 15\n\n"\ desc += "0 and 7 Invalid value. Must not be used\n\n"\ desc += "1 to 6 Number of data nibbles to be supported by respective channel" %define _DESC2267_ \ desc += "Fast Message DMA Control Register. The following register figure and table\n"\ desc += "shows the maximum possible configuration but the exact number of valid register\n"\ desc += "bits are dependent on supported SENT channels on the device. Please see the\n"\ desc += "device configuration section for number of support SENT channels. Reads of bits\n"\ desc += "beyond the supported number of channels should be ignored and writes to these\n"\ desc += "bits are unadvisable and may cause unexpected behavior. RW" %define _DESC2268_ \ desc += "Enable DMA for Fast Messages on Channels 0 to 15. These bits are writeable when\n"\ desc += "corresponding Fast Message Ready Interrupt Enable bits are set to 0." %define _DESC2269_ \ desc += "Slow Serial Message DMA Control Register. The following register figure and\n"\ desc += "table shows the maximum possible configuration but the exact number of valid\n"\ desc += "register bits are dependent on supported SENT channels on the device. Please\n"\ desc += "see the device configuration section for number of support SENT channels. Reads\n"\ desc += "of bits beyond the supported number of channels should be ignored and writes to\n"\ desc += "these bits are unadvisable and may cause unexpected behavior." %define _DESC2270_ \ desc += "Enable DMA for Slow Serial Messages on Channels 0 to 15. These bits are\n"\ desc += "writeable when corresponding Slow Serial Message Ready Interrupt Enable bits\n"\ desc += "are set to 0." %define _DESC2271_ \ desc += "Fast Message Ready Interrupt Control Register. The following register figure\n"\ desc += "and table shows the maximum possible configuration but the exact number of\n"\ desc += "valid register bits are dependent on supported SENT channels on the device.\n"\ desc += "Please see the device configuration section for number of support SENT\n"\ desc += "channels.Reads of bits beyond the supported number of channels should be\n"\ desc += "ignored and writes to these bits are unadvisable and may cause unexpected\n"\ desc += "behavior." %define _DESC2272_ \ desc += "Enable for Fast Message Ready Interrupt on Channels 0 to 15. These bits are\n"\ desc += "writeable when corresponding DMA enable bits are set to 0 in the Fast Message\n"\ desc += "DMA Control Register. The availability of message is indicated via assertion of\n"\ desc += "corresponding bit in Fast Message Ready Status Register irrespective of the\n"\ desc += "value set in corresponding interrupt enable bit and DMA is not enabled. When a\n"\ desc += "bit is asserted in this register, an interrupt for corresponding channel is\n"\ desc += "generated." %define _DESC2273_ \ desc += "Slow Serial Message Ready Interrupt Enable Register. The following register\n"\ desc += "figure and table shows the maximum possible configuration but the exact number\n"\ desc += "of valid register bits are dependent on supported SENT channels on the device.\n"\ desc += "Please see the device configuration section for number of support SENT\n"\ desc += "channels. Reads of bits beyond the supported number of channels should be\n"\ desc += "ignored and writes to these bits are unadvisable and may cause unexpected\n"\ desc += "behavior." %define _DESC2274_ \ desc += "Enable for Slow Serial Message Ready Interrupt on Channels 0 to 15. These bits\n"\ desc += "are writeable when corresponding DMA enable bits are set to 0 in the Slow\n"\ desc += "Serial DMA Control Register. The availability of message is indicated via\n"\ desc += "assertion of corresponding bit in Slow Serial Message Ready Status Register\n"\ desc += "irrespective of the value set in corresponding interrupt enable bit and DMA is\n"\ desc += "not enabled. When a bit in this register is asserted, an interrupt for\n"\ desc += "corresponding channel is generated." %define _DESC2275_ \ desc += "DMA Fast Message Data Read Register. DMA Source Size must be set to 32 bits\n"\ desc += "when reading this register (DMA_FMSG_DATA) via DMA." %define _DESC2276_ \ desc += "Channel Number. Indicates the channel number of the received message being read\n"\ desc += "by DMA. Valid values are 0 to '15'" %define _DESC2277_ \ desc += "Status and Communication Nibble of message" %define _DESC2278_ \ desc += "Data Nibble 1. Always supported" %define _DESC2279_ \ desc += "Data Nibble 2. Should be ignored if number of data nibbles supported by channel\n"\ desc += "is 1" %define _DESC2280_ \ desc += "Data Nibble 3. Should be ignored if number of data nibbles supported by channel\n"\ desc += "is 2 or less" %define _DESC2281_ \ desc += "Data Nibble 4. Should be ignored if number of data nibbles supported by channel\n"\ desc += "is 3 or less" %define _DESC2282_ \ desc += "Data Nibble 5. Should be ignored if number of data nibbles supported by channel\n"\ desc += "is 4 or less" %define _DESC2283_ \ desc += "Data Nibble 6. Should be ignored if number of data nibbles supported by channel\n"\ desc += "is 5 or less" %define _DESC2284_ \ desc += "DMA Fast Message CRC Read Register. DMA Source Size must be set to 32 bits when\n"\ desc += "reading this register (DMA_FMSG_CRC) via DMA." %define _DESC2285_ \ desc += "4-bit CRC value of the message." %define _DESC2286_ \ desc += "DMA Fast Message Time Stamp Read Register. The resolution of the time stamp is\n"\ desc += "set by programming the Time Stamp Prescaler Value in the GBL_CTRL register. DMA\n"\ desc += "Source Size must be set to 32 bits when reading this register (DMA_FMSG_TS) via\n"\ desc += "DMA." %define _DESC2287_ \ desc += "Time Stamp for received message. Indicates the relative time when the falling\n"\ desc += "edge that comes at the end of the calibration pulse (which is also the start of\n"\ desc += "the status and communication nibble pulse) was detected" %define _DESC2288_ \ desc += "DMA Slow Serial Message Bit3 Read Register. The above register (DMA_SMSG_BIT3)\n"\ desc += "is common for all types of slow serial messages. Bit C defines the type of\n"\ desc += "enhanced packet and bit TYPE defines whether it is short serial or enhanced\n"\ desc += "serial message. Since this register is used to read both Short and Enhanced\n"\ desc += "Serial Messages, the register fields have been placed in such a way to match\n"\ desc += "the bit positions in actual message defined by SAE Specification as shown in ,\n"\ desc += "and . and shows the enhanced serial messages format to be used when reading\n"\ desc += "this register for these two types of messages. shows the short serial\n"\ desc += "message.\n\n"\ desc += "DMA Source Size must be set to 32 bits when reading this register via DMA.\n\n"\ desc += "If the TYPE bit in the register reads '0', then remainder bits (for CFG, ID and\n"\ desc += "DATA) will be redundant and read zeros. The short serial message will be\n"\ desc += "located in DMA_SMSG_BIT2 register fields. If TYPE bit is '1', then the message\n"\ desc += "in register is Enhanced Serial Message and using CFG bit, software can decode\n"\ desc += "the ID and DATA fields." %define _DESC2289_ \ desc += "Serial Message Type. Indicates the type of Serial Message received" %define _DESC2290_ \ desc += "Placed as 0 by Specification" %define _DESC2291_ \ desc += "Configuration bit 'C'. Indicates the type of Enhanced Serial message" %define _DESC2292_ \ desc += "ID Field. Value depends on setting of 'C' bit. If 'C' bit is 0, this field is\n"\ desc += "ID[7:4] and if the 'C' bit is 1, this field is ID[3:0]" %define _DESC2293_ \ desc += "0 as per SAE Specification" %define _DESC2294_ \ desc += "ID or Data Field. Value depends on setting of 'C' bit. If 'C' bit is 0, this\n"\ desc += "field is ID[3:0] and if the 'C' bit is 1, this field is Data[15:12]" %define _DESC2295_ \ desc += "DMA Slow Serial Message Bit2 Read Register. This register (DMA_SMSG_BIT2) is\n"\ desc += "common for all types of slow serial messages. Hence, the register fields have\n"\ desc += "been placed in such a way to match the bit positions in actual message defined\n"\ desc += "by SAE Specification as shown in , and . , and shows the enhanced serial\n"\ desc += "messages format to be used when reading this register for these two types of\n"\ desc += "messages. shows the short serial message.\n\n"\ desc += "DMA Source Size must be set to 32 bits when reading this register via DMA." %define _DESC2296_ \ desc += "6-bit CRC value of the message. When TYPE bit in DMA_SMSG_BIT3 is set to 0,\n"\ desc += "this CRC is of 4-bits for Short Serial Messages and when TYPE bit is set to 1,\n"\ desc += "this CRC is of 6-bits for Enhanced Serial Messages." %define _DESC2297_ \ desc += "12-bit Data Value" %define _DESC2298_ \ desc += "DMA Slow Serial Message Time Stamp Read Register. The resolution of the time\n"\ desc += "stamp is set by programming the Time Stamp Prescaler Value in the GBL_CTRL\n"\ desc += "register.\n\n"\ desc += "DMA Source Size must be set to 32 bits when reading this register (DMA_SMSG_TS)\n"\ desc += "via DMA." %define _DESC2299_ \ desc += "Time Stamp for the received message. Indicates the relative time of detection\n"\ desc += "of the falling edge that comes at the end of the calibration pulse (which is\n"\ desc += "also the start of the status and communication nibble pulse) of the last Fast\n"\ desc += "Message that completed the Serial Message. Time Stamp for Slow Serial Messages\n"\ desc += "is not latched when the Slow Serial Message starts but when the Slow Serial\n"\ desc += "Message is completely received." %define _DESC2300_ \ desc += "Channel 'n' Clock Control Register (n = 0 to (CH-1)). The value of the CH is\n"\ desc += "device-specific. See the device configuration section for details. The SENT\n"\ desc += "Receiver module generates the Receiver Sensor Clock (or simply Receiver Clock)\n"\ desc += "internally to sample the incoming filtered sensor data. The user software must\n"\ desc += "program the prescaler value (for Receiver Clock) to match the ideal Sensor Tx\n"\ desc += "Clock period. The generated Receiver Clock is compensated for variations, clock\n"\ desc += "drift and jitter that might occur in the Sensor Tx Clock. See Adjustment for\n"\ desc += "variation in sensor (Tx) clock for more details.\n\n"\ desc += "This register configures the generation and subsequent compensation logic of\n"\ desc += "the Receiver Clock. User must program the contents of this register before\n"\ desc += "enabling the channel by writing to the corresponding channel enable bit in the\n"\ desc += "CHNL_EN ." %define _DESC2301_ \ desc += "Compensated Prescaler Value. This is the compensated prescaler value calculated\n"\ desc += "by Clock Compensation logic and this value is used to compensate for sensor Tx\n"\ desc += "clock variation. This value is indicated as a read only field for use by user\n"\ desc += "software, if needed. This is a 15-bit value.\n\n"\ desc += "'= Rx Prescaler Value' No variation, hence no compensation or Compensation is\n"\ desc += "disabled\n\n"\ desc += "'< Rx Prescaler Value' Tx Clock is SLOWER than the programmed receive clock\n\n"\ desc += "'> Rx Prescaler Value' Tx Clock is FASTER than the programmed receive clock\n\n"\ desc += "Thus, the new Receiver Clock Tick Period can be computed by software as\n\n"\ desc += "Compensated Prescaler Value x High Frequency Receiver Clock Period" %define _DESC2302_ \ desc += "Compensation Enable. To enable compensation logic to adjust the receiver clock\n"\ desc += "against variation in Tx clock on this channel. User must set the Prescaler\n"\ desc += "Value before enabling this bit." %define _DESC2303_ \ desc += "Rx Prescaler Value. This factor is required to generate required Receiver Clock\n"\ desc += "tick from the High Frequency Receiver Clock. This value can only be written\n"\ desc += "when Channel Enable bit is Zero. Hence this value must be programmed before\n"\ desc += "enabling the channel. If required receiver clock tick period (Trx_clk) is not\n"\ desc += "divisible by the high frequency receiver clock (protocol clock) period\n"\ desc += "(Thf_clk), the required prescaler value will have a fractional part which\n"\ desc += "cannot be programmed. In this case then user is advised to program the\n"\ desc += "prescaler value to the lower integer value.\n\n"\ desc += "0 Prescaler is bypassed. Should not be used.\n\n"\ desc += "Non-Zero Value Enables Prescaler\n\n"\ desc += "The required value is computed by software as follows:\n\n"\ desc += "(both clock periods taken in us).\n\n"\ desc += "Please see High frequency receiver clock (protocol clock) requirements before\n"\ desc += "setting this value.\n\n"\ desc += "e.g. if the required receiver clock tick period is 43 us and the High Frequency\n"\ desc += "Receiver clock is selected to be 62.5 MHz (or 0.016 us) then,\n\n"\ desc += "Prescaler Value = 43/0.016 = 2687.5. Hence user must program 2687 in this\n"\ desc += "register." %define _DESC2304_ \ desc += "Channel 'n' Status Register (n=0 to (CH-1)). This registers stores information\n"\ desc += "about certain events and error conditions that occur in the channel during the\n"\ desc += "message reception process. The assertion of these bit is not linked to any\n"\ desc += "message but it is a general alert to the CPU that a particular condition (error\n"\ desc += "or normal event) happened in the recent past. Messages are automatically\n"\ desc += "discarded when an error is detected.\n\n"\ desc += "User software can clear these bit at any time by writing 1 to them. This\n"\ desc += "register can be updated at any time irrespective of the setting in the CHNL_EN\n"\ desc += "bit for the corresponding channel.\n\n"\ desc += "The value of the CH is device-specific. See the device configuration section\n"\ desc += "for details." %define _DESC2305_ \ desc += "Bus Idle Status. This bit indicates that the sensor interface has been idle for\n"\ desc += "more than the period defined by the programmed Bus Idle Count value(in\n"\ desc += "CH_CONFIG ). CPU should write 1 to this clear this bit once it is read." %define _DESC2306_ \ desc += "Successive Calibration Check (Option 2 of SAE SENT Spec) Resynchronized. This\n"\ desc += "bit indicates that Successive Calibration Check (Option 2 of SAE Spec) has\n"\ desc += "failed three times and has resynchronized to assume 3rd message to be correct\n"\ desc += "and will be received. The successive calibration check error will also be\n"\ desc += "asserted during re-synchronization (to indicate the 3rd error being\n"\ desc += "detected)." %define _DESC2307_ \ desc += "Calibration Variation 20 - 25% Interrupt Status. This bit indicates that the\n"\ desc += "calibration pulse received on this channel has variation in between +-20% to\n"\ desc += "+-25% from 56 ticks." %define _DESC2308_ \ desc += "Slow Serial Message Overflow Status. This bit indicates overflow occurred on\n"\ desc += "this channel. Overflow will cause the older messages (which are not read out)\n"\ desc += "to be overwritten with newly received messages. However, any message that is\n"\ desc += "currently being read out by DMA or CPU will not get over-written." %define _DESC2309_ \ desc += "Fast Message Overflow Status. This bit indicates overflow occurred on this\n"\ desc += "channel. Overflow happens when effective data read rate by CPU is slower than\n"\ desc += "data receive rate on channel. On overflow, new incoming messages will overwrite\n"\ desc += "the previous messages (that are not read out) stored in the receiver buffers.\n"\ desc += "However, any message that is currently being read out by DMA or CPU will not\n"\ desc += "get over-written." %define _DESC2310_ \ desc += "This diagnostic checks status bit indicates that the ratio of calibration pulse\n"\ desc += "length to overall message length (with pause pulse) is more than +-1.5625%\n"\ desc += "between two messages. This check is valid only for messages with pause pulse.\n"\ desc += "This bit indicates whether this diagnostic has failed or passed on this\n"\ desc += "channel, and is cleared by writing a 1 to it." %define _DESC2311_ \ desc += "This diagnostic checks status bit indicates that Calibration pulse is more than\n"\ desc += "56 ticks +-25%. This bit indicates whether this diagnostic has failed or passed\n"\ desc += "on this channel, and is cleared by writing a 1 to it." %define _DESC2312_ \ desc += "Successive Calibration pulses differ by +-1.56%. SAE spec defines it be 1.5625%\n"\ desc += "but the accuracy of this check depends on the frequency of protocol clock (See\n"\ desc += "High frequency receiver clock (protocol clock) requirements ). This diagnostic\n"\ desc += "checks status bit indicates whether this diagnostic has failed or passed on\n"\ desc += "this channel, and is cleared by writing a 1 to it." %define _DESC2313_ \ desc += "Any nibble data value 15. This diagnostic checks status bit indicates whether\n"\ desc += "this diagnostic has failed or passed on this channel, and is cleared by writing\n"\ desc += "a 1 to it." %define _DESC2314_ \ desc += "Checksum error in Slow Serial Message. This diagnostic checks status bit\n"\ desc += "indicates whether this diagnostic has failed or passed on this channel, and is\n"\ desc += "cleared by writing a 1 to it." %define _DESC2315_ \ desc += "Checksum error in Fast Message. This diagnostic checks status bit indicates\n"\ desc += "whether this diagnostic has failed or passed on this channel, and is cleared by\n"\ desc += "writing a 1 to it." %define _DESC2316_ \ desc += "Not the expected number of negative edges between calibration pulse. This\n"\ desc += "diagnostic checks status bit indicates whether this diagnostic has failed or\n"\ desc += "passed on this channel. This bit will not set in case of 'Option 2' for\n"\ desc += "successive calibration pulse check is selected. This error will only set when\n"\ desc += "'Option 1' for successive calibration check is selected (SUCC_CAL_CHK). This\n"\ desc += "bit is cleared by writing a 1 to it." %define _DESC2317_ \ desc += "Channel 'n' Configuration Register (n=0 to (CH-1)). This register (CHn_CONFIG)\n"\ desc += "provides the configurability for interrupt assertion for various events and\n"\ desc += "error as explained in CH_STATUS and control bits for selection of various\n"\ desc += "receive options that might be required by the user software. This register also\n"\ desc += "configures the width of noise glitches (on the sensor input) to be filtered out\n"\ desc += "by the input programmable filter.\n\n"\ desc += "User must program the contents of this register before enabling the channel by\n"\ desc += "writing to the corresponding channel enable bit in the CHNL_EN .\n\n"\ desc += "The value of the CH is device-specific. See the device configuration section\n"\ desc += "for details." %define _DESC2318_ \ desc += "Bus Idle Count. This register value defines the maximum allowable idle period\n"\ desc += "on the sensor interface of this channel. The value is defined as follows:" %define _DESC2319_ \ desc += "Successive Calibration Check Resynchronized Interrupt Enable: This bit enables\n"\ desc += "interrupt assertion when Successive Calibration diagnosis has failed three\n"\ desc += "times in case of 'Option 2' being selected for Successive Calibration Check\n"\ desc += "Method and the check resynchronizes the take the third message to be correct." %define _DESC2320_ \ desc += "Calibration Variation 20 - 25% Interrupt Enable. This bit enables interrupt\n"\ desc += "assertion when corresponding status bit is set." %define _DESC2321_ \ desc += "Slow Serial Message Overflow Interrupt Enable. This bit enables interrupt\n"\ desc += "assertion when overflow occurs on reception of Slow Serial Messages in\n"\ desc += "corresponding channel" %define _DESC2322_ \ desc += "Fast Message Overflow Interrupt Enable. This bit enables interrupt assertion\n"\ desc += "when overflow occurs on\n\n"\ desc += "reception of Fast Messages in corresponding channel." %define _DESC2323_ \ desc += "Fast Message CRC Check Off: This bit can be used to switch off CRC check in\n"\ desc += "Fast Message" %define _DESC2324_ \ desc += "Ratio of calibration pulse length to message length varies by more than\n"\ desc += "+-1.5625% between two frames. Valid for messages with pause pulse. This bit\n"\ desc += "enables interrupt assertion when its respective diagnostic check fails on the\n"\ desc += "corresponding channel." %define _DESC2325_ \ desc += "Calibration pulse is wider than 56 ticks +-25%. This bit enables interrupt\n"\ desc += "assertion when its respective diagnostic check fails on the corresponding\n"\ desc += "channel." %define _DESC2326_ \ desc += "Successive Calibration pulses differ by more than +-1.56%. SAE spec defines it\n"\ desc += "be 1.5625% but the accuracy of this check depends on the protocol clock. For\n"\ desc += "instance for 62.5 MHz, this check will fail for 1.56% and passes for 1.55%.\n"\ desc += "This bit enables interrupt assertion when its respective diagnostic check fails\n"\ desc += "on the corresponding channel." %define _DESC2327_ \ desc += "Any nibble data value 15. This bit enables interrupt assertion when its\n"\ desc += "respective diagnostic check fails on the corresponding channel." %define _DESC2328_ \ desc += "Checksum error in Slow Serial Message. This bit enables interrupt assertion\n"\ desc += "when its respective diagnostic check fails on the corresponding channel." %define _DESC2329_ \ desc += "Checksum error in Fast Message. This bit enables interrupt assertion when its\n"\ desc += "respective diagnostic check fails on the corresponding channel." %define _DESC2330_ \ desc += "Not the expected number of negative edges between calibration pulse. This bit\n"\ desc += "enables interrupt assertion when its respective diagnostic check fails on the\n"\ desc += "corresponding channel." %define _DESC2331_ \ desc += "Enable for Interrupt on Reception of Fast Message with Changed Data: This bit\n"\ desc += "is used to enable storing and generating corresponding DMA or Message Ready\n"\ desc += "Interrupt Request for Fast Message only when any of the data nibbles after\n"\ desc += "different from previously received Fast Message on that channel. If a new Fast\n"\ desc += "Message is received that has same values for all data nibbles as that of\n"\ desc += "previous message then the current message will be discarded and will not be\n"\ desc += "stored in the buffer , and neither Fast Message Ready Interrupt nor DMA request\n"\ desc += "will be generated." %define _DESC2332_ \ desc += "Valid Calibration Pulse Range Selection: This bit is used to control whether\n"\ desc += "20% variation or 25% variation in Calibration Pulse will be tolerated when\n"\ desc += "detecting a Calibration Pulse" %define _DESC2333_ \ desc += "Pause Pulse Diagnostic Check Selection: This bit controls which diagnostic\n"\ desc += "checks to run when messages are enabled to be received with pause pulses." %define _DESC2334_ \ desc += "Fast Message CRC Type. This indicates the type of CRC method to be used for CRC\n"\ desc += "Diagnostic Check on the received fast messages" %define _DESC2335_ \ desc += "Fast Message CRC Status and Communication Nibble Enable. This bit enables the\n"\ desc += "inclusion of Status and Communication Nibble when CRC is calculated for Fast\n"\ desc += "Messages." %define _DESC2336_ \ desc += "Slow Serial Message CRC Type. This indicates the type of CRC method to be used\n"\ desc += "for CRC Diagnostic Check on the received slow serial messages." %define _DESC2337_ \ desc += "Pause Pulse Enable. Enables the channel receiver to detect a pause pulse." %define _DESC2338_ \ desc += "Successive Calibration Pulse Check Method. This bit indicates the method to be\n"\ desc += "used for performing the successive calibration pulse check. Default value is\n"\ desc += "1." %define _DESC2339_ \ desc += "Input Filter Sample Count. This indicates the number of Protocol Clock (of High\n"\ desc += "Frequency Receiver Clock) cycles required for channel input from device's pad\n"\ desc += "to remain stable before it is sampled as 0 or 1. This field defines the width\n"\ desc += "of glitches to be filtered out by the input programmable filter on that\n"\ desc += "channel. Only one bit should be set in this field and the output of filter will\n"\ desc += "be offset by twice the same number of clocks plus additional 3 clocks due to\n"\ desc += "synchronization. Default value is '4'.\n\n"\ desc += "0 No filtering. Input from device's pad is only synchronized\n\n"\ desc += "1 Non-Zero Filtering is enabled" %define _DESC2340_ \ desc += "Channel 'n' Fast Message Data Read Register (n=0 to (CH-1)). Address offset:\n"\ desc += "0x0160 + 0x18 x n\n\n"\ desc += "This is register CHn_FMSG_DATA. The contents of this register are same as\n"\ desc += "DMA_FMSG_DATA .\n\n"\ desc += "The value of the CH is device-specific. See the device configuration section\n"\ desc += "for details." %define _DESC2341_ \ desc += "Channel 'n' Fast Message CRC Read Register (n=0 to (CH-1)). Address offset:\n"\ desc += "0x0164 + 0x18 x n\n\n"\ desc += "This is register CHn_FMSG_CRC. The contents of this register are same as\n"\ desc += "DMA_FMSG_CRC ." %define _DESC2342_ \ desc += "Channel 'n' Fast Message Time Stamp Read Register (n=0 to (CH-1)). Address\n"\ desc += "offset: 0x0168 + 0x18 x n\n\n"\ desc += "This is register CHn_FMSG_TS. The contents of this register are same as\n"\ desc += "DMA_FMSG_TS ." %define _DESC2343_ \ desc += "Channel 'n' Serial Message Read Register (Bit 3) (n=0 to (CH-1)). Address\n"\ desc += "offset: 0x016C + 0x18 x n\n\n"\ desc += "This is register CHn_SMSG_BIT3. The contents of this register are same as\n"\ desc += "DMA_SMSG_BIT3 . The value of the CH is device-specific. See the device\n"\ desc += "configuration section for details." %define _DESC2344_ \ desc += "Always reads 0 by Specification" %define _DESC2345_ \ desc += "Channel 'n' Serial Message Read Register (Bit 2)(n=0 to (CH-1)). Address\n"\ desc += "offset: 0x0170 + 0x18 x n\n\n"\ desc += "This is register CHn_SMSG_BIT2. The contents of this register are same as\n"\ desc += "DMA_SMSG_BIT2 ." %define _DESC2346_ \ desc += "Channel 'n' Serial Message Time Stamp Read Register (n=0 to (CH-1)). Address\n"\ desc += "offset: 0x0174 + 0x18 x n\n\n"\ desc += "This is register CHn_SMSG_TS. The contents of this register are same as\n"\ desc += "DMA_SMSG_TS ." %define _DESC2347_ \ desc += "SSCM System Status. The System Status register reflects the current state of\n"\ desc += "the system." %define _DESC2348_ \ desc += "This field indicates that the SSCM has detected a configuration error during\n"\ desc += "reset. If a non-permanent error is detected, this bit can be cleared by writing\n"\ desc += "a 1." %define _DESC2349_ \ desc += "" %define _DESC2350_ \ desc += "This field is only updated during reset.\n\n"\ desc += "Reset value depends on the device status after leaving reset." %define _DESC2351_ \ desc += "Variable Length Instruction Mode. When booting in SC mode, this field indicates\n"\ desc += "that the code stored in the flash memory is using the VLE instruction set. The\n"\ desc += "value of this field is determined by the RCHW field of the flash memory boot\n"\ desc += "sector.\n\n"\ desc += "Reset value depends on the associated option bits in flash memory." %define _DESC2352_ \ desc += "SSCM System Memory and ID Register. The System Memory and ID register is a\n"\ desc += "read-only register which reflects the memory configuration of the system. It\n"\ desc += "also contains the JTAG ID." %define _DESC2353_ \ desc += "JTAG Part ID Number\n\n"\ desc += "Reset value reflets the JTAG ID of the device." %define _DESC2354_ \ desc += "SSCM Error Configuration Register. The Error Configuration register is a\n"\ desc += "read-write register that controls the error handling of the system." %define _DESC2355_ \ desc += "Peripheral Bus Abort Enable. This bit enables bus aborts on any access to a\n"\ desc += "peripheral slot that is not used on the device. This feature is intended to aid\n"\ desc += "in debugging when developing application code." %define _DESC2356_ \ desc += "Register Bus Abort Enable. This bit enables bus aborts on illegal accesses to\n"\ desc += "off-platform peripherals. Illegal accesses are defined as reads or writes to\n"\ desc += "reserved addresses within the address space for a particular peripheral. This\n"\ desc += "feature is intended to aid in debugging when developing application code.\n\n"\ desc += "Transfers to peripheral bus resources may be aborted even before they reach the\n"\ desc += "peripheral bus (in example, at the AIPS level). In this case, the PAE and RAE\n"\ desc += "register bits have no effect on the abort." %define _DESC2357_ \ desc += "Processor Start Address Register. " %define _DESC2358_ \ desc += "The boot processor will start executing application code from this address. In\n"\ desc += "SC mode this indicates the location determined by the RCHW search." %define _DESC2359_ \ desc += ". " %define _DESC2360_ \ desc += "Determined by the SSCM by reading the PLC slots. The encoding is:" %define _DESC2361_ \ desc += "Determined by the SSCM by reading the LC slots. The encoding is:" %define _DESC2362_ \ desc += "STM Control Register. The STM Control Register includes the prescale value,\n"\ desc += "freeze control and timer enable bits." %define _DESC2363_ \ desc += "Selects the clock divide value for the prescaler (1 - 256).\n\n"\ desc += "0x00 Divide system clock by 1\n\n"\ desc += "0x01 Divide system clock by 2\n\n"\ desc += "-----------------------\n\n"\ desc += "0xFF Divide system clock by 256" %define _DESC2364_ \ desc += "Allows the timer counter to be stopped when the device enters debug mode.\n\n"\ desc += "When the microcomputer enters debug mode, the STM is notified and uses the FRZ\n"\ desc += "bit to determine counter mode." %define _DESC2365_ \ desc += "STM Count Register. The STM Count Register holds the timer count value." %define _DESC2366_ \ desc += "When enabled, the counter increments at the rate of the system clock divided by\n"\ desc += "the prescale value." %define _DESC2367_ \ desc += "STM Channel Control Register. The STM Channel Control Register (STM_CCRn) has\n"\ desc += "the enable bit for channel n of the timer." %define _DESC2368_ \ desc += "STM Channel Interrupt Register. The STM Channel Interrupt Register has the\n"\ desc += "interrupt flag for channel n of the timer." %define _DESC2369_ \ desc += "STM Channel Compare Register. The STM channel compare register (STM_CMPn) holds\n"\ desc += "the compare value for channel n." %define _DESC2370_ \ desc += "If the STM_CCRn[CEN] bit is set and the STM_CMPn register matches the STM_CNT\n"\ desc += "register, a channel interrupt request is generated and the STM_CIRn[CIF] bit is\n"\ desc += "set." %define _DESC2371_ \ desc += "SWT Control Register. The SWT_CR contains fields for configuring and\n"\ desc += "controlling the SWT.\n\n"\ desc += "This register is read-only if either the SWT_CR[HLK] or SWT_CR[SLK] bits are\n"\ desc += "set." %define _DESC2372_ \ desc += "Master Access Protection for Master 0. The platform bus master assignments are\n"\ desc += "device specific.\n\n"\ desc += "Not all MAPn fields are implemented. See the device configuration section for\n"\ desc += "master ports that are implemented on the crossbar switch." %define _DESC2373_ \ desc += "Master Access Protection for Master 1. The platform bus master assignments are\n"\ desc += "device specific.\n\n"\ desc += "Not all MAPn fields are implemented. See the device configuration section for\n"\ desc += "master ports that are implemented on the crossbar switch." %define _DESC2374_ \ desc += "Master Access Protection for Master 2. The platform bus master assignments are\n"\ desc += "device specific.\n\n"\ desc += "Not all MAPn fields are implemented. See the device configuration section for\n"\ desc += "master ports that are implemented on the crossbar switch." %define _DESC2375_ \ desc += "Master Access Protection for Master 3. The platform bus master assignments are\n"\ desc += "device specific.\n\n"\ desc += "Not all MAPn fields are implemented. See the device configuration section for\n"\ desc += "master ports that are implemented on the crossbar switch." %define _DESC2376_ \ desc += "Master Access Protection for Master 4. The platform bus master assignments are\n"\ desc += "device specific.\n\n"\ desc += "Not all MAPn fields are implemented. See the device configuration section for\n"\ desc += "master ports that are implemented on the crossbar switch." %define _DESC2377_ \ desc += "Master Access Protection for Master 5. The platform bus master assignments are\n"\ desc += "device specific.\n\n"\ desc += "Not all MAPn fields are implemented. See the device configuration section for\n"\ desc += "master ports that are implemented on the crossbar switch." %define _DESC2378_ \ desc += "Master Access Protection for Master 6. The platform bus master assignments are\n"\ desc += "device specific.\n\n"\ desc += "Not all MAPn fields are implemented. See the device configuration section for\n"\ desc += "master ports that are implemented on the crossbar switch." %define _DESC2379_ \ desc += "Master Access Protection for Master 7. The platform bus master assignments are\n"\ desc += "device specific.\n\n"\ desc += "Not all MAPn fields are implemented. See the device configuration section for\n"\ desc += "master ports that are implemented on the crossbar switch." %define _DESC2380_ \ desc += "00 Fixed Service Sequence, the watchdog is serviced by writing the fixed\n"\ desc += "sequence 0xA602, 0xB480 to the SWT_SR.\n\n"\ desc += "01 Keyed Service Sequence, the watchdog is serviced by writing two pseudorandom\n"\ desc += "key values to the SWT_SR.\n\n"\ desc += "10 Reserved--do not use. Writing a value can cause the SWT not to be\n"\ desc += "serviced.\n\n"\ desc += "11 Reserved--do not use. Writing this value can cause the SWT not to be\n"\ desc += "serviced." %define _DESC2381_ \ desc += "Reset on Invalid Access." %define _DESC2382_ \ desc += "Window Mode." %define _DESC2383_ \ desc += "Interrupt Then Reset." %define _DESC2384_ \ desc += "Hard Lock. This bit is cleared only at reset." %define _DESC2385_ \ desc += "Soft Lock. This bit is cleared by writing the unlock sequence to the service\n"\ desc += "register." %define _DESC2386_ \ desc += "Stop Mode Control. Allows the watchdog timer to be stopped when the device\n"\ desc += "enters stop mode." %define _DESC2387_ \ desc += "Debug Mode Control. Allows the watchdog timer to be stopped when the device\n"\ desc += "enters debug mode." %define _DESC2388_ \ desc += "Watchdog Enabled." %define _DESC2389_ \ desc += "SWT Interrupt Register. The SWT_IR contains the time-out interrupt flag." %define _DESC2390_ \ desc += "Time-out Interrupt Flag. The flag and interrupt are cleared by writing a 1 to\n"\ desc += "this bit. Writing a 0 has no effect." %define _DESC2391_ \ desc += "SWT Time-out Register. The SWT Time-Out (SWT_TO) register contains the 32-bit\n"\ desc += "time-out period. This register is read-only if either the SWT_CR[HLK] or\n"\ desc += "SWT_CR[SLK] bits are set." %define _DESC2392_ \ desc += "Watchdog time-out period in clock cycles. An internal 32-bit down counter is\n"\ desc += "loaded with , when the service sequence is written or when the SWT is\n"\ desc += "enabled." %define _DESC2393_ \ desc += "SWT Window Register. The SWT Window (SWT_WN) register contains the 32-bit\n"\ desc += "window start value. This register is cleared on reset. This register is\n"\ desc += "read-only if either the SWT_CR[HLK] or SWT_CR[SLK] bits are set." %define _DESC2394_ \ desc += "Window start value. When window mode is enabled, the service sequence can only\n"\ desc += "be written when the internal down counter is less than this value." %define _DESC2395_ \ desc += "SWT Service Register. The SWT Service (SWT_SR) register is the target for\n"\ desc += "service operation writes used to reset the watchdog timer." %define _DESC2396_ \ desc += "Watchdog Service Code.This field is used to service the watchdog and to clear\n"\ desc += "the soft lock bit (SWT_CR[SLK]). If the SWT_CR[KEY] bit is set, two\n"\ desc += "pseudorandom key values are written to service the watchdog, see Functional\n"\ desc += "description for details. Otherwise, the sequence 0xA602 followed by 0xB480 is\n"\ desc += "written to the WSC field. To clear the soft lock bit (SWT_CR[SLK]), the value\n"\ desc += "0xC520 followed by 0xD928 is written to the WSC field. When read, the WSC field\n"\ desc += "always returns zero." %define _DESC2397_ \ desc += "SWT Counter Output Register. The SWT Counter Output (SWT_CO) register is a\n"\ desc += "read-only register that shows the value of the internal down counter when the\n"\ desc += "SWT is disabled." %define _DESC2398_ \ desc += "Watchdog Count. When the watchdog is disabled (SWT_CR[WEN]=0), this field shows\n"\ desc += "the value of the internal down counter. When the watchdog is enabled\n"\ desc += "(SWT_CR[WEN]=1), this field is cleared (the value is 0x0000_0000). Values in\n"\ desc += "this field can lag behind the internal counter value for up to six system plus\n"\ desc += "eight counter clock cycles. Therefore, the value read from this field\n"\ desc += "immediately after disabling the watchdog may be higher than the actual value of\n"\ desc += "the internal counter." %define _DESC2399_ \ desc += "SWT Service Key Register. The SWT Service Key (SWT_SK) register holds the\n"\ desc += "previous (or initial) service key value. This register is read-only if either\n"\ desc += "the SWT_CR[HLK] or SWT_CR[SLK] bits are set." %define _DESC2400_ \ desc += "Service Key.This field is the previous (or initial) service key value used in\n"\ desc += "keyed service mode. If SWT_CR[KEY] is set, the next key value to be written to\n"\ desc += "the SWT_SR is (17*SK+3) mod 2 16 ." %define _DESC2401_ \ desc += "NMI Status Flag Register. This register holds the status flags of the NMI\n"\ desc += "external source pin . This register is a clear-by-write-1 register type,\n"\ desc += "preventing inadvertent overwriting of other flags in the same register. The\n"\ desc += "status flag is set whenever an NMI event is detected. The overrun flag is set\n"\ desc += "whenever an NMI event is detected and the status flag is set (i.e., has not\n"\ desc += "yet been cleared).\n\n"\ desc += "The status flags are set independently of the NDSS bits. Therefore, these\n"\ desc += "flags can set but not generate a non-maskable interrupt or system wakeup if\n"\ desc += "NWRE = 0 or if NDSS is set to 'no request'.\n\n"\ desc += "The overrun flag is cleared by writing a '1' to the appropriate overrun bit in\n"\ desc += "the NSR. If the status bit is cleared and the overrun bit is still set, the\n"\ desc += "pending interrupt will not be cleared. NIF is set when all the following are\n"\ desc += "true: NMI Destination Source Select is disabled (NDSS = 11) NMI System Wakeup\n"\ desc += "Request is disabled (NWRE = 0) An NMI input event is seen Also see the notes\n"\ desc += "in NCR ." %define _DESC2402_ \ desc += "If enabled (i.e., NCR[NREE1] or NCR[NFEE1] is set), an NMI input event will set\n"\ desc += "NIF1. NIF1 causes an interrupt request based on the NMI destination, as\n"\ desc += "configured by NCR[NDSS1], and/or a system wakeup request based on NCR[NWRE1]." %define _DESC2403_ \ desc += "This field is a copy of the current NIF1 value whenever a NMI event occurs,\n"\ desc += "thereby indicating to the software that an NMI occurred while the last one was\n"\ desc += "not yet serviced. NOVF1 causes an interrupt request based on the NMI\n"\ desc += "destination, as configured by the NCR[NDSS1] bits, and/or a system wakeup\n"\ desc += "request based on the NCR[NWRE1] bit configuration." %define _DESC2404_ \ desc += "If enabled (i.e., if NCR[RREE] or NCR[RFEE] is set), this status bit is set and\n"\ desc += "will cause a functional reset request to the RGM if NCR[RDSS] equals 00b. This\n"\ desc += "bit is automatically cleared if the ESR1 reset request is configured in the\n"\ desc += "MC_RGM to generate a long or short 'functional' reset." %define _DESC2405_ \ desc += "This field is a copy of the current RIF value whenever a NMI event occurs,\n"\ desc += "thereby indicating to the software that an NMI occurred while the last one was\n"\ desc += "not yet serviced. If enabled (i.e., NCR[RREE] or NCR[RFEE] is set), this field\n"\ desc += "can cause a reset request to MC_RGM if NCR[RDSS] equals 00b. This bit is\n"\ desc += "automatically cleared if the ESR1 reset request is configured in the MC_RGM to\n"\ desc += "generate a long or short 'functional' reset." %define _DESC2406_ \ desc += "NMI Configuration Register. This register holds the configuration bits for the\n"\ desc += "non-maskable interrupt settings.\n\n"\ desc += "Writing a '0' to both NREE n and NFEE n disables the NMI functionality\n"\ desc += "completely (i.e. no system wakeup or interrupt will be generated on any pad\n"\ desc += "activity). Writing to the NCR when NIF = 1 or NOVF = 1 causes an interrupt to\n"\ desc += "the destination source/system wakeup to be generated independent of an NMI\n"\ desc += "wakeup event." %define _DESC2407_ \ desc += "Wakeup/Interrupt Status Flag Register. This register holds the wakeup/interrupt\n"\ desc += "flags." %define _DESC2408_ \ desc += "Interrupt Request Enable Register. This register is used to enable the\n"\ desc += "interrupt messaging from the wakeup/interrupt pads to the interrupt\n"\ desc += "controller" %define _DESC2409_ \ desc += "Wakeup/Interrupt Rising-Edge Event Enable Register. This register is used to\n"\ desc += "enable rising-edge triggered events on the corresponding wakeup/interrupt\n"\ desc += "pads" %define _DESC2410_ \ desc += "Wakeup/Interrupt Falling-Edge Event Enable Register. This register is used to\n"\ desc += "enable falling-edge triggered events on the corresponding wakeup/interrupt\n"\ desc += "pads" %define _DESC2411_ \ desc += "XBAR Priority Registers Slave. The priority registers (XBAR x _PRS n ) set the\n"\ desc += "priority of each master port on a per-slave-port basis and reside in each slave\n"\ desc += "port. The priority register can be accessed only with 32-bit accesses. The XBAR\n"\ desc += "x _PRS n register is read-only; attempts to write to it have no effect on it\n"\ desc += "and result in a bus-error response to the master initiating the write.\n\n"\ desc += "See the 'Crossbar switch configuration' section in the chip-specific details\n"\ desc += "for XBAR x _PRS n priority values." %define _DESC2412_ \ desc += "Master 2 priority. Sets the arbitration priority for this port on the\n"\ desc += "associated slave port:" %define _DESC2413_ \ desc += "Master 1 priority. Sets the arbitration priority for this port on the\n"\ desc += "associated slave port:" %define _DESC2414_ \ desc += "Master 0 priority. Sets the arbitration priority for this port on the\n"\ desc += "associated slave port:" %define _DESC2415_ \ desc += "XBAR Control Register. " %define _DESC2416_ \ desc += "Read only\n\n"\ desc += "Forces both of the slave port's registers to be read-only. After set, only a\n"\ desc += "hardware reset clears it." %define _DESC2417_ \ desc += "Halt Request Priority\n\n"\ desc += "Determines if a request to halt the crossbar is treated as the highest priority\n"\ desc += "request, or the lowest priority request." %define _DESC2418_ \ desc += "High Priority Enable\n\n"\ desc += "Determines if Master 2 is able to temporarily elevate it's request to the slave\n"\ desc += "to high priority status. This can help reduce the amount of time the high\n"\ desc += "priority requesting master must wait to gain control of the slave." %define _DESC2419_ \ desc += "High Priority Enable\n\n"\ desc += "Determines if Master 1 is able to temporarily elevate it's request to the slave\n"\ desc += "to high priority status. This can help reduce the amount of time the high\n"\ desc += "priority requesting master must wait to gain control of the slave." %define _DESC2420_ \ desc += "High Priority Enable\n\n"\ desc += "Determines if Master 0 is able to temporarily elevate it's request to the slave\n"\ desc += "to high priority status. This can help reduce the amount of time the high\n"\ desc += "priority requesting master must wait to gain control of the slave." %define _DESC2421_ \ desc += "Arbitration mode\n\n"\ desc += "Selects the arbitration policy for the slave port." %define _DESC2422_ \ desc += "Parking control\n\n"\ desc += "Determines the slave port's parking control. The low-power park feature results\n"\ desc += "in overall power savings if the slave port is not saturated; however, this\n"\ desc += "forces an extra latency clock when any master tries to access the slave port\n"\ desc += "while not in use because it is not parked on any master." %define _DESC2423_ \ desc += "Park\n\n"\ desc += "Determines which master port the current slave port parks on when no masters\n"\ desc += "are actively making requests and the PCTL bits are cleared.\n\n"\ desc += "Only select master ports that are actually present on the device. If not,\n"\ desc += "undefined behavior may occur." %define _DESC2424_ \ desc += "XOSC Control Register. The XOSC_CTL is only writable in supervisor mode." %define _DESC2425_ \ desc += "Crystal Oscillator bypass\n\n"\ desc += "This bit specifies whether the oscillator should be bypassed or not. Software\n"\ desc += "can only set this bit. System reset is needed to reset this bit." %define _DESC2426_ \ desc += "These bits specify the end of count value to be used for comparison by the\n"\ desc += "oscillator stabilization counter OSCCNT after reset or whenever it is switched\n"\ desc += "on from the off state. This counting period ensures that external oscillator\n"\ desc += "clock signal is stable before it can be selected by the system. When oscillator\n"\ desc += "counter reaches the value EOCV x 512, oscillator available interrupt request is\n"\ desc += "generated. The OSCCNT counter is kept under reset if oscillator bypass mode is\n"\ desc += "selected." %define _DESC2427_ \ desc += "This bit masks the I_OSC interrupt bit." %define _DESC2428_ \ desc += "Crystal oscillator clock interrupt\n\n"\ desc += "This bit is set by hardware when OSCCNT counter reaches the count value EOCV x\n"\ desc += "512. It is cleared by software by writing 1." %define _DESC2429_ \ desc += "Control Register. The CR defines the basic operating configuration of the\n"\ desc += "DMA.\n\n"\ desc += "The DMA arbitrates channel service requests 16 channels.\n\n"\ desc += "Arbitration can be configured to use a fixed-priority or a round-robin scheme.\n"\ desc += "In fixed-priority arbitration, the highest priority channel requesting service\n"\ desc += "is selected to execute. The channel priority registers assign the priorities\n"\ desc += "(see the DCHPRI n registers). In Round-Robin Arbitration mode, the channel\n"\ desc += "priorities are ignored, and channels are cycled through without regard to\n"\ desc += "priority.\n\n"\ desc += "Writes to the DMA_CR must be performed only when the DMA channels are inactive\n"\ desc += "(TCDn_CSR[ACTIVE] bits are cleared)." %define _DESC2430_ \ desc += "Cancel transfer" %define _DESC2431_ \ desc += "Error cancel transfer" %define _DESC2432_ \ desc += "Enable minor loop mapping" %define _DESC2433_ \ desc += "Continuous Link mode" %define _DESC2434_ \ desc += "Halt DMA operations" %define _DESC2435_ \ desc += "Halt on error" %define _DESC2436_ \ desc += "Enable round-robin group arbitration" %define _DESC2437_ \ desc += "Enable round-robin channel arbitration" %define _DESC2438_ \ desc += "Enable debug" %define _DESC2439_ \ desc += "Error Status. The ES provides information concerning the last recorded channel\n"\ desc += "error. Channel errors can be caused by a configuration error (an illegal\n"\ desc += "setting in the transfer-control descriptor or an illegal priority register\n"\ desc += "setting in Fixed Arbitration mode) or an error termination to a bus master read\n"\ desc += "or write cycle.\n\n"\ desc += "See Error reporting and handling for more details." %define _DESC2440_ \ desc += "ERRL status bits" %define _DESC2441_ \ desc += "Uncorrectable ECC error\n\n"\ desc += "0 No uncorrectable ECC error\n\n"\ desc += "1 The last recorded error was an uncorrectable TCD RAM error" %define _DESC2442_ \ desc += "Transfer cancelled" %define _DESC2443_ \ desc += "Channel priority error" %define _DESC2444_ \ desc += "Error channel number and/or last recorded error cancelled transfer" %define _DESC2445_ \ desc += "Source address error" %define _DESC2446_ \ desc += "Source offset error" %define _DESC2447_ \ desc += "Destination address error" %define _DESC2448_ \ desc += "Destination offset error" %define _DESC2449_ \ desc += "NBYTES/CITER configuration error" %define _DESC2450_ \ desc += "Scatter/gather configuration error" %define _DESC2451_ \ desc += "Source bus error" %define _DESC2452_ \ desc += "Destination bus error" %define _DESC2453_ \ desc += "Enable Request Register Low. The ERQ registers provide a bit map for the \n"\ desc += "implemented channels to enable the request signal for each channel. EQRL covers\n"\ desc += "channels -00.\n\n"\ desc += "The state of any given channel enable is directly affected by writes to this\n"\ desc += "register; it is also affected by writes to the SERQ and CERQ. The {S,C}ERQ\n"\ desc += "registers are provided so the request enable for a single channel can easily be\n"\ desc += "modified without needing to perform a read-modify-write sequence to the ERQ \n"\ desc += ".\n\n"\ desc += "DMA request input signals and this enable request flag must be asserted before\n"\ desc += "a channel's hardware service request is accepted. The state of the DMA enable\n"\ desc += "request flag does not affect a channel service request made explicitly through\n"\ desc += "software or a linked channel request." %define _DESC2454_ \ desc += "Enable DMA Request 15" %define _DESC2455_ \ desc += "Enable DMA Request 14" %define _DESC2456_ \ desc += "Enable DMA Request 13" %define _DESC2457_ \ desc += "Enable DMA Request 12" %define _DESC2458_ \ desc += "Enable DMA Request 11" %define _DESC2459_ \ desc += "Enable DMA Request 10" %define _DESC2460_ \ desc += "Enable DMA Request 9" %define _DESC2461_ \ desc += "Enable DMA Request 8" %define _DESC2462_ \ desc += "Enable DMA Request 7" %define _DESC2463_ \ desc += "Enable DMA Request 6" %define _DESC2464_ \ desc += "Enable DMA Request 5" %define _DESC2465_ \ desc += "Enable DMA Request 4" %define _DESC2466_ \ desc += "Enable DMA Request 3" %define _DESC2467_ \ desc += "Enable DMA Request 2" %define _DESC2468_ \ desc += "Enable DMA Request 1" %define _DESC2469_ \ desc += "Enable DMA Request 0" %define _DESC2470_ \ desc += "Enable Error Interrupt Register Low. The Enable Error Interrupt Register Low\n"\ desc += "(DMA_EEIL) provides a bit map for the channels to enable the error interrupt\n"\ desc += "signal for each channel.EEIL covers channels -00. The state of any given\n"\ desc += "channel's error interrupt enable is directly affected by writes to this\n"\ desc += "register; it is also affected by writes to the SEEI and CEEI. The {S,C}EEI are\n"\ desc += "provided so the error interrupt enable for a single channel can easily be\n"\ desc += "modified without the need to perform a read-modify-write sequence to the EEI \n"\ desc += "registers.\n\n"\ desc += "The DMA error indicator and the error interrupt enable flag must be asserted\n"\ desc += "before an error interrupt request for a given channel is asserted to the\n"\ desc += "interrupt controller." %define _DESC2471_ \ desc += "Enable error interrupt 15" %define _DESC2472_ \ desc += "Enable error interrupt 14" %define _DESC2473_ \ desc += "Enable error interrupt 13" %define _DESC2474_ \ desc += "Enable error interrupt 12" %define _DESC2475_ \ desc += "Enable error interrupt 11" %define _DESC2476_ \ desc += "Enable error interrupt 10" %define _DESC2477_ \ desc += "Enable error interrupt 9" %define _DESC2478_ \ desc += "Enable error interrupt 8" %define _DESC2479_ \ desc += "Enable error interrupt 7" %define _DESC2480_ \ desc += "Enable error interrupt 6" %define _DESC2481_ \ desc += "Enable error interrupt 5" %define _DESC2482_ \ desc += "Enable error interrupt 4" %define _DESC2483_ \ desc += "Enable error interrupt 3" %define _DESC2484_ \ desc += "Enable error interrupt 2" %define _DESC2485_ \ desc += "Enable error interrupt 1" %define _DESC2486_ \ desc += "Enable error interrupt 0" %define _DESC2487_ \ desc += "Set Enable Request Register. The Set Enable Request Register (DMA_SERQ)\n"\ desc += "provides a simple memory-mapped mechanism to set a given bit in the ERQ to\n"\ desc += "enable the DMA request for a given channel. The data value on a register write\n"\ desc += "causes the corresponding bit in the ERQ to be set. Setting the SAER bit\n"\ desc += "provides a global set function, forcing the entire contents of ERQ to be set.\n"\ desc += "If the NOP bit is set, the command is ignored. This allows you to write\n"\ desc += "multiple-byte registers as a 32-bit word. Reads of this register return all\n"\ desc += "zeroes." %define _DESC2488_ \ desc += "No operation" %define _DESC2489_ \ desc += "Set all enable requests" %define _DESC2490_ \ desc += "Set enable request\n\n"\ desc += "Sets the corresponding bit in ERQ" %define _DESC2491_ \ desc += "Clear Enable Request Register. The Clear Enable Request Register (DMA_CERQ)\n"\ desc += "provides a simple memory-mapped mechanism to clear a given bit in the ERQ to\n"\ desc += "disable the DMA request for a given channel. The data value on a register write\n"\ desc += "causes the corresponding bit in the ERQ to be cleared. Setting the CAER bit\n"\ desc += "provides a global clear function, forcing the entire contents of the ERQ to be\n"\ desc += "cleared, disabling all DMA request inputs.\n\n"\ desc += "If NOP is set, the command is ignored. This allows you to write multiple-byte\n"\ desc += "registers as a 32-bit word. Reads of this register return all zeroes." %define _DESC2492_ \ desc += "Clear all enable requests" %define _DESC2493_ \ desc += "Clear enable request\n\n"\ desc += "Clears the corresponding bit in ERQ" %define _DESC2494_ \ desc += "Set Enable Error Interrupt Register. The Set Enable Error Interrupt Register\n"\ desc += "(DMA_SEEI) provides a simple memory-mapped mechanism to set a given bit in the\n"\ desc += "EEI to enable the error interrupt for a given channel. The data value on a\n"\ desc += "register write causes the corresponding bit in the EEI to be set. Setting the\n"\ desc += "SAEE bit provides a global set function, forcing the entire EEI contents to be\n"\ desc += "set. If the NOP bit is set, the command is ignored. This allows you to write\n"\ desc += "multiple-byte registers as a 32-bit word. Reads of this register return all\n"\ desc += "zeroes." %define _DESC2495_ \ desc += "Sets all enable error interrupts" %define _DESC2496_ \ desc += "Set enable error interrupt\n\n"\ desc += "Sets the corresponding bit in EEI" %define _DESC2497_ \ desc += "Clear Enable Error Interrupt Register. The Clear Enable Error Interrupt\n"\ desc += "Register (DMA_CEEI) provides a simple memory-mapped mechanism to clear a given\n"\ desc += "bit in the EEI to disable the error interrupt for a given channel. The data\n"\ desc += "value on a register write causes the corresponding bit in the EEI to be\n"\ desc += "cleared. Setting the CAEE bit provides a global clear function, forcing the EEI\n"\ desc += "contents to be cleared, disabling all DMA request inputs.\n\n"\ desc += "If the NOP bit is set, the command is ignored. This allows you to write\n"\ desc += "multiple-byte registers as a 32-bit word. Reads of this register return all\n"\ desc += "zeroes." %define _DESC2498_ \ desc += "Clear all enable error interrupts" %define _DESC2499_ \ desc += "Clear enable error interrupt\n\n"\ desc += "Clears the corresponding bit in EEI" %define _DESC2500_ \ desc += "Clear Interrupt Request Register. The Clear Interrupt Request Register\n"\ desc += "(DMA_CINT) provides a simple, memory-mapped mechanism to clear a given bit in\n"\ desc += "the INT to disable the interrupt request for a given channel. The given value\n"\ desc += "on a register write causes the corresponding bit in the INT to be cleared.\n"\ desc += "Setting the CAIR bit provides a global clear function, forcing the entire\n"\ desc += "contents of the INT to be cleared, disabling all DMA interrupt requests.\n\n"\ desc += "If the NOP bit is set, the command is ignored. This allows you to write\n"\ desc += "multiple-byte registers as a 32-bit word. Reads of this register return all\n"\ desc += "zeroes." %define _DESC2501_ \ desc += "Clear all interrupt requests" %define _DESC2502_ \ desc += "Clear interrupt request\n\n"\ desc += "Clears the corresponding bit in INT" %define _DESC2503_ \ desc += "Clear Error Register. The CERR provides a simple memory-mapped mechanism to\n"\ desc += "clear a given bit in the ERR{H,L} to disable the error condition flag for a\n"\ desc += "given channel. The given value on a register write causes the corresponding bit\n"\ desc += "in the ERR{H,L} to be cleared. Setting the CAEI bit provides a global clear\n"\ desc += "function, forcing the ERR{H,L} contents to be cleared, clearing all channel\n"\ desc += "error indicators. If the NOP bit is set, the command is ignored. This allows\n"\ desc += "you to write multiple-byte registers as a 32-bit word. Reads of this register\n"\ desc += "return all zeroes." %define _DESC2504_ \ desc += "Clear all error indicators" %define _DESC2505_ \ desc += "Clear error indicator\n\n"\ desc += "Clears the corresponding bit in ERR" %define _DESC2506_ \ desc += "Set START Bit Register. The Set START Bit Register (DMA_SSRT) provides a simple\n"\ desc += "memory-mapped mechanism to set the START bit in the TCD of the given channel.\n"\ desc += "The data value on a register write causes the START bit in the corresponding\n"\ desc += "transfer control descriptor to be set. Setting the SAST bit provides a global\n"\ desc += "set function, forcing all START bits to be set. If the NOP bit is set, the\n"\ desc += "command is ignored. This allows you to write multiple-byte registers as a\n"\ desc += "32-bit word. Reads of this register return all zeroes." %define _DESC2507_ \ desc += "Set all START bits (activates all channels)" %define _DESC2508_ \ desc += "Set START bit\n\n"\ desc += "Sets the corresponding bit in TCD n _CSR[START]" %define _DESC2509_ \ desc += "Clear DONE Status Bit Register. The Clear DONE Status Bit Register (DMA_CDNE)\n"\ desc += "provides a simple memory-mapped mechanism to clear the DONE bit in the TCD of\n"\ desc += "the given channel. The data value on a register write causes the DONE bit in\n"\ desc += "the corresponding transfer control descriptor to be cleared. Setting the CADN\n"\ desc += "bit provides a global clear function, forcing all DONE bits to be cleared. If\n"\ desc += "the NOP bit is set, the command is ignored. This allows you to write\n"\ desc += "multiple-byte registers as a 32-bit word. Reads of this register return all\n"\ desc += "zeroes." %define _DESC2510_ \ desc += "Clears all DONE bits" %define _DESC2511_ \ desc += "Clear DONE bit\n\n"\ desc += "Clears the corresponding bit in TCD n _CSR[DONE]" %define _DESC2512_ \ desc += "Interrupt Request Register Low. The Interrupt Request Register Low (DMA_INTL)\n"\ desc += "provides a bit map for the lower half of the channels signaling the presence\n"\ desc += "of an interrupt request for each channel. Depending on the appropriate bit\n"\ desc += "setting in the transfer-control descriptors, the eDMA engine generates an\n"\ desc += "interrupt at data transfer completion. The outputs of this register are\n"\ desc += "directly routed to the interrupt controller (INTC). During the\n"\ desc += "interrupt-service routine associated with any given channel, it is the\n"\ desc += "software's responsibility to clear the appropriate bit, negating the interrupt\n"\ desc += "request. Typically, a write to the CINT in the interrupt service routine is\n"\ desc += "used for this purpose.\n\n"\ desc += "The state of any given channel's interrupt request is directly affected by\n"\ desc += "writes to this register; it is also affected by writes to the CINT. On writes\n"\ desc += "to the INT, a '1' in any bit position clears the corresponding channel's\n"\ desc += "interrupt request. A zero in any bit position has no effect on the\n"\ desc += "corresponding channel's current interrupt status. The CINT is provided so the\n"\ desc += "interrupt request for a single channel can easily be cleared without the need\n"\ desc += "to perform a read-modify-write sequence to the INT ." %define _DESC2513_ \ desc += "Interrupt request 15" %define _DESC2514_ \ desc += "Interrupt request 14" %define _DESC2515_ \ desc += "Interrupt request 13" %define _DESC2516_ \ desc += "Interrupt request 12" %define _DESC2517_ \ desc += "Interrupt request 11" %define _DESC2518_ \ desc += "Interrupt request 10" %define _DESC2519_ \ desc += "Interrupt request 9" %define _DESC2520_ \ desc += "Interrupt request 8" %define _DESC2521_ \ desc += "Interrupt request 7" %define _DESC2522_ \ desc += "Interrupt request 6" %define _DESC2523_ \ desc += "Interrupt request 5" %define _DESC2524_ \ desc += "Interrupt request 4" %define _DESC2525_ \ desc += "Interrupt request 3" %define _DESC2526_ \ desc += "Interrupt request 2" %define _DESC2527_ \ desc += "Interrupt request 1" %define _DESC2528_ \ desc += "Interrupt request 0" %define _DESC2529_ \ desc += "Error Register Low. The ERR provides a bit map for the channels, signaling\n"\ desc += "the presence of an error for each channel. ERRL covers channels -00. The eDMA\n"\ desc += "engine signals the occurrence of an error condition by setting the appropriate\n"\ desc += "bit in this register. The outputs of this register are enabled by the contents\n"\ desc += "of the EEI, then logically summed across groups of 16 channels to form several\n"\ desc += "group error interrupt requests that are then routed to the interrupt\n"\ desc += "controller. During the execution of the interrupt-service routine associated\n"\ desc += "with any DMA errors, it is software's responsibility to clear the appropriate\n"\ desc += "bit, negating the error-interrupt request. Typically, a write to the CERR in\n"\ desc += "the interrupt-service routine is used for this purpose. The normal DMA channel\n"\ desc += "completion indicators (setting the transfer control descriptor DONE flag and\n"\ desc += "the possible assertion of an interrupt request) are not affected when an error\n"\ desc += "is detected.\n\n"\ desc += "The contents of this register can also be polled because a non-zero value\n"\ desc += "indicates the presence of a channel error regardless of the state of the EEI.\n"\ desc += "The state of any given channel's error indicators is affected by writes to this\n"\ desc += "register; it is also affected by writes to the CERR. On writes to the ERR, a\n"\ desc += "one in any bit position clears the corresponding channel's error status. A zero\n"\ desc += "in any bit position has no effect on the corresponding channel's current error\n"\ desc += "status. The CERR is provided so the error indicator for a single channel can\n"\ desc += "easily be cleared." %define _DESC2530_ \ desc += "Error in channel 15" %define _DESC2531_ \ desc += "Error in channel 14" %define _DESC2532_ \ desc += "Error in channel 13" %define _DESC2533_ \ desc += "Error in channel 12" %define _DESC2534_ \ desc += "Error in channel 11" %define _DESC2535_ \ desc += "Error in channel 10" %define _DESC2536_ \ desc += "Error in channel 9" %define _DESC2537_ \ desc += "Error in channel 8" %define _DESC2538_ \ desc += "Error in channel 7" %define _DESC2539_ \ desc += "Error in channel 6" %define _DESC2540_ \ desc += "Error in channel 5" %define _DESC2541_ \ desc += "Error in channel 4" %define _DESC2542_ \ desc += "Error in channel 3" %define _DESC2543_ \ desc += "Error in channel 2" %define _DESC2544_ \ desc += "Error in channel 1" %define _DESC2545_ \ desc += "Error in channel 0" %define _DESC2546_ \ desc += "Hardware Request Status Register Low. The HRS provides a bit map for the DMA\n"\ desc += "channels, signaling the presence of a qualified hardware service request for\n"\ desc += "each channel. HRSL covers channels -00. The Hardware Request Status bits\n"\ desc += "reflect the current state of the register and qualified (via the ERQ fields)\n"\ desc += "DMA request signals as seen by the DMA's arbitration logic. This view into the\n"\ desc += "hardware request signals may be used for debug purposes.\n\n"\ desc += "These bits reflect the state of the request as seen by the arbitration logic.\n"\ desc += "Therefore, this status is affected by the ERQ bits." %define _DESC2547_ \ desc += "Hardware request status channel 15" %define _DESC2548_ \ desc += "Hardware request status channel 14" %define _DESC2549_ \ desc += "Hardware request status channel 13" %define _DESC2550_ \ desc += "Hardware request status channel 12" %define _DESC2551_ \ desc += "Hardware request status channel 11" %define _DESC2552_ \ desc += "Hardware request status channel 10" %define _DESC2553_ \ desc += "Hardware request status channel 9" %define _DESC2554_ \ desc += "Hardware request status channel 8" %define _DESC2555_ \ desc += "Hardware request status channel 7" %define _DESC2556_ \ desc += "Hardware request status channel 6" %define _DESC2557_ \ desc += "Hardware request status channel 5" %define _DESC2558_ \ desc += "Hardware request status channel 4" %define _DESC2559_ \ desc += "Hardware request status channel 3" %define _DESC2560_ \ desc += "Hardware request status channel 2" %define _DESC2561_ \ desc += "Hardware request status channel 1" %define _DESC2562_ \ desc += "Hardware request status channel 0" %define _DESC2563_ \ desc += "Channel Priority Register. When the Fixed-Priority Channel Arbitration mode is\n"\ desc += "enabled (CR[ERCA] = 0), the contents of these registers define the unique\n"\ desc += "priorities associated with each channel within a group. The channel priorities\n"\ desc += "are evaluated by numeric value; for example, 0 is the lowest priority, 1 is the\n"\ desc += "next higher priority, then 2, 3, and so on. Software must program the channel\n"\ desc += "priorities with unique values. Otherwise, a configuration error is reported.\n"\ desc += "The range of the priority value is limited to the values of 0 through 15." %define _DESC2564_ \ desc += "Enable channel preemption\n\n"\ desc += "This bit resets to zero." %define _DESC2565_ \ desc += "Disable preempt ability\n\n"\ desc += "This bit resets to zero." %define _DESC2566_ \ desc += "Channel n arbitration priority\n\n"\ desc += "Channel priority when fixed-priority arbitration is enabled\n\n"\ desc += "Reset value for the group and channel priority fields, GRPPRI and CHPRI, is\n"\ desc += "equal to the corresponding channel number for each priority register, i.e.,\n"\ desc += "DCHPRI31[GRPPRI] = 0b01 and DCHPRI31[CHPRI] equals 0b1111." %define _DESC2567_ \ desc += "Channel Master ID Register. The DMA Master ID Replication registers allow the\n"\ desc += "DMA to use the same protection level and AHB system bus ID of the master\n"\ desc += "programming the DMA's TCD. When enabled, the DMA uses the master ID and\n"\ desc += "protection level stored in the DCHMID register instead of the DMA's default\n"\ desc += "values. When a master (a core, for example) programs a TCD, its master ID and\n"\ desc += "protection level are captured when the TCD Word 7 control attributes are\n"\ desc += "written. Although the scatter/gather operation can change the contents of TCD\n"\ desc += "Word 7, that operation does not affect the DCHMID n registers." %define _DESC2568_ \ desc += "Enable Master ID replication" %define _DESC2569_ \ desc += "Privileged Access Level\n\n"\ desc += "The protection level captured in this register reflects the level used when\n"\ desc += "writing the channel's control attributes; lower byte of TCD Word 7." %define _DESC2570_ \ desc += "Master ID\n\n"\ desc += "DMA's master ID when channel n is active and master ID replication is\n"\ desc += "enabled.\n\n"\ desc += "The master ID captured in this register reflects the ID used when writing the\n"\ desc += "channel's control attributes; lower byte of TCD Word 7." %define _DESC2571_ \ desc += "TCD Source Address. See TCD Source Address register figure and DMA_TCDn_SADDR\n"\ desc += "field descriptions table as follows." %define _DESC2572_ \ desc += "Source address\n\n"\ desc += "Memory address pointing to the source data." %define _DESC2573_ \ desc += "TCD Transfer Attributes. See TCD Transfer Attributes register figure and\n"\ desc += "DMA_TCDn_ATTR field descriptions table as follows." %define _DESC2574_ \ desc += "Source address modulo.\n\n"\ desc += "0: Source address modulo feature is disabled\n\n"\ desc += "Not 0: This value defines a specific address range specified to be the value\n"\ desc += "after SADDR + SOFF calculation is performed on the original register value.\n"\ desc += "Setting this field provides the ability to implement a circular data queue\n"\ desc += "easily. For data queues requiring power-of-2 size bytes, the queue should start\n"\ desc += "at a 0-modulo-size address and the SMOD field should be set to the appropriate\n"\ desc += "value for the queue, freezing the desired number of upper address bits. The\n"\ desc += "value programmed into this field specifies the number of lower address bits\n"\ desc += "allowed to change. For a circular queue application, the SOFF is typically set\n"\ desc += "to the transfer size to implement post-increment addressing with the SMOD\n"\ desc += "function constraining the addresses to a 0-modulo-size range." %define _DESC2575_ \ desc += "Source data transfer size\n\n"\ desc += "Using a reserved encoding causes a configuration error." %define _DESC2576_ \ desc += "Destination address modulo\n\n"\ desc += "See the SMOD definition" %define _DESC2577_ \ desc += "Destination data transfer size\n\n"\ desc += "See the SSIZE definition" %define _DESC2578_ \ desc += "TCD Signed Source Address Offset. See TCD Signed Source Address Offset register\n"\ desc += "figure and DMA_TCDn_SOFF field descriptions table as follows." %define _DESC2579_ \ desc += "Source address signed offset\n\n"\ desc += "Sign-extended offset applied to the current source address to form the\n"\ desc += "next-state value as each source read is completed." %define _DESC2580_ \ desc += "TCD Minor Byte Count Minor Loop Disabled. See TCD Minor Byte Count (Minor Loop\n"\ desc += "Disabled) register figure and DMA_TCDn_NBYTES_MLNO field descriptions table\n"\ desc += "below.\n\n"\ desc += "If minor loop mapping is disabled (CR[EMLM] = 0), TCD word 2 is defined as\n"\ desc += "follows." %define _DESC2581_ \ desc += "Minor byte transfer count\n\n"\ desc += "Number of bytes to be transferred in each service request of the channel. As a\n"\ desc += "channel activates, the appropriate TCD contents load into the eDMA engine, and\n"\ desc += "the appropriate reads and writes perform until the minor byte transfer count\n"\ desc += "has transferred. This is an indivisible operation and cannot be halted.\n"\ desc += "(Although, it may be stalled by using the bandwidth control field, or via\n"\ desc += "preemption.) After the minor count is exhausted, the SADDR and DADDR values are\n"\ desc += "written back into the TCD memory, the major iteration count is decremented and\n"\ desc += "restored to the TCD memory. If the major iteration count is completed,\n"\ desc += "additional processing is performed.\n\n"\ desc += "An NBYTES value of 0x0000_0000 is interpreted as a 4 GB transfer." %define _DESC2582_ \ desc += "TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled. TCD Word 2\n"\ desc += "is defined as follows if:\n\n"\ desc += "Minor loop mapping is enabled (CR[EMLM] = 1) and SMLOE = 0 and DMLOE = 0" %define _DESC2583_ \ desc += "Source minor loop offset enable\n\n"\ desc += "Selects whether the minor loop offset is applied to the source address upon\n"\ desc += "minor loop completion." %define _DESC2584_ \ desc += "Destination minor loop offset enable\n\n"\ desc += "Selects whether the minor loop offset is applied to the destination address\n"\ desc += "upon minor loop completion." %define _DESC2585_ \ desc += "Minor byte transfer count\n\n"\ desc += "Number of bytes to be transferred in each service request of the channel.\n\n"\ desc += "As a channel activates, the appropriate TCD contents load into the eDMA engine,\n"\ desc += "and the appropriate reads and writes perform until the minor byte transfer\n"\ desc += "count has transferred. This is an indivisible operation and cannot be halted.\n"\ desc += "(Although, it may be stalled by using the bandwidth control field, or via\n"\ desc += "preemption.) After the minor count is exhausted, the SADDR and DADDR values are\n"\ desc += "written back into the TCD memory, the major iteration count is decremented and\n"\ desc += "restored to the TCD memory. If the major iteration count is completed,\n"\ desc += "additional processing is performed." %define _DESC2586_ \ desc += "TCD Signed Minor Loop Offset Minor Loop and Offset Enabled. TCD Word 2 is\n"\ desc += "defined as follows if:\n\n"\ desc += "Minor loop mapping is enabled (CR[EMLM] = 1) and Minor loop offset enabled\n"\ desc += "(SMLOE or DMLOE = 1)" %define _DESC2587_ \ desc += "If SMLOE or DMLOE is set, this field represents a sign-extended offset applied\n"\ desc += "to the source or destination address to form the next-state value after the\n"\ desc += "minor loop completes." %define _DESC2588_ \ desc += "TCD Last Source Address Adjustment. " %define _DESC2589_ \ desc += "Last source address adjustment\n\n"\ desc += "Adjustment value added to the source address at the completion of the major\n"\ desc += "iteration count. This value can be applied to restore the source address to the\n"\ desc += "initial value, or adjust the address to reference the next data structure." %define _DESC2590_ \ desc += "TCD Destination Address. See TCD Destination Address register figure and\n"\ desc += "DMA_TCDn_DADDR field descriptions table as follows." %define _DESC2591_ \ desc += "Destination address\n\n"\ desc += "Memory address pointing to the destination data." %define _DESC2592_ \ desc += "TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled. See TCD\n"\ desc += "Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) register\n"\ desc += "figure and DMA_TCDn_CITER_ELINKYES field descriptions table as follows." %define _DESC2593_ \ desc += "Enable channel-to-channel linking on minor-loop complete\n\n"\ desc += "As the channel completes the minor loop, this flag enables linking to another\n"\ desc += "channel, defined by the LINKCH field. The link target channel initiates a\n"\ desc += "channel service request via an internal mechanism that sets the TCD n\n"\ desc += "_CSR[START] bit of the specified channel.\n\n"\ desc += "If channel linking is disabled, the CITER value is extended to 15 bits in place\n"\ desc += "of a link channel number. If the major loop is exhausted, this link mechanism\n"\ desc += "is suppressed in favor of the MAJORELINK channel linking.\n\n"\ desc += "This bit must be equal to the BITER[ELINK] bit. Otherwise, a configuration\n"\ desc += "error is reported." %define _DESC2594_ \ desc += "Link channel number\n\n"\ desc += "If channel-to-channel linking is enabled (ELINK = 1), then after the minor loop\n"\ desc += "is exhausted, the eDMA engine initiates a channel service request to the\n"\ desc += "channel defined by these six bits by setting that channel's TCD n _CSR[START]\n"\ desc += "bit." %define _DESC2595_ \ desc += "Current major iteration count\n\n"\ desc += "This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current major\n"\ desc += "loop count for the channel. It is decremented each time the minor loop is\n"\ desc += "completed and updated in the transfer control descriptor memory. After the\n"\ desc += "major iteration count is exhausted, the channel performs a number of operations\n"\ desc += "(e.g., final source and destination address calculations), optionally\n"\ desc += "generating an interrupt to signal channel completion before reloading the CITER\n"\ desc += "field from the beginning iteration count (BITER) field.\n\n"\ desc += "When the CITER field is initially loaded by software, it must be set to the\n"\ desc += "same value as that contained in the BITER field. If the channel is configured\n"\ desc += "to execute a single service request, the initial values of BITER and CITER\n"\ desc += "should be 0x0001." %define _DESC2596_ \ desc += "TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled. See TCD\n"\ desc += "Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) register\n"\ desc += "figure and DMA_TCDn_CITER_ELINKNO field descriptions table as follows." %define _DESC2597_ \ desc += "Enable channel-to-channel linking on minor-loop complete\n\n"\ desc += "As the channel completes the minor loop, this flag enables linking to another\n"\ desc += "channel, defined by the LINKCH field. The link target channel initiates a\n"\ desc += "channel service request via an internal mechanism that sets the TCD n\n"\ desc += "_CSR[START] bit of the specified channel.If channel linking is disabled, the\n"\ desc += "CITER value is extended to 15 bits in place of a link channel number. If the\n"\ desc += "major loop is exhausted, this link mechanism is suppressed in favor of the\n"\ desc += "MAJORELINK channel linking.\n\n"\ desc += "This bit must be equal to the BITER[ELINK] bit. Otherwise, a configuration\n"\ desc += "error is reported." %define _DESC2598_ \ desc += "Current major iteration count\n\n"\ desc += "This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current major\n"\ desc += "loop count for the channel. It is decremented each time the minor loop is\n"\ desc += "completed and updated in the transfer control descriptor memory. After the\n"\ desc += "major iteration count is exhausted, the channel performs a number of operations\n"\ desc += "(for example, final source and destination address calculations), optionally\n"\ desc += "generating an interrupt to signal channel completion before reloading the CITER\n"\ desc += "field from the beginning iteration count (BITER) field.\n\n"\ desc += "When the CITER field is initially loaded by software, it must be set to the\n"\ desc += "same value as that contained in the BITER field. If the channel is configured\n"\ desc += "to execute a single service request, the initial values of BITER and CITER\n"\ desc += "should be 0x0001." %define _DESC2599_ \ desc += "TCD Signed Destination Address Offset. See TCD Signed Destination Address\n"\ desc += "Offset register figure and DMA_TCDn_DOFF field descriptions table as follows." %define _DESC2600_ \ desc += "Destination address signed offset\n\n"\ desc += "Sign-extended offset applied to the current destination address to form the\n"\ desc += "next-state value as each destination write is completed." %define _DESC2601_ \ desc += "TCD Last Destination Address Adjustment/Scatter Gather Address. " %define _DESC2602_ \ desc += "Destination last address adjustment or the memory address for the next transfer\n"\ desc += "control descriptor to be loaded into this channel (scatter/gather).\n\n"\ desc += "If (TCD n _CSR[ESG] = 0) then\n\n"\ desc += "Adjustment value added to the destination address at the completion of the\n"\ desc += "major iteration count. This value can apply to restore the destination address\n"\ desc += "to the initial value or adjust the address to reference the next data\n"\ desc += "structure. else\n\n"\ desc += "This address points to the beginning of a 0-modulo-32-byte region containing\n"\ desc += "the next transfer control descriptor to be loaded into this channel. This\n"\ desc += "channel reload is performed as the major iteration count completes. The\n"\ desc += "scatter/gather address must be 0-modulo-32-byte, else a configuration error is\n"\ desc += "reported." %define _DESC2603_ \ desc += "TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled. " %define _DESC2604_ \ desc += "Enables channel-to-channel linking on minor loop complete\n\n"\ desc += "As the channel completes the minor loop, this flag enables the linking to\n"\ desc += "another channel, defined by BITER[LINKCH]. The link target channel initiates a\n"\ desc += "channel service request via an internal mechanism that sets the TCD n\n"\ desc += "_CSR[START] bit of the specified channel. If channel linking disables, the\n"\ desc += "BITER value extends to 15 bits in place of a link channel number. If the major\n"\ desc += "loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK\n"\ desc += "channel linking.\n\n"\ desc += "When the software loads the TCD, this field must be set equal to the\n"\ desc += "corresponding CITER field. Otherwise, a configuration error is reported. As the\n"\ desc += "major iteration count is exhausted, the contents of this field is reloaded into\n"\ desc += "the CITER field." %define _DESC2605_ \ desc += "Link channel number\n\n"\ desc += "If channel-to-channel linking is enabled (ELINK = 1), then after the minor loop\n"\ desc += "is exhausted, the eDMA engine initiates a channel service request at the\n"\ desc += "channel defined by these six bits by setting that channel's TCD n _CSR[START]\n"\ desc += "bit.\n\n"\ desc += "When the software loads the TCD, this field must be set equal to the\n"\ desc += "corresponding CITER field. Otherwise, a configuration error is reported. As the\n"\ desc += "major iteration count is exhausted, the contents of this field is reloaded into\n"\ desc += "the CITER field." %define _DESC2606_ \ desc += "Starting major iteration count\n\n"\ desc += "As the transfer control descriptor is first loaded by software, this 9-bit\n"\ desc += "(ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER\n"\ desc += "field. As the major iteration count is exhausted, the contents of this field\n"\ desc += "are reloaded into the CITER field.\n\n"\ desc += "When the software loads the TCD, this field must be set equal to the\n"\ desc += "corresponding CITER field. Otherwise, a configuration error is reported. As the\n"\ desc += "major iteration count is exhausted, the contents of this field is reloaded into\n"\ desc += "the CITER field. If the channel is configured to execute a single service\n"\ desc += "request, the initial values of BITER and CITER should be 0x0001." %define _DESC2607_ \ desc += "TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled. " %define _DESC2608_ \ desc += "TCD Control and Status. See TCD Control and Status register figure and\n"\ desc += "DMA_TCDn_CSR field descriptions table as follows." %define _DESC2609_ \ desc += "Bandwidth control\n\n"\ desc += "Throttles the amount of bus bandwidth consumed by the eDMA. In general, as the\n"\ desc += "eDMA processes the minor loop, it continuously generates read/write sequences\n"\ desc += "until the minor count is exhausted. This field forces the eDMA to stall after\n"\ desc += "the completion of each read/write access to control the bus request bandwidth\n"\ desc += "seen by the crossbar switch (XBS).\n\n"\ desc += "If the source and destination sizes are equal, this field is ignored between\n"\ desc += "the first and second transfers and after the last write of each minor loop.\n"\ desc += "This behavior is a side effect of reducing start-up latency." %define _DESC2610_ \ desc += "Link channel number\n\n"\ desc += "If (MAJORELINK = 0) then\n\n"\ desc += "No channel-to-channel linking (or chaining) is performed after the major loop\n"\ desc += "counter is exhausted. else\n\n"\ desc += "After the major loop counter is exhausted, the eDMA engine initiates a channel\n"\ desc += "service request at the channel defined by these six bits by setting that\n"\ desc += "channel's TCD n _CSR[START] bit." %define _DESC2611_ \ desc += "Channel done\n\n"\ desc += "This flag indicates the eDMA has completed the major loop. The eDMA engine sets\n"\ desc += "it as the CITER count reaches zero; The software clears it, or the hardware\n"\ desc += "when the channel is activated.\n\n"\ desc += "This bit must be cleared to write the MAJORELINK or ESG bits. This bit resets\n"\ desc += "to zero." %define _DESC2612_ \ desc += "Channel active\n\n"\ desc += "This flag signals the channel is currently in execution. It is set when channel\n"\ desc += "service begins, and the eDMA clears it as the minor loop completes or if any\n"\ desc += "error condition is detected." %define _DESC2613_ \ desc += "Enable channel-to-channel linking on major loop complete\n\n"\ desc += "As the channel completes the major loop, this flag enables the linking to\n"\ desc += "another channel, defined by MAJORLINKCH. The link target channel initiates a\n"\ desc += "channel service request via an internal mechanism that sets the TCD n\n"\ desc += "_CSR[START] bit of the specified channel.\n\n"\ desc += "To support the dynamic linking coherency model, this field is forced to zero\n"\ desc += "when written to while the TCD n _CSR[DONE] bit is set." %define _DESC2614_ \ desc += "Enable scatter/gather processing\n\n"\ desc += "As the channel completes the major loop, this flag enables scatter/gather\n"\ desc += "processing in the current channel. If enabled, the eDMA engine uses DLASTSGA as\n"\ desc += "a memory pointer to a 0-modulo-32 address containing a 32-byte data structure\n"\ desc += "loaded as the transfer control descriptor into the local memory.\n\n"\ desc += "To support the dynamic scatter/gather coherency model, this field is forced to\n"\ desc += "zero when written to while the TCD n _CSR[DONE] bit is set." %define _DESC2615_ \ desc += "Disable request {H,L}" %define _DESC2616_ \ desc += "Enable an interrupt when major counter is half complete.\n\n"\ desc += "If this flag is set, the channel generates an interrupt request by setting the\n"\ desc += "appropriate bit in the INT when the current major iteration count reaches the\n"\ desc += "halfway point. Specifically, the comparison performed by the eDMA engine is\n"\ desc += "(CITER == (BITER >> 1)). This halfway point interrupt request is provided to\n"\ desc += "support double-buffered (aka ping-pong) schemes or other types of data movement\n"\ desc += "where the processor needs an early indication of the transfer's progress.\n\n"\ desc += "If BITER is set, do not use INTHALF. Use INTMAJOR instead." %define _DESC2617_ \ desc += "Enable an interrupt when major iteration count completes\n\n"\ desc += "If this flag is set, the channel generates an interrupt request by setting the\n"\ desc += "appropriate bit in the INT when the current major iteration count reaches\n"\ desc += "zero." %define _DESC2618_ \ desc += "Channel start\n\n"\ desc += "If this flag is set, the channel is requesting service. The eDMA hardware\n"\ desc += "automatically clears this flag after the channel begins execution. This bit\n"\ desc += "resets to zero." enum { } bitfield { bitfield_CMU_PLL_CSR{ "Reserved0"{ type="binary"; loc="0..7"; } "SFM"{ type="binary"; loc="8"; ${_DESC1_} } "Reserved1"{ type="binary"; loc="9..21"; } "CKSEL1"{ type="binary"; loc="22..23"; ${_DESC2_} } "Reserved2"{ type="binary"; loc="24..28"; } "RCDIV"{ type="binary"; loc="29..30"; ${_DESC3_} } "CME"{ type="binary"; loc="31"; } } bitfield_CMU_PLL_FDR{ "Reserved0"{ type="binary"; loc="0..11"; } "FD"{ type="binary"; loc="12..31"; ${_DESC5_} } } bitfield_CMU_PLL_HFREFR{ "Reserved0"{ type="binary"; loc="0..19"; } "HFREF"{ type="binary"; loc="20..31"; ${_DESC7_} } } bitfield_CMU_PLL_LFREFR{ "Reserved0"{ type="binary"; loc="0..19"; ${_DESC9_} } "LFREF"{ type="binary"; loc="20..31"; ${_DESC10_} } } bitfield_CMU_PLL_ISR{ "Reserved0"{ type="binary"; loc="0..27"; } "Reserved1"{ type="binary"; loc="28"; } "FHHI"{ type="binary"; loc="29"; ${_DESC12_} } "FLLI"{ type="binary"; loc="30"; ${_DESC13_} } "OLRI"{ type="binary"; loc="31"; ${_DESC14_} } } bitfield_CMU_PLL_MDR{ "Reserved0"{ type="binary"; loc="0..11"; } "MD"{ type="binary"; loc="12..31"; ${_DESC16_} } } bitfield_DECFILTER_MCR{ "MDIS"{ type="binary"; loc="0"; ${_DESC18_} } "FREN"{ type="binary"; loc="1"; ${_DESC19_} } "Reserved0"{ type="binary"; loc="2"; } "FRZ"{ type="binary"; loc="3"; ${_DESC20_} } "SRES"{ type="binary"; loc="4"; ${_DESC21_} } "Reserved1"{ type="binary"; loc="5..6"; } "IDEN"{ type="binary"; loc="7"; ${_DESC22_} } "ODEN"{ type="binary"; loc="8"; ${_DESC23_} } "ERREN"{ type="binary"; loc="9"; ${_DESC24_} } "Reserved2"{ type="binary"; loc="10"; } "FTYPE"{ type="binary"; loc="11..12"; ${_DESC25_} } "Reserved3"{ type="binary"; loc="13"; } "SCAL"{ type="binary"; loc="14..15"; ${_DESC26_} } "IDIS"{ type="binary"; loc="16"; ${_DESC27_} } "SAT"{ type="binary"; loc="17"; ${_DESC28_} } "ISEL"{ type="binary"; loc="18"; ${_DESC29_} } "Reserved4"{ type="binary"; loc="19"; } "DEC_RATE"{ type="binary"; loc="20..23"; ${_DESC30_} } "SDIE"{ type="binary"; loc="24"; ${_DESC31_} } "DSEL"{ type="binary"; loc="25"; ${_DESC32_} } "IBIE"{ type="binary"; loc="26"; ${_DESC33_} } "OBIE"{ type="binary"; loc="27"; ${_DESC34_} } "Reserved5"{ type="binary"; loc="28..31"; } } bitfield_DECFILTER_MSR{ "BSY"{ type="binary"; loc="0"; ${_DESC36_} } "Reserved0"{ type="binary"; loc="1"; } "DEC_COUNTER"{ type="binary"; loc="2..5"; ${_DESC37_} } "IDFC"{ type="binary"; loc="6"; ${_DESC38_} } "ODFC"{ type="binary"; loc="7"; ${_DESC39_} } "Reserved1"{ type="binary"; loc="8"; } "IBIC"{ type="binary"; loc="9"; ${_DESC40_} } "OBIC"{ type="binary"; loc="10"; ${_DESC41_} } "Reserved2"{ type="binary"; loc="11"; } "Reserved3"{ type="binary"; loc="12"; } "OVFC"{ type="binary"; loc="13"; ${_DESC42_} } "OVRC"{ type="binary"; loc="14"; ${_DESC43_} } "IVRC"{ type="binary"; loc="15"; ${_DESC44_} } "Reserved4"{ type="binary"; loc="16..21"; } "IDF"{ type="binary"; loc="22"; ${_DESC45_} } "ODF"{ type="binary"; loc="23"; ${_DESC46_} } "Reserved5"{ type="binary"; loc="24"; } "IBIF"{ type="binary"; loc="25"; ${_DESC47_} } "OBIF"{ type="binary"; loc="26"; ${_DESC48_} } "Reserved6"{ type="binary"; loc="27"; } "Reserved7"{ type="binary"; loc="28"; } "OVF"{ type="binary"; loc="29"; ${_DESC49_} } "OVR"{ type="binary"; loc="30"; ${_DESC50_} } "IVR"{ type="binary"; loc="31"; ${_DESC51_} } } bitfield_DECFILTER_MXCR{ "SDMAE"{ type="binary"; loc="0"; ${_DESC53_} } "SSIG"{ type="binary"; loc="1"; ${_DESC54_} } "SSAT"{ type="binary"; loc="2"; ${_DESC55_} } "SCSAT"{ type="binary"; loc="3"; ${_DESC56_} } "Reserved0"{ type="binary"; loc="4..13"; } "SRQ"{ type="binary"; loc="14"; ${_DESC57_} } "SZRO"{ type="binary"; loc="15"; ${_DESC58_} } "SISEL"{ type="binary"; loc="16"; ${_DESC59_} } "Reserved1"{ type="binary"; loc="17"; } "SZROSEL"{ type="binary"; loc="18..19"; ${_DESC60_} } "Reserved2"{ type="binary"; loc="20..21"; } "SHLTSEL"{ type="binary"; loc="22..23"; ${_DESC61_} } "Reserved3"{ type="binary"; loc="24"; } "SRQSEL"{ type="binary"; loc="25..27"; ${_DESC62_} } "Reserved4"{ type="binary"; loc="28..29"; } "SENSEL"{ type="binary"; loc="30..31"; ${_DESC63_} } } bitfield_DECFILTER_MXSR{ "Reserved0"{ type="binary"; loc="0..6"; } "SDFC"{ type="binary"; loc="7"; ${_DESC65_} } "Reserved1"{ type="binary"; loc="8..9"; } "SSEC"{ type="binary"; loc="10"; ${_DESC66_} } "SCEC"{ type="binary"; loc="11"; ${_DESC67_} } "Reserved2"{ type="binary"; loc="12"; } "SSOVFC"{ type="binary"; loc="13"; ${_DESC68_} } "SCOVFC"{ type="binary"; loc="14"; ${_DESC69_} } "SVRC"{ type="binary"; loc="15"; ${_DESC70_} } "Reserved3"{ type="binary"; loc="16..22"; } "SDF"{ type="binary"; loc="23"; ${_DESC71_} } "Reserved4"{ type="binary"; loc="24..25"; } "SSE"{ type="binary"; loc="26"; ${_DESC72_} } "SCE"{ type="binary"; loc="27"; ${_DESC73_} } "Reserved5"{ type="binary"; loc="28"; } "SSOVF"{ type="binary"; loc="29"; ${_DESC74_} } "SCOVF"{ type="binary"; loc="30"; ${_DESC75_} } "SVR"{ type="binary"; loc="31"; ${_DESC76_} } } bitfield_DECFILTER_IB{ "Reserved0"{ type="binary"; loc="0..2"; } "Reserved1"{ type="binary"; loc="3"; } "INTAG"{ type="binary"; loc="4..7"; ${_DESC78_} } "Reserved2"{ type="binary"; loc="8..13"; } "PREFILL"{ type="binary"; loc="14"; ${_DESC79_} } "FLUSH"{ type="binary"; loc="15"; ${_DESC80_} } "INPBUF"{ type="binary"; loc="16..31"; ${_DESC81_} } } bitfield_DECFILTER_OB{ "Reserved0"{ type="binary"; loc="0..10"; } "Reserved1"{ type="binary"; loc="11"; } "OUTTAG"{ type="binary"; loc="12..15"; ${_DESC83_} } "OUTBUF"{ type="binary"; loc="16..31"; ${_DESC84_} } } bitfield_DECFILTER_COEF0{ "COEFnSIGNR"{ type="binary"; loc="0..7"; ${_DESC86_} } "COEFn"{ type="binary"; loc="8..31"; ${_DESC87_} } } bitfield_DECFILTER_TAP0{ "TAPnSIGNR"{ type="binary"; loc="0..7"; ${_DESC89_} } "TAPn"{ type="binary"; loc="8..31"; ${_DESC90_} } } bitfield_DECFILTER_FINTVAL{ "SUM_VALUE"{ type="binary"; loc="0..31"; ${_DESC92_} } } bitfield_DECFILTER_FINTCNT{ "COUNT"{ type="binary"; loc="0..31"; ${_DESC94_} } } bitfield_DECFILTER_CINTVAL{ "SUM_VALUE"{ type="binary"; loc="0..31"; ${_DESC96_} } } bitfield_DECFILTER_CINTCNT{ "COUNT"{ type="binary"; loc="0..31"; ${_DESC98_} } } bitfield_DMAMUX_0_CHCFG0{ "SOURCE"{ type="binary"; loc="2..7"; ${_DESC100_} } "TRIG"{ type="binary"; loc="1"; ${_DESC101_} } "ENBL"{ type="binary"; loc="0"; ${_DESC102_} } } bitfield_DSPI_0_MCR{ "MSTR"{ type="binary"; loc="0"; ${_DESC104_} } "CONT_SCKE"{ type="binary"; loc="1"; ${_DESC105_} } "DCONF"{ type="binary"; loc="2..3"; ${_DESC106_} } "FRZ"{ type="binary"; loc="4"; ${_DESC107_} } "MTFE"{ type="binary"; loc="5"; ${_DESC108_} } "PCSSE"{ type="binary"; loc="6"; ${_DESC109_} } "ROOE"{ type="binary"; loc="7"; ${_DESC110_} } "PCSIS"{ type="binary"; loc="8..15"; ${_DESC111_} } "DOZE"{ type="binary"; loc="16"; ${_DESC112_} } "MDIS"{ type="binary"; loc="17"; ${_DESC113_} } "DIS_TXF"{ type="binary"; loc="18"; ${_DESC114_} } "DIS_RXF"{ type="binary"; loc="19"; ${_DESC115_} } "CLR_TXF"{ type="binary"; loc="20"; ${_DESC116_} } "CLR_RXF"{ type="binary"; loc="21"; ${_DESC117_} } "SMPL_PT"{ type="binary"; loc="22..23"; ${_DESC118_} } "Reserved0"{ type="binary"; loc="24..27"; } "XSPI"{ type="binary"; loc="28"; ${_DESC119_} } "FCPCS"{ type="binary"; loc="29"; ${_DESC120_} } "PES"{ type="binary"; loc="30"; ${_DESC121_} } "HALT"{ type="binary"; loc="31"; ${_DESC122_} } } bitfield_DSPI_0_TCR{ "SPI_TCNT"{ type="binary"; loc="0..15"; ${_DESC124_} } "Reserved0"{ type="binary"; loc="16..31"; } } bitfield_DSPI_0_CTAR0{ "DBR"{ type="binary"; loc="0"; ${_DESC126_} } "FMSZ"{ type="binary"; loc="1..4"; ${_DESC127_} } "CPOL"{ type="binary"; loc="5"; ${_DESC128_} } "CPHA"{ type="binary"; loc="6"; ${_DESC129_} } "LSBFE"{ type="binary"; loc="7"; ${_DESC130_} } "PCSSCK"{ type="binary"; loc="8..9"; ${_DESC131_} } "PASC"{ type="binary"; loc="10..11"; ${_DESC132_} } "PDT"{ type="binary"; loc="12..13"; ${_DESC133_} } "PBR"{ type="binary"; loc="14..15"; ${_DESC134_} } "CSSCK"{ type="binary"; loc="16..19"; ${_DESC135_} } "ASC"{ type="binary"; loc="20..23"; ${_DESC136_} } "DT"{ type="binary"; loc="24..27"; ${_DESC137_} } "BR"{ type="binary"; loc="28..31"; ${_DESC138_} } } bitfield_DSPI_0_CTAR_SLAVE0{ "FMSZ"{ type="binary"; loc="0..4"; ${_DESC140_} } "CPOL"{ type="binary"; loc="5"; ${_DESC141_} } "CPHA"{ type="binary"; loc="6"; ${_DESC142_} } "PE"{ type="binary"; loc="7"; ${_DESC143_} } "PP"{ type="binary"; loc="8"; ${_DESC144_} } "FMSZ5"{ type="binary"; loc="9"; ${_DESC145_} } "Reserved0"{ type="binary"; loc="10..31"; } } bitfield_DSPI_0_SR{ "TCF"{ type="binary"; loc="0"; ${_DESC147_} } "TXRXS"{ type="binary"; loc="1"; ${_DESC148_} } "SPITCF"{ type="binary"; loc="2"; ${_DESC149_} } "EOQF"{ type="binary"; loc="3"; ${_DESC150_} } "TFUF"{ type="binary"; loc="4"; ${_DESC151_} } "DSITCF"{ type="binary"; loc="5"; ${_DESC152_} } "TFFF"{ type="binary"; loc="6"; ${_DESC153_} } "BSYF"{ type="binary"; loc="7"; ${_DESC154_} } "CMDTCF"{ type="binary"; loc="8"; ${_DESC155_} } "DPEF"{ type="binary"; loc="9"; ${_DESC156_} } "SPEF"{ type="binary"; loc="10"; ${_DESC157_} } "DDIF"{ type="binary"; loc="11"; ${_DESC158_} } "RFOF"{ type="binary"; loc="12"; ${_DESC159_} } "TFIWF"{ type="binary"; loc="13"; ${_DESC160_} } "RFDF"{ type="binary"; loc="14"; ${_DESC161_} } "CMDFFF"{ type="binary"; loc="15"; ${_DESC162_} } "TXCTR"{ type="binary"; loc="16..19"; ${_DESC163_} } "TXNXTPTR"{ type="binary"; loc="20..23"; ${_DESC164_} } "RXCTR"{ type="binary"; loc="24..27"; ${_DESC165_} } "POPNXTPTR"{ type="binary"; loc="28..31"; ${_DESC166_} } } bitfield_DSPI_0_RSER{ "TCF_RE"{ type="binary"; loc="0"; ${_DESC168_} } "CMDFFF_RE"{ type="binary"; loc="1"; ${_DESC169_} } "SPITCF_RE"{ type="binary"; loc="2"; ${_DESC170_} } "EOQF_RE"{ type="binary"; loc="3"; ${_DESC171_} } "TFUF_RE"{ type="binary"; loc="4"; ${_DESC172_} } "DSITCF_RE"{ type="binary"; loc="5"; ${_DESC173_} } "TFFF_RE"{ type="binary"; loc="6"; ${_DESC174_} } "TFFF_DIRS"{ type="binary"; loc="7"; ${_DESC175_} } "CMDTCF_RE"{ type="binary"; loc="8"; ${_DESC176_} } "DPEF_RE"{ type="binary"; loc="9"; ${_DESC177_} } "SPEF_RE"{ type="binary"; loc="10"; ${_DESC178_} } "DDIF_RE"{ type="binary"; loc="11"; ${_DESC179_} } "RFOF_RE"{ type="binary"; loc="12"; ${_DESC180_} } "TFIWF_RE"{ type="binary"; loc="13"; ${_DESC181_} } "RFDF_RE"{ type="binary"; loc="14"; ${_DESC182_} } "RFDF_DIRS"{ type="binary"; loc="15"; ${_DESC183_} } "CMDFFF_DIRS"{ type="binary"; loc="16"; ${_DESC184_} } "DDIF_DIRS"{ type="binary"; loc="17"; ${_DESC185_} } "Reserved0"{ type="binary"; loc="18..31"; } } bitfield_DSPI_0_PUSHR{ "CONT"{ type="binary"; loc="0"; ${_DESC187_} } "CTAS"{ type="binary"; loc="1..3"; ${_DESC188_} } "EOQ"{ type="binary"; loc="4"; ${_DESC189_} } "CTCNT"{ type="binary"; loc="5"; ${_DESC190_} } "PE_MASC"{ type="binary"; loc="6"; ${_DESC191_} } "PP_MCSC"{ type="binary"; loc="7"; ${_DESC192_} } "PCS"{ type="binary"; loc="8..15"; ${_DESC193_} } "TXDATA"{ type="binary"; loc="16..31"; ${_DESC194_} } } bitfield_DSPI_0_PUSHR_SLAVE{ "Reserved0"{ type="binary"; loc="0..15"; } "TXDATA"{ type="binary"; loc="16..31"; ${_DESC196_} } } bitfield_DSPI_0_POPR{ "RXDATA"{ type="binary"; loc="0..31"; ${_DESC198_} } } bitfield_DSPI_0_TXFR0{ "TXCMD_TXDATA"{ type="binary"; loc="0..15"; ${_DESC200_} } "TXDATA"{ type="binary"; loc="16..31"; ${_DESC201_} } } bitfield_DSPI_0_RXFR0{ "RXDATA"{ type="binary"; loc="0..31"; ${_DESC203_} } } bitfield_DSPI_0_DSICR0{ "Reserved0"{ type="binary"; loc="0"; } "FMSZ4"{ type="binary"; loc="1"; ${_DESC205_} } "Reserved1"{ type="binary"; loc="2..7"; } "FMSZ5"{ type="binary"; loc="8"; ${_DESC206_} } "Reserved2"{ type="binary"; loc="9"; } "ITSB"{ type="binary"; loc="10"; ${_DESC207_} } "TSBC"{ type="binary"; loc="11"; ${_DESC208_} } "TXSS"{ type="binary"; loc="12"; ${_DESC209_} } "TPOL"{ type="binary"; loc="13"; ${_DESC210_} } "TRRE"{ type="binary"; loc="14"; ${_DESC211_} } "CID"{ type="binary"; loc="15"; ${_DESC212_} } "DCONT"{ type="binary"; loc="16"; ${_DESC213_} } "DSICTAS"{ type="binary"; loc="17..19"; ${_DESC214_} } "DMS"{ type="binary"; loc="20"; ${_DESC215_} } "PES"{ type="binary"; loc="21"; ${_DESC216_} } "PE"{ type="binary"; loc="22"; ${_DESC217_} } "PP"{ type="binary"; loc="23"; ${_DESC218_} } "DPCSx"{ type="binary"; loc="24..31"; ${_DESC219_} } } bitfield_DSPI_0_SDR0{ "SER_DATA"{ type="binary"; loc="0..31"; ${_DESC221_} } } bitfield_DSPI_0_ASDR0{ "ASER_DATA"{ type="binary"; loc="0..31"; ${_DESC223_} } } bitfield_DSPI_0_COMPR0{ "COMP_DATA"{ type="binary"; loc="0..31"; ${_DESC225_} } } bitfield_DSPI_0_DDR0{ "DESER_DATA"{ type="binary"; loc="0..31"; ${_DESC227_} } } bitfield_DSPI_0_DSICR1{ "Reserved0"{ type="binary"; loc="0..1"; } "TSBCNT"{ type="binary"; loc="2..7"; ${_DESC229_} } "Reserved1"{ type="binary"; loc="8..12"; } "DSI64E"{ type="binary"; loc="13"; ${_DESC230_} } "DSE1"{ type="binary"; loc="14"; ${_DESC231_} } "DSE0"{ type="binary"; loc="15"; ${_DESC232_} } "TRGPRD"{ type="binary"; loc="16..23"; ${_DESC233_} } "DPCS1_x"{ type="binary"; loc="24..31"; ${_DESC234_} } } bitfield_DSPI_0_SSR0{ "SS"{ type="binary"; loc="0..31"; ${_DESC236_} } } bitfield_DSPI_0_PISR0{ "IPS7"{ type="binary"; loc="0..3"; ${_DESC238_} } "IPS6"{ type="binary"; loc="4..7"; ${_DESC239_} } "IPS5"{ type="binary"; loc="8..11"; ${_DESC240_} } "IPS4"{ type="binary"; loc="12..15"; ${_DESC241_} } "IPS3"{ type="binary"; loc="16..19"; ${_DESC242_} } "IPS2"{ type="binary"; loc="20..23"; ${_DESC243_} } "IPS1"{ type="binary"; loc="24..27"; ${_DESC244_} } "IPS0"{ type="binary"; loc="28..31"; ${_DESC245_} } } bitfield_DSPI_0_PISR1{ "IPS15"{ type="binary"; loc="0..3"; ${_DESC247_} } "IPS14"{ type="binary"; loc="4..7"; ${_DESC248_} } "IPS13"{ type="binary"; loc="8..11"; ${_DESC249_} } "IPS12"{ type="binary"; loc="12..15"; ${_DESC250_} } "IPS11"{ type="binary"; loc="16..19"; ${_DESC251_} } "IPS10"{ type="binary"; loc="20..23"; ${_DESC252_} } "IPS9"{ type="binary"; loc="24..27"; ${_DESC253_} } "IPS8"{ type="binary"; loc="28..31"; ${_DESC254_} } } bitfield_DSPI_0_PISR2{ "IPS23"{ type="binary"; loc="0..3"; ${_DESC256_} } "IPS22"{ type="binary"; loc="4..7"; ${_DESC257_} } "IPS21"{ type="binary"; loc="8..11"; ${_DESC258_} } "IPS20"{ type="binary"; loc="12..15"; ${_DESC259_} } "IPS19"{ type="binary"; loc="16..19"; ${_DESC260_} } "IPS18"{ type="binary"; loc="20..23"; ${_DESC261_} } "IPS17"{ type="binary"; loc="24..27"; ${_DESC262_} } "IPS16"{ type="binary"; loc="28..31"; ${_DESC263_} } } bitfield_DSPI_0_PISR3{ "IPS31"{ type="binary"; loc="0..3"; ${_DESC265_} } "IPS30"{ type="binary"; loc="4..7"; ${_DESC266_} } "IPS29"{ type="binary"; loc="8..11"; ${_DESC267_} } "IPS28"{ type="binary"; loc="12..15"; ${_DESC268_} } "IPS27"{ type="binary"; loc="16..19"; ${_DESC269_} } "IPS26"{ type="binary"; loc="20..23"; ${_DESC270_} } "IPS25"{ type="binary"; loc="24..27"; ${_DESC271_} } "IPS24"{ type="binary"; loc="28..31"; ${_DESC272_} } } bitfield_DSPI_0_DIMR0{ "MASK"{ type="binary"; loc="0..31"; ${_DESC274_} } } bitfield_DSPI_0_DPIR0{ "DP"{ type="binary"; loc="0..31"; ${_DESC276_} } } bitfield_DSPI_0_SDR1{ "SER_DATA"{ type="binary"; loc="0..31"; ${_DESC278_} } } bitfield_DSPI_0_ASDR1{ "ASER_DATA"{ type="binary"; loc="0..31"; ${_DESC280_} } } bitfield_DSPI_0_COMPR1{ "COMP_DATA"{ type="binary"; loc="0..31"; ${_DESC282_} } } bitfield_DSPI_0_DDR1{ "DESER_DATA"{ type="binary"; loc="0..31"; ${_DESC284_} } } bitfield_DSPI_0_SSR1{ "SS"{ type="binary"; loc="0..31"; ${_DESC286_} } } bitfield_DSPI_0_PISR4{ "IPS39"{ type="binary"; loc="0..3"; ${_DESC288_} } "IPS38"{ type="binary"; loc="4..7"; ${_DESC289_} } "IPS37"{ type="binary"; loc="8..11"; ${_DESC290_} } "IPS36"{ type="binary"; loc="12..15"; ${_DESC291_} } "IPS35"{ type="binary"; loc="16..19"; ${_DESC292_} } "IPS34"{ type="binary"; loc="20..23"; ${_DESC293_} } "IPS33"{ type="binary"; loc="24..27"; ${_DESC294_} } "IPS32"{ type="binary"; loc="28..31"; ${_DESC295_} } } bitfield_DSPI_0_PISR5{ "IPS47"{ type="binary"; loc="0..3"; ${_DESC297_} } "IPS46"{ type="binary"; loc="4..7"; ${_DESC298_} } "IPS45"{ type="binary"; loc="8..11"; ${_DESC299_} } "IPS44"{ type="binary"; loc="12..15"; ${_DESC300_} } "IPS43"{ type="binary"; loc="16..19"; ${_DESC301_} } "IPS42"{ type="binary"; loc="20..23"; ${_DESC302_} } "IPS41"{ type="binary"; loc="24..27"; ${_DESC303_} } "IPS40"{ type="binary"; loc="28..31"; ${_DESC304_} } } bitfield_DSPI_0_PISR6{ "IPS55"{ type="binary"; loc="0..3"; ${_DESC306_} } "IPS54"{ type="binary"; loc="4..7"; ${_DESC307_} } "IPS53"{ type="binary"; loc="8..11"; ${_DESC308_} } "IPS52"{ type="binary"; loc="12..15"; ${_DESC309_} } "IPS51"{ type="binary"; loc="16..19"; ${_DESC310_} } "IPS50"{ type="binary"; loc="20..23"; ${_DESC311_} } "IPS49"{ type="binary"; loc="24..27"; ${_DESC312_} } "IPS48"{ type="binary"; loc="28..31"; ${_DESC313_} } } bitfield_DSPI_0_PISR7{ "IPS63"{ type="binary"; loc="0..3"; ${_DESC315_} } "IPS62"{ type="binary"; loc="4..7"; ${_DESC316_} } "IPS61"{ type="binary"; loc="8..11"; ${_DESC317_} } "IPS60"{ type="binary"; loc="12..15"; ${_DESC318_} } "IPS59"{ type="binary"; loc="16..19"; ${_DESC319_} } "IPS58"{ type="binary"; loc="20..23"; ${_DESC320_} } "IPS57"{ type="binary"; loc="24..27"; ${_DESC321_} } "IPS56"{ type="binary"; loc="28..31"; ${_DESC322_} } } bitfield_DSPI_0_DIMR1{ "MASK"{ type="binary"; loc="0..31"; ${_DESC324_} } } bitfield_DSPI_0_DPIR1{ "DP"{ type="binary"; loc="0..31"; ${_DESC326_} } } bitfield_DSPI_0_CTARE0{ "Reserved0"{ type="binary"; loc="0..14"; } "FMSZE"{ type="binary"; loc="15"; ${_DESC328_} } "Reserved1"{ type="binary"; loc="16..20"; } "DTCP"{ type="binary"; loc="21..31"; ${_DESC329_} } } bitfield_DSPI_0_SREX{ "Reserved0"{ type="binary"; loc="0..23"; } "CMDCTR"{ type="binary"; loc="24..27"; ${_DESC331_} } "CMDNXTPTR"{ type="binary"; loc="28..31"; ${_DESC332_} } } bitfield_DTS_ENABLE{ "DTS_EN"{ type="binary"; loc="31"; ${_DESC334_} } "DTS_EN_B"{ type="binary"; loc="30"; ${_DESC335_} } "Reserved0"{ type="binary"; loc="0..29"; } } bitfield_DTS_STARTUP{ "AD"{ type="binary"; loc="0..31"; ${_DESC337_} } } bitfield_DTS_SEMAPHORE{ "ST"{ type="binary"; loc="0..31"; ${_DESC339_} } } bitfield_DTS_SEMAPHORE_B{ "ST_B"{ type="binary"; loc="0..31"; ${_DESC341_} } } bitfield_EIMCR{ "Reserved0"{ type="binary"; loc="0..30"; } "GEIEN"{ type="binary"; loc="31"; ${_DESC343_} } } bitfield_EIM_EICHEN{ "EICH0EN"{ type="binary"; loc="0"; ${_DESC345_} } "EICH1EN"{ type="binary"; loc="1"; ${_DESC345_} } "EICH2EN"{ type="binary"; loc="2"; ${_DESC345_} } "EICH3EN"{ type="binary"; loc="3"; ${_DESC345_} } "EICH4EN"{ type="binary"; loc="4"; ${_DESC345_} } "EICH5EN"{ type="binary"; loc="5"; ${_DESC345_} } "Reserved0"{ type="binary"; loc="6..31"; } } bitfield_EIM_EICHD0_Word0{ "CHKBIT_MASK"{ type="binary"; loc="0..7"; ${_DESC347_} } "Reserved0"{ type="binary"; loc="8..31"; } } bitfield_EIM_EICHD0_Word1{ "UDATA_MASK"{ type="binary"; loc="0..31"; ${_DESC349_} } } bitfield_EIM_EICHD0_Word2{ "LDATA_MASK"{ type="binary"; loc="0..31"; ${_DESC351_} } } bitfield_ERM_CR{ "ESCIE0"{ type="binary"; loc="0"; ${_DESC353_} } "ENCIE0"{ type="binary"; loc="1"; ${_DESC354_} } "Reserved0"{ type="binary"; loc="2..3"; } "ESCIE1"{ type="binary"; loc="4"; ${_DESC355_} } "ENCIE1"{ type="binary"; loc="5"; ${_DESC356_} } "Reserved1"{ type="binary"; loc="6..7"; } "ESCIE2"{ type="binary"; loc="8"; ${_DESC357_} } "ENCIE2"{ type="binary"; loc="9"; ${_DESC358_} } "Reserved2"{ type="binary"; loc="10..11"; } "ESCIE3"{ type="binary"; loc="12"; ${_DESC359_} } "ENCIE3"{ type="binary"; loc="13"; ${_DESC360_} } "Reserved3"{ type="binary"; loc="14..15"; } "ESCIE4"{ type="binary"; loc="16"; ${_DESC361_} } "ENCIE4"{ type="binary"; loc="17"; ${_DESC362_} } "Reserved4"{ type="binary"; loc="18..19"; } "ESCIE5"{ type="binary"; loc="20"; ${_DESC363_} } "ENCIE5"{ type="binary"; loc="21"; ${_DESC364_} } "Reserved5"{ type="binary"; loc="22..23"; } "ESCIE6"{ type="binary"; loc="24"; ${_DESC365_} } "ENCIE6"{ type="binary"; loc="25"; ${_DESC366_} } "Reserved6"{ type="binary"; loc="26..27"; } "ESCIE7"{ type="binary"; loc="28"; ${_DESC367_} } "ENCIE7"{ type="binary"; loc="29"; ${_DESC368_} } "Reserved7"{ type="binary"; loc="30..31"; } } bitfield_ERM_SR{ "SBC0"{ type="binary"; loc="0"; ${_DESC370_} } "NCE0"{ type="binary"; loc="1"; ${_DESC371_} } "Reserved0"{ type="binary"; loc="2..3"; } "SBC1"{ type="binary"; loc="4"; ${_DESC372_} } "NCE1"{ type="binary"; loc="5"; ${_DESC373_} } "Reserved1"{ type="binary"; loc="6..7"; } "SBC2"{ type="binary"; loc="8"; ${_DESC374_} } "NCE2"{ type="binary"; loc="9"; ${_DESC375_} } "Reserved2"{ type="binary"; loc="10..11"; } "SBC3"{ type="binary"; loc="12"; ${_DESC376_} } "NCE3"{ type="binary"; loc="13"; ${_DESC377_} } "Reserved3"{ type="binary"; loc="14..15"; } "SBC4"{ type="binary"; loc="16"; ${_DESC378_} } "NCE4"{ type="binary"; loc="17"; ${_DESC379_} } "Reserved4"{ type="binary"; loc="18..19"; } "SBC5"{ type="binary"; loc="20"; ${_DESC380_} } "NCE5"{ type="binary"; loc="21"; ${_DESC381_} } "Reserved5"{ type="binary"; loc="22..23"; } "SBC6"{ type="binary"; loc="24"; ${_DESC382_} } "NCE6"{ type="binary"; loc="25"; ${_DESC383_} } "Reserved6"{ type="binary"; loc="26..27"; } "SBC7"{ type="binary"; loc="28"; ${_DESC384_} } "NCE7"{ type="binary"; loc="29"; ${_DESC385_} } "Reserved7"{ type="binary"; loc="30..31"; } } bitfield_ERM_EAR0{ "EAR"{ type="binary"; loc="0..31"; ${_DESC387_} } } bitfield_ERM_SYN0{ "SYNDROME"{ type="binary"; loc="0..7"; ${_DESC389_} } "Reserved0"{ type="binary"; loc="8..31"; } } bitfield_FEC_EIR{ "HBERR"{ type="binary"; loc="0"; ${_DESC391_} } "BABR"{ type="binary"; loc="1"; ${_DESC392_} } "BABT"{ type="binary"; loc="2"; ${_DESC393_} } "GRA"{ type="binary"; loc="3"; ${_DESC394_} } "TXF"{ type="binary"; loc="4"; ${_DESC395_} } "TXB"{ type="binary"; loc="5"; ${_DESC396_} } "RXF"{ type="binary"; loc="6"; ${_DESC397_} } "RXB"{ type="binary"; loc="7"; ${_DESC398_} } "MII"{ type="binary"; loc="8"; ${_DESC399_} } "EBERR"{ type="binary"; loc="9"; ${_DESC400_} } "LC"{ type="binary"; loc="10"; ${_DESC401_} } "RL"{ type="binary"; loc="11"; ${_DESC402_} } "UN"{ type="binary"; loc="12"; ${_DESC403_} } "Reserved0"{ type="binary"; loc="13..31"; ${_DESC9_} } } bitfield_FEC_EIMR{ "HBERR"{ type="binary"; loc="0"; ${_DESC405_} } "BABR"{ type="binary"; loc="1"; ${_DESC406_} } "BABT"{ type="binary"; loc="2"; ${_DESC407_} } "GRA"{ type="binary"; loc="3"; ${_DESC408_} } "TXF"{ type="binary"; loc="4"; ${_DESC409_} } "TXB"{ type="binary"; loc="5"; ${_DESC410_} } "RXF"{ type="binary"; loc="6"; ${_DESC411_} } "RXB"{ type="binary"; loc="7"; ${_DESC412_} } "MII"{ type="binary"; loc="8"; ${_DESC413_} } "EBERR"{ type="binary"; loc="9"; ${_DESC414_} } "LC"{ type="binary"; loc="10"; ${_DESC415_} } "RL"{ type="binary"; loc="11"; ${_DESC416_} } "UN"{ type="binary"; loc="12"; ${_DESC417_} } "Reserved0"{ type="binary"; loc="13..31"; ${_DESC9_} } } bitfield_FEC_RDAR{ "Reserved0"{ type="binary"; loc="0..6"; ${_DESC9_} } "RDAR"{ type="binary"; loc="7"; ${_DESC419_} } "Reserved1"{ type="binary"; loc="8..31"; ${_DESC9_} } } bitfield_FEC_TDAR{ "Reserved0"{ type="binary"; loc="0..6"; ${_DESC9_} } "TDAR"{ type="binary"; loc="7"; ${_DESC421_} } "Reserved1"{ type="binary"; loc="8..31"; ${_DESC9_} } } bitfield_FEC_ECR{ "Reserved0"{ type="binary"; loc="0..3"; } "Reserved1"{ type="binary"; loc="4"; ${_DESC9_} } "Reserved2"{ type="binary"; loc="5"; } "Reserved3"{ type="binary"; loc="6..28"; ${_DESC9_} } "Reserved4"{ type="binary"; loc="29"; } "ETHER_EN"{ type="binary"; loc="30"; ${_DESC423_} } "RESET"{ type="binary"; loc="31"; ${_DESC424_} } } bitfield_FEC_MMFR{ "ST"{ type="binary"; loc="0..1"; ${_DESC426_} } "OP"{ type="binary"; loc="2..3"; ${_DESC427_} } "PA"{ type="binary"; loc="4..8"; ${_DESC428_} } "RA"{ type="binary"; loc="9..13"; ${_DESC429_} } "TA"{ type="binary"; loc="14..15"; ${_DESC430_} } "DATA"{ type="binary"; loc="16..31"; ${_DESC431_} } } bitfield_FEC_MSCR{ "Reserved0"{ type="binary"; loc="0..23"; ${_DESC9_} } "DIS_PRE"{ type="binary"; loc="24"; ${_DESC433_} } "MII_SPEED"{ type="binary"; loc="25..30"; ${_DESC434_} } "Reserved1"{ type="binary"; loc="31"; ${_DESC9_} } } bitfield_FEC_MIBC{ "MIB_DIS"{ type="binary"; loc="0"; ${_DESC436_} } "MIB_IDLE"{ type="binary"; loc="1"; ${_DESC437_} } "Reserved0"{ type="binary"; loc="2..31"; ${_DESC9_} } } bitfield_FEC_RCR{ "Reserved0"{ type="binary"; loc="0..4"; ${_DESC9_} } "MAX_FL"{ type="binary"; loc="5..15"; ${_DESC439_} } "Reserved1"{ type="binary"; loc="16..19"; ${_DESC9_} } "RMII_ECHO"{ type="binary"; loc="20"; ${_DESC440_} } "RMII_LOOP"{ type="binary"; loc="21"; ${_DESC441_} } "RMII_10T"{ type="binary"; loc="22"; ${_DESC442_} } "RMII_MODE"{ type="binary"; loc="23"; ${_DESC443_} } "Reserved2"{ type="binary"; loc="24..25"; ${_DESC9_} } "FCE"{ type="binary"; loc="26"; ${_DESC444_} } "BC_REJ"{ type="binary"; loc="27"; ${_DESC445_} } "PROM"{ type="binary"; loc="28"; ${_DESC446_} } "MII_MODE"{ type="binary"; loc="29"; ${_DESC447_} } "DRT"{ type="binary"; loc="30"; ${_DESC448_} } "LOOP"{ type="binary"; loc="31"; ${_DESC449_} } } bitfield_FEC_TCR{ "Reserved0"{ type="binary"; loc="0..26"; } "RFC_PAUSE"{ type="binary"; loc="27"; ${_DESC451_} } "TFC_PAUSE"{ type="binary"; loc="28"; ${_DESC452_} } "FDEN"{ type="binary"; loc="29"; ${_DESC453_} } "HBC"{ type="binary"; loc="30"; ${_DESC454_} } "GTS"{ type="binary"; loc="31"; ${_DESC455_} } } bitfield_FEC_PALR{ "PADDR1"{ type="binary"; loc="0..31"; ${_DESC457_} } } bitfield_FEC_PAUR{ "PADDR2"{ type="binary"; loc="0..15"; ${_DESC459_} } "TYPE"{ type="binary"; loc="16..31"; ${_DESC460_} } } bitfield_FEC_OPD{ "OPCODE"{ type="binary"; loc="0..15"; ${_DESC462_} } "PAUSE_DUR"{ type="binary"; loc="16..31"; ${_DESC463_} } } bitfield_FEC_IAUR{ "IADDR1"{ type="binary"; loc="0..31"; ${_DESC465_} } } bitfield_FEC_IALR{ "IADDR2"{ type="binary"; loc="0..31"; ${_DESC467_} } } bitfield_FEC_GAUR{ "GADDR1"{ type="binary"; loc="0..31"; ${_DESC469_} } } bitfield_FEC_GALR{ "GADDR2"{ type="binary"; loc="0..31"; ${_DESC471_} } } bitfield_FEC_TFWR{ "Reserved0"{ type="binary"; loc="0..29"; } "TFWR"{ type="binary"; loc="30..31"; ${_DESC473_} } } bitfield_FEC_FRBR{ "Reserved0"{ type="binary"; loc="0..20"; } "Reserved1"{ type="binary"; loc="21"; } "R_BOUND"{ type="binary"; loc="22..29"; ${_DESC475_} } "Reserved2"{ type="binary"; loc="30..31"; } } bitfield_FEC_FRSR{ "Reserved0"{ type="binary"; loc="0..20"; } "Reserved1"{ type="binary"; loc="21"; } "R_FSTART"{ type="binary"; loc="22..29"; ${_DESC477_} } "Reserved2"{ type="binary"; loc="30..31"; } } bitfield_FEC_ERDSR{ "R_DES_START"{ type="binary"; loc="0..29"; ${_DESC479_} } "Reserved0"{ type="binary"; loc="30..31"; } } bitfield_FEC_ETDSR{ "X_DES_START"{ type="binary"; loc="0..29"; ${_DESC481_} } "Reserved0"{ type="binary"; loc="30..31"; } } bitfield_FEC_EMRBR{ "Reserved0"{ type="binary"; loc="0..20"; } "R_BUF_SIZE"{ type="binary"; loc="21..27"; ${_DESC483_} } "Reserved1"{ type="binary"; loc="28..31"; } } bitfield_FEC_RMON_T_DROP{ "RMON_T_DROP"{ type="binary"; loc="0..31"; ${_DESC485_} } } bitfield_FEC_RMON_T_PACKETS{ "RMON_T_PACKETS"{ type="binary"; loc="0..31"; ${_DESC487_} } } bitfield_FEC_RMON_T_BC_PKT{ "RMON_T_BC_PKT"{ type="binary"; loc="0..31"; ${_DESC489_} } } bitfield_FEC_RMON_T_MC_PKT{ "RMON_T_MC_PKT"{ type="binary"; loc="0..31"; ${_DESC491_} } } bitfield_FEC_RMON_T_CRC_ALIGN{ "RMON_T_CRC_ALIGN"{ type="binary"; loc="0..31"; ${_DESC493_} } } bitfield_FEC_RMON_T_UNDERSIZE{ "RMON_T_UNDERSIZE"{ type="binary"; loc="0..31"; ${_DESC495_} } } bitfield_FEC_RMON_T_OVERSIZE{ "RMON_T_OVERSIZE"{ type="binary"; loc="0..31"; ${_DESC497_} } } bitfield_FEC_RMON_T_FRAG{ "RMON_T_FRAG"{ type="binary"; loc="0..31"; ${_DESC499_} } } bitfield_FEC_RMON_T_JAB{ "RMON_T_JAB"{ type="binary"; loc="0..31"; ${_DESC501_} } } bitfield_FEC_RMON_T_COL{ "RMON_T_COL"{ type="binary"; loc="0..31"; ${_DESC503_} } } bitfield_FEC_RMON_T_P64{ "RMON_T_P64"{ type="binary"; loc="0..31"; ${_DESC505_} } } bitfield_FEC_RMON_T_P65TO127{ "RMON_T_P65TO127"{ type="binary"; loc="0..31"; ${_DESC507_} } } bitfield_FEC_RMON_T_P128TO255{ "RMON_T_P128TO255"{ type="binary"; loc="0..31"; ${_DESC509_} } } bitfield_FEC_RMON_T_P256TO511{ "RMON_T_P256TO511"{ type="binary"; loc="0..31"; ${_DESC511_} } } bitfield_FEC_RMON_T_P512TO1023{ "RMON_T_P512TO1023"{ type="binary"; loc="0..31"; ${_DESC513_} } } bitfield_FEC_RMON_T_P1024TO2047{ "RMON_T_P1024TO2047"{ type="binary"; loc="0..31"; ${_DESC515_} } } bitfield_FEC_RMON_T_P_GTE2048{ "RMON_T_P_GTE2048"{ type="binary"; loc="0..31"; ${_DESC517_} } } bitfield_FEC_RMON_T_OCTETS{ "RMON_T_OCTETS"{ type="binary"; loc="0..31"; ${_DESC519_} } } bitfield_FEC_IEEE_T_DROP{ "IEEE_T_DROP"{ type="binary"; loc="0..31"; ${_DESC521_} } } bitfield_FEC_IEEE_T_FRAME_OK{ "IEEE_T_FRAME_OK"{ type="binary"; loc="0..31"; ${_DESC523_} } } bitfield_FEC_IEEE_T_1COL{ "IEEE_T_1COL"{ type="binary"; loc="0..31"; ${_DESC525_} } } bitfield_FEC_IEEE_T_MCOL{ "IEEE_T_MCOL"{ type="binary"; loc="0..31"; ${_DESC527_} } } bitfield_FEC_IEEE_T_DEF{ "IEEE_T_DEF"{ type="binary"; loc="0..31"; ${_DESC529_} } } bitfield_FEC_IEEE_T_LCOL{ "IEEE_T_LCOL"{ type="binary"; loc="0..31"; ${_DESC531_} } } bitfield_FEC_IEEE_T_EXCOL{ "IEEE_T_EXCOL"{ type="binary"; loc="0..31"; ${_DESC533_} } } bitfield_FEC_IEEE_T_MACERR{ "IEEE_T_MACERR"{ type="binary"; loc="0..31"; ${_DESC535_} } } bitfield_FEC_IEEE_T_CSERR{ "IEEE_T_CSERR"{ type="binary"; loc="0..31"; ${_DESC537_} } } bitfield_FEC_IEEE_T_SQE{ "IEEE_T_SQE"{ type="binary"; loc="0..31"; ${_DESC539_} } } bitfield_FEC_IEEE_T_FDXFC{ "IEEE_T_FDXFC"{ type="binary"; loc="0..31"; ${_DESC541_} } } bitfield_FEC_IEEE_T_OCTETS_OK{ "IEEE_T_OCTETS_OK"{ type="binary"; loc="0..31"; ${_DESC543_} } } bitfield_FEC_RMON_R_DROP{ "RMON_R_DROP"{ type="binary"; loc="0..31"; ${_DESC545_} } } bitfield_FEC_RMON_R_PACKETS{ "RMON_R_PACKETS"{ type="binary"; loc="0..31"; ${_DESC547_} } } bitfield_FEC_RMON_R_BC_PKT{ "RMON_R_BC_PKT"{ type="binary"; loc="0..31"; ${_DESC549_} } } bitfield_FEC_RMON_R_MC_PKT{ "RMON_R_MC_PKT"{ type="binary"; loc="0..31"; ${_DESC551_} } } bitfield_FEC_RMON_R_CRC_ALIGN{ "RMON_R_CRC_ALIGN"{ type="binary"; loc="0..31"; ${_DESC553_} } } bitfield_FEC_RMON_R_UNDERSIZE{ "RMON_R_UNDERSIZE"{ type="binary"; loc="0..31"; ${_DESC555_} } } bitfield_FEC_RMON_R_OVERSIZE{ "RMON_R_OVERSIZE"{ type="binary"; loc="0..31"; ${_DESC557_} } } bitfield_FEC_RMON_R_FRAG{ "RMON_R_FRAG"{ type="binary"; loc="0..31"; ${_DESC559_} } } bitfield_FEC_RMON_R_JAB{ "RMON_R_JAB"{ type="binary"; loc="0..31"; ${_DESC561_} } } bitfield_FEC_RMON_R_RESVD_0{ "RMON_R_RESVD_0"{ type="binary"; loc="0..31"; ${_DESC9_} } } bitfield_FEC_RMON_R_P64{ "RMON_R_P64"{ type="binary"; loc="0..31"; ${_DESC564_} } } bitfield_FEC_RMON_R_P65TO127{ "RMON_R_P65TO127"{ type="binary"; loc="0..31"; ${_DESC566_} } } bitfield_FEC_RMON_R_P128TO255{ "RMON_R_P128TO255"{ type="binary"; loc="0..31"; ${_DESC568_} } } bitfield_FEC_RMON_R_P256TO511{ "RMON_R_P256TO511"{ type="binary"; loc="0..31"; ${_DESC570_} } } bitfield_FEC_RMON_R_P512TO1023{ "RMON_R_P512TO1023"{ type="binary"; loc="0..31"; ${_DESC572_} } } bitfield_FEC_RMON_R_P1024TO2047{ "RMON_R_P1024TO2047"{ type="binary"; loc="0..31"; ${_DESC574_} } } bitfield_FEC_RMON_R_P_GTE2048{ "RMON_R_P_GTE2048"{ type="binary"; loc="0..31"; ${_DESC576_} } } bitfield_FEC_RMON_R_OCTETS{ "RMON_R_OCTETS"{ type="binary"; loc="0..31"; ${_DESC578_} } } bitfield_FEC_IEEE_R_DROP{ "IEEE_R_DROP"{ type="binary"; loc="0..31"; ${_DESC545_} } } bitfield_FEC_IEEE_R_FRAME_OK{ "IEEE_R_FRAME_OK"{ type="binary"; loc="0..31"; ${_DESC580_} } } bitfield_FEC_IEEE_R_CRC{ "IEEE_R_CRC"{ type="binary"; loc="0..31"; ${_DESC582_} } } bitfield_FEC_IEEE_R_ALIGN{ "IEEE_R_ALIGN"{ type="binary"; loc="0..31"; ${_DESC584_} } } bitfield_FEC_IEEE_R_MACERR{ "IEEE_R_MACERR"{ type="binary"; loc="0..31"; ${_DESC586_} } } bitfield_FEC_IEEE_R_FDXFC{ "IEEE_R_FDXFC"{ type="binary"; loc="0..31"; ${_DESC588_} } } bitfield_FEC_IEEE_R_OCTETS_OK{ "IEEE_R_OCTETS_OK"{ type="binary"; loc="0..31"; ${_DESC590_} } } bitfield_GTMINT_GTMMCR{ "Reserved0"{ type="binary"; loc="0"; } "MDIS"{ type="binary"; loc="1"; ${_DESC592_} } "Reserved1"{ type="binary"; loc="2..14"; } "AEISREN"{ type="binary"; loc="15"; ${_DESC593_} } "Reserved2"{ type="binary"; loc="16"; } "STPS"{ type="binary"; loc="17"; ${_DESC594_} } "Reserved3"{ type="binary"; loc="18..31"; } } bitfield_GTMINTCLR{ "Reserved0"{ type="binary"; loc="0..21"; } "INTCLR_PTR"{ type="binary"; loc="22..31"; ${_DESC596_} } } bitfield_GTMINT_GTMMAEICR{ "Reserved0"{ type="binary"; loc="0..30"; } "AEISRST"{ type="binary"; loc="31"; ${_DESC598_} } } bitfield_INTC_0_BCR{ "Reserved0"{ type="binary"; loc="0..18"; } "HVEN3"{ type="binary"; loc="19"; ${_DESC600_} } "Reserved1"{ type="binary"; loc="20..22"; } "HVEN2"{ type="binary"; loc="23"; ${_DESC600_} } "Reserved2"{ type="binary"; loc="24..26"; } "HVEN1"{ type="binary"; loc="27"; ${_DESC600_} } "Reserved3"{ type="binary"; loc="28..30"; } "HVEN0"{ type="binary"; loc="31"; ${_DESC600_} } } bitfield_INTC_0_CPR0{ "Reserved0"{ type="binary"; loc="0..27"; } "PRI"{ type="binary"; loc="28..31"; ${_DESC602_} } } bitfield_INTC_0_IACKR0{ "VTBA"{ type="binary"; loc="0..19"; ${_DESC604_} } "INTVEC"{ type="binary"; loc="20..29"; ${_DESC605_} } "Reserved0"{ type="binary"; loc="30..31"; } } bitfield_INTC_0_EOIR0{ "EOI"{ type="binary"; loc="0..31"; ${_DESC607_} } } bitfield_INTC_0_SSCIR0{ "Reserved0"{ type="binary"; loc="0..5"; } "SETa"{ type="binary"; loc="6"; ${_DESC609_} } "CLRa"{ type="binary"; loc="7"; ${_DESC610_} } } bitfield_INTC_0_PSR0{ "PRC_SELn"{ type="binary"; loc="0..3"; ${_DESC612_} } "Reserved0"{ type="binary"; loc="4..6"; } "SWTn"{ type="binary"; loc="7"; ${_DESC613_} } "Reserved1"{ type="binary"; loc="8..11"; } "PRIn"{ type="binary"; loc="12..15"; ${_DESC614_} } } bitfield_IRCOSC_CTL{ "Reserved0"{ type="binary"; loc="0..6"; } "Reserved1"{ type="binary"; loc="7"; ${_DESC616_} } "Reserved2"{ type="binary"; loc="8..10"; } "USER_TRIM"{ type="binary"; loc="11..15"; ${_DESC617_} } "Reserved3"{ type="binary"; loc="16..18"; } "Reserved4"{ type="binary"; loc="19..23"; ${_DESC618_} } "Reserved5"{ type="binary"; loc="24..25"; } "Reserved6"{ type="binary"; loc="26"; ${_DESC619_} } "Reserved7"{ type="binary"; loc="27..31"; } } bitfield_IRCOSC_NT{ "Reserved0"{ type="binary"; loc="0..19"; } "REG_EN"{ type="binary"; loc="20"; ${_DESC621_} } "TSENS_EN"{ type="binary"; loc="21"; ${_DESC622_} } "Reserved1"{ type="binary"; loc="22..23"; } "RCTRIM"{ type="binary"; loc="24..31"; ${_DESC623_} } } bitfield_IRCOSC_TT{ "Reserved0"{ type="binary"; loc="0..1"; } "COLD_TRIM"{ type="binary"; loc="2..11"; ${_DESC625_} } "Reserved1"{ type="binary"; loc="12..13"; } "HOT_TRIM"{ type="binary"; loc="14..23"; ${_DESC626_} } "Reserved2"{ type="binary"; loc="24..25"; } "TSENS_TRIM"{ type="binary"; loc="26..31"; ${_DESC627_} } } bitfield_LFAST_0_MCR{ "MSEN"{ type="binary"; loc="0"; ${_DESC629_} } "Reserved0"{ type="binary"; loc="1..6"; } "IPGDBG"{ type="binary"; loc="7"; ${_DESC630_} } "Reserved1"{ type="binary"; loc="8..14"; } "LSSEL"{ type="binary"; loc="15"; ${_DESC631_} } "DRFEN"{ type="binary"; loc="16"; ${_DESC632_} } "RXEN"{ type="binary"; loc="17"; ${_DESC633_} } "TXEN"{ type="binary"; loc="18"; ${_DESC634_} } "Reserved2"{ type="binary"; loc="19..26"; } "TXARBD"{ type="binary"; loc="27"; ${_DESC635_} } "CTSEN"{ type="binary"; loc="28"; ${_DESC636_} } "Reserved3"{ type="binary"; loc="29"; } "DRFRST"{ type="binary"; loc="30"; ${_DESC637_} } "DATAEN"{ type="binary"; loc="31"; ${_DESC638_} } } bitfield_LFAST_0_SCR{ "Reserved0"{ type="binary"; loc="0..14"; } "DRMD"{ type="binary"; loc="15"; ${_DESC640_} } "Reserved1"{ type="binary"; loc="16..22"; } "RDR"{ type="binary"; loc="23"; ${_DESC641_} } "Reserved2"{ type="binary"; loc="24..30"; } "TDR"{ type="binary"; loc="31"; ${_DESC642_} } } bitfield_LFAST_0_COCR{ "SMPSEL"{ type="binary"; loc="0..7"; ${_DESC644_} } "Reserved0"{ type="binary"; loc="8..27"; } "CORRTH"{ type="binary"; loc="28..30"; ${_DESC645_} } "Reserved1"{ type="binary"; loc="31"; } } bitfield_LFAST_0_TMCR{ "Reserved0"{ type="binary"; loc="0..5"; } "CLKTST"{ type="binary"; loc="6"; ${_DESC647_} } "LPON"{ type="binary"; loc="7"; ${_DESC648_} } "Reserved1"{ type="binary"; loc="8..12"; } "LPMOD"{ type="binary"; loc="13..15"; ${_DESC649_} } "LPFRMTH"{ type="binary"; loc="16..31"; ${_DESC650_} } } bitfield_LFAST_0_ALCR{ "Reserved0"{ type="binary"; loc="0..14"; } "LPCNTEN"{ type="binary"; loc="15"; ${_DESC652_} } "LPFMCNT"{ type="binary"; loc="16..31"; ${_DESC653_} } } bitfield_LFAST_0_RCDCR{ "Reserved0"{ type="binary"; loc="0..11"; } "DRCNT"{ type="binary"; loc="12..15"; ${_DESC655_} } "Reserved1"{ type="binary"; loc="16..31"; } } bitfield_LFAST_0_SLCR{ "HSCNT"{ type="binary"; loc="0..7"; ${_DESC657_} } "Reserved0"{ type="binary"; loc="8..11"; } "LSCNT"{ type="binary"; loc="12..15"; ${_DESC658_} } "HWKCNT"{ type="binary"; loc="16..23"; ${_DESC659_} } "Reserved1"{ type="binary"; loc="24..27"; } "LWKCNT"{ type="binary"; loc="28..31"; ${_DESC660_} } } bitfield_LFAST_0_ICR{ "Reserved0"{ type="binary"; loc="0..13"; } "ICLCSEQ"{ type="binary"; loc="14"; ${_DESC662_} } "SNDICLC"{ type="binary"; loc="15"; ${_DESC663_} } "Reserved1"{ type="binary"; loc="16..23"; } "ICLCPLD"{ type="binary"; loc="24..31"; ${_DESC664_} } } bitfield_LFAST_0_PICR{ "Reserved0"{ type="binary"; loc="0..14"; } "PNGREQ"{ type="binary"; loc="15"; ${_DESC666_} } "PNGAUTO"{ type="binary"; loc="16"; ${_DESC667_} } "Reserved1"{ type="binary"; loc="17..23"; } "PNGPYLD"{ type="binary"; loc="24..31"; ${_DESC668_} } } bitfield_LFAST_0_RFCR{ "Reserved0"{ type="binary"; loc="0..9"; } "RCTSMX"{ type="binary"; loc="10..15"; ${_DESC670_} } "Reserved1"{ type="binary"; loc="16..25"; } "RCTSMN"{ type="binary"; loc="26..31"; ${_DESC671_} } } bitfield_LFAST_0_TIER{ "Reserved0"{ type="binary"; loc="0..13"; } "TXIIE"{ type="binary"; loc="14"; ${_DESC673_} } "TXOVIE"{ type="binary"; loc="15"; ${_DESC674_} } "Reserved1"{ type="binary"; loc="16..26"; } "TXPNGIE"{ type="binary"; loc="27"; ${_DESC675_} } "Reserved2"{ type="binary"; loc="28"; } "TXUNSIE"{ type="binary"; loc="29"; ${_DESC676_} } "TXICLCIE"{ type="binary"; loc="30"; ${_DESC677_} } "TXDTIE"{ type="binary"; loc="31"; ${_DESC678_} } } bitfield_LFAST_0_RIER{ "Reserved0"{ type="binary"; loc="0..7"; } "RXUOIE"{ type="binary"; loc="8"; ${_DESC680_} } "RXMNIE"{ type="binary"; loc="9"; ${_DESC681_} } "RXMXIE"{ type="binary"; loc="10"; ${_DESC682_} } "RXUFIE"{ type="binary"; loc="11"; ${_DESC683_} } "RXOFIE"{ type="binary"; loc="12"; ${_DESC684_} } "RXSZIE"{ type="binary"; loc="13"; ${_DESC685_} } "RXICIE"{ type="binary"; loc="14"; ${_DESC686_} } "RXLCEIE"{ type="binary"; loc="15"; ${_DESC687_} } "Reserved1"{ type="binary"; loc="16..27"; } "RXCTSIE"{ type="binary"; loc="28"; ${_DESC688_} } "RXDIE"{ type="binary"; loc="29"; ${_DESC689_} } "RXUNSIE"{ type="binary"; loc="30"; ${_DESC690_} } "Reserved2"{ type="binary"; loc="31"; } } bitfield_LFAST_0_RIIER{ "Reserved0"{ type="binary"; loc="0..17"; } "ICPFIE"{ type="binary"; loc="18"; ${_DESC692_} } "ICPSIE"{ type="binary"; loc="19"; ${_DESC693_} } "ICPRIE"{ type="binary"; loc="20"; ${_DESC694_} } "ICTOIE"{ type="binary"; loc="21"; ${_DESC695_} } "ICLPIE"{ type="binary"; loc="22"; ${_DESC696_} } "ICCTIE"{ type="binary"; loc="23"; ${_DESC697_} } "ICTDIE"{ type="binary"; loc="24"; ${_DESC698_} } "ICTEIE"{ type="binary"; loc="25"; ${_DESC699_} } "ICRFIE"{ type="binary"; loc="26"; ${_DESC700_} } "ICRSIE"{ type="binary"; loc="27"; ${_DESC701_} } "ICTFIE"{ type="binary"; loc="28"; ${_DESC702_} } "ICTSIE"{ type="binary"; loc="29"; ${_DESC703_} } "ICPOFIE"{ type="binary"; loc="30"; ${_DESC704_} } "ICPONIE"{ type="binary"; loc="31"; ${_DESC705_} } } bitfield_LFAST_0_LCR{ "Reserved0"{ type="binary"; loc="0..7"; } "SWWKLD"{ type="binary"; loc="8"; ${_DESC707_} } "SWSLPLD"{ type="binary"; loc="9"; ${_DESC708_} } "SWWKLR"{ type="binary"; loc="10"; ${_DESC709_} } "SWSLPLR"{ type="binary"; loc="11"; ${_DESC710_} } "SWOFFLD"{ type="binary"; loc="12"; ${_DESC711_} } "SWONLD"{ type="binary"; loc="13"; ${_DESC712_} } "SWOFFLR"{ type="binary"; loc="14"; ${_DESC713_} } "SWONLR"{ type="binary"; loc="15"; ${_DESC714_} } "LVRXOFF"{ type="binary"; loc="16"; ${_DESC715_} } "LVTXOE"{ type="binary"; loc="17"; ${_DESC716_} } "TXCMUX"{ type="binary"; loc="18"; ${_DESC717_} } "LVRFEN"{ type="binary"; loc="19"; ${_DESC718_} } "LVLPEN"{ type="binary"; loc="20"; ${_DESC719_} } "Reserved1"{ type="binary"; loc="21"; } "LVRXOP"{ type="binary"; loc="22..24"; ${_DESC720_} } "Reserved2"{ type="binary"; loc="25"; } "Reserved3"{ type="binary"; loc="26"; } "Reserved4"{ type="binary"; loc="27..28"; } "LVTXOP"{ type="binary"; loc="29"; ${_DESC721_} } "LVCKSS"{ type="binary"; loc="30"; ${_DESC722_} } "LVCKP"{ type="binary"; loc="31"; ${_DESC723_} } } bitfield_LFAST_0_UNSTCR{ "Reserved0"{ type="binary"; loc="0..14"; } "USNDRQ"{ type="binary"; loc="15"; ${_DESC725_} } "Reserved1"{ type="binary"; loc="16..24"; } "UNSHDR"{ type="binary"; loc="25..31"; ${_DESC726_} } } bitfield_LFAST_0_UNSTDR8{ "UNTXD"{ type="binary"; loc="0..31"; ${_DESC728_} } } bitfield_LFAST_0_GSR{ "DUALMD"{ type="binary"; loc="0"; ${_DESC730_} } "Reserved0"{ type="binary"; loc="1..12"; } "LRMD"{ type="binary"; loc="13"; ${_DESC731_} } "LDSM"{ type="binary"; loc="14"; ${_DESC732_} } "DRSM"{ type="binary"; loc="15"; ${_DESC733_} } "Reserved1"{ type="binary"; loc="16..26"; } "LPTXDN"{ type="binary"; loc="27"; ${_DESC734_} } "LPFPDV"{ type="binary"; loc="28"; ${_DESC735_} } "LPCPDV"{ type="binary"; loc="29"; ${_DESC736_} } "LPCHDV"{ type="binary"; loc="30"; ${_DESC737_} } "LPCSDV"{ type="binary"; loc="31"; ${_DESC738_} } } bitfield_LFAST_0_PISR{ "Reserved0"{ type="binary"; loc="0..23"; } "RXPNGD"{ type="binary"; loc="24..31"; ${_DESC740_} } } bitfield_LFAST_0_DFSR{ "Reserved0"{ type="binary"; loc="0..1"; } "RXDCNT"{ type="binary"; loc="2..7"; ${_DESC742_} } "Reserved1"{ type="binary"; loc="8..12"; } "RXFCNT"{ type="binary"; loc="13..15"; ${_DESC743_} } "Reserved2"{ type="binary"; loc="16..17"; } "TXDCNT"{ type="binary"; loc="18..23"; ${_DESC744_} } "Reserved3"{ type="binary"; loc="24..28"; } "TXFCNT"{ type="binary"; loc="29..31"; ${_DESC745_} } } bitfield_LFAST_0_TISR{ "Reserved0"{ type="binary"; loc="0..13"; } "TXIEF"{ type="binary"; loc="14"; ${_DESC747_} } "TXOVF"{ type="binary"; loc="15"; ${_DESC748_} } "Reserved1"{ type="binary"; loc="16..26"; } "TXPNGF"{ type="binary"; loc="27"; ${_DESC749_} } "Reserved2"{ type="binary"; loc="28"; } "TXUNSF"{ type="binary"; loc="29"; ${_DESC750_} } "TXICLCF"{ type="binary"; loc="30"; ${_DESC751_} } "TXDTF"{ type="binary"; loc="31"; ${_DESC752_} } } bitfield_LFAST_0_RISR{ "Reserved0"{ type="binary"; loc="0..7"; } "RXUOF"{ type="binary"; loc="8"; ${_DESC680_} } "RXMNF"{ type="binary"; loc="9"; ${_DESC754_} } "RXMXF"{ type="binary"; loc="10"; ${_DESC755_} } "RXUFF"{ type="binary"; loc="11"; ${_DESC756_} } "RXOFF"{ type="binary"; loc="12"; ${_DESC757_} } "RXSZF"{ type="binary"; loc="13"; ${_DESC758_} } "RXICF"{ type="binary"; loc="14"; ${_DESC759_} } "RXLCEF"{ type="binary"; loc="15"; ${_DESC760_} } "Reserved1"{ type="binary"; loc="16..27"; } "RXCTSF"{ type="binary"; loc="28"; ${_DESC761_} } "RXDF"{ type="binary"; loc="29"; ${_DESC762_} } "RXUNSF"{ type="binary"; loc="30"; ${_DESC763_} } "Reserved2"{ type="binary"; loc="31"; } } bitfield_LFAST_0_RIISR{ "Reserved0"{ type="binary"; loc="0..17"; } "ICPFF"{ type="binary"; loc="18"; ${_DESC692_} } "ICPSF"{ type="binary"; loc="19"; ${_DESC693_} } "ICPRF"{ type="binary"; loc="20"; ${_DESC765_} } "ICTOF"{ type="binary"; loc="21"; ${_DESC695_} } "ICLPF"{ type="binary"; loc="22"; ${_DESC696_} } "ICCTF"{ type="binary"; loc="23"; ${_DESC766_} } "ICTDF"{ type="binary"; loc="24"; ${_DESC698_} } "ICTEF"{ type="binary"; loc="25"; ${_DESC699_} } "ICRFF"{ type="binary"; loc="26"; ${_DESC700_} } "ICRSF"{ type="binary"; loc="27"; ${_DESC701_} } "ICTFF"{ type="binary"; loc="28"; ${_DESC702_} } "ICTSF"{ type="binary"; loc="29"; ${_DESC703_} } "ICPOFF"{ type="binary"; loc="30"; ${_DESC704_} } "ICPONF"{ type="binary"; loc="31"; ${_DESC705_} } } bitfield_LFAST_0_PLLLSR{ "Reserved0"{ type="binary"; loc="0..27"; } "LRSLPS"{ type="binary"; loc="28"; ${_DESC768_} } "LDSLPS"{ type="binary"; loc="29"; ${_DESC769_} } "LDPDS"{ type="binary"; loc="30"; ${_DESC770_} } "LRPDS"{ type="binary"; loc="31"; ${_DESC771_} } } bitfield_LFAST_0_UNSRSR{ "Reserved0"{ type="binary"; loc="0..22"; } "URXDV"{ type="binary"; loc="23"; ${_DESC773_} } "Reserved1"{ type="binary"; loc="24..28"; } "URPCNT"{ type="binary"; loc="29..31"; ${_DESC774_} } } bitfield_LFAST_0_UNSRDR8{ "UNRXD"{ type="binary"; loc="0..31"; ${_DESC776_} } } bitfield_LINFlexD_0_LINCR1{ "Reserved0"{ type="binary"; loc="0..15"; } "CCD"{ type="binary"; loc="16"; ${_DESC778_} } "CFD"{ type="binary"; loc="17"; ${_DESC779_} } "LASE"{ type="binary"; loc="18"; ${_DESC780_} } "AUTOWU"{ type="binary"; loc="19"; ${_DESC781_} } "MBL"{ type="binary"; loc="20..23"; ${_DESC782_} } "BF"{ type="binary"; loc="24"; ${_DESC783_} } "Reserved1"{ type="binary"; loc="25"; } "LBKM"{ type="binary"; loc="26"; ${_DESC784_} } "MME"{ type="binary"; loc="27"; ${_DESC785_} } "SSBL"{ type="binary"; loc="28"; ${_DESC786_} } "RBLM"{ type="binary"; loc="29"; ${_DESC787_} } "SLEEP"{ type="binary"; loc="30"; ${_DESC788_} } "INIT"{ type="binary"; loc="31"; ${_DESC789_} } } bitfield_LINFlexD_0_LINIER{ "Reserved0"{ type="binary"; loc="0..15"; } "SZIE"{ type="binary"; loc="16"; ${_DESC791_} } "OCIE"{ type="binary"; loc="17"; ${_DESC792_} } "BEIE"{ type="binary"; loc="18"; ${_DESC793_} } "CEIE"{ type="binary"; loc="19"; ${_DESC794_} } "HEIE"{ type="binary"; loc="20"; ${_DESC795_} } "Reserved1"{ type="binary"; loc="21..22"; } "FEIE"{ type="binary"; loc="23"; ${_DESC796_} } "BOIE"{ type="binary"; loc="24"; ${_DESC797_} } "LSIE"{ type="binary"; loc="25"; ${_DESC798_} } "WUIE"{ type="binary"; loc="26"; ${_DESC799_} } "DBFIE"{ type="binary"; loc="27"; ${_DESC800_} } "DBEIETOIE"{ type="binary"; loc="28"; ${_DESC801_} } "DRIE"{ type="binary"; loc="29"; ${_DESC802_} } "DTIE"{ type="binary"; loc="30"; ${_DESC803_} } "HRIE"{ type="binary"; loc="31"; ${_DESC804_} } } bitfield_LINFlexD_0_LINSR{ "Reserved0"{ type="binary"; loc="0..11"; } "AUTOSYNC_COMP"{ type="binary"; loc="12"; ${_DESC806_} } "RDC"{ type="binary"; loc="13..15"; ${_DESC807_} } "LINS"{ type="binary"; loc="16..19"; ${_DESC808_} } "Reserved1"{ type="binary"; loc="20..21"; } "RMB"{ type="binary"; loc="22"; ${_DESC809_} } "DRBNE"{ type="binary"; loc="23"; ${_DESC810_} } "RXbusy"{ type="binary"; loc="24"; ${_DESC811_} } "RDI"{ type="binary"; loc="25"; ${_DESC812_} } "WUF"{ type="binary"; loc="26"; ${_DESC813_} } "DBFF"{ type="binary"; loc="27"; ${_DESC814_} } "DBEF"{ type="binary"; loc="28"; ${_DESC815_} } "DRF"{ type="binary"; loc="29"; ${_DESC816_} } "DTF"{ type="binary"; loc="30"; ${_DESC817_} } "HRF"{ type="binary"; loc="31"; ${_DESC818_} } } bitfield_LINFlexD_0_LINESR{ "Reserved0"{ type="binary"; loc="0..15"; } "SZF"{ type="binary"; loc="16"; ${_DESC820_} } "OCF"{ type="binary"; loc="17"; ${_DESC821_} } "BEF"{ type="binary"; loc="18"; ${_DESC822_} } "CEF"{ type="binary"; loc="19"; ${_DESC823_} } "SFEF"{ type="binary"; loc="20"; ${_DESC824_} } "SDEF"{ type="binary"; loc="21"; ${_DESC825_} } "IDPEF"{ type="binary"; loc="22"; ${_DESC826_} } "FEF"{ type="binary"; loc="23"; ${_DESC827_} } "BOF"{ type="binary"; loc="24"; ${_DESC828_} } "Reserved1"{ type="binary"; loc="25..30"; } "NF"{ type="binary"; loc="31"; ${_DESC829_} } } bitfield_LINFlexD_0_UARTCR{ "Reserved0"{ type="binary"; loc="0"; } "Reserved1"{ type="binary"; loc="1..8"; } "NEF"{ type="binary"; loc="9..11"; ${_DESC831_} } "DTU"{ type="binary"; loc="12"; ${_DESC832_} } "SBUR"{ type="binary"; loc="13..14"; ${_DESC833_} } "WLS"{ type="binary"; loc="15"; ${_DESC834_} } "TDFLTFC"{ type="binary"; loc="16..18"; ${_DESC835_} } "RDFLRFC"{ type="binary"; loc="19..21"; ${_DESC836_} } "RFBM"{ type="binary"; loc="22"; ${_DESC837_} } "TFBM"{ type="binary"; loc="23"; ${_DESC838_} } "WL1"{ type="binary"; loc="24"; ${_DESC839_} } "PC1"{ type="binary"; loc="25"; ${_DESC840_} } "RxEn"{ type="binary"; loc="26"; ${_DESC841_} } "TxEn"{ type="binary"; loc="27"; ${_DESC842_} } "PC0"{ type="binary"; loc="28"; ${_DESC840_} } "PCE"{ type="binary"; loc="29"; ${_DESC843_} } "WL0"{ type="binary"; loc="30"; ${_DESC844_} } "UART"{ type="binary"; loc="31"; ${_DESC845_} } } bitfield_LINFlexD_0_UARTSR{ "Reserved0"{ type="binary"; loc="0..15"; } "SZF"{ type="binary"; loc="16"; ${_DESC847_} } "OCF"{ type="binary"; loc="17"; ${_DESC848_} } "PE"{ type="binary"; loc="18..21"; ${_DESC849_} } "RMB"{ type="binary"; loc="22"; ${_DESC850_} } "FEF"{ type="binary"; loc="23"; ${_DESC851_} } "BOF"{ type="binary"; loc="24"; ${_DESC852_} } "RDI"{ type="binary"; loc="25"; ${_DESC853_} } "WUF"{ type="binary"; loc="26"; ${_DESC854_} } "RFNE"{ type="binary"; loc="27"; ${_DESC855_} } "TO"{ type="binary"; loc="28"; ${_DESC856_} } "DRFRFE"{ type="binary"; loc="29"; ${_DESC857_} } "DTFTFF"{ type="binary"; loc="30"; ${_DESC858_} } "NF"{ type="binary"; loc="31"; ${_DESC859_} } } bitfield_LINFlexD_0_LINTCSR{ "Reserved0"{ type="binary"; loc="0..20"; } "MODE"{ type="binary"; loc="21"; ${_DESC861_} } "IOT"{ type="binary"; loc="22"; ${_DESC862_} } "TOCE"{ type="binary"; loc="23"; ${_DESC863_} } "CNT"{ type="binary"; loc="24..31"; ${_DESC864_} } } bitfield_LINFlexD_0_LINOCR{ "Reserved0"{ type="binary"; loc="0..15"; } "OC2"{ type="binary"; loc="16..23"; ${_DESC866_} } "OC1"{ type="binary"; loc="24..31"; ${_DESC867_} } } bitfield_LINFlexD_0_LINTOCR{ "Reserved0"{ type="binary"; loc="0..19"; } "RTO"{ type="binary"; loc="20..23"; ${_DESC869_} } "Reserved1"{ type="binary"; loc="24"; } "HTO"{ type="binary"; loc="25..31"; ${_DESC870_} } } bitfield_LINFlexD_0_LINFBRR{ "Reserved0"{ type="binary"; loc="0..27"; } "FBR"{ type="binary"; loc="28..31"; ${_DESC872_} } } bitfield_LINFlexD_0_LINIBRR{ "Reserved0"{ type="binary"; loc="0..11"; } "IBR"{ type="binary"; loc="12..31"; ${_DESC874_} } } bitfield_LINFlexD_0_LINCFR{ "Reserved0"{ type="binary"; loc="0..23"; } "CF"{ type="binary"; loc="24..31"; ${_DESC876_} } } bitfield_LINFlexD_0_LINCR2{ "Reserved0"{ type="binary"; loc="0..15"; } "TBDE"{ type="binary"; loc="16"; ${_DESC878_} } "IOBE"{ type="binary"; loc="17"; ${_DESC879_} } "IOPE"{ type="binary"; loc="18"; ${_DESC880_} } "WURQ"{ type="binary"; loc="19"; ${_DESC881_} } "DDRQ"{ type="binary"; loc="20"; ${_DESC882_} } "DTRQ"{ type="binary"; loc="21"; ${_DESC883_} } "ABRQ"{ type="binary"; loc="22"; ${_DESC884_} } "HTRQ"{ type="binary"; loc="23"; ${_DESC885_} } "Reserved1"{ type="binary"; loc="24..31"; } } bitfield_LINFlexD_0_BIDR{ "Reserved0"{ type="binary"; loc="0..15"; } "DFL"{ type="binary"; loc="16..21"; ${_DESC887_} } "DIR"{ type="binary"; loc="22"; ${_DESC888_} } "CCS"{ type="binary"; loc="23"; ${_DESC889_} } "Reserved1"{ type="binary"; loc="24..25"; } "ID"{ type="binary"; loc="26..31"; ${_DESC890_} } } bitfield_LINFlexD_0_BDRL{ "DATA3"{ type="binary"; loc="0..7"; ${_DESC892_} } "DATA2"{ type="binary"; loc="8..15"; ${_DESC893_} } "DATA1"{ type="binary"; loc="16..23"; ${_DESC894_} } "DATA0"{ type="binary"; loc="24..31"; ${_DESC895_} } } bitfield_LINFlexD_0_BDRM{ "DATA7"{ type="binary"; loc="0..7"; ${_DESC897_} } "DATA6"{ type="binary"; loc="8..15"; ${_DESC898_} } "DATA5"{ type="binary"; loc="16..23"; ${_DESC899_} } "DATA4"{ type="binary"; loc="24..31"; ${_DESC900_} } } bitfield_LINFlexD_0_IFER{ "Reserved0"{ type="binary"; loc="0..15"; } "FACT"{ type="binary"; loc="16..31"; ${_DESC902_} } } bitfield_LINFlexD_0_IFMI{ "Reserved0"{ type="binary"; loc="0..26"; } "IFMI"{ type="binary"; loc="27..31"; ${_DESC904_} } } bitfield_LINFlexD_0_IFMR{ "Reserved0"{ type="binary"; loc="0..23"; } "IFM"{ type="binary"; loc="24..31"; ${_DESC906_} } } bitfield_LINFlexD_0_IFCR0{ "Reserved0"{ type="binary"; loc="0..15"; } "DFL"{ type="binary"; loc="16..21"; ${_DESC908_} } "DIR"{ type="binary"; loc="22"; ${_DESC909_} } "CCS"{ type="binary"; loc="23"; ${_DESC910_} } "Reserved1"{ type="binary"; loc="24..25"; } "ID"{ type="binary"; loc="26..31"; ${_DESC911_} } } bitfield_LINFlexD_0_GCR{ "Reserved0"{ type="binary"; loc="0..25"; } "TDFBM"{ type="binary"; loc="26"; ${_DESC913_} } "RDFBM"{ type="binary"; loc="27"; ${_DESC914_} } "TDLIS"{ type="binary"; loc="28"; ${_DESC915_} } "RDLIS"{ type="binary"; loc="29"; ${_DESC916_} } "STOP"{ type="binary"; loc="30"; ${_DESC917_} } "SR"{ type="binary"; loc="31"; ${_DESC918_} } } bitfield_LINFlexD_0_UARTPTO{ "Reserved0"{ type="binary"; loc="0..19"; } "PTO"{ type="binary"; loc="20..31"; ${_DESC920_} } } bitfield_LINFlexD_0_UARTCTO{ "Reserved0"{ type="binary"; loc="0..19"; } "CTO"{ type="binary"; loc="20..31"; ${_DESC922_} } } bitfield_LINFlexD_0_DMATXE{ "Reserved0"{ type="binary"; loc="0..15"; ${_DESC924_} } "DTE"{ type="binary"; loc="16..31"; ${_DESC925_} } } bitfield_LINFlexD_0_DMARXE{ "Reserved0"{ type="binary"; loc="0..15"; ${_DESC927_} } "DRE"{ type="binary"; loc="16..31"; ${_DESC928_} } } bitfield_MC_CGM_PCS_SDUR{ "SDUR"{ type="binary"; loc="0..7"; ${_DESC930_} } } bitfield_MC_CGM_PCS_DIVC1{ "INIT"{ type="binary"; loc="0..15"; ${_DESC932_} } "Reserved0"{ type="binary"; loc="16..23"; } "RATE"{ type="binary"; loc="24..31"; ${_DESC933_} } } bitfield_MC_CGM_PCS_DIVS1{ "Reserved0"{ type="binary"; loc="0..11"; } "DIVS"{ type="binary"; loc="12..31"; ${_DESC935_} } } bitfield_MC_CGM_PCS_DIVE1{ "Reserved0"{ type="binary"; loc="0..11"; } "DIVE"{ type="binary"; loc="12..31"; ${_DESC937_} } } bitfield_MC_CGM_PCS_DIVC2{ "INIT"{ type="binary"; loc="0..15"; ${_DESC939_} } "Reserved0"{ type="binary"; loc="16..23"; } "RATE"{ type="binary"; loc="24..31"; ${_DESC940_} } } bitfield_MC_CGM_PCS_DIVS2{ "Reserved0"{ type="binary"; loc="0..11"; } "DIVS"{ type="binary"; loc="12..31"; ${_DESC942_} } } bitfield_MC_CGM_PCS_DIVE2{ "Reserved0"{ type="binary"; loc="0..11"; } "DIVE"{ type="binary"; loc="12..31"; ${_DESC944_} } } bitfield_MC_CGM_PCS_DIVC3{ "INIT"{ type="binary"; loc="0..15"; ${_DESC946_} } "Reserved0"{ type="binary"; loc="16..23"; } "RATE"{ type="binary"; loc="24..31"; ${_DESC947_} } } bitfield_MC_CGM_PCS_DIVS3{ "Reserved0"{ type="binary"; loc="0..11"; } "DIVS"{ type="binary"; loc="12..31"; ${_DESC949_} } } bitfield_MC_CGM_PCS_DIVE3{ "Reserved0"{ type="binary"; loc="0..11"; } "DIVE"{ type="binary"; loc="12..31"; ${_DESC951_} } } bitfield_MC_CGM_SC_SS{ "Reserved0"{ type="binary"; loc="0..3"; } "SELSTAT"{ type="binary"; loc="4..7"; ${_DESC953_} } "Reserved1"{ type="binary"; loc="8..11"; } "SWTRG"{ type="binary"; loc="12..14"; ${_DESC954_} } "SWIP"{ type="binary"; loc="15"; ${_DESC955_} } "Reserved2"{ type="binary"; loc="16..31"; } } bitfield_MC_CGM_SC_DC0{ "DE"{ type="binary"; loc="0"; ${_DESC957_} } "Reserved0"{ type="binary"; loc="1..9"; } "DIV"{ type="binary"; loc="10..15"; ${_DESC958_} } "Reserved1"{ type="binary"; loc="16..31"; } } bitfield_MC_CGM_SC_DC1{ "DE"{ type="binary"; loc="0"; ${_DESC957_} } "Reserved0"{ type="binary"; loc="1..9"; } "DIV"{ type="binary"; loc="10..15"; ${_DESC960_} } "Reserved1"{ type="binary"; loc="16..31"; } } bitfield_MC_CGM_AC0_SC{ "Reserved0"{ type="binary"; loc="0..3"; } "SELCTL"{ type="binary"; loc="4..7"; ${_DESC962_} } "Reserved1"{ type="binary"; loc="8..31"; } } bitfield_MC_CGM_AC0_SS{ "Reserved0"{ type="binary"; loc="0..3"; } "SELSTAT"{ type="binary"; loc="4..7"; ${_DESC964_} } "Reserved1"{ type="binary"; loc="8..31"; } } bitfield_MC_CGM_AC0_DC0{ "DE"{ type="binary"; loc="0"; ${_DESC966_} } "Reserved0"{ type="binary"; loc="1..11"; } "DIV"{ type="binary"; loc="12..15"; ${_DESC967_} } "Reserved1"{ type="binary"; loc="16..31"; } } bitfield_MC_CGM_AC0_DC1{ "DE"{ type="binary"; loc="0"; ${_DESC966_} } "Reserved0"{ type="binary"; loc="1..8"; } "DIV"{ type="binary"; loc="9..15"; ${_DESC969_} } "Reserved1"{ type="binary"; loc="16..31"; } } bitfield_MC_CGM_AC0_DC2{ "DE"{ type="binary"; loc="0"; ${_DESC966_} } "Reserved0"{ type="binary"; loc="1..8"; } "DIV"{ type="binary"; loc="9..15"; ${_DESC971_} } "Reserved1"{ type="binary"; loc="16..31"; } } bitfield_MC_CGM_AC1_SC{ "Reserved0"{ type="binary"; loc="0..3"; } "SELCTL"{ type="binary"; loc="4..7"; ${_DESC973_} } "Reserved1"{ type="binary"; loc="8..31"; } } bitfield_MC_CGM_AC1_SS{ "Reserved0"{ type="binary"; loc="0..3"; } "SELSTAT"{ type="binary"; loc="4..7"; ${_DESC975_} } "Reserved1"{ type="binary"; loc="8..31"; } } bitfield_MC_CGM_AC1_DC0{ "DE"{ type="binary"; loc="0"; ${_DESC966_} } "Reserved0"{ type="binary"; loc="1..8"; } "DIV"{ type="binary"; loc="9..15"; ${_DESC977_} } "Reserved1"{ type="binary"; loc="16..31"; } } bitfield_MC_CGM_AC2_DC0{ "DE"{ type="binary"; loc="0"; ${_DESC966_} } "Reserved0"{ type="binary"; loc="1..9"; } "DIV"{ type="binary"; loc="10..15"; ${_DESC979_} } "Reserved1"{ type="binary"; loc="16..31"; } } bitfield_MC_CGM_AC3_SC{ "Reserved0"{ type="binary"; loc="0..3"; } "SELCTL"{ type="binary"; loc="4..7"; ${_DESC981_} } "Reserved1"{ type="binary"; loc="8..31"; } } bitfield_MC_CGM_AC3_SS{ "Reserved0"{ type="binary"; loc="0..3"; } "SELSTAT"{ type="binary"; loc="4..7"; ${_DESC983_} } "Reserved1"{ type="binary"; loc="8..31"; } } bitfield_MC_CGM_AC7_SC{ "Reserved0"{ type="binary"; loc="0..3"; } "SELCTL"{ type="binary"; loc="4..7"; ${_DESC985_} } "Reserved1"{ type="binary"; loc="8..31"; } } bitfield_MC_CGM_AC7_SS{ "Reserved0"{ type="binary"; loc="0..3"; } "SELSTAT"{ type="binary"; loc="4..7"; ${_DESC987_} } "Reserved1"{ type="binary"; loc="8..31"; } } bitfield_MC_CGM_AC7_DC0{ "DE"{ type="binary"; loc="0"; ${_DESC966_} } "Reserved0"{ type="binary"; loc="1..6"; } "DIV"{ type="binary"; loc="7..15"; ${_DESC989_} } "Reserved1"{ type="binary"; loc="16..31"; } } bitfield_MC_CGM_AC8_SC{ "Reserved0"{ type="binary"; loc="0..3"; } "SELCTL"{ type="binary"; loc="4..7"; ${_DESC991_} } "Reserved1"{ type="binary"; loc="8..31"; } } bitfield_MC_CGM_AC8_SS{ "Reserved0"{ type="binary"; loc="0..3"; } "SELSTAT"{ type="binary"; loc="4..7"; ${_DESC993_} } "Reserved1"{ type="binary"; loc="8..31"; } } bitfield_MC_CGM_AC8_DC0{ "DE"{ type="binary"; loc="0"; ${_DESC966_} } "Reserved0"{ type="binary"; loc="1..9"; } "DIV"{ type="binary"; loc="10..15"; ${_DESC995_} } "Reserved1"{ type="binary"; loc="16..31"; } } bitfield_MC_CGM_AC10_SC{ "Reserved0"{ type="binary"; loc="0..3"; } "SELCTL"{ type="binary"; loc="4..7"; ${_DESC997_} } "Reserved1"{ type="binary"; loc="8..31"; } } bitfield_MC_CGM_AC10_SS{ "Reserved0"{ type="binary"; loc="0..3"; } "SELSTAT"{ type="binary"; loc="4..7"; ${_DESC999_} } "Reserved1"{ type="binary"; loc="8..31"; } } bitfield_MC_CGM_AC10_DC0{ "DE"{ type="binary"; loc="0"; ${_DESC966_} } "Reserved0"{ type="binary"; loc="1..11"; } "DIV"{ type="binary"; loc="12..15"; ${_DESC1001_} } "Reserved1"{ type="binary"; loc="16..31"; } } bitfield_MC_CGM_AC11_SC{ "Reserved0"{ type="binary"; loc="0..3"; } "SELCTL"{ type="binary"; loc="4..7"; ${_DESC1003_} } "Reserved1"{ type="binary"; loc="8..31"; } } bitfield_MC_CGM_AC11_SS{ "Reserved0"{ type="binary"; loc="0..3"; } "SELSTAT"{ type="binary"; loc="4..7"; ${_DESC1005_} } "Reserved1"{ type="binary"; loc="8..31"; } } bitfield_MC_CGM_AC11_DC0{ "DE"{ type="binary"; loc="0"; ${_DESC1007_} } "Reserved0"{ type="binary"; loc="1..2"; } "DIV"{ type="binary"; loc="3..15"; ${_DESC1008_} } "Reserved1"{ type="binary"; loc="16..29"; } "DIV_FMT"{ type="binary"; loc="30..31"; ${_DESC1009_} } } bitfield_MC_CGM_AC11_DC1{ "DE"{ type="binary"; loc="0"; ${_DESC966_} } "Reserved0"{ type="binary"; loc="1..11"; } "DIV"{ type="binary"; loc="12..15"; ${_DESC1011_} } "Reserved1"{ type="binary"; loc="16..31"; } } bitfield_MC_ME_GS{ "S_CURRENT_MODE"{ type="binary"; loc="0..3"; ${_DESC1013_} } "S_MTRANS"{ type="binary"; loc="4"; ${_DESC1014_} } "Reserved0"{ type="binary"; loc="5"; } "Reserved1"{ type="binary"; loc="6..7"; } "S_PDO"{ type="binary"; loc="8"; ${_DESC1015_} } "Reserved2"{ type="binary"; loc="9..10"; } "S_MVR"{ type="binary"; loc="11"; ${_DESC1016_} } "Reserved3"{ type="binary"; loc="12..13"; } "S_FLA"{ type="binary"; loc="14..15"; ${_DESC1017_} } "Reserved4"{ type="binary"; loc="16..24"; } "S_PLL0"{ type="binary"; loc="25"; ${_DESC1018_} } "S_XOSC"{ type="binary"; loc="26"; ${_DESC1019_} } "S_IRC"{ type="binary"; loc="27"; ${_DESC1020_} } "S_SYSCLK"{ type="binary"; loc="28..31"; ${_DESC1021_} } } bitfield_MC_ME_MCTL{ "TARGET_MODE"{ type="binary"; loc="0..3"; ${_DESC1023_} } "Reserved0"{ type="binary"; loc="4..15"; } "KEY"{ type="binary"; loc="16..31"; ${_DESC1024_} } } bitfield_MC_ME_ME{ "Reserved0"{ type="binary"; loc="0..15"; } "RESET_DEST"{ type="binary"; loc="16"; ${_DESC1026_} } "Reserved1"{ type="binary"; loc="17..20"; } "STOP0"{ type="binary"; loc="21"; ${_DESC1027_} } "Reserved2"{ type="binary"; loc="22"; } "HALT0"{ type="binary"; loc="23"; ${_DESC1028_} } "RUN3"{ type="binary"; loc="24"; ${_DESC1029_} } "RUN2"{ type="binary"; loc="25"; ${_DESC1030_} } "RUN1"{ type="binary"; loc="26"; ${_DESC1031_} } "RUN0"{ type="binary"; loc="27"; ${_DESC1032_} } "DRUN"{ type="binary"; loc="28"; ${_DESC1033_} } "SAFE"{ type="binary"; loc="29"; ${_DESC1034_} } "TEST"{ type="binary"; loc="30"; ${_DESC1035_} } "RESET_FUNC"{ type="binary"; loc="31"; ${_DESC1036_} } } bitfield_MC_ME_IS{ "Reserved0"{ type="binary"; loc="0..25"; } "I_ICONF_CC"{ type="binary"; loc="26"; ${_DESC1038_} } "I_ICONF_CU"{ type="binary"; loc="27"; ${_DESC1039_} } "I_ICONF"{ type="binary"; loc="28"; ${_DESC1040_} } "I_IMODE"{ type="binary"; loc="29"; ${_DESC1041_} } "I_SAFE"{ type="binary"; loc="30"; ${_DESC1042_} } "I_MTC"{ type="binary"; loc="31"; ${_DESC1043_} } } bitfield_MC_ME_IM{ "Reserved0"{ type="binary"; loc="0..25"; } "M_ICONF_CC"{ type="binary"; loc="26"; ${_DESC1045_} } "M_ICONF_CU"{ type="binary"; loc="27"; ${_DESC1046_} } "M_ICONF"{ type="binary"; loc="28"; ${_DESC1047_} } "M_IMODE"{ type="binary"; loc="29"; ${_DESC1048_} } "M_SAFE"{ type="binary"; loc="30"; ${_DESC1049_} } "M_MTC"{ type="binary"; loc="31"; ${_DESC1050_} } } bitfield_MC_ME_IMTS{ "Reserved0"{ type="binary"; loc="0..26"; } "S_MTI"{ type="binary"; loc="27"; ${_DESC1052_} } "S_MRI"{ type="binary"; loc="28"; ${_DESC1053_} } "S_DMA"{ type="binary"; loc="29"; ${_DESC1054_} } "S_NMA"{ type="binary"; loc="30"; ${_DESC1055_} } "S_SEA"{ type="binary"; loc="31"; ${_DESC1056_} } } bitfield_MC_ME_DMTS{ "PREVIOUS_MODE"{ type="binary"; loc="0..3"; ${_DESC1058_} } "Reserved0"{ type="binary"; loc="4..7"; } "MPH_BUSY"{ type="binary"; loc="8"; ${_DESC1059_} } "Reserved1"{ type="binary"; loc="9..10"; } "PMC_PROG"{ type="binary"; loc="11"; ${_DESC1060_} } "DBG_MODE"{ type="binary"; loc="12"; ${_DESC1061_} } "CCKL_PROG"{ type="binary"; loc="13"; ${_DESC1062_} } "PCS_PROG"{ type="binary"; loc="14"; ${_DESC1063_} } "SMR"{ type="binary"; loc="15"; ${_DESC1064_} } "Reserved2"{ type="binary"; loc="16"; } "VREG_CSRC_SC"{ type="binary"; loc="17"; ${_DESC1065_} } "CSRC_CSRC_SC"{ type="binary"; loc="18"; ${_DESC1066_} } "IRC_SC"{ type="binary"; loc="19"; ${_DESC1067_} } "SCSRC_SC"{ type="binary"; loc="20"; ${_DESC1068_} } "SYSCLK_SW"{ type="binary"; loc="21"; ${_DESC1069_} } "Reserved3"{ type="binary"; loc="22"; } "FLASH_SC"{ type="binary"; loc="23"; ${_DESC1070_} } "CDP_PRPH_224_255"{ type="binary"; loc="24"; ${_DESC1071_} } "CDP_PRPH_192_223"{ type="binary"; loc="25"; ${_DESC1072_} } "CDP_PRPH_160_191"{ type="binary"; loc="26"; ${_DESC1073_} } "CDP_PRPH_128_159"{ type="binary"; loc="27"; ${_DESC1074_} } "CDP_PRPH_96_127"{ type="binary"; loc="28"; ${_DESC1075_} } "CDP_PRPH_64_95"{ type="binary"; loc="29"; ${_DESC1076_} } "CDP_PRPH_32_63"{ type="binary"; loc="30"; ${_DESC1077_} } "CDP_PRPH_0_31"{ type="binary"; loc="31"; ${_DESC1078_} } } bitfield_MC_ME_RESET_MC{ "Reserved0"{ type="binary"; loc="0"; } "PWRLVL"{ type="binary"; loc="1..3"; ${_DESC1080_} } "Reserved1"{ type="binary"; loc="4..7"; } "PDO"{ type="binary"; loc="8"; ${_DESC1081_} } "Reserved2"{ type="binary"; loc="9..10"; } "MVRON"{ type="binary"; loc="11"; ${_DESC1082_} } "Reserved3"{ type="binary"; loc="12..13"; } "FLAON"{ type="binary"; loc="14..15"; ${_DESC1083_} } "Reserved4"{ type="binary"; loc="16..24"; } "PLL0ON"{ type="binary"; loc="25"; ${_DESC1084_} } "XOSCON"{ type="binary"; loc="26"; ${_DESC1085_} } "IRCON"{ type="binary"; loc="27"; ${_DESC1086_} } "SYSCLK"{ type="binary"; loc="28..31"; ${_DESC1087_} } } bitfield_MC_ME_PS0{ "S_PIT_RTI_1"{ type="binary"; loc="0"; ${_DESC1095_} } "S_PIT_RTI_0"{ type="binary"; loc="1"; ${_DESC1095_} } "S_DECIFILTER"{ type="binary"; loc="2"; ${_DESC1095_} } "Reserved0"{ type="binary"; loc="3..19"; } "S_SIPI_0"{ type="binary"; loc="20"; ${_DESC1095_} } "Reserved1"{ type="binary"; loc="21"; } "S_LFAST_0"{ type="binary"; loc="22"; ${_DESC1095_} } "Reserved2"{ type="binary"; loc="23..31"; } } bitfield_MC_ME_PS1{ "Reserved0"{ type="binary"; loc="0..2"; } "S_ADCSD_0"{ type="binary"; loc="3"; ${_DESC1095_} } "S_ADCSD_2"{ type="binary"; loc="4"; ${_DESC1095_} } "Reserved1"{ type="binary"; loc="5..26"; } "S_DMAMUX_0"{ type="binary"; loc="27"; ${_DESC1095_} } "Reserved2"{ type="binary"; loc="28..31"; } } bitfield_MC_ME_PS2{ "Reserved0"{ type="binary"; loc="0..2"; } "S_LINFlexD_0"{ type="binary"; loc="3"; ${_DESC1095_} } "S_LINFlexD_1"{ type="binary"; loc="4"; ${_DESC1095_} } "Reserved1"{ type="binary"; loc="5..9"; } "S_LINFlexD_14"{ type="binary"; loc="10"; ${_DESC1095_} } "Reserved2"{ type="binary"; loc="11..20"; } "S_CAN_RAM_CTRL"{ type="binary"; loc="21"; ${_DESC1095_} } "S_CCU"{ type="binary"; loc="22"; ${_DESC1095_} } "Reserved3"{ type="binary"; loc="23..24"; } "S_MCAN_1"{ type="binary"; loc="25"; ${_DESC1095_} } "S_MCAN_2"{ type="binary"; loc="26"; ${_DESC1095_} } "Reserved4"{ type="binary"; loc="27..31"; } } bitfield_MC_ME_PS3{ "S_ADCSAR_0"{ type="binary"; loc="0"; ${_DESC1095_} } "Reserved0"{ type="binary"; loc="1..3"; } "S_ADCSAR_4"{ type="binary"; loc="4"; ${_DESC1095_} } "Reserved1"{ type="binary"; loc="5..14"; } "S_ADCSAR_b"{ type="binary"; loc="15"; ${_DESC1095_} } "Reserved2"{ type="binary"; loc="16..22"; } "S_SENT_0"{ type="binary"; loc="23"; ${_DESC1095_} } "Reserved3"{ type="binary"; loc="24..27"; } "S_DSPI_0"{ type="binary"; loc="28"; ${_DESC1095_} } "Reserved4"{ type="binary"; loc="29"; } "S_DSPI_4"{ type="binary"; loc="30"; ${_DESC1095_} } "Reserved5"{ type="binary"; loc="31"; } } bitfield_MC_ME_PS4{ "Reserved0"{ type="binary"; loc="0..30"; } "S_GTMINT"{ type="binary"; loc="31"; ${_DESC1095_} } } bitfield_MC_ME_RUN_PC0{ "Reserved0"{ type="binary"; loc="0..23"; } "RUN3"{ type="binary"; loc="24"; ${_DESC1101_} } "RUN2"{ type="binary"; loc="25"; ${_DESC1102_} } "RUN1"{ type="binary"; loc="26"; ${_DESC1103_} } "RUN0"{ type="binary"; loc="27"; ${_DESC1104_} } "DRUN"{ type="binary"; loc="28"; ${_DESC1105_} } "SAFE"{ type="binary"; loc="29"; ${_DESC1106_} } "TEST"{ type="binary"; loc="30"; ${_DESC1107_} } "RESET"{ type="binary"; loc="31"; ${_DESC1108_} } } bitfield_MC_ME_LP_PC0{ "Reserved0"{ type="binary"; loc="0..20"; } "STOP0"{ type="binary"; loc="21"; ${_DESC1110_} } "Reserved1"{ type="binary"; loc="22"; } "HALT0"{ type="binary"; loc="23"; ${_DESC1111_} } "Reserved2"{ type="binary"; loc="24..31"; } } bitfield_MC_ME_PCTL9{ "Reserved0"{ type="binary"; loc="0"; } "DBG_F"{ type="binary"; loc="1"; ${_DESC1113_} } "LP_CFG"{ type="binary"; loc="2..4"; ${_DESC1114_} } "RUN_CFG"{ type="binary"; loc="5..7"; ${_DESC1115_} } } bitfield_MC_ME_CS{ "Reserved0"{ type="binary"; loc="0..30"; } "S_CORE0"{ type="binary"; loc="31"; ${_DESC1137_} } } bitfield_MC_ME_CCTL0{ "Reserved0"{ type="binary"; loc="0..4"; } "STOP0"{ type="binary"; loc="5"; ${_DESC1139_} } "Reserved1"{ type="binary"; loc="6"; } "HALT0"{ type="binary"; loc="7"; ${_DESC1140_} } "RUN3"{ type="binary"; loc="8"; ${_DESC1141_} } "RUN2"{ type="binary"; loc="9"; ${_DESC1142_} } "RUN1"{ type="binary"; loc="10"; ${_DESC1143_} } "RUN0"{ type="binary"; loc="11"; ${_DESC1144_} } "DRUN"{ type="binary"; loc="12"; ${_DESC1145_} } "SAFE"{ type="binary"; loc="13"; ${_DESC1146_} } "TEST"{ type="binary"; loc="14"; ${_DESC1147_} } "RESET"{ type="binary"; loc="15"; ${_DESC1148_} } } bitfield_MC_ME_CADDR0{ "ADDR"{ type="binary"; loc="0..29"; ${_DESC1150_} } "Reserved0"{ type="binary"; loc="30"; } "RMC"{ type="binary"; loc="31"; ${_DESC1151_} } } bitfield_MC_PCU_PSTAT{ "Reserved0"{ type="binary"; loc="0..30"; } "PD0"{ type="binary"; loc="31"; ${_DESC1153_} } } bitfield_MC_RGM_DES{ "Reserved0"{ type="binary"; loc="0..6"; } "F_VOR_DEST"{ type="binary"; loc="7"; ${_DESC1155_} } "F_TSR_DEST"{ type="binary"; loc="8"; ${_DESC1156_} } "Reserved1"{ type="binary"; loc="9..16"; } "F_SSCM_DEST"{ type="binary"; loc="17"; ${_DESC1157_} } "Reserved2"{ type="binary"; loc="18..20"; } "F_JTAG_DEST"{ type="binary"; loc="21"; ${_DESC1158_} } "Reserved3"{ type="binary"; loc="22"; } "F_EDR"{ type="binary"; loc="23"; ${_DESC1159_} } "Reserved4"{ type="binary"; loc="24..27"; } "F_SOFT_DEST"{ type="binary"; loc="28"; ${_DESC1160_} } "Reserved5"{ type="binary"; loc="29"; } "F_PORST"{ type="binary"; loc="30"; ${_DESC1161_} } "F_POR"{ type="binary"; loc="31"; ${_DESC1162_} } } bitfield_MC_RGM_DERD{ "Reserved0"{ type="binary"; loc="0..7"; } "D_TSR_DEST"{ type="binary"; loc="8"; ${_DESC1164_} } "Reserved1"{ type="binary"; loc="9..29"; } "D_PORST"{ type="binary"; loc="30"; ${_DESC1165_} } "Reserved2"{ type="binary"; loc="31"; } } bitfield_MC_RGM_DEAR{ "Reserved0"{ type="binary"; loc="0..7"; } "AR_TSR_DEST"{ type="binary"; loc="8"; ${_DESC1167_} } "Reserved1"{ type="binary"; loc="9..29"; } "AR_PORST"{ type="binary"; loc="30"; ${_DESC1168_} } "Reserved2"{ type="binary"; loc="31"; } } bitfield_MC_RGM_DBRE{ "Reserved0"{ type="binary"; loc="0..6"; } "BE_VOR_DEST"{ type="binary"; loc="7"; ${_DESC1170_} } "BE_TSR_DEST"{ type="binary"; loc="8"; ${_DESC1171_} } "Reserved1"{ type="binary"; loc="9..16"; } "BE_SSCM_DEST"{ type="binary"; loc="17"; ${_DESC1172_} } "Reserved2"{ type="binary"; loc="18..20"; } "BE_JTAG_DEST"{ type="binary"; loc="21"; ${_DESC1173_} } "Reserved3"{ type="binary"; loc="22"; } "BE_EDR"{ type="binary"; loc="23"; ${_DESC1174_} } "Reserved4"{ type="binary"; loc="24..27"; } "BE_SOFT_DEST"{ type="binary"; loc="28"; ${_DESC1175_} } "Reserved5"{ type="binary"; loc="29"; } "BE_PORST"{ type="binary"; loc="30"; ${_DESC1176_} } "BE_POR"{ type="binary"; loc="31"; ${_DESC1177_} } } bitfield_MC_RGM_FES{ "Reserved0"{ type="binary"; loc="0..5"; } "F_FLASH"{ type="binary"; loc="6"; ${_DESC1179_} } "F_VOR_FUNC"{ type="binary"; loc="7"; ${_DESC1180_} } "F_TSR_FUNC"{ type="binary"; loc="8"; ${_DESC1181_} } "Reserved1"{ type="binary"; loc="9..14"; } "F_PLL0"{ type="binary"; loc="15"; ${_DESC1182_} } "Reserved2"{ type="binary"; loc="16..17"; } "F_CMU_FHL0"{ type="binary"; loc="18"; ${_DESC1183_} } "F_CMU_OLR"{ type="binary"; loc="19"; ${_DESC1184_} } "F_CORE"{ type="binary"; loc="20"; ${_DESC1185_} } "F_JTAG_FUNC"{ type="binary"; loc="21"; ${_DESC1186_} } "F_CWD"{ type="binary"; loc="22"; ${_DESC1187_} } "F_SWT"{ type="binary"; loc="23"; ${_DESC1188_} } "Reserved3"{ type="binary"; loc="24..27"; } "F_SOFT_FUNC"{ type="binary"; loc="28"; ${_DESC1189_} } "Reserved4"{ type="binary"; loc="29"; } "F_ESR1"{ type="binary"; loc="30"; ${_DESC1190_} } "F_ESR0"{ type="binary"; loc="31"; ${_DESC1191_} } } bitfield_MC_RGM_FERD{ "Reserved0"{ type="binary"; loc="0..5"; } "D_FLASH"{ type="binary"; loc="6"; ${_DESC1193_} } "D_VOR_FUNC"{ type="binary"; loc="7"; ${_DESC1194_} } "D_TSR_FUNC"{ type="binary"; loc="8"; ${_DESC1195_} } "Reserved1"{ type="binary"; loc="9..14"; } "D_PLL0"{ type="binary"; loc="15"; ${_DESC1196_} } "Reserved2"{ type="binary"; loc="16..17"; } "D_CMU_FHL0"{ type="binary"; loc="18"; ${_DESC1197_} } "D_CMU_OLR"{ type="binary"; loc="19"; ${_DESC1198_} } "D_CORE"{ type="binary"; loc="20"; ${_DESC1199_} } "Reserved3"{ type="binary"; loc="21"; } "D_SWT"{ type="binary"; loc="22"; ${_DESC1200_} } "D_CWD"{ type="binary"; loc="23"; ${_DESC1201_} } "Reserved4"{ type="binary"; loc="24..29"; } "D_ESR1"{ type="binary"; loc="30"; ${_DESC1202_} } "Reserved5"{ type="binary"; loc="31"; } } bitfield_MC_RGM_FEAR{ "Reserved0"{ type="binary"; loc="0..5"; } "AR_FLASH"{ type="binary"; loc="6"; ${_DESC1204_} } "AR_VOR_FUNC"{ type="binary"; loc="7"; ${_DESC1205_} } "AR_TSR_FUNC"{ type="binary"; loc="8"; ${_DESC1206_} } "Reserved1"{ type="binary"; loc="9..14"; } "AR_PLL0"{ type="binary"; loc="15"; ${_DESC1207_} } "Reserved2"{ type="binary"; loc="16..17"; } "AR_CMU_FHL0"{ type="binary"; loc="18"; ${_DESC1208_} } "AR_CMU_OLR"{ type="binary"; loc="19"; ${_DESC1209_} } "AR_CORE"{ type="binary"; loc="20"; ${_DESC1210_} } "Reserved3"{ type="binary"; loc="21"; } "AR_CWD"{ type="binary"; loc="22"; ${_DESC1211_} } "AR_SWT"{ type="binary"; loc="23"; ${_DESC1212_} } "Reserved4"{ type="binary"; loc="24..29"; } "AR_ESR1"{ type="binary"; loc="30"; ${_DESC1213_} } "Reserved5"{ type="binary"; loc="31"; } } bitfield_MC_RGM_FBRE{ "Reserved0"{ type="binary"; loc="0..5"; } "BE_FLASH"{ type="binary"; loc="6"; ${_DESC1215_} } "BE_VOR_FUNC"{ type="binary"; loc="7"; ${_DESC1216_} } "BE_TSR_FUNC"{ type="binary"; loc="8"; ${_DESC1217_} } "Reserved1"{ type="binary"; loc="9..14"; } "BE_PLL0"{ type="binary"; loc="15"; ${_DESC1218_} } "Reserved2"{ type="binary"; loc="16..17"; } "BE_CMU_FHL0"{ type="binary"; loc="18"; ${_DESC1219_} } "BE_CMU_OLR"{ type="binary"; loc="19"; ${_DESC1220_} } "BE_CORE"{ type="binary"; loc="20"; ${_DESC1221_} } "BE_JTAG_FUNC"{ type="binary"; loc="21"; ${_DESC1222_} } "BE_CWD"{ type="binary"; loc="22"; ${_DESC1223_} } "BE_SWT"{ type="binary"; loc="23"; ${_DESC1224_} } "Reserved3"{ type="binary"; loc="24..27"; } "BE_SOFT_FUNC"{ type="binary"; loc="28"; ${_DESC1225_} } "Reserved4"{ type="binary"; loc="29"; } "BE_ESR1"{ type="binary"; loc="30"; ${_DESC1226_} } "BE_ESR0"{ type="binary"; loc="31"; ${_DESC1227_} } } bitfield_MC_RGM_FESS{ "Reserved0"{ type="binary"; loc="0..5"; } "SS_FLASH"{ type="binary"; loc="6"; ${_DESC1229_} } "SS_VOR_FUNC"{ type="binary"; loc="7"; ${_DESC1230_} } "SS_TSR_FUNC"{ type="binary"; loc="8"; ${_DESC1231_} } "Reserved1"{ type="binary"; loc="9..14"; } "SS_PLL0"{ type="binary"; loc="15"; ${_DESC1232_} } "Reserved2"{ type="binary"; loc="16..17"; } "SS_CMU_FHL0"{ type="binary"; loc="18"; ${_DESC1233_} } "SS_CMU_OLR"{ type="binary"; loc="19"; ${_DESC1234_} } "SS_CORE"{ type="binary"; loc="20"; ${_DESC1235_} } "SS_JTAG_FUNC"{ type="binary"; loc="21"; ${_DESC1236_} } "SS_CWD"{ type="binary"; loc="22"; ${_DESC1237_} } "SS_SWT"{ type="binary"; loc="23"; ${_DESC1238_} } "Reserved3"{ type="binary"; loc="24..27"; } "SS_SOFT_FUNC"{ type="binary"; loc="28"; ${_DESC1239_} } "Reserved4"{ type="binary"; loc="29"; } "SS_ESR1"{ type="binary"; loc="30"; ${_DESC1240_} } "SS_ESR0"{ type="binary"; loc="31"; ${_DESC1241_} } } bitfield_MC_RGM_FRET{ "Reserved0"{ type="binary"; loc="0..3"; } "FRET"{ type="binary"; loc="4..7"; ${_DESC1243_} } } bitfield_MC_RGM_DRET{ "Reserved0"{ type="binary"; loc="0..3"; } "DRET"{ type="binary"; loc="4..7"; ${_DESC1245_} } } bitfield_MC_RGM_EROEC{ "Reserved0"{ type="binary"; loc="0..5"; } "ERIS"{ type="binary"; loc="6"; ${_DESC1247_} } "EROEC"{ type="binary"; loc="7"; ${_DESC1248_} } } bitfield_MC_RGM_PRST0{ "PIT_RTC_1_RST"{ type="binary"; loc="0"; ${_DESC1250_} } "PIT_RTC_0_RST"{ type="binary"; loc="1"; ${_DESC1250_} } "DECFILTER_RST"{ type="binary"; loc="2"; ${_DESC1250_} } "Reserved0"{ type="binary"; loc="3..15"; } "SIUL_RST"{ type="binary"; loc="16"; ${_DESC1250_} } "Reserved1"{ type="binary"; loc="17..19"; } "SIPI_0_RST"{ type="binary"; loc="20"; ${_DESC1250_} } "Reserved2"{ type="binary"; loc="21"; } "LFAST_0_RST"{ type="binary"; loc="22"; ${_DESC1250_} } "Reserved3"{ type="binary"; loc="23..31"; } } bitfield_MC_RGM_PRST1{ "Reserved0"{ type="binary"; loc="0..3"; } "ADCSD_2_RST"{ type="binary"; loc="4"; ${_DESC1250_} } "Reserved1"{ type="binary"; loc="5..26"; } "DMAMUX_0_RST"{ type="binary"; loc="27"; ${_DESC1250_} } "Reserved2"{ type="binary"; loc="28..31"; } } bitfield_MC_RGM_PRST2{ "Reserved0"{ type="binary"; loc="0..2"; } "LINFlexD_0_RST"{ type="binary"; loc="3"; ${_DESC1250_} } "LINFlexD_1_RST"{ type="binary"; loc="4"; ${_DESC1250_} } "Reserved1"{ type="binary"; loc="5..9"; } "LINFlexD_14_RST"{ type="binary"; loc="10"; ${_DESC1250_} } "Reserved2"{ type="binary"; loc="11..20"; } "CAN_RAM_CTR_RST"{ type="binary"; loc="21"; ${_DESC1250_} } "CCCU_RST"{ type="binary"; loc="22"; ${_DESC1250_} } "Reserved3"{ type="binary"; loc="23..24"; } "MCAN_1_RST"{ type="binary"; loc="25"; ${_DESC1250_} } "MCAN_2_RST"{ type="binary"; loc="26"; ${_DESC1250_} } "Reserved4"{ type="binary"; loc="27..31"; } } bitfield_MC_RGM_PRST3{ "ADCSAR_0_RST"{ type="binary"; loc="0"; ${_DESC1250_} } "Reserved0"{ type="binary"; loc="1..3"; } "ADCSAR_4_RST"{ type="binary"; loc="4"; ${_DESC1250_} } "Reserved1"{ type="binary"; loc="5..14"; } "ADCSAR_b_RST"{ type="binary"; loc="15"; ${_DESC1250_} } "Reserved2"{ type="binary"; loc="16..22"; } "SENT_0_RST"{ type="binary"; loc="23"; ${_DESC1250_} } "Reserved3"{ type="binary"; loc="24..27"; } "DSPI_0_RST"{ type="binary"; loc="28"; ${_DESC1250_} } "Reserved4"{ type="binary"; loc="29"; } "DSPI_4_RST"{ type="binary"; loc="30"; ${_DESC1250_} } "Reserved5"{ type="binary"; loc="31"; } } bitfield_MC_RGM_PRST4{ "Reserved0"{ type="binary"; loc="0..30"; } "GTMINT_RST"{ type="binary"; loc="31"; ${_DESC1250_} } } bitfield_MP55_MCR{ "Reserved0"{ type="binary"; loc="0..15"; } "EER"{ type="binary"; loc="16"; ${_DESC1256_} } "RWE"{ type="binary"; loc="17"; ${_DESC1257_} } "SBC"{ type="binary"; loc="18"; ${_DESC1258_} } "Reserved1"{ type="binary"; loc="19"; } "PEAS"{ type="binary"; loc="20"; ${_DESC1259_} } "DONE"{ type="binary"; loc="21"; ${_DESC1260_} } "PEG"{ type="binary"; loc="22"; ${_DESC1261_} } "PECIE"{ type="binary"; loc="23"; ${_DESC1262_} } "FERS"{ type="binary"; loc="24"; ${_DESC1263_} } "Reserved2"{ type="binary"; loc="25..26"; } "PGM"{ type="binary"; loc="27"; ${_DESC1264_} } "PSUS"{ type="binary"; loc="28"; ${_DESC1265_} } "ERS"{ type="binary"; loc="29"; ${_DESC1266_} } "ESUS"{ type="binary"; loc="30"; ${_DESC1267_} } "EHV"{ type="binary"; loc="31"; ${_DESC1268_} } } bitfield_MP55_MCRE{ "Reserved0"{ type="binary"; loc="0"; } "n8Kh"{ type="binary"; loc="1..2"; ${_DESC1270_} } "n256K"{ type="binary"; loc="3..7"; ${_DESC1271_} } "n64Kh"{ type="binary"; loc="8..10"; ${_DESC1272_} } "n32Kh"{ type="binary"; loc="11..12"; ${_DESC1273_} } "n16Kh"{ type="binary"; loc="13..15"; ${_DESC1274_} } "n64Km"{ type="binary"; loc="16..18"; ${_DESC1275_} } "n32Km"{ type="binary"; loc="19..20"; ${_DESC1276_} } "n16Km"{ type="binary"; loc="21..23"; ${_DESC1277_} } "n64Kl"{ type="binary"; loc="24..26"; ${_DESC1278_} } "n32Kl"{ type="binary"; loc="27..28"; ${_DESC1279_} } "n16Kl"{ type="binary"; loc="29..31"; ${_DESC1280_} } } bitfield_MP55_LOCK0{ "TSLOCK"{ type="binary"; loc="0"; ${_DESC1282_} } "Reserved0"{ type="binary"; loc="1"; } "LLK"{ type="binary"; loc="2..15"; ${_DESC1283_} } "MLK"{ type="binary"; loc="16..31"; ${_DESC1284_} } } bitfield_MP55_LOCK1{ "Reserved0"{ type="binary"; loc="0..15"; } "HLK"{ type="binary"; loc="16..31"; ${_DESC1286_} } } bitfield_MP55_LOCK2{ "Reserved0"{ type="binary"; loc="0"; } "A256KLK"{ type="binary"; loc="1..31"; ${_DESC1288_} } } bitfield_MP55_SEL0{ "Reserved0"{ type="binary"; loc="0..1"; } "LSL"{ type="binary"; loc="2..15"; ${_DESC1290_} } "MSL"{ type="binary"; loc="16..31"; ${_DESC1291_} } } bitfield_MP55_SEL1{ "Reserved0"{ type="binary"; loc="0..15"; } "HSL"{ type="binary"; loc="16..31"; ${_DESC1293_} } } bitfield_MP55_SEL2{ "Reserved0"{ type="binary"; loc="0"; } "A256KSL"{ type="binary"; loc="1..31"; ${_DESC1295_} } } bitfield_MP55_ADR{ "SAD"{ type="binary"; loc="0"; ${_DESC1297_} } "Reserved0"{ type="binary"; loc="1..7"; } "AD"{ type="binary"; loc="8..28"; ${_DESC1298_} } "Reserved1"{ type="binary"; loc="29..31"; } } bitfield_MP55_UT0{ "UTE"{ type="binary"; loc="0"; ${_DESC1300_} } "SBCE"{ type="binary"; loc="1"; ${_DESC1301_} } "Reserved0"{ type="binary"; loc="2..21"; } "NAIBP"{ type="binary"; loc="22"; ${_DESC1302_} } "AIBPE"{ type="binary"; loc="23"; ${_DESC1303_} } "Reserved1"{ type="binary"; loc="24"; } "AISUS"{ type="binary"; loc="25"; ${_DESC1304_} } "MRE"{ type="binary"; loc="26"; ${_DESC1305_} } "MRV"{ type="binary"; loc="27"; ${_DESC1306_} } "Reserved2"{ type="binary"; loc="28"; } "AIS"{ type="binary"; loc="29"; ${_DESC1307_} } "AIE"{ type="binary"; loc="30"; ${_DESC1308_} } "AID"{ type="binary"; loc="31"; ${_DESC1309_} } } bitfield_MP55_UMISR0{ "MS0"{ type="binary"; loc="0..31"; ${_DESC1311_} } } bitfield_MP55_UMISR1{ "MS1"{ type="binary"; loc="0..31"; ${_DESC1313_} } } bitfield_MP55_UMISR2{ "MS2"{ type="binary"; loc="0..31"; ${_DESC1315_} } } bitfield_MP55_UMISR3{ "MS3"{ type="binary"; loc="0..31"; ${_DESC1317_} } } bitfield_MP55_UMISR8{ "MS8"{ type="binary"; loc="0..31"; ${_DESC1319_} } } bitfield_MP55_UMISR9{ "MS9"{ type="binary"; loc="0..31"; ${_DESC1321_} } } bitfield_MP55_OPP0{ "Reserved0"{ type="binary"; loc="0..1"; } "LOPP"{ type="binary"; loc="2..15"; ${_DESC1323_} } "MOPP"{ type="binary"; loc="16..31"; ${_DESC1324_} } } bitfield_MP55_OPP1{ "Reserved0"{ type="binary"; loc="0..15"; } "HOPP"{ type="binary"; loc="16..31"; ${_DESC1326_} } } bitfield_MP55_OPP2{ "Reserved0"{ type="binary"; loc="0"; } "A256OPP"{ type="binary"; loc="1..31"; ${_DESC1328_} } } bitfield_MP55_TDMPC{ "TDMPC"{ type="binary"; loc="0..31"; ${_DESC1330_} } } bitfield_M_CAN_1_CREL{ "REL"{ type="binary"; loc="0..3"; ${_DESC1332_} } "STEP"{ type="binary"; loc="4..7"; ${_DESC1333_} } "SUBSTEP"{ type="binary"; loc="8..11"; ${_DESC1334_} } "YEAR"{ type="binary"; loc="12..15"; ${_DESC1335_} } "MON"{ type="binary"; loc="16..23"; ${_DESC1336_} } "DAY"{ type="binary"; loc="24..31"; ${_DESC1337_} } } bitfield_M_CAN_1_ENDN{ "ETV"{ type="binary"; loc="0..31"; ${_DESC1339_} } } bitfield_M_CAN_1_FBTP{ "TDCO"{ type="binary"; loc="0..2"; ${_DESC1341_} } "TDC"{ type="binary"; loc="3"; } "Reserved0"{ type="binary"; loc="4"; } "FBRP"{ type="binary"; loc="5..16"; ${_DESC1342_} } "Reserved1"{ type="binary"; loc="17..19"; } "FTSEG1"{ type="binary"; loc="20..23"; ${_DESC1343_} } "Reserved2"{ type="binary"; loc="24"; } "FTSEG2"{ type="binary"; loc="25..27"; ${_DESC1344_} } "Reserved3"{ type="binary"; loc="28..29"; } "FSJW"{ type="binary"; loc="30..31"; ${_DESC1345_} } } bitfield_M_CAN_1_TEST{ "Reserved0"{ type="binary"; loc="0..18"; } "TDCV"{ type="binary"; loc="19..23"; ${_DESC1347_} } "RX"{ type="binary"; loc="24"; ${_DESC1348_} } "TX"{ type="binary"; loc="25..26"; ${_DESC1349_} } "LBCK"{ type="binary"; loc="27"; ${_DESC1350_} } "Reserved1"{ type="binary"; loc="28..31"; } } bitfield_M_CAN_1_RWD{ "Reserved0"{ type="binary"; loc="0..15"; } "WDV"{ type="binary"; loc="16..23"; ${_DESC1352_} } "WDC"{ type="binary"; loc="24..31"; ${_DESC1353_} } } bitfield_M_CAN_1_CCCR{ "Reserved0"{ type="binary"; loc="0..15"; } "LONG"{ type="binary"; loc="16"; } "FAST"{ type="binary"; loc="17"; } "LACT"{ type="binary"; loc="18"; } "FACT"{ type="binary"; loc="19"; } "CLRL"{ type="binary"; loc="20"; } "SETL"{ type="binary"; loc="21"; } "CLRF"{ type="binary"; loc="22"; } "SETF"{ type="binary"; loc="23"; } "TEST"{ type="binary"; loc="24"; ${_DESC1355_} } "DAR"{ type="binary"; loc="25"; ${_DESC1356_} } "MON"{ type="binary"; loc="26"; ${_DESC1357_} } "CSR"{ type="binary"; loc="27"; ${_DESC1358_} } "CSA"{ type="binary"; loc="28"; ${_DESC1359_} } "ASM"{ type="binary"; loc="29"; ${_DESC1360_} } "CCE"{ type="binary"; loc="30"; ${_DESC1361_} } "INIT"{ type="binary"; loc="31"; ${_DESC1362_} } } bitfield_M_CAN_1_BTP{ "Reserved0"{ type="binary"; loc="0..5"; } "BRP"{ type="binary"; loc="6..15"; ${_DESC1364_} } "Reserved1"{ type="binary"; loc="16..17"; } "TSEG1"{ type="binary"; loc="18..23"; ${_DESC1365_} } "TSEG2"{ type="binary"; loc="24..27"; ${_DESC1366_} } "SJW"{ type="binary"; loc="28..31"; ${_DESC1367_} } } bitfield_M_CAN_1_TSCC{ "Reserved0"{ type="binary"; loc="0..11"; } "TCP"{ type="binary"; loc="12..15"; ${_DESC1369_} } "Reserved1"{ type="binary"; loc="16..29"; } "TSS"{ type="binary"; loc="30..31"; ${_DESC1370_} } } bitfield_M_CAN_1_TSCV{ "Reserved0"{ type="binary"; loc="0..15"; } "TSC"{ type="binary"; loc="16..31"; ${_DESC1372_} } } bitfield_M_CAN_1_TOCC{ "TOP"{ type="binary"; loc="0..15"; ${_DESC1374_} } "Reserved0"{ type="binary"; loc="16..28"; } "TOS"{ type="binary"; loc="29..30"; ${_DESC1375_} } "ETOC"{ type="binary"; loc="31"; ${_DESC1376_} } } bitfield_M_CAN_1_TOCV{ "Reserved0"{ type="binary"; loc="0..15"; } "TOC"{ type="binary"; loc="16..31"; ${_DESC1378_} } } bitfield_M_CAN_1_ECR{ "Reserved0"{ type="binary"; loc="0..7"; } "CEL"{ type="binary"; loc="8..15"; ${_DESC1380_} } "RP"{ type="binary"; loc="16"; ${_DESC1381_} } "REC"{ type="binary"; loc="17..23"; ${_DESC1382_} } "TEC"{ type="binary"; loc="24..31"; ${_DESC1383_} } } bitfield_M_CAN_1_PSR{ "Reserved0"{ type="binary"; loc="0..17"; } "REDL"{ type="binary"; loc="18"; ${_DESC1385_} } "RBRS"{ type="binary"; loc="19"; ${_DESC1386_} } "RESI"{ type="binary"; loc="20"; ${_DESC1386_} } "FLEC"{ type="binary"; loc="21..23"; ${_DESC1387_} } "BO"{ type="binary"; loc="24"; ${_DESC1388_} } "EW"{ type="binary"; loc="25"; ${_DESC1389_} } "EP"{ type="binary"; loc="26"; ${_DESC1390_} } "ACT"{ type="binary"; loc="27..28"; ${_DESC1391_} } "LEC"{ type="binary"; loc="29..31"; ${_DESC1392_} } } bitfield_M_CAN_1_IR{ "STE"{ type="binary"; loc="0"; ${_DESC1394_} } "FOE"{ type="binary"; loc="1"; ${_DESC1395_} } "ACKE"{ type="binary"; loc="2"; ${_DESC1396_} } "BE"{ type="binary"; loc="3"; ${_DESC1397_} } "CRCE"{ type="binary"; loc="4"; ${_DESC1398_} } "WDI"{ type="binary"; loc="5"; ${_DESC1399_} } "BO"{ type="binary"; loc="6"; ${_DESC1388_} } "EW"{ type="binary"; loc="7"; ${_DESC1389_} } "EP"{ type="binary"; loc="8"; ${_DESC1390_} } "ELO"{ type="binary"; loc="9"; ${_DESC1400_} } "BEU"{ type="binary"; loc="10"; ${_DESC1401_} } "BEC"{ type="binary"; loc="11"; ${_DESC1402_} } "DRX"{ type="binary"; loc="12"; ${_DESC1403_} } "TOO"{ type="binary"; loc="13"; ${_DESC1404_} } "UMD"{ type="binary"; loc="14"; ${_DESC1405_} } "TSW"{ type="binary"; loc="15"; ${_DESC1406_} } "TEFL"{ type="binary"; loc="16"; ${_DESC1407_} } "TEFF"{ type="binary"; loc="17"; ${_DESC1408_} } "TEFW"{ type="binary"; loc="18"; ${_DESC1409_} } "TEFN"{ type="binary"; loc="19"; ${_DESC1410_} } "TFE"{ type="binary"; loc="20"; ${_DESC1411_} } "TCF"{ type="binary"; loc="21"; ${_DESC1412_} } "TC"{ type="binary"; loc="22"; ${_DESC1413_} } "HPM"{ type="binary"; loc="23"; ${_DESC1414_} } "RF1L"{ type="binary"; loc="24"; ${_DESC1415_} } "RF1F"{ type="binary"; loc="25"; ${_DESC1416_} } "RF1W"{ type="binary"; loc="26"; ${_DESC1417_} } "RF1N"{ type="binary"; loc="27"; ${_DESC1418_} } "RF0L"{ type="binary"; loc="28"; ${_DESC1419_} } "RF0F"{ type="binary"; loc="29"; ${_DESC1420_} } "RF0W"{ type="binary"; loc="30"; ${_DESC1421_} } "RF0N"{ type="binary"; loc="31"; ${_DESC1422_} } } bitfield_M_CAN_1_IE{ "STEE"{ type="binary"; loc="0"; ${_DESC1424_} } "FOEE"{ type="binary"; loc="1"; ${_DESC1425_} } "ACKEE"{ type="binary"; loc="2"; ${_DESC1426_} } "BEE"{ type="binary"; loc="3"; ${_DESC793_} } "CRCEE"{ type="binary"; loc="4"; ${_DESC1427_} } "WDIE"{ type="binary"; loc="5"; ${_DESC1428_} } "BOE"{ type="binary"; loc="6"; ${_DESC1429_} } "EWE"{ type="binary"; loc="7"; ${_DESC1430_} } "EPE"{ type="binary"; loc="8"; ${_DESC1431_} } "ELOE"{ type="binary"; loc="9"; ${_DESC1432_} } "BEUE"{ type="binary"; loc="10"; ${_DESC1433_} } "BECE"{ type="binary"; loc="11"; ${_DESC1434_} } "DRXE"{ type="binary"; loc="12"; } "TOOE"{ type="binary"; loc="13"; ${_DESC1435_} } "UMDE"{ type="binary"; loc="14"; ${_DESC1436_} } "TSWE"{ type="binary"; loc="15"; ${_DESC1437_} } "TEFLE"{ type="binary"; loc="16"; ${_DESC1438_} } "TEFFE"{ type="binary"; loc="17"; ${_DESC1439_} } "TEFWE"{ type="binary"; loc="18"; ${_DESC1440_} } "TEFNE"{ type="binary"; loc="19"; ${_DESC1441_} } "TFEE"{ type="binary"; loc="20"; ${_DESC1442_} } "TCFE"{ type="binary"; loc="21"; ${_DESC1443_} } "TCE"{ type="binary"; loc="22"; ${_DESC1444_} } "HPME"{ type="binary"; loc="23"; ${_DESC1445_} } "RF1LE"{ type="binary"; loc="24"; ${_DESC1446_} } "RF1FE"{ type="binary"; loc="25"; ${_DESC1447_} } "RF1WE"{ type="binary"; loc="26"; ${_DESC1448_} } "RF1NE"{ type="binary"; loc="27"; ${_DESC1449_} } "RF0LE"{ type="binary"; loc="28"; ${_DESC1450_} } "RF0FE"{ type="binary"; loc="29"; ${_DESC1451_} } "RF0WE"{ type="binary"; loc="30"; ${_DESC1452_} } "RF0NE"{ type="binary"; loc="31"; ${_DESC1453_} } } bitfield_M_CAN_1_ILS{ "STEL"{ type="binary"; loc="0"; ${_DESC1455_} } "FOEL"{ type="binary"; loc="1"; ${_DESC1456_} } "ACKEL"{ type="binary"; loc="2"; ${_DESC1457_} } "BEL"{ type="binary"; loc="3"; ${_DESC1458_} } "CRCEL"{ type="binary"; loc="4"; ${_DESC1459_} } "WDIL"{ type="binary"; loc="5"; ${_DESC1460_} } "BOL"{ type="binary"; loc="6"; ${_DESC1461_} } "EWL"{ type="binary"; loc="7"; ${_DESC1462_} } "EPL"{ type="binary"; loc="8"; ${_DESC1463_} } "ELOL"{ type="binary"; loc="9"; ${_DESC1464_} } "BEUL"{ type="binary"; loc="10"; ${_DESC1465_} } "BECL"{ type="binary"; loc="11"; ${_DESC1466_} } "DRXL"{ type="binary"; loc="12"; } "TOOL"{ type="binary"; loc="13"; ${_DESC1467_} } "UMDL"{ type="binary"; loc="14"; ${_DESC1468_} } "TSWL"{ type="binary"; loc="15"; ${_DESC1469_} } "TEFLL"{ type="binary"; loc="16"; ${_DESC1470_} } "TEFFL"{ type="binary"; loc="17"; ${_DESC1471_} } "TEFWL"{ type="binary"; loc="18"; ${_DESC1472_} } "TEFNL"{ type="binary"; loc="19"; ${_DESC1473_} } "TFEL"{ type="binary"; loc="20"; ${_DESC1474_} } "TCFL"{ type="binary"; loc="21"; ${_DESC1475_} } "TCL"{ type="binary"; loc="22"; ${_DESC1476_} } "HPML"{ type="binary"; loc="23"; ${_DESC1477_} } "RF1LL"{ type="binary"; loc="24"; ${_DESC1478_} } "RF1FL"{ type="binary"; loc="25"; ${_DESC1479_} } "RF1WL"{ type="binary"; loc="26"; ${_DESC1480_} } "RF1NL"{ type="binary"; loc="27"; ${_DESC1481_} } "RF0LL"{ type="binary"; loc="28"; ${_DESC1482_} } "RF0FL"{ type="binary"; loc="29"; ${_DESC1483_} } "RF0WL"{ type="binary"; loc="30"; ${_DESC1484_} } "RF0NL"{ type="binary"; loc="31"; ${_DESC1485_} } } bitfield_M_CAN_1_ILE{ "Reserved0"{ type="binary"; loc="0..29"; } "EINT1"{ type="binary"; loc="30"; ${_DESC1487_} } "EINT0"{ type="binary"; loc="31"; ${_DESC1488_} } } bitfield_M_CAN_1_GFC{ "Reserved0"{ type="binary"; loc="0..25"; } "ANFS"{ type="binary"; loc="26..27"; ${_DESC1490_} } "ANFE"{ type="binary"; loc="28..29"; ${_DESC1491_} } "RRFS"{ type="binary"; loc="30"; ${_DESC1492_} } "RRFE"{ type="binary"; loc="31"; ${_DESC1493_} } } bitfield_M_CAN_1_SIDFC{ "Reserved0"{ type="binary"; loc="0..7"; } "LSS"{ type="binary"; loc="8..15"; ${_DESC1495_} } "FLSSA"{ type="binary"; loc="16..29"; ${_DESC1496_} } "Reserved1"{ type="binary"; loc="30..31"; } } bitfield_M_CAN_1_XIDFC{ "Reserved0"{ type="binary"; loc="0..8"; } "LSE"{ type="binary"; loc="9..15"; ${_DESC1498_} } "FLESA"{ type="binary"; loc="16..29"; ${_DESC1499_} } "Reserved1"{ type="binary"; loc="30..31"; } } bitfield_M_CAN_1_XIDAM{ "Reserved0"{ type="binary"; loc="0..2"; } "EIDM"{ type="binary"; loc="3..31"; ${_DESC1501_} } } bitfield_M_CAN_1_HPMS{ "Reserved0"{ type="binary"; loc="0..15"; } "FLST"{ type="binary"; loc="16"; ${_DESC1503_} } "FIDX"{ type="binary"; loc="17..23"; ${_DESC1504_} } "MSI"{ type="binary"; loc="24..25"; ${_DESC1505_} } "BIDX"{ type="binary"; loc="26..31"; ${_DESC1506_} } } bitfield_M_CAN_1_NDAT1{ "ND1"{ type="binary"; loc="0..31"; ${_DESC1508_} } } bitfield_M_CAN_1_NDAT2{ "ND2"{ type="binary"; loc="0..31"; ${_DESC1510_} } } bitfield_M_CAN_1_RXF0C{ "Reserved0"{ type="binary"; loc="0"; } "F0WM"{ type="binary"; loc="1..7"; ${_DESC1512_} } "Reserved1"{ type="binary"; loc="8..9"; } "F0S"{ type="binary"; loc="10..15"; ${_DESC1513_} } "F0SA"{ type="binary"; loc="16..29"; ${_DESC1514_} } "Reserved2"{ type="binary"; loc="30..31"; } } bitfield_M_CAN_1_RXF0S{ "Reserved0"{ type="binary"; loc="0..5"; } "RF0L"{ type="binary"; loc="6"; ${_DESC1516_} } "F0F"{ type="binary"; loc="7"; ${_DESC1420_} } "Reserved1"{ type="binary"; loc="8..9"; } "F0PI"{ type="binary"; loc="10..15"; ${_DESC1517_} } "Reserved2"{ type="binary"; loc="16..17"; } "F0GI"{ type="binary"; loc="18..23"; ${_DESC1518_} } "Reserved3"{ type="binary"; loc="24"; } "F0FL"{ type="binary"; loc="25..31"; ${_DESC1519_} } } bitfield_M_CAN_1_RXF0A{ "Reserved0"{ type="binary"; loc="0..25"; } "F0AI"{ type="binary"; loc="26..31"; ${_DESC1521_} } } bitfield_M_CAN_1_RXBC{ "Reserved0"{ type="binary"; loc="0..15"; } "RBSA"{ type="binary"; loc="16..29"; ${_DESC1523_} } "Reserved1"{ type="binary"; loc="30..31"; } } bitfield_M_CAN_1_RXF1C{ "Reserved0"{ type="binary"; loc="0"; } "F1WM"{ type="binary"; loc="1..7"; ${_DESC1525_} } "Reserved1"{ type="binary"; loc="8"; } "F1S"{ type="binary"; loc="9..15"; ${_DESC1526_} } "F1SA"{ type="binary"; loc="16..29"; ${_DESC1527_} } "Reserved2"{ type="binary"; loc="30..31"; } } bitfield_M_CAN_1_RXF1S{ "DMS"{ type="binary"; loc="0..1"; ${_DESC1529_} } "Reserved0"{ type="binary"; loc="2..5"; } "RF1L"{ type="binary"; loc="6"; ${_DESC1530_} } "F1F"{ type="binary"; loc="7"; ${_DESC1416_} } "Reserved1"{ type="binary"; loc="8..9"; } "F1PI"{ type="binary"; loc="10..15"; ${_DESC1531_} } "Reserved2"{ type="binary"; loc="16..17"; } "F1G1"{ type="binary"; loc="18..23"; ${_DESC1532_} } "Reserved3"{ type="binary"; loc="24"; } "F1FL"{ type="binary"; loc="25..31"; ${_DESC1533_} } } bitfield_M_CAN_1_RXF1A{ "Reserved0"{ type="binary"; loc="0..25"; } "F1AI"{ type="binary"; loc="26..31"; ${_DESC1535_} } } bitfield_M_CAN_1_TXBC{ "Reserved0"{ type="binary"; loc="0"; } "TQFM"{ type="binary"; loc="1"; ${_DESC1537_} } "TQFS"{ type="binary"; loc="2..7"; ${_DESC1538_} } "Reserved1"{ type="binary"; loc="8..9"; } "NDTB"{ type="binary"; loc="10..15"; ${_DESC1539_} } "TBSA"{ type="binary"; loc="16..29"; ${_DESC1540_} } "Reserved2"{ type="binary"; loc="30..31"; } } bitfield_M_CAN_1_TXFQS{ "Reserved0"{ type="binary"; loc="0..9"; } "TFQF"{ type="binary"; loc="10"; ${_DESC1542_} } "TFQPI"{ type="binary"; loc="11..15"; ${_DESC1543_} } "Reserved1"{ type="binary"; loc="16..18"; } "TFGI"{ type="binary"; loc="19..23"; ${_DESC1544_} } "Reserved2"{ type="binary"; loc="24..25"; } "TFFL"{ type="binary"; loc="26..31"; ${_DESC1545_} } } bitfield_M_CAN_1_TXBRP{ "TRP"{ type="binary"; loc="0..31"; ${_DESC1547_} } } bitfield_M_CAN_1_TXBAR{ "AR"{ type="binary"; loc="0..31"; ${_DESC1549_} } } bitfield_M_CAN_1_TXBCR{ "CR"{ type="binary"; loc="0..31"; ${_DESC1551_} } } bitfield_M_CAN_1_TXBTO{ "TO"{ type="binary"; loc="0..31"; ${_DESC1553_} } } bitfield_M_CAN_1_TXBCF{ "CF"{ type="binary"; loc="0..31"; ${_DESC1555_} } } bitfield_M_CAN_1_TXBTIE{ "TIE"{ type="binary"; loc="0..31"; ${_DESC1557_} } } bitfield_M_CAN_1_TXBCIE{ "CFIE"{ type="binary"; loc="0..31"; ${_DESC1559_} } } bitfield_M_CAN_1_TXEFC{ "Reserved0"{ type="binary"; loc="0..1"; } "EFWM"{ type="binary"; loc="2..7"; ${_DESC1561_} } "Reserved1"{ type="binary"; loc="8..9"; } "EFS"{ type="binary"; loc="10..15"; ${_DESC1562_} } "EFSA"{ type="binary"; loc="16..29"; ${_DESC1563_} } "Reserved2"{ type="binary"; loc="30..31"; } } bitfield_M_CAN_1_TXEFS{ "Reserved0"{ type="binary"; loc="0..5"; } "TEFL"{ type="binary"; loc="6"; ${_DESC1565_} } "EFF"{ type="binary"; loc="7"; ${_DESC1566_} } "Reserved1"{ type="binary"; loc="8..10"; } "EFPI"{ type="binary"; loc="11..15"; ${_DESC1567_} } "Reserved2"{ type="binary"; loc="16..18"; } "EFGI"{ type="binary"; loc="19..23"; ${_DESC1568_} } "Reserved3"{ type="binary"; loc="24..25"; } "EFFL"{ type="binary"; loc="26..31"; ${_DESC1569_} } } bitfield_M_CAN_1_TXEFA{ "Reserved0"{ type="binary"; loc="0..26"; } "EFAI"{ type="binary"; loc="27..31"; ${_DESC1571_} } } bitfield_PASS_LCSTAT{ "CNS"{ type="binary"; loc="0"; ${_DESC1573_} } "JUN"{ type="binary"; loc="1"; ${_DESC1574_} } "Reserved0"{ type="binary"; loc="2..28"; } "LIFE"{ type="binary"; loc="29..31"; ${_DESC1575_} } } bitfield_PASS_CHSEL{ "Reserved0"{ type="binary"; loc="0..29"; } "GRP"{ type="binary"; loc="30..31"; ${_DESC1577_} } } bitfield_PASS_CSTAT{ "Reserved0"{ type="binary"; loc="0..27"; } "CMST"{ type="binary"; loc="28..31"; ${_DESC1579_} } } bitfield_PASS_CIN0{ "PW32"{ type="binary"; loc="0..31"; ${_DESC1581_} } } bitfield_PASS_LOCK0_PG0{ "TSLOCK"{ type="binary"; loc="0"; ${_DESC1583_} } "ATSL"{ type="binary"; loc="1"; ${_DESC1584_} } "LOWLOCK"{ type="binary"; loc="2..15"; ${_DESC1585_} } "MIDLOCK"{ type="binary"; loc="16..31"; ${_DESC1586_} } } bitfield_PASS_LOCK1_PG0{ "Reserved0"{ type="binary"; loc="0..15"; } "HIGHLOCK"{ type="binary"; loc="16..31"; ${_DESC1588_} } } bitfield_PASS_LOCK2_PG0{ "256LCK_L"{ type="binary"; loc="0..31"; ${_DESC1590_} } } bitfield_PASS_LOCK3_PG0{ "PGL"{ type="binary"; loc="0"; ${_DESC1592_} } "DBL"{ type="binary"; loc="1"; ${_DESC1593_} } "MO"{ type="binary"; loc="2"; ${_DESC1594_} } "Reserved0"{ type="binary"; loc="3"; } "MSTR"{ type="binary"; loc="4..7"; ${_DESC1595_} } "Reserved1"{ type="binary"; loc="8..10"; } "RL4"{ type="binary"; loc="11"; ${_DESC1596_} } "RL3"{ type="binary"; loc="12"; ${_DESC1597_} } "RL2"{ type="binary"; loc="13"; ${_DESC1598_} } "RL1"{ type="binary"; loc="14"; ${_DESC1599_} } "RL0"{ type="binary"; loc="15"; ${_DESC1600_} } "256LCK_U"{ type="binary"; loc="16..31"; ${_DESC1601_} } } bitfield_PBRIDGE_A_MPRA{ "MPROT0"{ type="binary"; loc="0..3"; ${_DESC1603_} } "MPROT1"{ type="binary"; loc="4..7"; ${_DESC1604_} } "MPROT2"{ type="binary"; loc="8..11"; ${_DESC1605_} } "MPROT3"{ type="binary"; loc="12..15"; ${_DESC1606_} } "MPROT4"{ type="binary"; loc="16..19"; ${_DESC1607_} } "MPROT5"{ type="binary"; loc="20..23"; ${_DESC1608_} } "MPROT6"{ type="binary"; loc="24..27"; ${_DESC1609_} } "MPROT7"{ type="binary"; loc="28..31"; ${_DESC1610_} } } bitfield_PBRIDGE_A_PACRA{ "PACRa"{ type="binary"; loc="0..3"; ${_DESC1612_} } "PACRb"{ type="binary"; loc="4..7"; ${_DESC1613_} } "PACRc"{ type="binary"; loc="8..11"; ${_DESC1614_} } "PACRd"{ type="binary"; loc="12..15"; ${_DESC1615_} } "PACRe"{ type="binary"; loc="16..19"; ${_DESC1616_} } "PACRf"{ type="binary"; loc="20..23"; ${_DESC1617_} } "PACRg"{ type="binary"; loc="24..27"; ${_DESC1618_} } "PACRh"{ type="binary"; loc="28..31"; ${_DESC1619_} } } bitfield_PBRIDGE_A_OPACRA{ "OPACRa"{ type="binary"; loc="0..3"; ${_DESC1612_} } "OPACRb"{ type="binary"; loc="4..7"; ${_DESC1613_} } "OPACRc"{ type="binary"; loc="8..11"; ${_DESC1614_} } "OPACRd"{ type="binary"; loc="12..15"; ${_DESC1615_} } "OPACRe"{ type="binary"; loc="16..19"; ${_DESC1616_} } "OPACRf"{ type="binary"; loc="20..23"; ${_DESC1617_} } "OPACRg"{ type="binary"; loc="24..27"; ${_DESC1618_} } "OPACRh"{ type="binary"; loc="28..31"; ${_DESC1619_} } } bitfield_PFLASH_PFCR1{ "P0_M15PFE"{ type="binary"; loc="0"; ${_DESC1622_} } "P0_M14PFE"{ type="binary"; loc="1"; ${_DESC1623_} } "P0_M13PFE"{ type="binary"; loc="2"; ${_DESC1624_} } "P0_M12PFE"{ type="binary"; loc="3"; ${_DESC1625_} } "P0_M11PFE"{ type="binary"; loc="4"; ${_DESC1626_} } "P0_M10PFE"{ type="binary"; loc="5"; ${_DESC1627_} } "P0_M9PFE"{ type="binary"; loc="6"; ${_DESC1628_} } "P0_M8PFE"{ type="binary"; loc="7"; ${_DESC1629_} } "P0_M7PFE"{ type="binary"; loc="8"; ${_DESC1630_} } "P0_M6PFE"{ type="binary"; loc="9"; ${_DESC1631_} } "P0_M5PFE"{ type="binary"; loc="10"; ${_DESC1632_} } "P0_M4PFE"{ type="binary"; loc="11"; ${_DESC1633_} } "P0_M3PFE"{ type="binary"; loc="12"; ${_DESC1634_} } "P0_M2PFE"{ type="binary"; loc="13"; ${_DESC1635_} } "P0_M1PFE"{ type="binary"; loc="14"; ${_DESC1636_} } "P0_M0PFE"{ type="binary"; loc="15"; ${_DESC1637_} } "Reserved0"{ type="binary"; loc="16..18"; } "RWSC"{ type="binary"; loc="19..23"; ${_DESC1638_} } "Reserved1"{ type="binary"; loc="24"; } "P0_DPFEN"{ type="binary"; loc="25"; ${_DESC1639_} } "Reserved2"{ type="binary"; loc="26"; ${_DESC1640_} } "P0_IPFEN"{ type="binary"; loc="27"; ${_DESC1641_} } "Reserved3"{ type="binary"; loc="28"; ${_DESC1640_} } "P0_PFLIM"{ type="binary"; loc="29..30"; ${_DESC1642_} } "P0_BFEN"{ type="binary"; loc="31"; ${_DESC1643_} } } bitfield_PFLASH_PFCR3{ "P0_WCFG"{ type="binary"; loc="0..1"; ${_DESC1645_} } "Reserved0"{ type="binary"; loc="2..3"; } "Reserved1"{ type="binary"; loc="4..10"; ${_DESC1640_} } "Reserved2"{ type="binary"; loc="11"; } "Reserved3"{ type="binary"; loc="12..14"; ${_DESC1640_} } "BAF_DIS"{ type="binary"; loc="15"; ${_DESC1646_} } "Reserved4"{ type="binary"; loc="16..17"; } "Reserved5"{ type="binary"; loc="18..31"; ${_DESC1640_} } } bitfield_PFLASH_PFAPR{ "M0AP"{ type="binary"; loc="0..1"; ${_DESC1648_} } "M1AP"{ type="binary"; loc="2..3"; ${_DESC1649_} } "M2AP"{ type="binary"; loc="4..5"; ${_DESC1650_} } "M3AP"{ type="binary"; loc="6..7"; ${_DESC1651_} } "M4AP"{ type="binary"; loc="8..9"; ${_DESC1652_} } "M5AP"{ type="binary"; loc="10..11"; ${_DESC1653_} } "M6AP"{ type="binary"; loc="12..13"; ${_DESC1654_} } "M7AP"{ type="binary"; loc="14..15"; ${_DESC1655_} } "M8AP"{ type="binary"; loc="16..17"; ${_DESC1656_} } "M9AP"{ type="binary"; loc="18..19"; ${_DESC1657_} } "M10AP"{ type="binary"; loc="20..21"; ${_DESC1658_} } "M11AP"{ type="binary"; loc="22..23"; ${_DESC1659_} } "M12AP"{ type="binary"; loc="24..25"; ${_DESC1660_} } "M13AP"{ type="binary"; loc="26..27"; ${_DESC1661_} } "M14AP"{ type="binary"; loc="28..29"; ${_DESC1662_} } "M15AP"{ type="binary"; loc="30..31"; ${_DESC1663_} } } bitfield_PFLASH_PFCRCR{ "Reserved0"{ type="binary"; loc="0..22"; } "SAFE_CAL"{ type="binary"; loc="23"; ${_DESC1665_} } "Reserved1"{ type="binary"; loc="24..26"; } "IRMEN"{ type="binary"; loc="27"; ${_DESC1666_} } "Reserved2"{ type="binary"; loc="28..30"; } "GRMEN"{ type="binary"; loc="31"; ${_DESC1667_} } } bitfield_PFLASH_PFCRDE{ "CRD0EN"{ type="binary"; loc="0"; ${_DESC1669_} } "CRD1EN"{ type="binary"; loc="1"; ${_DESC1670_} } "CRD2EN"{ type="binary"; loc="2"; ${_DESC1671_} } "CRD3EN"{ type="binary"; loc="3"; ${_DESC1672_} } "CRD4EN"{ type="binary"; loc="4"; ${_DESC1673_} } "CRD5EN"{ type="binary"; loc="5"; ${_DESC1674_} } "CRD6EN"{ type="binary"; loc="6"; ${_DESC1675_} } "CRD7EN"{ type="binary"; loc="7"; ${_DESC1676_} } "CRD8EN"{ type="binary"; loc="8"; ${_DESC1677_} } "CRD9EN"{ type="binary"; loc="9"; ${_DESC1678_} } "CRD10EN"{ type="binary"; loc="10"; ${_DESC1679_} } "CRD11EN"{ type="binary"; loc="11"; ${_DESC1680_} } "CRD12EN"{ type="binary"; loc="12"; ${_DESC1681_} } "CRD13EN"{ type="binary"; loc="13"; ${_DESC1682_} } "CRD14EN"{ type="binary"; loc="14"; ${_DESC1683_} } "CRD15EN"{ type="binary"; loc="15"; ${_DESC1684_} } "CRD16EN"{ type="binary"; loc="16"; ${_DESC1685_} } "CRD17EN"{ type="binary"; loc="17"; ${_DESC1686_} } "CRD18EN"{ type="binary"; loc="18"; ${_DESC1687_} } "CRD19EN"{ type="binary"; loc="19"; ${_DESC1688_} } "CRD20EN"{ type="binary"; loc="20"; ${_DESC1689_} } "CRD21EN"{ type="binary"; loc="21"; ${_DESC1690_} } "CRD22EN"{ type="binary"; loc="22"; ${_DESC1691_} } "CRD23EN"{ type="binary"; loc="23"; ${_DESC1692_} } "CRD24EN"{ type="binary"; loc="24"; ${_DESC1693_} } "CRD25EN"{ type="binary"; loc="25"; ${_DESC1694_} } "CRD26EN"{ type="binary"; loc="26"; ${_DESC1695_} } "CRD27EN"{ type="binary"; loc="27"; ${_DESC1696_} } "CRD28EN"{ type="binary"; loc="28"; ${_DESC1697_} } "CRD29EN"{ type="binary"; loc="29"; ${_DESC1698_} } "CRD30EN"{ type="binary"; loc="30"; ${_DESC1699_} } "CRD31EN"{ type="binary"; loc="31"; ${_DESC1700_} } } bitfield_PFLASH_PFCRD0_W0{ "LSTARTADDR"{ type="binary"; loc="0..27"; ${_DESC1702_} } "Reserved0"{ type="binary"; loc="28..31"; } } bitfield_PFLASH_PFCRD0_W1{ "PSTARTADDR"{ type="binary"; loc="0..27"; ${_DESC1703_} } "Reserved1"{ type="binary"; loc="28..31"; } } bitfield_PFLASH_PFCRD0_W2{ "M0EN"{ type="binary"; loc="0"; ${_DESC1704_} } "M1EN"{ type="binary"; loc="1"; ${_DESC1705_} } "M2EN"{ type="binary"; loc="2"; ${_DESC1706_} } "M3EN"{ type="binary"; loc="3"; ${_DESC1707_} } "M4EN"{ type="binary"; loc="4"; ${_DESC1708_} } "M5EN"{ type="binary"; loc="5"; ${_DESC1709_} } "M6EN"{ type="binary"; loc="6"; ${_DESC1710_} } "M7EN"{ type="binary"; loc="7"; ${_DESC1711_} } "M8EN"{ type="binary"; loc="8"; ${_DESC1712_} } "M9EN"{ type="binary"; loc="9"; ${_DESC1713_} } "M10EN"{ type="binary"; loc="10"; ${_DESC1714_} } "M11EN"{ type="binary"; loc="11"; ${_DESC1715_} } "M12EN"{ type="binary"; loc="12"; ${_DESC1716_} } "M13EN"{ type="binary"; loc="13"; ${_DESC1717_} } "M14EN"{ type="binary"; loc="14"; ${_DESC1718_} } "M15EN"{ type="binary"; loc="15"; ${_DESC1719_} } "Reserved2"{ type="binary"; loc="16..26"; } "CRDSize"{ type="binary"; loc="27..31"; ${_DESC1720_} } } bitfield_PIT_0_MCR{ "Reserved0"{ type="binary"; loc="0..29"; } "MDIS"{ type="binary"; loc="30"; ${_DESC1722_} } "FRZ"{ type="binary"; loc="31"; ${_DESC1723_} } } bitfield_PIT_0_LTMR64H{ "LTH"{ type="binary"; loc="0..31"; ${_DESC1725_} } } bitfield_PIT_0_LTMR64L{ "LTL"{ type="binary"; loc="0..31"; ${_DESC1727_} } } bitfield_PIT_0_LDVAL0{ "TSV"{ type="binary"; loc="0..31"; ${_DESC1729_} } } bitfield_PIT_0_CVAL0{ "TVL"{ type="binary"; loc="0..31"; ${_DESC1731_} } } bitfield_PIT_0_TCTRL0{ "Reserved0"{ type="binary"; loc="0..28"; } "CHN"{ type="binary"; loc="29"; ${_DESC1733_} } "TIE"{ type="binary"; loc="30"; ${_DESC1734_} } "TEN"{ type="binary"; loc="31"; ${_DESC1735_} } } bitfield_PIT_0_TFLG0{ "Reserved0"{ type="binary"; loc="0..30"; ${_DESC1737_} } "TIF"{ type="binary"; loc="31"; ${_DESC1738_} } } bitfield_PLLDIG_PLLCR{ "Reserved0"{ type="binary"; loc="0..21"; } "CLKCFG"{ type="binary"; loc="22..23"; ${_DESC1740_} } "Reserved1"{ type="binary"; loc="24"; } "Reserved2"{ type="binary"; loc="25"; } "Reserved3"{ type="binary"; loc="26"; } "Reserved4"{ type="binary"; loc="27"; } "LOLIE"{ type="binary"; loc="28"; ${_DESC1741_} } "LOLRE"{ type="binary"; loc="29"; ${_DESC1742_} } "Reserved5"{ type="binary"; loc="30"; } "Reserved6"{ type="binary"; loc="31"; } } bitfield_PLLDIG_PLLSR{ "Reserved0"{ type="binary"; loc="0..23"; } "Reserved1"{ type="binary"; loc="24"; } "Reserved2"{ type="binary"; loc="25"; } "Reserved3"{ type="binary"; loc="26"; } "Reserved4"{ type="binary"; loc="27"; } "LOLF"{ type="binary"; loc="28"; ${_DESC1744_} } "LOCK"{ type="binary"; loc="29"; ${_DESC1745_} } "Reserved5"{ type="binary"; loc="30"; } "Reserved6"{ type="binary"; loc="31"; } } bitfield_PLLDIG_PLLDV{ "Reserved0"{ type="binary"; loc="0"; } "RFDPHI1"{ type="binary"; loc="1..4"; ${_DESC1747_} } "Reserved1"{ type="binary"; loc="5..9"; } "RFDPHI"{ type="binary"; loc="10..15"; ${_DESC1748_} } "Reserved2"{ type="binary"; loc="16"; } "PREDIV"{ type="binary"; loc="17..19"; ${_DESC1749_} } "Reserved3"{ type="binary"; loc="20..24"; } "MFD"{ type="binary"; loc="25..31"; ${_DESC1750_} } } bitfield_PMCDIG_GR_S{ "Reserved0"{ type="binary"; loc="0..16"; } "VD14"{ type="binary"; loc="17"; ${_DESC1752_} } "Reserved1"{ type="binary"; loc="18..20"; } "VD10"{ type="binary"; loc="21"; ${_DESC1753_} } "VD9"{ type="binary"; loc="22"; ${_DESC1754_} } "Reserved2"{ type="binary"; loc="23..27"; } "VD3"{ type="binary"; loc="28"; ${_DESC1755_} } "Reserved3"{ type="binary"; loc="29..30"; } "VD2"{ type="binary"; loc="31"; ${_DESC1756_} } } bitfield_PMCDIG_GR_P{ "Reserved0"{ type="binary"; loc="0..8"; } "VD14_A"{ type="binary"; loc="9"; ${_DESC1758_} } "VD14_IM"{ type="binary"; loc="10"; ${_DESC1759_} } "Reserved1"{ type="binary"; loc="11..15"; } "VD10_F"{ type="binary"; loc="16"; ${_DESC1760_} } "VD10_C"{ type="binary"; loc="17"; ${_DESC1761_} } "Reserved2"{ type="binary"; loc="18"; } "VD10_IF"{ type="binary"; loc="19"; ${_DESC1762_} } "VD10_IJ"{ type="binary"; loc="20"; ${_DESC1763_} } "Reserved3"{ type="binary"; loc="21..23"; } "VD9_C"{ type="binary"; loc="24"; ${_DESC1764_} } "Reserved4"{ type="binary"; loc="25..27"; } "VD3_C"{ type="binary"; loc="28"; ${_DESC1765_} } "Reserved5"{ type="binary"; loc="29..30"; } "VD2_C"{ type="binary"; loc="31"; ${_DESC1766_} } } bitfield_PMCDIG_IE_P{ "IE_EN"{ type="binary"; loc="0"; ${_DESC1768_} } "Reserved0"{ type="binary"; loc="1..8"; } "VD14IE_A"{ type="binary"; loc="9"; ${_DESC1769_} } "VD14IE_IM"{ type="binary"; loc="10"; ${_DESC1770_} } "Reserved1"{ type="binary"; loc="11..15"; } "VD10IE_F"{ type="binary"; loc="16"; ${_DESC1771_} } "VD10IE_C"{ type="binary"; loc="17"; ${_DESC1772_} } "Reserved2"{ type="binary"; loc="18"; } "VD10IE_IF"{ type="binary"; loc="19"; ${_DESC1773_} } "VD10IE_IJ"{ type="binary"; loc="20"; ${_DESC1774_} } "Reserved3"{ type="binary"; loc="21..23"; } "VD9IE_C"{ type="binary"; loc="24"; ${_DESC1775_} } "Reserved4"{ type="binary"; loc="25..27"; } "VD3IE_C"{ type="binary"; loc="28"; ${_DESC1776_} } "Reserved5"{ type="binary"; loc="29..30"; } "VD2IE_C"{ type="binary"; loc="31"; ${_DESC1777_} } } bitfield_PMCDIG_EPR_VD3{ "Reserved0"{ type="binary"; loc="0..27"; } "LVD3_C"{ type="binary"; loc="28"; ${_DESC1779_} } "Reserved1"{ type="binary"; loc="29..31"; } } bitfield_PMCDIG_REE_VD3{ "Reserved0"{ type="binary"; loc="0..27"; } "LVD3_C"{ type="binary"; loc="28"; ${_DESC1781_} } "Reserved1"{ type="binary"; loc="29..31"; } } bitfield_PMCDIG_RES_VD3{ "Reserved0"{ type="binary"; loc="0..27"; } "LVD3_C"{ type="binary"; loc="28"; ${_DESC1783_} } "Reserved1"{ type="binary"; loc="29..31"; } } bitfield_PMCDIG_EPR_VD9{ "Reserved0"{ type="binary"; loc="0..27"; } "LVD9_C"{ type="binary"; loc="28"; ${_DESC1785_} } "Reserved1"{ type="binary"; loc="29..31"; } } bitfield_PMCDIG_EPR_VD10{ "Reserved0"{ type="binary"; loc="0..15"; } "LVD10_F"{ type="binary"; loc="16"; ${_DESC1787_} } "LVD10_C"{ type="binary"; loc="17"; ${_DESC1788_} } "Reserved1"{ type="binary"; loc="18"; } "LVD10_IF"{ type="binary"; loc="19"; ${_DESC1789_} } "LVD10_IJ"{ type="binary"; loc="20"; ${_DESC1790_} } "Reserved2"{ type="binary"; loc="21..31"; } } bitfield_PMCDIG_REE_VD10{ "Reserved0"{ type="binary"; loc="0..15"; } "LVD10_F"{ type="binary"; loc="16"; ${_DESC1792_} } "LVD10_C"{ type="binary"; loc="17"; ${_DESC1793_} } "Reserved1"{ type="binary"; loc="18"; } "LVD10_IF"{ type="binary"; loc="19"; ${_DESC1794_} } "LVD10_IJ"{ type="binary"; loc="20"; ${_DESC1795_} } "Reserved2"{ type="binary"; loc="21..31"; } } bitfield_PMCDIG_EPR_VD14{ "Reserved0"{ type="binary"; loc="0..8"; } "LVD14_A"{ type="binary"; loc="9"; ${_DESC1798_} } "LVD14_IM"{ type="binary"; loc="10"; ${_DESC1799_} } "Reserved1"{ type="binary"; loc="11..31"; } } bitfield_PMCDIG_REE_VD14{ "Reserved0"{ type="binary"; loc="0..8"; } "LVD14_A"{ type="binary"; loc="9"; ${_DESC1801_} } "LVD14_IM"{ type="binary"; loc="10"; ${_DESC1802_} } "Reserved1"{ type="binary"; loc="11..31"; } } bitfield_PMCDIG_RES_VD14{ "Reserved0"{ type="binary"; loc="0..8"; } "LVD14_A"{ type="binary"; loc="9"; ${_DESC1804_} } "LVD14_IM"{ type="binary"; loc="10"; ${_DESC1805_} } "Reserved1"{ type="binary"; loc="11..31"; } } bitfield_PMCDIG_VSIO{ "Reserved0"{ type="binary"; loc="0..20"; } "VSIO_IF"{ type="binary"; loc="21"; ${_DESC1807_} } "VSIO_IJ"{ type="binary"; loc="22"; ${_DESC1808_} } "VSIO_IM"{ type="binary"; loc="23"; ${_DESC1809_} } "Reserved1"{ type="binary"; loc="24..31"; } } bitfield_PMCDIG_MREG_CTRL{ "Reserved0"{ type="binary"; loc="0..30"; } "MREG_ENB"{ type="binary"; loc="31"; ${_DESC1811_} } } bitfield_PMCDIG_EPR_TD{ "Reserved0"{ type="binary"; loc="0..28"; } "TEMP_2"{ type="binary"; loc="29"; ${_DESC1813_} } "TEMP_1"{ type="binary"; loc="30"; ${_DESC1814_} } "TEMP_0"{ type="binary"; loc="31"; ${_DESC1815_} } } bitfield_PMCDIG_REE_TD{ "Reserved0"{ type="binary"; loc="0..28"; } "TEMP_2"{ type="binary"; loc="29"; ${_DESC1817_} } "TEMP_1"{ type="binary"; loc="30"; ${_DESC1818_} } "TEMP_0"{ type="binary"; loc="31"; ${_DESC1819_} } } bitfield_PMCDIG_RES_TD{ "Reserved0"{ type="binary"; loc="0..28"; } "TEMP_2"{ type="binary"; loc="29"; ${_DESC1821_} } "TEMP_1"{ type="binary"; loc="30"; ${_DESC1822_} } "TEMP_0"{ type="binary"; loc="31"; ${_DESC1823_} } } bitfield_PMCDIG_CTL_TD{ "Reserved0"{ type="binary"; loc="0..15"; } "TS3IE"{ type="binary"; loc="16"; ${_DESC1825_} } "TS2IE"{ type="binary"; loc="17"; ${_DESC1826_} } "TS0IE"{ type="binary"; loc="18"; ${_DESC1827_} } "Reserved1"{ type="binary"; loc="19"; } "TRIM_ADJ_OVER"{ type="binary"; loc="20..23"; ${_DESC1828_} } "Reserved2"{ type="binary"; loc="24..25"; } "TRIM_ADJ_UNDER"{ type="binary"; loc="26..29"; ${_DESC1829_} } "DOUT_EN"{ type="binary"; loc="30"; ${_DESC1830_} } "AOUT_EN"{ type="binary"; loc="31"; ${_DESC1831_} } } bitfield_PRAMC_PRCR1{ "Reserved0"{ type="binary"; loc="0..24"; } "P0_BO_DIS"{ type="binary"; loc="25"; ${_DESC1833_} } "Reserved1"{ type="binary"; loc="26..30"; } "FT_DIS"{ type="binary"; loc="31"; ${_DESC1834_} } } bitfield_SARADC_0_MCR{ "OWREN"{ type="binary"; loc="0"; ${_DESC1836_} } "WLSIDE"{ type="binary"; loc="1"; ${_DESC1837_} } "MODE"{ type="binary"; loc="2"; ${_DESC1838_} } "XSTRTEN"{ type="binary"; loc="3"; ${_DESC1839_} } "NSTART"{ type="binary"; loc="4"; ${_DESC1840_} } "NTRGEN"{ type="binary"; loc="5"; ${_DESC1841_} } "NEDGESEL"{ type="binary"; loc="6..7"; ${_DESC1842_} } "JSTART"{ type="binary"; loc="8"; ${_DESC1843_} } "JTRGEN"{ type="binary"; loc="9"; ${_DESC1844_} } "JEDGESEL"{ type="binary"; loc="10..11"; ${_DESC1845_} } "JTRGSEQ"{ type="binary"; loc="12"; ${_DESC1846_} } "Reserved0"{ type="binary"; loc="13"; ${_DESC1847_} } "CTUEN"{ type="binary"; loc="14"; ${_DESC1848_} } "CTU_MODE"{ type="binary"; loc="15"; ${_DESC1849_} } "Reserved1"{ type="binary"; loc="16..19"; } "JTRGSEL"{ type="binary"; loc="20..23"; ${_DESC1850_} } "ABORTCHAIN"{ type="binary"; loc="24"; ${_DESC1851_} } "ABORT"{ type="binary"; loc="25"; ${_DESC1852_} } "Reserved2"{ type="binary"; loc="26"; ${_DESC9_} } "FRZ"{ type="binary"; loc="27"; ${_DESC1853_} } "Reserved3"{ type="binary"; loc="28..30"; ${_DESC9_} } "PWDN"{ type="binary"; loc="31"; ${_DESC1854_} } } bitfield_SARADC_0_MSR{ "Reserved0"{ type="binary"; loc="0..3"; ${_DESC1847_} } "NSTART"{ type="binary"; loc="4"; ${_DESC1856_} } "Reserved1"{ type="binary"; loc="5..7"; ${_DESC1847_} } "JSTART"{ type="binary"; loc="8"; ${_DESC1857_} } "Reserved2"{ type="binary"; loc="9..12"; ${_DESC1847_} } "JABORTCHAIN"{ type="binary"; loc="13"; ${_DESC1858_} } "Reserved3"{ type="binary"; loc="14"; ${_DESC1847_} } "CTUSTART"{ type="binary"; loc="15"; ${_DESC1859_} } "CHADDR"{ type="binary"; loc="16..23"; ${_DESC1860_} } "Reserved4"{ type="binary"; loc="24..28"; ${_DESC9_} } "ADCSTATUS"{ type="binary"; loc="29..31"; ${_DESC1861_} } } bitfield_SARADC_0_ISR{ "Reserved0"{ type="binary"; loc="0..26"; ${_DESC1847_} } "EOCTU"{ type="binary"; loc="27"; ${_DESC1863_} } "JEOC"{ type="binary"; loc="28"; ${_DESC1864_} } "JECH"{ type="binary"; loc="29"; ${_DESC1865_} } "NEOC"{ type="binary"; loc="30"; ${_DESC1866_} } "NECH"{ type="binary"; loc="31"; ${_DESC1867_} } } bitfield_SARADC_0_ICIPR0{ "EOC_CHx"{ type="binary"; loc="0..31"; ${_DESC1869_} } } bitfield_SARADC_0_IMR{ "Reserved0"{ type="binary"; loc="0..26"; ${_DESC1847_} } "MSKEOCTU"{ type="binary"; loc="27"; ${_DESC1871_} } "MSKJEOC"{ type="binary"; loc="28"; ${_DESC1872_} } "MSKJECH"{ type="binary"; loc="29"; ${_DESC1873_} } "MSKNEOC"{ type="binary"; loc="30"; ${_DESC1874_} } "MSKNECH"{ type="binary"; loc="31"; ${_DESC1875_} } } bitfield_SARADC_0_ICIMR0{ "IM_CHx"{ type="binary"; loc="0..31"; ${_DESC1877_} } } bitfield_SARADC_0_WTISR{ "WDG15H"{ type="binary"; loc="0"; ${_DESC1879_} } "WDG15L"{ type="binary"; loc="1"; ${_DESC1880_} } "WDG14H"{ type="binary"; loc="2"; ${_DESC1879_} } "WDG14L"{ type="binary"; loc="3"; ${_DESC1880_} } "WDG13H"{ type="binary"; loc="4"; ${_DESC1879_} } "WDG13L"{ type="binary"; loc="5"; ${_DESC1880_} } "WDG12H"{ type="binary"; loc="6"; ${_DESC1879_} } "WDG12L"{ type="binary"; loc="7"; ${_DESC1880_} } "WDG11H"{ type="binary"; loc="8"; ${_DESC1879_} } "WDG11L"{ type="binary"; loc="9"; ${_DESC1880_} } "WDG10H"{ type="binary"; loc="10"; ${_DESC1879_} } "WDG10L"{ type="binary"; loc="11"; ${_DESC1880_} } "WDG9H"{ type="binary"; loc="12"; ${_DESC1879_} } "WDG9L"{ type="binary"; loc="13"; ${_DESC1880_} } "WDG8H"{ type="binary"; loc="14"; ${_DESC1879_} } "WDG8L"{ type="binary"; loc="15"; ${_DESC1880_} } "WDG7H"{ type="binary"; loc="16"; ${_DESC1879_} } "WDG7L"{ type="binary"; loc="17"; ${_DESC1880_} } "WDG6H"{ type="binary"; loc="18"; ${_DESC1879_} } "WDG6L"{ type="binary"; loc="19"; ${_DESC1880_} } "WDG5H"{ type="binary"; loc="20"; ${_DESC1879_} } "WDG5L"{ type="binary"; loc="21"; ${_DESC1880_} } "WDG4H"{ type="binary"; loc="22"; ${_DESC1879_} } "WDG4L"{ type="binary"; loc="23"; ${_DESC1880_} } "WDG3H"{ type="binary"; loc="24"; ${_DESC1879_} } "WDG3L"{ type="binary"; loc="25"; ${_DESC1880_} } "WDG2H"{ type="binary"; loc="26"; ${_DESC1879_} } "WDG2L"{ type="binary"; loc="27"; ${_DESC1880_} } "WDG1H"{ type="binary"; loc="28"; ${_DESC1879_} } "WDG1L"{ type="binary"; loc="29"; ${_DESC1880_} } "WDG0H"{ type="binary"; loc="30"; ${_DESC1879_} } "WDG0L"{ type="binary"; loc="31"; ${_DESC1880_} } } bitfield_SARADC_0_WTIMR{ "MSKWDG15H"{ type="binary"; loc="0"; ${_DESC1882_} } "MSKWDG15L"{ type="binary"; loc="1"; ${_DESC1883_} } "MSKWDG14H"{ type="binary"; loc="2"; ${_DESC1882_} } "MSKWDG14L"{ type="binary"; loc="3"; ${_DESC1883_} } "MSKWDG13H"{ type="binary"; loc="4"; ${_DESC1882_} } "MSKWDG13L"{ type="binary"; loc="5"; ${_DESC1883_} } "MSKWDG12H"{ type="binary"; loc="6"; ${_DESC1882_} } "MSKWDG12L"{ type="binary"; loc="7"; ${_DESC1883_} } "MSKWDG11H"{ type="binary"; loc="8"; ${_DESC1882_} } "MSKWDG11L"{ type="binary"; loc="9"; ${_DESC1883_} } "MSKWDG10H"{ type="binary"; loc="10"; ${_DESC1882_} } "MSKWDG10L"{ type="binary"; loc="11"; ${_DESC1883_} } "MSKWDG9H"{ type="binary"; loc="12"; ${_DESC1882_} } "MSKWDG9L"{ type="binary"; loc="13"; ${_DESC1883_} } "MSKWDG8H"{ type="binary"; loc="14"; ${_DESC1882_} } "MSKWDG8L"{ type="binary"; loc="15"; ${_DESC1883_} } "MSKWDG7H"{ type="binary"; loc="16"; ${_DESC1882_} } "MSKWDG7L"{ type="binary"; loc="17"; ${_DESC1883_} } "MSKWDG6H"{ type="binary"; loc="18"; ${_DESC1882_} } "MSKWDG6L"{ type="binary"; loc="19"; ${_DESC1883_} } "MSKWDG5H"{ type="binary"; loc="20"; ${_DESC1882_} } "MSKWDG5L"{ type="binary"; loc="21"; ${_DESC1883_} } "MSKWDG4H"{ type="binary"; loc="22"; ${_DESC1882_} } "MSKWDG4L"{ type="binary"; loc="23"; ${_DESC1883_} } "MSKWDG3H"{ type="binary"; loc="24"; ${_DESC1882_} } "MSKWDG3L"{ type="binary"; loc="25"; ${_DESC1883_} } "MSKWDG2H"{ type="binary"; loc="26"; ${_DESC1882_} } "MSKWDG2L"{ type="binary"; loc="27"; ${_DESC1883_} } "MSKWDG1H"{ type="binary"; loc="28"; ${_DESC1882_} } "MSKWDG1L"{ type="binary"; loc="29"; ${_DESC1883_} } "MSKWDG0H"{ type="binary"; loc="30"; ${_DESC1882_} } "MSKWDG0L"{ type="binary"; loc="31"; ${_DESC1883_} } } bitfield_SARADC_0_DMAE{ "Reserved0"{ type="binary"; loc="0..29"; ${_DESC1847_} } "DCLR"{ type="binary"; loc="30"; ${_DESC1885_} } "DMAEN"{ type="binary"; loc="31"; ${_DESC1886_} } } bitfield_SARADC_0_ICDSR0{ "DS_CHx"{ type="binary"; loc="0..31"; ${_DESC1888_} } } bitfield_SARADC_0_WTHRHLR0{ "Reserved0"{ type="binary"; loc="0..3"; ${_DESC1847_} } "THRH"{ type="binary"; loc="4..15"; ${_DESC1890_} } "Reserved1"{ type="binary"; loc="16..19"; ${_DESC1847_} } "THRL"{ type="binary"; loc="20..31"; ${_DESC1891_} } } bitfield_SARADC_0_CTR0{ "CRES"{ type="binary"; loc="0"; ${_DESC1893_} } "Reserved0"{ type="binary"; loc="1..19"; ${_DESC1847_} } "PRECHG"{ type="binary"; loc="20..23"; ${_DESC1894_} } "INPSAMP"{ type="binary"; loc="24..31"; ${_DESC1895_} } } bitfield_SARADC_0_ICNCMR0{ "NCE_CHx"{ type="binary"; loc="0..31"; ${_DESC1897_} } } bitfield_SARADC_0_ICJCMR0{ "JCE_CH"{ type="binary"; loc="0..31"; ${_DESC1899_} } } bitfield_SARADC_0_PDEDR{ "Reserved0"{ type="binary"; loc="0..23"; ${_DESC1847_} } "PDED"{ type="binary"; loc="24..31"; ${_DESC1901_} } } bitfield_SARADC_0_ICDR0{ "Reserved0"{ type="binary"; loc="0"; ${_DESC1847_} } "REFSEL"{ type="binary"; loc="1"; ${_DESC1903_} } "Reserved1"{ type="binary"; loc="2..3"; ${_DESC1904_} } "PCE"{ type="binary"; loc="4"; ${_DESC1905_} } "Reserved2"{ type="binary"; loc="5"; ${_DESC1906_} } "CTSEL"{ type="binary"; loc="6..7"; ${_DESC1907_} } "Reserved3"{ type="binary"; loc="8..11"; ${_DESC1847_} } "VALID"{ type="binary"; loc="12"; ${_DESC1908_} } "OVERW"{ type="binary"; loc="13"; ${_DESC1909_} } "RESULT"{ type="binary"; loc="14..15"; ${_DESC1910_} } "Reserved4"{ type="binary"; loc="16..19"; ${_DESC1847_} } "CDATA"{ type="binary"; loc="20..31"; ${_DESC1911_} } } bitfield_SARADC_0_ICWSELR0{ "WSEL_CH7"{ type="binary"; loc="0..3"; ${_DESC1913_} } "WSEL_CH6"{ type="binary"; loc="4..7"; ${_DESC1914_} } "WSEL_CH5"{ type="binary"; loc="8..11"; ${_DESC1915_} } "WSEL_CH4"{ type="binary"; loc="12..15"; ${_DESC1916_} } "WSEL_CH3"{ type="binary"; loc="16..19"; ${_DESC1917_} } "WSEL_CH2"{ type="binary"; loc="20..23"; ${_DESC1918_} } "WSEL_CH1"{ type="binary"; loc="24..27"; ${_DESC1919_} } "WSEL_CH0"{ type="binary"; loc="28..31"; ${_DESC1920_} } } bitfield_SARADC_0_ICWENR0{ "WEN_CHx"{ type="binary"; loc="0..31"; ${_DESC1922_} } } bitfield_SARADC_0_ICAWORR0{ "AWOR_CHx"{ type="binary"; loc="0..31"; ${_DESC1924_} } } bitfield_SARADC_0_TCJCMR{ "JCE_CHx"{ type="binary"; loc="0..31"; ${_DESC1899_} } } bitfield_SARADC_0_TCWSELR0{ "WSEL_CHa"{ type="binary"; loc="0..3"; ${_DESC1931_} } "WSEL_CHb"{ type="binary"; loc="4..7"; ${_DESC1932_} } "WSEL_CHc"{ type="binary"; loc="8..11"; ${_DESC1933_} } "WSEL_CHd"{ type="binary"; loc="12..15"; ${_DESC1934_} } "WSEL_CHe"{ type="binary"; loc="16..19"; ${_DESC1935_} } "WSEL_CHf"{ type="binary"; loc="20..23"; ${_DESC1936_} } "WSEL_CHg"{ type="binary"; loc="24..27"; ${_DESC1937_} } "WSEL_CHh"{ type="binary"; loc="28..31"; ${_DESC1938_} } } bitfield_SARADC_0_TCCAPR0{ "ESIC_TCH3"{ type="binary"; loc="0"; ${_DESC1942_} } "ICSEL_TCH3"{ type="binary"; loc="1..7"; ${_DESC1943_} } "ESIC_TCH2"{ type="binary"; loc="8"; ${_DESC1944_} } "ICSEL_TCH2"{ type="binary"; loc="9..15"; ${_DESC1945_} } "ESIC_TCH1"{ type="binary"; loc="16"; ${_DESC1946_} } "ICSEL_TCH1"{ type="binary"; loc="17..23"; ${_DESC1947_} } "ESIC_TCH0"{ type="binary"; loc="24"; ${_DESC1948_} } "ICSEL_TCH0"{ type="binary"; loc="25..31"; ${_DESC1949_} } } bitfield_SARADC_0_TCDR96{ "Reserved0"{ type="binary"; loc="0"; ${_DESC1847_} } "REFSEL"{ type="binary"; loc="1"; ${_DESC1903_} } "Reserved1"{ type="binary"; loc="2..3"; ${_DESC1906_} } "PCE"{ type="binary"; loc="4"; ${_DESC1951_} } "Reserved2"{ type="binary"; loc="5"; ${_DESC1906_} } "CTSEL"{ type="binary"; loc="6..7"; ${_DESC1907_} } "Reserved3"{ type="binary"; loc="8..11"; ${_DESC1847_} } "VALID"{ type="binary"; loc="12"; ${_DESC1908_} } "OVERW"{ type="binary"; loc="13"; ${_DESC1909_} } "RESULT"{ type="binary"; loc="14..15"; ${_DESC1910_} } "Reserved4"{ type="binary"; loc="16..19"; ${_DESC1847_} } "CDATA"{ type="binary"; loc="20..31"; ${_DESC1911_} } } bitfield_SARADC_0_ECDSDR{ "Reserved0"{ type="binary"; loc="0..19"; ${_DESC1847_} } "DSD"{ type="binary"; loc="20..31"; ${_DESC1953_} } } bitfield_SARADC_0_ECMICR0{ "Reserved0"{ type="binary"; loc="0"; ${_DESC1847_} } "ICSEL_ECH152_159"{ type="binary"; loc="1..7"; ${_DESC1963_} } "Reserved1"{ type="binary"; loc="8"; ${_DESC1847_} } "ICSEL_ECH144_151"{ type="binary"; loc="9..15"; ${_DESC1963_} } "Reserved2"{ type="binary"; loc="16"; ${_DESC1847_} } "ICSEL_ECH136_143"{ type="binary"; loc="17..23"; ${_DESC1963_} } "Reserved3"{ type="binary"; loc="24"; ${_DESC1847_} } "ICSEL_ECH128_135"{ type="binary"; loc="25..31"; ${_DESC1963_} } } bitfield_SARADC_0_ECDR128{ "Reserved0"{ type="binary"; loc="0"; ${_DESC1847_} } "REFSEL"{ type="binary"; loc="1"; ${_DESC1903_} } "Reserved1"{ type="binary"; loc="2..3"; ${_DESC1906_} } "PCE"{ type="binary"; loc="4"; ${_DESC1905_} } "Reserved2"{ type="binary"; loc="5"; ${_DESC1906_} } "CTSEL"{ type="binary"; loc="6..7"; ${_DESC1907_} } "Reserved3"{ type="binary"; loc="8..11"; ${_DESC1847_} } "VALID"{ type="binary"; loc="12"; ${_DESC1908_} } "OVERW"{ type="binary"; loc="13"; ${_DESC1909_} } "RESULT"{ type="binary"; loc="14..15"; ${_DESC1910_} } "Reserved4"{ type="binary"; loc="16..19"; ${_DESC1847_} } "CDATA"{ type="binary"; loc="20..31"; ${_DESC1911_} } } bitfield_SDADC_3_MCR{ "Reserved0"{ type="binary"; loc="0..2"; ${_DESC9_} } "PDR"{ type="binary"; loc="3..7"; ${_DESC1966_} } "Reserved1"{ type="binary"; loc="8"; ${_DESC9_} } "PGAN"{ type="binary"; loc="9..11"; ${_DESC1967_} } "Reserved2"{ type="binary"; loc="12"; } "Reserved3"{ type="binary"; loc="13"; } "EMSEL"{ type="binary"; loc="14"; ${_DESC1968_} } "HPFEN"{ type="binary"; loc="15"; ${_DESC1969_} } "WDGEN"{ type="binary"; loc="16"; ${_DESC1970_} } "TRIGEDSEL"{ type="binary"; loc="17..18"; ${_DESC1971_} } "TRIGEN"{ type="binary"; loc="19"; ${_DESC1972_} } "TRIGSEL"{ type="binary"; loc="20..23"; ${_DESC1973_} } "FRZ"{ type="binary"; loc="24"; ${_DESC1974_} } "Reserved4"{ type="binary"; loc="25..26"; ${_DESC9_} } "VCOMSEL"{ type="binary"; loc="27"; ${_DESC1975_} } "WRMODE"{ type="binary"; loc="28"; ${_DESC1976_} } "GECEN"{ type="binary"; loc="29"; ${_DESC1977_} } "MODE"{ type="binary"; loc="30"; ${_DESC1978_} } "EN"{ type="binary"; loc="31"; ${_DESC1979_} } } bitfield_SDADC_3_CSR{ "Reserved0"{ type="binary"; loc="0..7"; ${_DESC9_} } "BIASEN"{ type="binary"; loc="8..15"; ${_DESC1981_} } "Reserved1"{ type="binary"; loc="16..20"; ${_DESC9_} } "ANCHSEL_WRAP"{ type="binary"; loc="21..23"; ${_DESC1982_} } "Reserved2"{ type="binary"; loc="24..28"; ${_DESC9_} } "ANCHSEL"{ type="binary"; loc="29..31"; ${_DESC1983_} } } bitfield_SDADC_3_RKR{ "Reserved0"{ type="binary"; loc="0..15"; ${_DESC9_} } "RESET_KEY"{ type="binary"; loc="16..31"; ${_DESC1985_} } } bitfield_SDADC_3_SFR{ "Reserved0"{ type="binary"; loc="0..12"; ${_DESC9_} } "ANCHSEL_CNT"{ type="binary"; loc="13..15"; ${_DESC1987_} } "Reserved1"{ type="binary"; loc="16..22"; ${_DESC9_} } "DFEF"{ type="binary"; loc="23"; ${_DESC1988_} } "Reserved2"{ type="binary"; loc="24..26"; ${_DESC9_} } "WTHH"{ type="binary"; loc="27"; ${_DESC1989_} } "WTHL"{ type="binary"; loc="28"; ${_DESC1990_} } "CDVF"{ type="binary"; loc="29"; ${_DESC1991_} } "DFORF"{ type="binary"; loc="30"; ${_DESC1992_} } "DFFF"{ type="binary"; loc="31"; ${_DESC1993_} } } bitfield_SDADC_3_RSER{ "Reserved0"{ type="binary"; loc="0..13"; ${_DESC9_} } "WTHDIRS"{ type="binary"; loc="14"; ${_DESC1995_} } "DFFDIRS"{ type="binary"; loc="15"; ${_DESC1996_} } "GDIGE"{ type="binary"; loc="16"; ${_DESC1997_} } "Reserved1"{ type="binary"; loc="17..27"; ${_DESC9_} } "WTHDIRE"{ type="binary"; loc="28"; ${_DESC1998_} } "CDVEE"{ type="binary"; loc="29"; ${_DESC1999_} } "DFORIE"{ type="binary"; loc="30"; ${_DESC2000_} } "DFFDIRE"{ type="binary"; loc="31"; ${_DESC2001_} } } bitfield_SDADC_3_OSDR{ "Reserved0"{ type="binary"; loc="0..23"; ${_DESC9_} } "OSD"{ type="binary"; loc="24..31"; ${_DESC2003_} } } bitfield_SDADC_3_FCR{ "Reserved0"{ type="binary"; loc="0..19"; ${_DESC9_} } "FTHLD"{ type="binary"; loc="20..23"; ${_DESC2005_} } "Reserved1"{ type="binary"; loc="24..28"; ${_DESC9_} } "FSIZE"{ type="binary"; loc="29..30"; ${_DESC2006_} } "FE"{ type="binary"; loc="31"; ${_DESC2007_} } } bitfield_SDADC_3_STKR{ "Reserved0"{ type="binary"; loc="0..15"; ${_DESC9_} } "ST_KEY"{ type="binary"; loc="16..31"; ${_DESC2009_} } } bitfield_SDADC_3_CDR{ "Reserved0"{ type="binary"; loc="0..15"; ${_DESC9_} } "CDATA"{ type="binary"; loc="16..31"; ${_DESC2011_} } } bitfield_SDADC_3_WTHHLR{ "THRH"{ type="binary"; loc="0..15"; ${_DESC2013_} } "THRL"{ type="binary"; loc="16..31"; ${_DESC2014_} } } bitfield_SIPI_0_CCR0{ "Reserved0"{ type="binary"; loc="0..14"; } "TC"{ type="binary"; loc="15"; ${_DESC2016_} } "Reserved1"{ type="binary"; loc="16..23"; } "WL[1:0]"{ type="binary"; loc="24..25"; ${_DESC2017_} } "CHEN"{ type="binary"; loc="26"; ${_DESC2018_} } "ST"{ type="binary"; loc="27"; ${_DESC2019_} } "IDT"{ type="binary"; loc="28"; ${_DESC2020_} } "RRT"{ type="binary"; loc="29"; ${_DESC2021_} } "WRT"{ type="binary"; loc="30"; ${_DESC2022_} } "DEN"{ type="binary"; loc="31"; ${_DESC2023_} } } bitfield_SIPI_0_CSR0{ "Reserved0"{ type="binary"; loc="0..23"; } "RAR"{ type="binary"; loc="24"; ${_DESC2025_} } "TID[2:0]"{ type="binary"; loc="25..27"; ${_DESC2026_} } "ACKR"{ type="binary"; loc="28"; ${_DESC2027_} } "CB"{ type="binary"; loc="29"; ${_DESC2028_} } "Reserved1"{ type="binary"; loc="30..31"; } } bitfield_SIPI_0_CIR0{ "Reserved0"{ type="binary"; loc="0..25"; } "WAIE"{ type="binary"; loc="26"; } "RAIE"{ type="binary"; loc="27"; } "TCIE"{ type="binary"; loc="28"; } "TOIE"{ type="binary"; loc="29"; } "TIDIE"{ type="binary"; loc="30"; } "ACKIE"{ type="binary"; loc="31"; } } bitfield_SIPI_0_CTOR0{ "Reserved0"{ type="binary"; loc="0..23"; } "TOR"{ type="binary"; loc="24..31"; ${_DESC2031_} } } bitfield_SIPI_0_CCRC0{ "CRCI"{ type="binary"; loc="0..15"; ${_DESC2033_} } "CRCT"{ type="binary"; loc="16..31"; ${_DESC2034_} } } bitfield_SIPI_0_CAR0{ "CAR"{ type="binary"; loc="0..31"; ${_DESC2036_} } } bitfield_SIPI_0_CDR0{ "CDR"{ type="binary"; loc="0..31"; ${_DESC2038_} } } bitfield_SIPI_0_CCR1{ "Reserved0"{ type="binary"; loc="0..14"; } "TC"{ type="binary"; loc="15"; ${_DESC2040_} } "Reserved1"{ type="binary"; loc="16..23"; } "WL[1:0]"{ type="binary"; loc="24..25"; ${_DESC2041_} } "CHEN"{ type="binary"; loc="26"; ${_DESC2018_} } "ST"{ type="binary"; loc="27"; ${_DESC2042_} } "IDT"{ type="binary"; loc="28"; ${_DESC2043_} } "RRT"{ type="binary"; loc="29"; ${_DESC2044_} } "WRT"{ type="binary"; loc="30"; ${_DESC2045_} } "DEN"{ type="binary"; loc="31"; ${_DESC2023_} } } bitfield_SIPI_0_CSR1{ "Reserved0"{ type="binary"; loc="0..23"; } "RAR"{ type="binary"; loc="24"; ${_DESC2025_} } "TID[2:0]"{ type="binary"; loc="25..27"; ${_DESC2047_} } "ACKR"{ type="binary"; loc="28"; ${_DESC2027_} } "CB"{ type="binary"; loc="29"; ${_DESC2048_} } "Reserved1"{ type="binary"; loc="30..31"; } } bitfield_SIPI_0_CIR1{ "Reserved0"{ type="binary"; loc="0..25"; } "WAIE"{ type="binary"; loc="26"; ${_DESC2050_} } "RAIE"{ type="binary"; loc="27"; ${_DESC2051_} } "TCIE"{ type="binary"; loc="28"; ${_DESC2052_} } "TOIE"{ type="binary"; loc="29"; ${_DESC2053_} } "TIDIE"{ type="binary"; loc="30"; ${_DESC2054_} } "ACKIE"{ type="binary"; loc="31"; ${_DESC2055_} } } bitfield_SIPI_0_CCR2{ "Reserved0"{ type="binary"; loc="0..14"; } "TC"{ type="binary"; loc="15"; ${_DESC2061_} } "Reserved1"{ type="binary"; loc="16..23"; } "WL[1:0]"{ type="binary"; loc="24..25"; ${_DESC2017_} } "CHEN"{ type="binary"; loc="26"; ${_DESC2018_} } "ST"{ type="binary"; loc="27"; ${_DESC2042_} } "IDT"{ type="binary"; loc="28"; ${_DESC2020_} } "RRT"{ type="binary"; loc="29"; ${_DESC2021_} } "WRT"{ type="binary"; loc="30"; ${_DESC2062_} } "DEN"{ type="binary"; loc="31"; ${_DESC2063_} } } bitfield_SIPI_0_CSR2{ "Reserved0"{ type="binary"; loc="0..23"; } "RAR"{ type="binary"; loc="24"; ${_DESC2025_} } "TID[2:0]"{ type="binary"; loc="25..27"; ${_DESC2026_} } "ACKR"{ type="binary"; loc="28"; ${_DESC2027_} } "CB"{ type="binary"; loc="29"; ${_DESC2065_} } "Reserved1"{ type="binary"; loc="30..31"; } } bitfield_SIPI_0_CTOR2{ "Reserved0"{ type="binary"; loc="0..23"; } "TOR"{ type="binary"; loc="24..31"; ${_DESC2068_} } } bitfield_SIPI_0_CDR2_0{ "CDR2"{ type="binary"; loc="0..31"; ${_DESC2038_} } } bitfield_SIPI_0_CCR3{ "Reserved0"{ type="binary"; loc="0..14"; } "TC"{ type="binary"; loc="15"; ${_DESC2073_} } "Reserved1"{ type="binary"; loc="16..23"; } "WL[1:0]"{ type="binary"; loc="24..25"; ${_DESC2041_} } "CHEN"{ type="binary"; loc="26"; ${_DESC2018_} } "ST"{ type="binary"; loc="27"; ${_DESC2074_} } "IDT"{ type="binary"; loc="28"; ${_DESC2075_} } "RRT"{ type="binary"; loc="29"; ${_DESC2076_} } "WRT"{ type="binary"; loc="30"; ${_DESC2077_} } "DEN"{ type="binary"; loc="31"; ${_DESC2023_} } } bitfield_SIPI_0_CSR3{ "Reserved0"{ type="binary"; loc="0..23"; } "RAR"{ type="binary"; loc="24"; ${_DESC2025_} } "TID[2:0]"{ type="binary"; loc="25..27"; ${_DESC2026_} } "ACKR"{ type="binary"; loc="28"; ${_DESC2027_} } "CB"{ type="binary"; loc="29"; ${_DESC2079_} } "Reserved1"{ type="binary"; loc="30..31"; } } bitfield_SIPI_0_CTOR3{ "Reserved0"{ type="binary"; loc="0..23"; } "TOR"{ type="binary"; loc="24..31"; ${_DESC2082_} } } bitfield_SIPI_0_MCR{ "FRZ"{ type="binary"; loc="0"; ${_DESC2087_} } "DOZE"{ type="binary"; loc="1"; ${_DESC2088_} } "HALT"{ type="binary"; loc="2"; ${_DESC2089_} } "Reserved0"{ type="binary"; loc="3..4"; } "PRSCLR"{ type="binary"; loc="5..15"; ${_DESC2090_} } "AID"{ type="binary"; loc="16..17"; ${_DESC2091_} } "Reserved1"{ type="binary"; loc="18..20"; } "CRCIE"{ type="binary"; loc="21"; } "MCRIE"{ type="binary"; loc="22"; } "Reserved2"{ type="binary"; loc="23..26"; } "CHNSB"{ type="binary"; loc="27"; } "TEN"{ type="binary"; loc="28"; ${_DESC2092_} } "INIT"{ type="binary"; loc="29"; ${_DESC2093_} } "MOEN"{ type="binary"; loc="30"; ${_DESC2094_} } "SR"{ type="binary"; loc="31"; ${_DESC2095_} } } bitfield_SIPI_0_SR{ "FRZACK"{ type="binary"; loc="0"; ${_DESC2097_} } "LPMACK"{ type="binary"; loc="1"; ${_DESC2098_} } "Reserved0"{ type="binary"; loc="2..20"; } "GCRCE"{ type="binary"; loc="21"; ${_DESC2099_} } "MCR"{ type="binary"; loc="22"; ${_DESC2100_} } "Reserved1"{ type="binary"; loc="23"; } "TE"{ type="binary"; loc="24..27"; ${_DESC2101_} } "STATE"{ type="binary"; loc="28..31"; ${_DESC2102_} } } bitfield_SIPI_0_MAXCR{ "MXCNT"{ type="binary"; loc="0..29"; ${_DESC2104_} } "Reserved0"{ type="binary"; loc="30..31"; } } bitfield_SIPI_0_ARR{ "ADRLD"{ type="binary"; loc="0..29"; ${_DESC2106_} } "Reserved0"{ type="binary"; loc="30..31"; } } bitfield_SIPI_0_ACR{ "ADCNT"{ type="binary"; loc="0..29"; ${_DESC2108_} } "Reserved0"{ type="binary"; loc="30..31"; } } bitfield_SIPI_0_ERR{ "Reserved0"{ type="binary"; loc="0..4"; } "TOE3"{ type="binary"; loc="5"; ${_DESC2110_} } "TIDE3"{ type="binary"; loc="6"; ${_DESC2111_} } "ACKE3"{ type="binary"; loc="7"; ${_DESC2112_} } "Reserved1"{ type="binary"; loc="8..12"; } "TOE2"{ type="binary"; loc="13"; ${_DESC2113_} } "TIDE2"{ type="binary"; loc="14"; ${_DESC2114_} } "ACKE2"{ type="binary"; loc="15"; ${_DESC2115_} } "Reserved2"{ type="binary"; loc="16..20"; } "TOE1"{ type="binary"; loc="21"; ${_DESC2116_} } "TIDE1"{ type="binary"; loc="22"; ${_DESC2117_} } "ACKE1"{ type="binary"; loc="23"; ${_DESC2118_} } "Reserved3"{ type="binary"; loc="24..28"; } "TOE0"{ type="binary"; loc="29"; ${_DESC2119_} } "TIDE0"{ type="binary"; loc="30"; ${_DESC2120_} } "ACKE0"{ type="binary"; loc="31"; ${_DESC2121_} } } bitfield_SIUL2_MIDR1{ "PARTNUM"{ type="binary"; loc="0..15"; ${_DESC2123_} } "Reserved0"{ type="binary"; loc="16"; } "PKG"{ type="binary"; loc="17..21"; ${_DESC2124_} } "Reserved1"{ type="binary"; loc="22..23"; } "MAJOR_MASK"{ type="binary"; loc="24..27"; ${_DESC2125_} } "MINOR_MASK"{ type="binary"; loc="28..31"; ${_DESC2126_} } } bitfield_SIUL2_MIDR2{ "SF"{ type="binary"; loc="0"; ${_DESC2128_} } "FLASH_SIZE_1"{ type="binary"; loc="1..4"; ${_DESC2129_} } "FLASH_SIZE_2"{ type="binary"; loc="5..8"; ${_DESC2130_} } "Reserved0"{ type="binary"; loc="9..15"; } "FAMILYNUM"{ type="binary"; loc="16..23"; ${_DESC2131_} } "Reserved1"{ type="binary"; loc="24..31"; } } bitfield_SIUL2_DISR0{ "Reserved0"{ type="binary"; loc="0..20"; } "EIF10"{ type="binary"; loc="21"; ${_DESC2133_} } "Reserved1"{ type="binary"; loc="22..25"; } "EIF5"{ type="binary"; loc="26"; ${_DESC2133_} } "Reserved2"{ type="binary"; loc="27"; } "EIF3"{ type="binary"; loc="28"; ${_DESC2133_} } "EIF2"{ type="binary"; loc="29"; ${_DESC2133_} } "EIF1"{ type="binary"; loc="30"; ${_DESC2133_} } "EIF0"{ type="binary"; loc="31"; ${_DESC2133_} } } bitfield_SIUL2_DIRER0{ "Reserved0"{ type="binary"; loc="0..20"; } "EIRE10"{ type="binary"; loc="21"; ${_DESC2135_} } "Reserved1"{ type="binary"; loc="22..25"; } "EIRE5"{ type="binary"; loc="26"; ${_DESC2135_} } "Reserved2"{ type="binary"; loc="27"; } "EIRE3"{ type="binary"; loc="28"; ${_DESC2135_} } "EIRE2"{ type="binary"; loc="29"; ${_DESC2135_} } "EIRE1"{ type="binary"; loc="30"; ${_DESC2135_} } "EIRE0"{ type="binary"; loc="31"; ${_DESC2135_} } } bitfield_SIUL2_DIRSR0{ "Reserved0"{ type="binary"; loc="0..20"; } "DIRS10"{ type="binary"; loc="21"; ${_DESC2137_} } "Reserved1"{ type="binary"; loc="22..25"; } "DIRS5"{ type="binary"; loc="26"; ${_DESC2137_} } "Reserved2"{ type="binary"; loc="27"; } "DIRS3"{ type="binary"; loc="28"; ${_DESC2137_} } "DIRS2"{ type="binary"; loc="29"; ${_DESC2137_} } "DIRS1"{ type="binary"; loc="30"; ${_DESC2137_} } "DIRS0"{ type="binary"; loc="31"; ${_DESC2137_} } } bitfield_SIUL2_IREER0{ "Reserved0"{ type="binary"; loc="0..20"; } "IREE10"{ type="binary"; loc="21"; ${_DESC2139_} } "Reserved1"{ type="binary"; loc="22..25"; } "IREE5"{ type="binary"; loc="26"; ${_DESC2139_} } "Reserved2"{ type="binary"; loc="27"; } "IREE3"{ type="binary"; loc="28"; ${_DESC2139_} } "IREE2"{ type="binary"; loc="29"; ${_DESC2139_} } "IREE1"{ type="binary"; loc="30"; ${_DESC2139_} } "IREE0"{ type="binary"; loc="31"; ${_DESC2139_} } } bitfield_SIUL2_IFEER0{ "Reserved0"{ type="binary"; loc="0..20"; } "IFEE10"{ type="binary"; loc="21"; ${_DESC2141_} } "Reserved1"{ type="binary"; loc="22..25"; } "IFEE5"{ type="binary"; loc="26"; ${_DESC2141_} } "Reserved2"{ type="binary"; loc="27"; } "IFEE3"{ type="binary"; loc="28"; ${_DESC2141_} } "IFEE2"{ type="binary"; loc="29"; ${_DESC2141_} } "IFEE1"{ type="binary"; loc="30"; ${_DESC2141_} } "IFEE0"{ type="binary"; loc="31"; ${_DESC2141_} } } bitfield_SIUL2_IFER0{ "Reserved0"{ type="binary"; loc="0..20"; } "IFE10"{ type="binary"; loc="21"; ${_DESC2143_} } "Reserved1"{ type="binary"; loc="22..25"; } "IFE5"{ type="binary"; loc="26"; ${_DESC2143_} } "Reserved2"{ type="binary"; loc="27"; } "IFE3"{ type="binary"; loc="28"; ${_DESC2143_} } "IFE2"{ type="binary"; loc="29"; ${_DESC2143_} } "IFE1"{ type="binary"; loc="30"; ${_DESC2143_} } "IFE0"{ type="binary"; loc="31"; ${_DESC2143_} } } bitfield_SIUL2_IFMCR0{ "Reserved0"{ type="binary"; loc="0..27"; } "MAXCNTx"{ type="binary"; loc="28..31"; ${_DESC2145_} } } bitfield_SIUL2_IFCPR{ "Reserved0"{ type="binary"; loc="0..27"; } "IFCP"{ type="binary"; loc="28..31"; ${_DESC2147_} } } bitfield_SIUL2_MSCR_IO_0{ "Reserved0"{ type="binary"; loc="0..1"; } "OERC"{ type="binary"; loc="2..3"; ${_DESC2149_} } "Reserved1"{ type="binary"; loc="4"; } "ODC"{ type="binary"; loc="5..7"; ${_DESC2150_} } "SMC"{ type="binary"; loc="8"; ${_DESC2151_} } "APC"{ type="binary"; loc="9"; ${_DESC2152_} } "ILS"{ type="binary"; loc="10..11"; ${_DESC2153_} } "IBE"{ type="binary"; loc="12"; ${_DESC2154_} } "HYS"{ type="binary"; loc="13"; ${_DESC2155_} } "WPDE"{ type="binary"; loc="14"; ${_DESC2156_} } "WPUE"{ type="binary"; loc="15"; ${_DESC2157_} } "INV"{ type="binary"; loc="16"; ${_DESC2158_} } "Reserved2"{ type="binary"; loc="17..23"; } "SSS"{ type="binary"; loc="24..31"; ${_DESC2159_} } } bitfield_SIUL2_MSCR_MUX_512{ "Reserved0"{ type="binary"; loc="0..15"; } "INV"{ type="binary"; loc="16"; ${_DESC2158_} } "Reserved1"{ type="binary"; loc="17..23"; } "SSS"{ type="binary"; loc="24..31"; ${_DESC2159_} } } bitfield_SIUL2_GPDO0{ "Reserved0"{ type="binary"; loc="0..6"; } "PDOa"{ type="binary"; loc="7"; ${_DESC2162_} } } bitfield_SIUL2_GPDI0{ "Reserved0"{ type="binary"; loc="0..6"; } "PDIa"{ type="binary"; loc="7"; ${_DESC2164_} } } bitfield_SIUL2_PGPDO0_1{ "PPDOa"{ type="binary"; loc="0..15"; ${_DESC2166_} } "PPDOb"{ type="binary"; loc="16..31"; ${_DESC2166_} } } bitfield_SIUL2_PGPDI0_1{ "PPDIa"{ type="binary"; loc="0..15"; ${_DESC2168_} } "PPDIb"{ type="binary"; loc="16..31"; ${_DESC2168_} } } bitfield_SIUL2_MPGPDO0{ "MASK"{ type="binary"; loc="0..15"; ${_DESC2170_} } "MPPDO"{ type="binary"; loc="16..31"; ${_DESC2171_} } } bitfield_SMPU_0_CESR0{ "MERR"{ type="binary"; loc="0..15"; ${_DESC2173_} } "Reserved0"{ type="binary"; loc="16"; } "Reserved1"{ type="binary"; loc="17..27"; } "HRL"{ type="binary"; loc="28..30"; ${_DESC2174_} } "GVLD"{ type="binary"; loc="31"; ${_DESC2175_} } } bitfield_SMPU_0_CESR1{ "MEOVR"{ type="binary"; loc="0..15"; ${_DESC2177_} } "Reserved0"{ type="binary"; loc="16"; } "Reserved1"{ type="binary"; loc="17..27"; } "NRGD"{ type="binary"; loc="28..31"; ${_DESC2178_} } } bitfield_SMPU_0_EAR0{ "EADDR"{ type="binary"; loc="0..31"; ${_DESC2180_} } } bitfield_SMPU_0_EDR0{ "EACD"{ type="binary"; loc="0..23"; ${_DESC2182_} } "Reserved0"{ type="binary"; loc="24"; ${_DESC2183_} } "EATTR"{ type="binary"; loc="25..26"; ${_DESC2184_} } "ERW"{ type="binary"; loc="27"; ${_DESC2185_} } "EMN"{ type="binary"; loc="28..31"; ${_DESC2186_} } } bitfield_SMPU_0_RGD0_WORD0{ "SRTADDR"{ type="binary"; loc="0..31"; ${_DESC2188_} } } bitfield_SMPU_0_RGD0_WORD1{ "ENDADDR"{ type="binary"; loc="0..31"; ${_DESC2190_} } } bitfield_SMPU_0_RGD0_WORD2_FMT0{ "M0P"{ type="binary"; loc="0..1"; ${_DESC2192_} } "M1P"{ type="binary"; loc="2..3"; ${_DESC2193_} } "M2P"{ type="binary"; loc="4..5"; ${_DESC2194_} } "M3P"{ type="binary"; loc="6..7"; ${_DESC2195_} } "M4P"{ type="binary"; loc="8..9"; ${_DESC2196_} } "M5P"{ type="binary"; loc="10..11"; ${_DESC2197_} } "M6P"{ type="binary"; loc="12..13"; ${_DESC2198_} } "M7P"{ type="binary"; loc="14..15"; ${_DESC2199_} } "M8P"{ type="binary"; loc="16..17"; ${_DESC2200_} } "M9P"{ type="binary"; loc="18..19"; ${_DESC2201_} } "M10P"{ type="binary"; loc="20..21"; ${_DESC2202_} } "M11P"{ type="binary"; loc="22..23"; ${_DESC2203_} } "M12P"{ type="binary"; loc="24..25"; ${_DESC2204_} } "M13P"{ type="binary"; loc="26..27"; ${_DESC2205_} } "M14P"{ type="binary"; loc="28..29"; ${_DESC2206_} } "M15P"{ type="binary"; loc="30..31"; ${_DESC2207_} } } bitfield_SMPU_0_RGD0_WORD2_FMT1{ "M0S"{ type="binary"; loc="0..1"; ${_DESC2209_} } "M1S"{ type="binary"; loc="2..3"; ${_DESC2210_} } "M2S"{ type="binary"; loc="4..5"; ${_DESC2211_} } "M3S"{ type="binary"; loc="6..7"; ${_DESC2212_} } "M4S"{ type="binary"; loc="8..9"; ${_DESC2213_} } "M5S"{ type="binary"; loc="10..11"; ${_DESC2214_} } "M6S"{ type="binary"; loc="12..13"; ${_DESC2215_} } "M7S"{ type="binary"; loc="14..15"; ${_DESC2216_} } "M8S"{ type="binary"; loc="16..17"; ${_DESC2217_} } "M9S"{ type="binary"; loc="18..19"; ${_DESC2218_} } "M10S"{ type="binary"; loc="20..21"; ${_DESC2219_} } "M11S"{ type="binary"; loc="22..23"; ${_DESC2220_} } "M12S"{ type="binary"; loc="24..25"; ${_DESC2221_} } "M13S"{ type="binary"; loc="26..27"; ${_DESC2222_} } "M14S"{ type="binary"; loc="28..29"; ${_DESC2223_} } "M15S"{ type="binary"; loc="30..31"; ${_DESC2224_} } } bitfield_SMPU_0_RGD0_WORD3{ "ACCSET1"{ type="binary"; loc="0..5"; ${_DESC2226_} } "ACCSET2"{ type="binary"; loc="6..11"; ${_DESC2227_} } "ACCSET3"{ type="binary"; loc="12..17"; ${_DESC2228_} } "Reserved0"{ type="binary"; loc="18..26"; } "FMT"{ type="binary"; loc="27"; ${_DESC2229_} } "RO"{ type="binary"; loc="28"; ${_DESC2230_} } "Reserved1"{ type="binary"; loc="29"; } "CI"{ type="binary"; loc="30"; ${_DESC2231_} } "VLD"{ type="binary"; loc="31"; ${_DESC2232_} } } bitfield_SRX_0_GBL_CTRL{ "TSPRSC"{ type="binary"; loc="0..7"; ${_DESC2234_} } "Reserved0"{ type="binary"; loc="8..21"; } "FMDUIE"{ type="binary"; loc="22"; ${_DESC2235_} } "SMDUIE"{ type="binary"; loc="23"; ${_DESC2236_} } "Reserved1"{ type="binary"; loc="24"; } "Reserved2"{ type="binary"; loc="25"; } "Reserved3"{ type="binary"; loc="26"; } "FAST_CLR"{ type="binary"; loc="27"; ${_DESC2237_} } "Reserved4"{ type="binary"; loc="28"; } "DBG_FRZ"{ type="binary"; loc="29"; ${_DESC2238_} } "Reserved5"{ type="binary"; loc="30"; } "SENT_EN"{ type="binary"; loc="31"; ${_DESC2239_} } } bitfield_SRX_0_CHNL_EN{ "Reserved0"{ type="binary"; loc="0..15"; } "EN_CH[15:0]"{ type="binary"; loc="16..31"; ${_DESC2241_} } } bitfield_SRX_0_GBL_STATUS{ "Reserved0"{ type="binary"; loc="0..21"; } "FDMU"{ type="binary"; loc="22"; ${_DESC2243_} } "SMDU"{ type="binary"; loc="23"; ${_DESC2244_} } "Reserved1"{ type="binary"; loc="24..31"; } } bitfield_SRX_0_FMSG_RDY{ "Reserved0"{ type="binary"; loc="0..15"; } "F_RDY[15:0]"{ type="binary"; loc="16..31"; ${_DESC2246_} } } bitfield_SRX_0_SMSG_RDY{ "Reserved0"{ type="binary"; loc="0..15"; } "S_RDY[15:0]"{ type="binary"; loc="16..31"; ${_DESC2248_} } } bitfield_SRX_0_DATA_CTRL1{ "Reserved0"{ type="binary"; loc="0"; } "NIBBCH0"{ type="binary"; loc="1..3"; ${_DESC2250_} } "Reserved1"{ type="binary"; loc="4"; } "NIBBCH1"{ type="binary"; loc="5..7"; ${_DESC2251_} } "Reserved2"{ type="binary"; loc="8"; } "NIBBCH2"{ type="binary"; loc="9..11"; ${_DESC2252_} } "Reserved3"{ type="binary"; loc="12"; } "NIBBCH3"{ type="binary"; loc="13..15"; ${_DESC2253_} } "Reserved4"{ type="binary"; loc="16"; } "NIBBCH4"{ type="binary"; loc="17..19"; ${_DESC2254_} } "Reserved5"{ type="binary"; loc="20"; } "NIBBCH5"{ type="binary"; loc="21..23"; ${_DESC2255_} } "Reserved6"{ type="binary"; loc="24"; } "NIBBCH6"{ type="binary"; loc="25..27"; ${_DESC2256_} } "Reserved7"{ type="binary"; loc="28"; } "NIBBCH7"{ type="binary"; loc="29..31"; ${_DESC2257_} } } bitfield_SRX_0_DATA_CTRL2{ "Reserved0"{ type="binary"; loc="0"; } "NIBBCH8"{ type="binary"; loc="1..3"; ${_DESC2259_} } "Reserved1"{ type="binary"; loc="4"; } "NIBBCH9"{ type="binary"; loc="5..7"; ${_DESC2260_} } "Reserved2"{ type="binary"; loc="8"; } "NIBBCH10"{ type="binary"; loc="9..11"; ${_DESC2261_} } "Reserved3"{ type="binary"; loc="12"; } "NIBBCH11"{ type="binary"; loc="13..15"; ${_DESC2262_} } "Reserved4"{ type="binary"; loc="16"; } "NIBBCH12"{ type="binary"; loc="17..19"; ${_DESC2263_} } "Reserved5"{ type="binary"; loc="20"; } "NIBBCH13"{ type="binary"; loc="21..23"; ${_DESC2264_} } "Reserved6"{ type="binary"; loc="24"; } "NIBBCH14"{ type="binary"; loc="25..27"; ${_DESC2265_} } "Reserved7"{ type="binary"; loc="28"; } "NIBBCH15"{ type="binary"; loc="29..31"; ${_DESC2266_} } } bitfield_SRX_0_FDMA_CTRL{ "Reserved0"{ type="binary"; loc="0..15"; } "FDMA_EN[15:0]"{ type="binary"; loc="16..31"; ${_DESC2268_} } } bitfield_SRX_0_SDMA_CTRL{ "Reserved0"{ type="binary"; loc="0..15"; } "SDMA_EN[15:0]"{ type="binary"; loc="16..31"; ${_DESC2270_} } } bitfield_SRX_0_FRDY_IE{ "Reserved0"{ type="binary"; loc="0..15"; } "FRDY_IE[15:0]"{ type="binary"; loc="16..31"; ${_DESC2272_} } } bitfield_SRX_0_SRDY_IE{ "Reserved0"{ type="binary"; loc="0..15"; } "SRDY_IE[15:0]"{ type="binary"; loc="16..31"; ${_DESC2274_} } } bitfield_SRX_0_DMA_FMSG_DATA{ "CHNUM"{ type="binary"; loc="0..3"; ${_DESC2276_} } "SCNIB"{ type="binary"; loc="4..7"; ${_DESC2277_} } "DNIB1"{ type="binary"; loc="8..11"; ${_DESC2278_} } "DNIB2"{ type="binary"; loc="12..15"; ${_DESC2279_} } "DNIB3"{ type="binary"; loc="16..19"; ${_DESC2280_} } "DNIB4"{ type="binary"; loc="20..23"; ${_DESC2281_} } "DNIB5"{ type="binary"; loc="24..27"; ${_DESC2282_} } "DNIB6"{ type="binary"; loc="28..31"; ${_DESC2283_} } } bitfield_SRX_0_DMA_FMSG_CRC{ "Reserved0"{ type="binary"; loc="0..11"; } "CRC4b"{ type="binary"; loc="12..15"; ${_DESC2285_} } "Reserved1"{ type="binary"; loc="16..31"; } } bitfield_SRX_0_DMA_FMSG_TS{ "TS"{ type="binary"; loc="0..31"; ${_DESC2287_} } } bitfield_SRX_0_DMA_SMSG_BIT3{ "CHNUM"{ type="binary"; loc="0..3"; ${_DESC2276_} } "TYPE"{ type="binary"; loc="4"; ${_DESC2289_} } "Reserved0"{ type="binary"; loc="5..20"; ${_DESC2290_} } "CFG"{ type="binary"; loc="21"; ${_DESC2291_} } "ID7_4_D3_0"{ type="binary"; loc="22..25"; ${_DESC2292_} } "Reserved1"{ type="binary"; loc="26"; ${_DESC2293_} } "ID3_0_DATA15_12"{ type="binary"; loc="27..30"; ${_DESC2294_} } "Reserved2"{ type="binary"; loc="31"; ${_DESC2293_} } } bitfield_SRX_0_DMA_SMSG_BIT2{ "Reserved0"{ type="binary"; loc="0..9"; } "SMCRC"{ type="binary"; loc="10..15"; ${_DESC2296_} } "Reserved1"{ type="binary"; loc="16..19"; } "DATA[11:0]"{ type="binary"; loc="20..31"; ${_DESC2297_} } } bitfield_SRX_0_DMA_SMSG_TS{ "TS"{ type="binary"; loc="0..31"; ${_DESC2299_} } } bitfield_SRX_0_CH0_CLK_CTRL{ "Reserved0"{ type="binary"; loc="0"; } "CM_PRSC"{ type="binary"; loc="1..15"; ${_DESC2301_} } "COMP_EN"{ type="binary"; loc="16"; ${_DESC2302_} } "Reserved1"{ type="binary"; loc="17"; } "PRSC"{ type="binary"; loc="18..31"; ${_DESC2303_} } } bitfield_SRX_0_CH0_STATUS{ "BUS_IDLE"{ type="binary"; loc="0"; ${_DESC2305_} } "Reserved0"{ type="binary"; loc="1..3"; } "CAL_RESYNC"{ type="binary"; loc="4"; ${_DESC2306_} } "CAL_20_25"{ type="binary"; loc="5"; ${_DESC2307_} } "SMSG_OFLW"{ type="binary"; loc="6"; ${_DESC2308_} } "FMSG_OFLW"{ type="binary"; loc="7"; ${_DESC2309_} } "Reserved1"{ type="binary"; loc="8"; } "PP_DIAG_ERR"{ type="binary"; loc="9"; ${_DESC2310_} } "CAL_LEN_ERR"{ type="binary"; loc="10"; ${_DESC2311_} } "CAL_DIAG_ERR"{ type="binary"; loc="11"; ${_DESC2312_} } "NIB_VAL_ERR"{ type="binary"; loc="12"; ${_DESC2313_} } "SMSG_CRC_ERR"{ type="binary"; loc="13"; ${_DESC2314_} } "FMSG_CRC_ERR"{ type="binary"; loc="14"; ${_DESC2315_} } "NUM_EDGES_ERR"{ type="binary"; loc="15"; ${_DESC2316_} } "Reserved2"{ type="binary"; loc="16..31"; } } bitfield_SRX_0_CH0_CONFIG{ "BUS_IDLE_CNT"{ type="binary"; loc="0..3"; ${_DESC2318_} } "IE_CAL_RESYNC"{ type="binary"; loc="4"; ${_DESC2319_} } "IE_CAL_20_25"{ type="binary"; loc="5"; ${_DESC2320_} } "IE_SMSG_OFLW"{ type="binary"; loc="6"; ${_DESC2321_} } "IE_FMSG_OFLW"{ type="binary"; loc="7"; ${_DESC2322_} } "FCRC_CHK_OFF"{ type="binary"; loc="8"; ${_DESC2323_} } "IE_PP_DIAG_ERR"{ type="binary"; loc="9"; ${_DESC2324_} } "IE_CAL_LEN_ERR"{ type="binary"; loc="10"; ${_DESC2325_} } "IE_CAL_DIAG_ERR"{ type="binary"; loc="11"; ${_DESC2326_} } "IE_NIB_VAL_ERR"{ type="binary"; loc="12"; ${_DESC2327_} } "IE_SMSG_CRC_ERR"{ type="binary"; loc="13"; ${_DESC2328_} } "IE_FMSG_CRC_ERR"{ type="binary"; loc="14"; ${_DESC2329_} } "IE_NUM_EDGES_ERR"{ type="binary"; loc="15"; ${_DESC2330_} } "DCHNG_INT"{ type="binary"; loc="16"; ${_DESC2331_} } "CAL_RNG"{ type="binary"; loc="17"; ${_DESC2332_} } "PP_CHKSEL"{ type="binary"; loc="18"; ${_DESC2333_} } "FCRC_TYPE"{ type="binary"; loc="19"; ${_DESC2334_} } "FCRC_SC_EN"{ type="binary"; loc="20"; ${_DESC2335_} } "SCRC_TYPE"{ type="binary"; loc="21"; ${_DESC2336_} } "PAUSE_EN"{ type="binary"; loc="22"; ${_DESC2337_} } "SUCC_CAL_CHK"{ type="binary"; loc="23"; ${_DESC2338_} } "FIL_CNT"{ type="binary"; loc="24..31"; ${_DESC2339_} } } bitfield_SRX_0_CH0_SMSG_BIT3{ "CHNUM"{ type="binary"; loc="0..3"; ${_DESC2276_} } "TYPE"{ type="binary"; loc="4"; ${_DESC2289_} } "Reserved0"{ type="binary"; loc="5..20"; ${_DESC2344_} } "CFG"{ type="binary"; loc="21"; ${_DESC2291_} } "ID7_4_ID3_0"{ type="binary"; loc="22..25"; ${_DESC2292_} } "Reserved1"{ type="binary"; loc="26"; ${_DESC2293_} } "ID3_0_DATA15_12"{ type="binary"; loc="27..30"; ${_DESC2294_} } "Reserved2"{ type="binary"; loc="31"; ${_DESC2293_} } } bitfield_SSCM_STATUS{ "Reserved0"{ type="binary"; loc="0"; ${_DESC9_} } "CER"{ type="binary"; loc="1"; ${_DESC2348_} } "Reserved1"{ type="binary"; loc="2"; ${_DESC9_} } "NXEN1"{ type="binary"; loc="3"; } "NXEN"{ type="binary"; loc="4"; ${_DESC2349_} } "Reserved2"{ type="binary"; loc="5"; ${_DESC9_} } "Reserved3"{ type="binary"; loc="6"; ${_DESC9_} } "Reserved4"{ type="binary"; loc="7"; ${_DESC9_} } "BMODE"{ type="binary"; loc="8..10"; ${_DESC2350_} } "VLE"{ type="binary"; loc="11"; ${_DESC2351_} } "Reserved5"{ type="binary"; loc="12"; ${_DESC9_} } "Reserved6"{ type="binary"; loc="13"; ${_DESC9_} } "Reserved7"{ type="binary"; loc="14..15"; } } bitfield_SSCM_MEMCONFIG{ "JPIN"{ type="binary"; loc="0..9"; ${_DESC2353_} } "Reserved0"{ type="binary"; loc="10"; ${_DESC9_} } "MREV"{ type="binary"; loc="11..14"; } "Reserved1"{ type="binary"; loc="15"; } } bitfield_SSCM_ERROR{ "Reserved0"{ type="binary"; loc="0..13"; } "PAE"{ type="binary"; loc="14"; ${_DESC2355_} } "RAE"{ type="binary"; loc="15"; ${_DESC2356_} } } bitfield_SSCM_PSA{ "SADR"{ type="binary"; loc="0..31"; ${_DESC2358_} } } bitfield_SSCM_LCSTAT{ "Reserved0"{ type="binary"; loc="0..21"; } "PLC"{ type="binary"; loc="22..23"; ${_DESC2360_} } "Reserved1"{ type="binary"; loc="24..28"; } "LC"{ type="binary"; loc="29..31"; ${_DESC2361_} } } bitfield_STM_2_CR{ "-"{ type="binary"; loc="0..15"; } "CPS"{ type="binary"; loc="16..23"; ${_DESC2363_} } "-"{ type="binary"; loc="24..29"; } "FRZ"{ type="binary"; loc="30"; ${_DESC2364_} } "TEN"{ type="binary"; loc="31"; } } bitfield_STM_2_CNT{ "CNT"{ type="binary"; loc="0..31"; ${_DESC2366_} } } bitfield_STM_2_CCR0{ "-"{ type="binary"; loc="0..30"; } "CEN"{ type="binary"; loc="31"; } } bitfield_STM_2_CIR0{ "-"{ type="binary"; loc="0..30"; } "CIF"{ type="binary"; loc="31"; } } bitfield_STM_2_CMP0{ "CMP"{ type="binary"; loc="0..31"; ${_DESC2370_} } } bitfield_SWT_2_CR{ "MAP0"{ type="binary"; loc="0"; ${_DESC2372_} } "MAP1"{ type="binary"; loc="1"; ${_DESC2373_} } "MAP2"{ type="binary"; loc="2"; ${_DESC2374_} } "MAP3"{ type="binary"; loc="3"; ${_DESC2375_} } "MAP4"{ type="binary"; loc="4"; ${_DESC2376_} } "MAP5"{ type="binary"; loc="5"; ${_DESC2377_} } "MAP6"{ type="binary"; loc="6"; ${_DESC2378_} } "MAP7"{ type="binary"; loc="7"; ${_DESC2379_} } "Reserved0"{ type="binary"; loc="8..20"; } "SMD"{ type="binary"; loc="21..22"; ${_DESC2380_} } "RIA"{ type="binary"; loc="23"; ${_DESC2381_} } "WND"{ type="binary"; loc="24"; ${_DESC2382_} } "ITR"{ type="binary"; loc="25"; ${_DESC2383_} } "HLK"{ type="binary"; loc="26"; ${_DESC2384_} } "SLK"{ type="binary"; loc="27"; ${_DESC2385_} } "Reserved1"{ type="binary"; loc="28"; } "STP"{ type="binary"; loc="29"; ${_DESC2386_} } "FRZ"{ type="binary"; loc="30"; ${_DESC2387_} } "WEN"{ type="binary"; loc="31"; ${_DESC2388_} } } bitfield_SWT_2_IR{ "Reserved0"{ type="binary"; loc="0..30"; } "TIF"{ type="binary"; loc="31"; ${_DESC2390_} } } bitfield_SWT_2_TO{ "WTO"{ type="binary"; loc="0..31"; ${_DESC2392_} } } bitfield_SWT_2_WN{ "WST"{ type="binary"; loc="0..31"; ${_DESC2394_} } } bitfield_SWT_2_SR{ "Reserved0"{ type="binary"; loc="0..15"; } "WSC"{ type="binary"; loc="16..31"; ${_DESC2396_} } } bitfield_SWT_2_CO{ "CNT"{ type="binary"; loc="0..31"; ${_DESC2398_} } } bitfield_SWT_2_SK{ "Reserved0"{ type="binary"; loc="0..15"; } "SK"{ type="binary"; loc="16..31"; ${_DESC2400_} } } bitfield_WKPU_NSR{ "Reserved0"{ type="binary"; loc="0..15"; } "NIF"{ type="binary"; loc="16"; ${_DESC2402_} } "NOVF"{ type="binary"; loc="17"; ${_DESC2403_} } "Reserved1"{ type="binary"; loc="18..23"; } "RIF"{ type="binary"; loc="24"; ${_DESC2404_} } "ROVF"{ type="binary"; loc="25"; ${_DESC2405_} } "Reserved2"{ type="binary"; loc="26..31"; } } bitfield_WKPU_NCR{ "Reserved0"{ type="binary"; loc="0..15"; } "NLOCK"{ type="binary"; loc="16"; } "NDSS"{ type="binary"; loc="17..18"; } "NWRE"{ type="binary"; loc="19"; } "Reserved1"{ type="binary"; loc="20"; } "NREE"{ type="binary"; loc="21"; ${_DESC2349_} } "NFEE"{ type="binary"; loc="22"; ${_DESC2349_} } "Reserved2"{ type="binary"; loc="23"; } "RLOCK"{ type="binary"; loc="24"; } "RDSS"{ type="binary"; loc="25..26"; } "RWRE"{ type="binary"; loc="27"; } "Reserved3"{ type="binary"; loc="28"; } "RREE"{ type="binary"; loc="29"; } "RFEE"{ type="binary"; loc="30"; } "Reserved4"{ type="binary"; loc="31"; } } bitfield_WKPU_WISR{ "Reserved0"{ type="binary"; loc="0..12"; } "EIFc"{ type="binary"; loc="13"; } "EIFb"{ type="binary"; loc="14"; } "Reserved1"{ type="binary"; loc="15..16"; } "EIFa"{ type="binary"; loc="17..27"; } "Reserved2"{ type="binary"; loc="28..31"; } } bitfield_WKPU_IRER{ "Reserved0"{ type="binary"; loc="0..12"; } "EIREc"{ type="binary"; loc="13"; } "EIREb"{ type="binary"; loc="14"; } "Reserved1"{ type="binary"; loc="15..16"; } "EIREa"{ type="binary"; loc="17..27"; } "Reserved2"{ type="binary"; loc="28..31"; } } bitfield_WKPU_WIREER{ "Reserved0"{ type="binary"; loc="0..12"; } "IREEc"{ type="binary"; loc="13"; } "IREEb"{ type="binary"; loc="14"; } "Reserved1"{ type="binary"; loc="15..16"; } "IREEa"{ type="binary"; loc="17..27"; } "Reserved2"{ type="binary"; loc="28..31"; } } bitfield_WKPU_WIFEER{ "Reserved0"{ type="binary"; loc="0..12"; } "IFEEc"{ type="binary"; loc="13"; } "IFEEb"{ type="binary"; loc="14"; } "Reserved1"{ type="binary"; loc="15..16"; } "IFEEa"{ type="binary"; loc="17..27"; } "Reserved2"{ type="binary"; loc="28..31"; } } bitfield_XBAR_0_PRS0{ "Reserved0"{ type="binary"; loc="0..20"; } "M2"{ type="binary"; loc="21..23"; ${_DESC2412_} } "Reserved1"{ type="binary"; loc="24"; } "M1"{ type="binary"; loc="25..27"; ${_DESC2413_} } "Reserved2"{ type="binary"; loc="28"; } "M0"{ type="binary"; loc="29..31"; ${_DESC2414_} } } bitfield_XBAR_0_CRS0{ "RO"{ type="binary"; loc="0"; ${_DESC2416_} } "HRP"{ type="binary"; loc="1"; ${_DESC2417_} } "Reserved0"{ type="binary"; loc="2..12"; } "HPE2"{ type="binary"; loc="13"; ${_DESC2418_} } "HPE1"{ type="binary"; loc="14"; ${_DESC2419_} } "HPE0"{ type="binary"; loc="15"; ${_DESC2420_} } "Reserved1"{ type="binary"; loc="16..21"; } "ARB"{ type="binary"; loc="22..23"; ${_DESC2421_} } "Reserved2"{ type="binary"; loc="24..25"; } "PCTL"{ type="binary"; loc="26..27"; ${_DESC2422_} } "Reserved3"{ type="binary"; loc="28"; } "PARK"{ type="binary"; loc="29..31"; ${_DESC2423_} } } bitfield_XOSC_CTL{ "OSCBYP"{ type="binary"; loc="0"; ${_DESC2425_} } "Reserved0"{ type="binary"; loc="1..7"; } "EOCV"{ type="binary"; loc="8..15"; ${_DESC2426_} } "M_OSC"{ type="binary"; loc="16"; ${_DESC2427_} } "Reserved1"{ type="binary"; loc="17..18"; } "Reserved2"{ type="binary"; loc="19..23"; ${_DESC618_} } "I_OSC"{ type="binary"; loc="24"; ${_DESC2428_} } "Reserved3"{ type="binary"; loc="25..31"; } } bitfield_eDMA_0_CR{ "Reserved0"{ type="binary"; loc="0..13"; } "CX"{ type="binary"; loc="14"; ${_DESC2430_} } "ECX"{ type="binary"; loc="15"; ${_DESC2431_} } "Reserved1"{ type="binary"; loc="16..19"; } "Reserved2"{ type="binary"; loc="20..23"; } "EMLM"{ type="binary"; loc="24"; ${_DESC2432_} } "CLM"{ type="binary"; loc="25"; ${_DESC2433_} } "HALT"{ type="binary"; loc="26"; ${_DESC2434_} } "HOE"{ type="binary"; loc="27"; ${_DESC2435_} } "ERGA"{ type="binary"; loc="28"; ${_DESC2436_} } "ERCA"{ type="binary"; loc="29"; ${_DESC2437_} } "EDBG"{ type="binary"; loc="30"; ${_DESC2438_} } "Reserved3"{ type="binary"; loc="31"; } } bitfield_eDMA_0_ES{ "VLD"{ type="binary"; loc="0"; ${_DESC2440_} } "Reserved0"{ type="binary"; loc="1..13"; } "UCE"{ type="binary"; loc="14"; ${_DESC2441_} } "ECX"{ type="binary"; loc="15"; ${_DESC2442_} } "Reserved1"{ type="binary"; loc="16"; } "CPE"{ type="binary"; loc="17"; ${_DESC2443_} } "ERRCHN"{ type="binary"; loc="18..23"; ${_DESC2444_} } "SAE"{ type="binary"; loc="24"; ${_DESC2445_} } "SOE"{ type="binary"; loc="25"; ${_DESC2446_} } "DAE"{ type="binary"; loc="26"; ${_DESC2447_} } "DOE"{ type="binary"; loc="27"; ${_DESC2448_} } "NCE"{ type="binary"; loc="28"; ${_DESC2449_} } "SGE"{ type="binary"; loc="29"; ${_DESC2450_} } "SBE"{ type="binary"; loc="30"; ${_DESC2451_} } "DBE"{ type="binary"; loc="31"; ${_DESC2452_} } } bitfield_eDMA_0_ERQL{ "Reserved0"{ type="binary"; loc="0..15"; } "ERQ15"{ type="binary"; loc="16"; ${_DESC2454_} } "ERQ14"{ type="binary"; loc="17"; ${_DESC2455_} } "ERQ13"{ type="binary"; loc="18"; ${_DESC2456_} } "ERQ12"{ type="binary"; loc="19"; ${_DESC2457_} } "ERQ11"{ type="binary"; loc="20"; ${_DESC2458_} } "ERQ10"{ type="binary"; loc="21"; ${_DESC2459_} } "ERQ9"{ type="binary"; loc="22"; ${_DESC2460_} } "ERQ8"{ type="binary"; loc="23"; ${_DESC2461_} } "ERQ7"{ type="binary"; loc="24"; ${_DESC2462_} } "ERQ6"{ type="binary"; loc="25"; ${_DESC2463_} } "ERQ5"{ type="binary"; loc="26"; ${_DESC2464_} } "ERQ4"{ type="binary"; loc="27"; ${_DESC2465_} } "ERQ3"{ type="binary"; loc="28"; ${_DESC2466_} } "ERQ2"{ type="binary"; loc="29"; ${_DESC2467_} } "ERQ1"{ type="binary"; loc="30"; ${_DESC2468_} } "ERQ0"{ type="binary"; loc="31"; ${_DESC2469_} } } bitfield_eDMA_0_EEIL{ "Reserved0"{ type="binary"; loc="0..15"; } "EEI15"{ type="binary"; loc="16"; ${_DESC2471_} } "EEI14"{ type="binary"; loc="17"; ${_DESC2472_} } "EEI13"{ type="binary"; loc="18"; ${_DESC2473_} } "EEI12"{ type="binary"; loc="19"; ${_DESC2474_} } "EEI11"{ type="binary"; loc="20"; ${_DESC2475_} } "EEI10"{ type="binary"; loc="21"; ${_DESC2476_} } "EEI9"{ type="binary"; loc="22"; ${_DESC2477_} } "EEI8"{ type="binary"; loc="23"; ${_DESC2478_} } "EEI7"{ type="binary"; loc="24"; ${_DESC2479_} } "EEI6"{ type="binary"; loc="25"; ${_DESC2480_} } "EEI5"{ type="binary"; loc="26"; ${_DESC2481_} } "EEI4"{ type="binary"; loc="27"; ${_DESC2482_} } "EEI3"{ type="binary"; loc="28"; ${_DESC2483_} } "EEI2"{ type="binary"; loc="29"; ${_DESC2484_} } "EEI1"{ type="binary"; loc="30"; ${_DESC2485_} } "EEI0"{ type="binary"; loc="31"; ${_DESC2486_} } } bitfield_eDMA_0_SERQ{ "NOP"{ type="binary"; loc="0"; ${_DESC2488_} } "SAER"{ type="binary"; loc="1"; ${_DESC2489_} } "SERQ"{ type="binary"; loc="2..7"; ${_DESC2490_} } } bitfield_eDMA_0_CERQ{ "NOP"{ type="binary"; loc="0"; ${_DESC2488_} } "CAER"{ type="binary"; loc="1"; ${_DESC2492_} } "CERQ"{ type="binary"; loc="2..7"; ${_DESC2493_} } } bitfield_eDMA_0_SEEI{ "NOP"{ type="binary"; loc="0"; ${_DESC2488_} } "SAEE"{ type="binary"; loc="1"; ${_DESC2495_} } "SEEI"{ type="binary"; loc="2..7"; ${_DESC2496_} } } bitfield_eDMA_0_CEEI{ "NOP"{ type="binary"; loc="0"; ${_DESC2488_} } "CAEE"{ type="binary"; loc="1"; ${_DESC2498_} } "CEEI"{ type="binary"; loc="2..7"; ${_DESC2499_} } } bitfield_eDMA_0_CINT{ "NOP"{ type="binary"; loc="0"; ${_DESC2488_} } "CAIR"{ type="binary"; loc="1"; ${_DESC2501_} } "CINT"{ type="binary"; loc="2..7"; ${_DESC2502_} } } bitfield_eDMA_0_CERR{ "NOP"{ type="binary"; loc="0"; ${_DESC2488_} } "CAEI"{ type="binary"; loc="1"; ${_DESC2504_} } "CERR"{ type="binary"; loc="2..7"; ${_DESC2505_} } } bitfield_eDMA_0_SSRT{ "NOP"{ type="binary"; loc="0"; ${_DESC2488_} } "SAST"{ type="binary"; loc="1"; ${_DESC2507_} } "SSRT"{ type="binary"; loc="2..7"; ${_DESC2508_} } } bitfield_eDMA_0_CDNE{ "NOP"{ type="binary"; loc="0"; ${_DESC2488_} } "CADN"{ type="binary"; loc="1"; ${_DESC2510_} } "CDNE"{ type="binary"; loc="2..7"; ${_DESC2511_} } } bitfield_eDMA_0_INTL{ "Reserved0"{ type="binary"; loc="0..15"; } "INT15"{ type="binary"; loc="16"; ${_DESC2513_} } "INT14"{ type="binary"; loc="17"; ${_DESC2514_} } "INT13"{ type="binary"; loc="18"; ${_DESC2515_} } "INT12"{ type="binary"; loc="19"; ${_DESC2516_} } "INT11"{ type="binary"; loc="20"; ${_DESC2517_} } "INT10"{ type="binary"; loc="21"; ${_DESC2518_} } "INT9"{ type="binary"; loc="22"; ${_DESC2519_} } "INT8"{ type="binary"; loc="23"; ${_DESC2520_} } "INT7"{ type="binary"; loc="24"; ${_DESC2521_} } "INT6"{ type="binary"; loc="25"; ${_DESC2522_} } "INT5"{ type="binary"; loc="26"; ${_DESC2523_} } "INT4"{ type="binary"; loc="27"; ${_DESC2524_} } "INT3"{ type="binary"; loc="28"; ${_DESC2525_} } "INT2"{ type="binary"; loc="29"; ${_DESC2526_} } "INT1"{ type="binary"; loc="30"; ${_DESC2527_} } "INT0"{ type="binary"; loc="31"; ${_DESC2528_} } } bitfield_eDMA_0_ERRL{ "Reserved0"{ type="binary"; loc="0..15"; } "ERR15"{ type="binary"; loc="16"; ${_DESC2530_} } "ERR14"{ type="binary"; loc="17"; ${_DESC2531_} } "ERR13"{ type="binary"; loc="18"; ${_DESC2532_} } "ERR12"{ type="binary"; loc="19"; ${_DESC2533_} } "ERR11"{ type="binary"; loc="20"; ${_DESC2534_} } "ERR10"{ type="binary"; loc="21"; ${_DESC2535_} } "ERR9"{ type="binary"; loc="22"; ${_DESC2536_} } "ERR8"{ type="binary"; loc="23"; ${_DESC2537_} } "ERR7"{ type="binary"; loc="24"; ${_DESC2538_} } "ERR6"{ type="binary"; loc="25"; ${_DESC2539_} } "ERR5"{ type="binary"; loc="26"; ${_DESC2540_} } "ERR4"{ type="binary"; loc="27"; ${_DESC2541_} } "ERR3"{ type="binary"; loc="28"; ${_DESC2542_} } "ERR2"{ type="binary"; loc="29"; ${_DESC2543_} } "ERR1"{ type="binary"; loc="30"; ${_DESC2544_} } "ERR0"{ type="binary"; loc="31"; ${_DESC2545_} } } bitfield_eDMA_0_HRSL{ "Reserved0"{ type="binary"; loc="0..15"; } "HRS15"{ type="binary"; loc="16"; ${_DESC2547_} } "HRS14"{ type="binary"; loc="17"; ${_DESC2548_} } "HRS13"{ type="binary"; loc="18"; ${_DESC2549_} } "HRS12"{ type="binary"; loc="19"; ${_DESC2550_} } "HRS11"{ type="binary"; loc="20"; ${_DESC2551_} } "HRS10"{ type="binary"; loc="21"; ${_DESC2552_} } "HRS9"{ type="binary"; loc="22"; ${_DESC2553_} } "HRS8"{ type="binary"; loc="23"; ${_DESC2554_} } "HRS7"{ type="binary"; loc="24"; ${_DESC2555_} } "HRS6"{ type="binary"; loc="25"; ${_DESC2556_} } "HRS5"{ type="binary"; loc="26"; ${_DESC2557_} } "HRS4"{ type="binary"; loc="27"; ${_DESC2558_} } "HRS3"{ type="binary"; loc="28"; ${_DESC2559_} } "HRS2"{ type="binary"; loc="29"; ${_DESC2560_} } "HRS1"{ type="binary"; loc="30"; ${_DESC2561_} } "HRS0"{ type="binary"; loc="31"; ${_DESC2562_} } } bitfield_eDMA_0_DCHPRI0{ "ECP"{ type="binary"; loc="0"; ${_DESC2564_} } "DPA"{ type="binary"; loc="1"; ${_DESC2565_} } "Reserved0"{ type="binary"; loc="2..3"; } "CHPRI"{ type="binary"; loc="4..7"; ${_DESC2566_} } } bitfield_eDMA_0_DCHMID0{ "EMI"{ type="binary"; loc="0"; ${_DESC2568_} } "PAL"{ type="binary"; loc="1"; ${_DESC2569_} } "Reserved0"{ type="binary"; loc="2..3"; } "MID"{ type="binary"; loc="4..7"; ${_DESC2570_} } } bitfield_eDMA_0_TCD0_SADDR{ "SADDR"{ type="binary"; loc="0..31"; ${_DESC2572_} } } bitfield_eDMA_0_TCD0_ATTR{ "SMOD"{ type="binary"; loc="0..4"; ${_DESC2574_} } "SSIZE"{ type="binary"; loc="5..7"; ${_DESC2575_} } "DMOD"{ type="binary"; loc="8..12"; ${_DESC2576_} } "DSIZE"{ type="binary"; loc="13..15"; ${_DESC2577_} } } bitfield_eDMA_0_TCD0_SOFF{ "SOFF"{ type="binary"; loc="0..15"; ${_DESC2579_} } } bitfield_eDMA_0_TCD0_NBYTES_MLNO{ "NBYTES"{ type="binary"; loc="0..31"; ${_DESC2581_} } } bitfield_eDMA_0_TCD0_NBYTES_MLOFFNO{ "SMLOE"{ type="binary"; loc="0"; ${_DESC2583_} } "DMLOE"{ type="binary"; loc="1"; ${_DESC2584_} } "NBYTES"{ type="binary"; loc="2..31"; ${_DESC2585_} } } bitfield_eDMA_0_TCD0_NBYTES_MLOFFYES{ "SMLOE"{ type="binary"; loc="0"; ${_DESC2583_} } "DMLOE"{ type="binary"; loc="1"; ${_DESC2584_} } "MLOFF"{ type="binary"; loc="2..21"; ${_DESC2587_} } "NBYTES"{ type="binary"; loc="22..31"; ${_DESC2585_} } } bitfield_eDMA_0_TCD0_SLAST{ "SLAST"{ type="binary"; loc="0..31"; ${_DESC2589_} } } bitfield_eDMA_0_TCD0_DADDR{ "DADDR"{ type="binary"; loc="0..31"; ${_DESC2591_} } } bitfield_eDMA_0_TCD0_CITER_ELINKYES{ "ELINK"{ type="binary"; loc="0"; ${_DESC2593_} } "LINKCH"{ type="binary"; loc="1..6"; ${_DESC2594_} } "CITER"{ type="binary"; loc="7..15"; ${_DESC2595_} } } bitfield_eDMA_0_TCD0_CITER_ELINKNO{ "ELINK"{ type="binary"; loc="0"; ${_DESC2597_} } "CITER"{ type="binary"; loc="1..15"; ${_DESC2598_} } } bitfield_eDMA_0_TCD0_DOFF{ "DOFF"{ type="binary"; loc="0..15"; ${_DESC2600_} } } bitfield_eDMA_0_TCD0_DLASTSGA{ "DLASTSGA"{ type="binary"; loc="0..31"; ${_DESC2602_} } } bitfield_eDMA_0_TCD0_BITER_ELINKYES{ "ELINK"{ type="binary"; loc="0"; ${_DESC2604_} } "LINKCH"{ type="binary"; loc="1..6"; ${_DESC2605_} } "BITER"{ type="binary"; loc="7..15"; ${_DESC2606_} } } bitfield_eDMA_0_TCD0_BITER_ELINKNO{ "ELINK"{ type="binary"; loc="0"; ${_DESC2604_} } "BITER"{ type="binary"; loc="1..15"; ${_DESC2606_} } } bitfield_eDMA_0_TCD0_CSR{ "BWC"{ type="binary"; loc="0..1"; ${_DESC2609_} } "MAJORLINKCH"{ type="binary"; loc="2..7"; ${_DESC2610_} } "DONE"{ type="binary"; loc="8"; ${_DESC2611_} } "ACTIVE"{ type="binary"; loc="9"; ${_DESC2612_} } "MAJORELINK"{ type="binary"; loc="10"; ${_DESC2613_} } "ESG"{ type="binary"; loc="11"; ${_DESC2614_} } "DREQ"{ type="binary"; loc="12"; ${_DESC2615_} } "INTHALF"{ type="binary"; loc="13"; ${_DESC2616_} } "INTMAJOR"{ type="binary"; loc="14"; ${_DESC2617_} } "START"{ type="binary"; loc="15"; ${_DESC2618_} } } } register { CMU_PLL_CSR { address = 0xfffb0200; sn = "CMU_PLL_CSR"; access = "memorymapped"; width = 32; ${_DESC0_}; type = "bitfield_CMU_PLL_CSR" } CMU_PLL_FDR { address = 0xfffb0204; sn = "CMU_PLL_FDR"; access = "memorymapped"; width = 32; ${_DESC4_}; type = "bitfield_CMU_PLL_FDR" permission = "write/none" } CMU_PLL_HFREFR { address = 0xfffb0208; sn = "CMU_PLL_HFREFR"; access = "memorymapped"; width = 32; ${_DESC6_}; type = "bitfield_CMU_PLL_HFREFR" } CMU_PLL_LFREFR { address = 0xfffb020c; sn = "CMU_PLL_LFREFR"; access = "memorymapped"; width = 32; ${_DESC8_}; type = "bitfield_CMU_PLL_LFREFR" } CMU_PLL_ISR { address = 0xfffb0210; sn = "CMU_PLL_ISR"; access = "memorymapped"; width = 32; ${_DESC11_}; type = "bitfield_CMU_PLL_ISR" } CMU_PLL_MDR { address = 0xfffb0218; sn = "CMU_PLL_MDR"; access = "memorymapped"; width = 32; ${_DESC15_}; type = "bitfield_CMU_PLL_MDR" } DECFILTER_MCR { address = 0xfff88000; sn = "DECFILTER_MCR"; access = "memorymapped"; width = 32; ${_DESC17_}; type = "bitfield_DECFILTER_MCR" } DECFILTER_MSR { address = 0xfff88004; sn = "DECFILTER_MSR"; access = "memorymapped"; width = 32; ${_DESC35_}; type = "bitfield_DECFILTER_MSR" } DECFILTER_MXCR { address = 0xfff88008; sn = "DECFILTER_MXCR"; access = "memorymapped"; width = 32; ${_DESC52_}; type = "bitfield_DECFILTER_MXCR" } DECFILTER_MXSR { address = 0xfff8800c; sn = "DECFILTER_MXSR"; access = "memorymapped"; width = 32; ${_DESC64_}; type = "bitfield_DECFILTER_MXSR" } DECFILTER_IB { address = 0xfff88010; sn = "DECFILTER_IB"; access = "memorymapped"; width = 32; ${_DESC77_}; type = "bitfield_DECFILTER_IB" } DECFILTER_OB { address = 0xfff88014; sn = "DECFILTER_OB"; access = "memorymapped"; width = 32; ${_DESC82_}; type = "bitfield_DECFILTER_OB" permission = "write/none" } DECFILTER_COEF0 { address = 0xfff88020; sn = "DECFILTER_COEF0"; access = "memorymapped"; width = 32; ${_DESC85_}; type = "bitfield_DECFILTER_COEF0" } DECFILTER_COEF1 { address = 0xfff88024; sn = "DECFILTER_COEF1"; access = "memorymapped"; width = 32; ${_DESC85_}; type = "bitfield_DECFILTER_COEF0" } DECFILTER_COEF2 { address = 0xfff88028; sn = "DECFILTER_COEF2"; access = "memorymapped"; width = 32; ${_DESC85_}; type = "bitfield_DECFILTER_COEF0" } DECFILTER_COEF3 { address = 0xfff8802c; sn = "DECFILTER_COEF3"; access = "memorymapped"; width = 32; ${_DESC85_}; type = "bitfield_DECFILTER_COEF0" } DECFILTER_COEF4 { address = 0xfff88030; sn = "DECFILTER_COEF4"; access = "memorymapped"; width = 32; ${_DESC85_}; type = "bitfield_DECFILTER_COEF0" } DECFILTER_COEF5 { address = 0xfff88034; sn = "DECFILTER_COEF5"; access = "memorymapped"; width = 32; ${_DESC85_}; type = "bitfield_DECFILTER_COEF0" } DECFILTER_COEF6 { address = 0xfff88038; sn = "DECFILTER_COEF6"; access = "memorymapped"; width = 32; ${_DESC85_}; type = "bitfield_DECFILTER_COEF0" } DECFILTER_COEF7 { address = 0xfff8803c; sn = "DECFILTER_COEF7"; access = "memorymapped"; width = 32; ${_DESC85_}; type = "bitfield_DECFILTER_COEF0" } DECFILTER_COEF8 { address = 0xfff88040; sn = "DECFILTER_COEF8"; access = "memorymapped"; width = 32; ${_DESC85_}; type = "bitfield_DECFILTER_COEF0" } DECFILTER_TAP0 { address = 0xfff88078; sn = "DECFILTER_TAP0"; access = "memorymapped"; width = 32; ${_DESC88_}; type = "bitfield_DECFILTER_TAP0" permission = "write/none" } DECFILTER_TAP1 { address = 0xfff8807c; sn = "DECFILTER_TAP1"; access = "memorymapped"; width = 32; ${_DESC88_}; type = "bitfield_DECFILTER_TAP0" permission = "write/none" } DECFILTER_TAP2 { address = 0xfff88080; sn = "DECFILTER_TAP2"; access = "memorymapped"; width = 32; ${_DESC88_}; type = "bitfield_DECFILTER_TAP0" permission = "write/none" } DECFILTER_TAP3 { address = 0xfff88084; sn = "DECFILTER_TAP3"; access = "memorymapped"; width = 32; ${_DESC88_}; type = "bitfield_DECFILTER_TAP0" permission = "write/none" } DECFILTER_TAP4 { address = 0xfff88088; sn = "DECFILTER_TAP4"; access = "memorymapped"; width = 32; ${_DESC88_}; type = "bitfield_DECFILTER_TAP0" permission = "write/none" } DECFILTER_TAP5 { address = 0xfff8808c; sn = "DECFILTER_TAP5"; access = "memorymapped"; width = 32; ${_DESC88_}; type = "bitfield_DECFILTER_TAP0" permission = "write/none" } DECFILTER_TAP6 { address = 0xfff88090; sn = "DECFILTER_TAP6"; access = "memorymapped"; width = 32; ${_DESC88_}; type = "bitfield_DECFILTER_TAP0" permission = "write/none" } DECFILTER_TAP7 { address = 0xfff88094; sn = "DECFILTER_TAP7"; access = "memorymapped"; width = 32; ${_DESC88_}; type = "bitfield_DECFILTER_TAP0" permission = "write/none" } DECFILTER_FINTVAL { address = 0xfff880e0; sn = "DECFILTER_FINTVAL"; access = "memorymapped"; width = 32; ${_DESC91_}; type = "bitfield_DECFILTER_FINTVAL" permission = "write/none" } DECFILTER_FINTCNT { address = 0xfff880e4; sn = "DECFILTER_FINTCNT"; access = "memorymapped"; width = 32; ${_DESC93_}; type = "bitfield_DECFILTER_FINTCNT" permission = "write/none" } DECFILTER_CINTVAL { address = 0xfff880e8; sn = "DECFILTER_CINTVAL"; access = "memorymapped"; width = 32; ${_DESC95_}; type = "bitfield_DECFILTER_CINTVAL" permission = "write/none" } DECFILTER_CINTCNT { address = 0xfff880ec; sn = "DECFILTER_CINTCNT"; access = "memorymapped"; width = 32; ${_DESC97_}; type = "bitfield_DECFILTER_CINTCNT" permission = "write/none" } DMAMUX_0_CHCFG0 { address = 0xfff6c000; sn = "DMAMUX_0_CHCFG0"; access = "memorymapped"; width = 8; ${_DESC99_}; type = "bitfield_DMAMUX_0_CHCFG0" } DMAMUX_0_CHCFG1 { address = 0xfff6c001; sn = "DMAMUX_0_CHCFG1"; access = "memorymapped"; width = 8; ${_DESC99_}; type = "bitfield_DMAMUX_0_CHCFG0" } DMAMUX_0_CHCFG2 { address = 0xfff6c002; sn = "DMAMUX_0_CHCFG2"; access = "memorymapped"; width = 8; ${_DESC99_}; type = "bitfield_DMAMUX_0_CHCFG0" } DMAMUX_0_CHCFG3 { address = 0xfff6c003; sn = "DMAMUX_0_CHCFG3"; access = "memorymapped"; width = 8; ${_DESC99_}; type = "bitfield_DMAMUX_0_CHCFG0" } DMAMUX_0_CHCFG4 { address = 0xfff6c004; sn = "DMAMUX_0_CHCFG4"; access = "memorymapped"; width = 8; ${_DESC99_}; type = "bitfield_DMAMUX_0_CHCFG0" } DMAMUX_0_CHCFG5 { address = 0xfff6c005; sn = "DMAMUX_0_CHCFG5"; access = "memorymapped"; width = 8; ${_DESC99_}; type = "bitfield_DMAMUX_0_CHCFG0" } DMAMUX_0_CHCFG6 { address = 0xfff6c006; sn = "DMAMUX_0_CHCFG6"; access = "memorymapped"; width = 8; ${_DESC99_}; type = "bitfield_DMAMUX_0_CHCFG0" } DMAMUX_0_CHCFG7 { address = 0xfff6c007; sn = "DMAMUX_0_CHCFG7"; access = "memorymapped"; width = 8; ${_DESC99_}; type = "bitfield_DMAMUX_0_CHCFG0" } DMAMUX_1_CHCFG0 { address = 0xfff6c200; sn = "DMAMUX_1_CHCFG0"; access = "memorymapped"; width = 8; ${_DESC99_}; type = "bitfield_DMAMUX_0_CHCFG0" } DMAMUX_1_CHCFG1 { address = 0xfff6c201; sn = "DMAMUX_1_CHCFG1"; access = "memorymapped"; width = 8; ${_DESC99_}; type = "bitfield_DMAMUX_0_CHCFG0" } DMAMUX_1_CHCFG2 { address = 0xfff6c202; sn = "DMAMUX_1_CHCFG2"; access = "memorymapped"; width = 8; ${_DESC99_}; type = "bitfield_DMAMUX_0_CHCFG0" } DMAMUX_1_CHCFG3 { address = 0xfff6c203; sn = "DMAMUX_1_CHCFG3"; access = "memorymapped"; width = 8; ${_DESC99_}; type = "bitfield_DMAMUX_0_CHCFG0" } DMAMUX_1_CHCFG4 { address = 0xfff6c204; sn = "DMAMUX_1_CHCFG4"; access = "memorymapped"; width = 8; ${_DESC99_}; type = "bitfield_DMAMUX_0_CHCFG0" } DMAMUX_1_CHCFG5 { address = 0xfff6c205; sn = "DMAMUX_1_CHCFG5"; access = "memorymapped"; width = 8; ${_DESC99_}; type = "bitfield_DMAMUX_0_CHCFG0" } DMAMUX_1_CHCFG6 { address = 0xfff6c206; sn = "DMAMUX_1_CHCFG6"; access = "memorymapped"; width = 8; ${_DESC99_}; type = "bitfield_DMAMUX_0_CHCFG0" } DMAMUX_1_CHCFG7 { address = 0xfff6c207; sn = "DMAMUX_1_CHCFG7"; access = "memorymapped"; width = 8; ${_DESC99_}; type = "bitfield_DMAMUX_0_CHCFG0" } DSPI_0_MCR { address = 0xffe70000; sn = "DSPI_0_MCR"; access = "memorymapped"; width = 32; ${_DESC103_}; type = "bitfield_DSPI_0_MCR" } DSPI_0_TCR { address = 0xffe70008; sn = "DSPI_0_TCR"; access = "memorymapped"; width = 32; ${_DESC123_}; type = "bitfield_DSPI_0_TCR" } DSPI_0_CTAR0 { address = 0xffe7000c; sn = "DSPI_0_CTAR0"; access = "memorymapped"; width = 32; ${_DESC125_}; type = "bitfield_DSPI_0_CTAR0" } DSPI_0_CTAR_SLAVE0 { address = 0xffe7000c; sn = "DSPI_0_CTAR_SLAVE0"; access = "memorymapped"; width = 32; ${_DESC139_}; type = "bitfield_DSPI_0_CTAR_SLAVE0" } DSPI_0_CTAR1 { address = 0xffe70010; sn = "DSPI_0_CTAR1"; access = "memorymapped"; width = 32; ${_DESC125_}; type = "bitfield_DSPI_0_CTAR0" } DSPI_0_CTAR_SLAVE1 { address = 0xffe70010; sn = "DSPI_0_CTAR_SLAVE1"; access = "memorymapped"; width = 32; ${_DESC139_}; type = "bitfield_DSPI_0_CTAR_SLAVE0" } DSPI_0_CTAR2 { address = 0xffe70014; sn = "DSPI_0_CTAR2"; access = "memorymapped"; width = 32; ${_DESC125_}; type = "bitfield_DSPI_0_CTAR0" } DSPI_0_CTAR3 { address = 0xffe70018; sn = "DSPI_0_CTAR3"; access = "memorymapped"; width = 32; ${_DESC125_}; type = "bitfield_DSPI_0_CTAR0" } DSPI_0_CTAR4 { address = 0xffe7001c; sn = "DSPI_0_CTAR4"; access = "memorymapped"; width = 32; ${_DESC125_}; type = "bitfield_DSPI_0_CTAR0" } DSPI_0_CTAR5 { address = 0xffe70020; sn = "DSPI_0_CTAR5"; access = "memorymapped"; width = 32; ${_DESC125_}; type = "bitfield_DSPI_0_CTAR0" } DSPI_0_CTAR6 { address = 0xffe70024; sn = "DSPI_0_CTAR6"; access = "memorymapped"; width = 32; ${_DESC125_}; type = "bitfield_DSPI_0_CTAR0" } DSPI_0_CTAR7 { address = 0xffe70028; sn = "DSPI_0_CTAR7"; access = "memorymapped"; width = 32; ${_DESC125_}; type = "bitfield_DSPI_0_CTAR0" } DSPI_0_SR { address = 0xffe7002c; sn = "DSPI_0_SR"; access = "memorymapped"; width = 32; ${_DESC146_}; type = "bitfield_DSPI_0_SR" } DSPI_0_RSER { address = 0xffe70030; sn = "DSPI_0_RSER"; access = "memorymapped"; width = 32; ${_DESC167_}; type = "bitfield_DSPI_0_RSER" } DSPI_0_PUSHR { address = 0xffe70034; sn = "DSPI_0_PUSHR"; access = "memorymapped"; width = 32; ${_DESC186_}; type = "bitfield_DSPI_0_PUSHR" } DSPI_0_PUSHR_SLAVE { address = 0xffe70034; sn = "DSPI_0_PUSHR_SLAVE"; access = "memorymapped"; width = 32; ${_DESC195_}; type = "bitfield_DSPI_0_PUSHR_SLAVE" } DSPI_0_POPR { address = 0xffe70038; sn = "DSPI_0_POPR"; access = "memorymapped"; width = 32; ${_DESC197_}; type = "bitfield_DSPI_0_POPR" permission = "write/none" } DSPI_0_TXFR0 { address = 0xffe7003c; sn = "DSPI_0_TXFR0"; access = "memorymapped"; width = 32; ${_DESC199_}; type = "bitfield_DSPI_0_TXFR0" permission = "write/none" } DSPI_0_TXFR1 { address = 0xffe70040; sn = "DSPI_0_TXFR1"; access = "memorymapped"; width = 32; ${_DESC199_}; type = "bitfield_DSPI_0_TXFR0" permission = "write/none" } DSPI_0_TXFR2 { address = 0xffe70044; sn = "DSPI_0_TXFR2"; access = "memorymapped"; width = 32; ${_DESC199_}; type = "bitfield_DSPI_0_TXFR0" permission = "write/none" } DSPI_0_TXFR3 { address = 0xffe70048; sn = "DSPI_0_TXFR3"; access = "memorymapped"; width = 32; ${_DESC199_}; type = "bitfield_DSPI_0_TXFR0" permission = "write/none" } DSPI_0_RXFR0 { address = 0xffe7007c; sn = "DSPI_0_RXFR0"; access = "memorymapped"; width = 32; ${_DESC202_}; type = "bitfield_DSPI_0_RXFR0" permission = "write/none" } DSPI_0_RXFR1 { address = 0xffe70080; sn = "DSPI_0_RXFR1"; access = "memorymapped"; width = 32; ${_DESC202_}; type = "bitfield_DSPI_0_RXFR0" permission = "write/none" } DSPI_0_RXFR2 { address = 0xffe70084; sn = "DSPI_0_RXFR2"; access = "memorymapped"; width = 32; ${_DESC202_}; type = "bitfield_DSPI_0_RXFR0" permission = "write/none" } DSPI_0_RXFR3 { address = 0xffe70088; sn = "DSPI_0_RXFR3"; access = "memorymapped"; width = 32; ${_DESC202_}; type = "bitfield_DSPI_0_RXFR0" permission = "write/none" } DSPI_0_DSICR0 { address = 0xffe700bc; sn = "DSPI_0_DSICR0"; access = "memorymapped"; width = 32; ${_DESC204_}; type = "bitfield_DSPI_0_DSICR0" } DSPI_0_SDR0 { address = 0xffe700c0; sn = "DSPI_0_SDR0"; access = "memorymapped"; width = 32; ${_DESC220_}; type = "bitfield_DSPI_0_SDR0" permission = "write/none" } DSPI_0_ASDR0 { address = 0xffe700c4; sn = "DSPI_0_ASDR0"; access = "memorymapped"; width = 32; ${_DESC222_}; type = "bitfield_DSPI_0_ASDR0" } DSPI_0_COMPR0 { address = 0xffe700c8; sn = "DSPI_0_COMPR0"; access = "memorymapped"; width = 32; ${_DESC224_}; type = "bitfield_DSPI_0_COMPR0" permission = "write/none" } DSPI_0_DDR0 { address = 0xffe700cc; sn = "DSPI_0_DDR0"; access = "memorymapped"; width = 32; ${_DESC226_}; type = "bitfield_DSPI_0_DDR0" permission = "write/none" } DSPI_0_DSICR1 { address = 0xffe700d0; sn = "DSPI_0_DSICR1"; access = "memorymapped"; width = 32; ${_DESC228_}; type = "bitfield_DSPI_0_DSICR1" } DSPI_0_SSR0 { address = 0xffe700d4; sn = "DSPI_0_SSR0"; access = "memorymapped"; width = 32; ${_DESC235_}; type = "bitfield_DSPI_0_SSR0" } DSPI_0_PISR0 { address = 0xffe700d8; sn = "DSPI_0_PISR0"; access = "memorymapped"; width = 32; ${_DESC237_}; type = "bitfield_DSPI_0_PISR0" } DSPI_0_PISR1 { address = 0xffe700dc; sn = "DSPI_0_PISR1"; access = "memorymapped"; width = 32; ${_DESC246_}; type = "bitfield_DSPI_0_PISR1" } DSPI_0_PISR2 { address = 0xffe700e0; sn = "DSPI_0_PISR2"; access = "memorymapped"; width = 32; ${_DESC255_}; type = "bitfield_DSPI_0_PISR2" } DSPI_0_PISR3 { address = 0xffe700e4; sn = "DSPI_0_PISR3"; access = "memorymapped"; width = 32; ${_DESC264_}; type = "bitfield_DSPI_0_PISR3" } DSPI_0_DIMR0 { address = 0xffe700e8; sn = "DSPI_0_DIMR0"; access = "memorymapped"; width = 32; ${_DESC273_}; type = "bitfield_DSPI_0_DIMR0" } DSPI_0_DPIR0 { address = 0xffe700ec; sn = "DSPI_0_DPIR0"; access = "memorymapped"; width = 32; ${_DESC275_}; type = "bitfield_DSPI_0_DPIR0" } DSPI_0_SDR1 { address = 0xffe700f0; sn = "DSPI_0_SDR1"; access = "memorymapped"; width = 32; ${_DESC277_}; type = "bitfield_DSPI_0_SDR1" permission = "write/none" } DSPI_0_ASDR1 { address = 0xffe700f4; sn = "DSPI_0_ASDR1"; access = "memorymapped"; width = 32; ${_DESC279_}; type = "bitfield_DSPI_0_ASDR1" } DSPI_0_COMPR1 { address = 0xffe700f8; sn = "DSPI_0_COMPR1"; access = "memorymapped"; width = 32; ${_DESC281_}; type = "bitfield_DSPI_0_COMPR1" permission = "write/none" } DSPI_0_DDR1 { address = 0xffe700fc; sn = "DSPI_0_DDR1"; access = "memorymapped"; width = 32; ${_DESC283_}; type = "bitfield_DSPI_0_DDR1" permission = "write/none" } DSPI_0_SSR1 { address = 0xffe70100; sn = "DSPI_0_SSR1"; access = "memorymapped"; width = 32; ${_DESC285_}; type = "bitfield_DSPI_0_SSR1" } DSPI_0_PISR4 { address = 0xffe70104; sn = "DSPI_0_PISR4"; access = "memorymapped"; width = 32; ${_DESC287_}; type = "bitfield_DSPI_0_PISR4" } DSPI_0_PISR5 { address = 0xffe70108; sn = "DSPI_0_PISR5"; access = "memorymapped"; width = 32; ${_DESC296_}; type = "bitfield_DSPI_0_PISR5" } DSPI_0_PISR6 { address = 0xffe7010c; sn = "DSPI_0_PISR6"; access = "memorymapped"; width = 32; ${_DESC305_}; type = "bitfield_DSPI_0_PISR6" } DSPI_0_PISR7 { address = 0xffe70110; sn = "DSPI_0_PISR7"; access = "memorymapped"; width = 32; ${_DESC314_}; type = "bitfield_DSPI_0_PISR7" } DSPI_0_DIMR1 { address = 0xffe70114; sn = "DSPI_0_DIMR1"; access = "memorymapped"; width = 32; ${_DESC323_}; type = "bitfield_DSPI_0_DIMR1" } DSPI_0_DPIR1 { address = 0xffe70118; sn = "DSPI_0_DPIR1"; access = "memorymapped"; width = 32; ${_DESC325_}; type = "bitfield_DSPI_0_DPIR1" } DSPI_0_CTARE0 { address = 0xffe7011c; sn = "DSPI_0_CTARE0"; access = "memorymapped"; width = 32; ${_DESC327_}; type = "bitfield_DSPI_0_CTARE0" } DSPI_0_CTARE1 { address = 0xffe70120; sn = "DSPI_0_CTARE1"; access = "memorymapped"; width = 32; ${_DESC327_}; type = "bitfield_DSPI_0_CTARE0" } DSPI_0_CTARE2 { address = 0xffe70124; sn = "DSPI_0_CTARE2"; access = "memorymapped"; width = 32; ${_DESC327_}; type = "bitfield_DSPI_0_CTARE0" } DSPI_0_CTARE3 { address = 0xffe70128; sn = "DSPI_0_CTARE3"; access = "memorymapped"; width = 32; ${_DESC327_}; type = "bitfield_DSPI_0_CTARE0" } DSPI_0_CTARE4 { address = 0xffe7012c; sn = "DSPI_0_CTARE4"; access = "memorymapped"; width = 32; ${_DESC327_}; type = "bitfield_DSPI_0_CTARE0" } DSPI_0_CTARE5 { address = 0xffe70130; sn = "DSPI_0_CTARE5"; access = "memorymapped"; width = 32; ${_DESC327_}; type = "bitfield_DSPI_0_CTARE0" } DSPI_0_CTARE6 { address = 0xffe70134; sn = "DSPI_0_CTARE6"; access = "memorymapped"; width = 32; ${_DESC327_}; type = "bitfield_DSPI_0_CTARE0" } DSPI_0_CTARE7 { address = 0xffe70138; sn = "DSPI_0_CTARE7"; access = "memorymapped"; width = 32; ${_DESC327_}; type = "bitfield_DSPI_0_CTARE0" } DSPI_0_SREX { address = 0xffe7013c; sn = "DSPI_0_SREX"; access = "memorymapped"; width = 32; ${_DESC330_}; type = "bitfield_DSPI_0_SREX" permission = "write/none" } DSPI_4_MCR { address = 0xffe78000; sn = "DSPI_4_MCR"; access = "memorymapped"; width = 32; ${_DESC103_}; type = "bitfield_DSPI_0_MCR" } DSPI_4_TCR { address = 0xffe78008; sn = "DSPI_4_TCR"; access = "memorymapped"; width = 32; ${_DESC123_}; type = "bitfield_DSPI_0_TCR" } DSPI_4_CTAR0 { address = 0xffe7800c; sn = "DSPI_4_CTAR0"; access = "memorymapped"; width = 32; ${_DESC125_}; type = "bitfield_DSPI_0_CTAR0" } DSPI_4_CTAR_SLAVE0 { address = 0xffe7800c; sn = "DSPI_4_CTAR_SLAVE0"; access = "memorymapped"; width = 32; ${_DESC139_}; type = "bitfield_DSPI_0_CTAR_SLAVE0" } DSPI_4_CTAR1 { address = 0xffe78010; sn = "DSPI_4_CTAR1"; access = "memorymapped"; width = 32; ${_DESC125_}; type = "bitfield_DSPI_0_CTAR0" } DSPI_4_CTAR_SLAVE1 { address = 0xffe78010; sn = "DSPI_4_CTAR_SLAVE1"; access = "memorymapped"; width = 32; ${_DESC139_}; type = "bitfield_DSPI_0_CTAR_SLAVE0" } DSPI_4_CTAR2 { address = 0xffe78014; sn = "DSPI_4_CTAR2"; access = "memorymapped"; width = 32; ${_DESC125_}; type = "bitfield_DSPI_0_CTAR0" } DSPI_4_CTAR3 { address = 0xffe78018; sn = "DSPI_4_CTAR3"; access = "memorymapped"; width = 32; ${_DESC125_}; type = "bitfield_DSPI_0_CTAR0" } DSPI_4_CTAR4 { address = 0xffe7801c; sn = "DSPI_4_CTAR4"; access = "memorymapped"; width = 32; ${_DESC125_}; type = "bitfield_DSPI_0_CTAR0" } DSPI_4_CTAR5 { address = 0xffe78020; sn = "DSPI_4_CTAR5"; access = "memorymapped"; width = 32; ${_DESC125_}; type = "bitfield_DSPI_0_CTAR0" } DSPI_4_CTAR6 { address = 0xffe78024; sn = "DSPI_4_CTAR6"; access = "memorymapped"; width = 32; ${_DESC125_}; type = "bitfield_DSPI_0_CTAR0" } DSPI_4_CTAR7 { address = 0xffe78028; sn = "DSPI_4_CTAR7"; access = "memorymapped"; width = 32; ${_DESC125_}; type = "bitfield_DSPI_0_CTAR0" } DSPI_4_SR { address = 0xffe7802c; sn = "DSPI_4_SR"; access = "memorymapped"; width = 32; ${_DESC146_}; type = "bitfield_DSPI_0_SR" } DSPI_4_RSER { address = 0xffe78030; sn = "DSPI_4_RSER"; access = "memorymapped"; width = 32; ${_DESC167_}; type = "bitfield_DSPI_0_RSER" } DSPI_4_PUSHR { address = 0xffe78034; sn = "DSPI_4_PUSHR"; access = "memorymapped"; width = 32; ${_DESC186_}; type = "bitfield_DSPI_0_PUSHR" } DSPI_4_PUSHR_SLAVE { address = 0xffe78034; sn = "DSPI_4_PUSHR_SLAVE"; access = "memorymapped"; width = 32; ${_DESC195_}; type = "bitfield_DSPI_0_PUSHR_SLAVE" } DSPI_4_POPR { address = 0xffe78038; sn = "DSPI_4_POPR"; access = "memorymapped"; width = 32; ${_DESC197_}; type = "bitfield_DSPI_0_POPR" permission = "write/none" } DSPI_4_TXFR0 { address = 0xffe7803c; sn = "DSPI_4_TXFR0"; access = "memorymapped"; width = 32; ${_DESC199_}; type = "bitfield_DSPI_0_TXFR0" permission = "write/none" } DSPI_4_TXFR1 { address = 0xffe78040; sn = "DSPI_4_TXFR1"; access = "memorymapped"; width = 32; ${_DESC199_}; type = "bitfield_DSPI_0_TXFR0" permission = "write/none" } DSPI_4_TXFR2 { address = 0xffe78044; sn = "DSPI_4_TXFR2"; access = "memorymapped"; width = 32; ${_DESC199_}; type = "bitfield_DSPI_0_TXFR0" permission = "write/none" } DSPI_4_TXFR3 { address = 0xffe78048; sn = "DSPI_4_TXFR3"; access = "memorymapped"; width = 32; ${_DESC199_}; type = "bitfield_DSPI_0_TXFR0" permission = "write/none" } DSPI_4_RXFR0 { address = 0xffe7807c; sn = "DSPI_4_RXFR0"; access = "memorymapped"; width = 32; ${_DESC202_}; type = "bitfield_DSPI_0_RXFR0" permission = "write/none" } DSPI_4_RXFR1 { address = 0xffe78080; sn = "DSPI_4_RXFR1"; access = "memorymapped"; width = 32; ${_DESC202_}; type = "bitfield_DSPI_0_RXFR0" permission = "write/none" } DSPI_4_RXFR2 { address = 0xffe78084; sn = "DSPI_4_RXFR2"; access = "memorymapped"; width = 32; ${_DESC202_}; type = "bitfield_DSPI_0_RXFR0" permission = "write/none" } DSPI_4_RXFR3 { address = 0xffe78088; sn = "DSPI_4_RXFR3"; access = "memorymapped"; width = 32; ${_DESC202_}; type = "bitfield_DSPI_0_RXFR0" permission = "write/none" } DSPI_4_DSICR0 { address = 0xffe780bc; sn = "DSPI_4_DSICR0"; access = "memorymapped"; width = 32; ${_DESC204_}; type = "bitfield_DSPI_0_DSICR0" } DSPI_4_SDR0 { address = 0xffe780c0; sn = "DSPI_4_SDR0"; access = "memorymapped"; width = 32; ${_DESC220_}; type = "bitfield_DSPI_0_SDR0" permission = "write/none" } DSPI_4_ASDR0 { address = 0xffe780c4; sn = "DSPI_4_ASDR0"; access = "memorymapped"; width = 32; ${_DESC222_}; type = "bitfield_DSPI_0_ASDR0" } DSPI_4_COMPR0 { address = 0xffe780c8; sn = "DSPI_4_COMPR0"; access = "memorymapped"; width = 32; ${_DESC224_}; type = "bitfield_DSPI_0_COMPR0" permission = "write/none" } DSPI_4_DDR0 { address = 0xffe780cc; sn = "DSPI_4_DDR0"; access = "memorymapped"; width = 32; ${_DESC226_}; type = "bitfield_DSPI_0_DDR0" permission = "write/none" } DSPI_4_DSICR1 { address = 0xffe780d0; sn = "DSPI_4_DSICR1"; access = "memorymapped"; width = 32; ${_DESC228_}; type = "bitfield_DSPI_0_DSICR1" } DSPI_4_SSR0 { address = 0xffe780d4; sn = "DSPI_4_SSR0"; access = "memorymapped"; width = 32; ${_DESC235_}; type = "bitfield_DSPI_0_SSR0" } DSPI_4_PISR0 { address = 0xffe780d8; sn = "DSPI_4_PISR0"; access = "memorymapped"; width = 32; ${_DESC237_}; type = "bitfield_DSPI_0_PISR0" } DSPI_4_PISR1 { address = 0xffe780dc; sn = "DSPI_4_PISR1"; access = "memorymapped"; width = 32; ${_DESC246_}; type = "bitfield_DSPI_0_PISR1" } DSPI_4_PISR2 { address = 0xffe780e0; sn = "DSPI_4_PISR2"; access = "memorymapped"; width = 32; ${_DESC255_}; type = "bitfield_DSPI_0_PISR2" } DSPI_4_PISR3 { address = 0xffe780e4; sn = "DSPI_4_PISR3"; access = "memorymapped"; width = 32; ${_DESC264_}; type = "bitfield_DSPI_0_PISR3" } DSPI_4_DIMR0 { address = 0xffe780e8; sn = "DSPI_4_DIMR0"; access = "memorymapped"; width = 32; ${_DESC273_}; type = "bitfield_DSPI_0_DIMR0" } DSPI_4_DPIR0 { address = 0xffe780ec; sn = "DSPI_4_DPIR0"; access = "memorymapped"; width = 32; ${_DESC275_}; type = "bitfield_DSPI_0_DPIR0" } DSPI_4_SDR1 { address = 0xffe780f0; sn = "DSPI_4_SDR1"; access = "memorymapped"; width = 32; ${_DESC277_}; type = "bitfield_DSPI_0_SDR1" permission = "write/none" } DSPI_4_ASDR1 { address = 0xffe780f4; sn = "DSPI_4_ASDR1"; access = "memorymapped"; width = 32; ${_DESC279_}; type = "bitfield_DSPI_0_ASDR1" } DSPI_4_COMPR1 { address = 0xffe780f8; sn = "DSPI_4_COMPR1"; access = "memorymapped"; width = 32; ${_DESC281_}; type = "bitfield_DSPI_0_COMPR1" permission = "write/none" } DSPI_4_DDR1 { address = 0xffe780fc; sn = "DSPI_4_DDR1"; access = "memorymapped"; width = 32; ${_DESC283_}; type = "bitfield_DSPI_0_DDR1" permission = "write/none" } DSPI_4_SSR1 { address = 0xffe78100; sn = "DSPI_4_SSR1"; access = "memorymapped"; width = 32; ${_DESC285_}; type = "bitfield_DSPI_0_SSR1" } DSPI_4_PISR4 { address = 0xffe78104; sn = "DSPI_4_PISR4"; access = "memorymapped"; width = 32; ${_DESC287_}; type = "bitfield_DSPI_0_PISR4" } DSPI_4_PISR5 { address = 0xffe78108; sn = "DSPI_4_PISR5"; access = "memorymapped"; width = 32; ${_DESC296_}; type = "bitfield_DSPI_0_PISR5" } DSPI_4_PISR6 { address = 0xffe7810c; sn = "DSPI_4_PISR6"; access = "memorymapped"; width = 32; ${_DESC305_}; type = "bitfield_DSPI_0_PISR6" } DSPI_4_PISR7 { address = 0xffe78110; sn = "DSPI_4_PISR7"; access = "memorymapped"; width = 32; ${_DESC314_}; type = "bitfield_DSPI_0_PISR7" } DSPI_4_DIMR1 { address = 0xffe78114; sn = "DSPI_4_DIMR1"; access = "memorymapped"; width = 32; ${_DESC323_}; type = "bitfield_DSPI_0_DIMR1" } DSPI_4_DPIR1 { address = 0xffe78118; sn = "DSPI_4_DPIR1"; access = "memorymapped"; width = 32; ${_DESC325_}; type = "bitfield_DSPI_0_DPIR1" } DSPI_4_CTARE0 { address = 0xffe7811c; sn = "DSPI_4_CTARE0"; access = "memorymapped"; width = 32; ${_DESC327_}; type = "bitfield_DSPI_0_CTARE0" } DSPI_4_CTARE1 { address = 0xffe78120; sn = "DSPI_4_CTARE1"; access = "memorymapped"; width = 32; ${_DESC327_}; type = "bitfield_DSPI_0_CTARE0" } DSPI_4_CTARE2 { address = 0xffe78124; sn = "DSPI_4_CTARE2"; access = "memorymapped"; width = 32; ${_DESC327_}; type = "bitfield_DSPI_0_CTARE0" } DSPI_4_CTARE3 { address = 0xffe78128; sn = "DSPI_4_CTARE3"; access = "memorymapped"; width = 32; ${_DESC327_}; type = "bitfield_DSPI_0_CTARE0" } DSPI_4_CTARE4 { address = 0xffe7812c; sn = "DSPI_4_CTARE4"; access = "memorymapped"; width = 32; ${_DESC327_}; type = "bitfield_DSPI_0_CTARE0" } DSPI_4_CTARE5 { address = 0xffe78130; sn = "DSPI_4_CTARE5"; access = "memorymapped"; width = 32; ${_DESC327_}; type = "bitfield_DSPI_0_CTARE0" } DSPI_4_CTARE6 { address = 0xffe78134; sn = "DSPI_4_CTARE6"; access = "memorymapped"; width = 32; ${_DESC327_}; type = "bitfield_DSPI_0_CTARE0" } DSPI_4_CTARE7 { address = 0xffe78138; sn = "DSPI_4_CTARE7"; access = "memorymapped"; width = 32; ${_DESC327_}; type = "bitfield_DSPI_0_CTARE0" } DSPI_4_SREX { address = 0xffe7813c; sn = "DSPI_4_SREX"; access = "memorymapped"; width = 32; ${_DESC330_}; type = "bitfield_DSPI_0_SREX" permission = "write/none" } DTS_ENABLE { address = 0xfff38000; sn = "DTS_ENABLE"; access = "memorymapped"; width = 32; ${_DESC333_}; type = "bitfield_DTS_ENABLE" } DTS_STARTUP { address = 0xfff38004; sn = "DTS_STARTUP"; access = "memorymapped"; width = 32; ${_DESC336_}; type = "bitfield_DTS_STARTUP" } DTS_SEMAPHORE { address = 0xfff38008; sn = "DTS_SEMAPHORE"; access = "memorymapped"; width = 32; ${_DESC338_}; type = "bitfield_DTS_SEMAPHORE" } DTS_SEMAPHORE_B { address = 0xfff3800c; sn = "DTS_SEMAPHORE_B"; access = "memorymapped"; width = 32; ${_DESC340_}; type = "bitfield_DTS_SEMAPHORE_B" } EIMCR { address = 0xfc0dc000; sn = "EIMCR"; access = "memorymapped"; width = 32; ${_DESC342_}; type = "bitfield_EIMCR" } EIM_EICHEN { address = 0xfc0dc004; sn = "EIM_EICHEN"; access = "memorymapped"; width = 32; ${_DESC344_}; type = "bitfield_EIM_EICHEN" } EIM_EICHD0_Word0 { address = 0xfc0dc100; sn = "EIM_EICHD0_Word0"; access = "memorymapped"; width = 32; ${_DESC346_}; type = "bitfield_EIM_EICHD0_Word0" } EIM_EICHD0_Word1 { address = 0xfc0dc104; sn = "EIM_EICHD0_Word1"; access = "memorymapped"; width = 32; ${_DESC348_}; type = "bitfield_EIM_EICHD0_Word1" } EIM_EICHD0_Word2 { address = 0xfc0dc108; sn = "EIM_EICHD0_Word2"; access = "memorymapped"; width = 32; ${_DESC350_}; type = "bitfield_EIM_EICHD0_Word2" } EIM_EICHD1_Word0 { address = 0xfc0dc200; sn = "EIM_EICHD1_Word0"; access = "memorymapped"; width = 32; ${_DESC346_}; type = "bitfield_EIM_EICHD0_Word0" } EIM_EICHD1_Word1 { address = 0xfc0dc204; sn = "EIM_EICHD1_Word1"; access = "memorymapped"; width = 32; ${_DESC348_}; type = "bitfield_EIM_EICHD0_Word1" } EIM_EICHD1_Word2 { address = 0xfc0dc208; sn = "EIM_EICHD1_Word2"; access = "memorymapped"; width = 32; ${_DESC350_}; type = "bitfield_EIM_EICHD0_Word2" } EIM_EICHD2_Word0 { address = 0xfc0dc300; sn = "EIM_EICHD2_Word0"; access = "memorymapped"; width = 32; ${_DESC346_}; type = "bitfield_EIM_EICHD0_Word0" } EIM_EICHD2_Word1 { address = 0xfc0dc304; sn = "EIM_EICHD2_Word1"; access = "memorymapped"; width = 32; ${_DESC348_}; type = "bitfield_EIM_EICHD0_Word1" } EIM_EICHD2_Word2 { address = 0xfc0dc308; sn = "EIM_EICHD2_Word2"; access = "memorymapped"; width = 32; ${_DESC350_}; type = "bitfield_EIM_EICHD0_Word2" } EIM_EICHD3_Word0 { address = 0xfc0dc400; sn = "EIM_EICHD3_Word0"; access = "memorymapped"; width = 32; ${_DESC346_}; type = "bitfield_EIM_EICHD0_Word0" } EIM_EICHD3_Word1 { address = 0xfc0dc404; sn = "EIM_EICHD3_Word1"; access = "memorymapped"; width = 32; ${_DESC348_}; type = "bitfield_EIM_EICHD0_Word1" } EIM_EICHD3_Word2 { address = 0xfc0dc408; sn = "EIM_EICHD3_Word2"; access = "memorymapped"; width = 32; ${_DESC350_}; type = "bitfield_EIM_EICHD0_Word2" } EIM_EICHD4_Word0 { address = 0xfc0dc500; sn = "EIM_EICHD4_Word0"; access = "memorymapped"; width = 32; ${_DESC346_}; type = "bitfield_EIM_EICHD0_Word0" } EIM_EICHD4_Word1 { address = 0xfc0dc504; sn = "EIM_EICHD4_Word1"; access = "memorymapped"; width = 32; ${_DESC348_}; type = "bitfield_EIM_EICHD0_Word1" } EIM_EICHD4_Word2 { address = 0xfc0dc508; sn = "EIM_EICHD4_Word2"; access = "memorymapped"; width = 32; ${_DESC350_}; type = "bitfield_EIM_EICHD0_Word2" } EIM_EICHD5_Word0 { address = 0xfc0dc600; sn = "EIM_EICHD5_Word0"; access = "memorymapped"; width = 32; ${_DESC346_}; type = "bitfield_EIM_EICHD0_Word0" } EIM_EICHD5_Word1 { address = 0xfc0dc604; sn = "EIM_EICHD5_Word1"; access = "memorymapped"; width = 32; ${_DESC348_}; type = "bitfield_EIM_EICHD0_Word1" } EIM_EICHD5_Word2 { address = 0xfc0dc608; sn = "EIM_EICHD5_Word2"; access = "memorymapped"; width = 32; ${_DESC350_}; type = "bitfield_EIM_EICHD0_Word2" } ERM_CR { address = 0xfc0e0000; sn = "ERM_CR"; access = "memorymapped"; width = 32; ${_DESC352_}; type = "bitfield_ERM_CR" } ERM_SR { address = 0xfc0e0010; sn = "ERM_SR"; access = "memorymapped"; width = 32; ${_DESC369_}; type = "bitfield_ERM_SR" } ERM_EAR0 { address = 0xfc0e0100; sn = "ERM_EAR0"; access = "memorymapped"; width = 32; ${_DESC386_}; type = "bitfield_ERM_EAR0" permission = "write/none" } ERM_SYN0 { address = 0xfc0e0104; sn = "ERM_SYN0"; access = "memorymapped"; width = 32; ${_DESC388_}; type = "bitfield_ERM_SYN0" permission = "write/none" } ERM_EAR1 { address = 0xfc0e0110; sn = "ERM_EAR1"; access = "memorymapped"; width = 32; ${_DESC386_}; type = "bitfield_ERM_EAR0" permission = "write/none" } ERM_SYN1 { address = 0xfc0e0114; sn = "ERM_SYN1"; access = "memorymapped"; width = 32; ${_DESC388_}; type = "bitfield_ERM_SYN0" permission = "write/none" } ERM_EAR2 { address = 0xfc0e0120; sn = "ERM_EAR2"; access = "memorymapped"; width = 32; ${_DESC386_}; type = "bitfield_ERM_EAR0" permission = "write/none" } ERM_SYN2 { address = 0xfc0e0124; sn = "ERM_SYN2"; access = "memorymapped"; width = 32; ${_DESC388_}; type = "bitfield_ERM_SYN0" permission = "write/none" } ERM_EAR3 { address = 0xfc0e0130; sn = "ERM_EAR3"; access = "memorymapped"; width = 32; ${_DESC386_}; type = "bitfield_ERM_EAR0" permission = "write/none" } ERM_SYN3 { address = 0xfc0e0134; sn = "ERM_SYN3"; access = "memorymapped"; width = 32; ${_DESC388_}; type = "bitfield_ERM_SYN0" permission = "write/none" } ERM_EAR4 { address = 0xfc0e0140; sn = "ERM_EAR4"; access = "memorymapped"; width = 32; ${_DESC386_}; type = "bitfield_ERM_EAR0" permission = "write/none" } ERM_SYN4 { address = 0xfc0e0144; sn = "ERM_SYN4"; access = "memorymapped"; width = 32; ${_DESC388_}; type = "bitfield_ERM_SYN0" permission = "write/none" } ERM_EAR5 { address = 0xfc0e0150; sn = "ERM_EAR5"; access = "memorymapped"; width = 32; ${_DESC386_}; type = "bitfield_ERM_EAR0" permission = "write/none" } ERM_SYN5 { address = 0xfc0e0154; sn = "ERM_SYN5"; access = "memorymapped"; width = 32; ${_DESC388_}; type = "bitfield_ERM_SYN0" permission = "write/none" } ERM_EAR6 { address = 0xfc0e0160; sn = "ERM_EAR6"; access = "memorymapped"; width = 32; ${_DESC386_}; type = "bitfield_ERM_EAR0" permission = "write/none" } ERM_SYN6 { address = 0xfc0e0164; sn = "ERM_SYN6"; access = "memorymapped"; width = 32; ${_DESC388_}; type = "bitfield_ERM_SYN0" permission = "write/none" } ERM_EAR7 { address = 0xfc0e0170; sn = "ERM_EAR7"; access = "memorymapped"; width = 32; ${_DESC386_}; type = "bitfield_ERM_EAR0" permission = "write/none" } ERM_SYN7 { address = 0xfc0e0174; sn = "ERM_SYN7"; access = "memorymapped"; width = 32; ${_DESC388_}; type = "bitfield_ERM_SYN0" permission = "write/none" } FEC_EIR { address = 0xfc0b0004; sn = "FEC_EIR"; access = "memorymapped"; width = 32; ${_DESC390_}; type = "bitfield_FEC_EIR" } FEC_EIMR { address = 0xfc0b0008; sn = "FEC_EIMR"; access = "memorymapped"; width = 32; ${_DESC404_}; type = "bitfield_FEC_EIMR" } FEC_RDAR { address = 0xfc0b0010; sn = "FEC_RDAR"; access = "memorymapped"; width = 32; ${_DESC418_}; type = "bitfield_FEC_RDAR" } FEC_TDAR { address = 0xfc0b0014; sn = "FEC_TDAR"; access = "memorymapped"; width = 32; ${_DESC420_}; type = "bitfield_FEC_TDAR" } FEC_ECR { address = 0xfc0b0024; sn = "FEC_ECR"; access = "memorymapped"; width = 32; ${_DESC422_}; type = "bitfield_FEC_ECR" } FEC_MMFR { address = 0xfc0b0040; sn = "FEC_MMFR"; access = "memorymapped"; width = 32; ${_DESC425_}; type = "bitfield_FEC_MMFR" } FEC_MSCR { address = 0xfc0b0044; sn = "FEC_MSCR"; access = "memorymapped"; width = 32; ${_DESC432_}; type = "bitfield_FEC_MSCR" } FEC_MIBC { address = 0xfc0b0064; sn = "FEC_MIBC"; access = "memorymapped"; width = 32; ${_DESC435_}; type = "bitfield_FEC_MIBC" } FEC_RCR { address = 0xfc0b0084; sn = "FEC_RCR"; access = "memorymapped"; width = 32; ${_DESC438_}; type = "bitfield_FEC_RCR" } FEC_TCR { address = 0xfc0b00c4; sn = "FEC_TCR"; access = "memorymapped"; width = 32; ${_DESC450_}; type = "bitfield_FEC_TCR" } FEC_PALR { address = 0xfc0b00e4; sn = "FEC_PALR"; access = "memorymapped"; width = 32; ${_DESC456_}; type = "bitfield_FEC_PALR" } FEC_PAUR { address = 0xfc0b00e8; sn = "FEC_PAUR"; access = "memorymapped"; width = 32; ${_DESC458_}; type = "bitfield_FEC_PAUR" } FEC_OPD { address = 0xfc0b00ec; sn = "FEC_OPD"; access = "memorymapped"; width = 32; ${_DESC461_}; type = "bitfield_FEC_OPD" } FEC_IAUR { address = 0xfc0b0118; sn = "FEC_IAUR"; access = "memorymapped"; width = 32; ${_DESC464_}; type = "bitfield_FEC_IAUR" } FEC_IALR { address = 0xfc0b011c; sn = "FEC_IALR"; access = "memorymapped"; width = 32; ${_DESC466_}; type = "bitfield_FEC_IALR" } FEC_GAUR { address = 0xfc0b0120; sn = "FEC_GAUR"; access = "memorymapped"; width = 32; ${_DESC468_}; type = "bitfield_FEC_GAUR" } FEC_GALR { address = 0xfc0b0124; sn = "FEC_GALR"; access = "memorymapped"; width = 32; ${_DESC470_}; type = "bitfield_FEC_GALR" } FEC_TFWR { address = 0xfc0b0144; sn = "FEC_TFWR"; access = "memorymapped"; width = 32; ${_DESC472_}; type = "bitfield_FEC_TFWR" } FEC_FRBR { address = 0xfc0b014c; sn = "FEC_FRBR"; access = "memorymapped"; width = 32; ${_DESC474_}; type = "bitfield_FEC_FRBR" permission = "write/none" } FEC_FRSR { address = 0xfc0b0150; sn = "FEC_FRSR"; access = "memorymapped"; width = 32; ${_DESC476_}; type = "bitfield_FEC_FRSR" } FEC_ERDSR { address = 0xfc0b0180; sn = "FEC_ERDSR"; access = "memorymapped"; width = 32; ${_DESC478_}; type = "bitfield_FEC_ERDSR" } FEC_ETDSR { address = 0xfc0b0184; sn = "FEC_ETDSR"; access = "memorymapped"; width = 32; ${_DESC480_}; type = "bitfield_FEC_ETDSR" } FEC_EMRBR { address = 0xfc0b0188; sn = "FEC_EMRBR"; access = "memorymapped"; width = 32; ${_DESC482_}; type = "bitfield_FEC_EMRBR" } FEC_RMON_T_DROP { address = 0xfc0b0200; sn = "FEC_RMON_T_DROP"; access = "memorymapped"; width = 32; ${_DESC484_}; type = "bitfield_FEC_RMON_T_DROP" permission = "write/none" } FEC_RMON_T_PACKETS { address = 0xfc0b0204; sn = "FEC_RMON_T_PACKETS"; access = "memorymapped"; width = 32; ${_DESC486_}; type = "bitfield_FEC_RMON_T_PACKETS" permission = "write/none" } FEC_RMON_T_BC_PKT { address = 0xfc0b0208; sn = "FEC_RMON_T_BC_PKT"; access = "memorymapped"; width = 32; ${_DESC488_}; type = "bitfield_FEC_RMON_T_BC_PKT" permission = "write/none" } FEC_RMON_T_MC_PKT { address = 0xfc0b020c; sn = "FEC_RMON_T_MC_PKT"; access = "memorymapped"; width = 32; ${_DESC490_}; type = "bitfield_FEC_RMON_T_MC_PKT" permission = "write/none" } FEC_RMON_T_CRC_ALIGN { address = 0xfc0b0210; sn = "FEC_RMON_T_CRC_ALIGN"; access = "memorymapped"; width = 32; ${_DESC492_}; type = "bitfield_FEC_RMON_T_CRC_ALIGN" permission = "write/none" } FEC_RMON_T_UNDERSIZE { address = 0xfc0b0214; sn = "FEC_RMON_T_UNDERSIZE"; access = "memorymapped"; width = 32; ${_DESC494_}; type = "bitfield_FEC_RMON_T_UNDERSIZE" permission = "write/none" } FEC_RMON_T_OVERSIZE { address = 0xfc0b0218; sn = "FEC_RMON_T_OVERSIZE"; access = "memorymapped"; width = 32; ${_DESC496_}; type = "bitfield_FEC_RMON_T_OVERSIZE" permission = "write/none" } FEC_RMON_T_FRAG { address = 0xfc0b021c; sn = "FEC_RMON_T_FRAG"; access = "memorymapped"; width = 32; ${_DESC498_}; type = "bitfield_FEC_RMON_T_FRAG" permission = "write/none" } FEC_RMON_T_JAB { address = 0xfc0b0220; sn = "FEC_RMON_T_JAB"; access = "memorymapped"; width = 32; ${_DESC500_}; type = "bitfield_FEC_RMON_T_JAB" permission = "write/none" } FEC_RMON_T_COL { address = 0xfc0b0224; sn = "FEC_RMON_T_COL"; access = "memorymapped"; width = 32; ${_DESC502_}; type = "bitfield_FEC_RMON_T_COL" permission = "write/none" } FEC_RMON_T_P64 { address = 0xfc0b0228; sn = "FEC_RMON_T_P64"; access = "memorymapped"; width = 32; ${_DESC504_}; type = "bitfield_FEC_RMON_T_P64" permission = "write/none" } FEC_RMON_T_P65TO127 { address = 0xfc0b022c; sn = "FEC_RMON_T_P65TO127"; access = "memorymapped"; width = 32; ${_DESC506_}; type = "bitfield_FEC_RMON_T_P65TO127" permission = "write/none" } FEC_RMON_T_P128TO255 { address = 0xfc0b0230; sn = "FEC_RMON_T_P128TO255"; access = "memorymapped"; width = 32; ${_DESC508_}; type = "bitfield_FEC_RMON_T_P128TO255" permission = "write/none" } FEC_RMON_T_P256TO511 { address = 0xfc0b0234; sn = "FEC_RMON_T_P256TO511"; access = "memorymapped"; width = 32; ${_DESC510_}; type = "bitfield_FEC_RMON_T_P256TO511" permission = "write/none" } FEC_RMON_T_P512TO1023 { address = 0xfc0b0238; sn = "FEC_RMON_T_P512TO1023"; access = "memorymapped"; width = 32; ${_DESC512_}; type = "bitfield_FEC_RMON_T_P512TO1023" permission = "write/none" } FEC_RMON_T_P1024TO2047 { address = 0xfc0b023c; sn = "FEC_RMON_T_P1024TO2047"; access = "memorymapped"; width = 32; ${_DESC514_}; type = "bitfield_FEC_RMON_T_P1024TO2047" permission = "write/none" } FEC_RMON_T_P_GTE2048 { address = 0xfc0b0240; sn = "FEC_RMON_T_P_GTE2048"; access = "memorymapped"; width = 32; ${_DESC516_}; type = "bitfield_FEC_RMON_T_P_GTE2048" permission = "write/none" } FEC_RMON_T_OCTETS { address = 0xfc0b0244; sn = "FEC_RMON_T_OCTETS"; access = "memorymapped"; width = 32; ${_DESC518_}; type = "bitfield_FEC_RMON_T_OCTETS" permission = "write/none" } FEC_IEEE_T_DROP { address = 0xfc0b0248; sn = "FEC_IEEE_T_DROP"; access = "memorymapped"; width = 32; ${_DESC520_}; type = "bitfield_FEC_IEEE_T_DROP" permission = "write/none" } FEC_IEEE_T_FRAME_OK { address = 0xfc0b024c; sn = "FEC_IEEE_T_FRAME_OK"; access = "memorymapped"; width = 32; ${_DESC522_}; type = "bitfield_FEC_IEEE_T_FRAME_OK" permission = "write/none" } FEC_IEEE_T_1COL { address = 0xfc0b0250; sn = "FEC_IEEE_T_1COL"; access = "memorymapped"; width = 32; ${_DESC524_}; type = "bitfield_FEC_IEEE_T_1COL" permission = "write/none" } FEC_IEEE_T_MCOL { address = 0xfc0b0254; sn = "FEC_IEEE_T_MCOL"; access = "memorymapped"; width = 32; ${_DESC526_}; type = "bitfield_FEC_IEEE_T_MCOL" permission = "write/none" } FEC_IEEE_T_DEF { address = 0xfc0b0258; sn = "FEC_IEEE_T_DEF"; access = "memorymapped"; width = 32; ${_DESC528_}; type = "bitfield_FEC_IEEE_T_DEF" permission = "write/none" } FEC_IEEE_T_LCOL { address = 0xfc0b025c; sn = "FEC_IEEE_T_LCOL"; access = "memorymapped"; width = 32; ${_DESC530_}; type = "bitfield_FEC_IEEE_T_LCOL" permission = "write/none" } FEC_IEEE_T_EXCOL { address = 0xfc0b0260; sn = "FEC_IEEE_T_EXCOL"; access = "memorymapped"; width = 32; ${_DESC532_}; type = "bitfield_FEC_IEEE_T_EXCOL" permission = "write/none" } FEC_IEEE_T_MACERR { address = 0xfc0b0264; sn = "FEC_IEEE_T_MACERR"; access = "memorymapped"; width = 32; ${_DESC534_}; type = "bitfield_FEC_IEEE_T_MACERR" permission = "write/none" } FEC_IEEE_T_CSERR { address = 0xfc0b0268; sn = "FEC_IEEE_T_CSERR"; access = "memorymapped"; width = 32; ${_DESC536_}; type = "bitfield_FEC_IEEE_T_CSERR" permission = "write/none" } FEC_IEEE_T_SQE { address = 0xfc0b026c; sn = "FEC_IEEE_T_SQE"; access = "memorymapped"; width = 32; ${_DESC538_}; type = "bitfield_FEC_IEEE_T_SQE" permission = "write/none" } FEC_IEEE_T_FDXFC { address = 0xfc0b0270; sn = "FEC_IEEE_T_FDXFC"; access = "memorymapped"; width = 32; ${_DESC540_}; type = "bitfield_FEC_IEEE_T_FDXFC" permission = "write/none" } FEC_IEEE_T_OCTETS_OK { address = 0xfc0b0274; sn = "FEC_IEEE_T_OCTETS_OK"; access = "memorymapped"; width = 32; ${_DESC542_}; type = "bitfield_FEC_IEEE_T_OCTETS_OK" permission = "write/none" } FEC_RMON_R_DROP { address = 0xfc0b0280; sn = "FEC_RMON_R_DROP"; access = "memorymapped"; width = 32; ${_DESC544_}; type = "bitfield_FEC_RMON_R_DROP" permission = "write/none" } FEC_RMON_R_PACKETS { address = 0xfc0b0284; sn = "FEC_RMON_R_PACKETS"; access = "memorymapped"; width = 32; ${_DESC546_}; type = "bitfield_FEC_RMON_R_PACKETS" permission = "write/none" } FEC_RMON_R_BC_PKT { address = 0xfc0b0288; sn = "FEC_RMON_R_BC_PKT"; access = "memorymapped"; width = 32; ${_DESC548_}; type = "bitfield_FEC_RMON_R_BC_PKT" permission = "write/none" } FEC_RMON_R_MC_PKT { address = 0xfc0b028c; sn = "FEC_RMON_R_MC_PKT"; access = "memorymapped"; width = 32; ${_DESC550_}; type = "bitfield_FEC_RMON_R_MC_PKT" permission = "write/none" } FEC_RMON_R_CRC_ALIGN { address = 0xfc0b0290; sn = "FEC_RMON_R_CRC_ALIGN"; access = "memorymapped"; width = 32; ${_DESC552_}; type = "bitfield_FEC_RMON_R_CRC_ALIGN" permission = "write/none" } FEC_RMON_R_UNDERSIZE { address = 0xfc0b0294; sn = "FEC_RMON_R_UNDERSIZE"; access = "memorymapped"; width = 32; ${_DESC554_}; type = "bitfield_FEC_RMON_R_UNDERSIZE" permission = "write/none" } FEC_RMON_R_OVERSIZE { address = 0xfc0b0298; sn = "FEC_RMON_R_OVERSIZE"; access = "memorymapped"; width = 32; ${_DESC556_}; type = "bitfield_FEC_RMON_R_OVERSIZE" permission = "write/none" } FEC_RMON_R_FRAG { address = 0xfc0b029c; sn = "FEC_RMON_R_FRAG"; access = "memorymapped"; width = 32; ${_DESC558_}; type = "bitfield_FEC_RMON_R_FRAG" permission = "write/none" } FEC_RMON_R_JAB { address = 0xfc0b02a0; sn = "FEC_RMON_R_JAB"; access = "memorymapped"; width = 32; ${_DESC560_}; type = "bitfield_FEC_RMON_R_JAB" permission = "write/none" } FEC_RMON_R_RESVD_0 { address = 0xfc0b02a4; sn = "FEC_RMON_R_RESVD_0"; access = "memorymapped"; width = 32; ${_DESC562_}; type = "bitfield_FEC_RMON_R_RESVD_0" permission = "write/none" } FEC_RMON_R_P64 { address = 0xfc0b02a8; sn = "FEC_RMON_R_P64"; access = "memorymapped"; width = 32; ${_DESC563_}; type = "bitfield_FEC_RMON_R_P64" permission = "write/none" } FEC_RMON_R_P65TO127 { address = 0xfc0b02ac; sn = "FEC_RMON_R_P65TO127"; access = "memorymapped"; width = 32; ${_DESC565_}; type = "bitfield_FEC_RMON_R_P65TO127" permission = "write/none" } FEC_RMON_R_P128TO255 { address = 0xfc0b02b0; sn = "FEC_RMON_R_P128TO255"; access = "memorymapped"; width = 32; ${_DESC567_}; type = "bitfield_FEC_RMON_R_P128TO255" permission = "write/none" } FEC_RMON_R_P256TO511 { address = 0xfc0b02b4; sn = "FEC_RMON_R_P256TO511"; access = "memorymapped"; width = 32; ${_DESC569_}; type = "bitfield_FEC_RMON_R_P256TO511" permission = "write/none" } FEC_RMON_R_P512TO1023 { address = 0xfc0b02b8; sn = "FEC_RMON_R_P512TO1023"; access = "memorymapped"; width = 32; ${_DESC571_}; type = "bitfield_FEC_RMON_R_P512TO1023" permission = "write/none" } FEC_RMON_R_P1024TO2047 { address = 0xfc0b02bc; sn = "FEC_RMON_R_P1024TO2047"; access = "memorymapped"; width = 32; ${_DESC573_}; type = "bitfield_FEC_RMON_R_P1024TO2047" permission = "write/none" } FEC_RMON_R_P_GTE2048 { address = 0xfc0b02c0; sn = "FEC_RMON_R_P_GTE2048"; access = "memorymapped"; width = 32; ${_DESC575_}; type = "bitfield_FEC_RMON_R_P_GTE2048" permission = "write/none" } FEC_RMON_R_OCTETS { address = 0xfc0b02c4; sn = "FEC_RMON_R_OCTETS"; access = "memorymapped"; width = 32; ${_DESC577_}; type = "bitfield_FEC_RMON_R_OCTETS" permission = "write/none" } FEC_IEEE_R_DROP { address = 0xfc0b02c8; sn = "FEC_IEEE_R_DROP"; access = "memorymapped"; width = 32; ${_DESC544_}; type = "bitfield_FEC_IEEE_R_DROP" permission = "write/none" } FEC_IEEE_R_FRAME_OK { address = 0xfc0b02cc; sn = "FEC_IEEE_R_FRAME_OK"; access = "memorymapped"; width = 32; ${_DESC579_}; type = "bitfield_FEC_IEEE_R_FRAME_OK" permission = "write/none" } FEC_IEEE_R_CRC { address = 0xfc0b02d0; sn = "FEC_IEEE_R_CRC"; access = "memorymapped"; width = 32; ${_DESC581_}; type = "bitfield_FEC_IEEE_R_CRC" permission = "write/none" } FEC_IEEE_R_ALIGN { address = 0xfc0b02d4; sn = "FEC_IEEE_R_ALIGN"; access = "memorymapped"; width = 32; ${_DESC583_}; type = "bitfield_FEC_IEEE_R_ALIGN" permission = "write/none" } FEC_IEEE_R_MACERR { address = 0xfc0b02d8; sn = "FEC_IEEE_R_MACERR"; access = "memorymapped"; width = 32; ${_DESC585_}; type = "bitfield_FEC_IEEE_R_MACERR" permission = "write/none" } FEC_IEEE_R_FDXFC { address = 0xfc0b02dc; sn = "FEC_IEEE_R_FDXFC"; access = "memorymapped"; width = 32; ${_DESC587_}; type = "bitfield_FEC_IEEE_R_FDXFC" permission = "write/none" } FEC_IEEE_R_OCTETS_OK { address = 0xfc0b02e0; sn = "FEC_IEEE_R_OCTETS_OK"; access = "memorymapped"; width = 32; ${_DESC589_}; type = "bitfield_FEC_IEEE_R_OCTETS_OK" permission = "write/none" } GTMINT_GTMMCR { address = 0xffd000c0; sn = "GTMINT_GTMMCR"; access = "memorymapped"; width = 32; ${_DESC591_}; type = "bitfield_GTMINT_GTMMCR" } GTMINTCLR { address = 0xffd000c8; sn = "GTMINTCLR"; access = "memorymapped"; width = 32; ${_DESC595_}; type = "bitfield_GTMINTCLR" } GTMINT_GTMMAEICR { address = 0xffd000cc; sn = "GTMINT_GTMMAEICR"; access = "memorymapped"; width = 32; ${_DESC597_}; type = "bitfield_GTMINT_GTMMAEICR" } INTC_0_BCR { address = 0xfc040000; sn = "INTC_0_BCR"; access = "memorymapped"; width = 32; ${_DESC599_}; type = "bitfield_INTC_0_BCR" } INTC_0_CPR0 { address = 0xfc040010; sn = "INTC_0_CPR0"; access = "memorymapped"; width = 32; ${_DESC601_}; type = "bitfield_INTC_0_CPR0" } INTC_0_IACKR0 { address = 0xfc040020; sn = "INTC_0_IACKR0"; access = "memorymapped"; width = 32; ${_DESC603_}; type = "bitfield_INTC_0_IACKR0" } INTC_0_EOIR0 { address = 0xfc040030; sn = "INTC_0_EOIR0"; access = "memorymapped"; width = 32; ${_DESC606_}; type = "bitfield_INTC_0_EOIR0" permission = "read/none" } INTC_0_SSCIR0 { address = 0xfc040040; sn = "INTC_0_SSCIR0"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR1 { address = 0xfc040041; sn = "INTC_0_SSCIR1"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR2 { address = 0xfc040042; sn = "INTC_0_SSCIR2"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR3 { address = 0xfc040043; sn = "INTC_0_SSCIR3"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR4 { address = 0xfc040044; sn = "INTC_0_SSCIR4"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR5 { address = 0xfc040045; sn = "INTC_0_SSCIR5"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR6 { address = 0xfc040046; sn = "INTC_0_SSCIR6"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR7 { address = 0xfc040047; sn = "INTC_0_SSCIR7"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR8 { address = 0xfc040048; sn = "INTC_0_SSCIR8"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR9 { address = 0xfc040049; sn = "INTC_0_SSCIR9"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR10 { address = 0xfc04004a; sn = "INTC_0_SSCIR10"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR11 { address = 0xfc04004b; sn = "INTC_0_SSCIR11"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR12 { address = 0xfc04004c; sn = "INTC_0_SSCIR12"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR13 { address = 0xfc04004d; sn = "INTC_0_SSCIR13"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR14 { address = 0xfc04004e; sn = "INTC_0_SSCIR14"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR15 { address = 0xfc04004f; sn = "INTC_0_SSCIR15"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR16 { address = 0xfc040050; sn = "INTC_0_SSCIR16"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR17 { address = 0xfc040051; sn = "INTC_0_SSCIR17"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR18 { address = 0xfc040052; sn = "INTC_0_SSCIR18"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR19 { address = 0xfc040053; sn = "INTC_0_SSCIR19"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR20 { address = 0xfc040054; sn = "INTC_0_SSCIR20"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR21 { address = 0xfc040055; sn = "INTC_0_SSCIR21"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR22 { address = 0xfc040056; sn = "INTC_0_SSCIR22"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR23 { address = 0xfc040057; sn = "INTC_0_SSCIR23"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR24 { address = 0xfc040058; sn = "INTC_0_SSCIR24"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR25 { address = 0xfc040059; sn = "INTC_0_SSCIR25"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR26 { address = 0xfc04005a; sn = "INTC_0_SSCIR26"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR27 { address = 0xfc04005b; sn = "INTC_0_SSCIR27"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR28 { address = 0xfc04005c; sn = "INTC_0_SSCIR28"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR29 { address = 0xfc04005d; sn = "INTC_0_SSCIR29"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR30 { address = 0xfc04005e; sn = "INTC_0_SSCIR30"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_SSCIR31 { address = 0xfc04005f; sn = "INTC_0_SSCIR31"; access = "memorymapped"; width = 8; ${_DESC608_}; type = "bitfield_INTC_0_SSCIR0" } INTC_0_PSR0 { address = 0xfc040060; sn = "INTC_0_PSR0"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR1 { address = 0xfc040062; sn = "INTC_0_PSR1"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR2 { address = 0xfc040064; sn = "INTC_0_PSR2"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR3 { address = 0xfc040066; sn = "INTC_0_PSR3"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR4 { address = 0xfc040068; sn = "INTC_0_PSR4"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR5 { address = 0xfc04006a; sn = "INTC_0_PSR5"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR6 { address = 0xfc04006c; sn = "INTC_0_PSR6"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR7 { address = 0xfc04006e; sn = "INTC_0_PSR7"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR8 { address = 0xfc040070; sn = "INTC_0_PSR8"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR9 { address = 0xfc040072; sn = "INTC_0_PSR9"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR10 { address = 0xfc040074; sn = "INTC_0_PSR10"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR11 { address = 0xfc040076; sn = "INTC_0_PSR11"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR12 { address = 0xfc040078; sn = "INTC_0_PSR12"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR13 { address = 0xfc04007a; sn = "INTC_0_PSR13"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR14 { address = 0xfc04007c; sn = "INTC_0_PSR14"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR15 { address = 0xfc04007e; sn = "INTC_0_PSR15"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR16 { address = 0xfc040080; sn = "INTC_0_PSR16"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR17 { address = 0xfc040082; sn = "INTC_0_PSR17"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR18 { address = 0xfc040084; sn = "INTC_0_PSR18"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR19 { address = 0xfc040086; sn = "INTC_0_PSR19"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR20 { address = 0xfc040088; sn = "INTC_0_PSR20"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR21 { address = 0xfc04008a; sn = "INTC_0_PSR21"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR22 { address = 0xfc04008c; sn = "INTC_0_PSR22"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR23 { address = 0xfc04008e; sn = "INTC_0_PSR23"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR24 { address = 0xfc040090; sn = "INTC_0_PSR24"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR25 { address = 0xfc040092; sn = "INTC_0_PSR25"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR26 { address = 0xfc040094; sn = "INTC_0_PSR26"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR27 { address = 0xfc040096; sn = "INTC_0_PSR27"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR28 { address = 0xfc040098; sn = "INTC_0_PSR28"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR29 { address = 0xfc04009a; sn = "INTC_0_PSR29"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR30 { address = 0xfc04009c; sn = "INTC_0_PSR30"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR31 { address = 0xfc04009e; sn = "INTC_0_PSR31"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR32 { address = 0xfc0400a0; sn = "INTC_0_PSR32"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR33 { address = 0xfc0400a2; sn = "INTC_0_PSR33"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR34 { address = 0xfc0400a4; sn = "INTC_0_PSR34"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR35 { address = 0xfc0400a6; sn = "INTC_0_PSR35"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR36 { address = 0xfc0400a8; sn = "INTC_0_PSR36"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR37 { address = 0xfc0400aa; sn = "INTC_0_PSR37"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR38 { address = 0xfc0400ac; sn = "INTC_0_PSR38"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR39 { address = 0xfc0400ae; sn = "INTC_0_PSR39"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR40 { address = 0xfc0400b0; sn = "INTC_0_PSR40"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR41 { address = 0xfc0400b2; sn = "INTC_0_PSR41"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR42 { address = 0xfc0400b4; sn = "INTC_0_PSR42"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR43 { address = 0xfc0400b6; sn = "INTC_0_PSR43"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR44 { address = 0xfc0400b8; sn = "INTC_0_PSR44"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR45 { address = 0xfc0400ba; sn = "INTC_0_PSR45"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR46 { address = 0xfc0400bc; sn = "INTC_0_PSR46"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR47 { address = 0xfc0400be; sn = "INTC_0_PSR47"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR48 { address = 0xfc0400c0; sn = "INTC_0_PSR48"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR49 { address = 0xfc0400c2; sn = "INTC_0_PSR49"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR50 { address = 0xfc0400c4; sn = "INTC_0_PSR50"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR51 { address = 0xfc0400c6; sn = "INTC_0_PSR51"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR52 { address = 0xfc0400c8; sn = "INTC_0_PSR52"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR53 { address = 0xfc0400ca; sn = "INTC_0_PSR53"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR54 { address = 0xfc0400cc; sn = "INTC_0_PSR54"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR55 { address = 0xfc0400ce; sn = "INTC_0_PSR55"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR56 { address = 0xfc0400d0; sn = "INTC_0_PSR56"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR57 { address = 0xfc0400d2; sn = "INTC_0_PSR57"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR58 { address = 0xfc0400d4; sn = "INTC_0_PSR58"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR59 { address = 0xfc0400d6; sn = "INTC_0_PSR59"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR60 { address = 0xfc0400d8; sn = "INTC_0_PSR60"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR61 { address = 0xfc0400da; sn = "INTC_0_PSR61"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR62 { address = 0xfc0400dc; sn = "INTC_0_PSR62"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR63 { address = 0xfc0400de; sn = "INTC_0_PSR63"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR64 { address = 0xfc0400e0; sn = "INTC_0_PSR64"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR65 { address = 0xfc0400e2; sn = "INTC_0_PSR65"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR66 { address = 0xfc0400e4; sn = "INTC_0_PSR66"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR67 { address = 0xfc0400e6; sn = "INTC_0_PSR67"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR68 { address = 0xfc0400e8; sn = "INTC_0_PSR68"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR69 { address = 0xfc0400ea; sn = "INTC_0_PSR69"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR70 { address = 0xfc0400ec; sn = "INTC_0_PSR70"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR71 { address = 0xfc0400ee; sn = "INTC_0_PSR71"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR72 { address = 0xfc0400f0; sn = "INTC_0_PSR72"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR73 { address = 0xfc0400f2; sn = "INTC_0_PSR73"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR74 { address = 0xfc0400f4; sn = "INTC_0_PSR74"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR75 { address = 0xfc0400f6; sn = "INTC_0_PSR75"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR76 { address = 0xfc0400f8; sn = "INTC_0_PSR76"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR77 { address = 0xfc0400fa; sn = "INTC_0_PSR77"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR78 { address = 0xfc0400fc; sn = "INTC_0_PSR78"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR79 { address = 0xfc0400fe; sn = "INTC_0_PSR79"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR80 { address = 0xfc040100; sn = "INTC_0_PSR80"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR81 { address = 0xfc040102; sn = "INTC_0_PSR81"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR82 { address = 0xfc040104; sn = "INTC_0_PSR82"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR83 { address = 0xfc040106; sn = "INTC_0_PSR83"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR84 { address = 0xfc040108; sn = "INTC_0_PSR84"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR85 { address = 0xfc04010a; sn = "INTC_0_PSR85"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR86 { address = 0xfc04010c; sn = "INTC_0_PSR86"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR87 { address = 0xfc04010e; sn = "INTC_0_PSR87"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR88 { address = 0xfc040110; sn = "INTC_0_PSR88"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR89 { address = 0xfc040112; sn = "INTC_0_PSR89"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR90 { address = 0xfc040114; sn = "INTC_0_PSR90"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR91 { address = 0xfc040116; sn = "INTC_0_PSR91"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR92 { address = 0xfc040118; sn = "INTC_0_PSR92"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR93 { address = 0xfc04011a; sn = "INTC_0_PSR93"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR94 { address = 0xfc04011c; sn = "INTC_0_PSR94"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR95 { address = 0xfc04011e; sn = "INTC_0_PSR95"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR96 { address = 0xfc040120; sn = "INTC_0_PSR96"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR97 { address = 0xfc040122; sn = "INTC_0_PSR97"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR98 { address = 0xfc040124; sn = "INTC_0_PSR98"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR99 { address = 0xfc040126; sn = "INTC_0_PSR99"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR100 { address = 0xfc040128; sn = "INTC_0_PSR100"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR101 { address = 0xfc04012a; sn = "INTC_0_PSR101"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR102 { address = 0xfc04012c; sn = "INTC_0_PSR102"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR103 { address = 0xfc04012e; sn = "INTC_0_PSR103"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR104 { address = 0xfc040130; sn = "INTC_0_PSR104"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR105 { address = 0xfc040132; sn = "INTC_0_PSR105"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR106 { address = 0xfc040134; sn = "INTC_0_PSR106"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR107 { address = 0xfc040136; sn = "INTC_0_PSR107"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR108 { address = 0xfc040138; sn = "INTC_0_PSR108"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR109 { address = 0xfc04013a; sn = "INTC_0_PSR109"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR110 { address = 0xfc04013c; sn = "INTC_0_PSR110"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR111 { address = 0xfc04013e; sn = "INTC_0_PSR111"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR112 { address = 0xfc040140; sn = "INTC_0_PSR112"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR113 { address = 0xfc040142; sn = "INTC_0_PSR113"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR114 { address = 0xfc040144; sn = "INTC_0_PSR114"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR115 { address = 0xfc040146; sn = "INTC_0_PSR115"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR116 { address = 0xfc040148; sn = "INTC_0_PSR116"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR117 { address = 0xfc04014a; sn = "INTC_0_PSR117"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR118 { address = 0xfc04014c; sn = "INTC_0_PSR118"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR119 { address = 0xfc04014e; sn = "INTC_0_PSR119"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR120 { address = 0xfc040150; sn = "INTC_0_PSR120"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR121 { address = 0xfc040152; sn = "INTC_0_PSR121"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR122 { address = 0xfc040154; sn = "INTC_0_PSR122"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR123 { address = 0xfc040156; sn = "INTC_0_PSR123"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR124 { address = 0xfc040158; sn = "INTC_0_PSR124"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR125 { address = 0xfc04015a; sn = "INTC_0_PSR125"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR126 { address = 0xfc04015c; sn = "INTC_0_PSR126"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR127 { address = 0xfc04015e; sn = "INTC_0_PSR127"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR128 { address = 0xfc040160; sn = "INTC_0_PSR128"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR129 { address = 0xfc040162; sn = "INTC_0_PSR129"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR130 { address = 0xfc040164; sn = "INTC_0_PSR130"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR131 { address = 0xfc040166; sn = "INTC_0_PSR131"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR132 { address = 0xfc040168; sn = "INTC_0_PSR132"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR133 { address = 0xfc04016a; sn = "INTC_0_PSR133"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR134 { address = 0xfc04016c; sn = "INTC_0_PSR134"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR135 { address = 0xfc04016e; sn = "INTC_0_PSR135"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR136 { address = 0xfc040170; sn = "INTC_0_PSR136"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR137 { address = 0xfc040172; sn = "INTC_0_PSR137"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR138 { address = 0xfc040174; sn = "INTC_0_PSR138"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR139 { address = 0xfc040176; sn = "INTC_0_PSR139"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR140 { address = 0xfc040178; sn = "INTC_0_PSR140"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR141 { address = 0xfc04017a; sn = "INTC_0_PSR141"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR142 { address = 0xfc04017c; sn = "INTC_0_PSR142"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR143 { address = 0xfc04017e; sn = "INTC_0_PSR143"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR144 { address = 0xfc040180; sn = "INTC_0_PSR144"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR145 { address = 0xfc040182; sn = "INTC_0_PSR145"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR146 { address = 0xfc040184; sn = "INTC_0_PSR146"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR147 { address = 0xfc040186; sn = "INTC_0_PSR147"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR148 { address = 0xfc040188; sn = "INTC_0_PSR148"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR149 { address = 0xfc04018a; sn = "INTC_0_PSR149"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR150 { address = 0xfc04018c; sn = "INTC_0_PSR150"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR151 { address = 0xfc04018e; sn = "INTC_0_PSR151"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR152 { address = 0xfc040190; sn = "INTC_0_PSR152"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR153 { address = 0xfc040192; sn = "INTC_0_PSR153"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR154 { address = 0xfc040194; sn = "INTC_0_PSR154"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR155 { address = 0xfc040196; sn = "INTC_0_PSR155"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR156 { address = 0xfc040198; sn = "INTC_0_PSR156"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR157 { address = 0xfc04019a; sn = "INTC_0_PSR157"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR158 { address = 0xfc04019c; sn = "INTC_0_PSR158"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR159 { address = 0xfc04019e; sn = "INTC_0_PSR159"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR160 { address = 0xfc0401a0; sn = "INTC_0_PSR160"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR161 { address = 0xfc0401a2; sn = "INTC_0_PSR161"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR162 { address = 0xfc0401a4; sn = "INTC_0_PSR162"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR163 { address = 0xfc0401a6; sn = "INTC_0_PSR163"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR164 { address = 0xfc0401a8; sn = "INTC_0_PSR164"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR165 { address = 0xfc0401aa; sn = "INTC_0_PSR165"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR166 { address = 0xfc0401ac; sn = "INTC_0_PSR166"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR167 { address = 0xfc0401ae; sn = "INTC_0_PSR167"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR168 { address = 0xfc0401b0; sn = "INTC_0_PSR168"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR169 { address = 0xfc0401b2; sn = "INTC_0_PSR169"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR170 { address = 0xfc0401b4; sn = "INTC_0_PSR170"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR171 { address = 0xfc0401b6; sn = "INTC_0_PSR171"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR172 { address = 0xfc0401b8; sn = "INTC_0_PSR172"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR173 { address = 0xfc0401ba; sn = "INTC_0_PSR173"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR174 { address = 0xfc0401bc; sn = "INTC_0_PSR174"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR175 { address = 0xfc0401be; sn = "INTC_0_PSR175"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR176 { address = 0xfc0401c0; sn = "INTC_0_PSR176"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR177 { address = 0xfc0401c2; sn = "INTC_0_PSR177"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR178 { address = 0xfc0401c4; sn = "INTC_0_PSR178"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR179 { address = 0xfc0401c6; sn = "INTC_0_PSR179"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR180 { address = 0xfc0401c8; sn = "INTC_0_PSR180"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR181 { address = 0xfc0401ca; sn = "INTC_0_PSR181"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR182 { address = 0xfc0401cc; sn = "INTC_0_PSR182"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR183 { address = 0xfc0401ce; sn = "INTC_0_PSR183"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR184 { address = 0xfc0401d0; sn = "INTC_0_PSR184"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR185 { address = 0xfc0401d2; sn = "INTC_0_PSR185"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR186 { address = 0xfc0401d4; sn = "INTC_0_PSR186"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR187 { address = 0xfc0401d6; sn = "INTC_0_PSR187"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR188 { address = 0xfc0401d8; sn = "INTC_0_PSR188"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR189 { address = 0xfc0401da; sn = "INTC_0_PSR189"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR190 { address = 0xfc0401dc; sn = "INTC_0_PSR190"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR191 { address = 0xfc0401de; sn = "INTC_0_PSR191"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR192 { address = 0xfc0401e0; sn = "INTC_0_PSR192"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR193 { address = 0xfc0401e2; sn = "INTC_0_PSR193"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR194 { address = 0xfc0401e4; sn = "INTC_0_PSR194"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR195 { address = 0xfc0401e6; sn = "INTC_0_PSR195"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR196 { address = 0xfc0401e8; sn = "INTC_0_PSR196"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR197 { address = 0xfc0401ea; sn = "INTC_0_PSR197"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR198 { address = 0xfc0401ec; sn = "INTC_0_PSR198"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR199 { address = 0xfc0401ee; sn = "INTC_0_PSR199"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR200 { address = 0xfc0401f0; sn = "INTC_0_PSR200"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR201 { address = 0xfc0401f2; sn = "INTC_0_PSR201"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR202 { address = 0xfc0401f4; sn = "INTC_0_PSR202"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR203 { address = 0xfc0401f6; sn = "INTC_0_PSR203"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR204 { address = 0xfc0401f8; sn = "INTC_0_PSR204"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR205 { address = 0xfc0401fa; sn = "INTC_0_PSR205"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR206 { address = 0xfc0401fc; sn = "INTC_0_PSR206"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR207 { address = 0xfc0401fe; sn = "INTC_0_PSR207"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR208 { address = 0xfc040200; sn = "INTC_0_PSR208"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR209 { address = 0xfc040202; sn = "INTC_0_PSR209"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR210 { address = 0xfc040204; sn = "INTC_0_PSR210"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR211 { address = 0xfc040206; sn = "INTC_0_PSR211"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR212 { address = 0xfc040208; sn = "INTC_0_PSR212"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR213 { address = 0xfc04020a; sn = "INTC_0_PSR213"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR214 { address = 0xfc04020c; sn = "INTC_0_PSR214"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR215 { address = 0xfc04020e; sn = "INTC_0_PSR215"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR216 { address = 0xfc040210; sn = "INTC_0_PSR216"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR217 { address = 0xfc040212; sn = "INTC_0_PSR217"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR218 { address = 0xfc040214; sn = "INTC_0_PSR218"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR219 { address = 0xfc040216; sn = "INTC_0_PSR219"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR220 { address = 0xfc040218; sn = "INTC_0_PSR220"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR221 { address = 0xfc04021a; sn = "INTC_0_PSR221"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR222 { address = 0xfc04021c; sn = "INTC_0_PSR222"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR223 { address = 0xfc04021e; sn = "INTC_0_PSR223"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR224 { address = 0xfc040220; sn = "INTC_0_PSR224"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR225 { address = 0xfc040222; sn = "INTC_0_PSR225"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR226 { address = 0xfc040224; sn = "INTC_0_PSR226"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR227 { address = 0xfc040226; sn = "INTC_0_PSR227"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR228 { address = 0xfc040228; sn = "INTC_0_PSR228"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR229 { address = 0xfc04022a; sn = "INTC_0_PSR229"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR230 { address = 0xfc04022c; sn = "INTC_0_PSR230"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR231 { address = 0xfc04022e; sn = "INTC_0_PSR231"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR232 { address = 0xfc040230; sn = "INTC_0_PSR232"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR233 { address = 0xfc040232; sn = "INTC_0_PSR233"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR234 { address = 0xfc040234; sn = "INTC_0_PSR234"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR235 { address = 0xfc040236; sn = "INTC_0_PSR235"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR236 { address = 0xfc040238; sn = "INTC_0_PSR236"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR237 { address = 0xfc04023a; sn = "INTC_0_PSR237"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR238 { address = 0xfc04023c; sn = "INTC_0_PSR238"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR239 { address = 0xfc04023e; sn = "INTC_0_PSR239"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR240 { address = 0xfc040240; sn = "INTC_0_PSR240"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR241 { address = 0xfc040242; sn = "INTC_0_PSR241"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR242 { address = 0xfc040244; sn = "INTC_0_PSR242"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR243 { address = 0xfc040246; sn = "INTC_0_PSR243"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR244 { address = 0xfc040248; sn = "INTC_0_PSR244"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR245 { address = 0xfc04024a; sn = "INTC_0_PSR245"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR246 { address = 0xfc04024c; sn = "INTC_0_PSR246"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR247 { address = 0xfc04024e; sn = "INTC_0_PSR247"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR248 { address = 0xfc040250; sn = "INTC_0_PSR248"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR249 { address = 0xfc040252; sn = "INTC_0_PSR249"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR250 { address = 0xfc040254; sn = "INTC_0_PSR250"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR251 { address = 0xfc040256; sn = "INTC_0_PSR251"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR252 { address = 0xfc040258; sn = "INTC_0_PSR252"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR253 { address = 0xfc04025a; sn = "INTC_0_PSR253"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR254 { address = 0xfc04025c; sn = "INTC_0_PSR254"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR255 { address = 0xfc04025e; sn = "INTC_0_PSR255"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR256 { address = 0xfc040260; sn = "INTC_0_PSR256"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR257 { address = 0xfc040262; sn = "INTC_0_PSR257"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR258 { address = 0xfc040264; sn = "INTC_0_PSR258"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR259 { address = 0xfc040266; sn = "INTC_0_PSR259"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR260 { address = 0xfc040268; sn = "INTC_0_PSR260"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR261 { address = 0xfc04026a; sn = "INTC_0_PSR261"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR262 { address = 0xfc04026c; sn = "INTC_0_PSR262"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR263 { address = 0xfc04026e; sn = "INTC_0_PSR263"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR264 { address = 0xfc040270; sn = "INTC_0_PSR264"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR265 { address = 0xfc040272; sn = "INTC_0_PSR265"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR266 { address = 0xfc040274; sn = "INTC_0_PSR266"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR267 { address = 0xfc040276; sn = "INTC_0_PSR267"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR268 { address = 0xfc040278; sn = "INTC_0_PSR268"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR269 { address = 0xfc04027a; sn = "INTC_0_PSR269"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR270 { address = 0xfc04027c; sn = "INTC_0_PSR270"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR271 { address = 0xfc04027e; sn = "INTC_0_PSR271"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR272 { address = 0xfc040280; sn = "INTC_0_PSR272"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR273 { address = 0xfc040282; sn = "INTC_0_PSR273"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR274 { address = 0xfc040284; sn = "INTC_0_PSR274"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR275 { address = 0xfc040286; sn = "INTC_0_PSR275"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR276 { address = 0xfc040288; sn = "INTC_0_PSR276"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR277 { address = 0xfc04028a; sn = "INTC_0_PSR277"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR278 { address = 0xfc04028c; sn = "INTC_0_PSR278"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR279 { address = 0xfc04028e; sn = "INTC_0_PSR279"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR280 { address = 0xfc040290; sn = "INTC_0_PSR280"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR281 { address = 0xfc040292; sn = "INTC_0_PSR281"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR282 { address = 0xfc040294; sn = "INTC_0_PSR282"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR283 { address = 0xfc040296; sn = "INTC_0_PSR283"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR284 { address = 0xfc040298; sn = "INTC_0_PSR284"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR285 { address = 0xfc04029a; sn = "INTC_0_PSR285"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR286 { address = 0xfc04029c; sn = "INTC_0_PSR286"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR287 { address = 0xfc04029e; sn = "INTC_0_PSR287"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR288 { address = 0xfc0402a0; sn = "INTC_0_PSR288"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR289 { address = 0xfc0402a2; sn = "INTC_0_PSR289"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR290 { address = 0xfc0402a4; sn = "INTC_0_PSR290"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR291 { address = 0xfc0402a6; sn = "INTC_0_PSR291"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR292 { address = 0xfc0402a8; sn = "INTC_0_PSR292"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR293 { address = 0xfc0402aa; sn = "INTC_0_PSR293"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR294 { address = 0xfc0402ac; sn = "INTC_0_PSR294"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR295 { address = 0xfc0402ae; sn = "INTC_0_PSR295"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR296 { address = 0xfc0402b0; sn = "INTC_0_PSR296"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR297 { address = 0xfc0402b2; sn = "INTC_0_PSR297"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR298 { address = 0xfc0402b4; sn = "INTC_0_PSR298"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR299 { address = 0xfc0402b6; sn = "INTC_0_PSR299"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR300 { address = 0xfc0402b8; sn = "INTC_0_PSR300"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR301 { address = 0xfc0402ba; sn = "INTC_0_PSR301"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR302 { address = 0xfc0402bc; sn = "INTC_0_PSR302"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR303 { address = 0xfc0402be; sn = "INTC_0_PSR303"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR304 { address = 0xfc0402c0; sn = "INTC_0_PSR304"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR305 { address = 0xfc0402c2; sn = "INTC_0_PSR305"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR306 { address = 0xfc0402c4; sn = "INTC_0_PSR306"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR307 { address = 0xfc0402c6; sn = "INTC_0_PSR307"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR308 { address = 0xfc0402c8; sn = "INTC_0_PSR308"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR309 { address = 0xfc0402ca; sn = "INTC_0_PSR309"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR310 { address = 0xfc0402cc; sn = "INTC_0_PSR310"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR311 { address = 0xfc0402ce; sn = "INTC_0_PSR311"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR312 { address = 0xfc0402d0; sn = "INTC_0_PSR312"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR313 { address = 0xfc0402d2; sn = "INTC_0_PSR313"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR314 { address = 0xfc0402d4; sn = "INTC_0_PSR314"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR315 { address = 0xfc0402d6; sn = "INTC_0_PSR315"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR316 { address = 0xfc0402d8; sn = "INTC_0_PSR316"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR317 { address = 0xfc0402da; sn = "INTC_0_PSR317"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR318 { address = 0xfc0402dc; sn = "INTC_0_PSR318"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR319 { address = 0xfc0402de; sn = "INTC_0_PSR319"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR320 { address = 0xfc0402e0; sn = "INTC_0_PSR320"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR321 { address = 0xfc0402e2; sn = "INTC_0_PSR321"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR322 { address = 0xfc0402e4; sn = "INTC_0_PSR322"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR323 { address = 0xfc0402e6; sn = "INTC_0_PSR323"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR324 { address = 0xfc0402e8; sn = "INTC_0_PSR324"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR325 { address = 0xfc0402ea; sn = "INTC_0_PSR325"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR326 { address = 0xfc0402ec; sn = "INTC_0_PSR326"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR327 { address = 0xfc0402ee; sn = "INTC_0_PSR327"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR328 { address = 0xfc0402f0; sn = "INTC_0_PSR328"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR329 { address = 0xfc0402f2; sn = "INTC_0_PSR329"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR330 { address = 0xfc0402f4; sn = "INTC_0_PSR330"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR331 { address = 0xfc0402f6; sn = "INTC_0_PSR331"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR332 { address = 0xfc0402f8; sn = "INTC_0_PSR332"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR333 { address = 0xfc0402fa; sn = "INTC_0_PSR333"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR334 { address = 0xfc0402fc; sn = "INTC_0_PSR334"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR335 { address = 0xfc0402fe; sn = "INTC_0_PSR335"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR336 { address = 0xfc040300; sn = "INTC_0_PSR336"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR337 { address = 0xfc040302; sn = "INTC_0_PSR337"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR338 { address = 0xfc040304; sn = "INTC_0_PSR338"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR339 { address = 0xfc040306; sn = "INTC_0_PSR339"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR340 { address = 0xfc040308; sn = "INTC_0_PSR340"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR341 { address = 0xfc04030a; sn = "INTC_0_PSR341"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR342 { address = 0xfc04030c; sn = "INTC_0_PSR342"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR343 { address = 0xfc04030e; sn = "INTC_0_PSR343"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR344 { address = 0xfc040310; sn = "INTC_0_PSR344"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR345 { address = 0xfc040312; sn = "INTC_0_PSR345"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR346 { address = 0xfc040314; sn = "INTC_0_PSR346"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR347 { address = 0xfc040316; sn = "INTC_0_PSR347"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR348 { address = 0xfc040318; sn = "INTC_0_PSR348"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR349 { address = 0xfc04031a; sn = "INTC_0_PSR349"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR350 { address = 0xfc04031c; sn = "INTC_0_PSR350"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR351 { address = 0xfc04031e; sn = "INTC_0_PSR351"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR352 { address = 0xfc040320; sn = "INTC_0_PSR352"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR353 { address = 0xfc040322; sn = "INTC_0_PSR353"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR354 { address = 0xfc040324; sn = "INTC_0_PSR354"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR355 { address = 0xfc040326; sn = "INTC_0_PSR355"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR356 { address = 0xfc040328; sn = "INTC_0_PSR356"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR357 { address = 0xfc04032a; sn = "INTC_0_PSR357"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR358 { address = 0xfc04032c; sn = "INTC_0_PSR358"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR359 { address = 0xfc04032e; sn = "INTC_0_PSR359"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR360 { address = 0xfc040330; sn = "INTC_0_PSR360"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR361 { address = 0xfc040332; sn = "INTC_0_PSR361"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR362 { address = 0xfc040334; sn = "INTC_0_PSR362"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR363 { address = 0xfc040336; sn = "INTC_0_PSR363"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR364 { address = 0xfc040338; sn = "INTC_0_PSR364"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR365 { address = 0xfc04033a; sn = "INTC_0_PSR365"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR366 { address = 0xfc04033c; sn = "INTC_0_PSR366"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR367 { address = 0xfc04033e; sn = "INTC_0_PSR367"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR368 { address = 0xfc040340; sn = "INTC_0_PSR368"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR369 { address = 0xfc040342; sn = "INTC_0_PSR369"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR370 { address = 0xfc040344; sn = "INTC_0_PSR370"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR371 { address = 0xfc040346; sn = "INTC_0_PSR371"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR372 { address = 0xfc040348; sn = "INTC_0_PSR372"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR373 { address = 0xfc04034a; sn = "INTC_0_PSR373"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR374 { address = 0xfc04034c; sn = "INTC_0_PSR374"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR375 { address = 0xfc04034e; sn = "INTC_0_PSR375"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR376 { address = 0xfc040350; sn = "INTC_0_PSR376"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR377 { address = 0xfc040352; sn = "INTC_0_PSR377"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR378 { address = 0xfc040354; sn = "INTC_0_PSR378"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR379 { address = 0xfc040356; sn = "INTC_0_PSR379"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR380 { address = 0xfc040358; sn = "INTC_0_PSR380"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR381 { address = 0xfc04035a; sn = "INTC_0_PSR381"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR382 { address = 0xfc04035c; sn = "INTC_0_PSR382"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR383 { address = 0xfc04035e; sn = "INTC_0_PSR383"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR384 { address = 0xfc040360; sn = "INTC_0_PSR384"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR385 { address = 0xfc040362; sn = "INTC_0_PSR385"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR386 { address = 0xfc040364; sn = "INTC_0_PSR386"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR387 { address = 0xfc040366; sn = "INTC_0_PSR387"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR388 { address = 0xfc040368; sn = "INTC_0_PSR388"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR389 { address = 0xfc04036a; sn = "INTC_0_PSR389"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR390 { address = 0xfc04036c; sn = "INTC_0_PSR390"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR391 { address = 0xfc04036e; sn = "INTC_0_PSR391"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR392 { address = 0xfc040370; sn = "INTC_0_PSR392"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR393 { address = 0xfc040372; sn = "INTC_0_PSR393"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR394 { address = 0xfc040374; sn = "INTC_0_PSR394"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR395 { address = 0xfc040376; sn = "INTC_0_PSR395"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR396 { address = 0xfc040378; sn = "INTC_0_PSR396"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR397 { address = 0xfc04037a; sn = "INTC_0_PSR397"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR398 { address = 0xfc04037c; sn = "INTC_0_PSR398"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR399 { address = 0xfc04037e; sn = "INTC_0_PSR399"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR400 { address = 0xfc040380; sn = "INTC_0_PSR400"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR401 { address = 0xfc040382; sn = "INTC_0_PSR401"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR402 { address = 0xfc040384; sn = "INTC_0_PSR402"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR403 { address = 0xfc040386; sn = "INTC_0_PSR403"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR404 { address = 0xfc040388; sn = "INTC_0_PSR404"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR405 { address = 0xfc04038a; sn = "INTC_0_PSR405"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR406 { address = 0xfc04038c; sn = "INTC_0_PSR406"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR407 { address = 0xfc04038e; sn = "INTC_0_PSR407"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR408 { address = 0xfc040390; sn = "INTC_0_PSR408"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR409 { address = 0xfc040392; sn = "INTC_0_PSR409"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR410 { address = 0xfc040394; sn = "INTC_0_PSR410"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR411 { address = 0xfc040396; sn = "INTC_0_PSR411"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR412 { address = 0xfc040398; sn = "INTC_0_PSR412"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR413 { address = 0xfc04039a; sn = "INTC_0_PSR413"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR414 { address = 0xfc04039c; sn = "INTC_0_PSR414"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR415 { address = 0xfc04039e; sn = "INTC_0_PSR415"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR416 { address = 0xfc0403a0; sn = "INTC_0_PSR416"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR417 { address = 0xfc0403a2; sn = "INTC_0_PSR417"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR418 { address = 0xfc0403a4; sn = "INTC_0_PSR418"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR419 { address = 0xfc0403a6; sn = "INTC_0_PSR419"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR420 { address = 0xfc0403a8; sn = "INTC_0_PSR420"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR421 { address = 0xfc0403aa; sn = "INTC_0_PSR421"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR422 { address = 0xfc0403ac; sn = "INTC_0_PSR422"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR423 { address = 0xfc0403ae; sn = "INTC_0_PSR423"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR424 { address = 0xfc0403b0; sn = "INTC_0_PSR424"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR425 { address = 0xfc0403b2; sn = "INTC_0_PSR425"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR426 { address = 0xfc0403b4; sn = "INTC_0_PSR426"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR427 { address = 0xfc0403b6; sn = "INTC_0_PSR427"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR428 { address = 0xfc0403b8; sn = "INTC_0_PSR428"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR429 { address = 0xfc0403ba; sn = "INTC_0_PSR429"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR430 { address = 0xfc0403bc; sn = "INTC_0_PSR430"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR431 { address = 0xfc0403be; sn = "INTC_0_PSR431"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR432 { address = 0xfc0403c0; sn = "INTC_0_PSR432"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR433 { address = 0xfc0403c2; sn = "INTC_0_PSR433"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR434 { address = 0xfc0403c4; sn = "INTC_0_PSR434"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR435 { address = 0xfc0403c6; sn = "INTC_0_PSR435"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR436 { address = 0xfc0403c8; sn = "INTC_0_PSR436"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR437 { address = 0xfc0403ca; sn = "INTC_0_PSR437"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR438 { address = 0xfc0403cc; sn = "INTC_0_PSR438"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR439 { address = 0xfc0403ce; sn = "INTC_0_PSR439"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR440 { address = 0xfc0403d0; sn = "INTC_0_PSR440"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR441 { address = 0xfc0403d2; sn = "INTC_0_PSR441"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR442 { address = 0xfc0403d4; sn = "INTC_0_PSR442"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR443 { address = 0xfc0403d6; sn = "INTC_0_PSR443"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR444 { address = 0xfc0403d8; sn = "INTC_0_PSR444"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR445 { address = 0xfc0403da; sn = "INTC_0_PSR445"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR446 { address = 0xfc0403dc; sn = "INTC_0_PSR446"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR447 { address = 0xfc0403de; sn = "INTC_0_PSR447"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR448 { address = 0xfc0403e0; sn = "INTC_0_PSR448"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR449 { address = 0xfc0403e2; sn = "INTC_0_PSR449"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR450 { address = 0xfc0403e4; sn = "INTC_0_PSR450"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR451 { address = 0xfc0403e6; sn = "INTC_0_PSR451"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR452 { address = 0xfc0403e8; sn = "INTC_0_PSR452"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR453 { address = 0xfc0403ea; sn = "INTC_0_PSR453"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR454 { address = 0xfc0403ec; sn = "INTC_0_PSR454"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR455 { address = 0xfc0403ee; sn = "INTC_0_PSR455"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR456 { address = 0xfc0403f0; sn = "INTC_0_PSR456"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR457 { address = 0xfc0403f2; sn = "INTC_0_PSR457"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR458 { address = 0xfc0403f4; sn = "INTC_0_PSR458"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR459 { address = 0xfc0403f6; sn = "INTC_0_PSR459"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR460 { address = 0xfc0403f8; sn = "INTC_0_PSR460"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR461 { address = 0xfc0403fa; sn = "INTC_0_PSR461"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR462 { address = 0xfc0403fc; sn = "INTC_0_PSR462"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR463 { address = 0xfc0403fe; sn = "INTC_0_PSR463"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR464 { address = 0xfc040400; sn = "INTC_0_PSR464"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR465 { address = 0xfc040402; sn = "INTC_0_PSR465"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR466 { address = 0xfc040404; sn = "INTC_0_PSR466"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR467 { address = 0xfc040406; sn = "INTC_0_PSR467"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR468 { address = 0xfc040408; sn = "INTC_0_PSR468"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR469 { address = 0xfc04040a; sn = "INTC_0_PSR469"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR470 { address = 0xfc04040c; sn = "INTC_0_PSR470"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR471 { address = 0xfc04040e; sn = "INTC_0_PSR471"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR472 { address = 0xfc040410; sn = "INTC_0_PSR472"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR473 { address = 0xfc040412; sn = "INTC_0_PSR473"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR474 { address = 0xfc040414; sn = "INTC_0_PSR474"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR475 { address = 0xfc040416; sn = "INTC_0_PSR475"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR476 { address = 0xfc040418; sn = "INTC_0_PSR476"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR477 { address = 0xfc04041a; sn = "INTC_0_PSR477"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR478 { address = 0xfc04041c; sn = "INTC_0_PSR478"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR479 { address = 0xfc04041e; sn = "INTC_0_PSR479"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR480 { address = 0xfc040420; sn = "INTC_0_PSR480"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR481 { address = 0xfc040422; sn = "INTC_0_PSR481"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR482 { address = 0xfc040424; sn = "INTC_0_PSR482"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR483 { address = 0xfc040426; sn = "INTC_0_PSR483"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR484 { address = 0xfc040428; sn = "INTC_0_PSR484"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR485 { address = 0xfc04042a; sn = "INTC_0_PSR485"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR486 { address = 0xfc04042c; sn = "INTC_0_PSR486"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR487 { address = 0xfc04042e; sn = "INTC_0_PSR487"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR488 { address = 0xfc040430; sn = "INTC_0_PSR488"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR489 { address = 0xfc040432; sn = "INTC_0_PSR489"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR490 { address = 0xfc040434; sn = "INTC_0_PSR490"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR491 { address = 0xfc040436; sn = "INTC_0_PSR491"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR492 { address = 0xfc040438; sn = "INTC_0_PSR492"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR493 { address = 0xfc04043a; sn = "INTC_0_PSR493"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR494 { address = 0xfc04043c; sn = "INTC_0_PSR494"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR495 { address = 0xfc04043e; sn = "INTC_0_PSR495"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR496 { address = 0xfc040440; sn = "INTC_0_PSR496"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR497 { address = 0xfc040442; sn = "INTC_0_PSR497"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR498 { address = 0xfc040444; sn = "INTC_0_PSR498"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR499 { address = 0xfc040446; sn = "INTC_0_PSR499"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR500 { address = 0xfc040448; sn = "INTC_0_PSR500"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR501 { address = 0xfc04044a; sn = "INTC_0_PSR501"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR502 { address = 0xfc04044c; sn = "INTC_0_PSR502"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR503 { address = 0xfc04044e; sn = "INTC_0_PSR503"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR504 { address = 0xfc040450; sn = "INTC_0_PSR504"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR505 { address = 0xfc040452; sn = "INTC_0_PSR505"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR506 { address = 0xfc040454; sn = "INTC_0_PSR506"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR507 { address = 0xfc040456; sn = "INTC_0_PSR507"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR508 { address = 0xfc040458; sn = "INTC_0_PSR508"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR509 { address = 0xfc04045a; sn = "INTC_0_PSR509"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR510 { address = 0xfc04045c; sn = "INTC_0_PSR510"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR511 { address = 0xfc04045e; sn = "INTC_0_PSR511"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR512 { address = 0xfc040460; sn = "INTC_0_PSR512"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR513 { address = 0xfc040462; sn = "INTC_0_PSR513"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR514 { address = 0xfc040464; sn = "INTC_0_PSR514"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR515 { address = 0xfc040466; sn = "INTC_0_PSR515"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR516 { address = 0xfc040468; sn = "INTC_0_PSR516"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR517 { address = 0xfc04046a; sn = "INTC_0_PSR517"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR518 { address = 0xfc04046c; sn = "INTC_0_PSR518"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR519 { address = 0xfc04046e; sn = "INTC_0_PSR519"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR520 { address = 0xfc040470; sn = "INTC_0_PSR520"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR521 { address = 0xfc040472; sn = "INTC_0_PSR521"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR522 { address = 0xfc040474; sn = "INTC_0_PSR522"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR523 { address = 0xfc040476; sn = "INTC_0_PSR523"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR524 { address = 0xfc040478; sn = "INTC_0_PSR524"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR525 { address = 0xfc04047a; sn = "INTC_0_PSR525"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR526 { address = 0xfc04047c; sn = "INTC_0_PSR526"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR527 { address = 0xfc04047e; sn = "INTC_0_PSR527"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR528 { address = 0xfc040480; sn = "INTC_0_PSR528"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR529 { address = 0xfc040482; sn = "INTC_0_PSR529"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR530 { address = 0xfc040484; sn = "INTC_0_PSR530"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR531 { address = 0xfc040486; sn = "INTC_0_PSR531"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR532 { address = 0xfc040488; sn = "INTC_0_PSR532"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR533 { address = 0xfc04048a; sn = "INTC_0_PSR533"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR534 { address = 0xfc04048c; sn = "INTC_0_PSR534"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR535 { address = 0xfc04048e; sn = "INTC_0_PSR535"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR536 { address = 0xfc040490; sn = "INTC_0_PSR536"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR537 { address = 0xfc040492; sn = "INTC_0_PSR537"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR538 { address = 0xfc040494; sn = "INTC_0_PSR538"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR539 { address = 0xfc040496; sn = "INTC_0_PSR539"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR540 { address = 0xfc040498; sn = "INTC_0_PSR540"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR541 { address = 0xfc04049a; sn = "INTC_0_PSR541"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR542 { address = 0xfc04049c; sn = "INTC_0_PSR542"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR543 { address = 0xfc04049e; sn = "INTC_0_PSR543"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR544 { address = 0xfc0404a0; sn = "INTC_0_PSR544"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR545 { address = 0xfc0404a2; sn = "INTC_0_PSR545"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR546 { address = 0xfc0404a4; sn = "INTC_0_PSR546"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR547 { address = 0xfc0404a6; sn = "INTC_0_PSR547"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR548 { address = 0xfc0404a8; sn = "INTC_0_PSR548"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR549 { address = 0xfc0404aa; sn = "INTC_0_PSR549"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR550 { address = 0xfc0404ac; sn = "INTC_0_PSR550"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR551 { address = 0xfc0404ae; sn = "INTC_0_PSR551"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR552 { address = 0xfc0404b0; sn = "INTC_0_PSR552"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR553 { address = 0xfc0404b2; sn = "INTC_0_PSR553"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR554 { address = 0xfc0404b4; sn = "INTC_0_PSR554"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR555 { address = 0xfc0404b6; sn = "INTC_0_PSR555"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR556 { address = 0xfc0404b8; sn = "INTC_0_PSR556"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR557 { address = 0xfc0404ba; sn = "INTC_0_PSR557"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR558 { address = 0xfc0404bc; sn = "INTC_0_PSR558"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR559 { address = 0xfc0404be; sn = "INTC_0_PSR559"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR560 { address = 0xfc0404c0; sn = "INTC_0_PSR560"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR561 { address = 0xfc0404c2; sn = "INTC_0_PSR561"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR562 { address = 0xfc0404c4; sn = "INTC_0_PSR562"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR563 { address = 0xfc0404c6; sn = "INTC_0_PSR563"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR564 { address = 0xfc0404c8; sn = "INTC_0_PSR564"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR565 { address = 0xfc0404ca; sn = "INTC_0_PSR565"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR566 { address = 0xfc0404cc; sn = "INTC_0_PSR566"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR567 { address = 0xfc0404ce; sn = "INTC_0_PSR567"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR568 { address = 0xfc0404d0; sn = "INTC_0_PSR568"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR569 { address = 0xfc0404d2; sn = "INTC_0_PSR569"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR570 { address = 0xfc0404d4; sn = "INTC_0_PSR570"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR571 { address = 0xfc0404d6; sn = "INTC_0_PSR571"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR572 { address = 0xfc0404d8; sn = "INTC_0_PSR572"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR573 { address = 0xfc0404da; sn = "INTC_0_PSR573"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR574 { address = 0xfc0404dc; sn = "INTC_0_PSR574"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR575 { address = 0xfc0404de; sn = "INTC_0_PSR575"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR576 { address = 0xfc0404e0; sn = "INTC_0_PSR576"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR577 { address = 0xfc0404e2; sn = "INTC_0_PSR577"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR578 { address = 0xfc0404e4; sn = "INTC_0_PSR578"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR579 { address = 0xfc0404e6; sn = "INTC_0_PSR579"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR580 { address = 0xfc0404e8; sn = "INTC_0_PSR580"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR581 { address = 0xfc0404ea; sn = "INTC_0_PSR581"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR582 { address = 0xfc0404ec; sn = "INTC_0_PSR582"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR583 { address = 0xfc0404ee; sn = "INTC_0_PSR583"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR584 { address = 0xfc0404f0; sn = "INTC_0_PSR584"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR585 { address = 0xfc0404f2; sn = "INTC_0_PSR585"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR586 { address = 0xfc0404f4; sn = "INTC_0_PSR586"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR587 { address = 0xfc0404f6; sn = "INTC_0_PSR587"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR588 { address = 0xfc0404f8; sn = "INTC_0_PSR588"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR589 { address = 0xfc0404fa; sn = "INTC_0_PSR589"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR590 { address = 0xfc0404fc; sn = "INTC_0_PSR590"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR591 { address = 0xfc0404fe; sn = "INTC_0_PSR591"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR592 { address = 0xfc040500; sn = "INTC_0_PSR592"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR593 { address = 0xfc040502; sn = "INTC_0_PSR593"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR594 { address = 0xfc040504; sn = "INTC_0_PSR594"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR595 { address = 0xfc040506; sn = "INTC_0_PSR595"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR596 { address = 0xfc040508; sn = "INTC_0_PSR596"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR597 { address = 0xfc04050a; sn = "INTC_0_PSR597"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR598 { address = 0xfc04050c; sn = "INTC_0_PSR598"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR599 { address = 0xfc04050e; sn = "INTC_0_PSR599"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR600 { address = 0xfc040510; sn = "INTC_0_PSR600"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR601 { address = 0xfc040512; sn = "INTC_0_PSR601"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR602 { address = 0xfc040514; sn = "INTC_0_PSR602"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR603 { address = 0xfc040516; sn = "INTC_0_PSR603"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR604 { address = 0xfc040518; sn = "INTC_0_PSR604"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR605 { address = 0xfc04051a; sn = "INTC_0_PSR605"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR606 { address = 0xfc04051c; sn = "INTC_0_PSR606"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR607 { address = 0xfc04051e; sn = "INTC_0_PSR607"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR608 { address = 0xfc040520; sn = "INTC_0_PSR608"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR609 { address = 0xfc040522; sn = "INTC_0_PSR609"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR610 { address = 0xfc040524; sn = "INTC_0_PSR610"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR611 { address = 0xfc040526; sn = "INTC_0_PSR611"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR612 { address = 0xfc040528; sn = "INTC_0_PSR612"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR613 { address = 0xfc04052a; sn = "INTC_0_PSR613"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR614 { address = 0xfc04052c; sn = "INTC_0_PSR614"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR615 { address = 0xfc04052e; sn = "INTC_0_PSR615"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR616 { address = 0xfc040530; sn = "INTC_0_PSR616"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR617 { address = 0xfc040532; sn = "INTC_0_PSR617"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR618 { address = 0xfc040534; sn = "INTC_0_PSR618"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR619 { address = 0xfc040536; sn = "INTC_0_PSR619"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR620 { address = 0xfc040538; sn = "INTC_0_PSR620"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR621 { address = 0xfc04053a; sn = "INTC_0_PSR621"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR622 { address = 0xfc04053c; sn = "INTC_0_PSR622"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR623 { address = 0xfc04053e; sn = "INTC_0_PSR623"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR624 { address = 0xfc040540; sn = "INTC_0_PSR624"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR625 { address = 0xfc040542; sn = "INTC_0_PSR625"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR626 { address = 0xfc040544; sn = "INTC_0_PSR626"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR627 { address = 0xfc040546; sn = "INTC_0_PSR627"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR628 { address = 0xfc040548; sn = "INTC_0_PSR628"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR629 { address = 0xfc04054a; sn = "INTC_0_PSR629"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR630 { address = 0xfc04054c; sn = "INTC_0_PSR630"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR631 { address = 0xfc04054e; sn = "INTC_0_PSR631"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR632 { address = 0xfc040550; sn = "INTC_0_PSR632"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR633 { address = 0xfc040552; sn = "INTC_0_PSR633"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR634 { address = 0xfc040554; sn = "INTC_0_PSR634"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR635 { address = 0xfc040556; sn = "INTC_0_PSR635"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR636 { address = 0xfc040558; sn = "INTC_0_PSR636"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR637 { address = 0xfc04055a; sn = "INTC_0_PSR637"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR638 { address = 0xfc04055c; sn = "INTC_0_PSR638"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR639 { address = 0xfc04055e; sn = "INTC_0_PSR639"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR640 { address = 0xfc040560; sn = "INTC_0_PSR640"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR641 { address = 0xfc040562; sn = "INTC_0_PSR641"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR642 { address = 0xfc040564; sn = "INTC_0_PSR642"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR643 { address = 0xfc040566; sn = "INTC_0_PSR643"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR644 { address = 0xfc040568; sn = "INTC_0_PSR644"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR645 { address = 0xfc04056a; sn = "INTC_0_PSR645"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR646 { address = 0xfc04056c; sn = "INTC_0_PSR646"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR647 { address = 0xfc04056e; sn = "INTC_0_PSR647"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR648 { address = 0xfc040570; sn = "INTC_0_PSR648"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR649 { address = 0xfc040572; sn = "INTC_0_PSR649"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR650 { address = 0xfc040574; sn = "INTC_0_PSR650"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR651 { address = 0xfc040576; sn = "INTC_0_PSR651"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR652 { address = 0xfc040578; sn = "INTC_0_PSR652"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR653 { address = 0xfc04057a; sn = "INTC_0_PSR653"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR654 { address = 0xfc04057c; sn = "INTC_0_PSR654"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR655 { address = 0xfc04057e; sn = "INTC_0_PSR655"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR656 { address = 0xfc040580; sn = "INTC_0_PSR656"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR657 { address = 0xfc040582; sn = "INTC_0_PSR657"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR658 { address = 0xfc040584; sn = "INTC_0_PSR658"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR659 { address = 0xfc040586; sn = "INTC_0_PSR659"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR660 { address = 0xfc040588; sn = "INTC_0_PSR660"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR661 { address = 0xfc04058a; sn = "INTC_0_PSR661"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR662 { address = 0xfc04058c; sn = "INTC_0_PSR662"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR663 { address = 0xfc04058e; sn = "INTC_0_PSR663"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR664 { address = 0xfc040590; sn = "INTC_0_PSR664"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR665 { address = 0xfc040592; sn = "INTC_0_PSR665"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR666 { address = 0xfc040594; sn = "INTC_0_PSR666"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR667 { address = 0xfc040596; sn = "INTC_0_PSR667"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR668 { address = 0xfc040598; sn = "INTC_0_PSR668"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR669 { address = 0xfc04059a; sn = "INTC_0_PSR669"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR670 { address = 0xfc04059c; sn = "INTC_0_PSR670"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR671 { address = 0xfc04059e; sn = "INTC_0_PSR671"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR672 { address = 0xfc0405a0; sn = "INTC_0_PSR672"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR673 { address = 0xfc0405a2; sn = "INTC_0_PSR673"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR674 { address = 0xfc0405a4; sn = "INTC_0_PSR674"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR675 { address = 0xfc0405a6; sn = "INTC_0_PSR675"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR676 { address = 0xfc0405a8; sn = "INTC_0_PSR676"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR677 { address = 0xfc0405aa; sn = "INTC_0_PSR677"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR678 { address = 0xfc0405ac; sn = "INTC_0_PSR678"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR679 { address = 0xfc0405ae; sn = "INTC_0_PSR679"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR680 { address = 0xfc0405b0; sn = "INTC_0_PSR680"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR681 { address = 0xfc0405b2; sn = "INTC_0_PSR681"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR682 { address = 0xfc0405b4; sn = "INTC_0_PSR682"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR683 { address = 0xfc0405b6; sn = "INTC_0_PSR683"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR684 { address = 0xfc0405b8; sn = "INTC_0_PSR684"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR685 { address = 0xfc0405ba; sn = "INTC_0_PSR685"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR686 { address = 0xfc0405bc; sn = "INTC_0_PSR686"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR687 { address = 0xfc0405be; sn = "INTC_0_PSR687"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR688 { address = 0xfc0405c0; sn = "INTC_0_PSR688"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR689 { address = 0xfc0405c2; sn = "INTC_0_PSR689"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR690 { address = 0xfc0405c4; sn = "INTC_0_PSR690"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR691 { address = 0xfc0405c6; sn = "INTC_0_PSR691"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR692 { address = 0xfc0405c8; sn = "INTC_0_PSR692"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR693 { address = 0xfc0405ca; sn = "INTC_0_PSR693"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR694 { address = 0xfc0405cc; sn = "INTC_0_PSR694"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR695 { address = 0xfc0405ce; sn = "INTC_0_PSR695"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR696 { address = 0xfc0405d0; sn = "INTC_0_PSR696"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR697 { address = 0xfc0405d2; sn = "INTC_0_PSR697"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR698 { address = 0xfc0405d4; sn = "INTC_0_PSR698"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR699 { address = 0xfc0405d6; sn = "INTC_0_PSR699"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR700 { address = 0xfc0405d8; sn = "INTC_0_PSR700"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR701 { address = 0xfc0405da; sn = "INTC_0_PSR701"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR702 { address = 0xfc0405dc; sn = "INTC_0_PSR702"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR703 { address = 0xfc0405de; sn = "INTC_0_PSR703"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR704 { address = 0xfc0405e0; sn = "INTC_0_PSR704"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR705 { address = 0xfc0405e2; sn = "INTC_0_PSR705"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR706 { address = 0xfc0405e4; sn = "INTC_0_PSR706"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR707 { address = 0xfc0405e6; sn = "INTC_0_PSR707"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR708 { address = 0xfc0405e8; sn = "INTC_0_PSR708"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR709 { address = 0xfc0405ea; sn = "INTC_0_PSR709"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR710 { address = 0xfc0405ec; sn = "INTC_0_PSR710"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR711 { address = 0xfc0405ee; sn = "INTC_0_PSR711"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR712 { address = 0xfc0405f0; sn = "INTC_0_PSR712"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR713 { address = 0xfc0405f2; sn = "INTC_0_PSR713"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR714 { address = 0xfc0405f4; sn = "INTC_0_PSR714"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR715 { address = 0xfc0405f6; sn = "INTC_0_PSR715"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR716 { address = 0xfc0405f8; sn = "INTC_0_PSR716"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR717 { address = 0xfc0405fa; sn = "INTC_0_PSR717"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR718 { address = 0xfc0405fc; sn = "INTC_0_PSR718"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR719 { address = 0xfc0405fe; sn = "INTC_0_PSR719"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR720 { address = 0xfc040600; sn = "INTC_0_PSR720"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR721 { address = 0xfc040602; sn = "INTC_0_PSR721"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR722 { address = 0xfc040604; sn = "INTC_0_PSR722"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR723 { address = 0xfc040606; sn = "INTC_0_PSR723"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR724 { address = 0xfc040608; sn = "INTC_0_PSR724"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR725 { address = 0xfc04060a; sn = "INTC_0_PSR725"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR726 { address = 0xfc04060c; sn = "INTC_0_PSR726"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR727 { address = 0xfc04060e; sn = "INTC_0_PSR727"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR728 { address = 0xfc040610; sn = "INTC_0_PSR728"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR729 { address = 0xfc040612; sn = "INTC_0_PSR729"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR730 { address = 0xfc040614; sn = "INTC_0_PSR730"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR731 { address = 0xfc040616; sn = "INTC_0_PSR731"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR732 { address = 0xfc040618; sn = "INTC_0_PSR732"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR733 { address = 0xfc04061a; sn = "INTC_0_PSR733"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR734 { address = 0xfc04061c; sn = "INTC_0_PSR734"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR735 { address = 0xfc04061e; sn = "INTC_0_PSR735"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR736 { address = 0xfc040620; sn = "INTC_0_PSR736"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR737 { address = 0xfc040622; sn = "INTC_0_PSR737"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR738 { address = 0xfc040624; sn = "INTC_0_PSR738"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR739 { address = 0xfc040626; sn = "INTC_0_PSR739"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR740 { address = 0xfc040628; sn = "INTC_0_PSR740"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR741 { address = 0xfc04062a; sn = "INTC_0_PSR741"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR742 { address = 0xfc04062c; sn = "INTC_0_PSR742"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR743 { address = 0xfc04062e; sn = "INTC_0_PSR743"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR744 { address = 0xfc040630; sn = "INTC_0_PSR744"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR745 { address = 0xfc040632; sn = "INTC_0_PSR745"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR746 { address = 0xfc040634; sn = "INTC_0_PSR746"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR747 { address = 0xfc040636; sn = "INTC_0_PSR747"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR748 { address = 0xfc040638; sn = "INTC_0_PSR748"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR749 { address = 0xfc04063a; sn = "INTC_0_PSR749"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR750 { address = 0xfc04063c; sn = "INTC_0_PSR750"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR751 { address = 0xfc04063e; sn = "INTC_0_PSR751"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR752 { address = 0xfc040640; sn = "INTC_0_PSR752"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR753 { address = 0xfc040642; sn = "INTC_0_PSR753"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR754 { address = 0xfc040644; sn = "INTC_0_PSR754"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR755 { address = 0xfc040646; sn = "INTC_0_PSR755"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR756 { address = 0xfc040648; sn = "INTC_0_PSR756"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR757 { address = 0xfc04064a; sn = "INTC_0_PSR757"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR758 { address = 0xfc04064c; sn = "INTC_0_PSR758"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR759 { address = 0xfc04064e; sn = "INTC_0_PSR759"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR760 { address = 0xfc040650; sn = "INTC_0_PSR760"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR761 { address = 0xfc040652; sn = "INTC_0_PSR761"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR762 { address = 0xfc040654; sn = "INTC_0_PSR762"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR763 { address = 0xfc040656; sn = "INTC_0_PSR763"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR764 { address = 0xfc040658; sn = "INTC_0_PSR764"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR765 { address = 0xfc04065a; sn = "INTC_0_PSR765"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR766 { address = 0xfc04065c; sn = "INTC_0_PSR766"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR767 { address = 0xfc04065e; sn = "INTC_0_PSR767"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR768 { address = 0xfc040660; sn = "INTC_0_PSR768"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR769 { address = 0xfc040662; sn = "INTC_0_PSR769"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR770 { address = 0xfc040664; sn = "INTC_0_PSR770"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR771 { address = 0xfc040666; sn = "INTC_0_PSR771"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR772 { address = 0xfc040668; sn = "INTC_0_PSR772"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR773 { address = 0xfc04066a; sn = "INTC_0_PSR773"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR774 { address = 0xfc04066c; sn = "INTC_0_PSR774"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR775 { address = 0xfc04066e; sn = "INTC_0_PSR775"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR776 { address = 0xfc040670; sn = "INTC_0_PSR776"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR777 { address = 0xfc040672; sn = "INTC_0_PSR777"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR778 { address = 0xfc040674; sn = "INTC_0_PSR778"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR779 { address = 0xfc040676; sn = "INTC_0_PSR779"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR780 { address = 0xfc040678; sn = "INTC_0_PSR780"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR781 { address = 0xfc04067a; sn = "INTC_0_PSR781"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR782 { address = 0xfc04067c; sn = "INTC_0_PSR782"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR783 { address = 0xfc04067e; sn = "INTC_0_PSR783"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR784 { address = 0xfc040680; sn = "INTC_0_PSR784"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR785 { address = 0xfc040682; sn = "INTC_0_PSR785"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR786 { address = 0xfc040684; sn = "INTC_0_PSR786"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR787 { address = 0xfc040686; sn = "INTC_0_PSR787"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR788 { address = 0xfc040688; sn = "INTC_0_PSR788"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR789 { address = 0xfc04068a; sn = "INTC_0_PSR789"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR790 { address = 0xfc04068c; sn = "INTC_0_PSR790"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR791 { address = 0xfc04068e; sn = "INTC_0_PSR791"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR792 { address = 0xfc040690; sn = "INTC_0_PSR792"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR793 { address = 0xfc040692; sn = "INTC_0_PSR793"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR794 { address = 0xfc040694; sn = "INTC_0_PSR794"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR795 { address = 0xfc040696; sn = "INTC_0_PSR795"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR796 { address = 0xfc040698; sn = "INTC_0_PSR796"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR797 { address = 0xfc04069a; sn = "INTC_0_PSR797"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR798 { address = 0xfc04069c; sn = "INTC_0_PSR798"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR799 { address = 0xfc04069e; sn = "INTC_0_PSR799"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR800 { address = 0xfc0406a0; sn = "INTC_0_PSR800"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR801 { address = 0xfc0406a2; sn = "INTC_0_PSR801"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR802 { address = 0xfc0406a4; sn = "INTC_0_PSR802"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR803 { address = 0xfc0406a6; sn = "INTC_0_PSR803"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR804 { address = 0xfc0406a8; sn = "INTC_0_PSR804"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR805 { address = 0xfc0406aa; sn = "INTC_0_PSR805"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR806 { address = 0xfc0406ac; sn = "INTC_0_PSR806"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR807 { address = 0xfc0406ae; sn = "INTC_0_PSR807"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR808 { address = 0xfc0406b0; sn = "INTC_0_PSR808"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR809 { address = 0xfc0406b2; sn = "INTC_0_PSR809"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR810 { address = 0xfc0406b4; sn = "INTC_0_PSR810"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR811 { address = 0xfc0406b6; sn = "INTC_0_PSR811"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR812 { address = 0xfc0406b8; sn = "INTC_0_PSR812"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR813 { address = 0xfc0406ba; sn = "INTC_0_PSR813"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR814 { address = 0xfc0406bc; sn = "INTC_0_PSR814"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR815 { address = 0xfc0406be; sn = "INTC_0_PSR815"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR816 { address = 0xfc0406c0; sn = "INTC_0_PSR816"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR817 { address = 0xfc0406c2; sn = "INTC_0_PSR817"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR818 { address = 0xfc0406c4; sn = "INTC_0_PSR818"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR819 { address = 0xfc0406c6; sn = "INTC_0_PSR819"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR820 { address = 0xfc0406c8; sn = "INTC_0_PSR820"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR821 { address = 0xfc0406ca; sn = "INTC_0_PSR821"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR822 { address = 0xfc0406cc; sn = "INTC_0_PSR822"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR823 { address = 0xfc0406ce; sn = "INTC_0_PSR823"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR824 { address = 0xfc0406d0; sn = "INTC_0_PSR824"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR825 { address = 0xfc0406d2; sn = "INTC_0_PSR825"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR826 { address = 0xfc0406d4; sn = "INTC_0_PSR826"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR827 { address = 0xfc0406d6; sn = "INTC_0_PSR827"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR828 { address = 0xfc0406d8; sn = "INTC_0_PSR828"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR829 { address = 0xfc0406da; sn = "INTC_0_PSR829"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR830 { address = 0xfc0406dc; sn = "INTC_0_PSR830"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR831 { address = 0xfc0406de; sn = "INTC_0_PSR831"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR832 { address = 0xfc0406e0; sn = "INTC_0_PSR832"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR833 { address = 0xfc0406e2; sn = "INTC_0_PSR833"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR834 { address = 0xfc0406e4; sn = "INTC_0_PSR834"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR835 { address = 0xfc0406e6; sn = "INTC_0_PSR835"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR836 { address = 0xfc0406e8; sn = "INTC_0_PSR836"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR837 { address = 0xfc0406ea; sn = "INTC_0_PSR837"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR838 { address = 0xfc0406ec; sn = "INTC_0_PSR838"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR839 { address = 0xfc0406ee; sn = "INTC_0_PSR839"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR840 { address = 0xfc0406f0; sn = "INTC_0_PSR840"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR841 { address = 0xfc0406f2; sn = "INTC_0_PSR841"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR842 { address = 0xfc0406f4; sn = "INTC_0_PSR842"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR843 { address = 0xfc0406f6; sn = "INTC_0_PSR843"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR844 { address = 0xfc0406f8; sn = "INTC_0_PSR844"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR845 { address = 0xfc0406fa; sn = "INTC_0_PSR845"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR846 { address = 0xfc0406fc; sn = "INTC_0_PSR846"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR847 { address = 0xfc0406fe; sn = "INTC_0_PSR847"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR848 { address = 0xfc040700; sn = "INTC_0_PSR848"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR849 { address = 0xfc040702; sn = "INTC_0_PSR849"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR850 { address = 0xfc040704; sn = "INTC_0_PSR850"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR851 { address = 0xfc040706; sn = "INTC_0_PSR851"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR852 { address = 0xfc040708; sn = "INTC_0_PSR852"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR853 { address = 0xfc04070a; sn = "INTC_0_PSR853"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR854 { address = 0xfc04070c; sn = "INTC_0_PSR854"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR855 { address = 0xfc04070e; sn = "INTC_0_PSR855"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR856 { address = 0xfc040710; sn = "INTC_0_PSR856"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR857 { address = 0xfc040712; sn = "INTC_0_PSR857"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR858 { address = 0xfc040714; sn = "INTC_0_PSR858"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR859 { address = 0xfc040716; sn = "INTC_0_PSR859"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR860 { address = 0xfc040718; sn = "INTC_0_PSR860"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR861 { address = 0xfc04071a; sn = "INTC_0_PSR861"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR862 { address = 0xfc04071c; sn = "INTC_0_PSR862"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR863 { address = 0xfc04071e; sn = "INTC_0_PSR863"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR864 { address = 0xfc040720; sn = "INTC_0_PSR864"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR865 { address = 0xfc040722; sn = "INTC_0_PSR865"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR866 { address = 0xfc040724; sn = "INTC_0_PSR866"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR867 { address = 0xfc040726; sn = "INTC_0_PSR867"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR868 { address = 0xfc040728; sn = "INTC_0_PSR868"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR869 { address = 0xfc04072a; sn = "INTC_0_PSR869"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR870 { address = 0xfc04072c; sn = "INTC_0_PSR870"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR871 { address = 0xfc04072e; sn = "INTC_0_PSR871"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR872 { address = 0xfc040730; sn = "INTC_0_PSR872"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR873 { address = 0xfc040732; sn = "INTC_0_PSR873"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR874 { address = 0xfc040734; sn = "INTC_0_PSR874"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR875 { address = 0xfc040736; sn = "INTC_0_PSR875"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR876 { address = 0xfc040738; sn = "INTC_0_PSR876"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR877 { address = 0xfc04073a; sn = "INTC_0_PSR877"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR878 { address = 0xfc04073c; sn = "INTC_0_PSR878"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR879 { address = 0xfc04073e; sn = "INTC_0_PSR879"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR880 { address = 0xfc040740; sn = "INTC_0_PSR880"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR881 { address = 0xfc040742; sn = "INTC_0_PSR881"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR882 { address = 0xfc040744; sn = "INTC_0_PSR882"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR883 { address = 0xfc040746; sn = "INTC_0_PSR883"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR884 { address = 0xfc040748; sn = "INTC_0_PSR884"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR885 { address = 0xfc04074a; sn = "INTC_0_PSR885"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR886 { address = 0xfc04074c; sn = "INTC_0_PSR886"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR887 { address = 0xfc04074e; sn = "INTC_0_PSR887"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR888 { address = 0xfc040750; sn = "INTC_0_PSR888"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR889 { address = 0xfc040752; sn = "INTC_0_PSR889"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR890 { address = 0xfc040754; sn = "INTC_0_PSR890"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR891 { address = 0xfc040756; sn = "INTC_0_PSR891"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR892 { address = 0xfc040758; sn = "INTC_0_PSR892"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR893 { address = 0xfc04075a; sn = "INTC_0_PSR893"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR894 { address = 0xfc04075c; sn = "INTC_0_PSR894"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR895 { address = 0xfc04075e; sn = "INTC_0_PSR895"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR896 { address = 0xfc040760; sn = "INTC_0_PSR896"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR897 { address = 0xfc040762; sn = "INTC_0_PSR897"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR898 { address = 0xfc040764; sn = "INTC_0_PSR898"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR899 { address = 0xfc040766; sn = "INTC_0_PSR899"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR900 { address = 0xfc040768; sn = "INTC_0_PSR900"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR901 { address = 0xfc04076a; sn = "INTC_0_PSR901"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR902 { address = 0xfc04076c; sn = "INTC_0_PSR902"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR903 { address = 0xfc04076e; sn = "INTC_0_PSR903"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR904 { address = 0xfc040770; sn = "INTC_0_PSR904"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR905 { address = 0xfc040772; sn = "INTC_0_PSR905"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR906 { address = 0xfc040774; sn = "INTC_0_PSR906"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR907 { address = 0xfc040776; sn = "INTC_0_PSR907"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR908 { address = 0xfc040778; sn = "INTC_0_PSR908"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR909 { address = 0xfc04077a; sn = "INTC_0_PSR909"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR910 { address = 0xfc04077c; sn = "INTC_0_PSR910"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR911 { address = 0xfc04077e; sn = "INTC_0_PSR911"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR912 { address = 0xfc040780; sn = "INTC_0_PSR912"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR913 { address = 0xfc040782; sn = "INTC_0_PSR913"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR914 { address = 0xfc040784; sn = "INTC_0_PSR914"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR915 { address = 0xfc040786; sn = "INTC_0_PSR915"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR916 { address = 0xfc040788; sn = "INTC_0_PSR916"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR917 { address = 0xfc04078a; sn = "INTC_0_PSR917"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR918 { address = 0xfc04078c; sn = "INTC_0_PSR918"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR919 { address = 0xfc04078e; sn = "INTC_0_PSR919"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR920 { address = 0xfc040790; sn = "INTC_0_PSR920"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR921 { address = 0xfc040792; sn = "INTC_0_PSR921"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR922 { address = 0xfc040794; sn = "INTC_0_PSR922"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR923 { address = 0xfc040796; sn = "INTC_0_PSR923"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR924 { address = 0xfc040798; sn = "INTC_0_PSR924"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR925 { address = 0xfc04079a; sn = "INTC_0_PSR925"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR926 { address = 0xfc04079c; sn = "INTC_0_PSR926"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR927 { address = 0xfc04079e; sn = "INTC_0_PSR927"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR928 { address = 0xfc0407a0; sn = "INTC_0_PSR928"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR929 { address = 0xfc0407a2; sn = "INTC_0_PSR929"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR930 { address = 0xfc0407a4; sn = "INTC_0_PSR930"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR931 { address = 0xfc0407a6; sn = "INTC_0_PSR931"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR932 { address = 0xfc0407a8; sn = "INTC_0_PSR932"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR933 { address = 0xfc0407aa; sn = "INTC_0_PSR933"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR934 { address = 0xfc0407ac; sn = "INTC_0_PSR934"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR935 { address = 0xfc0407ae; sn = "INTC_0_PSR935"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR936 { address = 0xfc0407b0; sn = "INTC_0_PSR936"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR937 { address = 0xfc0407b2; sn = "INTC_0_PSR937"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR938 { address = 0xfc0407b4; sn = "INTC_0_PSR938"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR939 { address = 0xfc0407b6; sn = "INTC_0_PSR939"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR940 { address = 0xfc0407b8; sn = "INTC_0_PSR940"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR941 { address = 0xfc0407ba; sn = "INTC_0_PSR941"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR942 { address = 0xfc0407bc; sn = "INTC_0_PSR942"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR943 { address = 0xfc0407be; sn = "INTC_0_PSR943"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR944 { address = 0xfc0407c0; sn = "INTC_0_PSR944"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR945 { address = 0xfc0407c2; sn = "INTC_0_PSR945"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR946 { address = 0xfc0407c4; sn = "INTC_0_PSR946"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR947 { address = 0xfc0407c6; sn = "INTC_0_PSR947"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR948 { address = 0xfc0407c8; sn = "INTC_0_PSR948"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR949 { address = 0xfc0407ca; sn = "INTC_0_PSR949"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR950 { address = 0xfc0407cc; sn = "INTC_0_PSR950"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR951 { address = 0xfc0407ce; sn = "INTC_0_PSR951"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR952 { address = 0xfc0407d0; sn = "INTC_0_PSR952"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR953 { address = 0xfc0407d2; sn = "INTC_0_PSR953"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR954 { address = 0xfc0407d4; sn = "INTC_0_PSR954"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR955 { address = 0xfc0407d6; sn = "INTC_0_PSR955"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR956 { address = 0xfc0407d8; sn = "INTC_0_PSR956"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR957 { address = 0xfc0407da; sn = "INTC_0_PSR957"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR958 { address = 0xfc0407dc; sn = "INTC_0_PSR958"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR959 { address = 0xfc0407de; sn = "INTC_0_PSR959"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR960 { address = 0xfc0407e0; sn = "INTC_0_PSR960"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR961 { address = 0xfc0407e2; sn = "INTC_0_PSR961"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR962 { address = 0xfc0407e4; sn = "INTC_0_PSR962"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR963 { address = 0xfc0407e6; sn = "INTC_0_PSR963"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR964 { address = 0xfc0407e8; sn = "INTC_0_PSR964"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR965 { address = 0xfc0407ea; sn = "INTC_0_PSR965"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR966 { address = 0xfc0407ec; sn = "INTC_0_PSR966"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR967 { address = 0xfc0407ee; sn = "INTC_0_PSR967"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR968 { address = 0xfc0407f0; sn = "INTC_0_PSR968"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR969 { address = 0xfc0407f2; sn = "INTC_0_PSR969"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR970 { address = 0xfc0407f4; sn = "INTC_0_PSR970"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR971 { address = 0xfc0407f6; sn = "INTC_0_PSR971"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR972 { address = 0xfc0407f8; sn = "INTC_0_PSR972"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR973 { address = 0xfc0407fa; sn = "INTC_0_PSR973"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR974 { address = 0xfc0407fc; sn = "INTC_0_PSR974"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR975 { address = 0xfc0407fe; sn = "INTC_0_PSR975"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR976 { address = 0xfc040800; sn = "INTC_0_PSR976"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR977 { address = 0xfc040802; sn = "INTC_0_PSR977"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR978 { address = 0xfc040804; sn = "INTC_0_PSR978"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR979 { address = 0xfc040806; sn = "INTC_0_PSR979"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR980 { address = 0xfc040808; sn = "INTC_0_PSR980"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR981 { address = 0xfc04080a; sn = "INTC_0_PSR981"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR982 { address = 0xfc04080c; sn = "INTC_0_PSR982"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR983 { address = 0xfc04080e; sn = "INTC_0_PSR983"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR984 { address = 0xfc040810; sn = "INTC_0_PSR984"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR985 { address = 0xfc040812; sn = "INTC_0_PSR985"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR986 { address = 0xfc040814; sn = "INTC_0_PSR986"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR987 { address = 0xfc040816; sn = "INTC_0_PSR987"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR988 { address = 0xfc040818; sn = "INTC_0_PSR988"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR989 { address = 0xfc04081a; sn = "INTC_0_PSR989"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR990 { address = 0xfc04081c; sn = "INTC_0_PSR990"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR991 { address = 0xfc04081e; sn = "INTC_0_PSR991"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR992 { address = 0xfc040820; sn = "INTC_0_PSR992"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR993 { address = 0xfc040822; sn = "INTC_0_PSR993"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR994 { address = 0xfc040824; sn = "INTC_0_PSR994"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR995 { address = 0xfc040826; sn = "INTC_0_PSR995"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR996 { address = 0xfc040828; sn = "INTC_0_PSR996"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR997 { address = 0xfc04082a; sn = "INTC_0_PSR997"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR998 { address = 0xfc04082c; sn = "INTC_0_PSR998"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR999 { address = 0xfc04082e; sn = "INTC_0_PSR999"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR1000 { address = 0xfc040830; sn = "INTC_0_PSR1000"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR1001 { address = 0xfc040832; sn = "INTC_0_PSR1001"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR1002 { address = 0xfc040834; sn = "INTC_0_PSR1002"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR1003 { address = 0xfc040836; sn = "INTC_0_PSR1003"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR1004 { address = 0xfc040838; sn = "INTC_0_PSR1004"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR1005 { address = 0xfc04083a; sn = "INTC_0_PSR1005"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR1006 { address = 0xfc04083c; sn = "INTC_0_PSR1006"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR1007 { address = 0xfc04083e; sn = "INTC_0_PSR1007"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR1008 { address = 0xfc040840; sn = "INTC_0_PSR1008"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR1009 { address = 0xfc040842; sn = "INTC_0_PSR1009"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR1010 { address = 0xfc040844; sn = "INTC_0_PSR1010"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR1011 { address = 0xfc040846; sn = "INTC_0_PSR1011"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR1012 { address = 0xfc040848; sn = "INTC_0_PSR1012"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR1013 { address = 0xfc04084a; sn = "INTC_0_PSR1013"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR1014 { address = 0xfc04084c; sn = "INTC_0_PSR1014"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR1015 { address = 0xfc04084e; sn = "INTC_0_PSR1015"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR1016 { address = 0xfc040850; sn = "INTC_0_PSR1016"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR1017 { address = 0xfc040852; sn = "INTC_0_PSR1017"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR1018 { address = 0xfc040854; sn = "INTC_0_PSR1018"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR1019 { address = 0xfc040856; sn = "INTC_0_PSR1019"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR1020 { address = 0xfc040858; sn = "INTC_0_PSR1020"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR1021 { address = 0xfc04085a; sn = "INTC_0_PSR1021"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR1022 { address = 0xfc04085c; sn = "INTC_0_PSR1022"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } INTC_0_PSR1023 { address = 0xfc04085e; sn = "INTC_0_PSR1023"; access = "memorymapped"; width = 16; ${_DESC611_}; type = "bitfield_INTC_0_PSR0" } IRCOSC_CTL { address = 0xfffb0000; sn = "IRCOSC_CTL"; access = "memorymapped"; width = 32; ${_DESC615_}; type = "bitfield_IRCOSC_CTL" } IRCOSC_NT { address = 0xfffb0004; sn = "IRCOSC_NT"; access = "memorymapped"; width = 32; ${_DESC620_}; type = "bitfield_IRCOSC_NT" permission = "write/none" } IRCOSC_TT { address = 0xfffb0008; sn = "IRCOSC_TT"; access = "memorymapped"; width = 32; ${_DESC624_}; type = "bitfield_IRCOSC_TT" } LFAST_0_MCR { address = 0xfffd8000; sn = "LFAST_0_MCR"; access = "memorymapped"; width = 32; ${_DESC628_}; type = "bitfield_LFAST_0_MCR" } LFAST_0_SCR { address = 0xfffd8004; sn = "LFAST_0_SCR"; access = "memorymapped"; width = 32; ${_DESC639_}; type = "bitfield_LFAST_0_SCR" } LFAST_0_COCR { address = 0xfffd8008; sn = "LFAST_0_COCR"; access = "memorymapped"; width = 32; ${_DESC643_}; type = "bitfield_LFAST_0_COCR" } LFAST_0_TMCR { address = 0xfffd800c; sn = "LFAST_0_TMCR"; access = "memorymapped"; width = 32; ${_DESC646_}; type = "bitfield_LFAST_0_TMCR" } LFAST_0_ALCR { address = 0xfffd8010; sn = "LFAST_0_ALCR"; access = "memorymapped"; width = 32; ${_DESC651_}; type = "bitfield_LFAST_0_ALCR" } LFAST_0_RCDCR { address = 0xfffd8014; sn = "LFAST_0_RCDCR"; access = "memorymapped"; width = 32; ${_DESC654_}; type = "bitfield_LFAST_0_RCDCR" } LFAST_0_SLCR { address = 0xfffd8018; sn = "LFAST_0_SLCR"; access = "memorymapped"; width = 32; ${_DESC656_}; type = "bitfield_LFAST_0_SLCR" } LFAST_0_ICR { address = 0xfffd801c; sn = "LFAST_0_ICR"; access = "memorymapped"; width = 32; ${_DESC661_}; type = "bitfield_LFAST_0_ICR" } LFAST_0_PICR { address = 0xfffd8020; sn = "LFAST_0_PICR"; access = "memorymapped"; width = 32; ${_DESC665_}; type = "bitfield_LFAST_0_PICR" } LFAST_0_RFCR { address = 0xfffd802c; sn = "LFAST_0_RFCR"; access = "memorymapped"; width = 32; ${_DESC669_}; type = "bitfield_LFAST_0_RFCR" } LFAST_0_TIER { address = 0xfffd8030; sn = "LFAST_0_TIER"; access = "memorymapped"; width = 32; ${_DESC672_}; type = "bitfield_LFAST_0_TIER" } LFAST_0_RIER { address = 0xfffd8034; sn = "LFAST_0_RIER"; access = "memorymapped"; width = 32; ${_DESC679_}; type = "bitfield_LFAST_0_RIER" } LFAST_0_RIIER { address = 0xfffd8038; sn = "LFAST_0_RIIER"; access = "memorymapped"; width = 32; ${_DESC691_}; type = "bitfield_LFAST_0_RIIER" } LFAST_0_LCR { address = 0xfffd8040; sn = "LFAST_0_LCR"; access = "memorymapped"; width = 32; ${_DESC706_}; type = "bitfield_LFAST_0_LCR" } LFAST_0_UNSTCR { address = 0xfffd8044; sn = "LFAST_0_UNSTCR"; access = "memorymapped"; width = 32; ${_DESC724_}; type = "bitfield_LFAST_0_UNSTCR" } LFAST_0_UNSTDR8 { address = 0xfffd8048; sn = "LFAST_0_UNSTDR8"; access = "memorymapped"; width = 32; ${_DESC727_}; type = "bitfield_LFAST_0_UNSTDR8" } LFAST_0_UNSTDR7 { address = 0xfffd804c; sn = "LFAST_0_UNSTDR7"; access = "memorymapped"; width = 32; ${_DESC727_}; type = "bitfield_LFAST_0_UNSTDR8" } LFAST_0_UNSTDR6 { address = 0xfffd8050; sn = "LFAST_0_UNSTDR6"; access = "memorymapped"; width = 32; ${_DESC727_}; type = "bitfield_LFAST_0_UNSTDR8" } LFAST_0_UNSTDR5 { address = 0xfffd8054; sn = "LFAST_0_UNSTDR5"; access = "memorymapped"; width = 32; ${_DESC727_}; type = "bitfield_LFAST_0_UNSTDR8" } LFAST_0_UNSTDR4 { address = 0xfffd8058; sn = "LFAST_0_UNSTDR4"; access = "memorymapped"; width = 32; ${_DESC727_}; type = "bitfield_LFAST_0_UNSTDR8" } LFAST_0_UNSTDR3 { address = 0xfffd805c; sn = "LFAST_0_UNSTDR3"; access = "memorymapped"; width = 32; ${_DESC727_}; type = "bitfield_LFAST_0_UNSTDR8" } LFAST_0_UNSTDR2 { address = 0xfffd8060; sn = "LFAST_0_UNSTDR2"; access = "memorymapped"; width = 32; ${_DESC727_}; type = "bitfield_LFAST_0_UNSTDR8" } LFAST_0_UNSTDR1 { address = 0xfffd8064; sn = "LFAST_0_UNSTDR1"; access = "memorymapped"; width = 32; ${_DESC727_}; type = "bitfield_LFAST_0_UNSTDR8" } LFAST_0_UNSTDR0 { address = 0xfffd8068; sn = "LFAST_0_UNSTDR0"; access = "memorymapped"; width = 32; ${_DESC727_}; type = "bitfield_LFAST_0_UNSTDR8" } LFAST_0_GSR { address = 0xfffd8080; sn = "LFAST_0_GSR"; access = "memorymapped"; width = 32; ${_DESC729_}; type = "bitfield_LFAST_0_GSR" permission = "write/none" } LFAST_0_PISR { address = 0xfffd8084; sn = "LFAST_0_PISR"; access = "memorymapped"; width = 32; ${_DESC739_}; type = "bitfield_LFAST_0_PISR" permission = "write/none" } LFAST_0_DFSR { address = 0xfffd8094; sn = "LFAST_0_DFSR"; access = "memorymapped"; width = 32; ${_DESC741_}; type = "bitfield_LFAST_0_DFSR" permission = "write/none" } LFAST_0_TISR { address = 0xfffd8098; sn = "LFAST_0_TISR"; access = "memorymapped"; width = 32; ${_DESC746_}; type = "bitfield_LFAST_0_TISR" } LFAST_0_RISR { address = 0xfffd809c; sn = "LFAST_0_RISR"; access = "memorymapped"; width = 32; ${_DESC753_}; type = "bitfield_LFAST_0_RISR" } LFAST_0_RIISR { address = 0xfffd80a0; sn = "LFAST_0_RIISR"; access = "memorymapped"; width = 32; ${_DESC764_}; type = "bitfield_LFAST_0_RIISR" } LFAST_0_PLLLSR { address = 0xfffd80a4; sn = "LFAST_0_PLLLSR"; access = "memorymapped"; width = 32; ${_DESC767_}; type = "bitfield_LFAST_0_PLLLSR" permission = "write/none" } LFAST_0_UNSRSR { address = 0xfffd80a8; sn = "LFAST_0_UNSRSR"; access = "memorymapped"; width = 32; ${_DESC772_}; type = "bitfield_LFAST_0_UNSRSR" } LFAST_0_UNSRDR8 { address = 0xfffd80ac; sn = "LFAST_0_UNSRDR8"; access = "memorymapped"; width = 32; ${_DESC775_}; type = "bitfield_LFAST_0_UNSRDR8" permission = "write/none" } LFAST_0_UNSRDR7 { address = 0xfffd80b0; sn = "LFAST_0_UNSRDR7"; access = "memorymapped"; width = 32; ${_DESC775_}; type = "bitfield_LFAST_0_UNSRDR8" permission = "write/none" } LFAST_0_UNSRDR6 { address = 0xfffd80b4; sn = "LFAST_0_UNSRDR6"; access = "memorymapped"; width = 32; ${_DESC775_}; type = "bitfield_LFAST_0_UNSRDR8" permission = "write/none" } LFAST_0_UNSRDR5 { address = 0xfffd80b8; sn = "LFAST_0_UNSRDR5"; access = "memorymapped"; width = 32; ${_DESC775_}; type = "bitfield_LFAST_0_UNSRDR8" permission = "write/none" } LFAST_0_UNSRDR4 { address = 0xfffd80bc; sn = "LFAST_0_UNSRDR4"; access = "memorymapped"; width = 32; ${_DESC775_}; type = "bitfield_LFAST_0_UNSRDR8" permission = "write/none" } LFAST_0_UNSRDR3 { address = 0xfffd80c0; sn = "LFAST_0_UNSRDR3"; access = "memorymapped"; width = 32; ${_DESC775_}; type = "bitfield_LFAST_0_UNSRDR8" permission = "write/none" } LFAST_0_UNSRDR2 { address = 0xfffd80c4; sn = "LFAST_0_UNSRDR2"; access = "memorymapped"; width = 32; ${_DESC775_}; type = "bitfield_LFAST_0_UNSRDR8" permission = "write/none" } LFAST_0_UNSRDR1 { address = 0xfffd80c8; sn = "LFAST_0_UNSRDR1"; access = "memorymapped"; width = 32; ${_DESC775_}; type = "bitfield_LFAST_0_UNSRDR8" permission = "write/none" } LFAST_0_UNSRDR0 { address = 0xfffd80cc; sn = "LFAST_0_UNSRDR0"; access = "memorymapped"; width = 32; ${_DESC775_}; type = "bitfield_LFAST_0_UNSRDR8" permission = "write/none" } LINFlexD_0_LINCR1 { address = 0xffe8c000; sn = "LINFlexD_0_LINCR1"; access = "memorymapped"; width = 32; ${_DESC777_}; type = "bitfield_LINFlexD_0_LINCR1" } LINFlexD_0_LINIER { address = 0xffe8c004; sn = "LINFlexD_0_LINIER"; access = "memorymapped"; width = 32; ${_DESC790_}; type = "bitfield_LINFlexD_0_LINIER" } LINFlexD_0_LINSR { address = 0xffe8c008; sn = "LINFlexD_0_LINSR"; access = "memorymapped"; width = 32; ${_DESC805_}; type = "bitfield_LINFlexD_0_LINSR" } LINFlexD_0_LINESR { address = 0xffe8c00c; sn = "LINFlexD_0_LINESR"; access = "memorymapped"; width = 32; ${_DESC819_}; type = "bitfield_LINFlexD_0_LINESR" } LINFlexD_0_UARTCR { address = 0xffe8c010; sn = "LINFlexD_0_UARTCR"; access = "memorymapped"; width = 32; ${_DESC830_}; type = "bitfield_LINFlexD_0_UARTCR" } LINFlexD_0_UARTSR { address = 0xffe8c014; sn = "LINFlexD_0_UARTSR"; access = "memorymapped"; width = 32; ${_DESC846_}; type = "bitfield_LINFlexD_0_UARTSR" } LINFlexD_0_LINTCSR { address = 0xffe8c018; sn = "LINFlexD_0_LINTCSR"; access = "memorymapped"; width = 32; ${_DESC860_}; type = "bitfield_LINFlexD_0_LINTCSR" } LINFlexD_0_LINOCR { address = 0xffe8c01c; sn = "LINFlexD_0_LINOCR"; access = "memorymapped"; width = 32; ${_DESC865_}; type = "bitfield_LINFlexD_0_LINOCR" } LINFlexD_0_LINTOCR { address = 0xffe8c020; sn = "LINFlexD_0_LINTOCR"; access = "memorymapped"; width = 32; ${_DESC868_}; type = "bitfield_LINFlexD_0_LINTOCR" } LINFlexD_0_LINFBRR { address = 0xffe8c024; sn = "LINFlexD_0_LINFBRR"; access = "memorymapped"; width = 32; ${_DESC871_}; type = "bitfield_LINFlexD_0_LINFBRR" } LINFlexD_0_LINIBRR { address = 0xffe8c028; sn = "LINFlexD_0_LINIBRR"; access = "memorymapped"; width = 32; ${_DESC873_}; type = "bitfield_LINFlexD_0_LINIBRR" } LINFlexD_0_LINCFR { address = 0xffe8c02c; sn = "LINFlexD_0_LINCFR"; access = "memorymapped"; width = 32; ${_DESC875_}; type = "bitfield_LINFlexD_0_LINCFR" } LINFlexD_0_LINCR2 { address = 0xffe8c030; sn = "LINFlexD_0_LINCR2"; access = "memorymapped"; width = 32; ${_DESC877_}; type = "bitfield_LINFlexD_0_LINCR2" } LINFlexD_0_BIDR { address = 0xffe8c034; sn = "LINFlexD_0_BIDR"; access = "memorymapped"; width = 32; ${_DESC886_}; type = "bitfield_LINFlexD_0_BIDR" } LINFlexD_0_BDRL { address = 0xffe8c038; sn = "LINFlexD_0_BDRL"; access = "memorymapped"; width = 32; ${_DESC891_}; type = "bitfield_LINFlexD_0_BDRL" } LINFlexD_0_BDRM { address = 0xffe8c03c; sn = "LINFlexD_0_BDRM"; access = "memorymapped"; width = 32; ${_DESC896_}; type = "bitfield_LINFlexD_0_BDRM" } LINFlexD_0_IFER { address = 0xffe8c040; sn = "LINFlexD_0_IFER"; access = "memorymapped"; width = 32; ${_DESC901_}; type = "bitfield_LINFlexD_0_IFER" } LINFlexD_0_IFMI { address = 0xffe8c044; sn = "LINFlexD_0_IFMI"; access = "memorymapped"; width = 32; ${_DESC903_}; type = "bitfield_LINFlexD_0_IFMI" permission = "write/none" } LINFlexD_0_IFMR { address = 0xffe8c048; sn = "LINFlexD_0_IFMR"; access = "memorymapped"; width = 32; ${_DESC905_}; type = "bitfield_LINFlexD_0_IFMR" } LINFlexD_0_IFCR0 { address = 0xffe8c04c; sn = "LINFlexD_0_IFCR0"; access = "memorymapped"; width = 32; ${_DESC907_}; type = "bitfield_LINFlexD_0_IFCR0" } LINFlexD_0_IFCR1 { address = 0xffe8c050; sn = "LINFlexD_0_IFCR1"; access = "memorymapped"; width = 32; ${_DESC907_}; type = "bitfield_LINFlexD_0_IFCR0" } LINFlexD_0_IFCR2 { address = 0xffe8c054; sn = "LINFlexD_0_IFCR2"; access = "memorymapped"; width = 32; ${_DESC907_}; type = "bitfield_LINFlexD_0_IFCR0" } LINFlexD_0_IFCR3 { address = 0xffe8c058; sn = "LINFlexD_0_IFCR3"; access = "memorymapped"; width = 32; ${_DESC907_}; type = "bitfield_LINFlexD_0_IFCR0" } LINFlexD_0_IFCR4 { address = 0xffe8c05c; sn = "LINFlexD_0_IFCR4"; access = "memorymapped"; width = 32; ${_DESC907_}; type = "bitfield_LINFlexD_0_IFCR0" } LINFlexD_0_IFCR5 { address = 0xffe8c060; sn = "LINFlexD_0_IFCR5"; access = "memorymapped"; width = 32; ${_DESC907_}; type = "bitfield_LINFlexD_0_IFCR0" } LINFlexD_0_IFCR6 { address = 0xffe8c064; sn = "LINFlexD_0_IFCR6"; access = "memorymapped"; width = 32; ${_DESC907_}; type = "bitfield_LINFlexD_0_IFCR0" } LINFlexD_0_IFCR7 { address = 0xffe8c068; sn = "LINFlexD_0_IFCR7"; access = "memorymapped"; width = 32; ${_DESC907_}; type = "bitfield_LINFlexD_0_IFCR0" } LINFlexD_0_IFCR8 { address = 0xffe8c06c; sn = "LINFlexD_0_IFCR8"; access = "memorymapped"; width = 32; ${_DESC907_}; type = "bitfield_LINFlexD_0_IFCR0" } LINFlexD_0_IFCR9 { address = 0xffe8c070; sn = "LINFlexD_0_IFCR9"; access = "memorymapped"; width = 32; ${_DESC907_}; type = "bitfield_LINFlexD_0_IFCR0" } LINFlexD_0_IFCR10 { address = 0xffe8c074; sn = "LINFlexD_0_IFCR10"; access = "memorymapped"; width = 32; ${_DESC907_}; type = "bitfield_LINFlexD_0_IFCR0" } LINFlexD_0_IFCR11 { address = 0xffe8c078; sn = "LINFlexD_0_IFCR11"; access = "memorymapped"; width = 32; ${_DESC907_}; type = "bitfield_LINFlexD_0_IFCR0" } LINFlexD_0_IFCR12 { address = 0xffe8c07c; sn = "LINFlexD_0_IFCR12"; access = "memorymapped"; width = 32; ${_DESC907_}; type = "bitfield_LINFlexD_0_IFCR0" } LINFlexD_0_IFCR13 { address = 0xffe8c080; sn = "LINFlexD_0_IFCR13"; access = "memorymapped"; width = 32; ${_DESC907_}; type = "bitfield_LINFlexD_0_IFCR0" } LINFlexD_0_IFCR14 { address = 0xffe8c084; sn = "LINFlexD_0_IFCR14"; access = "memorymapped"; width = 32; ${_DESC907_}; type = "bitfield_LINFlexD_0_IFCR0" } LINFlexD_0_IFCR15 { address = 0xffe8c088; sn = "LINFlexD_0_IFCR15"; access = "memorymapped"; width = 32; ${_DESC907_}; type = "bitfield_LINFlexD_0_IFCR0" } LINFlexD_0_GCR { address = 0xffe8c08c; sn = "LINFlexD_0_GCR"; access = "memorymapped"; width = 32; ${_DESC912_}; type = "bitfield_LINFlexD_0_GCR" } LINFlexD_0_UARTPTO { address = 0xffe8c090; sn = "LINFlexD_0_UARTPTO"; access = "memorymapped"; width = 32; ${_DESC919_}; type = "bitfield_LINFlexD_0_UARTPTO" } LINFlexD_0_UARTCTO { address = 0xffe8c094; sn = "LINFlexD_0_UARTCTO"; access = "memorymapped"; width = 32; ${_DESC921_}; type = "bitfield_LINFlexD_0_UARTCTO" } LINFlexD_0_DMATXE { address = 0xffe8c098; sn = "LINFlexD_0_DMATXE"; access = "memorymapped"; width = 32; ${_DESC923_}; type = "bitfield_LINFlexD_0_DMATXE" } LINFlexD_0_DMARXE { address = 0xffe8c09c; sn = "LINFlexD_0_DMARXE"; access = "memorymapped"; width = 32; ${_DESC926_}; type = "bitfield_LINFlexD_0_DMARXE" } LINFlexD_1_LINCR1 { address = 0xffe90000; sn = "LINFlexD_1_LINCR1"; access = "memorymapped"; width = 32; ${_DESC777_}; type = "bitfield_LINFlexD_0_LINCR1" } LINFlexD_1_LINIER { address = 0xffe90004; sn = "LINFlexD_1_LINIER"; access = "memorymapped"; width = 32; ${_DESC790_}; type = "bitfield_LINFlexD_0_LINIER" } LINFlexD_1_LINSR { address = 0xffe90008; sn = "LINFlexD_1_LINSR"; access = "memorymapped"; width = 32; ${_DESC805_}; type = "bitfield_LINFlexD_0_LINSR" } LINFlexD_1_LINESR { address = 0xffe9000c; sn = "LINFlexD_1_LINESR"; access = "memorymapped"; width = 32; ${_DESC819_}; type = "bitfield_LINFlexD_0_LINESR" } LINFlexD_1_UARTCR { address = 0xffe90010; sn = "LINFlexD_1_UARTCR"; access = "memorymapped"; width = 32; ${_DESC830_}; type = "bitfield_LINFlexD_0_UARTCR" } LINFlexD_1_UARTSR { address = 0xffe90014; sn = "LINFlexD_1_UARTSR"; access = "memorymapped"; width = 32; ${_DESC846_}; type = "bitfield_LINFlexD_0_UARTSR" } LINFlexD_1_LINTCSR { address = 0xffe90018; sn = "LINFlexD_1_LINTCSR"; access = "memorymapped"; width = 32; ${_DESC860_}; type = "bitfield_LINFlexD_0_LINTCSR" } LINFlexD_1_LINOCR { address = 0xffe9001c; sn = "LINFlexD_1_LINOCR"; access = "memorymapped"; width = 32; ${_DESC865_}; type = "bitfield_LINFlexD_0_LINOCR" } LINFlexD_1_LINTOCR { address = 0xffe90020; sn = "LINFlexD_1_LINTOCR"; access = "memorymapped"; width = 32; ${_DESC868_}; type = "bitfield_LINFlexD_0_LINTOCR" } LINFlexD_1_LINFBRR { address = 0xffe90024; sn = "LINFlexD_1_LINFBRR"; access = "memorymapped"; width = 32; ${_DESC871_}; type = "bitfield_LINFlexD_0_LINFBRR" } LINFlexD_1_LINIBRR { address = 0xffe90028; sn = "LINFlexD_1_LINIBRR"; access = "memorymapped"; width = 32; ${_DESC873_}; type = "bitfield_LINFlexD_0_LINIBRR" } LINFlexD_1_LINCFR { address = 0xffe9002c; sn = "LINFlexD_1_LINCFR"; access = "memorymapped"; width = 32; ${_DESC875_}; type = "bitfield_LINFlexD_0_LINCFR" } LINFlexD_1_LINCR2 { address = 0xffe90030; sn = "LINFlexD_1_LINCR2"; access = "memorymapped"; width = 32; ${_DESC877_}; type = "bitfield_LINFlexD_0_LINCR2" } LINFlexD_1_BIDR { address = 0xffe90034; sn = "LINFlexD_1_BIDR"; access = "memorymapped"; width = 32; ${_DESC886_}; type = "bitfield_LINFlexD_0_BIDR" } LINFlexD_1_BDRL { address = 0xffe90038; sn = "LINFlexD_1_BDRL"; access = "memorymapped"; width = 32; ${_DESC891_}; type = "bitfield_LINFlexD_0_BDRL" } LINFlexD_1_BDRM { address = 0xffe9003c; sn = "LINFlexD_1_BDRM"; access = "memorymapped"; width = 32; ${_DESC896_}; type = "bitfield_LINFlexD_0_BDRM" } LINFlexD_1_IFER { address = 0xffe90040; sn = "LINFlexD_1_IFER"; access = "memorymapped"; width = 32; ${_DESC901_}; type = "bitfield_LINFlexD_0_IFER" } LINFlexD_1_IFMI { address = 0xffe90044; sn = "LINFlexD_1_IFMI"; access = "memorymapped"; width = 32; ${_DESC903_}; type = "bitfield_LINFlexD_0_IFMI" permission = "write/none" } LINFlexD_1_IFMR { address = 0xffe90048; sn = "LINFlexD_1_IFMR"; access = "memorymapped"; width = 32; ${_DESC905_}; type = "bitfield_LINFlexD_0_IFMR" } LINFlexD_1_GCR { address = 0xffe9004c; sn = "LINFlexD_1_GCR"; access = "memorymapped"; width = 32; ${_DESC912_}; type = "bitfield_LINFlexD_0_GCR" } LINFlexD_1_UARTPTO { address = 0xffe90050; sn = "LINFlexD_1_UARTPTO"; access = "memorymapped"; width = 32; ${_DESC919_}; type = "bitfield_LINFlexD_0_UARTPTO" } LINFlexD_1_UARTCTO { address = 0xffe90054; sn = "LINFlexD_1_UARTCTO"; access = "memorymapped"; width = 32; ${_DESC921_}; type = "bitfield_LINFlexD_0_UARTCTO" } LINFlexD_1_DMATXE { address = 0xffe90058; sn = "LINFlexD_1_DMATXE"; access = "memorymapped"; width = 32; ${_DESC923_}; type = "bitfield_LINFlexD_0_DMATXE" } LINFlexD_1_DMARXE { address = 0xffe9005c; sn = "LINFlexD_1_DMARXE"; access = "memorymapped"; width = 32; ${_DESC926_}; type = "bitfield_LINFlexD_0_DMARXE" } LINFlexD_14_LINCR1 { address = 0xffea8000; sn = "LINFlexD_14_LINCR1"; access = "memorymapped"; width = 32; ${_DESC777_}; type = "bitfield_LINFlexD_0_LINCR1" } LINFlexD_14_LINIER { address = 0xffea8004; sn = "LINFlexD_14_LINIER"; access = "memorymapped"; width = 32; ${_DESC790_}; type = "bitfield_LINFlexD_0_LINIER" } LINFlexD_14_LINSR { address = 0xffea8008; sn = "LINFlexD_14_LINSR"; access = "memorymapped"; width = 32; ${_DESC805_}; type = "bitfield_LINFlexD_0_LINSR" } LINFlexD_14_LINESR { address = 0xffea800c; sn = "LINFlexD_14_LINESR"; access = "memorymapped"; width = 32; ${_DESC819_}; type = "bitfield_LINFlexD_0_LINESR" } LINFlexD_14_UARTCR { address = 0xffea8010; sn = "LINFlexD_14_UARTCR"; access = "memorymapped"; width = 32; ${_DESC830_}; type = "bitfield_LINFlexD_0_UARTCR" } LINFlexD_14_UARTSR { address = 0xffea8014; sn = "LINFlexD_14_UARTSR"; access = "memorymapped"; width = 32; ${_DESC846_}; type = "bitfield_LINFlexD_0_UARTSR" } LINFlexD_14_LINTCSR { address = 0xffea8018; sn = "LINFlexD_14_LINTCSR"; access = "memorymapped"; width = 32; ${_DESC860_}; type = "bitfield_LINFlexD_0_LINTCSR" } LINFlexD_14_LINOCR { address = 0xffea801c; sn = "LINFlexD_14_LINOCR"; access = "memorymapped"; width = 32; ${_DESC865_}; type = "bitfield_LINFlexD_0_LINOCR" } LINFlexD_14_LINTOCR { address = 0xffea8020; sn = "LINFlexD_14_LINTOCR"; access = "memorymapped"; width = 32; ${_DESC868_}; type = "bitfield_LINFlexD_0_LINTOCR" } LINFlexD_14_LINFBRR { address = 0xffea8024; sn = "LINFlexD_14_LINFBRR"; access = "memorymapped"; width = 32; ${_DESC871_}; type = "bitfield_LINFlexD_0_LINFBRR" } LINFlexD_14_LINIBRR { address = 0xffea8028; sn = "LINFlexD_14_LINIBRR"; access = "memorymapped"; width = 32; ${_DESC873_}; type = "bitfield_LINFlexD_0_LINIBRR" } LINFlexD_14_LINCFR { address = 0xffea802c; sn = "LINFlexD_14_LINCFR"; access = "memorymapped"; width = 32; ${_DESC875_}; type = "bitfield_LINFlexD_0_LINCFR" } LINFlexD_14_LINCR2 { address = 0xffea8030; sn = "LINFlexD_14_LINCR2"; access = "memorymapped"; width = 32; ${_DESC877_}; type = "bitfield_LINFlexD_0_LINCR2" } LINFlexD_14_BIDR { address = 0xffea8034; sn = "LINFlexD_14_BIDR"; access = "memorymapped"; width = 32; ${_DESC886_}; type = "bitfield_LINFlexD_0_BIDR" } LINFlexD_14_BDRL { address = 0xffea8038; sn = "LINFlexD_14_BDRL"; access = "memorymapped"; width = 32; ${_DESC891_}; type = "bitfield_LINFlexD_0_BDRL" } LINFlexD_14_BDRM { address = 0xffea803c; sn = "LINFlexD_14_BDRM"; access = "memorymapped"; width = 32; ${_DESC896_}; type = "bitfield_LINFlexD_0_BDRM" } LINFlexD_14_IFER { address = 0xffea8040; sn = "LINFlexD_14_IFER"; access = "memorymapped"; width = 32; ${_DESC901_}; type = "bitfield_LINFlexD_0_IFER" } LINFlexD_14_IFMI { address = 0xffea8044; sn = "LINFlexD_14_IFMI"; access = "memorymapped"; width = 32; ${_DESC903_}; type = "bitfield_LINFlexD_0_IFMI" permission = "write/none" } LINFlexD_14_IFMR { address = 0xffea8048; sn = "LINFlexD_14_IFMR"; access = "memorymapped"; width = 32; ${_DESC905_}; type = "bitfield_LINFlexD_0_IFMR" } LINFlexD_14_GCR { address = 0xffea804c; sn = "LINFlexD_14_GCR"; access = "memorymapped"; width = 32; ${_DESC912_}; type = "bitfield_LINFlexD_0_GCR" } LINFlexD_14_UARTPTO { address = 0xffea8050; sn = "LINFlexD_14_UARTPTO"; access = "memorymapped"; width = 32; ${_DESC919_}; type = "bitfield_LINFlexD_0_UARTPTO" } LINFlexD_14_UARTCTO { address = 0xffea8054; sn = "LINFlexD_14_UARTCTO"; access = "memorymapped"; width = 32; ${_DESC921_}; type = "bitfield_LINFlexD_0_UARTCTO" } LINFlexD_14_DMATXE { address = 0xffea8058; sn = "LINFlexD_14_DMATXE"; access = "memorymapped"; width = 32; ${_DESC923_}; type = "bitfield_LINFlexD_0_DMATXE" } LINFlexD_14_DMARXE { address = 0xffea805c; sn = "LINFlexD_14_DMARXE"; access = "memorymapped"; width = 32; ${_DESC926_}; type = "bitfield_LINFlexD_0_DMARXE" } MC_CGM_PCS_SDUR { address = 0xfffb0700; sn = "MC_CGM_PCS_SDUR"; access = "memorymapped"; width = 8; ${_DESC929_}; type = "bitfield_MC_CGM_PCS_SDUR" } MC_CGM_PCS_DIVC1 { address = 0xfffb0704; sn = "MC_CGM_PCS_DIVC1"; access = "memorymapped"; width = 32; ${_DESC931_}; type = "bitfield_MC_CGM_PCS_DIVC1" } MC_CGM_PCS_DIVS1 { address = 0xfffb0708; sn = "MC_CGM_PCS_DIVS1"; access = "memorymapped"; width = 32; ${_DESC934_}; type = "bitfield_MC_CGM_PCS_DIVS1" } MC_CGM_PCS_DIVE1 { address = 0xfffb070c; sn = "MC_CGM_PCS_DIVE1"; access = "memorymapped"; width = 32; ${_DESC936_}; type = "bitfield_MC_CGM_PCS_DIVE1" } MC_CGM_PCS_DIVC2 { address = 0xfffb0710; sn = "MC_CGM_PCS_DIVC2"; access = "memorymapped"; width = 32; ${_DESC938_}; type = "bitfield_MC_CGM_PCS_DIVC2" } MC_CGM_PCS_DIVS2 { address = 0xfffb0714; sn = "MC_CGM_PCS_DIVS2"; access = "memorymapped"; width = 32; ${_DESC941_}; type = "bitfield_MC_CGM_PCS_DIVS2" } MC_CGM_PCS_DIVE2 { address = 0xfffb0718; sn = "MC_CGM_PCS_DIVE2"; access = "memorymapped"; width = 32; ${_DESC943_}; type = "bitfield_MC_CGM_PCS_DIVE2" } MC_CGM_PCS_DIVC3 { address = 0xfffb071c; sn = "MC_CGM_PCS_DIVC3"; access = "memorymapped"; width = 32; ${_DESC945_}; type = "bitfield_MC_CGM_PCS_DIVC3" } MC_CGM_PCS_DIVS3 { address = 0xfffb0720; sn = "MC_CGM_PCS_DIVS3"; access = "memorymapped"; width = 32; ${_DESC948_}; type = "bitfield_MC_CGM_PCS_DIVS3" } MC_CGM_PCS_DIVE3 { address = 0xfffb0724; sn = "MC_CGM_PCS_DIVE3"; access = "memorymapped"; width = 32; ${_DESC950_}; type = "bitfield_MC_CGM_PCS_DIVE3" } MC_CGM_SC_SS { address = 0xfffb07e4; sn = "MC_CGM_SC_SS"; access = "memorymapped"; width = 32; ${_DESC952_}; type = "bitfield_MC_CGM_SC_SS" permission = "write/none" } MC_CGM_SC_DC0 { address = 0xfffb07e8; sn = "MC_CGM_SC_DC0"; access = "memorymapped"; width = 32; ${_DESC956_}; type = "bitfield_MC_CGM_SC_DC0" } MC_CGM_SC_DC1 { address = 0xfffb07ec; sn = "MC_CGM_SC_DC1"; access = "memorymapped"; width = 32; ${_DESC959_}; type = "bitfield_MC_CGM_SC_DC1" } MC_CGM_AC0_SC { address = 0xfffb0800; sn = "MC_CGM_AC0_SC"; access = "memorymapped"; width = 32; ${_DESC961_}; type = "bitfield_MC_CGM_AC0_SC" } MC_CGM_AC0_SS { address = 0xfffb0804; sn = "MC_CGM_AC0_SS"; access = "memorymapped"; width = 32; ${_DESC963_}; type = "bitfield_MC_CGM_AC0_SS" permission = "write/none" } MC_CGM_AC0_DC0 { address = 0xfffb0808; sn = "MC_CGM_AC0_DC0"; access = "memorymapped"; width = 32; ${_DESC965_}; type = "bitfield_MC_CGM_AC0_DC0" } MC_CGM_AC0_DC1 { address = 0xfffb080c; sn = "MC_CGM_AC0_DC1"; access = "memorymapped"; width = 32; ${_DESC968_}; type = "bitfield_MC_CGM_AC0_DC1" } MC_CGM_AC0_DC2 { address = 0xfffb0810; sn = "MC_CGM_AC0_DC2"; access = "memorymapped"; width = 32; ${_DESC970_}; type = "bitfield_MC_CGM_AC0_DC2" } MC_CGM_AC1_SC { address = 0xfffb0820; sn = "MC_CGM_AC1_SC"; access = "memorymapped"; width = 32; ${_DESC972_}; type = "bitfield_MC_CGM_AC1_SC" } MC_CGM_AC1_SS { address = 0xfffb0824; sn = "MC_CGM_AC1_SS"; access = "memorymapped"; width = 32; ${_DESC974_}; type = "bitfield_MC_CGM_AC1_SS" permission = "write/none" } MC_CGM_AC1_DC0 { address = 0xfffb0828; sn = "MC_CGM_AC1_DC0"; access = "memorymapped"; width = 32; ${_DESC976_}; type = "bitfield_MC_CGM_AC1_DC0" } MC_CGM_AC2_DC0 { address = 0xfffb0848; sn = "MC_CGM_AC2_DC0"; access = "memorymapped"; width = 32; ${_DESC978_}; type = "bitfield_MC_CGM_AC2_DC0" } MC_CGM_AC3_SC { address = 0xfffb0860; sn = "MC_CGM_AC3_SC"; access = "memorymapped"; width = 32; ${_DESC980_}; type = "bitfield_MC_CGM_AC3_SC" } MC_CGM_AC3_SS { address = 0xfffb0864; sn = "MC_CGM_AC3_SS"; access = "memorymapped"; width = 32; ${_DESC982_}; type = "bitfield_MC_CGM_AC3_SS" permission = "write/none" } MC_CGM_AC7_SC { address = 0xfffb08e0; sn = "MC_CGM_AC7_SC"; access = "memorymapped"; width = 32; ${_DESC984_}; type = "bitfield_MC_CGM_AC7_SC" } MC_CGM_AC7_SS { address = 0xfffb08e4; sn = "MC_CGM_AC7_SS"; access = "memorymapped"; width = 32; ${_DESC986_}; type = "bitfield_MC_CGM_AC7_SS" permission = "write/none" } MC_CGM_AC7_DC0 { address = 0xfffb08e8; sn = "MC_CGM_AC7_DC0"; access = "memorymapped"; width = 32; ${_DESC988_}; type = "bitfield_MC_CGM_AC7_DC0" } MC_CGM_AC8_SC { address = 0xfffb0900; sn = "MC_CGM_AC8_SC"; access = "memorymapped"; width = 32; ${_DESC990_}; type = "bitfield_MC_CGM_AC8_SC" } MC_CGM_AC8_SS { address = 0xfffb0904; sn = "MC_CGM_AC8_SS"; access = "memorymapped"; width = 32; ${_DESC992_}; type = "bitfield_MC_CGM_AC8_SS" permission = "write/none" } MC_CGM_AC8_DC0 { address = 0xfffb0908; sn = "MC_CGM_AC8_DC0"; access = "memorymapped"; width = 32; ${_DESC994_}; type = "bitfield_MC_CGM_AC8_DC0" } MC_CGM_AC10_SC { address = 0xfffb0940; sn = "MC_CGM_AC10_SC"; access = "memorymapped"; width = 32; ${_DESC996_}; type = "bitfield_MC_CGM_AC10_SC" } MC_CGM_AC10_SS { address = 0xfffb0944; sn = "MC_CGM_AC10_SS"; access = "memorymapped"; width = 32; ${_DESC998_}; type = "bitfield_MC_CGM_AC10_SS" permission = "write/none" } MC_CGM_AC10_DC0 { address = 0xfffb0948; sn = "MC_CGM_AC10_DC0"; access = "memorymapped"; width = 32; ${_DESC1000_}; type = "bitfield_MC_CGM_AC10_DC0" } MC_CGM_AC11_SC { address = 0xfffb0960; sn = "MC_CGM_AC11_SC"; access = "memorymapped"; width = 32; ${_DESC1002_}; type = "bitfield_MC_CGM_AC11_SC" } MC_CGM_AC11_SS { address = 0xfffb0964; sn = "MC_CGM_AC11_SS"; access = "memorymapped"; width = 32; ${_DESC1004_}; type = "bitfield_MC_CGM_AC11_SS" permission = "write/none" } MC_CGM_AC11_DC0 { address = 0xfffb0968; sn = "MC_CGM_AC11_DC0"; access = "memorymapped"; width = 32; ${_DESC1006_}; type = "bitfield_MC_CGM_AC11_DC0" } MC_CGM_AC11_DC1 { address = 0xfffb096c; sn = "MC_CGM_AC11_DC1"; access = "memorymapped"; width = 32; ${_DESC1010_}; type = "bitfield_MC_CGM_AC11_DC1" } MC_ME_GS { address = 0xfffb8000; sn = "MC_ME_GS"; access = "memorymapped"; width = 32; ${_DESC1012_}; type = "bitfield_MC_ME_GS" permission = "write/none" } MC_ME_MCTL { address = 0xfffb8004; sn = "MC_ME_MCTL"; access = "memorymapped"; width = 32; ${_DESC1022_}; type = "bitfield_MC_ME_MCTL" } MC_ME_ME { address = 0xfffb8008; sn = "MC_ME_ME"; access = "memorymapped"; width = 32; ${_DESC1025_}; type = "bitfield_MC_ME_ME" } MC_ME_IS { address = 0xfffb800c; sn = "MC_ME_IS"; access = "memorymapped"; width = 32; ${_DESC1037_}; type = "bitfield_MC_ME_IS" } MC_ME_IM { address = 0xfffb8010; sn = "MC_ME_IM"; access = "memorymapped"; width = 32; ${_DESC1044_}; type = "bitfield_MC_ME_IM" } MC_ME_IMTS { address = 0xfffb8014; sn = "MC_ME_IMTS"; access = "memorymapped"; width = 32; ${_DESC1051_}; type = "bitfield_MC_ME_IMTS" } MC_ME_DMTS { address = 0xfffb8018; sn = "MC_ME_DMTS"; access = "memorymapped"; width = 32; ${_DESC1057_}; type = "bitfield_MC_ME_DMTS" permission = "write/none" } MC_ME_RESET_MC { address = 0xfffb8020; sn = "MC_ME_RESET_MC"; access = "memorymapped"; width = 32; ${_DESC1079_}; type = "bitfield_MC_ME_RESET_MC" permission = "write/none" } MC_ME_TEST_MC { address = 0xfffb8024; sn = "MC_ME_TEST_MC"; access = "memorymapped"; width = 32; ${_DESC1088_}; type = "bitfield_MC_ME_RESET_MC" } MC_ME_SAFE_MC { address = 0xfffb8028; sn = "MC_ME_SAFE_MC"; access = "memorymapped"; width = 32; ${_DESC1089_}; type = "bitfield_MC_ME_RESET_MC" } MC_ME_DRUN_MC { address = 0xfffb802c; sn = "MC_ME_DRUN_MC"; access = "memorymapped"; width = 32; ${_DESC1090_}; type = "bitfield_MC_ME_RESET_MC" } MC_ME_RUN0_MC { address = 0xfffb8030; sn = "MC_ME_RUN0_MC"; access = "memorymapped"; width = 32; ${_DESC1091_}; type = "bitfield_MC_ME_RESET_MC" } MC_ME_RUN1_MC { address = 0xfffb8034; sn = "MC_ME_RUN1_MC"; access = "memorymapped"; width = 32; ${_DESC1091_}; type = "bitfield_MC_ME_RESET_MC" } MC_ME_RUN2_MC { address = 0xfffb8038; sn = "MC_ME_RUN2_MC"; access = "memorymapped"; width = 32; ${_DESC1091_}; type = "bitfield_MC_ME_RESET_MC" } MC_ME_RUN3_MC { address = 0xfffb803c; sn = "MC_ME_RUN3_MC"; access = "memorymapped"; width = 32; ${_DESC1091_}; type = "bitfield_MC_ME_RESET_MC" } MC_ME_HALT0_MC { address = 0xfffb8040; sn = "MC_ME_HALT0_MC"; access = "memorymapped"; width = 32; ${_DESC1092_}; type = "bitfield_MC_ME_RESET_MC" } MC_ME_STOP0_MC { address = 0xfffb8048; sn = "MC_ME_STOP0_MC"; access = "memorymapped"; width = 32; ${_DESC1093_}; type = "bitfield_MC_ME_RESET_MC" } MC_ME_PS0 { address = 0xfffb8060; sn = "MC_ME_PS0"; access = "memorymapped"; width = 32; ${_DESC1094_}; type = "bitfield_MC_ME_PS0" permission = "write/none" } MC_ME_PS1 { address = 0xfffb8064; sn = "MC_ME_PS1"; access = "memorymapped"; width = 32; ${_DESC1096_}; type = "bitfield_MC_ME_PS1" permission = "write/none" } MC_ME_PS2 { address = 0xfffb8068; sn = "MC_ME_PS2"; access = "memorymapped"; width = 32; ${_DESC1097_}; type = "bitfield_MC_ME_PS2" permission = "write/none" } MC_ME_PS3 { address = 0xfffb806c; sn = "MC_ME_PS3"; access = "memorymapped"; width = 32; ${_DESC1098_}; type = "bitfield_MC_ME_PS3" permission = "write/none" } MC_ME_PS4 { address = 0xfffb8070; sn = "MC_ME_PS4"; access = "memorymapped"; width = 32; ${_DESC1099_}; type = "bitfield_MC_ME_PS4" permission = "write/none" } MC_ME_RUN_PC0 { address = 0xfffb8080; sn = "MC_ME_RUN_PC0"; access = "memorymapped"; width = 32; ${_DESC1100_}; type = "bitfield_MC_ME_RUN_PC0" } MC_ME_RUN_PC1 { address = 0xfffb8084; sn = "MC_ME_RUN_PC1"; access = "memorymapped"; width = 32; ${_DESC1100_}; type = "bitfield_MC_ME_RUN_PC0" } MC_ME_RUN_PC2 { address = 0xfffb8088; sn = "MC_ME_RUN_PC2"; access = "memorymapped"; width = 32; ${_DESC1100_}; type = "bitfield_MC_ME_RUN_PC0" } MC_ME_RUN_PC3 { address = 0xfffb808c; sn = "MC_ME_RUN_PC3"; access = "memorymapped"; width = 32; ${_DESC1100_}; type = "bitfield_MC_ME_RUN_PC0" } MC_ME_RUN_PC4 { address = 0xfffb8090; sn = "MC_ME_RUN_PC4"; access = "memorymapped"; width = 32; ${_DESC1100_}; type = "bitfield_MC_ME_RUN_PC0" } MC_ME_RUN_PC5 { address = 0xfffb8094; sn = "MC_ME_RUN_PC5"; access = "memorymapped"; width = 32; ${_DESC1100_}; type = "bitfield_MC_ME_RUN_PC0" } MC_ME_RUN_PC6 { address = 0xfffb8098; sn = "MC_ME_RUN_PC6"; access = "memorymapped"; width = 32; ${_DESC1100_}; type = "bitfield_MC_ME_RUN_PC0" } MC_ME_RUN_PC7 { address = 0xfffb809c; sn = "MC_ME_RUN_PC7"; access = "memorymapped"; width = 32; ${_DESC1100_}; type = "bitfield_MC_ME_RUN_PC0" } MC_ME_LP_PC0 { address = 0xfffb80a0; sn = "MC_ME_LP_PC0"; access = "memorymapped"; width = 32; ${_DESC1109_}; type = "bitfield_MC_ME_LP_PC0" } MC_ME_LP_PC1 { address = 0xfffb80a4; sn = "MC_ME_LP_PC1"; access = "memorymapped"; width = 32; ${_DESC1109_}; type = "bitfield_MC_ME_LP_PC0" } MC_ME_LP_PC2 { address = 0xfffb80a8; sn = "MC_ME_LP_PC2"; access = "memorymapped"; width = 32; ${_DESC1109_}; type = "bitfield_MC_ME_LP_PC0" } MC_ME_LP_PC3 { address = 0xfffb80ac; sn = "MC_ME_LP_PC3"; access = "memorymapped"; width = 32; ${_DESC1109_}; type = "bitfield_MC_ME_LP_PC0" } MC_ME_LP_PC4 { address = 0xfffb80b0; sn = "MC_ME_LP_PC4"; access = "memorymapped"; width = 32; ${_DESC1109_}; type = "bitfield_MC_ME_LP_PC0" } MC_ME_LP_PC5 { address = 0xfffb80b4; sn = "MC_ME_LP_PC5"; access = "memorymapped"; width = 32; ${_DESC1109_}; type = "bitfield_MC_ME_LP_PC0" } MC_ME_LP_PC6 { address = 0xfffb80b8; sn = "MC_ME_LP_PC6"; access = "memorymapped"; width = 32; ${_DESC1109_}; type = "bitfield_MC_ME_LP_PC0" } MC_ME_LP_PC7 { address = 0xfffb80bc; sn = "MC_ME_LP_PC7"; access = "memorymapped"; width = 32; ${_DESC1109_}; type = "bitfield_MC_ME_LP_PC0" } MC_ME_PCTL9 { address = 0xfffb80c9; sn = "MC_ME_PCTL9"; access = "memorymapped"; width = 8; ${_DESC1112_}; type = "bitfield_MC_ME_PCTL9" } MC_ME_PCTL11 { address = 0xfffb80cb; sn = "MC_ME_PCTL11"; access = "memorymapped"; width = 8; ${_DESC1116_}; type = "bitfield_MC_ME_PCTL9" } MC_ME_PCTL29 { address = 0xfffb80dd; sn = "MC_ME_PCTL29"; access = "memorymapped"; width = 8; ${_DESC1117_}; type = "bitfield_MC_ME_PCTL9" } MC_ME_PCTL30 { address = 0xfffb80de; sn = "MC_ME_PCTL30"; access = "memorymapped"; width = 8; ${_DESC1118_}; type = "bitfield_MC_ME_PCTL9" } MC_ME_PCTL31 { address = 0xfffb80df; sn = "MC_ME_PCTL31"; access = "memorymapped"; width = 8; ${_DESC1119_}; type = "bitfield_MC_ME_PCTL9" } MC_ME_PCTL36 { address = 0xfffb80e4; sn = "MC_ME_PCTL36"; access = "memorymapped"; width = 8; ${_DESC1120_}; type = "bitfield_MC_ME_PCTL9" } MC_ME_PCTL59 { address = 0xfffb80fb; sn = "MC_ME_PCTL59"; access = "memorymapped"; width = 8; ${_DESC1121_}; type = "bitfield_MC_ME_PCTL9" } MC_ME_PCTL69 { address = 0xfffb8105; sn = "MC_ME_PCTL69"; access = "memorymapped"; width = 8; ${_DESC1122_}; type = "bitfield_MC_ME_PCTL9" } MC_ME_PCTL70 { address = 0xfffb8106; sn = "MC_ME_PCTL70"; access = "memorymapped"; width = 8; ${_DESC1123_}; type = "bitfield_MC_ME_PCTL9" } MC_ME_PCTL73 { address = 0xfffb8109; sn = "MC_ME_PCTL73"; access = "memorymapped"; width = 8; ${_DESC1124_}; type = "bitfield_MC_ME_PCTL9" } MC_ME_PCTL74 { address = 0xfffb810a; sn = "MC_ME_PCTL74"; access = "memorymapped"; width = 8; ${_DESC1125_}; type = "bitfield_MC_ME_PCTL9" } MC_ME_PCTL85 { address = 0xfffb8115; sn = "MC_ME_PCTL85"; access = "memorymapped"; width = 8; ${_DESC1126_}; type = "bitfield_MC_ME_PCTL9" } MC_ME_PCTL91 { address = 0xfffb811b; sn = "MC_ME_PCTL91"; access = "memorymapped"; width = 8; ${_DESC1127_}; type = "bitfield_MC_ME_PCTL9" } MC_ME_PCTL92 { address = 0xfffb811c; sn = "MC_ME_PCTL92"; access = "memorymapped"; width = 8; ${_DESC1128_}; type = "bitfield_MC_ME_PCTL9" } MC_ME_PCTL97 { address = 0xfffb8121; sn = "MC_ME_PCTL97"; access = "memorymapped"; width = 8; ${_DESC1129_}; type = "bitfield_MC_ME_PCTL9" } MC_ME_PCTL99 { address = 0xfffb8123; sn = "MC_ME_PCTL99"; access = "memorymapped"; width = 8; ${_DESC1130_}; type = "bitfield_MC_ME_PCTL9" } MC_ME_PCTL104 { address = 0xfffb8128; sn = "MC_ME_PCTL104"; access = "memorymapped"; width = 8; ${_DESC1131_}; type = "bitfield_MC_ME_PCTL9" } MC_ME_PCTL112 { address = 0xfffb8130; sn = "MC_ME_PCTL112"; access = "memorymapped"; width = 8; ${_DESC1132_}; type = "bitfield_MC_ME_PCTL9" } MC_ME_PCTL123 { address = 0xfffb813b; sn = "MC_ME_PCTL123"; access = "memorymapped"; width = 8; ${_DESC1133_}; type = "bitfield_MC_ME_PCTL9" } MC_ME_PCTL127 { address = 0xfffb813f; sn = "MC_ME_PCTL127"; access = "memorymapped"; width = 8; ${_DESC1134_}; type = "bitfield_MC_ME_PCTL9" } MC_ME_PCTL128 { address = 0xfffb8140; sn = "MC_ME_PCTL128"; access = "memorymapped"; width = 8; ${_DESC1135_}; type = "bitfield_MC_ME_PCTL9" } MC_ME_CS { address = 0xfffb81c0; sn = "MC_ME_CS"; access = "memorymapped"; width = 32; ${_DESC1136_}; type = "bitfield_MC_ME_CS" permission = "write/none" } MC_ME_CCTL0 { address = 0xfffb81c4; sn = "MC_ME_CCTL0"; access = "memorymapped"; width = 16; ${_DESC1138_}; type = "bitfield_MC_ME_CCTL0" } MC_ME_CADDR0 { address = 0xfffb81e0; sn = "MC_ME_CADDR0"; access = "memorymapped"; width = 32; ${_DESC1149_}; type = "bitfield_MC_ME_CADDR0" } MC_PCU_PSTAT { address = 0xfffa0040; sn = "MC_PCU_PSTAT"; access = "memorymapped"; width = 32; ${_DESC1152_}; type = "bitfield_MC_PCU_PSTAT" permission = "write/none" } MC_RGM_DES { address = 0xfffa8000; sn = "MC_RGM_DES"; access = "memorymapped"; width = 32; ${_DESC1154_}; type = "bitfield_MC_RGM_DES" } MC_RGM_DERD { address = 0xfffa8010; sn = "MC_RGM_DERD"; access = "memorymapped"; width = 32; ${_DESC1163_}; type = "bitfield_MC_RGM_DERD" } MC_RGM_DEAR { address = 0xfffa8020; sn = "MC_RGM_DEAR"; access = "memorymapped"; width = 32; ${_DESC1166_}; type = "bitfield_MC_RGM_DEAR" } MC_RGM_DBRE { address = 0xfffa8030; sn = "MC_RGM_DBRE"; access = "memorymapped"; width = 32; ${_DESC1169_}; type = "bitfield_MC_RGM_DBRE" permission = "write/none" } MC_RGM_FES { address = 0xfffa8300; sn = "MC_RGM_FES"; access = "memorymapped"; width = 32; ${_DESC1178_}; type = "bitfield_MC_RGM_FES" } MC_RGM_FERD { address = 0xfffa8310; sn = "MC_RGM_FERD"; access = "memorymapped"; width = 32; ${_DESC1192_}; type = "bitfield_MC_RGM_FERD" } MC_RGM_FEAR { address = 0xfffa8320; sn = "MC_RGM_FEAR"; access = "memorymapped"; width = 32; ${_DESC1203_}; type = "bitfield_MC_RGM_FEAR" } MC_RGM_FBRE { address = 0xfffa8330; sn = "MC_RGM_FBRE"; access = "memorymapped"; width = 32; ${_DESC1214_}; type = "bitfield_MC_RGM_FBRE" } MC_RGM_FESS { address = 0xfffa8340; sn = "MC_RGM_FESS"; access = "memorymapped"; width = 32; ${_DESC1228_}; type = "bitfield_MC_RGM_FESS" } MC_RGM_FRET { address = 0xfffa8604; sn = "MC_RGM_FRET"; access = "memorymapped"; width = 8; ${_DESC1242_}; type = "bitfield_MC_RGM_FRET" } MC_RGM_DRET { address = 0xfffa8608; sn = "MC_RGM_DRET"; access = "memorymapped"; width = 8; ${_DESC1244_}; type = "bitfield_MC_RGM_DRET" } MC_RGM_EROEC { address = 0xfffa860c; sn = "MC_RGM_EROEC"; access = "memorymapped"; width = 8; ${_DESC1246_}; type = "bitfield_MC_RGM_EROEC" } MC_RGM_PRST0 { address = 0xfffa8610; sn = "MC_RGM_PRST0"; access = "memorymapped"; width = 32; ${_DESC1249_}; type = "bitfield_MC_RGM_PRST0" } MC_RGM_PRST1 { address = 0xfffa8614; sn = "MC_RGM_PRST1"; access = "memorymapped"; width = 32; ${_DESC1251_}; type = "bitfield_MC_RGM_PRST1" } MC_RGM_PRST2 { address = 0xfffa8618; sn = "MC_RGM_PRST2"; access = "memorymapped"; width = 32; ${_DESC1252_}; type = "bitfield_MC_RGM_PRST2" } MC_RGM_PRST3 { address = 0xfffa861c; sn = "MC_RGM_PRST3"; access = "memorymapped"; width = 32; ${_DESC1253_}; type = "bitfield_MC_RGM_PRST3" } MC_RGM_PRST4 { address = 0xfffa8620; sn = "MC_RGM_PRST4"; access = "memorymapped"; width = 32; ${_DESC1254_}; type = "bitfield_MC_RGM_PRST4" } MP55_MCR { address = 0xfffe0000; sn = "MP55_MCR"; access = "memorymapped"; width = 32; ${_DESC1255_}; type = "bitfield_MP55_MCR" } MP55_MCRE { address = 0xfffe0008; sn = "MP55_MCRE"; access = "memorymapped"; width = 32; ${_DESC1269_}; type = "bitfield_MP55_MCRE" permission = "write/none" } MP55_LOCK0 { address = 0xfffe0010; sn = "MP55_LOCK0"; access = "memorymapped"; width = 32; ${_DESC1281_}; type = "bitfield_MP55_LOCK0" } MP55_LOCK1 { address = 0xfffe0014; sn = "MP55_LOCK1"; access = "memorymapped"; width = 32; ${_DESC1285_}; type = "bitfield_MP55_LOCK1" } MP55_LOCK2 { address = 0xfffe0018; sn = "MP55_LOCK2"; access = "memorymapped"; width = 32; ${_DESC1287_}; type = "bitfield_MP55_LOCK2" } MP55_SEL0 { address = 0xfffe0038; sn = "MP55_SEL0"; access = "memorymapped"; width = 32; ${_DESC1289_}; type = "bitfield_MP55_SEL0" } MP55_SEL1 { address = 0xfffe003c; sn = "MP55_SEL1"; access = "memorymapped"; width = 32; ${_DESC1292_}; type = "bitfield_MP55_SEL1" } MP55_SEL2 { address = 0xfffe0040; sn = "MP55_SEL2"; access = "memorymapped"; width = 32; ${_DESC1294_}; type = "bitfield_MP55_SEL2" } MP55_ADR { address = 0xfffe0050; sn = "MP55_ADR"; access = "memorymapped"; width = 32; ${_DESC1296_}; type = "bitfield_MP55_ADR" permission = "write/none" } MP55_UT0 { address = 0xfffe0054; sn = "MP55_UT0"; access = "memorymapped"; width = 32; ${_DESC1299_}; type = "bitfield_MP55_UT0" } MP55_UMISR0 { address = 0xfffe0058; sn = "MP55_UMISR0"; access = "memorymapped"; width = 32; ${_DESC1310_}; type = "bitfield_MP55_UMISR0" } MP55_UMISR1 { address = 0xfffe005c; sn = "MP55_UMISR1"; access = "memorymapped"; width = 32; ${_DESC1312_}; type = "bitfield_MP55_UMISR1" } MP55_UMISR2 { address = 0xfffe0060; sn = "MP55_UMISR2"; access = "memorymapped"; width = 32; ${_DESC1314_}; type = "bitfield_MP55_UMISR2" } MP55_UMISR3 { address = 0xfffe0064; sn = "MP55_UMISR3"; access = "memorymapped"; width = 32; ${_DESC1316_}; type = "bitfield_MP55_UMISR3" } MP55_UMISR8 { address = 0xfffe0078; sn = "MP55_UMISR8"; access = "memorymapped"; width = 32; ${_DESC1318_}; type = "bitfield_MP55_UMISR8" } MP55_UMISR9 { address = 0xfffe007c; sn = "MP55_UMISR9"; access = "memorymapped"; width = 32; ${_DESC1320_}; type = "bitfield_MP55_UMISR9" } MP55_OPP0 { address = 0xfffe0080; sn = "MP55_OPP0"; access = "memorymapped"; width = 32; ${_DESC1322_}; type = "bitfield_MP55_OPP0" permission = "write/none" } MP55_OPP1 { address = 0xfffe0084; sn = "MP55_OPP1"; access = "memorymapped"; width = 32; ${_DESC1325_}; type = "bitfield_MP55_OPP1" permission = "write/none" } MP55_OPP2 { address = 0xfffe0088; sn = "MP55_OPP2"; access = "memorymapped"; width = 32; ${_DESC1327_}; type = "bitfield_MP55_OPP2" permission = "write/none" } MP55_TDMPC { address = 0xfffe0090; sn = "MP55_TDMPC"; access = "memorymapped"; width = 32; ${_DESC1329_}; type = "bitfield_MP55_TDMPC" permission = "read/none" } M_CAN_1_CREL { address = 0xffee4000; sn = "M_CAN_1_CREL"; access = "memorymapped"; width = 32; ${_DESC1331_}; type = "bitfield_M_CAN_1_CREL" permission = "write/none" } M_CAN_1_ENDN { address = 0xffee4004; sn = "M_CAN_1_ENDN"; access = "memorymapped"; width = 32; ${_DESC1338_}; type = "bitfield_M_CAN_1_ENDN" permission = "write/none" } M_CAN_1_FBTP { address = 0xffee400c; sn = "M_CAN_1_FBTP"; access = "memorymapped"; width = 32; ${_DESC1340_}; type = "bitfield_M_CAN_1_FBTP" } M_CAN_1_TEST { address = 0xffee4010; sn = "M_CAN_1_TEST"; access = "memorymapped"; width = 32; ${_DESC1346_}; type = "bitfield_M_CAN_1_TEST" } M_CAN_1_RWD { address = 0xffee4014; sn = "M_CAN_1_RWD"; access = "memorymapped"; width = 32; ${_DESC1351_}; type = "bitfield_M_CAN_1_RWD" } M_CAN_1_CCCR { address = 0xffee4018; sn = "M_CAN_1_CCCR"; access = "memorymapped"; width = 32; ${_DESC1354_}; type = "bitfield_M_CAN_1_CCCR" } M_CAN_1_BTP { address = 0xffee401c; sn = "M_CAN_1_BTP"; access = "memorymapped"; width = 32; ${_DESC1363_}; type = "bitfield_M_CAN_1_BTP" } M_CAN_1_TSCC { address = 0xffee4020; sn = "M_CAN_1_TSCC"; access = "memorymapped"; width = 32; ${_DESC1368_}; type = "bitfield_M_CAN_1_TSCC" } M_CAN_1_TSCV { address = 0xffee4024; sn = "M_CAN_1_TSCV"; access = "memorymapped"; width = 32; ${_DESC1371_}; type = "bitfield_M_CAN_1_TSCV" } M_CAN_1_TOCC { address = 0xffee4028; sn = "M_CAN_1_TOCC"; access = "memorymapped"; width = 32; ${_DESC1373_}; type = "bitfield_M_CAN_1_TOCC" } M_CAN_1_TOCV { address = 0xffee402c; sn = "M_CAN_1_TOCV"; access = "memorymapped"; width = 32; ${_DESC1377_}; type = "bitfield_M_CAN_1_TOCV" } M_CAN_1_ECR { address = 0xffee4040; sn = "M_CAN_1_ECR"; access = "memorymapped"; width = 32; ${_DESC1379_}; type = "bitfield_M_CAN_1_ECR" permission = "write/none" } M_CAN_1_PSR { address = 0xffee4044; sn = "M_CAN_1_PSR"; access = "memorymapped"; width = 32; ${_DESC1384_}; type = "bitfield_M_CAN_1_PSR" permission = "write/none" } M_CAN_1_IR { address = 0xffee4050; sn = "M_CAN_1_IR"; access = "memorymapped"; width = 32; ${_DESC1393_}; type = "bitfield_M_CAN_1_IR" } M_CAN_1_IE { address = 0xffee4054; sn = "M_CAN_1_IE"; access = "memorymapped"; width = 32; ${_DESC1423_}; type = "bitfield_M_CAN_1_IE" } M_CAN_1_ILS { address = 0xffee4058; sn = "M_CAN_1_ILS"; access = "memorymapped"; width = 32; ${_DESC1454_}; type = "bitfield_M_CAN_1_ILS" } M_CAN_1_ILE { address = 0xffee405c; sn = "M_CAN_1_ILE"; access = "memorymapped"; width = 32; ${_DESC1486_}; type = "bitfield_M_CAN_1_ILE" } M_CAN_1_GFC { address = 0xffee4080; sn = "M_CAN_1_GFC"; access = "memorymapped"; width = 32; ${_DESC1489_}; type = "bitfield_M_CAN_1_GFC" } M_CAN_1_SIDFC { address = 0xffee4084; sn = "M_CAN_1_SIDFC"; access = "memorymapped"; width = 32; ${_DESC1494_}; type = "bitfield_M_CAN_1_SIDFC" } M_CAN_1_XIDFC { address = 0xffee4088; sn = "M_CAN_1_XIDFC"; access = "memorymapped"; width = 32; ${_DESC1497_}; type = "bitfield_M_CAN_1_XIDFC" } M_CAN_1_XIDAM { address = 0xffee4090; sn = "M_CAN_1_XIDAM"; access = "memorymapped"; width = 32; ${_DESC1500_}; type = "bitfield_M_CAN_1_XIDAM" } M_CAN_1_HPMS { address = 0xffee4094; sn = "M_CAN_1_HPMS"; access = "memorymapped"; width = 32; ${_DESC1502_}; type = "bitfield_M_CAN_1_HPMS" permission = "write/none" } M_CAN_1_NDAT1 { address = 0xffee4098; sn = "M_CAN_1_NDAT1"; access = "memorymapped"; width = 32; ${_DESC1507_}; type = "bitfield_M_CAN_1_NDAT1" } M_CAN_1_NDAT2 { address = 0xffee409c; sn = "M_CAN_1_NDAT2"; access = "memorymapped"; width = 32; ${_DESC1509_}; type = "bitfield_M_CAN_1_NDAT2" } M_CAN_1_RXF0C { address = 0xffee40a0; sn = "M_CAN_1_RXF0C"; access = "memorymapped"; width = 32; ${_DESC1511_}; type = "bitfield_M_CAN_1_RXF0C" } M_CAN_1_RXF0S { address = 0xffee40a4; sn = "M_CAN_1_RXF0S"; access = "memorymapped"; width = 32; ${_DESC1515_}; type = "bitfield_M_CAN_1_RXF0S" permission = "write/none" } M_CAN_1_RXF0A { address = 0xffee40a8; sn = "M_CAN_1_RXF0A"; access = "memorymapped"; width = 32; ${_DESC1520_}; type = "bitfield_M_CAN_1_RXF0A" } M_CAN_1_RXBC { address = 0xffee40ac; sn = "M_CAN_1_RXBC"; access = "memorymapped"; width = 32; ${_DESC1522_}; type = "bitfield_M_CAN_1_RXBC" } M_CAN_1_RXF1C { address = 0xffee40b0; sn = "M_CAN_1_RXF1C"; access = "memorymapped"; width = 32; ${_DESC1524_}; type = "bitfield_M_CAN_1_RXF1C" } M_CAN_1_RXF1S { address = 0xffee40b4; sn = "M_CAN_1_RXF1S"; access = "memorymapped"; width = 32; ${_DESC1528_}; type = "bitfield_M_CAN_1_RXF1S" permission = "write/none" } M_CAN_1_RXF1A { address = 0xffee40b8; sn = "M_CAN_1_RXF1A"; access = "memorymapped"; width = 32; ${_DESC1534_}; type = "bitfield_M_CAN_1_RXF1A" } M_CAN_1_TXBC { address = 0xffee40c0; sn = "M_CAN_1_TXBC"; access = "memorymapped"; width = 32; ${_DESC1536_}; type = "bitfield_M_CAN_1_TXBC" } M_CAN_1_TXFQS { address = 0xffee40c4; sn = "M_CAN_1_TXFQS"; access = "memorymapped"; width = 32; ${_DESC1541_}; type = "bitfield_M_CAN_1_TXFQS" permission = "write/none" } M_CAN_1_TXBRP { address = 0xffee40cc; sn = "M_CAN_1_TXBRP"; access = "memorymapped"; width = 32; ${_DESC1546_}; type = "bitfield_M_CAN_1_TXBRP" permission = "write/none" } M_CAN_1_TXBAR { address = 0xffee40d0; sn = "M_CAN_1_TXBAR"; access = "memorymapped"; width = 32; ${_DESC1548_}; type = "bitfield_M_CAN_1_TXBAR" } M_CAN_1_TXBCR { address = 0xffee40d4; sn = "M_CAN_1_TXBCR"; access = "memorymapped"; width = 32; ${_DESC1550_}; type = "bitfield_M_CAN_1_TXBCR" } M_CAN_1_TXBTO { address = 0xffee40d8; sn = "M_CAN_1_TXBTO"; access = "memorymapped"; width = 32; ${_DESC1552_}; type = "bitfield_M_CAN_1_TXBTO" permission = "write/none" } M_CAN_1_TXBCF { address = 0xffee40dc; sn = "M_CAN_1_TXBCF"; access = "memorymapped"; width = 32; ${_DESC1554_}; type = "bitfield_M_CAN_1_TXBCF" permission = "write/none" } M_CAN_1_TXBTIE { address = 0xffee40e0; sn = "M_CAN_1_TXBTIE"; access = "memorymapped"; width = 32; ${_DESC1556_}; type = "bitfield_M_CAN_1_TXBTIE" } M_CAN_1_TXBCIE { address = 0xffee40e4; sn = "M_CAN_1_TXBCIE"; access = "memorymapped"; width = 32; ${_DESC1558_}; type = "bitfield_M_CAN_1_TXBCIE" } M_CAN_1_TXEFC { address = 0xffee40f0; sn = "M_CAN_1_TXEFC"; access = "memorymapped"; width = 32; ${_DESC1560_}; type = "bitfield_M_CAN_1_TXEFC" } M_CAN_1_TXEFS { address = 0xffee40f4; sn = "M_CAN_1_TXEFS"; access = "memorymapped"; width = 32; ${_DESC1564_}; type = "bitfield_M_CAN_1_TXEFS" permission = "write/none" } M_CAN_1_TXEFA { address = 0xffee40f8; sn = "M_CAN_1_TXEFA"; access = "memorymapped"; width = 32; ${_DESC1570_}; type = "bitfield_M_CAN_1_TXEFA" } M_CAN_2_CREL { address = 0xffee8000; sn = "M_CAN_2_CREL"; access = "memorymapped"; width = 32; ${_DESC1331_}; type = "bitfield_M_CAN_1_CREL" permission = "write/none" } M_CAN_2_ENDN { address = 0xffee8004; sn = "M_CAN_2_ENDN"; access = "memorymapped"; width = 32; ${_DESC1338_}; type = "bitfield_M_CAN_1_ENDN" permission = "write/none" } M_CAN_2_FBTP { address = 0xffee800c; sn = "M_CAN_2_FBTP"; access = "memorymapped"; width = 32; ${_DESC1340_}; type = "bitfield_M_CAN_1_FBTP" } M_CAN_2_TEST { address = 0xffee8010; sn = "M_CAN_2_TEST"; access = "memorymapped"; width = 32; ${_DESC1346_}; type = "bitfield_M_CAN_1_TEST" } M_CAN_2_RWD { address = 0xffee8014; sn = "M_CAN_2_RWD"; access = "memorymapped"; width = 32; ${_DESC1351_}; type = "bitfield_M_CAN_1_RWD" } M_CAN_2_CCCR { address = 0xffee8018; sn = "M_CAN_2_CCCR"; access = "memorymapped"; width = 32; ${_DESC1354_}; type = "bitfield_M_CAN_1_CCCR" } M_CAN_2_BTP { address = 0xffee801c; sn = "M_CAN_2_BTP"; access = "memorymapped"; width = 32; ${_DESC1363_}; type = "bitfield_M_CAN_1_BTP" } M_CAN_2_TSCC { address = 0xffee8020; sn = "M_CAN_2_TSCC"; access = "memorymapped"; width = 32; ${_DESC1368_}; type = "bitfield_M_CAN_1_TSCC" } M_CAN_2_TSCV { address = 0xffee8024; sn = "M_CAN_2_TSCV"; access = "memorymapped"; width = 32; ${_DESC1371_}; type = "bitfield_M_CAN_1_TSCV" } M_CAN_2_TOCC { address = 0xffee8028; sn = "M_CAN_2_TOCC"; access = "memorymapped"; width = 32; ${_DESC1373_}; type = "bitfield_M_CAN_1_TOCC" } M_CAN_2_TOCV { address = 0xffee802c; sn = "M_CAN_2_TOCV"; access = "memorymapped"; width = 32; ${_DESC1377_}; type = "bitfield_M_CAN_1_TOCV" } M_CAN_2_ECR { address = 0xffee8040; sn = "M_CAN_2_ECR"; access = "memorymapped"; width = 32; ${_DESC1379_}; type = "bitfield_M_CAN_1_ECR" permission = "write/none" } M_CAN_2_PSR { address = 0xffee8044; sn = "M_CAN_2_PSR"; access = "memorymapped"; width = 32; ${_DESC1384_}; type = "bitfield_M_CAN_1_PSR" permission = "write/none" } M_CAN_2_IR { address = 0xffee8050; sn = "M_CAN_2_IR"; access = "memorymapped"; width = 32; ${_DESC1393_}; type = "bitfield_M_CAN_1_IR" } M_CAN_2_IE { address = 0xffee8054; sn = "M_CAN_2_IE"; access = "memorymapped"; width = 32; ${_DESC1423_}; type = "bitfield_M_CAN_1_IE" } M_CAN_2_ILS { address = 0xffee8058; sn = "M_CAN_2_ILS"; access = "memorymapped"; width = 32; ${_DESC1454_}; type = "bitfield_M_CAN_1_ILS" } M_CAN_2_ILE { address = 0xffee805c; sn = "M_CAN_2_ILE"; access = "memorymapped"; width = 32; ${_DESC1486_}; type = "bitfield_M_CAN_1_ILE" } M_CAN_2_GFC { address = 0xffee8080; sn = "M_CAN_2_GFC"; access = "memorymapped"; width = 32; ${_DESC1489_}; type = "bitfield_M_CAN_1_GFC" } M_CAN_2_SIDFC { address = 0xffee8084; sn = "M_CAN_2_SIDFC"; access = "memorymapped"; width = 32; ${_DESC1494_}; type = "bitfield_M_CAN_1_SIDFC" } M_CAN_2_XIDFC { address = 0xffee8088; sn = "M_CAN_2_XIDFC"; access = "memorymapped"; width = 32; ${_DESC1497_}; type = "bitfield_M_CAN_1_XIDFC" } M_CAN_2_XIDAM { address = 0xffee8090; sn = "M_CAN_2_XIDAM"; access = "memorymapped"; width = 32; ${_DESC1500_}; type = "bitfield_M_CAN_1_XIDAM" } M_CAN_2_HPMS { address = 0xffee8094; sn = "M_CAN_2_HPMS"; access = "memorymapped"; width = 32; ${_DESC1502_}; type = "bitfield_M_CAN_1_HPMS" permission = "write/none" } M_CAN_2_NDAT1 { address = 0xffee8098; sn = "M_CAN_2_NDAT1"; access = "memorymapped"; width = 32; ${_DESC1507_}; type = "bitfield_M_CAN_1_NDAT1" } M_CAN_2_NDAT2 { address = 0xffee809c; sn = "M_CAN_2_NDAT2"; access = "memorymapped"; width = 32; ${_DESC1509_}; type = "bitfield_M_CAN_1_NDAT2" } M_CAN_2_RXF0C { address = 0xffee80a0; sn = "M_CAN_2_RXF0C"; access = "memorymapped"; width = 32; ${_DESC1511_}; type = "bitfield_M_CAN_1_RXF0C" } M_CAN_2_RXF0S { address = 0xffee80a4; sn = "M_CAN_2_RXF0S"; access = "memorymapped"; width = 32; ${_DESC1515_}; type = "bitfield_M_CAN_1_RXF0S" permission = "write/none" } M_CAN_2_RXF0A { address = 0xffee80a8; sn = "M_CAN_2_RXF0A"; access = "memorymapped"; width = 32; ${_DESC1520_}; type = "bitfield_M_CAN_1_RXF0A" } M_CAN_2_RXBC { address = 0xffee80ac; sn = "M_CAN_2_RXBC"; access = "memorymapped"; width = 32; ${_DESC1522_}; type = "bitfield_M_CAN_1_RXBC" } M_CAN_2_RXF1C { address = 0xffee80b0; sn = "M_CAN_2_RXF1C"; access = "memorymapped"; width = 32; ${_DESC1524_}; type = "bitfield_M_CAN_1_RXF1C" } M_CAN_2_RXF1S { address = 0xffee80b4; sn = "M_CAN_2_RXF1S"; access = "memorymapped"; width = 32; ${_DESC1528_}; type = "bitfield_M_CAN_1_RXF1S" permission = "write/none" } M_CAN_2_RXF1A { address = 0xffee80b8; sn = "M_CAN_2_RXF1A"; access = "memorymapped"; width = 32; ${_DESC1534_}; type = "bitfield_M_CAN_1_RXF1A" } M_CAN_2_TXBC { address = 0xffee80c0; sn = "M_CAN_2_TXBC"; access = "memorymapped"; width = 32; ${_DESC1536_}; type = "bitfield_M_CAN_1_TXBC" } M_CAN_2_TXFQS { address = 0xffee80c4; sn = "M_CAN_2_TXFQS"; access = "memorymapped"; width = 32; ${_DESC1541_}; type = "bitfield_M_CAN_1_TXFQS" permission = "write/none" } M_CAN_2_TXBRP { address = 0xffee80cc; sn = "M_CAN_2_TXBRP"; access = "memorymapped"; width = 32; ${_DESC1546_}; type = "bitfield_M_CAN_1_TXBRP" permission = "write/none" } M_CAN_2_TXBAR { address = 0xffee80d0; sn = "M_CAN_2_TXBAR"; access = "memorymapped"; width = 32; ${_DESC1548_}; type = "bitfield_M_CAN_1_TXBAR" } M_CAN_2_TXBCR { address = 0xffee80d4; sn = "M_CAN_2_TXBCR"; access = "memorymapped"; width = 32; ${_DESC1550_}; type = "bitfield_M_CAN_1_TXBCR" } M_CAN_2_TXBTO { address = 0xffee80d8; sn = "M_CAN_2_TXBTO"; access = "memorymapped"; width = 32; ${_DESC1552_}; type = "bitfield_M_CAN_1_TXBTO" permission = "write/none" } M_CAN_2_TXBCF { address = 0xffee80dc; sn = "M_CAN_2_TXBCF"; access = "memorymapped"; width = 32; ${_DESC1554_}; type = "bitfield_M_CAN_1_TXBCF" permission = "write/none" } M_CAN_2_TXBTIE { address = 0xffee80e0; sn = "M_CAN_2_TXBTIE"; access = "memorymapped"; width = 32; ${_DESC1556_}; type = "bitfield_M_CAN_1_TXBTIE" } M_CAN_2_TXBCIE { address = 0xffee80e4; sn = "M_CAN_2_TXBCIE"; access = "memorymapped"; width = 32; ${_DESC1558_}; type = "bitfield_M_CAN_1_TXBCIE" } M_CAN_2_TXEFC { address = 0xffee80f0; sn = "M_CAN_2_TXEFC"; access = "memorymapped"; width = 32; ${_DESC1560_}; type = "bitfield_M_CAN_1_TXEFC" } M_CAN_2_TXEFS { address = 0xffee80f4; sn = "M_CAN_2_TXEFS"; access = "memorymapped"; width = 32; ${_DESC1564_}; type = "bitfield_M_CAN_1_TXEFS" permission = "write/none" } M_CAN_2_TXEFA { address = 0xffee80f8; sn = "M_CAN_2_TXEFA"; access = "memorymapped"; width = 32; ${_DESC1570_}; type = "bitfield_M_CAN_1_TXEFA" } PASS_LCSTAT { address = 0xffff4000; sn = "PASS_LCSTAT"; access = "memorymapped"; width = 32; ${_DESC1572_}; type = "bitfield_PASS_LCSTAT" permission = "write/none" } PASS_CHSEL { address = 0xffff4008; sn = "PASS_CHSEL"; access = "memorymapped"; width = 32; ${_DESC1576_}; type = "bitfield_PASS_CHSEL" } PASS_CSTAT { address = 0xffff4010; sn = "PASS_CSTAT"; access = "memorymapped"; width = 32; ${_DESC1578_}; type = "bitfield_PASS_CSTAT" permission = "write/none" } PASS_CIN0 { address = 0xffff4020; sn = "PASS_CIN0"; access = "memorymapped"; width = 32; ${_DESC1580_}; type = "bitfield_PASS_CIN0" permission = "read/none" } PASS_CIN1 { address = 0xffff4024; sn = "PASS_CIN1"; access = "memorymapped"; width = 32; ${_DESC1580_}; type = "bitfield_PASS_CIN0" permission = "read/none" } PASS_CIN2 { address = 0xffff4028; sn = "PASS_CIN2"; access = "memorymapped"; width = 32; ${_DESC1580_}; type = "bitfield_PASS_CIN0" permission = "read/none" } PASS_CIN3 { address = 0xffff402c; sn = "PASS_CIN3"; access = "memorymapped"; width = 32; ${_DESC1580_}; type = "bitfield_PASS_CIN0" permission = "read/none" } PASS_CIN4 { address = 0xffff4030; sn = "PASS_CIN4"; access = "memorymapped"; width = 32; ${_DESC1580_}; type = "bitfield_PASS_CIN0" permission = "read/none" } PASS_CIN5 { address = 0xffff4034; sn = "PASS_CIN5"; access = "memorymapped"; width = 32; ${_DESC1580_}; type = "bitfield_PASS_CIN0" permission = "read/none" } PASS_CIN6 { address = 0xffff4038; sn = "PASS_CIN6"; access = "memorymapped"; width = 32; ${_DESC1580_}; type = "bitfield_PASS_CIN0" permission = "read/none" } PASS_CIN7 { address = 0xffff403c; sn = "PASS_CIN7"; access = "memorymapped"; width = 32; ${_DESC1580_}; type = "bitfield_PASS_CIN0" permission = "read/none" } PASS_LOCK0_PG0 { address = 0xffff4100; sn = "PASS_LOCK0_PG0"; access = "memorymapped"; width = 32; ${_DESC1582_}; type = "bitfield_PASS_LOCK0_PG0" } PASS_LOCK1_PG0 { address = 0xffff4104; sn = "PASS_LOCK1_PG0"; access = "memorymapped"; width = 32; ${_DESC1587_}; type = "bitfield_PASS_LOCK1_PG0" } PASS_LOCK2_PG0 { address = 0xffff4108; sn = "PASS_LOCK2_PG0"; access = "memorymapped"; width = 32; ${_DESC1589_}; type = "bitfield_PASS_LOCK2_PG0" } PASS_LOCK3_PG0 { address = 0xffff410c; sn = "PASS_LOCK3_PG0"; access = "memorymapped"; width = 32; ${_DESC1591_}; type = "bitfield_PASS_LOCK3_PG0" } PASS_LOCK0_PG1 { address = 0xffff4110; sn = "PASS_LOCK0_PG1"; access = "memorymapped"; width = 32; ${_DESC1582_}; type = "bitfield_PASS_LOCK0_PG0" } PASS_LOCK1_PG1 { address = 0xffff4114; sn = "PASS_LOCK1_PG1"; access = "memorymapped"; width = 32; ${_DESC1587_}; type = "bitfield_PASS_LOCK1_PG0" } PASS_LOCK2_PG1 { address = 0xffff4118; sn = "PASS_LOCK2_PG1"; access = "memorymapped"; width = 32; ${_DESC1589_}; type = "bitfield_PASS_LOCK2_PG0" } PASS_LOCK3_PG1 { address = 0xffff411c; sn = "PASS_LOCK3_PG1"; access = "memorymapped"; width = 32; ${_DESC1591_}; type = "bitfield_PASS_LOCK3_PG0" } PASS_LOCK0_PG2 { address = 0xffff4120; sn = "PASS_LOCK0_PG2"; access = "memorymapped"; width = 32; ${_DESC1582_}; type = "bitfield_PASS_LOCK0_PG0" } PASS_LOCK1_PG2 { address = 0xffff4124; sn = "PASS_LOCK1_PG2"; access = "memorymapped"; width = 32; ${_DESC1587_}; type = "bitfield_PASS_LOCK1_PG0" } PASS_LOCK2_PG2 { address = 0xffff4128; sn = "PASS_LOCK2_PG2"; access = "memorymapped"; width = 32; ${_DESC1589_}; type = "bitfield_PASS_LOCK2_PG0" } PASS_LOCK3_PG2 { address = 0xffff412c; sn = "PASS_LOCK3_PG2"; access = "memorymapped"; width = 32; ${_DESC1591_}; type = "bitfield_PASS_LOCK3_PG0" } PASS_LOCK0_PG3 { address = 0xffff4130; sn = "PASS_LOCK0_PG3"; access = "memorymapped"; width = 32; ${_DESC1582_}; type = "bitfield_PASS_LOCK0_PG0" } PASS_LOCK1_PG3 { address = 0xffff4134; sn = "PASS_LOCK1_PG3"; access = "memorymapped"; width = 32; ${_DESC1587_}; type = "bitfield_PASS_LOCK1_PG0" } PASS_LOCK2_PG3 { address = 0xffff4138; sn = "PASS_LOCK2_PG3"; access = "memorymapped"; width = 32; ${_DESC1589_}; type = "bitfield_PASS_LOCK2_PG0" } PASS_LOCK3_PG3 { address = 0xffff413c; sn = "PASS_LOCK3_PG3"; access = "memorymapped"; width = 32; ${_DESC1591_}; type = "bitfield_PASS_LOCK3_PG0" } PBRIDGE_A_MPRA { address = 0xfc000000; sn = "PBRIDGE_A_MPRA"; access = "memorymapped"; width = 32; ${_DESC1602_}; type = "bitfield_PBRIDGE_A_MPRA" } PBRIDGE_A_PACRA { address = 0xfc000100; sn = "PBRIDGE_A_PACRA"; access = "memorymapped"; width = 32; ${_DESC1611_}; type = "bitfield_PBRIDGE_A_PACRA" } PBRIDGE_A_PACRB { address = 0xfc000104; sn = "PBRIDGE_A_PACRB"; access = "memorymapped"; width = 32; ${_DESC1611_}; type = "bitfield_PBRIDGE_A_PACRA" } PBRIDGE_A_PACRC { address = 0xfc000108; sn = "PBRIDGE_A_PACRC"; access = "memorymapped"; width = 32; ${_DESC1611_}; type = "bitfield_PBRIDGE_A_PACRA" } PBRIDGE_A_PACRD { address = 0xfc00010c; sn = "PBRIDGE_A_PACRD"; access = "memorymapped"; width = 32; ${_DESC1611_}; type = "bitfield_PBRIDGE_A_PACRA" } PBRIDGE_A_PACRF { address = 0xfc000114; sn = "PBRIDGE_A_PACRF"; access = "memorymapped"; width = 32; ${_DESC1611_}; type = "bitfield_PBRIDGE_A_PACRA" } PBRIDGE_A_PACRG { address = 0xfc000118; sn = "PBRIDGE_A_PACRG"; access = "memorymapped"; width = 32; ${_DESC1611_}; type = "bitfield_PBRIDGE_A_PACRA" } PBRIDGE_A_PACRH { address = 0xfc00011c; sn = "PBRIDGE_A_PACRH"; access = "memorymapped"; width = 32; ${_DESC1611_}; type = "bitfield_PBRIDGE_A_PACRA" } PBRIDGE_A_OPACRA { address = 0xfc000140; sn = "PBRIDGE_A_OPACRA"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRB { address = 0xfc000144; sn = "PBRIDGE_A_OPACRB"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRC { address = 0xfc000148; sn = "PBRIDGE_A_OPACRC"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRD { address = 0xfc00014c; sn = "PBRIDGE_A_OPACRD"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRE { address = 0xfc000150; sn = "PBRIDGE_A_OPACRE"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRF { address = 0xfc000154; sn = "PBRIDGE_A_OPACRF"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRG { address = 0xfc000158; sn = "PBRIDGE_A_OPACRG"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRH { address = 0xfc00015c; sn = "PBRIDGE_A_OPACRH"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRI { address = 0xfc000160; sn = "PBRIDGE_A_OPACRI"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRJ { address = 0xfc000164; sn = "PBRIDGE_A_OPACRJ"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRK { address = 0xfc000168; sn = "PBRIDGE_A_OPACRK"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRL { address = 0xfc00016c; sn = "PBRIDGE_A_OPACRL"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRM { address = 0xfc000170; sn = "PBRIDGE_A_OPACRM"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRN { address = 0xfc000174; sn = "PBRIDGE_A_OPACRN"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRO { address = 0xfc000178; sn = "PBRIDGE_A_OPACRO"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRP { address = 0xfc00017c; sn = "PBRIDGE_A_OPACRP"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRQ { address = 0xfc000180; sn = "PBRIDGE_A_OPACRQ"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRR { address = 0xfc000184; sn = "PBRIDGE_A_OPACRR"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRS { address = 0xfc000188; sn = "PBRIDGE_A_OPACRS"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRT { address = 0xfc00018c; sn = "PBRIDGE_A_OPACRT"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRU { address = 0xfc000190; sn = "PBRIDGE_A_OPACRU"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRV { address = 0xfc000194; sn = "PBRIDGE_A_OPACRV"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRW { address = 0xfc000198; sn = "PBRIDGE_A_OPACRW"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRX { address = 0xfc00019c; sn = "PBRIDGE_A_OPACRX"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRY { address = 0xfc0001a0; sn = "PBRIDGE_A_OPACRY"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRZ { address = 0xfc0001a4; sn = "PBRIDGE_A_OPACRZ"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRAA { address = 0xfc0001a8; sn = "PBRIDGE_A_OPACRAA"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRAB { address = 0xfc0001ac; sn = "PBRIDGE_A_OPACRAB"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRAC { address = 0xfc0001b0; sn = "PBRIDGE_A_OPACRAC"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRAD { address = 0xfc0001b4; sn = "PBRIDGE_A_OPACRAD"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRAE { address = 0xfc0001b8; sn = "PBRIDGE_A_OPACRAE"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PBRIDGE_A_OPACRAF { address = 0xfc0001bc; sn = "PBRIDGE_A_OPACRAF"; access = "memorymapped"; width = 32; ${_DESC1620_}; type = "bitfield_PBRIDGE_A_OPACRA" } PFLASH_PFCR1 { address = 0xfc030000; sn = "PFLASH_PFCR1"; access = "memorymapped"; width = 32; ${_DESC1621_}; type = "bitfield_PFLASH_PFCR1" } PFLASH_PFCR3 { address = 0xfc030008; sn = "PFLASH_PFCR3"; access = "memorymapped"; width = 32; ${_DESC1644_}; type = "bitfield_PFLASH_PFCR3" } PFLASH_PFAPR { address = 0xfc03000c; sn = "PFLASH_PFAPR"; access = "memorymapped"; width = 32; ${_DESC1647_}; type = "bitfield_PFLASH_PFAPR" } PFLASH_PFCRCR { address = 0xfc030010; sn = "PFLASH_PFCRCR"; access = "memorymapped"; width = 32; ${_DESC1664_}; type = "bitfield_PFLASH_PFCRCR" } PFLASH_PFCRDE { address = 0xfc030014; sn = "PFLASH_PFCRDE"; access = "memorymapped"; width = 32; ${_DESC1668_}; type = "bitfield_PFLASH_PFCRDE" } PFLASH_PFCRD0_W0 { address = 0xfc030100; sn = "PFLASH_PFCRD0_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD0_W1 { address = 0xfc030104; sn = "PFLASH_PFCRD0_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD0_W2 { address = 0xfc030108; sn = "PFLASH_PFCRD0_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD1_W0 { address = 0xfc030110; sn = "PFLASH_PFCRD1_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD1_W1 { address = 0xfc030114; sn = "PFLASH_PFCRD1_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD1_W2 { address = 0xfc030118; sn = "PFLASH_PFCRD1_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD2_W0 { address = 0xfc030120; sn = "PFLASH_PFCRD2_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD2_W1 { address = 0xfc030124; sn = "PFLASH_PFCRD2_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD2_W2 { address = 0xfc030128; sn = "PFLASH_PFCRD2_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD3_W0 { address = 0xfc030130; sn = "PFLASH_PFCRD3_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD3_W1 { address = 0xfc030134; sn = "PFLASH_PFCRD3_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD3_W2 { address = 0xfc030138; sn = "PFLASH_PFCRD3_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD4_W0 { address = 0xfc030140; sn = "PFLASH_PFCRD4_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD4_W1 { address = 0xfc030144; sn = "PFLASH_PFCRD4_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD4_W2 { address = 0xfc030148; sn = "PFLASH_PFCRD4_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD5_W0 { address = 0xfc030150; sn = "PFLASH_PFCRD5_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD5_W1 { address = 0xfc030154; sn = "PFLASH_PFCRD5_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD5_W2 { address = 0xfc030158; sn = "PFLASH_PFCRD5_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD6_W0 { address = 0xfc030160; sn = "PFLASH_PFCRD6_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD6_W1 { address = 0xfc030164; sn = "PFLASH_PFCRD6_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD6_W2 { address = 0xfc030168; sn = "PFLASH_PFCRD6_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD7_W0 { address = 0xfc030170; sn = "PFLASH_PFCRD7_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD7_W1 { address = 0xfc030174; sn = "PFLASH_PFCRD7_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD7_W2 { address = 0xfc030178; sn = "PFLASH_PFCRD7_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD8_W0 { address = 0xfc030180; sn = "PFLASH_PFCRD8_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD8_W1 { address = 0xfc030184; sn = "PFLASH_PFCRD8_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD8_W2 { address = 0xfc030188; sn = "PFLASH_PFCRD8_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD9_W0 { address = 0xfc030190; sn = "PFLASH_PFCRD9_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD9_W1 { address = 0xfc030194; sn = "PFLASH_PFCRD9_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD9_W2 { address = 0xfc030198; sn = "PFLASH_PFCRD9_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD10_W0 { address = 0xfc0301a0; sn = "PFLASH_PFCRD10_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD10_W1 { address = 0xfc0301a4; sn = "PFLASH_PFCRD10_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD10_W2 { address = 0xfc0301a8; sn = "PFLASH_PFCRD10_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD11_W0 { address = 0xfc0301b0; sn = "PFLASH_PFCRD11_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD11_W1 { address = 0xfc0301b4; sn = "PFLASH_PFCRD11_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD11_W2 { address = 0xfc0301b8; sn = "PFLASH_PFCRD11_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD12_W0 { address = 0xfc0301c0; sn = "PFLASH_PFCRD12_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD12_W1 { address = 0xfc0301c4; sn = "PFLASH_PFCRD12_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD12_W2 { address = 0xfc0301c8; sn = "PFLASH_PFCRD12_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD13_W0 { address = 0xfc0301d0; sn = "PFLASH_PFCRD13_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD13_W1 { address = 0xfc0301d4; sn = "PFLASH_PFCRD13_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD13_W2 { address = 0xfc0301d8; sn = "PFLASH_PFCRD13_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD14_W0 { address = 0xfc0301e0; sn = "PFLASH_PFCRD14_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD14_W1 { address = 0xfc0301e4; sn = "PFLASH_PFCRD14_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD14_W2 { address = 0xfc0301e8; sn = "PFLASH_PFCRD14_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD15_W0 { address = 0xfc0301f0; sn = "PFLASH_PFCRD15_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD15_W1 { address = 0xfc0301f4; sn = "PFLASH_PFCRD15_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD15_W2 { address = 0xfc0301f8; sn = "PFLASH_PFCRD15_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD16_W0 { address = 0xfc030200; sn = "PFLASH_PFCRD16_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD16_W1 { address = 0xfc030204; sn = "PFLASH_PFCRD16_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD16_W2 { address = 0xfc030208; sn = "PFLASH_PFCRD16_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD17_W0 { address = 0xfc030210; sn = "PFLASH_PFCRD17_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD17_W1 { address = 0xfc030214; sn = "PFLASH_PFCRD17_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD17_W2 { address = 0xfc030218; sn = "PFLASH_PFCRD17_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD18_W0 { address = 0xfc030220; sn = "PFLASH_PFCRD18_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD18_W1 { address = 0xfc030224; sn = "PFLASH_PFCRD18_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD18_W2 { address = 0xfc030228; sn = "PFLASH_PFCRD18_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD19_W0 { address = 0xfc030230; sn = "PFLASH_PFCRD19_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD19_W1 { address = 0xfc030234; sn = "PFLASH_PFCRD19_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD19_W2 { address = 0xfc030238; sn = "PFLASH_PFCRD19_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD20_W0 { address = 0xfc030240; sn = "PFLASH_PFCRD20_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD20_W1 { address = 0xfc030244; sn = "PFLASH_PFCRD20_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD20_W2 { address = 0xfc030248; sn = "PFLASH_PFCRD20_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD21_W0 { address = 0xfc030250; sn = "PFLASH_PFCRD21_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD21_W1 { address = 0xfc030254; sn = "PFLASH_PFCRD21_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD21_W2 { address = 0xfc030258; sn = "PFLASH_PFCRD21_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD22_W0 { address = 0xfc030260; sn = "PFLASH_PFCRD22_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD22_W1 { address = 0xfc030264; sn = "PFLASH_PFCRD22_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD22_W2 { address = 0xfc030268; sn = "PFLASH_PFCRD22_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD23_W0 { address = 0xfc030270; sn = "PFLASH_PFCRD23_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD23_W1 { address = 0xfc030274; sn = "PFLASH_PFCRD23_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD23_W2 { address = 0xfc030278; sn = "PFLASH_PFCRD23_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD24_W0 { address = 0xfc030280; sn = "PFLASH_PFCRD24_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD24_W1 { address = 0xfc030284; sn = "PFLASH_PFCRD24_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD24_W2 { address = 0xfc030288; sn = "PFLASH_PFCRD24_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD25_W0 { address = 0xfc030290; sn = "PFLASH_PFCRD25_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD25_W1 { address = 0xfc030294; sn = "PFLASH_PFCRD25_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD25_W2 { address = 0xfc030298; sn = "PFLASH_PFCRD25_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD26_W0 { address = 0xfc0302a0; sn = "PFLASH_PFCRD26_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD26_W1 { address = 0xfc0302a4; sn = "PFLASH_PFCRD26_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD26_W2 { address = 0xfc0302a8; sn = "PFLASH_PFCRD26_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD27_W0 { address = 0xfc0302b0; sn = "PFLASH_PFCRD27_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD27_W1 { address = 0xfc0302b4; sn = "PFLASH_PFCRD27_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD27_W2 { address = 0xfc0302b8; sn = "PFLASH_PFCRD27_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD28_W0 { address = 0xfc0302c0; sn = "PFLASH_PFCRD28_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD28_W1 { address = 0xfc0302c4; sn = "PFLASH_PFCRD28_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD28_W2 { address = 0xfc0302c8; sn = "PFLASH_PFCRD28_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD29_W0 { address = 0xfc0302d0; sn = "PFLASH_PFCRD29_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD29_W1 { address = 0xfc0302d4; sn = "PFLASH_PFCRD29_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD29_W2 { address = 0xfc0302d8; sn = "PFLASH_PFCRD29_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD30_W0 { address = 0xfc0302e0; sn = "PFLASH_PFCRD30_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD30_W1 { address = 0xfc0302e4; sn = "PFLASH_PFCRD30_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD30_W2 { address = 0xfc0302e8; sn = "PFLASH_PFCRD30_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PFLASH_PFCRD31_W0 { address = 0xfc0302f0; sn = "PFLASH_PFCRD31_W0"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W0" } PFLASH_PFCRD31_W1 { address = 0xfc0302f4; sn = "PFLASH_PFCRD31_W1"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W1" } PFLASH_PFCRD31_W2 { address = 0xfc0302f8; sn = "PFLASH_PFCRD31_W2"; access = "memorymapped"; width = 32; ${_DESC1701_}; type = "bitfield_PFLASH_PFCRD0_W2" } PIT_0_MCR { address = 0xfff84000; sn = "PIT_0_MCR"; access = "memorymapped"; width = 32; ${_DESC1721_}; type = "bitfield_PIT_0_MCR" } PIT_0_LTMR64H { address = 0xfff840e0; sn = "PIT_0_LTMR64H"; access = "memorymapped"; width = 32; ${_DESC1724_}; type = "bitfield_PIT_0_LTMR64H" permission = "write/none" } PIT_0_LTMR64L { address = 0xfff840e4; sn = "PIT_0_LTMR64L"; access = "memorymapped"; width = 32; ${_DESC1726_}; type = "bitfield_PIT_0_LTMR64L" permission = "write/none" } PIT_0_LDVAL0 { address = 0xfff84100; sn = "PIT_0_LDVAL0"; access = "memorymapped"; width = 32; ${_DESC1728_}; type = "bitfield_PIT_0_LDVAL0" } PIT_0_CVAL0 { address = 0xfff84104; sn = "PIT_0_CVAL0"; access = "memorymapped"; width = 32; ${_DESC1730_}; type = "bitfield_PIT_0_CVAL0" permission = "write/none" } PIT_0_TCTRL0 { address = 0xfff84108; sn = "PIT_0_TCTRL0"; access = "memorymapped"; width = 32; ${_DESC1732_}; type = "bitfield_PIT_0_TCTRL0" } PIT_0_TFLG0 { address = 0xfff8410c; sn = "PIT_0_TFLG0"; access = "memorymapped"; width = 32; ${_DESC1736_}; type = "bitfield_PIT_0_TFLG0" } PIT_0_LDVAL1 { address = 0xfff84110; sn = "PIT_0_LDVAL1"; access = "memorymapped"; width = 32; ${_DESC1728_}; type = "bitfield_PIT_0_LDVAL0" } PIT_0_CVAL1 { address = 0xfff84114; sn = "PIT_0_CVAL1"; access = "memorymapped"; width = 32; ${_DESC1730_}; type = "bitfield_PIT_0_CVAL0" permission = "write/none" } PIT_0_TCTRL1 { address = 0xfff84118; sn = "PIT_0_TCTRL1"; access = "memorymapped"; width = 32; ${_DESC1732_}; type = "bitfield_PIT_0_TCTRL0" } PIT_0_TFLG1 { address = 0xfff8411c; sn = "PIT_0_TFLG1"; access = "memorymapped"; width = 32; ${_DESC1736_}; type = "bitfield_PIT_0_TFLG0" } PIT_0_LDVAL2 { address = 0xfff84120; sn = "PIT_0_LDVAL2"; access = "memorymapped"; width = 32; ${_DESC1728_}; type = "bitfield_PIT_0_LDVAL0" } PIT_0_CVAL2 { address = 0xfff84124; sn = "PIT_0_CVAL2"; access = "memorymapped"; width = 32; ${_DESC1730_}; type = "bitfield_PIT_0_CVAL0" permission = "write/none" } PIT_0_TCTRL2 { address = 0xfff84128; sn = "PIT_0_TCTRL2"; access = "memorymapped"; width = 32; ${_DESC1732_}; type = "bitfield_PIT_0_TCTRL0" } PIT_0_TFLG2 { address = 0xfff8412c; sn = "PIT_0_TFLG2"; access = "memorymapped"; width = 32; ${_DESC1736_}; type = "bitfield_PIT_0_TFLG0" } PIT_0_LDVAL3 { address = 0xfff84130; sn = "PIT_0_LDVAL3"; access = "memorymapped"; width = 32; ${_DESC1728_}; type = "bitfield_PIT_0_LDVAL0" } PIT_0_CVAL3 { address = 0xfff84134; sn = "PIT_0_CVAL3"; access = "memorymapped"; width = 32; ${_DESC1730_}; type = "bitfield_PIT_0_CVAL0" permission = "write/none" } PIT_0_TCTRL3 { address = 0xfff84138; sn = "PIT_0_TCTRL3"; access = "memorymapped"; width = 32; ${_DESC1732_}; type = "bitfield_PIT_0_TCTRL0" } PIT_0_TFLG3 { address = 0xfff8413c; sn = "PIT_0_TFLG3"; access = "memorymapped"; width = 32; ${_DESC1736_}; type = "bitfield_PIT_0_TFLG0" } PIT_0_LDVAL4 { address = 0xfff84140; sn = "PIT_0_LDVAL4"; access = "memorymapped"; width = 32; ${_DESC1728_}; type = "bitfield_PIT_0_LDVAL0" } PIT_0_CVAL4 { address = 0xfff84144; sn = "PIT_0_CVAL4"; access = "memorymapped"; width = 32; ${_DESC1730_}; type = "bitfield_PIT_0_CVAL0" permission = "write/none" } PIT_0_TCTRL4 { address = 0xfff84148; sn = "PIT_0_TCTRL4"; access = "memorymapped"; width = 32; ${_DESC1732_}; type = "bitfield_PIT_0_TCTRL0" } PIT_0_TFLG4 { address = 0xfff8414c; sn = "PIT_0_TFLG4"; access = "memorymapped"; width = 32; ${_DESC1736_}; type = "bitfield_PIT_0_TFLG0" } PIT_0_LDVAL5 { address = 0xfff84150; sn = "PIT_0_LDVAL5"; access = "memorymapped"; width = 32; ${_DESC1728_}; type = "bitfield_PIT_0_LDVAL0" } PIT_0_CVAL5 { address = 0xfff84154; sn = "PIT_0_CVAL5"; access = "memorymapped"; width = 32; ${_DESC1730_}; type = "bitfield_PIT_0_CVAL0" permission = "write/none" } PIT_0_TCTRL5 { address = 0xfff84158; sn = "PIT_0_TCTRL5"; access = "memorymapped"; width = 32; ${_DESC1732_}; type = "bitfield_PIT_0_TCTRL0" } PIT_0_TFLG5 { address = 0xfff8415c; sn = "PIT_0_TFLG5"; access = "memorymapped"; width = 32; ${_DESC1736_}; type = "bitfield_PIT_0_TFLG0" } PIT_0_LDVAL6 { address = 0xfff84160; sn = "PIT_0_LDVAL6"; access = "memorymapped"; width = 32; ${_DESC1728_}; type = "bitfield_PIT_0_LDVAL0" } PIT_0_CVAL6 { address = 0xfff84164; sn = "PIT_0_CVAL6"; access = "memorymapped"; width = 32; ${_DESC1730_}; type = "bitfield_PIT_0_CVAL0" permission = "write/none" } PIT_0_TCTRL6 { address = 0xfff84168; sn = "PIT_0_TCTRL6"; access = "memorymapped"; width = 32; ${_DESC1732_}; type = "bitfield_PIT_0_TCTRL0" } PIT_0_TFLG6 { address = 0xfff8416c; sn = "PIT_0_TFLG6"; access = "memorymapped"; width = 32; ${_DESC1736_}; type = "bitfield_PIT_0_TFLG0" } PIT_0_LDVAL7 { address = 0xfff84170; sn = "PIT_0_LDVAL7"; access = "memorymapped"; width = 32; ${_DESC1728_}; type = "bitfield_PIT_0_LDVAL0" } PIT_0_CVAL7 { address = 0xfff84174; sn = "PIT_0_CVAL7"; access = "memorymapped"; width = 32; ${_DESC1730_}; type = "bitfield_PIT_0_CVAL0" permission = "write/none" } PIT_0_TCTRL7 { address = 0xfff84178; sn = "PIT_0_TCTRL7"; access = "memorymapped"; width = 32; ${_DESC1732_}; type = "bitfield_PIT_0_TCTRL0" } PIT_0_TFLG7 { address = 0xfff8417c; sn = "PIT_0_TFLG7"; access = "memorymapped"; width = 32; ${_DESC1736_}; type = "bitfield_PIT_0_TFLG0" } PIT_1_MCR { address = 0xfff80000; sn = "PIT_1_MCR"; access = "memorymapped"; width = 32; ${_DESC1721_}; type = "bitfield_PIT_0_MCR" } PIT_1_LTMR64H { address = 0xfff800e0; sn = "PIT_1_LTMR64H"; access = "memorymapped"; width = 32; ${_DESC1724_}; type = "bitfield_PIT_0_LTMR64H" permission = "write/none" } PIT_1_LTMR64L { address = 0xfff800e4; sn = "PIT_1_LTMR64L"; access = "memorymapped"; width = 32; ${_DESC1726_}; type = "bitfield_PIT_0_LTMR64L" permission = "write/none" } PIT_1_LDVAL0 { address = 0xfff80100; sn = "PIT_1_LDVAL0"; access = "memorymapped"; width = 32; ${_DESC1728_}; type = "bitfield_PIT_0_LDVAL0" } PIT_1_CVAL0 { address = 0xfff80104; sn = "PIT_1_CVAL0"; access = "memorymapped"; width = 32; ${_DESC1730_}; type = "bitfield_PIT_0_CVAL0" permission = "write/none" } PIT_1_TCTRL0 { address = 0xfff80108; sn = "PIT_1_TCTRL0"; access = "memorymapped"; width = 32; ${_DESC1732_}; type = "bitfield_PIT_0_TCTRL0" } PIT_1_TFLG0 { address = 0xfff8010c; sn = "PIT_1_TFLG0"; access = "memorymapped"; width = 32; ${_DESC1736_}; type = "bitfield_PIT_0_TFLG0" } PIT_1_LDVAL1 { address = 0xfff80110; sn = "PIT_1_LDVAL1"; access = "memorymapped"; width = 32; ${_DESC1728_}; type = "bitfield_PIT_0_LDVAL0" } PIT_1_CVAL1 { address = 0xfff80114; sn = "PIT_1_CVAL1"; access = "memorymapped"; width = 32; ${_DESC1730_}; type = "bitfield_PIT_0_CVAL0" permission = "write/none" } PIT_1_TCTRL1 { address = 0xfff80118; sn = "PIT_1_TCTRL1"; access = "memorymapped"; width = 32; ${_DESC1732_}; type = "bitfield_PIT_0_TCTRL0" } PIT_1_TFLG1 { address = 0xfff8011c; sn = "PIT_1_TFLG1"; access = "memorymapped"; width = 32; ${_DESC1736_}; type = "bitfield_PIT_0_TFLG0" } PIT_1_LDVAL2 { address = 0xfff80120; sn = "PIT_1_LDVAL2"; access = "memorymapped"; width = 32; ${_DESC1728_}; type = "bitfield_PIT_0_LDVAL0" } PIT_1_CVAL2 { address = 0xfff80124; sn = "PIT_1_CVAL2"; access = "memorymapped"; width = 32; ${_DESC1730_}; type = "bitfield_PIT_0_CVAL0" permission = "write/none" } PIT_1_TCTRL2 { address = 0xfff80128; sn = "PIT_1_TCTRL2"; access = "memorymapped"; width = 32; ${_DESC1732_}; type = "bitfield_PIT_0_TCTRL0" } PIT_1_TFLG2 { address = 0xfff8012c; sn = "PIT_1_TFLG2"; access = "memorymapped"; width = 32; ${_DESC1736_}; type = "bitfield_PIT_0_TFLG0" } PIT_1_LDVAL3 { address = 0xfff80130; sn = "PIT_1_LDVAL3"; access = "memorymapped"; width = 32; ${_DESC1728_}; type = "bitfield_PIT_0_LDVAL0" } PIT_1_CVAL3 { address = 0xfff80134; sn = "PIT_1_CVAL3"; access = "memorymapped"; width = 32; ${_DESC1730_}; type = "bitfield_PIT_0_CVAL0" permission = "write/none" } PIT_1_TCTRL3 { address = 0xfff80138; sn = "PIT_1_TCTRL3"; access = "memorymapped"; width = 32; ${_DESC1732_}; type = "bitfield_PIT_0_TCTRL0" } PIT_1_TFLG3 { address = 0xfff8013c; sn = "PIT_1_TFLG3"; access = "memorymapped"; width = 32; ${_DESC1736_}; type = "bitfield_PIT_0_TFLG0" } PIT_1_LDVAL4 { address = 0xfff80140; sn = "PIT_1_LDVAL4"; access = "memorymapped"; width = 32; ${_DESC1728_}; type = "bitfield_PIT_0_LDVAL0" } PIT_1_CVAL4 { address = 0xfff80144; sn = "PIT_1_CVAL4"; access = "memorymapped"; width = 32; ${_DESC1730_}; type = "bitfield_PIT_0_CVAL0" permission = "write/none" } PIT_1_TCTRL4 { address = 0xfff80148; sn = "PIT_1_TCTRL4"; access = "memorymapped"; width = 32; ${_DESC1732_}; type = "bitfield_PIT_0_TCTRL0" } PIT_1_TFLG4 { address = 0xfff8014c; sn = "PIT_1_TFLG4"; access = "memorymapped"; width = 32; ${_DESC1736_}; type = "bitfield_PIT_0_TFLG0" } PIT_1_LDVAL5 { address = 0xfff80150; sn = "PIT_1_LDVAL5"; access = "memorymapped"; width = 32; ${_DESC1728_}; type = "bitfield_PIT_0_LDVAL0" } PIT_1_CVAL5 { address = 0xfff80154; sn = "PIT_1_CVAL5"; access = "memorymapped"; width = 32; ${_DESC1730_}; type = "bitfield_PIT_0_CVAL0" permission = "write/none" } PIT_1_TCTRL5 { address = 0xfff80158; sn = "PIT_1_TCTRL5"; access = "memorymapped"; width = 32; ${_DESC1732_}; type = "bitfield_PIT_0_TCTRL0" } PIT_1_TFLG5 { address = 0xfff8015c; sn = "PIT_1_TFLG5"; access = "memorymapped"; width = 32; ${_DESC1736_}; type = "bitfield_PIT_0_TFLG0" } PIT_1_LDVAL6 { address = 0xfff80160; sn = "PIT_1_LDVAL6"; access = "memorymapped"; width = 32; ${_DESC1728_}; type = "bitfield_PIT_0_LDVAL0" } PIT_1_CVAL6 { address = 0xfff80164; sn = "PIT_1_CVAL6"; access = "memorymapped"; width = 32; ${_DESC1730_}; type = "bitfield_PIT_0_CVAL0" permission = "write/none" } PIT_1_TCTRL6 { address = 0xfff80168; sn = "PIT_1_TCTRL6"; access = "memorymapped"; width = 32; ${_DESC1732_}; type = "bitfield_PIT_0_TCTRL0" } PIT_1_TFLG6 { address = 0xfff8016c; sn = "PIT_1_TFLG6"; access = "memorymapped"; width = 32; ${_DESC1736_}; type = "bitfield_PIT_0_TFLG0" } PIT_1_LDVAL7 { address = 0xfff80170; sn = "PIT_1_LDVAL7"; access = "memorymapped"; width = 32; ${_DESC1728_}; type = "bitfield_PIT_0_LDVAL0" } PIT_1_CVAL7 { address = 0xfff80174; sn = "PIT_1_CVAL7"; access = "memorymapped"; width = 32; ${_DESC1730_}; type = "bitfield_PIT_0_CVAL0" permission = "write/none" } PIT_1_TCTRL7 { address = 0xfff80178; sn = "PIT_1_TCTRL7"; access = "memorymapped"; width = 32; ${_DESC1732_}; type = "bitfield_PIT_0_TCTRL0" } PIT_1_TFLG7 { address = 0xfff8017c; sn = "PIT_1_TFLG7"; access = "memorymapped"; width = 32; ${_DESC1736_}; type = "bitfield_PIT_0_TFLG0" } PLLDIG_PLLCR { address = 0xfffb0100; sn = "PLLDIG_PLLCR"; access = "memorymapped"; width = 32; ${_DESC1739_}; type = "bitfield_PLLDIG_PLLCR" } PLLDIG_PLLSR { address = 0xfffb0104; sn = "PLLDIG_PLLSR"; access = "memorymapped"; width = 32; ${_DESC1743_}; type = "bitfield_PLLDIG_PLLSR" } PLLDIG_PLLDV { address = 0xfffb0108; sn = "PLLDIG_PLLDV"; access = "memorymapped"; width = 32; ${_DESC1746_}; type = "bitfield_PLLDIG_PLLDV" } PMCDIG_GR_S { address = 0xfffa0400; sn = "PMCDIG_GR_S"; access = "memorymapped"; width = 32; ${_DESC1751_}; type = "bitfield_PMCDIG_GR_S" permission = "write/none" } PMCDIG_GR_P { address = 0xfffa0404; sn = "PMCDIG_GR_P"; access = "memorymapped"; width = 32; ${_DESC1757_}; type = "bitfield_PMCDIG_GR_P" permission = "write/none" } PMCDIG_IE_P { address = 0xfffa0408; sn = "PMCDIG_IE_P"; access = "memorymapped"; width = 32; ${_DESC1767_}; type = "bitfield_PMCDIG_IE_P" } PMCDIG_EPR_VD3 { address = 0xfffa0430; sn = "PMCDIG_EPR_VD3"; access = "memorymapped"; width = 32; ${_DESC1778_}; type = "bitfield_PMCDIG_EPR_VD3" } PMCDIG_REE_VD3 { address = 0xfffa0434; sn = "PMCDIG_REE_VD3"; access = "memorymapped"; width = 32; ${_DESC1780_}; type = "bitfield_PMCDIG_REE_VD3" } PMCDIG_RES_VD3 { address = 0xfffa0438; sn = "PMCDIG_RES_VD3"; access = "memorymapped"; width = 32; ${_DESC1782_}; type = "bitfield_PMCDIG_RES_VD3" } PMCDIG_EPR_VD9 { address = 0xfffa0490; sn = "PMCDIG_EPR_VD9"; access = "memorymapped"; width = 32; ${_DESC1784_}; type = "bitfield_PMCDIG_EPR_VD9" } PMCDIG_EPR_VD10 { address = 0xfffa04a0; sn = "PMCDIG_EPR_VD10"; access = "memorymapped"; width = 32; ${_DESC1786_}; type = "bitfield_PMCDIG_EPR_VD10" } PMCDIG_REE_VD10 { address = 0xfffa04a4; sn = "PMCDIG_REE_VD10"; access = "memorymapped"; width = 32; ${_DESC1791_}; type = "bitfield_PMCDIG_REE_VD10" } PMCDIG_RES_VD10 { address = 0xfffa04a8; sn = "PMCDIG_RES_VD10"; access = "memorymapped"; width = 32; ${_DESC1796_}; type = "bitfield_PMCDIG_REE_VD10" } PMCDIG_EPR_VD14 { address = 0xfffa04e0; sn = "PMCDIG_EPR_VD14"; access = "memorymapped"; width = 32; ${_DESC1797_}; type = "bitfield_PMCDIG_EPR_VD14" } PMCDIG_REE_VD14 { address = 0xfffa04e4; sn = "PMCDIG_REE_VD14"; access = "memorymapped"; width = 32; ${_DESC1800_}; type = "bitfield_PMCDIG_REE_VD14" } PMCDIG_RES_VD14 { address = 0xfffa04e8; sn = "PMCDIG_RES_VD14"; access = "memorymapped"; width = 32; ${_DESC1803_}; type = "bitfield_PMCDIG_RES_VD14" } PMCDIG_VSIO { address = 0xfffa0504; sn = "PMCDIG_VSIO"; access = "memorymapped"; width = 32; ${_DESC1806_}; type = "bitfield_PMCDIG_VSIO" } PMCDIG_MREG_CTRL { address = 0xfffa0640; sn = "PMCDIG_MREG_CTRL"; access = "memorymapped"; width = 32; ${_DESC1810_}; type = "bitfield_PMCDIG_MREG_CTRL" } PMCDIG_EPR_TD { address = 0xfffa0700; sn = "PMCDIG_EPR_TD"; access = "memorymapped"; width = 32; ${_DESC1812_}; type = "bitfield_PMCDIG_EPR_TD" } PMCDIG_REE_TD { address = 0xfffa0704; sn = "PMCDIG_REE_TD"; access = "memorymapped"; width = 32; ${_DESC1816_}; type = "bitfield_PMCDIG_REE_TD" } PMCDIG_RES_TD { address = 0xfffa0708; sn = "PMCDIG_RES_TD"; access = "memorymapped"; width = 32; ${_DESC1820_}; type = "bitfield_PMCDIG_RES_TD" } PMCDIG_CTL_TD { address = 0xfffa070c; sn = "PMCDIG_CTL_TD"; access = "memorymapped"; width = 32; ${_DESC1824_}; type = "bitfield_PMCDIG_CTL_TD" } PRAMC_PRCR1 { address = 0xfc020000; sn = "PRAMC_PRCR1"; access = "memorymapped"; width = 32; ${_DESC1832_}; type = "bitfield_PRAMC_PRCR1" } SARADC_0_MCR { address = 0xffe00000; sn = "SARADC_0_MCR"; access = "memorymapped"; width = 32; ${_DESC1835_}; type = "bitfield_SARADC_0_MCR" } SARADC_0_MSR { address = 0xffe00004; sn = "SARADC_0_MSR"; access = "memorymapped"; width = 32; ${_DESC1855_}; type = "bitfield_SARADC_0_MSR" permission = "write/none" } SARADC_0_ISR { address = 0xffe00010; sn = "SARADC_0_ISR"; access = "memorymapped"; width = 32; ${_DESC1862_}; type = "bitfield_SARADC_0_ISR" } SARADC_0_ICIPR0 { address = 0xffe00014; sn = "SARADC_0_ICIPR0"; access = "memorymapped"; width = 32; ${_DESC1868_}; type = "bitfield_SARADC_0_ICIPR0" } SARADC_0_ICIPR1 { address = 0xffe00018; sn = "SARADC_0_ICIPR1"; access = "memorymapped"; width = 32; ${_DESC1868_}; type = "bitfield_SARADC_0_ICIPR0" } SARADC_0_ICIPR2 { address = 0xffe0001c; sn = "SARADC_0_ICIPR2"; access = "memorymapped"; width = 32; ${_DESC1868_}; type = "bitfield_SARADC_0_ICIPR0" } SARADC_0_IMR { address = 0xffe00020; sn = "SARADC_0_IMR"; access = "memorymapped"; width = 32; ${_DESC1870_}; type = "bitfield_SARADC_0_IMR" } SARADC_0_ICIMR0 { address = 0xffe00024; sn = "SARADC_0_ICIMR0"; access = "memorymapped"; width = 32; ${_DESC1876_}; type = "bitfield_SARADC_0_ICIMR0" } SARADC_0_ICIMR1 { address = 0xffe00028; sn = "SARADC_0_ICIMR1"; access = "memorymapped"; width = 32; ${_DESC1876_}; type = "bitfield_SARADC_0_ICIMR0" } SARADC_0_ICIMR2 { address = 0xffe0002c; sn = "SARADC_0_ICIMR2"; access = "memorymapped"; width = 32; ${_DESC1876_}; type = "bitfield_SARADC_0_ICIMR0" } SARADC_0_WTISR { address = 0xffe00030; sn = "SARADC_0_WTISR"; access = "memorymapped"; width = 32; ${_DESC1878_}; type = "bitfield_SARADC_0_WTISR" } SARADC_0_WTIMR { address = 0xffe00034; sn = "SARADC_0_WTIMR"; access = "memorymapped"; width = 32; ${_DESC1881_}; type = "bitfield_SARADC_0_WTIMR" } SARADC_0_DMAE { address = 0xffe00040; sn = "SARADC_0_DMAE"; access = "memorymapped"; width = 32; ${_DESC1884_}; type = "bitfield_SARADC_0_DMAE" } SARADC_0_ICDSR0 { address = 0xffe00044; sn = "SARADC_0_ICDSR0"; access = "memorymapped"; width = 32; ${_DESC1887_}; type = "bitfield_SARADC_0_ICDSR0" } SARADC_0_ICDSR1 { address = 0xffe00048; sn = "SARADC_0_ICDSR1"; access = "memorymapped"; width = 32; ${_DESC1887_}; type = "bitfield_SARADC_0_ICDSR0" } SARADC_0_ICDSR2 { address = 0xffe0004c; sn = "SARADC_0_ICDSR2"; access = "memorymapped"; width = 32; ${_DESC1887_}; type = "bitfield_SARADC_0_ICDSR0" } SARADC_0_WTHRHLR0 { address = 0xffe00060; sn = "SARADC_0_WTHRHLR0"; access = "memorymapped"; width = 32; ${_DESC1889_}; type = "bitfield_SARADC_0_WTHRHLR0" } SARADC_0_WTHRHLR1 { address = 0xffe00064; sn = "SARADC_0_WTHRHLR1"; access = "memorymapped"; width = 32; ${_DESC1889_}; type = "bitfield_SARADC_0_WTHRHLR0" } SARADC_0_WTHRHLR2 { address = 0xffe00068; sn = "SARADC_0_WTHRHLR2"; access = "memorymapped"; width = 32; ${_DESC1889_}; type = "bitfield_SARADC_0_WTHRHLR0" } SARADC_0_WTHRHLR3 { address = 0xffe0006c; sn = "SARADC_0_WTHRHLR3"; access = "memorymapped"; width = 32; ${_DESC1889_}; type = "bitfield_SARADC_0_WTHRHLR0" } SARADC_0_CTR0 { address = 0xffe00094; sn = "SARADC_0_CTR0"; access = "memorymapped"; width = 32; ${_DESC1892_}; type = "bitfield_SARADC_0_CTR0" } SARADC_0_CTR1 { address = 0xffe00098; sn = "SARADC_0_CTR1"; access = "memorymapped"; width = 32; ${_DESC1892_}; type = "bitfield_SARADC_0_CTR0" } SARADC_0_CTR2 { address = 0xffe0009c; sn = "SARADC_0_CTR2"; access = "memorymapped"; width = 32; ${_DESC1892_}; type = "bitfield_SARADC_0_CTR0" } SARADC_0_CTR3 { address = 0xffe000a0; sn = "SARADC_0_CTR3"; access = "memorymapped"; width = 32; ${_DESC1892_}; type = "bitfield_SARADC_0_CTR0" } SARADC_0_ICNCMR0 { address = 0xffe000a4; sn = "SARADC_0_ICNCMR0"; access = "memorymapped"; width = 32; ${_DESC1896_}; type = "bitfield_SARADC_0_ICNCMR0" } SARADC_0_ICNCMR1 { address = 0xffe000a8; sn = "SARADC_0_ICNCMR1"; access = "memorymapped"; width = 32; ${_DESC1896_}; type = "bitfield_SARADC_0_ICNCMR0" } SARADC_0_ICNCMR2 { address = 0xffe000ac; sn = "SARADC_0_ICNCMR2"; access = "memorymapped"; width = 32; ${_DESC1896_}; type = "bitfield_SARADC_0_ICNCMR0" } SARADC_0_ICJCMR0 { address = 0xffe000b4; sn = "SARADC_0_ICJCMR0"; access = "memorymapped"; width = 32; ${_DESC1898_}; type = "bitfield_SARADC_0_ICJCMR0" } SARADC_0_ICJCMR1 { address = 0xffe000b8; sn = "SARADC_0_ICJCMR1"; access = "memorymapped"; width = 32; ${_DESC1898_}; type = "bitfield_SARADC_0_ICJCMR0" } SARADC_0_ICJCMR2 { address = 0xffe000bc; sn = "SARADC_0_ICJCMR2"; access = "memorymapped"; width = 32; ${_DESC1898_}; type = "bitfield_SARADC_0_ICJCMR0" } SARADC_0_PDEDR { address = 0xffe000c8; sn = "SARADC_0_PDEDR"; access = "memorymapped"; width = 32; ${_DESC1900_}; type = "bitfield_SARADC_0_PDEDR" } SARADC_0_ICDR0 { address = 0xffe00100; sn = "SARADC_0_ICDR0"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR1 { address = 0xffe00104; sn = "SARADC_0_ICDR1"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR2 { address = 0xffe00108; sn = "SARADC_0_ICDR2"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR3 { address = 0xffe0010c; sn = "SARADC_0_ICDR3"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR4 { address = 0xffe00110; sn = "SARADC_0_ICDR4"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR5 { address = 0xffe00114; sn = "SARADC_0_ICDR5"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR6 { address = 0xffe00118; sn = "SARADC_0_ICDR6"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR7 { address = 0xffe0011c; sn = "SARADC_0_ICDR7"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR8 { address = 0xffe00120; sn = "SARADC_0_ICDR8"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR9 { address = 0xffe00124; sn = "SARADC_0_ICDR9"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR10 { address = 0xffe00128; sn = "SARADC_0_ICDR10"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR11 { address = 0xffe0012c; sn = "SARADC_0_ICDR11"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR12 { address = 0xffe00130; sn = "SARADC_0_ICDR12"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR13 { address = 0xffe00134; sn = "SARADC_0_ICDR13"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR14 { address = 0xffe00138; sn = "SARADC_0_ICDR14"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR15 { address = 0xffe0013c; sn = "SARADC_0_ICDR15"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR16 { address = 0xffe00140; sn = "SARADC_0_ICDR16"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR17 { address = 0xffe00144; sn = "SARADC_0_ICDR17"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR18 { address = 0xffe00148; sn = "SARADC_0_ICDR18"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR19 { address = 0xffe0014c; sn = "SARADC_0_ICDR19"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR20 { address = 0xffe00150; sn = "SARADC_0_ICDR20"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR21 { address = 0xffe00154; sn = "SARADC_0_ICDR21"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR22 { address = 0xffe00158; sn = "SARADC_0_ICDR22"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR23 { address = 0xffe0015c; sn = "SARADC_0_ICDR23"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR24 { address = 0xffe00160; sn = "SARADC_0_ICDR24"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR25 { address = 0xffe00164; sn = "SARADC_0_ICDR25"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR26 { address = 0xffe00168; sn = "SARADC_0_ICDR26"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR27 { address = 0xffe0016c; sn = "SARADC_0_ICDR27"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR28 { address = 0xffe00170; sn = "SARADC_0_ICDR28"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR29 { address = 0xffe00174; sn = "SARADC_0_ICDR29"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR30 { address = 0xffe00178; sn = "SARADC_0_ICDR30"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR31 { address = 0xffe0017c; sn = "SARADC_0_ICDR31"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR32 { address = 0xffe00180; sn = "SARADC_0_ICDR32"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR33 { address = 0xffe00184; sn = "SARADC_0_ICDR33"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR34 { address = 0xffe00188; sn = "SARADC_0_ICDR34"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR35 { address = 0xffe0018c; sn = "SARADC_0_ICDR35"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR36 { address = 0xffe00190; sn = "SARADC_0_ICDR36"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR37 { address = 0xffe00194; sn = "SARADC_0_ICDR37"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR38 { address = 0xffe00198; sn = "SARADC_0_ICDR38"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR39 { address = 0xffe0019c; sn = "SARADC_0_ICDR39"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR40 { address = 0xffe001a0; sn = "SARADC_0_ICDR40"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR41 { address = 0xffe001a4; sn = "SARADC_0_ICDR41"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR42 { address = 0xffe001a8; sn = "SARADC_0_ICDR42"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR43 { address = 0xffe001ac; sn = "SARADC_0_ICDR43"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR44 { address = 0xffe001b0; sn = "SARADC_0_ICDR44"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR45 { address = 0xffe001b4; sn = "SARADC_0_ICDR45"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR46 { address = 0xffe001b8; sn = "SARADC_0_ICDR46"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR47 { address = 0xffe001bc; sn = "SARADC_0_ICDR47"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR48 { address = 0xffe001c0; sn = "SARADC_0_ICDR48"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR49 { address = 0xffe001c4; sn = "SARADC_0_ICDR49"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR50 { address = 0xffe001c8; sn = "SARADC_0_ICDR50"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR51 { address = 0xffe001cc; sn = "SARADC_0_ICDR51"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR52 { address = 0xffe001d0; sn = "SARADC_0_ICDR52"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR53 { address = 0xffe001d4; sn = "SARADC_0_ICDR53"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR54 { address = 0xffe001d8; sn = "SARADC_0_ICDR54"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR55 { address = 0xffe001dc; sn = "SARADC_0_ICDR55"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR56 { address = 0xffe001e0; sn = "SARADC_0_ICDR56"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR57 { address = 0xffe001e4; sn = "SARADC_0_ICDR57"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR58 { address = 0xffe001e8; sn = "SARADC_0_ICDR58"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR59 { address = 0xffe001ec; sn = "SARADC_0_ICDR59"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR60 { address = 0xffe001f0; sn = "SARADC_0_ICDR60"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR61 { address = 0xffe001f4; sn = "SARADC_0_ICDR61"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR62 { address = 0xffe001f8; sn = "SARADC_0_ICDR62"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR63 { address = 0xffe001fc; sn = "SARADC_0_ICDR63"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR64 { address = 0xffe00200; sn = "SARADC_0_ICDR64"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR65 { address = 0xffe00204; sn = "SARADC_0_ICDR65"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR66 { address = 0xffe00208; sn = "SARADC_0_ICDR66"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR67 { address = 0xffe0020c; sn = "SARADC_0_ICDR67"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR68 { address = 0xffe00210; sn = "SARADC_0_ICDR68"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR69 { address = 0xffe00214; sn = "SARADC_0_ICDR69"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR70 { address = 0xffe00218; sn = "SARADC_0_ICDR70"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR71 { address = 0xffe0021c; sn = "SARADC_0_ICDR71"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR72 { address = 0xffe00220; sn = "SARADC_0_ICDR72"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR73 { address = 0xffe00224; sn = "SARADC_0_ICDR73"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR74 { address = 0xffe00228; sn = "SARADC_0_ICDR74"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR75 { address = 0xffe0022c; sn = "SARADC_0_ICDR75"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR76 { address = 0xffe00230; sn = "SARADC_0_ICDR76"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR77 { address = 0xffe00234; sn = "SARADC_0_ICDR77"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR78 { address = 0xffe00238; sn = "SARADC_0_ICDR78"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR79 { address = 0xffe0023c; sn = "SARADC_0_ICDR79"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR80 { address = 0xffe00240; sn = "SARADC_0_ICDR80"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR81 { address = 0xffe00244; sn = "SARADC_0_ICDR81"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR82 { address = 0xffe00248; sn = "SARADC_0_ICDR82"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR83 { address = 0xffe0024c; sn = "SARADC_0_ICDR83"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR84 { address = 0xffe00250; sn = "SARADC_0_ICDR84"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR85 { address = 0xffe00254; sn = "SARADC_0_ICDR85"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR86 { address = 0xffe00258; sn = "SARADC_0_ICDR86"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR87 { address = 0xffe0025c; sn = "SARADC_0_ICDR87"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR88 { address = 0xffe00260; sn = "SARADC_0_ICDR88"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR89 { address = 0xffe00264; sn = "SARADC_0_ICDR89"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR90 { address = 0xffe00268; sn = "SARADC_0_ICDR90"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR91 { address = 0xffe0026c; sn = "SARADC_0_ICDR91"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR92 { address = 0xffe00270; sn = "SARADC_0_ICDR92"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR93 { address = 0xffe00274; sn = "SARADC_0_ICDR93"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR94 { address = 0xffe00278; sn = "SARADC_0_ICDR94"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICDR95 { address = 0xffe0027c; sn = "SARADC_0_ICDR95"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_0_ICWSELR0 { address = 0xffe002b0; sn = "SARADC_0_ICWSELR0"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_0_ICWSELR1 { address = 0xffe002b4; sn = "SARADC_0_ICWSELR1"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_0_ICWSELR2 { address = 0xffe002b8; sn = "SARADC_0_ICWSELR2"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_0_ICWSELR3 { address = 0xffe002bc; sn = "SARADC_0_ICWSELR3"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_0_ICWSELR4 { address = 0xffe002c0; sn = "SARADC_0_ICWSELR4"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_0_ICWSELR5 { address = 0xffe002c4; sn = "SARADC_0_ICWSELR5"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_0_ICWSELR6 { address = 0xffe002c8; sn = "SARADC_0_ICWSELR6"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_0_ICWSELR7 { address = 0xffe002cc; sn = "SARADC_0_ICWSELR7"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_0_ICWSELR8 { address = 0xffe002d0; sn = "SARADC_0_ICWSELR8"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_0_ICWSELR9 { address = 0xffe002d4; sn = "SARADC_0_ICWSELR9"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_0_ICWSELR10 { address = 0xffe002d8; sn = "SARADC_0_ICWSELR10"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_0_ICWSELR11 { address = 0xffe002dc; sn = "SARADC_0_ICWSELR11"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_0_ICWENR0 { address = 0xffe002e0; sn = "SARADC_0_ICWENR0"; access = "memorymapped"; width = 32; ${_DESC1921_}; type = "bitfield_SARADC_0_ICWENR0" } SARADC_0_ICWENR1 { address = 0xffe002e4; sn = "SARADC_0_ICWENR1"; access = "memorymapped"; width = 32; ${_DESC1921_}; type = "bitfield_SARADC_0_ICWENR0" } SARADC_0_ICWENR2 { address = 0xffe002e8; sn = "SARADC_0_ICWENR2"; access = "memorymapped"; width = 32; ${_DESC1921_}; type = "bitfield_SARADC_0_ICWENR0" } SARADC_0_ICAWORR0 { address = 0xffe002f0; sn = "SARADC_0_ICAWORR0"; access = "memorymapped"; width = 32; ${_DESC1923_}; type = "bitfield_SARADC_0_ICAWORR0" } SARADC_0_ICAWORR1 { address = 0xffe002f4; sn = "SARADC_0_ICAWORR1"; access = "memorymapped"; width = 32; ${_DESC1923_}; type = "bitfield_SARADC_0_ICAWORR0" } SARADC_0_ICAWORR2 { address = 0xffe002f8; sn = "SARADC_0_ICAWORR2"; access = "memorymapped"; width = 32; ${_DESC1923_}; type = "bitfield_SARADC_0_ICAWORR0" } SARADC_0_TCIPR { address = 0xffe00400; sn = "SARADC_0_TCIPR"; access = "memorymapped"; width = 32; ${_DESC1925_}; type = "bitfield_SARADC_0_ICIPR0" } SARADC_0_TCIMR { address = 0xffe00404; sn = "SARADC_0_TCIMR"; access = "memorymapped"; width = 32; ${_DESC1926_}; type = "bitfield_SARADC_0_ICIMR0" } SARADC_0_TCDSR { address = 0xffe00408; sn = "SARADC_0_TCDSR"; access = "memorymapped"; width = 32; ${_DESC1927_}; type = "bitfield_SARADC_0_ICDSR0" } SARADC_0_TCNCMR { address = 0xffe0040c; sn = "SARADC_0_TCNCMR"; access = "memorymapped"; width = 32; ${_DESC1928_}; type = "bitfield_SARADC_0_ICNCMR0" } SARADC_0_TCJCMR { address = 0xffe00410; sn = "SARADC_0_TCJCMR"; access = "memorymapped"; width = 32; ${_DESC1929_}; type = "bitfield_SARADC_0_TCJCMR" } SARADC_0_TCWSELR0 { address = 0xffe00414; sn = "SARADC_0_TCWSELR0"; access = "memorymapped"; width = 32; ${_DESC1930_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_0_TCWSELR1 { address = 0xffe00418; sn = "SARADC_0_TCWSELR1"; access = "memorymapped"; width = 32; ${_DESC1930_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_0_TCWSELR2 { address = 0xffe0041c; sn = "SARADC_0_TCWSELR2"; access = "memorymapped"; width = 32; ${_DESC1930_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_0_TCWSELR3 { address = 0xffe00420; sn = "SARADC_0_TCWSELR3"; access = "memorymapped"; width = 32; ${_DESC1930_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_0_TCWENR { address = 0xffe00424; sn = "SARADC_0_TCWENR"; access = "memorymapped"; width = 32; ${_DESC1939_}; type = "bitfield_SARADC_0_ICWENR0" } SARADC_0_TCAWORR { address = 0xffe00428; sn = "SARADC_0_TCAWORR"; access = "memorymapped"; width = 32; ${_DESC1940_}; type = "bitfield_SARADC_0_ICAWORR0" } SARADC_0_TCCAPR0 { address = 0xffe00430; sn = "SARADC_0_TCCAPR0"; access = "memorymapped"; width = 32; ${_DESC1941_}; type = "bitfield_SARADC_0_TCCAPR0" } SARADC_0_TCCAPR1 { address = 0xffe00434; sn = "SARADC_0_TCCAPR1"; access = "memorymapped"; width = 32; ${_DESC1941_}; type = "bitfield_SARADC_0_TCCAPR0" } SARADC_0_TCCAPR2 { address = 0xffe00438; sn = "SARADC_0_TCCAPR2"; access = "memorymapped"; width = 32; ${_DESC1941_}; type = "bitfield_SARADC_0_TCCAPR0" } SARADC_0_TCCAPR3 { address = 0xffe0043c; sn = "SARADC_0_TCCAPR3"; access = "memorymapped"; width = 32; ${_DESC1941_}; type = "bitfield_SARADC_0_TCCAPR0" } SARADC_0_TCCAPR4 { address = 0xffe00440; sn = "SARADC_0_TCCAPR4"; access = "memorymapped"; width = 32; ${_DESC1941_}; type = "bitfield_SARADC_0_TCCAPR0" } SARADC_0_TCCAPR5 { address = 0xffe00444; sn = "SARADC_0_TCCAPR5"; access = "memorymapped"; width = 32; ${_DESC1941_}; type = "bitfield_SARADC_0_TCCAPR0" } SARADC_0_TCCAPR6 { address = 0xffe00448; sn = "SARADC_0_TCCAPR6"; access = "memorymapped"; width = 32; ${_DESC1941_}; type = "bitfield_SARADC_0_TCCAPR0" } SARADC_0_TCCAPR7 { address = 0xffe0044c; sn = "SARADC_0_TCCAPR7"; access = "memorymapped"; width = 32; ${_DESC1941_}; type = "bitfield_SARADC_0_TCCAPR0" } SARADC_0_TCDR96 { address = 0xffe00450; sn = "SARADC_0_TCDR96"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR97 { address = 0xffe00454; sn = "SARADC_0_TCDR97"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR98 { address = 0xffe00458; sn = "SARADC_0_TCDR98"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR99 { address = 0xffe0045c; sn = "SARADC_0_TCDR99"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR100 { address = 0xffe00460; sn = "SARADC_0_TCDR100"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR101 { address = 0xffe00464; sn = "SARADC_0_TCDR101"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR102 { address = 0xffe00468; sn = "SARADC_0_TCDR102"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR103 { address = 0xffe0046c; sn = "SARADC_0_TCDR103"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR104 { address = 0xffe00470; sn = "SARADC_0_TCDR104"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR105 { address = 0xffe00474; sn = "SARADC_0_TCDR105"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR106 { address = 0xffe00478; sn = "SARADC_0_TCDR106"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR107 { address = 0xffe0047c; sn = "SARADC_0_TCDR107"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR108 { address = 0xffe00480; sn = "SARADC_0_TCDR108"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR109 { address = 0xffe00484; sn = "SARADC_0_TCDR109"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR110 { address = 0xffe00488; sn = "SARADC_0_TCDR110"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR111 { address = 0xffe0048c; sn = "SARADC_0_TCDR111"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR112 { address = 0xffe00490; sn = "SARADC_0_TCDR112"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR113 { address = 0xffe00494; sn = "SARADC_0_TCDR113"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR114 { address = 0xffe00498; sn = "SARADC_0_TCDR114"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR115 { address = 0xffe0049c; sn = "SARADC_0_TCDR115"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR116 { address = 0xffe004a0; sn = "SARADC_0_TCDR116"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR117 { address = 0xffe004a4; sn = "SARADC_0_TCDR117"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR118 { address = 0xffe004a8; sn = "SARADC_0_TCDR118"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR119 { address = 0xffe004ac; sn = "SARADC_0_TCDR119"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR120 { address = 0xffe004b0; sn = "SARADC_0_TCDR120"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR121 { address = 0xffe004b4; sn = "SARADC_0_TCDR121"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR122 { address = 0xffe004b8; sn = "SARADC_0_TCDR122"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR123 { address = 0xffe004bc; sn = "SARADC_0_TCDR123"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR124 { address = 0xffe004c0; sn = "SARADC_0_TCDR124"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR125 { address = 0xffe004c4; sn = "SARADC_0_TCDR125"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR126 { address = 0xffe004c8; sn = "SARADC_0_TCDR126"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_TCDR127 { address = 0xffe004cc; sn = "SARADC_0_TCDR127"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_0_ECDSDR { address = 0xffe00500; sn = "SARADC_0_ECDSDR"; access = "memorymapped"; width = 32; ${_DESC1952_}; type = "bitfield_SARADC_0_ECDSDR" } SARADC_0_ECIPR0 { address = 0xffe00510; sn = "SARADC_0_ECIPR0"; access = "memorymapped"; width = 32; ${_DESC1954_}; type = "bitfield_SARADC_0_ICIPR0" } SARADC_0_ECIPR1 { address = 0xffe00514; sn = "SARADC_0_ECIPR1"; access = "memorymapped"; width = 32; ${_DESC1954_}; type = "bitfield_SARADC_0_ICIPR0" } SARADC_0_ECIPR2 { address = 0xffe00518; sn = "SARADC_0_ECIPR2"; access = "memorymapped"; width = 32; ${_DESC1954_}; type = "bitfield_SARADC_0_ICIPR0" } SARADC_0_ECIPR3 { address = 0xffe0051c; sn = "SARADC_0_ECIPR3"; access = "memorymapped"; width = 32; ${_DESC1954_}; type = "bitfield_SARADC_0_ICIPR0" } SARADC_0_ECIMR0 { address = 0xffe00520; sn = "SARADC_0_ECIMR0"; access = "memorymapped"; width = 32; ${_DESC1955_}; type = "bitfield_SARADC_0_ICIMR0" } SARADC_0_ECIMR1 { address = 0xffe00524; sn = "SARADC_0_ECIMR1"; access = "memorymapped"; width = 32; ${_DESC1955_}; type = "bitfield_SARADC_0_ICIMR0" } SARADC_0_ECIMR2 { address = 0xffe00528; sn = "SARADC_0_ECIMR2"; access = "memorymapped"; width = 32; ${_DESC1955_}; type = "bitfield_SARADC_0_ICIMR0" } SARADC_0_ECIMR3 { address = 0xffe0052c; sn = "SARADC_0_ECIMR3"; access = "memorymapped"; width = 32; ${_DESC1955_}; type = "bitfield_SARADC_0_ICIMR0" } SARADC_0_ECDSR0 { address = 0xffe00530; sn = "SARADC_0_ECDSR0"; access = "memorymapped"; width = 32; ${_DESC1956_}; type = "bitfield_SARADC_0_ICDSR0" } SARADC_0_ECDSR1 { address = 0xffe00534; sn = "SARADC_0_ECDSR1"; access = "memorymapped"; width = 32; ${_DESC1956_}; type = "bitfield_SARADC_0_ICDSR0" } SARADC_0_ECDSR2 { address = 0xffe00538; sn = "SARADC_0_ECDSR2"; access = "memorymapped"; width = 32; ${_DESC1956_}; type = "bitfield_SARADC_0_ICDSR0" } SARADC_0_ECDSR3 { address = 0xffe0053c; sn = "SARADC_0_ECDSR3"; access = "memorymapped"; width = 32; ${_DESC1956_}; type = "bitfield_SARADC_0_ICDSR0" } SARADC_0_ECNCMR0 { address = 0xffe00540; sn = "SARADC_0_ECNCMR0"; access = "memorymapped"; width = 32; ${_DESC1957_}; type = "bitfield_SARADC_0_ICNCMR0" } SARADC_0_ECNCMR1 { address = 0xffe00544; sn = "SARADC_0_ECNCMR1"; access = "memorymapped"; width = 32; ${_DESC1957_}; type = "bitfield_SARADC_0_ICNCMR0" } SARADC_0_ECNCMR2 { address = 0xffe00548; sn = "SARADC_0_ECNCMR2"; access = "memorymapped"; width = 32; ${_DESC1957_}; type = "bitfield_SARADC_0_ICNCMR0" } SARADC_0_ECNCMR3 { address = 0xffe0054c; sn = "SARADC_0_ECNCMR3"; access = "memorymapped"; width = 32; ${_DESC1957_}; type = "bitfield_SARADC_0_ICNCMR0" } SARADC_0_ECJCMR0 { address = 0xffe00550; sn = "SARADC_0_ECJCMR0"; access = "memorymapped"; width = 32; ${_DESC1958_}; type = "bitfield_SARADC_0_TCJCMR" } SARADC_0_ECJCMR1 { address = 0xffe00554; sn = "SARADC_0_ECJCMR1"; access = "memorymapped"; width = 32; ${_DESC1958_}; type = "bitfield_SARADC_0_TCJCMR" } SARADC_0_ECJCMR2 { address = 0xffe00558; sn = "SARADC_0_ECJCMR2"; access = "memorymapped"; width = 32; ${_DESC1958_}; type = "bitfield_SARADC_0_TCJCMR" } SARADC_0_ECJCMR3 { address = 0xffe0055c; sn = "SARADC_0_ECJCMR3"; access = "memorymapped"; width = 32; ${_DESC1958_}; type = "bitfield_SARADC_0_TCJCMR" } SARADC_0_ECWSELR0 { address = 0xffe00560; sn = "SARADC_0_ECWSELR0"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_0_ECWSELR1 { address = 0xffe00564; sn = "SARADC_0_ECWSELR1"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_0_ECWSELR2 { address = 0xffe00568; sn = "SARADC_0_ECWSELR2"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_0_ECWSELR3 { address = 0xffe0056c; sn = "SARADC_0_ECWSELR3"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_0_ECWSELR4 { address = 0xffe00570; sn = "SARADC_0_ECWSELR4"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_0_ECWSELR5 { address = 0xffe00574; sn = "SARADC_0_ECWSELR5"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_0_ECWSELR6 { address = 0xffe00578; sn = "SARADC_0_ECWSELR6"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_0_ECWSELR7 { address = 0xffe0057c; sn = "SARADC_0_ECWSELR7"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_0_ECWSELR8 { address = 0xffe00580; sn = "SARADC_0_ECWSELR8"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_0_ECWSELR9 { address = 0xffe00584; sn = "SARADC_0_ECWSELR9"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_0_ECWSELR10 { address = 0xffe00588; sn = "SARADC_0_ECWSELR10"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_0_ECWSELR11 { address = 0xffe0058c; sn = "SARADC_0_ECWSELR11"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_0_ECWSELR12 { address = 0xffe00590; sn = "SARADC_0_ECWSELR12"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_0_ECWSELR13 { address = 0xffe00594; sn = "SARADC_0_ECWSELR13"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_0_ECWSELR14 { address = 0xffe00598; sn = "SARADC_0_ECWSELR14"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_0_ECWSELR15 { address = 0xffe0059c; sn = "SARADC_0_ECWSELR15"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_0_ECWENR0 { address = 0xffe005a0; sn = "SARADC_0_ECWENR0"; access = "memorymapped"; width = 32; ${_DESC1960_}; type = "bitfield_SARADC_0_ICWENR0" } SARADC_0_ECWENR1 { address = 0xffe005a4; sn = "SARADC_0_ECWENR1"; access = "memorymapped"; width = 32; ${_DESC1960_}; type = "bitfield_SARADC_0_ICWENR0" } SARADC_0_ECWENR2 { address = 0xffe005a8; sn = "SARADC_0_ECWENR2"; access = "memorymapped"; width = 32; ${_DESC1960_}; type = "bitfield_SARADC_0_ICWENR0" } SARADC_0_ECWENR3 { address = 0xffe005ac; sn = "SARADC_0_ECWENR3"; access = "memorymapped"; width = 32; ${_DESC1960_}; type = "bitfield_SARADC_0_ICWENR0" } SARADC_0_ECAWORR0 { address = 0xffe005b0; sn = "SARADC_0_ECAWORR0"; access = "memorymapped"; width = 32; ${_DESC1961_}; type = "bitfield_SARADC_0_ICAWORR0" } SARADC_0_ECAWORR1 { address = 0xffe005b4; sn = "SARADC_0_ECAWORR1"; access = "memorymapped"; width = 32; ${_DESC1961_}; type = "bitfield_SARADC_0_ICAWORR0" } SARADC_0_ECAWORR2 { address = 0xffe005b8; sn = "SARADC_0_ECAWORR2"; access = "memorymapped"; width = 32; ${_DESC1961_}; type = "bitfield_SARADC_0_ICAWORR0" } SARADC_0_ECAWORR3 { address = 0xffe005bc; sn = "SARADC_0_ECAWORR3"; access = "memorymapped"; width = 32; ${_DESC1961_}; type = "bitfield_SARADC_0_ICAWORR0" } SARADC_0_ECMICR0 { address = 0xffe005c0; sn = "SARADC_0_ECMICR0"; access = "memorymapped"; width = 32; ${_DESC1962_}; type = "bitfield_SARADC_0_ECMICR0" } SARADC_0_ECMICR1 { address = 0xffe005c4; sn = "SARADC_0_ECMICR1"; access = "memorymapped"; width = 32; ${_DESC1962_}; type = "bitfield_SARADC_0_ECMICR0" } SARADC_0_ECMICR2 { address = 0xffe005c8; sn = "SARADC_0_ECMICR2"; access = "memorymapped"; width = 32; ${_DESC1962_}; type = "bitfield_SARADC_0_ECMICR0" } SARADC_0_ECMICR3 { address = 0xffe005cc; sn = "SARADC_0_ECMICR3"; access = "memorymapped"; width = 32; ${_DESC1962_}; type = "bitfield_SARADC_0_ECMICR0" } SARADC_0_ECDR128 { address = 0xffe005d0; sn = "SARADC_0_ECDR128"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR129 { address = 0xffe005d4; sn = "SARADC_0_ECDR129"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR130 { address = 0xffe005d8; sn = "SARADC_0_ECDR130"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR131 { address = 0xffe005dc; sn = "SARADC_0_ECDR131"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR132 { address = 0xffe005e0; sn = "SARADC_0_ECDR132"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR133 { address = 0xffe005e4; sn = "SARADC_0_ECDR133"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR134 { address = 0xffe005e8; sn = "SARADC_0_ECDR134"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR135 { address = 0xffe005ec; sn = "SARADC_0_ECDR135"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR136 { address = 0xffe005f0; sn = "SARADC_0_ECDR136"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR137 { address = 0xffe005f4; sn = "SARADC_0_ECDR137"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR138 { address = 0xffe005f8; sn = "SARADC_0_ECDR138"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR139 { address = 0xffe005fc; sn = "SARADC_0_ECDR139"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR140 { address = 0xffe00600; sn = "SARADC_0_ECDR140"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR141 { address = 0xffe00604; sn = "SARADC_0_ECDR141"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR142 { address = 0xffe00608; sn = "SARADC_0_ECDR142"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR143 { address = 0xffe0060c; sn = "SARADC_0_ECDR143"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR144 { address = 0xffe00610; sn = "SARADC_0_ECDR144"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR145 { address = 0xffe00614; sn = "SARADC_0_ECDR145"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR146 { address = 0xffe00618; sn = "SARADC_0_ECDR146"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR147 { address = 0xffe0061c; sn = "SARADC_0_ECDR147"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR148 { address = 0xffe00620; sn = "SARADC_0_ECDR148"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR149 { address = 0xffe00624; sn = "SARADC_0_ECDR149"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR150 { address = 0xffe00628; sn = "SARADC_0_ECDR150"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR151 { address = 0xffe0062c; sn = "SARADC_0_ECDR151"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR152 { address = 0xffe00630; sn = "SARADC_0_ECDR152"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR153 { address = 0xffe00634; sn = "SARADC_0_ECDR153"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR154 { address = 0xffe00638; sn = "SARADC_0_ECDR154"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR155 { address = 0xffe0063c; sn = "SARADC_0_ECDR155"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR156 { address = 0xffe00640; sn = "SARADC_0_ECDR156"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR157 { address = 0xffe00644; sn = "SARADC_0_ECDR157"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR158 { address = 0xffe00648; sn = "SARADC_0_ECDR158"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR159 { address = 0xffe0064c; sn = "SARADC_0_ECDR159"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR160 { address = 0xffe00650; sn = "SARADC_0_ECDR160"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR161 { address = 0xffe00654; sn = "SARADC_0_ECDR161"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR162 { address = 0xffe00658; sn = "SARADC_0_ECDR162"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR163 { address = 0xffe0065c; sn = "SARADC_0_ECDR163"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR164 { address = 0xffe00660; sn = "SARADC_0_ECDR164"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR165 { address = 0xffe00664; sn = "SARADC_0_ECDR165"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR166 { address = 0xffe00668; sn = "SARADC_0_ECDR166"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR167 { address = 0xffe0066c; sn = "SARADC_0_ECDR167"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR168 { address = 0xffe00670; sn = "SARADC_0_ECDR168"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR169 { address = 0xffe00674; sn = "SARADC_0_ECDR169"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR170 { address = 0xffe00678; sn = "SARADC_0_ECDR170"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR171 { address = 0xffe0067c; sn = "SARADC_0_ECDR171"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR172 { address = 0xffe00680; sn = "SARADC_0_ECDR172"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR173 { address = 0xffe00684; sn = "SARADC_0_ECDR173"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR174 { address = 0xffe00688; sn = "SARADC_0_ECDR174"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR175 { address = 0xffe0068c; sn = "SARADC_0_ECDR175"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR176 { address = 0xffe00690; sn = "SARADC_0_ECDR176"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR177 { address = 0xffe00694; sn = "SARADC_0_ECDR177"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR178 { address = 0xffe00698; sn = "SARADC_0_ECDR178"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR179 { address = 0xffe0069c; sn = "SARADC_0_ECDR179"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR180 { address = 0xffe006a0; sn = "SARADC_0_ECDR180"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR181 { address = 0xffe006a4; sn = "SARADC_0_ECDR181"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR182 { address = 0xffe006a8; sn = "SARADC_0_ECDR182"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR183 { address = 0xffe006ac; sn = "SARADC_0_ECDR183"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR184 { address = 0xffe006b0; sn = "SARADC_0_ECDR184"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR185 { address = 0xffe006b4; sn = "SARADC_0_ECDR185"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR186 { address = 0xffe006b8; sn = "SARADC_0_ECDR186"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR187 { address = 0xffe006bc; sn = "SARADC_0_ECDR187"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR188 { address = 0xffe006c0; sn = "SARADC_0_ECDR188"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR189 { address = 0xffe006c4; sn = "SARADC_0_ECDR189"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR190 { address = 0xffe006c8; sn = "SARADC_0_ECDR190"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR191 { address = 0xffe006cc; sn = "SARADC_0_ECDR191"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR192 { address = 0xffe006d0; sn = "SARADC_0_ECDR192"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR193 { address = 0xffe006d4; sn = "SARADC_0_ECDR193"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR194 { address = 0xffe006d8; sn = "SARADC_0_ECDR194"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR195 { address = 0xffe006dc; sn = "SARADC_0_ECDR195"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR196 { address = 0xffe006e0; sn = "SARADC_0_ECDR196"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR197 { address = 0xffe006e4; sn = "SARADC_0_ECDR197"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR198 { address = 0xffe006e8; sn = "SARADC_0_ECDR198"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR199 { address = 0xffe006ec; sn = "SARADC_0_ECDR199"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR200 { address = 0xffe006f0; sn = "SARADC_0_ECDR200"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR201 { address = 0xffe006f4; sn = "SARADC_0_ECDR201"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR202 { address = 0xffe006f8; sn = "SARADC_0_ECDR202"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR203 { address = 0xffe006fc; sn = "SARADC_0_ECDR203"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR204 { address = 0xffe00700; sn = "SARADC_0_ECDR204"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR205 { address = 0xffe00704; sn = "SARADC_0_ECDR205"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR206 { address = 0xffe00708; sn = "SARADC_0_ECDR206"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR207 { address = 0xffe0070c; sn = "SARADC_0_ECDR207"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR208 { address = 0xffe00710; sn = "SARADC_0_ECDR208"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR209 { address = 0xffe00714; sn = "SARADC_0_ECDR209"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR210 { address = 0xffe00718; sn = "SARADC_0_ECDR210"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR211 { address = 0xffe0071c; sn = "SARADC_0_ECDR211"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR212 { address = 0xffe00720; sn = "SARADC_0_ECDR212"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR213 { address = 0xffe00724; sn = "SARADC_0_ECDR213"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR214 { address = 0xffe00728; sn = "SARADC_0_ECDR214"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR215 { address = 0xffe0072c; sn = "SARADC_0_ECDR215"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR216 { address = 0xffe00730; sn = "SARADC_0_ECDR216"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR217 { address = 0xffe00734; sn = "SARADC_0_ECDR217"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR218 { address = 0xffe00738; sn = "SARADC_0_ECDR218"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR219 { address = 0xffe0073c; sn = "SARADC_0_ECDR219"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR220 { address = 0xffe00740; sn = "SARADC_0_ECDR220"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR221 { address = 0xffe00744; sn = "SARADC_0_ECDR221"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR222 { address = 0xffe00748; sn = "SARADC_0_ECDR222"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR223 { address = 0xffe0074c; sn = "SARADC_0_ECDR223"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR224 { address = 0xffe00750; sn = "SARADC_0_ECDR224"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR225 { address = 0xffe00754; sn = "SARADC_0_ECDR225"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR226 { address = 0xffe00758; sn = "SARADC_0_ECDR226"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR227 { address = 0xffe0075c; sn = "SARADC_0_ECDR227"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR228 { address = 0xffe00760; sn = "SARADC_0_ECDR228"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR229 { address = 0xffe00764; sn = "SARADC_0_ECDR229"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR230 { address = 0xffe00768; sn = "SARADC_0_ECDR230"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR231 { address = 0xffe0076c; sn = "SARADC_0_ECDR231"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR232 { address = 0xffe00770; sn = "SARADC_0_ECDR232"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR233 { address = 0xffe00774; sn = "SARADC_0_ECDR233"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR234 { address = 0xffe00778; sn = "SARADC_0_ECDR234"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR235 { address = 0xffe0077c; sn = "SARADC_0_ECDR235"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR236 { address = 0xffe00780; sn = "SARADC_0_ECDR236"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR237 { address = 0xffe00784; sn = "SARADC_0_ECDR237"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR238 { address = 0xffe00788; sn = "SARADC_0_ECDR238"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR239 { address = 0xffe0078c; sn = "SARADC_0_ECDR239"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR240 { address = 0xffe00790; sn = "SARADC_0_ECDR240"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR241 { address = 0xffe00794; sn = "SARADC_0_ECDR241"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR242 { address = 0xffe00798; sn = "SARADC_0_ECDR242"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR243 { address = 0xffe0079c; sn = "SARADC_0_ECDR243"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR244 { address = 0xffe007a0; sn = "SARADC_0_ECDR244"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR245 { address = 0xffe007a4; sn = "SARADC_0_ECDR245"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR246 { address = 0xffe007a8; sn = "SARADC_0_ECDR246"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR247 { address = 0xffe007ac; sn = "SARADC_0_ECDR247"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR248 { address = 0xffe007b0; sn = "SARADC_0_ECDR248"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR249 { address = 0xffe007b4; sn = "SARADC_0_ECDR249"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR250 { address = 0xffe007b8; sn = "SARADC_0_ECDR250"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR251 { address = 0xffe007bc; sn = "SARADC_0_ECDR251"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR252 { address = 0xffe007c0; sn = "SARADC_0_ECDR252"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR253 { address = 0xffe007c4; sn = "SARADC_0_ECDR253"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR254 { address = 0xffe007c8; sn = "SARADC_0_ECDR254"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_0_ECDR255 { address = 0xffe007cc; sn = "SARADC_0_ECDR255"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_MCR { address = 0xffe10000; sn = "SARADC_4_MCR"; access = "memorymapped"; width = 32; ${_DESC1835_}; type = "bitfield_SARADC_0_MCR" } SARADC_4_MSR { address = 0xffe10004; sn = "SARADC_4_MSR"; access = "memorymapped"; width = 32; ${_DESC1855_}; type = "bitfield_SARADC_0_MSR" permission = "write/none" } SARADC_4_ISR { address = 0xffe10010; sn = "SARADC_4_ISR"; access = "memorymapped"; width = 32; ${_DESC1862_}; type = "bitfield_SARADC_0_ISR" } SARADC_4_ICIPR0 { address = 0xffe10014; sn = "SARADC_4_ICIPR0"; access = "memorymapped"; width = 32; ${_DESC1868_}; type = "bitfield_SARADC_0_ICIPR0" } SARADC_4_ICIPR1 { address = 0xffe10018; sn = "SARADC_4_ICIPR1"; access = "memorymapped"; width = 32; ${_DESC1868_}; type = "bitfield_SARADC_0_ICIPR0" } SARADC_4_ICIPR2 { address = 0xffe1001c; sn = "SARADC_4_ICIPR2"; access = "memorymapped"; width = 32; ${_DESC1868_}; type = "bitfield_SARADC_0_ICIPR0" } SARADC_4_IMR { address = 0xffe10020; sn = "SARADC_4_IMR"; access = "memorymapped"; width = 32; ${_DESC1870_}; type = "bitfield_SARADC_0_IMR" } SARADC_4_ICIMR0 { address = 0xffe10024; sn = "SARADC_4_ICIMR0"; access = "memorymapped"; width = 32; ${_DESC1876_}; type = "bitfield_SARADC_0_ICIMR0" } SARADC_4_ICIMR1 { address = 0xffe10028; sn = "SARADC_4_ICIMR1"; access = "memorymapped"; width = 32; ${_DESC1876_}; type = "bitfield_SARADC_0_ICIMR0" } SARADC_4_ICIMR2 { address = 0xffe1002c; sn = "SARADC_4_ICIMR2"; access = "memorymapped"; width = 32; ${_DESC1876_}; type = "bitfield_SARADC_0_ICIMR0" } SARADC_4_WTISR { address = 0xffe10030; sn = "SARADC_4_WTISR"; access = "memorymapped"; width = 32; ${_DESC1878_}; type = "bitfield_SARADC_0_WTISR" } SARADC_4_WTIMR { address = 0xffe10034; sn = "SARADC_4_WTIMR"; access = "memorymapped"; width = 32; ${_DESC1881_}; type = "bitfield_SARADC_0_WTIMR" } SARADC_4_DMAE { address = 0xffe10040; sn = "SARADC_4_DMAE"; access = "memorymapped"; width = 32; ${_DESC1884_}; type = "bitfield_SARADC_0_DMAE" } SARADC_4_ICDSR0 { address = 0xffe10044; sn = "SARADC_4_ICDSR0"; access = "memorymapped"; width = 32; ${_DESC1887_}; type = "bitfield_SARADC_0_ICDSR0" } SARADC_4_ICDSR1 { address = 0xffe10048; sn = "SARADC_4_ICDSR1"; access = "memorymapped"; width = 32; ${_DESC1887_}; type = "bitfield_SARADC_0_ICDSR0" } SARADC_4_ICDSR2 { address = 0xffe1004c; sn = "SARADC_4_ICDSR2"; access = "memorymapped"; width = 32; ${_DESC1887_}; type = "bitfield_SARADC_0_ICDSR0" } SARADC_4_WTHRHLR0 { address = 0xffe10060; sn = "SARADC_4_WTHRHLR0"; access = "memorymapped"; width = 32; ${_DESC1889_}; type = "bitfield_SARADC_0_WTHRHLR0" } SARADC_4_WTHRHLR1 { address = 0xffe10064; sn = "SARADC_4_WTHRHLR1"; access = "memorymapped"; width = 32; ${_DESC1889_}; type = "bitfield_SARADC_0_WTHRHLR0" } SARADC_4_WTHRHLR2 { address = 0xffe10068; sn = "SARADC_4_WTHRHLR2"; access = "memorymapped"; width = 32; ${_DESC1889_}; type = "bitfield_SARADC_0_WTHRHLR0" } SARADC_4_WTHRHLR3 { address = 0xffe1006c; sn = "SARADC_4_WTHRHLR3"; access = "memorymapped"; width = 32; ${_DESC1889_}; type = "bitfield_SARADC_0_WTHRHLR0" } SARADC_4_CTR0 { address = 0xffe10094; sn = "SARADC_4_CTR0"; access = "memorymapped"; width = 32; ${_DESC1892_}; type = "bitfield_SARADC_0_CTR0" } SARADC_4_CTR1 { address = 0xffe10098; sn = "SARADC_4_CTR1"; access = "memorymapped"; width = 32; ${_DESC1892_}; type = "bitfield_SARADC_0_CTR0" } SARADC_4_CTR2 { address = 0xffe1009c; sn = "SARADC_4_CTR2"; access = "memorymapped"; width = 32; ${_DESC1892_}; type = "bitfield_SARADC_0_CTR0" } SARADC_4_CTR3 { address = 0xffe100a0; sn = "SARADC_4_CTR3"; access = "memorymapped"; width = 32; ${_DESC1892_}; type = "bitfield_SARADC_0_CTR0" } SARADC_4_ICNCMR0 { address = 0xffe100a4; sn = "SARADC_4_ICNCMR0"; access = "memorymapped"; width = 32; ${_DESC1896_}; type = "bitfield_SARADC_0_ICNCMR0" } SARADC_4_ICNCMR1 { address = 0xffe100a8; sn = "SARADC_4_ICNCMR1"; access = "memorymapped"; width = 32; ${_DESC1896_}; type = "bitfield_SARADC_0_ICNCMR0" } SARADC_4_ICNCMR2 { address = 0xffe100ac; sn = "SARADC_4_ICNCMR2"; access = "memorymapped"; width = 32; ${_DESC1896_}; type = "bitfield_SARADC_0_ICNCMR0" } SARADC_4_ICJCMR0 { address = 0xffe100b4; sn = "SARADC_4_ICJCMR0"; access = "memorymapped"; width = 32; ${_DESC1898_}; type = "bitfield_SARADC_0_ICJCMR0" } SARADC_4_ICJCMR1 { address = 0xffe100b8; sn = "SARADC_4_ICJCMR1"; access = "memorymapped"; width = 32; ${_DESC1898_}; type = "bitfield_SARADC_0_ICJCMR0" } SARADC_4_ICJCMR2 { address = 0xffe100bc; sn = "SARADC_4_ICJCMR2"; access = "memorymapped"; width = 32; ${_DESC1898_}; type = "bitfield_SARADC_0_ICJCMR0" } SARADC_4_PDEDR { address = 0xffe100c8; sn = "SARADC_4_PDEDR"; access = "memorymapped"; width = 32; ${_DESC1900_}; type = "bitfield_SARADC_0_PDEDR" } SARADC_4_ICDR0 { address = 0xffe10100; sn = "SARADC_4_ICDR0"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR1 { address = 0xffe10104; sn = "SARADC_4_ICDR1"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR2 { address = 0xffe10108; sn = "SARADC_4_ICDR2"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR3 { address = 0xffe1010c; sn = "SARADC_4_ICDR3"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR4 { address = 0xffe10110; sn = "SARADC_4_ICDR4"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR5 { address = 0xffe10114; sn = "SARADC_4_ICDR5"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR6 { address = 0xffe10118; sn = "SARADC_4_ICDR6"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR7 { address = 0xffe1011c; sn = "SARADC_4_ICDR7"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR8 { address = 0xffe10120; sn = "SARADC_4_ICDR8"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR9 { address = 0xffe10124; sn = "SARADC_4_ICDR9"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR10 { address = 0xffe10128; sn = "SARADC_4_ICDR10"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR11 { address = 0xffe1012c; sn = "SARADC_4_ICDR11"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR12 { address = 0xffe10130; sn = "SARADC_4_ICDR12"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR13 { address = 0xffe10134; sn = "SARADC_4_ICDR13"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR14 { address = 0xffe10138; sn = "SARADC_4_ICDR14"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR15 { address = 0xffe1013c; sn = "SARADC_4_ICDR15"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR16 { address = 0xffe10140; sn = "SARADC_4_ICDR16"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR17 { address = 0xffe10144; sn = "SARADC_4_ICDR17"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR18 { address = 0xffe10148; sn = "SARADC_4_ICDR18"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR19 { address = 0xffe1014c; sn = "SARADC_4_ICDR19"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR20 { address = 0xffe10150; sn = "SARADC_4_ICDR20"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR21 { address = 0xffe10154; sn = "SARADC_4_ICDR21"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR22 { address = 0xffe10158; sn = "SARADC_4_ICDR22"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR23 { address = 0xffe1015c; sn = "SARADC_4_ICDR23"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR24 { address = 0xffe10160; sn = "SARADC_4_ICDR24"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR25 { address = 0xffe10164; sn = "SARADC_4_ICDR25"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR26 { address = 0xffe10168; sn = "SARADC_4_ICDR26"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR27 { address = 0xffe1016c; sn = "SARADC_4_ICDR27"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR28 { address = 0xffe10170; sn = "SARADC_4_ICDR28"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR29 { address = 0xffe10174; sn = "SARADC_4_ICDR29"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR30 { address = 0xffe10178; sn = "SARADC_4_ICDR30"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR31 { address = 0xffe1017c; sn = "SARADC_4_ICDR31"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR32 { address = 0xffe10180; sn = "SARADC_4_ICDR32"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR33 { address = 0xffe10184; sn = "SARADC_4_ICDR33"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR34 { address = 0xffe10188; sn = "SARADC_4_ICDR34"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR35 { address = 0xffe1018c; sn = "SARADC_4_ICDR35"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR36 { address = 0xffe10190; sn = "SARADC_4_ICDR36"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR37 { address = 0xffe10194; sn = "SARADC_4_ICDR37"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR38 { address = 0xffe10198; sn = "SARADC_4_ICDR38"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR39 { address = 0xffe1019c; sn = "SARADC_4_ICDR39"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR40 { address = 0xffe101a0; sn = "SARADC_4_ICDR40"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR41 { address = 0xffe101a4; sn = "SARADC_4_ICDR41"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR42 { address = 0xffe101a8; sn = "SARADC_4_ICDR42"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR43 { address = 0xffe101ac; sn = "SARADC_4_ICDR43"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR44 { address = 0xffe101b0; sn = "SARADC_4_ICDR44"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR45 { address = 0xffe101b4; sn = "SARADC_4_ICDR45"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR46 { address = 0xffe101b8; sn = "SARADC_4_ICDR46"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR47 { address = 0xffe101bc; sn = "SARADC_4_ICDR47"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR48 { address = 0xffe101c0; sn = "SARADC_4_ICDR48"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR49 { address = 0xffe101c4; sn = "SARADC_4_ICDR49"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR50 { address = 0xffe101c8; sn = "SARADC_4_ICDR50"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR51 { address = 0xffe101cc; sn = "SARADC_4_ICDR51"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR52 { address = 0xffe101d0; sn = "SARADC_4_ICDR52"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR53 { address = 0xffe101d4; sn = "SARADC_4_ICDR53"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR54 { address = 0xffe101d8; sn = "SARADC_4_ICDR54"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR55 { address = 0xffe101dc; sn = "SARADC_4_ICDR55"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR56 { address = 0xffe101e0; sn = "SARADC_4_ICDR56"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR57 { address = 0xffe101e4; sn = "SARADC_4_ICDR57"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR58 { address = 0xffe101e8; sn = "SARADC_4_ICDR58"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR59 { address = 0xffe101ec; sn = "SARADC_4_ICDR59"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR60 { address = 0xffe101f0; sn = "SARADC_4_ICDR60"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR61 { address = 0xffe101f4; sn = "SARADC_4_ICDR61"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR62 { address = 0xffe101f8; sn = "SARADC_4_ICDR62"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR63 { address = 0xffe101fc; sn = "SARADC_4_ICDR63"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR64 { address = 0xffe10200; sn = "SARADC_4_ICDR64"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR65 { address = 0xffe10204; sn = "SARADC_4_ICDR65"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR66 { address = 0xffe10208; sn = "SARADC_4_ICDR66"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR67 { address = 0xffe1020c; sn = "SARADC_4_ICDR67"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR68 { address = 0xffe10210; sn = "SARADC_4_ICDR68"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR69 { address = 0xffe10214; sn = "SARADC_4_ICDR69"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR70 { address = 0xffe10218; sn = "SARADC_4_ICDR70"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR71 { address = 0xffe1021c; sn = "SARADC_4_ICDR71"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR72 { address = 0xffe10220; sn = "SARADC_4_ICDR72"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR73 { address = 0xffe10224; sn = "SARADC_4_ICDR73"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR74 { address = 0xffe10228; sn = "SARADC_4_ICDR74"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR75 { address = 0xffe1022c; sn = "SARADC_4_ICDR75"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR76 { address = 0xffe10230; sn = "SARADC_4_ICDR76"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR77 { address = 0xffe10234; sn = "SARADC_4_ICDR77"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR78 { address = 0xffe10238; sn = "SARADC_4_ICDR78"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR79 { address = 0xffe1023c; sn = "SARADC_4_ICDR79"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR80 { address = 0xffe10240; sn = "SARADC_4_ICDR80"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR81 { address = 0xffe10244; sn = "SARADC_4_ICDR81"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR82 { address = 0xffe10248; sn = "SARADC_4_ICDR82"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR83 { address = 0xffe1024c; sn = "SARADC_4_ICDR83"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR84 { address = 0xffe10250; sn = "SARADC_4_ICDR84"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR85 { address = 0xffe10254; sn = "SARADC_4_ICDR85"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR86 { address = 0xffe10258; sn = "SARADC_4_ICDR86"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR87 { address = 0xffe1025c; sn = "SARADC_4_ICDR87"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR88 { address = 0xffe10260; sn = "SARADC_4_ICDR88"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR89 { address = 0xffe10264; sn = "SARADC_4_ICDR89"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR90 { address = 0xffe10268; sn = "SARADC_4_ICDR90"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR91 { address = 0xffe1026c; sn = "SARADC_4_ICDR91"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR92 { address = 0xffe10270; sn = "SARADC_4_ICDR92"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR93 { address = 0xffe10274; sn = "SARADC_4_ICDR93"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR94 { address = 0xffe10278; sn = "SARADC_4_ICDR94"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICDR95 { address = 0xffe1027c; sn = "SARADC_4_ICDR95"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_4_ICWSELR0 { address = 0xffe102b0; sn = "SARADC_4_ICWSELR0"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_4_ICWSELR1 { address = 0xffe102b4; sn = "SARADC_4_ICWSELR1"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_4_ICWSELR2 { address = 0xffe102b8; sn = "SARADC_4_ICWSELR2"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_4_ICWSELR3 { address = 0xffe102bc; sn = "SARADC_4_ICWSELR3"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_4_ICWSELR4 { address = 0xffe102c0; sn = "SARADC_4_ICWSELR4"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_4_ICWSELR5 { address = 0xffe102c4; sn = "SARADC_4_ICWSELR5"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_4_ICWSELR6 { address = 0xffe102c8; sn = "SARADC_4_ICWSELR6"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_4_ICWSELR7 { address = 0xffe102cc; sn = "SARADC_4_ICWSELR7"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_4_ICWSELR8 { address = 0xffe102d0; sn = "SARADC_4_ICWSELR8"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_4_ICWSELR9 { address = 0xffe102d4; sn = "SARADC_4_ICWSELR9"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_4_ICWSELR10 { address = 0xffe102d8; sn = "SARADC_4_ICWSELR10"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_4_ICWSELR11 { address = 0xffe102dc; sn = "SARADC_4_ICWSELR11"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_4_ICWENR0 { address = 0xffe102e0; sn = "SARADC_4_ICWENR0"; access = "memorymapped"; width = 32; ${_DESC1921_}; type = "bitfield_SARADC_0_ICWENR0" } SARADC_4_ICWENR1 { address = 0xffe102e4; sn = "SARADC_4_ICWENR1"; access = "memorymapped"; width = 32; ${_DESC1921_}; type = "bitfield_SARADC_0_ICWENR0" } SARADC_4_ICWENR2 { address = 0xffe102e8; sn = "SARADC_4_ICWENR2"; access = "memorymapped"; width = 32; ${_DESC1921_}; type = "bitfield_SARADC_0_ICWENR0" } SARADC_4_ICAWORR0 { address = 0xffe102f0; sn = "SARADC_4_ICAWORR0"; access = "memorymapped"; width = 32; ${_DESC1923_}; type = "bitfield_SARADC_0_ICAWORR0" } SARADC_4_ICAWORR1 { address = 0xffe102f4; sn = "SARADC_4_ICAWORR1"; access = "memorymapped"; width = 32; ${_DESC1923_}; type = "bitfield_SARADC_0_ICAWORR0" } SARADC_4_ICAWORR2 { address = 0xffe102f8; sn = "SARADC_4_ICAWORR2"; access = "memorymapped"; width = 32; ${_DESC1923_}; type = "bitfield_SARADC_0_ICAWORR0" } SARADC_4_TCIPR { address = 0xffe10400; sn = "SARADC_4_TCIPR"; access = "memorymapped"; width = 32; ${_DESC1925_}; type = "bitfield_SARADC_0_ICIPR0" } SARADC_4_TCIMR { address = 0xffe10404; sn = "SARADC_4_TCIMR"; access = "memorymapped"; width = 32; ${_DESC1926_}; type = "bitfield_SARADC_0_ICIMR0" } SARADC_4_TCDSR { address = 0xffe10408; sn = "SARADC_4_TCDSR"; access = "memorymapped"; width = 32; ${_DESC1927_}; type = "bitfield_SARADC_0_ICDSR0" } SARADC_4_TCNCMR { address = 0xffe1040c; sn = "SARADC_4_TCNCMR"; access = "memorymapped"; width = 32; ${_DESC1928_}; type = "bitfield_SARADC_0_ICNCMR0" } SARADC_4_TCJCMR { address = 0xffe10410; sn = "SARADC_4_TCJCMR"; access = "memorymapped"; width = 32; ${_DESC1929_}; type = "bitfield_SARADC_0_TCJCMR" } SARADC_4_TCWSELR0 { address = 0xffe10414; sn = "SARADC_4_TCWSELR0"; access = "memorymapped"; width = 32; ${_DESC1930_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_4_TCWSELR1 { address = 0xffe10418; sn = "SARADC_4_TCWSELR1"; access = "memorymapped"; width = 32; ${_DESC1930_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_4_TCWSELR2 { address = 0xffe1041c; sn = "SARADC_4_TCWSELR2"; access = "memorymapped"; width = 32; ${_DESC1930_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_4_TCWSELR3 { address = 0xffe10420; sn = "SARADC_4_TCWSELR3"; access = "memorymapped"; width = 32; ${_DESC1930_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_4_TCWENR { address = 0xffe10424; sn = "SARADC_4_TCWENR"; access = "memorymapped"; width = 32; ${_DESC1939_}; type = "bitfield_SARADC_0_ICWENR0" } SARADC_4_TCAWORR { address = 0xffe10428; sn = "SARADC_4_TCAWORR"; access = "memorymapped"; width = 32; ${_DESC1940_}; type = "bitfield_SARADC_0_ICAWORR0" } SARADC_4_TCCAPR0 { address = 0xffe10430; sn = "SARADC_4_TCCAPR0"; access = "memorymapped"; width = 32; ${_DESC1941_}; type = "bitfield_SARADC_0_TCCAPR0" } SARADC_4_TCCAPR1 { address = 0xffe10434; sn = "SARADC_4_TCCAPR1"; access = "memorymapped"; width = 32; ${_DESC1941_}; type = "bitfield_SARADC_0_TCCAPR0" } SARADC_4_TCCAPR2 { address = 0xffe10438; sn = "SARADC_4_TCCAPR2"; access = "memorymapped"; width = 32; ${_DESC1941_}; type = "bitfield_SARADC_0_TCCAPR0" } SARADC_4_TCCAPR3 { address = 0xffe1043c; sn = "SARADC_4_TCCAPR3"; access = "memorymapped"; width = 32; ${_DESC1941_}; type = "bitfield_SARADC_0_TCCAPR0" } SARADC_4_TCCAPR4 { address = 0xffe10440; sn = "SARADC_4_TCCAPR4"; access = "memorymapped"; width = 32; ${_DESC1941_}; type = "bitfield_SARADC_0_TCCAPR0" } SARADC_4_TCCAPR5 { address = 0xffe10444; sn = "SARADC_4_TCCAPR5"; access = "memorymapped"; width = 32; ${_DESC1941_}; type = "bitfield_SARADC_0_TCCAPR0" } SARADC_4_TCCAPR6 { address = 0xffe10448; sn = "SARADC_4_TCCAPR6"; access = "memorymapped"; width = 32; ${_DESC1941_}; type = "bitfield_SARADC_0_TCCAPR0" } SARADC_4_TCCAPR7 { address = 0xffe1044c; sn = "SARADC_4_TCCAPR7"; access = "memorymapped"; width = 32; ${_DESC1941_}; type = "bitfield_SARADC_0_TCCAPR0" } SARADC_4_TCDR96 { address = 0xffe10450; sn = "SARADC_4_TCDR96"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR97 { address = 0xffe10454; sn = "SARADC_4_TCDR97"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR98 { address = 0xffe10458; sn = "SARADC_4_TCDR98"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR99 { address = 0xffe1045c; sn = "SARADC_4_TCDR99"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR100 { address = 0xffe10460; sn = "SARADC_4_TCDR100"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR101 { address = 0xffe10464; sn = "SARADC_4_TCDR101"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR102 { address = 0xffe10468; sn = "SARADC_4_TCDR102"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR103 { address = 0xffe1046c; sn = "SARADC_4_TCDR103"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR104 { address = 0xffe10470; sn = "SARADC_4_TCDR104"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR105 { address = 0xffe10474; sn = "SARADC_4_TCDR105"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR106 { address = 0xffe10478; sn = "SARADC_4_TCDR106"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR107 { address = 0xffe1047c; sn = "SARADC_4_TCDR107"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR108 { address = 0xffe10480; sn = "SARADC_4_TCDR108"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR109 { address = 0xffe10484; sn = "SARADC_4_TCDR109"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR110 { address = 0xffe10488; sn = "SARADC_4_TCDR110"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR111 { address = 0xffe1048c; sn = "SARADC_4_TCDR111"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR112 { address = 0xffe10490; sn = "SARADC_4_TCDR112"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR113 { address = 0xffe10494; sn = "SARADC_4_TCDR113"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR114 { address = 0xffe10498; sn = "SARADC_4_TCDR114"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR115 { address = 0xffe1049c; sn = "SARADC_4_TCDR115"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR116 { address = 0xffe104a0; sn = "SARADC_4_TCDR116"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR117 { address = 0xffe104a4; sn = "SARADC_4_TCDR117"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR118 { address = 0xffe104a8; sn = "SARADC_4_TCDR118"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR119 { address = 0xffe104ac; sn = "SARADC_4_TCDR119"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR120 { address = 0xffe104b0; sn = "SARADC_4_TCDR120"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR121 { address = 0xffe104b4; sn = "SARADC_4_TCDR121"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR122 { address = 0xffe104b8; sn = "SARADC_4_TCDR122"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR123 { address = 0xffe104bc; sn = "SARADC_4_TCDR123"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR124 { address = 0xffe104c0; sn = "SARADC_4_TCDR124"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR125 { address = 0xffe104c4; sn = "SARADC_4_TCDR125"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR126 { address = 0xffe104c8; sn = "SARADC_4_TCDR126"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_TCDR127 { address = 0xffe104cc; sn = "SARADC_4_TCDR127"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_4_ECDSDR { address = 0xffe10500; sn = "SARADC_4_ECDSDR"; access = "memorymapped"; width = 32; ${_DESC1952_}; type = "bitfield_SARADC_0_ECDSDR" } SARADC_4_ECIPR0 { address = 0xffe10510; sn = "SARADC_4_ECIPR0"; access = "memorymapped"; width = 32; ${_DESC1954_}; type = "bitfield_SARADC_0_ICIPR0" } SARADC_4_ECIPR1 { address = 0xffe10514; sn = "SARADC_4_ECIPR1"; access = "memorymapped"; width = 32; ${_DESC1954_}; type = "bitfield_SARADC_0_ICIPR0" } SARADC_4_ECIPR2 { address = 0xffe10518; sn = "SARADC_4_ECIPR2"; access = "memorymapped"; width = 32; ${_DESC1954_}; type = "bitfield_SARADC_0_ICIPR0" } SARADC_4_ECIPR3 { address = 0xffe1051c; sn = "SARADC_4_ECIPR3"; access = "memorymapped"; width = 32; ${_DESC1954_}; type = "bitfield_SARADC_0_ICIPR0" } SARADC_4_ECIMR0 { address = 0xffe10520; sn = "SARADC_4_ECIMR0"; access = "memorymapped"; width = 32; ${_DESC1955_}; type = "bitfield_SARADC_0_ICIMR0" } SARADC_4_ECIMR1 { address = 0xffe10524; sn = "SARADC_4_ECIMR1"; access = "memorymapped"; width = 32; ${_DESC1955_}; type = "bitfield_SARADC_0_ICIMR0" } SARADC_4_ECIMR2 { address = 0xffe10528; sn = "SARADC_4_ECIMR2"; access = "memorymapped"; width = 32; ${_DESC1955_}; type = "bitfield_SARADC_0_ICIMR0" } SARADC_4_ECIMR3 { address = 0xffe1052c; sn = "SARADC_4_ECIMR3"; access = "memorymapped"; width = 32; ${_DESC1955_}; type = "bitfield_SARADC_0_ICIMR0" } SARADC_4_ECDSR0 { address = 0xffe10530; sn = "SARADC_4_ECDSR0"; access = "memorymapped"; width = 32; ${_DESC1956_}; type = "bitfield_SARADC_0_ICDSR0" } SARADC_4_ECDSR1 { address = 0xffe10534; sn = "SARADC_4_ECDSR1"; access = "memorymapped"; width = 32; ${_DESC1956_}; type = "bitfield_SARADC_0_ICDSR0" } SARADC_4_ECDSR2 { address = 0xffe10538; sn = "SARADC_4_ECDSR2"; access = "memorymapped"; width = 32; ${_DESC1956_}; type = "bitfield_SARADC_0_ICDSR0" } SARADC_4_ECDSR3 { address = 0xffe1053c; sn = "SARADC_4_ECDSR3"; access = "memorymapped"; width = 32; ${_DESC1956_}; type = "bitfield_SARADC_0_ICDSR0" } SARADC_4_ECNCMR0 { address = 0xffe10540; sn = "SARADC_4_ECNCMR0"; access = "memorymapped"; width = 32; ${_DESC1957_}; type = "bitfield_SARADC_0_ICNCMR0" } SARADC_4_ECNCMR1 { address = 0xffe10544; sn = "SARADC_4_ECNCMR1"; access = "memorymapped"; width = 32; ${_DESC1957_}; type = "bitfield_SARADC_0_ICNCMR0" } SARADC_4_ECNCMR2 { address = 0xffe10548; sn = "SARADC_4_ECNCMR2"; access = "memorymapped"; width = 32; ${_DESC1957_}; type = "bitfield_SARADC_0_ICNCMR0" } SARADC_4_ECNCMR3 { address = 0xffe1054c; sn = "SARADC_4_ECNCMR3"; access = "memorymapped"; width = 32; ${_DESC1957_}; type = "bitfield_SARADC_0_ICNCMR0" } SARADC_4_ECJCMR0 { address = 0xffe10550; sn = "SARADC_4_ECJCMR0"; access = "memorymapped"; width = 32; ${_DESC1958_}; type = "bitfield_SARADC_0_TCJCMR" } SARADC_4_ECJCMR1 { address = 0xffe10554; sn = "SARADC_4_ECJCMR1"; access = "memorymapped"; width = 32; ${_DESC1958_}; type = "bitfield_SARADC_0_TCJCMR" } SARADC_4_ECJCMR2 { address = 0xffe10558; sn = "SARADC_4_ECJCMR2"; access = "memorymapped"; width = 32; ${_DESC1958_}; type = "bitfield_SARADC_0_TCJCMR" } SARADC_4_ECJCMR3 { address = 0xffe1055c; sn = "SARADC_4_ECJCMR3"; access = "memorymapped"; width = 32; ${_DESC1958_}; type = "bitfield_SARADC_0_TCJCMR" } SARADC_4_ECWSELR0 { address = 0xffe10560; sn = "SARADC_4_ECWSELR0"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_4_ECWSELR1 { address = 0xffe10564; sn = "SARADC_4_ECWSELR1"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_4_ECWSELR2 { address = 0xffe10568; sn = "SARADC_4_ECWSELR2"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_4_ECWSELR3 { address = 0xffe1056c; sn = "SARADC_4_ECWSELR3"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_4_ECWSELR4 { address = 0xffe10570; sn = "SARADC_4_ECWSELR4"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_4_ECWSELR5 { address = 0xffe10574; sn = "SARADC_4_ECWSELR5"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_4_ECWSELR6 { address = 0xffe10578; sn = "SARADC_4_ECWSELR6"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_4_ECWSELR7 { address = 0xffe1057c; sn = "SARADC_4_ECWSELR7"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_4_ECWSELR8 { address = 0xffe10580; sn = "SARADC_4_ECWSELR8"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_4_ECWSELR9 { address = 0xffe10584; sn = "SARADC_4_ECWSELR9"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_4_ECWSELR10 { address = 0xffe10588; sn = "SARADC_4_ECWSELR10"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_4_ECWSELR11 { address = 0xffe1058c; sn = "SARADC_4_ECWSELR11"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_4_ECWSELR12 { address = 0xffe10590; sn = "SARADC_4_ECWSELR12"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_4_ECWSELR13 { address = 0xffe10594; sn = "SARADC_4_ECWSELR13"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_4_ECWSELR14 { address = 0xffe10598; sn = "SARADC_4_ECWSELR14"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_4_ECWSELR15 { address = 0xffe1059c; sn = "SARADC_4_ECWSELR15"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_4_ECWENR0 { address = 0xffe105a0; sn = "SARADC_4_ECWENR0"; access = "memorymapped"; width = 32; ${_DESC1960_}; type = "bitfield_SARADC_0_ICWENR0" } SARADC_4_ECWENR1 { address = 0xffe105a4; sn = "SARADC_4_ECWENR1"; access = "memorymapped"; width = 32; ${_DESC1960_}; type = "bitfield_SARADC_0_ICWENR0" } SARADC_4_ECWENR2 { address = 0xffe105a8; sn = "SARADC_4_ECWENR2"; access = "memorymapped"; width = 32; ${_DESC1960_}; type = "bitfield_SARADC_0_ICWENR0" } SARADC_4_ECWENR3 { address = 0xffe105ac; sn = "SARADC_4_ECWENR3"; access = "memorymapped"; width = 32; ${_DESC1960_}; type = "bitfield_SARADC_0_ICWENR0" } SARADC_4_ECAWORR0 { address = 0xffe105b0; sn = "SARADC_4_ECAWORR0"; access = "memorymapped"; width = 32; ${_DESC1961_}; type = "bitfield_SARADC_0_ICAWORR0" } SARADC_4_ECAWORR1 { address = 0xffe105b4; sn = "SARADC_4_ECAWORR1"; access = "memorymapped"; width = 32; ${_DESC1961_}; type = "bitfield_SARADC_0_ICAWORR0" } SARADC_4_ECAWORR2 { address = 0xffe105b8; sn = "SARADC_4_ECAWORR2"; access = "memorymapped"; width = 32; ${_DESC1961_}; type = "bitfield_SARADC_0_ICAWORR0" } SARADC_4_ECAWORR3 { address = 0xffe105bc; sn = "SARADC_4_ECAWORR3"; access = "memorymapped"; width = 32; ${_DESC1961_}; type = "bitfield_SARADC_0_ICAWORR0" } SARADC_4_ECMICR0 { address = 0xffe105c0; sn = "SARADC_4_ECMICR0"; access = "memorymapped"; width = 32; ${_DESC1962_}; type = "bitfield_SARADC_0_ECMICR0" } SARADC_4_ECMICR1 { address = 0xffe105c4; sn = "SARADC_4_ECMICR1"; access = "memorymapped"; width = 32; ${_DESC1962_}; type = "bitfield_SARADC_0_ECMICR0" } SARADC_4_ECMICR2 { address = 0xffe105c8; sn = "SARADC_4_ECMICR2"; access = "memorymapped"; width = 32; ${_DESC1962_}; type = "bitfield_SARADC_0_ECMICR0" } SARADC_4_ECMICR3 { address = 0xffe105cc; sn = "SARADC_4_ECMICR3"; access = "memorymapped"; width = 32; ${_DESC1962_}; type = "bitfield_SARADC_0_ECMICR0" } SARADC_4_ECDR128 { address = 0xffe105d0; sn = "SARADC_4_ECDR128"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR129 { address = 0xffe105d4; sn = "SARADC_4_ECDR129"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR130 { address = 0xffe105d8; sn = "SARADC_4_ECDR130"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR131 { address = 0xffe105dc; sn = "SARADC_4_ECDR131"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR132 { address = 0xffe105e0; sn = "SARADC_4_ECDR132"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR133 { address = 0xffe105e4; sn = "SARADC_4_ECDR133"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR134 { address = 0xffe105e8; sn = "SARADC_4_ECDR134"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR135 { address = 0xffe105ec; sn = "SARADC_4_ECDR135"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR136 { address = 0xffe105f0; sn = "SARADC_4_ECDR136"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR137 { address = 0xffe105f4; sn = "SARADC_4_ECDR137"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR138 { address = 0xffe105f8; sn = "SARADC_4_ECDR138"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR139 { address = 0xffe105fc; sn = "SARADC_4_ECDR139"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR140 { address = 0xffe10600; sn = "SARADC_4_ECDR140"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR141 { address = 0xffe10604; sn = "SARADC_4_ECDR141"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR142 { address = 0xffe10608; sn = "SARADC_4_ECDR142"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR143 { address = 0xffe1060c; sn = "SARADC_4_ECDR143"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR144 { address = 0xffe10610; sn = "SARADC_4_ECDR144"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR145 { address = 0xffe10614; sn = "SARADC_4_ECDR145"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR146 { address = 0xffe10618; sn = "SARADC_4_ECDR146"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR147 { address = 0xffe1061c; sn = "SARADC_4_ECDR147"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR148 { address = 0xffe10620; sn = "SARADC_4_ECDR148"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR149 { address = 0xffe10624; sn = "SARADC_4_ECDR149"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR150 { address = 0xffe10628; sn = "SARADC_4_ECDR150"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR151 { address = 0xffe1062c; sn = "SARADC_4_ECDR151"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR152 { address = 0xffe10630; sn = "SARADC_4_ECDR152"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR153 { address = 0xffe10634; sn = "SARADC_4_ECDR153"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR154 { address = 0xffe10638; sn = "SARADC_4_ECDR154"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR155 { address = 0xffe1063c; sn = "SARADC_4_ECDR155"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR156 { address = 0xffe10640; sn = "SARADC_4_ECDR156"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR157 { address = 0xffe10644; sn = "SARADC_4_ECDR157"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR158 { address = 0xffe10648; sn = "SARADC_4_ECDR158"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR159 { address = 0xffe1064c; sn = "SARADC_4_ECDR159"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR160 { address = 0xffe10650; sn = "SARADC_4_ECDR160"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR161 { address = 0xffe10654; sn = "SARADC_4_ECDR161"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR162 { address = 0xffe10658; sn = "SARADC_4_ECDR162"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR163 { address = 0xffe1065c; sn = "SARADC_4_ECDR163"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR164 { address = 0xffe10660; sn = "SARADC_4_ECDR164"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR165 { address = 0xffe10664; sn = "SARADC_4_ECDR165"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR166 { address = 0xffe10668; sn = "SARADC_4_ECDR166"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR167 { address = 0xffe1066c; sn = "SARADC_4_ECDR167"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR168 { address = 0xffe10670; sn = "SARADC_4_ECDR168"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR169 { address = 0xffe10674; sn = "SARADC_4_ECDR169"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR170 { address = 0xffe10678; sn = "SARADC_4_ECDR170"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR171 { address = 0xffe1067c; sn = "SARADC_4_ECDR171"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR172 { address = 0xffe10680; sn = "SARADC_4_ECDR172"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR173 { address = 0xffe10684; sn = "SARADC_4_ECDR173"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR174 { address = 0xffe10688; sn = "SARADC_4_ECDR174"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR175 { address = 0xffe1068c; sn = "SARADC_4_ECDR175"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR176 { address = 0xffe10690; sn = "SARADC_4_ECDR176"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR177 { address = 0xffe10694; sn = "SARADC_4_ECDR177"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR178 { address = 0xffe10698; sn = "SARADC_4_ECDR178"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR179 { address = 0xffe1069c; sn = "SARADC_4_ECDR179"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR180 { address = 0xffe106a0; sn = "SARADC_4_ECDR180"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR181 { address = 0xffe106a4; sn = "SARADC_4_ECDR181"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR182 { address = 0xffe106a8; sn = "SARADC_4_ECDR182"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR183 { address = 0xffe106ac; sn = "SARADC_4_ECDR183"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR184 { address = 0xffe106b0; sn = "SARADC_4_ECDR184"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR185 { address = 0xffe106b4; sn = "SARADC_4_ECDR185"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR186 { address = 0xffe106b8; sn = "SARADC_4_ECDR186"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR187 { address = 0xffe106bc; sn = "SARADC_4_ECDR187"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR188 { address = 0xffe106c0; sn = "SARADC_4_ECDR188"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR189 { address = 0xffe106c4; sn = "SARADC_4_ECDR189"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR190 { address = 0xffe106c8; sn = "SARADC_4_ECDR190"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR191 { address = 0xffe106cc; sn = "SARADC_4_ECDR191"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR192 { address = 0xffe106d0; sn = "SARADC_4_ECDR192"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR193 { address = 0xffe106d4; sn = "SARADC_4_ECDR193"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR194 { address = 0xffe106d8; sn = "SARADC_4_ECDR194"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR195 { address = 0xffe106dc; sn = "SARADC_4_ECDR195"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR196 { address = 0xffe106e0; sn = "SARADC_4_ECDR196"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR197 { address = 0xffe106e4; sn = "SARADC_4_ECDR197"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR198 { address = 0xffe106e8; sn = "SARADC_4_ECDR198"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR199 { address = 0xffe106ec; sn = "SARADC_4_ECDR199"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR200 { address = 0xffe106f0; sn = "SARADC_4_ECDR200"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR201 { address = 0xffe106f4; sn = "SARADC_4_ECDR201"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR202 { address = 0xffe106f8; sn = "SARADC_4_ECDR202"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR203 { address = 0xffe106fc; sn = "SARADC_4_ECDR203"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR204 { address = 0xffe10700; sn = "SARADC_4_ECDR204"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR205 { address = 0xffe10704; sn = "SARADC_4_ECDR205"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR206 { address = 0xffe10708; sn = "SARADC_4_ECDR206"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR207 { address = 0xffe1070c; sn = "SARADC_4_ECDR207"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR208 { address = 0xffe10710; sn = "SARADC_4_ECDR208"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR209 { address = 0xffe10714; sn = "SARADC_4_ECDR209"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR210 { address = 0xffe10718; sn = "SARADC_4_ECDR210"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR211 { address = 0xffe1071c; sn = "SARADC_4_ECDR211"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR212 { address = 0xffe10720; sn = "SARADC_4_ECDR212"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR213 { address = 0xffe10724; sn = "SARADC_4_ECDR213"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR214 { address = 0xffe10728; sn = "SARADC_4_ECDR214"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR215 { address = 0xffe1072c; sn = "SARADC_4_ECDR215"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR216 { address = 0xffe10730; sn = "SARADC_4_ECDR216"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR217 { address = 0xffe10734; sn = "SARADC_4_ECDR217"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR218 { address = 0xffe10738; sn = "SARADC_4_ECDR218"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR219 { address = 0xffe1073c; sn = "SARADC_4_ECDR219"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR220 { address = 0xffe10740; sn = "SARADC_4_ECDR220"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR221 { address = 0xffe10744; sn = "SARADC_4_ECDR221"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR222 { address = 0xffe10748; sn = "SARADC_4_ECDR222"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR223 { address = 0xffe1074c; sn = "SARADC_4_ECDR223"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR224 { address = 0xffe10750; sn = "SARADC_4_ECDR224"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR225 { address = 0xffe10754; sn = "SARADC_4_ECDR225"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR226 { address = 0xffe10758; sn = "SARADC_4_ECDR226"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR227 { address = 0xffe1075c; sn = "SARADC_4_ECDR227"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR228 { address = 0xffe10760; sn = "SARADC_4_ECDR228"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR229 { address = 0xffe10764; sn = "SARADC_4_ECDR229"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR230 { address = 0xffe10768; sn = "SARADC_4_ECDR230"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR231 { address = 0xffe1076c; sn = "SARADC_4_ECDR231"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR232 { address = 0xffe10770; sn = "SARADC_4_ECDR232"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR233 { address = 0xffe10774; sn = "SARADC_4_ECDR233"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR234 { address = 0xffe10778; sn = "SARADC_4_ECDR234"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR235 { address = 0xffe1077c; sn = "SARADC_4_ECDR235"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR236 { address = 0xffe10780; sn = "SARADC_4_ECDR236"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR237 { address = 0xffe10784; sn = "SARADC_4_ECDR237"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR238 { address = 0xffe10788; sn = "SARADC_4_ECDR238"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR239 { address = 0xffe1078c; sn = "SARADC_4_ECDR239"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR240 { address = 0xffe10790; sn = "SARADC_4_ECDR240"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR241 { address = 0xffe10794; sn = "SARADC_4_ECDR241"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR242 { address = 0xffe10798; sn = "SARADC_4_ECDR242"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR243 { address = 0xffe1079c; sn = "SARADC_4_ECDR243"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR244 { address = 0xffe107a0; sn = "SARADC_4_ECDR244"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR245 { address = 0xffe107a4; sn = "SARADC_4_ECDR245"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR246 { address = 0xffe107a8; sn = "SARADC_4_ECDR246"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR247 { address = 0xffe107ac; sn = "SARADC_4_ECDR247"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR248 { address = 0xffe107b0; sn = "SARADC_4_ECDR248"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR249 { address = 0xffe107b4; sn = "SARADC_4_ECDR249"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR250 { address = 0xffe107b8; sn = "SARADC_4_ECDR250"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR251 { address = 0xffe107bc; sn = "SARADC_4_ECDR251"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR252 { address = 0xffe107c0; sn = "SARADC_4_ECDR252"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR253 { address = 0xffe107c4; sn = "SARADC_4_ECDR253"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR254 { address = 0xffe107c8; sn = "SARADC_4_ECDR254"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_4_ECDR255 { address = 0xffe107cc; sn = "SARADC_4_ECDR255"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_MCR { address = 0xffe3c000; sn = "SARADC_B_MCR"; access = "memorymapped"; width = 32; ${_DESC1835_}; type = "bitfield_SARADC_0_MCR" } SARADC_B_MSR { address = 0xffe3c004; sn = "SARADC_B_MSR"; access = "memorymapped"; width = 32; ${_DESC1855_}; type = "bitfield_SARADC_0_MSR" permission = "write/none" } SARADC_B_ISR { address = 0xffe3c010; sn = "SARADC_B_ISR"; access = "memorymapped"; width = 32; ${_DESC1862_}; type = "bitfield_SARADC_0_ISR" } SARADC_B_ICIPR0 { address = 0xffe3c014; sn = "SARADC_B_ICIPR0"; access = "memorymapped"; width = 32; ${_DESC1868_}; type = "bitfield_SARADC_0_ICIPR0" } SARADC_B_ICIPR1 { address = 0xffe3c018; sn = "SARADC_B_ICIPR1"; access = "memorymapped"; width = 32; ${_DESC1868_}; type = "bitfield_SARADC_0_ICIPR0" } SARADC_B_ICIPR2 { address = 0xffe3c01c; sn = "SARADC_B_ICIPR2"; access = "memorymapped"; width = 32; ${_DESC1868_}; type = "bitfield_SARADC_0_ICIPR0" } SARADC_B_IMR { address = 0xffe3c020; sn = "SARADC_B_IMR"; access = "memorymapped"; width = 32; ${_DESC1870_}; type = "bitfield_SARADC_0_IMR" } SARADC_B_ICIMR0 { address = 0xffe3c024; sn = "SARADC_B_ICIMR0"; access = "memorymapped"; width = 32; ${_DESC1876_}; type = "bitfield_SARADC_0_ICIMR0" } SARADC_B_ICIMR1 { address = 0xffe3c028; sn = "SARADC_B_ICIMR1"; access = "memorymapped"; width = 32; ${_DESC1876_}; type = "bitfield_SARADC_0_ICIMR0" } SARADC_B_ICIMR2 { address = 0xffe3c02c; sn = "SARADC_B_ICIMR2"; access = "memorymapped"; width = 32; ${_DESC1876_}; type = "bitfield_SARADC_0_ICIMR0" } SARADC_B_WTISR { address = 0xffe3c030; sn = "SARADC_B_WTISR"; access = "memorymapped"; width = 32; ${_DESC1878_}; type = "bitfield_SARADC_0_WTISR" } SARADC_B_WTIMR { address = 0xffe3c034; sn = "SARADC_B_WTIMR"; access = "memorymapped"; width = 32; ${_DESC1881_}; type = "bitfield_SARADC_0_WTIMR" } SARADC_B_DMAE { address = 0xffe3c040; sn = "SARADC_B_DMAE"; access = "memorymapped"; width = 32; ${_DESC1884_}; type = "bitfield_SARADC_0_DMAE" } SARADC_B_ICDSR0 { address = 0xffe3c044; sn = "SARADC_B_ICDSR0"; access = "memorymapped"; width = 32; ${_DESC1887_}; type = "bitfield_SARADC_0_ICDSR0" } SARADC_B_ICDSR1 { address = 0xffe3c048; sn = "SARADC_B_ICDSR1"; access = "memorymapped"; width = 32; ${_DESC1887_}; type = "bitfield_SARADC_0_ICDSR0" } SARADC_B_ICDSR2 { address = 0xffe3c04c; sn = "SARADC_B_ICDSR2"; access = "memorymapped"; width = 32; ${_DESC1887_}; type = "bitfield_SARADC_0_ICDSR0" } SARADC_B_WTHRHLR0 { address = 0xffe3c060; sn = "SARADC_B_WTHRHLR0"; access = "memorymapped"; width = 32; ${_DESC1889_}; type = "bitfield_SARADC_0_WTHRHLR0" } SARADC_B_WTHRHLR1 { address = 0xffe3c064; sn = "SARADC_B_WTHRHLR1"; access = "memorymapped"; width = 32; ${_DESC1889_}; type = "bitfield_SARADC_0_WTHRHLR0" } SARADC_B_WTHRHLR2 { address = 0xffe3c068; sn = "SARADC_B_WTHRHLR2"; access = "memorymapped"; width = 32; ${_DESC1889_}; type = "bitfield_SARADC_0_WTHRHLR0" } SARADC_B_WTHRHLR3 { address = 0xffe3c06c; sn = "SARADC_B_WTHRHLR3"; access = "memorymapped"; width = 32; ${_DESC1889_}; type = "bitfield_SARADC_0_WTHRHLR0" } SARADC_B_CTR0 { address = 0xffe3c094; sn = "SARADC_B_CTR0"; access = "memorymapped"; width = 32; ${_DESC1892_}; type = "bitfield_SARADC_0_CTR0" } SARADC_B_CTR1 { address = 0xffe3c098; sn = "SARADC_B_CTR1"; access = "memorymapped"; width = 32; ${_DESC1892_}; type = "bitfield_SARADC_0_CTR0" } SARADC_B_CTR2 { address = 0xffe3c09c; sn = "SARADC_B_CTR2"; access = "memorymapped"; width = 32; ${_DESC1892_}; type = "bitfield_SARADC_0_CTR0" } SARADC_B_CTR3 { address = 0xffe3c0a0; sn = "SARADC_B_CTR3"; access = "memorymapped"; width = 32; ${_DESC1892_}; type = "bitfield_SARADC_0_CTR0" } SARADC_B_ICNCMR0 { address = 0xffe3c0a4; sn = "SARADC_B_ICNCMR0"; access = "memorymapped"; width = 32; ${_DESC1896_}; type = "bitfield_SARADC_0_ICNCMR0" } SARADC_B_ICNCMR1 { address = 0xffe3c0a8; sn = "SARADC_B_ICNCMR1"; access = "memorymapped"; width = 32; ${_DESC1896_}; type = "bitfield_SARADC_0_ICNCMR0" } SARADC_B_ICNCMR2 { address = 0xffe3c0ac; sn = "SARADC_B_ICNCMR2"; access = "memorymapped"; width = 32; ${_DESC1896_}; type = "bitfield_SARADC_0_ICNCMR0" } SARADC_B_ICJCMR0 { address = 0xffe3c0b4; sn = "SARADC_B_ICJCMR0"; access = "memorymapped"; width = 32; ${_DESC1898_}; type = "bitfield_SARADC_0_ICJCMR0" } SARADC_B_ICJCMR1 { address = 0xffe3c0b8; sn = "SARADC_B_ICJCMR1"; access = "memorymapped"; width = 32; ${_DESC1898_}; type = "bitfield_SARADC_0_ICJCMR0" } SARADC_B_ICJCMR2 { address = 0xffe3c0bc; sn = "SARADC_B_ICJCMR2"; access = "memorymapped"; width = 32; ${_DESC1898_}; type = "bitfield_SARADC_0_ICJCMR0" } SARADC_B_PDEDR { address = 0xffe3c0c8; sn = "SARADC_B_PDEDR"; access = "memorymapped"; width = 32; ${_DESC1900_}; type = "bitfield_SARADC_0_PDEDR" } SARADC_B_ICDR0 { address = 0xffe3c100; sn = "SARADC_B_ICDR0"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR1 { address = 0xffe3c104; sn = "SARADC_B_ICDR1"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR2 { address = 0xffe3c108; sn = "SARADC_B_ICDR2"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR3 { address = 0xffe3c10c; sn = "SARADC_B_ICDR3"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR4 { address = 0xffe3c110; sn = "SARADC_B_ICDR4"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR5 { address = 0xffe3c114; sn = "SARADC_B_ICDR5"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR6 { address = 0xffe3c118; sn = "SARADC_B_ICDR6"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR7 { address = 0xffe3c11c; sn = "SARADC_B_ICDR7"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR8 { address = 0xffe3c120; sn = "SARADC_B_ICDR8"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR9 { address = 0xffe3c124; sn = "SARADC_B_ICDR9"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR10 { address = 0xffe3c128; sn = "SARADC_B_ICDR10"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR11 { address = 0xffe3c12c; sn = "SARADC_B_ICDR11"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR12 { address = 0xffe3c130; sn = "SARADC_B_ICDR12"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR13 { address = 0xffe3c134; sn = "SARADC_B_ICDR13"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR14 { address = 0xffe3c138; sn = "SARADC_B_ICDR14"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR15 { address = 0xffe3c13c; sn = "SARADC_B_ICDR15"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR16 { address = 0xffe3c140; sn = "SARADC_B_ICDR16"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR17 { address = 0xffe3c144; sn = "SARADC_B_ICDR17"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR18 { address = 0xffe3c148; sn = "SARADC_B_ICDR18"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR19 { address = 0xffe3c14c; sn = "SARADC_B_ICDR19"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR20 { address = 0xffe3c150; sn = "SARADC_B_ICDR20"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR21 { address = 0xffe3c154; sn = "SARADC_B_ICDR21"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR22 { address = 0xffe3c158; sn = "SARADC_B_ICDR22"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR23 { address = 0xffe3c15c; sn = "SARADC_B_ICDR23"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR24 { address = 0xffe3c160; sn = "SARADC_B_ICDR24"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR25 { address = 0xffe3c164; sn = "SARADC_B_ICDR25"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR26 { address = 0xffe3c168; sn = "SARADC_B_ICDR26"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR27 { address = 0xffe3c16c; sn = "SARADC_B_ICDR27"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR28 { address = 0xffe3c170; sn = "SARADC_B_ICDR28"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR29 { address = 0xffe3c174; sn = "SARADC_B_ICDR29"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR30 { address = 0xffe3c178; sn = "SARADC_B_ICDR30"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR31 { address = 0xffe3c17c; sn = "SARADC_B_ICDR31"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR32 { address = 0xffe3c180; sn = "SARADC_B_ICDR32"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR33 { address = 0xffe3c184; sn = "SARADC_B_ICDR33"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR34 { address = 0xffe3c188; sn = "SARADC_B_ICDR34"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR35 { address = 0xffe3c18c; sn = "SARADC_B_ICDR35"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR36 { address = 0xffe3c190; sn = "SARADC_B_ICDR36"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR37 { address = 0xffe3c194; sn = "SARADC_B_ICDR37"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR38 { address = 0xffe3c198; sn = "SARADC_B_ICDR38"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR39 { address = 0xffe3c19c; sn = "SARADC_B_ICDR39"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR40 { address = 0xffe3c1a0; sn = "SARADC_B_ICDR40"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR41 { address = 0xffe3c1a4; sn = "SARADC_B_ICDR41"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR42 { address = 0xffe3c1a8; sn = "SARADC_B_ICDR42"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR43 { address = 0xffe3c1ac; sn = "SARADC_B_ICDR43"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR44 { address = 0xffe3c1b0; sn = "SARADC_B_ICDR44"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR45 { address = 0xffe3c1b4; sn = "SARADC_B_ICDR45"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR46 { address = 0xffe3c1b8; sn = "SARADC_B_ICDR46"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR47 { address = 0xffe3c1bc; sn = "SARADC_B_ICDR47"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR48 { address = 0xffe3c1c0; sn = "SARADC_B_ICDR48"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR49 { address = 0xffe3c1c4; sn = "SARADC_B_ICDR49"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR50 { address = 0xffe3c1c8; sn = "SARADC_B_ICDR50"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR51 { address = 0xffe3c1cc; sn = "SARADC_B_ICDR51"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR52 { address = 0xffe3c1d0; sn = "SARADC_B_ICDR52"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR53 { address = 0xffe3c1d4; sn = "SARADC_B_ICDR53"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR54 { address = 0xffe3c1d8; sn = "SARADC_B_ICDR54"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR55 { address = 0xffe3c1dc; sn = "SARADC_B_ICDR55"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR56 { address = 0xffe3c1e0; sn = "SARADC_B_ICDR56"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR57 { address = 0xffe3c1e4; sn = "SARADC_B_ICDR57"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR58 { address = 0xffe3c1e8; sn = "SARADC_B_ICDR58"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR59 { address = 0xffe3c1ec; sn = "SARADC_B_ICDR59"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR60 { address = 0xffe3c1f0; sn = "SARADC_B_ICDR60"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR61 { address = 0xffe3c1f4; sn = "SARADC_B_ICDR61"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR62 { address = 0xffe3c1f8; sn = "SARADC_B_ICDR62"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR63 { address = 0xffe3c1fc; sn = "SARADC_B_ICDR63"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR64 { address = 0xffe3c200; sn = "SARADC_B_ICDR64"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR65 { address = 0xffe3c204; sn = "SARADC_B_ICDR65"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR66 { address = 0xffe3c208; sn = "SARADC_B_ICDR66"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR67 { address = 0xffe3c20c; sn = "SARADC_B_ICDR67"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR68 { address = 0xffe3c210; sn = "SARADC_B_ICDR68"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR69 { address = 0xffe3c214; sn = "SARADC_B_ICDR69"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR70 { address = 0xffe3c218; sn = "SARADC_B_ICDR70"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR71 { address = 0xffe3c21c; sn = "SARADC_B_ICDR71"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR72 { address = 0xffe3c220; sn = "SARADC_B_ICDR72"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR73 { address = 0xffe3c224; sn = "SARADC_B_ICDR73"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR74 { address = 0xffe3c228; sn = "SARADC_B_ICDR74"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR75 { address = 0xffe3c22c; sn = "SARADC_B_ICDR75"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR76 { address = 0xffe3c230; sn = "SARADC_B_ICDR76"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR77 { address = 0xffe3c234; sn = "SARADC_B_ICDR77"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR78 { address = 0xffe3c238; sn = "SARADC_B_ICDR78"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR79 { address = 0xffe3c23c; sn = "SARADC_B_ICDR79"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR80 { address = 0xffe3c240; sn = "SARADC_B_ICDR80"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR81 { address = 0xffe3c244; sn = "SARADC_B_ICDR81"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR82 { address = 0xffe3c248; sn = "SARADC_B_ICDR82"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR83 { address = 0xffe3c24c; sn = "SARADC_B_ICDR83"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR84 { address = 0xffe3c250; sn = "SARADC_B_ICDR84"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR85 { address = 0xffe3c254; sn = "SARADC_B_ICDR85"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR86 { address = 0xffe3c258; sn = "SARADC_B_ICDR86"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR87 { address = 0xffe3c25c; sn = "SARADC_B_ICDR87"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR88 { address = 0xffe3c260; sn = "SARADC_B_ICDR88"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR89 { address = 0xffe3c264; sn = "SARADC_B_ICDR89"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR90 { address = 0xffe3c268; sn = "SARADC_B_ICDR90"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR91 { address = 0xffe3c26c; sn = "SARADC_B_ICDR91"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR92 { address = 0xffe3c270; sn = "SARADC_B_ICDR92"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR93 { address = 0xffe3c274; sn = "SARADC_B_ICDR93"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR94 { address = 0xffe3c278; sn = "SARADC_B_ICDR94"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICDR95 { address = 0xffe3c27c; sn = "SARADC_B_ICDR95"; access = "memorymapped"; width = 32; ${_DESC1902_}; type = "bitfield_SARADC_0_ICDR0" } SARADC_B_ICWSELR0 { address = 0xffe3c2b0; sn = "SARADC_B_ICWSELR0"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_B_ICWSELR1 { address = 0xffe3c2b4; sn = "SARADC_B_ICWSELR1"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_B_ICWSELR2 { address = 0xffe3c2b8; sn = "SARADC_B_ICWSELR2"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_B_ICWSELR3 { address = 0xffe3c2bc; sn = "SARADC_B_ICWSELR3"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_B_ICWSELR4 { address = 0xffe3c2c0; sn = "SARADC_B_ICWSELR4"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_B_ICWSELR5 { address = 0xffe3c2c4; sn = "SARADC_B_ICWSELR5"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_B_ICWSELR6 { address = 0xffe3c2c8; sn = "SARADC_B_ICWSELR6"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_B_ICWSELR7 { address = 0xffe3c2cc; sn = "SARADC_B_ICWSELR7"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_B_ICWSELR8 { address = 0xffe3c2d0; sn = "SARADC_B_ICWSELR8"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_B_ICWSELR9 { address = 0xffe3c2d4; sn = "SARADC_B_ICWSELR9"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_B_ICWSELR10 { address = 0xffe3c2d8; sn = "SARADC_B_ICWSELR10"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_B_ICWSELR11 { address = 0xffe3c2dc; sn = "SARADC_B_ICWSELR11"; access = "memorymapped"; width = 32; ${_DESC1912_}; type = "bitfield_SARADC_0_ICWSELR0" } SARADC_B_ICWENR0 { address = 0xffe3c2e0; sn = "SARADC_B_ICWENR0"; access = "memorymapped"; width = 32; ${_DESC1921_}; type = "bitfield_SARADC_0_ICWENR0" } SARADC_B_ICWENR1 { address = 0xffe3c2e4; sn = "SARADC_B_ICWENR1"; access = "memorymapped"; width = 32; ${_DESC1921_}; type = "bitfield_SARADC_0_ICWENR0" } SARADC_B_ICWENR2 { address = 0xffe3c2e8; sn = "SARADC_B_ICWENR2"; access = "memorymapped"; width = 32; ${_DESC1921_}; type = "bitfield_SARADC_0_ICWENR0" } SARADC_B_ICAWORR0 { address = 0xffe3c2f0; sn = "SARADC_B_ICAWORR0"; access = "memorymapped"; width = 32; ${_DESC1923_}; type = "bitfield_SARADC_0_ICAWORR0" } SARADC_B_ICAWORR1 { address = 0xffe3c2f4; sn = "SARADC_B_ICAWORR1"; access = "memorymapped"; width = 32; ${_DESC1923_}; type = "bitfield_SARADC_0_ICAWORR0" } SARADC_B_ICAWORR2 { address = 0xffe3c2f8; sn = "SARADC_B_ICAWORR2"; access = "memorymapped"; width = 32; ${_DESC1923_}; type = "bitfield_SARADC_0_ICAWORR0" } SARADC_B_TCIPR { address = 0xffe3c400; sn = "SARADC_B_TCIPR"; access = "memorymapped"; width = 32; ${_DESC1925_}; type = "bitfield_SARADC_0_ICIPR0" } SARADC_B_TCIMR { address = 0xffe3c404; sn = "SARADC_B_TCIMR"; access = "memorymapped"; width = 32; ${_DESC1926_}; type = "bitfield_SARADC_0_ICIMR0" } SARADC_B_TCDSR { address = 0xffe3c408; sn = "SARADC_B_TCDSR"; access = "memorymapped"; width = 32; ${_DESC1927_}; type = "bitfield_SARADC_0_ICDSR0" } SARADC_B_TCNCMR { address = 0xffe3c40c; sn = "SARADC_B_TCNCMR"; access = "memorymapped"; width = 32; ${_DESC1928_}; type = "bitfield_SARADC_0_ICNCMR0" } SARADC_B_TCJCMR { address = 0xffe3c410; sn = "SARADC_B_TCJCMR"; access = "memorymapped"; width = 32; ${_DESC1929_}; type = "bitfield_SARADC_0_TCJCMR" } SARADC_B_TCWSELR0 { address = 0xffe3c414; sn = "SARADC_B_TCWSELR0"; access = "memorymapped"; width = 32; ${_DESC1930_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_B_TCWSELR1 { address = 0xffe3c418; sn = "SARADC_B_TCWSELR1"; access = "memorymapped"; width = 32; ${_DESC1930_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_B_TCWSELR2 { address = 0xffe3c41c; sn = "SARADC_B_TCWSELR2"; access = "memorymapped"; width = 32; ${_DESC1930_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_B_TCWSELR3 { address = 0xffe3c420; sn = "SARADC_B_TCWSELR3"; access = "memorymapped"; width = 32; ${_DESC1930_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_B_TCWENR { address = 0xffe3c424; sn = "SARADC_B_TCWENR"; access = "memorymapped"; width = 32; ${_DESC1939_}; type = "bitfield_SARADC_0_ICWENR0" } SARADC_B_TCAWORR { address = 0xffe3c428; sn = "SARADC_B_TCAWORR"; access = "memorymapped"; width = 32; ${_DESC1940_}; type = "bitfield_SARADC_0_ICAWORR0" } SARADC_B_TCCAPR0 { address = 0xffe3c430; sn = "SARADC_B_TCCAPR0"; access = "memorymapped"; width = 32; ${_DESC1941_}; type = "bitfield_SARADC_0_TCCAPR0" } SARADC_B_TCCAPR1 { address = 0xffe3c434; sn = "SARADC_B_TCCAPR1"; access = "memorymapped"; width = 32; ${_DESC1941_}; type = "bitfield_SARADC_0_TCCAPR0" } SARADC_B_TCCAPR2 { address = 0xffe3c438; sn = "SARADC_B_TCCAPR2"; access = "memorymapped"; width = 32; ${_DESC1941_}; type = "bitfield_SARADC_0_TCCAPR0" } SARADC_B_TCCAPR3 { address = 0xffe3c43c; sn = "SARADC_B_TCCAPR3"; access = "memorymapped"; width = 32; ${_DESC1941_}; type = "bitfield_SARADC_0_TCCAPR0" } SARADC_B_TCCAPR4 { address = 0xffe3c440; sn = "SARADC_B_TCCAPR4"; access = "memorymapped"; width = 32; ${_DESC1941_}; type = "bitfield_SARADC_0_TCCAPR0" } SARADC_B_TCCAPR5 { address = 0xffe3c444; sn = "SARADC_B_TCCAPR5"; access = "memorymapped"; width = 32; ${_DESC1941_}; type = "bitfield_SARADC_0_TCCAPR0" } SARADC_B_TCCAPR6 { address = 0xffe3c448; sn = "SARADC_B_TCCAPR6"; access = "memorymapped"; width = 32; ${_DESC1941_}; type = "bitfield_SARADC_0_TCCAPR0" } SARADC_B_TCCAPR7 { address = 0xffe3c44c; sn = "SARADC_B_TCCAPR7"; access = "memorymapped"; width = 32; ${_DESC1941_}; type = "bitfield_SARADC_0_TCCAPR0" } SARADC_B_TCDR96 { address = 0xffe3c450; sn = "SARADC_B_TCDR96"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR97 { address = 0xffe3c454; sn = "SARADC_B_TCDR97"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR98 { address = 0xffe3c458; sn = "SARADC_B_TCDR98"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR99 { address = 0xffe3c45c; sn = "SARADC_B_TCDR99"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR100 { address = 0xffe3c460; sn = "SARADC_B_TCDR100"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR101 { address = 0xffe3c464; sn = "SARADC_B_TCDR101"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR102 { address = 0xffe3c468; sn = "SARADC_B_TCDR102"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR103 { address = 0xffe3c46c; sn = "SARADC_B_TCDR103"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR104 { address = 0xffe3c470; sn = "SARADC_B_TCDR104"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR105 { address = 0xffe3c474; sn = "SARADC_B_TCDR105"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR106 { address = 0xffe3c478; sn = "SARADC_B_TCDR106"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR107 { address = 0xffe3c47c; sn = "SARADC_B_TCDR107"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR108 { address = 0xffe3c480; sn = "SARADC_B_TCDR108"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR109 { address = 0xffe3c484; sn = "SARADC_B_TCDR109"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR110 { address = 0xffe3c488; sn = "SARADC_B_TCDR110"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR111 { address = 0xffe3c48c; sn = "SARADC_B_TCDR111"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR112 { address = 0xffe3c490; sn = "SARADC_B_TCDR112"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR113 { address = 0xffe3c494; sn = "SARADC_B_TCDR113"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR114 { address = 0xffe3c498; sn = "SARADC_B_TCDR114"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR115 { address = 0xffe3c49c; sn = "SARADC_B_TCDR115"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR116 { address = 0xffe3c4a0; sn = "SARADC_B_TCDR116"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR117 { address = 0xffe3c4a4; sn = "SARADC_B_TCDR117"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR118 { address = 0xffe3c4a8; sn = "SARADC_B_TCDR118"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR119 { address = 0xffe3c4ac; sn = "SARADC_B_TCDR119"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR120 { address = 0xffe3c4b0; sn = "SARADC_B_TCDR120"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR121 { address = 0xffe3c4b4; sn = "SARADC_B_TCDR121"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR122 { address = 0xffe3c4b8; sn = "SARADC_B_TCDR122"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR123 { address = 0xffe3c4bc; sn = "SARADC_B_TCDR123"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR124 { address = 0xffe3c4c0; sn = "SARADC_B_TCDR124"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR125 { address = 0xffe3c4c4; sn = "SARADC_B_TCDR125"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR126 { address = 0xffe3c4c8; sn = "SARADC_B_TCDR126"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_TCDR127 { address = 0xffe3c4cc; sn = "SARADC_B_TCDR127"; access = "memorymapped"; width = 32; ${_DESC1950_}; type = "bitfield_SARADC_0_TCDR96" } SARADC_B_ECDSDR { address = 0xffe3c500; sn = "SARADC_B_ECDSDR"; access = "memorymapped"; width = 32; ${_DESC1952_}; type = "bitfield_SARADC_0_ECDSDR" } SARADC_B_ECIPR0 { address = 0xffe3c510; sn = "SARADC_B_ECIPR0"; access = "memorymapped"; width = 32; ${_DESC1954_}; type = "bitfield_SARADC_0_ICIPR0" } SARADC_B_ECIPR1 { address = 0xffe3c514; sn = "SARADC_B_ECIPR1"; access = "memorymapped"; width = 32; ${_DESC1954_}; type = "bitfield_SARADC_0_ICIPR0" } SARADC_B_ECIPR2 { address = 0xffe3c518; sn = "SARADC_B_ECIPR2"; access = "memorymapped"; width = 32; ${_DESC1954_}; type = "bitfield_SARADC_0_ICIPR0" } SARADC_B_ECIPR3 { address = 0xffe3c51c; sn = "SARADC_B_ECIPR3"; access = "memorymapped"; width = 32; ${_DESC1954_}; type = "bitfield_SARADC_0_ICIPR0" } SARADC_B_ECIMR0 { address = 0xffe3c520; sn = "SARADC_B_ECIMR0"; access = "memorymapped"; width = 32; ${_DESC1955_}; type = "bitfield_SARADC_0_ICIMR0" } SARADC_B_ECIMR1 { address = 0xffe3c524; sn = "SARADC_B_ECIMR1"; access = "memorymapped"; width = 32; ${_DESC1955_}; type = "bitfield_SARADC_0_ICIMR0" } SARADC_B_ECIMR2 { address = 0xffe3c528; sn = "SARADC_B_ECIMR2"; access = "memorymapped"; width = 32; ${_DESC1955_}; type = "bitfield_SARADC_0_ICIMR0" } SARADC_B_ECIMR3 { address = 0xffe3c52c; sn = "SARADC_B_ECIMR3"; access = "memorymapped"; width = 32; ${_DESC1955_}; type = "bitfield_SARADC_0_ICIMR0" } SARADC_B_ECDSR0 { address = 0xffe3c530; sn = "SARADC_B_ECDSR0"; access = "memorymapped"; width = 32; ${_DESC1956_}; type = "bitfield_SARADC_0_ICDSR0" } SARADC_B_ECDSR1 { address = 0xffe3c534; sn = "SARADC_B_ECDSR1"; access = "memorymapped"; width = 32; ${_DESC1956_}; type = "bitfield_SARADC_0_ICDSR0" } SARADC_B_ECDSR2 { address = 0xffe3c538; sn = "SARADC_B_ECDSR2"; access = "memorymapped"; width = 32; ${_DESC1956_}; type = "bitfield_SARADC_0_ICDSR0" } SARADC_B_ECDSR3 { address = 0xffe3c53c; sn = "SARADC_B_ECDSR3"; access = "memorymapped"; width = 32; ${_DESC1956_}; type = "bitfield_SARADC_0_ICDSR0" } SARADC_B_ECNCMR0 { address = 0xffe3c540; sn = "SARADC_B_ECNCMR0"; access = "memorymapped"; width = 32; ${_DESC1957_}; type = "bitfield_SARADC_0_ICNCMR0" } SARADC_B_ECNCMR1 { address = 0xffe3c544; sn = "SARADC_B_ECNCMR1"; access = "memorymapped"; width = 32; ${_DESC1957_}; type = "bitfield_SARADC_0_ICNCMR0" } SARADC_B_ECNCMR2 { address = 0xffe3c548; sn = "SARADC_B_ECNCMR2"; access = "memorymapped"; width = 32; ${_DESC1957_}; type = "bitfield_SARADC_0_ICNCMR0" } SARADC_B_ECNCMR3 { address = 0xffe3c54c; sn = "SARADC_B_ECNCMR3"; access = "memorymapped"; width = 32; ${_DESC1957_}; type = "bitfield_SARADC_0_ICNCMR0" } SARADC_B_ECJCMR0 { address = 0xffe3c550; sn = "SARADC_B_ECJCMR0"; access = "memorymapped"; width = 32; ${_DESC1958_}; type = "bitfield_SARADC_0_TCJCMR" } SARADC_B_ECJCMR1 { address = 0xffe3c554; sn = "SARADC_B_ECJCMR1"; access = "memorymapped"; width = 32; ${_DESC1958_}; type = "bitfield_SARADC_0_TCJCMR" } SARADC_B_ECJCMR2 { address = 0xffe3c558; sn = "SARADC_B_ECJCMR2"; access = "memorymapped"; width = 32; ${_DESC1958_}; type = "bitfield_SARADC_0_TCJCMR" } SARADC_B_ECJCMR3 { address = 0xffe3c55c; sn = "SARADC_B_ECJCMR3"; access = "memorymapped"; width = 32; ${_DESC1958_}; type = "bitfield_SARADC_0_TCJCMR" } SARADC_B_ECWSELR0 { address = 0xffe3c560; sn = "SARADC_B_ECWSELR0"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_B_ECWSELR1 { address = 0xffe3c564; sn = "SARADC_B_ECWSELR1"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_B_ECWSELR2 { address = 0xffe3c568; sn = "SARADC_B_ECWSELR2"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_B_ECWSELR3 { address = 0xffe3c56c; sn = "SARADC_B_ECWSELR3"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_B_ECWSELR4 { address = 0xffe3c570; sn = "SARADC_B_ECWSELR4"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_B_ECWSELR5 { address = 0xffe3c574; sn = "SARADC_B_ECWSELR5"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_B_ECWSELR6 { address = 0xffe3c578; sn = "SARADC_B_ECWSELR6"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_B_ECWSELR7 { address = 0xffe3c57c; sn = "SARADC_B_ECWSELR7"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_B_ECWSELR8 { address = 0xffe3c580; sn = "SARADC_B_ECWSELR8"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_B_ECWSELR9 { address = 0xffe3c584; sn = "SARADC_B_ECWSELR9"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_B_ECWSELR10 { address = 0xffe3c588; sn = "SARADC_B_ECWSELR10"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_B_ECWSELR11 { address = 0xffe3c58c; sn = "SARADC_B_ECWSELR11"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_B_ECWSELR12 { address = 0xffe3c590; sn = "SARADC_B_ECWSELR12"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_B_ECWSELR13 { address = 0xffe3c594; sn = "SARADC_B_ECWSELR13"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_B_ECWSELR14 { address = 0xffe3c598; sn = "SARADC_B_ECWSELR14"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_B_ECWSELR15 { address = 0xffe3c59c; sn = "SARADC_B_ECWSELR15"; access = "memorymapped"; width = 32; ${_DESC1959_}; type = "bitfield_SARADC_0_TCWSELR0" } SARADC_B_ECWENR0 { address = 0xffe3c5a0; sn = "SARADC_B_ECWENR0"; access = "memorymapped"; width = 32; ${_DESC1960_}; type = "bitfield_SARADC_0_ICWENR0" } SARADC_B_ECWENR1 { address = 0xffe3c5a4; sn = "SARADC_B_ECWENR1"; access = "memorymapped"; width = 32; ${_DESC1960_}; type = "bitfield_SARADC_0_ICWENR0" } SARADC_B_ECWENR2 { address = 0xffe3c5a8; sn = "SARADC_B_ECWENR2"; access = "memorymapped"; width = 32; ${_DESC1960_}; type = "bitfield_SARADC_0_ICWENR0" } SARADC_B_ECWENR3 { address = 0xffe3c5ac; sn = "SARADC_B_ECWENR3"; access = "memorymapped"; width = 32; ${_DESC1960_}; type = "bitfield_SARADC_0_ICWENR0" } SARADC_B_ECAWORR0 { address = 0xffe3c5b0; sn = "SARADC_B_ECAWORR0"; access = "memorymapped"; width = 32; ${_DESC1961_}; type = "bitfield_SARADC_0_ICAWORR0" } SARADC_B_ECAWORR1 { address = 0xffe3c5b4; sn = "SARADC_B_ECAWORR1"; access = "memorymapped"; width = 32; ${_DESC1961_}; type = "bitfield_SARADC_0_ICAWORR0" } SARADC_B_ECAWORR2 { address = 0xffe3c5b8; sn = "SARADC_B_ECAWORR2"; access = "memorymapped"; width = 32; ${_DESC1961_}; type = "bitfield_SARADC_0_ICAWORR0" } SARADC_B_ECAWORR3 { address = 0xffe3c5bc; sn = "SARADC_B_ECAWORR3"; access = "memorymapped"; width = 32; ${_DESC1961_}; type = "bitfield_SARADC_0_ICAWORR0" } SARADC_B_ECMICR0 { address = 0xffe3c5c0; sn = "SARADC_B_ECMICR0"; access = "memorymapped"; width = 32; ${_DESC1962_}; type = "bitfield_SARADC_0_ECMICR0" } SARADC_B_ECMICR1 { address = 0xffe3c5c4; sn = "SARADC_B_ECMICR1"; access = "memorymapped"; width = 32; ${_DESC1962_}; type = "bitfield_SARADC_0_ECMICR0" } SARADC_B_ECMICR2 { address = 0xffe3c5c8; sn = "SARADC_B_ECMICR2"; access = "memorymapped"; width = 32; ${_DESC1962_}; type = "bitfield_SARADC_0_ECMICR0" } SARADC_B_ECMICR3 { address = 0xffe3c5cc; sn = "SARADC_B_ECMICR3"; access = "memorymapped"; width = 32; ${_DESC1962_}; type = "bitfield_SARADC_0_ECMICR0" } SARADC_B_ECDR128 { address = 0xffe3c5d0; sn = "SARADC_B_ECDR128"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR129 { address = 0xffe3c5d4; sn = "SARADC_B_ECDR129"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR130 { address = 0xffe3c5d8; sn = "SARADC_B_ECDR130"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR131 { address = 0xffe3c5dc; sn = "SARADC_B_ECDR131"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR132 { address = 0xffe3c5e0; sn = "SARADC_B_ECDR132"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR133 { address = 0xffe3c5e4; sn = "SARADC_B_ECDR133"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR134 { address = 0xffe3c5e8; sn = "SARADC_B_ECDR134"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR135 { address = 0xffe3c5ec; sn = "SARADC_B_ECDR135"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR136 { address = 0xffe3c5f0; sn = "SARADC_B_ECDR136"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR137 { address = 0xffe3c5f4; sn = "SARADC_B_ECDR137"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR138 { address = 0xffe3c5f8; sn = "SARADC_B_ECDR138"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR139 { address = 0xffe3c5fc; sn = "SARADC_B_ECDR139"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR140 { address = 0xffe3c600; sn = "SARADC_B_ECDR140"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR141 { address = 0xffe3c604; sn = "SARADC_B_ECDR141"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR142 { address = 0xffe3c608; sn = "SARADC_B_ECDR142"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR143 { address = 0xffe3c60c; sn = "SARADC_B_ECDR143"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR144 { address = 0xffe3c610; sn = "SARADC_B_ECDR144"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR145 { address = 0xffe3c614; sn = "SARADC_B_ECDR145"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR146 { address = 0xffe3c618; sn = "SARADC_B_ECDR146"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR147 { address = 0xffe3c61c; sn = "SARADC_B_ECDR147"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR148 { address = 0xffe3c620; sn = "SARADC_B_ECDR148"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR149 { address = 0xffe3c624; sn = "SARADC_B_ECDR149"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR150 { address = 0xffe3c628; sn = "SARADC_B_ECDR150"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR151 { address = 0xffe3c62c; sn = "SARADC_B_ECDR151"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR152 { address = 0xffe3c630; sn = "SARADC_B_ECDR152"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR153 { address = 0xffe3c634; sn = "SARADC_B_ECDR153"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR154 { address = 0xffe3c638; sn = "SARADC_B_ECDR154"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR155 { address = 0xffe3c63c; sn = "SARADC_B_ECDR155"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR156 { address = 0xffe3c640; sn = "SARADC_B_ECDR156"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR157 { address = 0xffe3c644; sn = "SARADC_B_ECDR157"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR158 { address = 0xffe3c648; sn = "SARADC_B_ECDR158"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR159 { address = 0xffe3c64c; sn = "SARADC_B_ECDR159"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR160 { address = 0xffe3c650; sn = "SARADC_B_ECDR160"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR161 { address = 0xffe3c654; sn = "SARADC_B_ECDR161"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR162 { address = 0xffe3c658; sn = "SARADC_B_ECDR162"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR163 { address = 0xffe3c65c; sn = "SARADC_B_ECDR163"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR164 { address = 0xffe3c660; sn = "SARADC_B_ECDR164"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR165 { address = 0xffe3c664; sn = "SARADC_B_ECDR165"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR166 { address = 0xffe3c668; sn = "SARADC_B_ECDR166"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR167 { address = 0xffe3c66c; sn = "SARADC_B_ECDR167"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR168 { address = 0xffe3c670; sn = "SARADC_B_ECDR168"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR169 { address = 0xffe3c674; sn = "SARADC_B_ECDR169"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR170 { address = 0xffe3c678; sn = "SARADC_B_ECDR170"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR171 { address = 0xffe3c67c; sn = "SARADC_B_ECDR171"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR172 { address = 0xffe3c680; sn = "SARADC_B_ECDR172"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR173 { address = 0xffe3c684; sn = "SARADC_B_ECDR173"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR174 { address = 0xffe3c688; sn = "SARADC_B_ECDR174"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR175 { address = 0xffe3c68c; sn = "SARADC_B_ECDR175"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR176 { address = 0xffe3c690; sn = "SARADC_B_ECDR176"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR177 { address = 0xffe3c694; sn = "SARADC_B_ECDR177"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR178 { address = 0xffe3c698; sn = "SARADC_B_ECDR178"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR179 { address = 0xffe3c69c; sn = "SARADC_B_ECDR179"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR180 { address = 0xffe3c6a0; sn = "SARADC_B_ECDR180"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR181 { address = 0xffe3c6a4; sn = "SARADC_B_ECDR181"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR182 { address = 0xffe3c6a8; sn = "SARADC_B_ECDR182"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR183 { address = 0xffe3c6ac; sn = "SARADC_B_ECDR183"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR184 { address = 0xffe3c6b0; sn = "SARADC_B_ECDR184"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR185 { address = 0xffe3c6b4; sn = "SARADC_B_ECDR185"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR186 { address = 0xffe3c6b8; sn = "SARADC_B_ECDR186"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR187 { address = 0xffe3c6bc; sn = "SARADC_B_ECDR187"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR188 { address = 0xffe3c6c0; sn = "SARADC_B_ECDR188"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR189 { address = 0xffe3c6c4; sn = "SARADC_B_ECDR189"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR190 { address = 0xffe3c6c8; sn = "SARADC_B_ECDR190"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR191 { address = 0xffe3c6cc; sn = "SARADC_B_ECDR191"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR192 { address = 0xffe3c6d0; sn = "SARADC_B_ECDR192"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR193 { address = 0xffe3c6d4; sn = "SARADC_B_ECDR193"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR194 { address = 0xffe3c6d8; sn = "SARADC_B_ECDR194"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR195 { address = 0xffe3c6dc; sn = "SARADC_B_ECDR195"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR196 { address = 0xffe3c6e0; sn = "SARADC_B_ECDR196"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR197 { address = 0xffe3c6e4; sn = "SARADC_B_ECDR197"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR198 { address = 0xffe3c6e8; sn = "SARADC_B_ECDR198"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR199 { address = 0xffe3c6ec; sn = "SARADC_B_ECDR199"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR200 { address = 0xffe3c6f0; sn = "SARADC_B_ECDR200"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR201 { address = 0xffe3c6f4; sn = "SARADC_B_ECDR201"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR202 { address = 0xffe3c6f8; sn = "SARADC_B_ECDR202"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR203 { address = 0xffe3c6fc; sn = "SARADC_B_ECDR203"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR204 { address = 0xffe3c700; sn = "SARADC_B_ECDR204"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR205 { address = 0xffe3c704; sn = "SARADC_B_ECDR205"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR206 { address = 0xffe3c708; sn = "SARADC_B_ECDR206"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR207 { address = 0xffe3c70c; sn = "SARADC_B_ECDR207"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR208 { address = 0xffe3c710; sn = "SARADC_B_ECDR208"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR209 { address = 0xffe3c714; sn = "SARADC_B_ECDR209"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR210 { address = 0xffe3c718; sn = "SARADC_B_ECDR210"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR211 { address = 0xffe3c71c; sn = "SARADC_B_ECDR211"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR212 { address = 0xffe3c720; sn = "SARADC_B_ECDR212"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR213 { address = 0xffe3c724; sn = "SARADC_B_ECDR213"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR214 { address = 0xffe3c728; sn = "SARADC_B_ECDR214"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR215 { address = 0xffe3c72c; sn = "SARADC_B_ECDR215"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR216 { address = 0xffe3c730; sn = "SARADC_B_ECDR216"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR217 { address = 0xffe3c734; sn = "SARADC_B_ECDR217"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR218 { address = 0xffe3c738; sn = "SARADC_B_ECDR218"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR219 { address = 0xffe3c73c; sn = "SARADC_B_ECDR219"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR220 { address = 0xffe3c740; sn = "SARADC_B_ECDR220"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR221 { address = 0xffe3c744; sn = "SARADC_B_ECDR221"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR222 { address = 0xffe3c748; sn = "SARADC_B_ECDR222"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR223 { address = 0xffe3c74c; sn = "SARADC_B_ECDR223"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR224 { address = 0xffe3c750; sn = "SARADC_B_ECDR224"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR225 { address = 0xffe3c754; sn = "SARADC_B_ECDR225"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR226 { address = 0xffe3c758; sn = "SARADC_B_ECDR226"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR227 { address = 0xffe3c75c; sn = "SARADC_B_ECDR227"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR228 { address = 0xffe3c760; sn = "SARADC_B_ECDR228"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR229 { address = 0xffe3c764; sn = "SARADC_B_ECDR229"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR230 { address = 0xffe3c768; sn = "SARADC_B_ECDR230"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR231 { address = 0xffe3c76c; sn = "SARADC_B_ECDR231"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR232 { address = 0xffe3c770; sn = "SARADC_B_ECDR232"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR233 { address = 0xffe3c774; sn = "SARADC_B_ECDR233"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR234 { address = 0xffe3c778; sn = "SARADC_B_ECDR234"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR235 { address = 0xffe3c77c; sn = "SARADC_B_ECDR235"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR236 { address = 0xffe3c780; sn = "SARADC_B_ECDR236"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR237 { address = 0xffe3c784; sn = "SARADC_B_ECDR237"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR238 { address = 0xffe3c788; sn = "SARADC_B_ECDR238"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR239 { address = 0xffe3c78c; sn = "SARADC_B_ECDR239"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR240 { address = 0xffe3c790; sn = "SARADC_B_ECDR240"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR241 { address = 0xffe3c794; sn = "SARADC_B_ECDR241"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR242 { address = 0xffe3c798; sn = "SARADC_B_ECDR242"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR243 { address = 0xffe3c79c; sn = "SARADC_B_ECDR243"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR244 { address = 0xffe3c7a0; sn = "SARADC_B_ECDR244"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR245 { address = 0xffe3c7a4; sn = "SARADC_B_ECDR245"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR246 { address = 0xffe3c7a8; sn = "SARADC_B_ECDR246"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR247 { address = 0xffe3c7ac; sn = "SARADC_B_ECDR247"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR248 { address = 0xffe3c7b0; sn = "SARADC_B_ECDR248"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR249 { address = 0xffe3c7b4; sn = "SARADC_B_ECDR249"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR250 { address = 0xffe3c7b8; sn = "SARADC_B_ECDR250"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR251 { address = 0xffe3c7bc; sn = "SARADC_B_ECDR251"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR252 { address = 0xffe3c7c0; sn = "SARADC_B_ECDR252"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR253 { address = 0xffe3c7c4; sn = "SARADC_B_ECDR253"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR254 { address = 0xffe3c7c8; sn = "SARADC_B_ECDR254"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SARADC_B_ECDR255 { address = 0xffe3c7cc; sn = "SARADC_B_ECDR255"; access = "memorymapped"; width = 32; ${_DESC1964_}; type = "bitfield_SARADC_0_ECDR128" } SDADC_3_MCR { address = 0xfff10000; sn = "SDADC_3_MCR"; access = "memorymapped"; width = 32; ${_DESC1965_}; type = "bitfield_SDADC_3_MCR" } SDADC_3_CSR { address = 0xfff10004; sn = "SDADC_3_CSR"; access = "memorymapped"; width = 32; ${_DESC1980_}; type = "bitfield_SDADC_3_CSR" } SDADC_3_RKR { address = 0xfff10008; sn = "SDADC_3_RKR"; access = "memorymapped"; width = 32; ${_DESC1984_}; type = "bitfield_SDADC_3_RKR" } SDADC_3_SFR { address = 0xfff1000c; sn = "SDADC_3_SFR"; access = "memorymapped"; width = 32; ${_DESC1986_}; type = "bitfield_SDADC_3_SFR" } SDADC_3_RSER { address = 0xfff10010; sn = "SDADC_3_RSER"; access = "memorymapped"; width = 32; ${_DESC1994_}; type = "bitfield_SDADC_3_RSER" } SDADC_3_OSDR { address = 0xfff10014; sn = "SDADC_3_OSDR"; access = "memorymapped"; width = 32; ${_DESC2002_}; type = "bitfield_SDADC_3_OSDR" } SDADC_3_FCR { address = 0xfff10018; sn = "SDADC_3_FCR"; access = "memorymapped"; width = 32; ${_DESC2004_}; type = "bitfield_SDADC_3_FCR" } SDADC_3_STKR { address = 0xfff1001c; sn = "SDADC_3_STKR"; access = "memorymapped"; width = 32; ${_DESC2008_}; type = "bitfield_SDADC_3_STKR" } SDADC_3_CDR { address = 0xfff10020; sn = "SDADC_3_CDR"; access = "memorymapped"; width = 32; ${_DESC2010_}; type = "bitfield_SDADC_3_CDR" } SDADC_3_WTHHLR { address = 0xfff10024; sn = "SDADC_3_WTHHLR"; access = "memorymapped"; width = 32; ${_DESC2012_}; type = "bitfield_SDADC_3_WTHHLR" } SIPI_0_CCR0 { address = 0xfffd0000; sn = "SIPI_0_CCR0"; access = "memorymapped"; width = 32; ${_DESC2015_}; type = "bitfield_SIPI_0_CCR0" } SIPI_0_CSR0 { address = 0xfffd0004; sn = "SIPI_0_CSR0"; access = "memorymapped"; width = 32; ${_DESC2024_}; type = "bitfield_SIPI_0_CSR0" permission = "write/none" } SIPI_0_CIR0 { address = 0xfffd000c; sn = "SIPI_0_CIR0"; access = "memorymapped"; width = 32; ${_DESC2029_}; type = "bitfield_SIPI_0_CIR0" } SIPI_0_CTOR0 { address = 0xfffd0010; sn = "SIPI_0_CTOR0"; access = "memorymapped"; width = 32; ${_DESC2030_}; type = "bitfield_SIPI_0_CTOR0" } SIPI_0_CCRC0 { address = 0xfffd0014; sn = "SIPI_0_CCRC0"; access = "memorymapped"; width = 32; ${_DESC2032_}; type = "bitfield_SIPI_0_CCRC0" permission = "write/none" } SIPI_0_CAR0 { address = 0xfffd0018; sn = "SIPI_0_CAR0"; access = "memorymapped"; width = 32; ${_DESC2035_}; type = "bitfield_SIPI_0_CAR0" } SIPI_0_CDR0 { address = 0xfffd001c; sn = "SIPI_0_CDR0"; access = "memorymapped"; width = 32; ${_DESC2037_}; type = "bitfield_SIPI_0_CDR0" } SIPI_0_CCR1 { address = 0xfffd0020; sn = "SIPI_0_CCR1"; access = "memorymapped"; width = 32; ${_DESC2039_}; type = "bitfield_SIPI_0_CCR1" } SIPI_0_CSR1 { address = 0xfffd0024; sn = "SIPI_0_CSR1"; access = "memorymapped"; width = 32; ${_DESC2046_}; type = "bitfield_SIPI_0_CSR1" permission = "write/none" } SIPI_0_CIR1 { address = 0xfffd002c; sn = "SIPI_0_CIR1"; access = "memorymapped"; width = 32; ${_DESC2049_}; type = "bitfield_SIPI_0_CIR1" } SIPI_0_CTOR1 { address = 0xfffd0030; sn = "SIPI_0_CTOR1"; access = "memorymapped"; width = 32; ${_DESC2056_}; type = "bitfield_SIPI_0_CTOR0" } SIPI_0_CCRC1 { address = 0xfffd0034; sn = "SIPI_0_CCRC1"; access = "memorymapped"; width = 32; ${_DESC2057_}; type = "bitfield_SIPI_0_CCRC0" permission = "write/none" } SIPI_0_CAR1 { address = 0xfffd0038; sn = "SIPI_0_CAR1"; access = "memorymapped"; width = 32; ${_DESC2058_}; type = "bitfield_SIPI_0_CAR0" } SIPI_0_CDR1 { address = 0xfffd003c; sn = "SIPI_0_CDR1"; access = "memorymapped"; width = 32; ${_DESC2059_}; type = "bitfield_SIPI_0_CDR0" } SIPI_0_CCR2 { address = 0xfffd0040; sn = "SIPI_0_CCR2"; access = "memorymapped"; width = 32; ${_DESC2060_}; type = "bitfield_SIPI_0_CCR2" } SIPI_0_CSR2 { address = 0xfffd0044; sn = "SIPI_0_CSR2"; access = "memorymapped"; width = 32; ${_DESC2064_}; type = "bitfield_SIPI_0_CSR2" permission = "write/none" } SIPI_0_CIR2 { address = 0xfffd004c; sn = "SIPI_0_CIR2"; access = "memorymapped"; width = 32; ${_DESC2066_}; type = "bitfield_SIPI_0_CIR1" } SIPI_0_CTOR2 { address = 0xfffd0050; sn = "SIPI_0_CTOR2"; access = "memorymapped"; width = 32; ${_DESC2067_}; type = "bitfield_SIPI_0_CTOR2" } SIPI_0_CCRC2 { address = 0xfffd0054; sn = "SIPI_0_CCRC2"; access = "memorymapped"; width = 32; ${_DESC2069_}; type = "bitfield_SIPI_0_CCRC0" permission = "write/none" } SIPI_0_CAR2 { address = 0xfffd0058; sn = "SIPI_0_CAR2"; access = "memorymapped"; width = 32; ${_DESC2070_}; type = "bitfield_SIPI_0_CAR0" } SIPI_0_CDR2_0 { address = 0xfffd005c; sn = "SIPI_0_CDR2_0"; access = "memorymapped"; width = 32; ${_DESC2071_}; type = "bitfield_SIPI_0_CDR2_0" } SIPI_0_CDR2_1 { address = 0xfffd0060; sn = "SIPI_0_CDR2_1"; access = "memorymapped"; width = 32; ${_DESC2071_}; type = "bitfield_SIPI_0_CDR2_0" } SIPI_0_CDR2_2 { address = 0xfffd0064; sn = "SIPI_0_CDR2_2"; access = "memorymapped"; width = 32; ${_DESC2071_}; type = "bitfield_SIPI_0_CDR2_0" } SIPI_0_CDR2_3 { address = 0xfffd0068; sn = "SIPI_0_CDR2_3"; access = "memorymapped"; width = 32; ${_DESC2071_}; type = "bitfield_SIPI_0_CDR2_0" } SIPI_0_CDR2_4 { address = 0xfffd006c; sn = "SIPI_0_CDR2_4"; access = "memorymapped"; width = 32; ${_DESC2071_}; type = "bitfield_SIPI_0_CDR2_0" } SIPI_0_CDR2_5 { address = 0xfffd0070; sn = "SIPI_0_CDR2_5"; access = "memorymapped"; width = 32; ${_DESC2071_}; type = "bitfield_SIPI_0_CDR2_0" } SIPI_0_CDR2_6 { address = 0xfffd0074; sn = "SIPI_0_CDR2_6"; access = "memorymapped"; width = 32; ${_DESC2071_}; type = "bitfield_SIPI_0_CDR2_0" } SIPI_0_CDR2_7 { address = 0xfffd0078; sn = "SIPI_0_CDR2_7"; access = "memorymapped"; width = 32; ${_DESC2071_}; type = "bitfield_SIPI_0_CDR2_0" } SIPI_0_CCR3 { address = 0xfffd007c; sn = "SIPI_0_CCR3"; access = "memorymapped"; width = 32; ${_DESC2072_}; type = "bitfield_SIPI_0_CCR3" } SIPI_0_CSR3 { address = 0xfffd0080; sn = "SIPI_0_CSR3"; access = "memorymapped"; width = 32; ${_DESC2078_}; type = "bitfield_SIPI_0_CSR3" permission = "write/none" } SIPI_0_CIR3 { address = 0xfffd0088; sn = "SIPI_0_CIR3"; access = "memorymapped"; width = 32; ${_DESC2080_}; type = "bitfield_SIPI_0_CIR1" } SIPI_0_CTOR3 { address = 0xfffd008c; sn = "SIPI_0_CTOR3"; access = "memorymapped"; width = 32; ${_DESC2081_}; type = "bitfield_SIPI_0_CTOR3" } SIPI_0_CCRC3 { address = 0xfffd0090; sn = "SIPI_0_CCRC3"; access = "memorymapped"; width = 32; ${_DESC2083_}; type = "bitfield_SIPI_0_CCRC0" permission = "write/none" } SIPI_0_CAR3 { address = 0xfffd0094; sn = "SIPI_0_CAR3"; access = "memorymapped"; width = 32; ${_DESC2084_}; type = "bitfield_SIPI_0_CAR0" } SIPI_0_CDR3 { address = 0xfffd0098; sn = "SIPI_0_CDR3"; access = "memorymapped"; width = 32; ${_DESC2085_}; type = "bitfield_SIPI_0_CDR0" } SIPI_0_MCR { address = 0xfffd009c; sn = "SIPI_0_MCR"; access = "memorymapped"; width = 32; ${_DESC2086_}; type = "bitfield_SIPI_0_MCR" } SIPI_0_SR { address = 0xfffd00a0; sn = "SIPI_0_SR"; access = "memorymapped"; width = 32; ${_DESC2096_}; type = "bitfield_SIPI_0_SR" permission = "write/none" } SIPI_0_MAXCR { address = 0xfffd00a4; sn = "SIPI_0_MAXCR"; access = "memorymapped"; width = 32; ${_DESC2103_}; type = "bitfield_SIPI_0_MAXCR" } SIPI_0_ARR { address = 0xfffd00a8; sn = "SIPI_0_ARR"; access = "memorymapped"; width = 32; ${_DESC2105_}; type = "bitfield_SIPI_0_ARR" } SIPI_0_ACR { address = 0xfffd00ac; sn = "SIPI_0_ACR"; access = "memorymapped"; width = 32; ${_DESC2107_}; type = "bitfield_SIPI_0_ACR" } SIPI_0_ERR { address = 0xfffd00b0; sn = "SIPI_0_ERR"; access = "memorymapped"; width = 32; ${_DESC2109_}; type = "bitfield_SIPI_0_ERR" permission = "write/none" } SIUL2_MIDR1 { address = 0xfffc0004; sn = "SIUL2_MIDR1"; access = "memorymapped"; width = 32; ${_DESC2122_}; type = "bitfield_SIUL2_MIDR1" permission = "write/none" } SIUL2_MIDR2 { address = 0xfffc0008; sn = "SIUL2_MIDR2"; access = "memorymapped"; width = 32; ${_DESC2127_}; type = "bitfield_SIUL2_MIDR2" permission = "write/none" } SIUL2_DISR0 { address = 0xfffc0010; sn = "SIUL2_DISR0"; access = "memorymapped"; width = 32; ${_DESC2132_}; type = "bitfield_SIUL2_DISR0" } SIUL2_DIRER0 { address = 0xfffc0018; sn = "SIUL2_DIRER0"; access = "memorymapped"; width = 32; ${_DESC2134_}; type = "bitfield_SIUL2_DIRER0" } SIUL2_DIRSR0 { address = 0xfffc0020; sn = "SIUL2_DIRSR0"; access = "memorymapped"; width = 32; ${_DESC2136_}; type = "bitfield_SIUL2_DIRSR0" } SIUL2_IREER0 { address = 0xfffc0028; sn = "SIUL2_IREER0"; access = "memorymapped"; width = 32; ${_DESC2138_}; type = "bitfield_SIUL2_IREER0" } SIUL2_IFEER0 { address = 0xfffc0030; sn = "SIUL2_IFEER0"; access = "memorymapped"; width = 32; ${_DESC2140_}; type = "bitfield_SIUL2_IFEER0" } SIUL2_IFER0 { address = 0xfffc0038; sn = "SIUL2_IFER0"; access = "memorymapped"; width = 32; ${_DESC2142_}; type = "bitfield_SIUL2_IFER0" } SIUL2_IFMCR0 { address = 0xfffc0040; sn = "SIUL2_IFMCR0"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR1 { address = 0xfffc0044; sn = "SIUL2_IFMCR1"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR2 { address = 0xfffc0048; sn = "SIUL2_IFMCR2"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR3 { address = 0xfffc004c; sn = "SIUL2_IFMCR3"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR4 { address = 0xfffc0050; sn = "SIUL2_IFMCR4"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR5 { address = 0xfffc0054; sn = "SIUL2_IFMCR5"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR6 { address = 0xfffc0058; sn = "SIUL2_IFMCR6"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR7 { address = 0xfffc005c; sn = "SIUL2_IFMCR7"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR8 { address = 0xfffc0060; sn = "SIUL2_IFMCR8"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR9 { address = 0xfffc0064; sn = "SIUL2_IFMCR9"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR10 { address = 0xfffc0068; sn = "SIUL2_IFMCR10"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR11 { address = 0xfffc006c; sn = "SIUL2_IFMCR11"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR12 { address = 0xfffc0070; sn = "SIUL2_IFMCR12"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR13 { address = 0xfffc0074; sn = "SIUL2_IFMCR13"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR14 { address = 0xfffc0078; sn = "SIUL2_IFMCR14"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR15 { address = 0xfffc007c; sn = "SIUL2_IFMCR15"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR16 { address = 0xfffc0080; sn = "SIUL2_IFMCR16"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR17 { address = 0xfffc0084; sn = "SIUL2_IFMCR17"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR18 { address = 0xfffc0088; sn = "SIUL2_IFMCR18"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR19 { address = 0xfffc008c; sn = "SIUL2_IFMCR19"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR20 { address = 0xfffc0090; sn = "SIUL2_IFMCR20"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR21 { address = 0xfffc0094; sn = "SIUL2_IFMCR21"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR22 { address = 0xfffc0098; sn = "SIUL2_IFMCR22"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR23 { address = 0xfffc009c; sn = "SIUL2_IFMCR23"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR24 { address = 0xfffc00a0; sn = "SIUL2_IFMCR24"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR25 { address = 0xfffc00a4; sn = "SIUL2_IFMCR25"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR26 { address = 0xfffc00a8; sn = "SIUL2_IFMCR26"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR27 { address = 0xfffc00ac; sn = "SIUL2_IFMCR27"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR28 { address = 0xfffc00b0; sn = "SIUL2_IFMCR28"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR29 { address = 0xfffc00b4; sn = "SIUL2_IFMCR29"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR30 { address = 0xfffc00b8; sn = "SIUL2_IFMCR30"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFMCR31 { address = 0xfffc00bc; sn = "SIUL2_IFMCR31"; access = "memorymapped"; width = 32; ${_DESC2144_}; type = "bitfield_SIUL2_IFMCR0" } SIUL2_IFCPR { address = 0xfffc00c0; sn = "SIUL2_IFCPR"; access = "memorymapped"; width = 32; ${_DESC2146_}; type = "bitfield_SIUL2_IFCPR" } SIUL2_MSCR_IO_0 { address = 0xfffc0240; sn = "SIUL2_MSCR_IO_0"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_1 { address = 0xfffc0244; sn = "SIUL2_MSCR_IO_1"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_2 { address = 0xfffc0248; sn = "SIUL2_MSCR_IO_2"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_3 { address = 0xfffc024c; sn = "SIUL2_MSCR_IO_3"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_4 { address = 0xfffc0250; sn = "SIUL2_MSCR_IO_4"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_5 { address = 0xfffc0254; sn = "SIUL2_MSCR_IO_5"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_6 { address = 0xfffc0258; sn = "SIUL2_MSCR_IO_6"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_7 { address = 0xfffc025c; sn = "SIUL2_MSCR_IO_7"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_8 { address = 0xfffc0260; sn = "SIUL2_MSCR_IO_8"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_9 { address = 0xfffc0264; sn = "SIUL2_MSCR_IO_9"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_10 { address = 0xfffc0268; sn = "SIUL2_MSCR_IO_10"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_11 { address = 0xfffc026c; sn = "SIUL2_MSCR_IO_11"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_12 { address = 0xfffc0270; sn = "SIUL2_MSCR_IO_12"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_13 { address = 0xfffc0274; sn = "SIUL2_MSCR_IO_13"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_14 { address = 0xfffc0278; sn = "SIUL2_MSCR_IO_14"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_15 { address = 0xfffc027c; sn = "SIUL2_MSCR_IO_15"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_16 { address = 0xfffc0280; sn = "SIUL2_MSCR_IO_16"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_17 { address = 0xfffc0284; sn = "SIUL2_MSCR_IO_17"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_18 { address = 0xfffc0288; sn = "SIUL2_MSCR_IO_18"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_19 { address = 0xfffc028c; sn = "SIUL2_MSCR_IO_19"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_20 { address = 0xfffc0290; sn = "SIUL2_MSCR_IO_20"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_21 { address = 0xfffc0294; sn = "SIUL2_MSCR_IO_21"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_22 { address = 0xfffc0298; sn = "SIUL2_MSCR_IO_22"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_23 { address = 0xfffc029c; sn = "SIUL2_MSCR_IO_23"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_24 { address = 0xfffc02a0; sn = "SIUL2_MSCR_IO_24"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_25 { address = 0xfffc02a4; sn = "SIUL2_MSCR_IO_25"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_26 { address = 0xfffc02a8; sn = "SIUL2_MSCR_IO_26"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_27 { address = 0xfffc02ac; sn = "SIUL2_MSCR_IO_27"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_28 { address = 0xfffc02b0; sn = "SIUL2_MSCR_IO_28"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_29 { address = 0xfffc02b4; sn = "SIUL2_MSCR_IO_29"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_30 { address = 0xfffc02b8; sn = "SIUL2_MSCR_IO_30"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_31 { address = 0xfffc02bc; sn = "SIUL2_MSCR_IO_31"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_32 { address = 0xfffc02c0; sn = "SIUL2_MSCR_IO_32"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_33 { address = 0xfffc02c4; sn = "SIUL2_MSCR_IO_33"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_34 { address = 0xfffc02c8; sn = "SIUL2_MSCR_IO_34"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_35 { address = 0xfffc02cc; sn = "SIUL2_MSCR_IO_35"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_36 { address = 0xfffc02d0; sn = "SIUL2_MSCR_IO_36"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_37 { address = 0xfffc02d4; sn = "SIUL2_MSCR_IO_37"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_38 { address = 0xfffc02d8; sn = "SIUL2_MSCR_IO_38"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_39 { address = 0xfffc02dc; sn = "SIUL2_MSCR_IO_39"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_40 { address = 0xfffc02e0; sn = "SIUL2_MSCR_IO_40"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_41 { address = 0xfffc02e4; sn = "SIUL2_MSCR_IO_41"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_42 { address = 0xfffc02e8; sn = "SIUL2_MSCR_IO_42"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_43 { address = 0xfffc02ec; sn = "SIUL2_MSCR_IO_43"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_44 { address = 0xfffc02f0; sn = "SIUL2_MSCR_IO_44"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_45 { address = 0xfffc02f4; sn = "SIUL2_MSCR_IO_45"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_46 { address = 0xfffc02f8; sn = "SIUL2_MSCR_IO_46"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_47 { address = 0xfffc02fc; sn = "SIUL2_MSCR_IO_47"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_48 { address = 0xfffc0300; sn = "SIUL2_MSCR_IO_48"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_49 { address = 0xfffc0304; sn = "SIUL2_MSCR_IO_49"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_50 { address = 0xfffc0308; sn = "SIUL2_MSCR_IO_50"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_51 { address = 0xfffc030c; sn = "SIUL2_MSCR_IO_51"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_52 { address = 0xfffc0310; sn = "SIUL2_MSCR_IO_52"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_53 { address = 0xfffc0314; sn = "SIUL2_MSCR_IO_53"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_54 { address = 0xfffc0318; sn = "SIUL2_MSCR_IO_54"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_55 { address = 0xfffc031c; sn = "SIUL2_MSCR_IO_55"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_56 { address = 0xfffc0320; sn = "SIUL2_MSCR_IO_56"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_57 { address = 0xfffc0324; sn = "SIUL2_MSCR_IO_57"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_58 { address = 0xfffc0328; sn = "SIUL2_MSCR_IO_58"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_59 { address = 0xfffc032c; sn = "SIUL2_MSCR_IO_59"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_60 { address = 0xfffc0330; sn = "SIUL2_MSCR_IO_60"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_61 { address = 0xfffc0334; sn = "SIUL2_MSCR_IO_61"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_62 { address = 0xfffc0338; sn = "SIUL2_MSCR_IO_62"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_63 { address = 0xfffc033c; sn = "SIUL2_MSCR_IO_63"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_64 { address = 0xfffc0340; sn = "SIUL2_MSCR_IO_64"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_65 { address = 0xfffc0344; sn = "SIUL2_MSCR_IO_65"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_66 { address = 0xfffc0348; sn = "SIUL2_MSCR_IO_66"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_67 { address = 0xfffc034c; sn = "SIUL2_MSCR_IO_67"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_68 { address = 0xfffc0350; sn = "SIUL2_MSCR_IO_68"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_69 { address = 0xfffc0354; sn = "SIUL2_MSCR_IO_69"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_70 { address = 0xfffc0358; sn = "SIUL2_MSCR_IO_70"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_71 { address = 0xfffc035c; sn = "SIUL2_MSCR_IO_71"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_72 { address = 0xfffc0360; sn = "SIUL2_MSCR_IO_72"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_73 { address = 0xfffc0364; sn = "SIUL2_MSCR_IO_73"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_74 { address = 0xfffc0368; sn = "SIUL2_MSCR_IO_74"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_75 { address = 0xfffc036c; sn = "SIUL2_MSCR_IO_75"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_76 { address = 0xfffc0370; sn = "SIUL2_MSCR_IO_76"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_77 { address = 0xfffc0374; sn = "SIUL2_MSCR_IO_77"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_78 { address = 0xfffc0378; sn = "SIUL2_MSCR_IO_78"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_79 { address = 0xfffc037c; sn = "SIUL2_MSCR_IO_79"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_80 { address = 0xfffc0380; sn = "SIUL2_MSCR_IO_80"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_81 { address = 0xfffc0384; sn = "SIUL2_MSCR_IO_81"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_82 { address = 0xfffc0388; sn = "SIUL2_MSCR_IO_82"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_83 { address = 0xfffc038c; sn = "SIUL2_MSCR_IO_83"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_84 { address = 0xfffc0390; sn = "SIUL2_MSCR_IO_84"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_85 { address = 0xfffc0394; sn = "SIUL2_MSCR_IO_85"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_86 { address = 0xfffc0398; sn = "SIUL2_MSCR_IO_86"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_87 { address = 0xfffc039c; sn = "SIUL2_MSCR_IO_87"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_88 { address = 0xfffc03a0; sn = "SIUL2_MSCR_IO_88"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_89 { address = 0xfffc03a4; sn = "SIUL2_MSCR_IO_89"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_90 { address = 0xfffc03a8; sn = "SIUL2_MSCR_IO_90"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_91 { address = 0xfffc03ac; sn = "SIUL2_MSCR_IO_91"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_92 { address = 0xfffc03b0; sn = "SIUL2_MSCR_IO_92"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_93 { address = 0xfffc03b4; sn = "SIUL2_MSCR_IO_93"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_94 { address = 0xfffc03b8; sn = "SIUL2_MSCR_IO_94"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_95 { address = 0xfffc03bc; sn = "SIUL2_MSCR_IO_95"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_96 { address = 0xfffc03c0; sn = "SIUL2_MSCR_IO_96"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_97 { address = 0xfffc03c4; sn = "SIUL2_MSCR_IO_97"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_98 { address = 0xfffc03c8; sn = "SIUL2_MSCR_IO_98"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_99 { address = 0xfffc03cc; sn = "SIUL2_MSCR_IO_99"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_100 { address = 0xfffc03d0; sn = "SIUL2_MSCR_IO_100"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_101 { address = 0xfffc03d4; sn = "SIUL2_MSCR_IO_101"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_102 { address = 0xfffc03d8; sn = "SIUL2_MSCR_IO_102"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_103 { address = 0xfffc03dc; sn = "SIUL2_MSCR_IO_103"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_104 { address = 0xfffc03e0; sn = "SIUL2_MSCR_IO_104"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_105 { address = 0xfffc03e4; sn = "SIUL2_MSCR_IO_105"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_106 { address = 0xfffc03e8; sn = "SIUL2_MSCR_IO_106"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_107 { address = 0xfffc03ec; sn = "SIUL2_MSCR_IO_107"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_108 { address = 0xfffc03f0; sn = "SIUL2_MSCR_IO_108"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_109 { address = 0xfffc03f4; sn = "SIUL2_MSCR_IO_109"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_110 { address = 0xfffc03f8; sn = "SIUL2_MSCR_IO_110"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_111 { address = 0xfffc03fc; sn = "SIUL2_MSCR_IO_111"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_112 { address = 0xfffc0400; sn = "SIUL2_MSCR_IO_112"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_113 { address = 0xfffc0404; sn = "SIUL2_MSCR_IO_113"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_114 { address = 0xfffc0408; sn = "SIUL2_MSCR_IO_114"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_115 { address = 0xfffc040c; sn = "SIUL2_MSCR_IO_115"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_116 { address = 0xfffc0410; sn = "SIUL2_MSCR_IO_116"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_117 { address = 0xfffc0414; sn = "SIUL2_MSCR_IO_117"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_118 { address = 0xfffc0418; sn = "SIUL2_MSCR_IO_118"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_119 { address = 0xfffc041c; sn = "SIUL2_MSCR_IO_119"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_120 { address = 0xfffc0420; sn = "SIUL2_MSCR_IO_120"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_121 { address = 0xfffc0424; sn = "SIUL2_MSCR_IO_121"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_122 { address = 0xfffc0428; sn = "SIUL2_MSCR_IO_122"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_123 { address = 0xfffc042c; sn = "SIUL2_MSCR_IO_123"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_124 { address = 0xfffc0430; sn = "SIUL2_MSCR_IO_124"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_125 { address = 0xfffc0434; sn = "SIUL2_MSCR_IO_125"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_126 { address = 0xfffc0438; sn = "SIUL2_MSCR_IO_126"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_127 { address = 0xfffc043c; sn = "SIUL2_MSCR_IO_127"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_128 { address = 0xfffc0440; sn = "SIUL2_MSCR_IO_128"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_129 { address = 0xfffc0444; sn = "SIUL2_MSCR_IO_129"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_130 { address = 0xfffc0448; sn = "SIUL2_MSCR_IO_130"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_131 { address = 0xfffc044c; sn = "SIUL2_MSCR_IO_131"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_132 { address = 0xfffc0450; sn = "SIUL2_MSCR_IO_132"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_133 { address = 0xfffc0454; sn = "SIUL2_MSCR_IO_133"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_134 { address = 0xfffc0458; sn = "SIUL2_MSCR_IO_134"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_135 { address = 0xfffc045c; sn = "SIUL2_MSCR_IO_135"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_136 { address = 0xfffc0460; sn = "SIUL2_MSCR_IO_136"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_137 { address = 0xfffc0464; sn = "SIUL2_MSCR_IO_137"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_138 { address = 0xfffc0468; sn = "SIUL2_MSCR_IO_138"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_139 { address = 0xfffc046c; sn = "SIUL2_MSCR_IO_139"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_140 { address = 0xfffc0470; sn = "SIUL2_MSCR_IO_140"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_141 { address = 0xfffc0474; sn = "SIUL2_MSCR_IO_141"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_142 { address = 0xfffc0478; sn = "SIUL2_MSCR_IO_142"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_143 { address = 0xfffc047c; sn = "SIUL2_MSCR_IO_143"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_144 { address = 0xfffc0480; sn = "SIUL2_MSCR_IO_144"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_145 { address = 0xfffc0484; sn = "SIUL2_MSCR_IO_145"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_146 { address = 0xfffc0488; sn = "SIUL2_MSCR_IO_146"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_147 { address = 0xfffc048c; sn = "SIUL2_MSCR_IO_147"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_148 { address = 0xfffc0490; sn = "SIUL2_MSCR_IO_148"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_149 { address = 0xfffc0494; sn = "SIUL2_MSCR_IO_149"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_150 { address = 0xfffc0498; sn = "SIUL2_MSCR_IO_150"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_151 { address = 0xfffc049c; sn = "SIUL2_MSCR_IO_151"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_152 { address = 0xfffc04a0; sn = "SIUL2_MSCR_IO_152"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_153 { address = 0xfffc04a4; sn = "SIUL2_MSCR_IO_153"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_154 { address = 0xfffc04a8; sn = "SIUL2_MSCR_IO_154"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_155 { address = 0xfffc04ac; sn = "SIUL2_MSCR_IO_155"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_156 { address = 0xfffc04b0; sn = "SIUL2_MSCR_IO_156"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_157 { address = 0xfffc04b4; sn = "SIUL2_MSCR_IO_157"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_158 { address = 0xfffc04b8; sn = "SIUL2_MSCR_IO_158"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_159 { address = 0xfffc04bc; sn = "SIUL2_MSCR_IO_159"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_160 { address = 0xfffc04c0; sn = "SIUL2_MSCR_IO_160"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_161 { address = 0xfffc04c4; sn = "SIUL2_MSCR_IO_161"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_162 { address = 0xfffc04c8; sn = "SIUL2_MSCR_IO_162"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_163 { address = 0xfffc04cc; sn = "SIUL2_MSCR_IO_163"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_164 { address = 0xfffc04d0; sn = "SIUL2_MSCR_IO_164"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_165 { address = 0xfffc04d4; sn = "SIUL2_MSCR_IO_165"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_166 { address = 0xfffc04d8; sn = "SIUL2_MSCR_IO_166"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_167 { address = 0xfffc04dc; sn = "SIUL2_MSCR_IO_167"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_168 { address = 0xfffc04e0; sn = "SIUL2_MSCR_IO_168"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_169 { address = 0xfffc04e4; sn = "SIUL2_MSCR_IO_169"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_170 { address = 0xfffc04e8; sn = "SIUL2_MSCR_IO_170"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_171 { address = 0xfffc04ec; sn = "SIUL2_MSCR_IO_171"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_172 { address = 0xfffc04f0; sn = "SIUL2_MSCR_IO_172"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_173 { address = 0xfffc04f4; sn = "SIUL2_MSCR_IO_173"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_174 { address = 0xfffc04f8; sn = "SIUL2_MSCR_IO_174"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_175 { address = 0xfffc04fc; sn = "SIUL2_MSCR_IO_175"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_176 { address = 0xfffc0500; sn = "SIUL2_MSCR_IO_176"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_177 { address = 0xfffc0504; sn = "SIUL2_MSCR_IO_177"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_178 { address = 0xfffc0508; sn = "SIUL2_MSCR_IO_178"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_179 { address = 0xfffc050c; sn = "SIUL2_MSCR_IO_179"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_180 { address = 0xfffc0510; sn = "SIUL2_MSCR_IO_180"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_181 { address = 0xfffc0514; sn = "SIUL2_MSCR_IO_181"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_182 { address = 0xfffc0518; sn = "SIUL2_MSCR_IO_182"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_183 { address = 0xfffc051c; sn = "SIUL2_MSCR_IO_183"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_184 { address = 0xfffc0520; sn = "SIUL2_MSCR_IO_184"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_185 { address = 0xfffc0524; sn = "SIUL2_MSCR_IO_185"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_186 { address = 0xfffc0528; sn = "SIUL2_MSCR_IO_186"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_187 { address = 0xfffc052c; sn = "SIUL2_MSCR_IO_187"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_188 { address = 0xfffc0530; sn = "SIUL2_MSCR_IO_188"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_189 { address = 0xfffc0534; sn = "SIUL2_MSCR_IO_189"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_190 { address = 0xfffc0538; sn = "SIUL2_MSCR_IO_190"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_191 { address = 0xfffc053c; sn = "SIUL2_MSCR_IO_191"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_192 { address = 0xfffc0540; sn = "SIUL2_MSCR_IO_192"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_193 { address = 0xfffc0544; sn = "SIUL2_MSCR_IO_193"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_194 { address = 0xfffc0548; sn = "SIUL2_MSCR_IO_194"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_195 { address = 0xfffc054c; sn = "SIUL2_MSCR_IO_195"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_196 { address = 0xfffc0550; sn = "SIUL2_MSCR_IO_196"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_197 { address = 0xfffc0554; sn = "SIUL2_MSCR_IO_197"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_198 { address = 0xfffc0558; sn = "SIUL2_MSCR_IO_198"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_199 { address = 0xfffc055c; sn = "SIUL2_MSCR_IO_199"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_200 { address = 0xfffc0560; sn = "SIUL2_MSCR_IO_200"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_201 { address = 0xfffc0564; sn = "SIUL2_MSCR_IO_201"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_202 { address = 0xfffc0568; sn = "SIUL2_MSCR_IO_202"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_203 { address = 0xfffc056c; sn = "SIUL2_MSCR_IO_203"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_204 { address = 0xfffc0570; sn = "SIUL2_MSCR_IO_204"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_205 { address = 0xfffc0574; sn = "SIUL2_MSCR_IO_205"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_206 { address = 0xfffc0578; sn = "SIUL2_MSCR_IO_206"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_207 { address = 0xfffc057c; sn = "SIUL2_MSCR_IO_207"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_208 { address = 0xfffc0580; sn = "SIUL2_MSCR_IO_208"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_209 { address = 0xfffc0584; sn = "SIUL2_MSCR_IO_209"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_210 { address = 0xfffc0588; sn = "SIUL2_MSCR_IO_210"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_211 { address = 0xfffc058c; sn = "SIUL2_MSCR_IO_211"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_212 { address = 0xfffc0590; sn = "SIUL2_MSCR_IO_212"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_213 { address = 0xfffc0594; sn = "SIUL2_MSCR_IO_213"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_214 { address = 0xfffc0598; sn = "SIUL2_MSCR_IO_214"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_215 { address = 0xfffc059c; sn = "SIUL2_MSCR_IO_215"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_216 { address = 0xfffc05a0; sn = "SIUL2_MSCR_IO_216"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_217 { address = 0xfffc05a4; sn = "SIUL2_MSCR_IO_217"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_218 { address = 0xfffc05a8; sn = "SIUL2_MSCR_IO_218"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_219 { address = 0xfffc05ac; sn = "SIUL2_MSCR_IO_219"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_220 { address = 0xfffc05b0; sn = "SIUL2_MSCR_IO_220"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_221 { address = 0xfffc05b4; sn = "SIUL2_MSCR_IO_221"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_222 { address = 0xfffc05b8; sn = "SIUL2_MSCR_IO_222"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_223 { address = 0xfffc05bc; sn = "SIUL2_MSCR_IO_223"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_224 { address = 0xfffc05c0; sn = "SIUL2_MSCR_IO_224"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_225 { address = 0xfffc05c4; sn = "SIUL2_MSCR_IO_225"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_226 { address = 0xfffc05c8; sn = "SIUL2_MSCR_IO_226"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_227 { address = 0xfffc05cc; sn = "SIUL2_MSCR_IO_227"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_228 { address = 0xfffc05d0; sn = "SIUL2_MSCR_IO_228"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_229 { address = 0xfffc05d4; sn = "SIUL2_MSCR_IO_229"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_230 { address = 0xfffc05d8; sn = "SIUL2_MSCR_IO_230"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_231 { address = 0xfffc05dc; sn = "SIUL2_MSCR_IO_231"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_232 { address = 0xfffc05e0; sn = "SIUL2_MSCR_IO_232"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_233 { address = 0xfffc05e4; sn = "SIUL2_MSCR_IO_233"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_234 { address = 0xfffc05e8; sn = "SIUL2_MSCR_IO_234"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_235 { address = 0xfffc05ec; sn = "SIUL2_MSCR_IO_235"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_236 { address = 0xfffc05f0; sn = "SIUL2_MSCR_IO_236"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_237 { address = 0xfffc05f4; sn = "SIUL2_MSCR_IO_237"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_238 { address = 0xfffc05f8; sn = "SIUL2_MSCR_IO_238"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_239 { address = 0xfffc05fc; sn = "SIUL2_MSCR_IO_239"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_240 { address = 0xfffc0600; sn = "SIUL2_MSCR_IO_240"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_241 { address = 0xfffc0604; sn = "SIUL2_MSCR_IO_241"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_242 { address = 0xfffc0608; sn = "SIUL2_MSCR_IO_242"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_243 { address = 0xfffc060c; sn = "SIUL2_MSCR_IO_243"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_244 { address = 0xfffc0610; sn = "SIUL2_MSCR_IO_244"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_245 { address = 0xfffc0614; sn = "SIUL2_MSCR_IO_245"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_246 { address = 0xfffc0618; sn = "SIUL2_MSCR_IO_246"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_247 { address = 0xfffc061c; sn = "SIUL2_MSCR_IO_247"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_248 { address = 0xfffc0620; sn = "SIUL2_MSCR_IO_248"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_249 { address = 0xfffc0624; sn = "SIUL2_MSCR_IO_249"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_250 { address = 0xfffc0628; sn = "SIUL2_MSCR_IO_250"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_251 { address = 0xfffc062c; sn = "SIUL2_MSCR_IO_251"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_252 { address = 0xfffc0630; sn = "SIUL2_MSCR_IO_252"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_253 { address = 0xfffc0634; sn = "SIUL2_MSCR_IO_253"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_254 { address = 0xfffc0638; sn = "SIUL2_MSCR_IO_254"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_255 { address = 0xfffc063c; sn = "SIUL2_MSCR_IO_255"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_256 { address = 0xfffc0640; sn = "SIUL2_MSCR_IO_256"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_257 { address = 0xfffc0644; sn = "SIUL2_MSCR_IO_257"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_258 { address = 0xfffc0648; sn = "SIUL2_MSCR_IO_258"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_259 { address = 0xfffc064c; sn = "SIUL2_MSCR_IO_259"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_260 { address = 0xfffc0650; sn = "SIUL2_MSCR_IO_260"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_261 { address = 0xfffc0654; sn = "SIUL2_MSCR_IO_261"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_262 { address = 0xfffc0658; sn = "SIUL2_MSCR_IO_262"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_263 { address = 0xfffc065c; sn = "SIUL2_MSCR_IO_263"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_264 { address = 0xfffc0660; sn = "SIUL2_MSCR_IO_264"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_265 { address = 0xfffc0664; sn = "SIUL2_MSCR_IO_265"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_266 { address = 0xfffc0668; sn = "SIUL2_MSCR_IO_266"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_267 { address = 0xfffc066c; sn = "SIUL2_MSCR_IO_267"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_268 { address = 0xfffc0670; sn = "SIUL2_MSCR_IO_268"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_269 { address = 0xfffc0674; sn = "SIUL2_MSCR_IO_269"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_270 { address = 0xfffc0678; sn = "SIUL2_MSCR_IO_270"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_271 { address = 0xfffc067c; sn = "SIUL2_MSCR_IO_271"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_272 { address = 0xfffc0680; sn = "SIUL2_MSCR_IO_272"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_273 { address = 0xfffc0684; sn = "SIUL2_MSCR_IO_273"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_274 { address = 0xfffc0688; sn = "SIUL2_MSCR_IO_274"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_275 { address = 0xfffc068c; sn = "SIUL2_MSCR_IO_275"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_276 { address = 0xfffc0690; sn = "SIUL2_MSCR_IO_276"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_277 { address = 0xfffc0694; sn = "SIUL2_MSCR_IO_277"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_278 { address = 0xfffc0698; sn = "SIUL2_MSCR_IO_278"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_279 { address = 0xfffc069c; sn = "SIUL2_MSCR_IO_279"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_280 { address = 0xfffc06a0; sn = "SIUL2_MSCR_IO_280"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_281 { address = 0xfffc06a4; sn = "SIUL2_MSCR_IO_281"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_282 { address = 0xfffc06a8; sn = "SIUL2_MSCR_IO_282"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_283 { address = 0xfffc06ac; sn = "SIUL2_MSCR_IO_283"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_284 { address = 0xfffc06b0; sn = "SIUL2_MSCR_IO_284"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_285 { address = 0xfffc06b4; sn = "SIUL2_MSCR_IO_285"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_286 { address = 0xfffc06b8; sn = "SIUL2_MSCR_IO_286"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_287 { address = 0xfffc06bc; sn = "SIUL2_MSCR_IO_287"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_288 { address = 0xfffc06c0; sn = "SIUL2_MSCR_IO_288"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_289 { address = 0xfffc06c4; sn = "SIUL2_MSCR_IO_289"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_290 { address = 0xfffc06c8; sn = "SIUL2_MSCR_IO_290"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_291 { address = 0xfffc06cc; sn = "SIUL2_MSCR_IO_291"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_292 { address = 0xfffc06d0; sn = "SIUL2_MSCR_IO_292"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_293 { address = 0xfffc06d4; sn = "SIUL2_MSCR_IO_293"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_294 { address = 0xfffc06d8; sn = "SIUL2_MSCR_IO_294"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_295 { address = 0xfffc06dc; sn = "SIUL2_MSCR_IO_295"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_296 { address = 0xfffc06e0; sn = "SIUL2_MSCR_IO_296"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_297 { address = 0xfffc06e4; sn = "SIUL2_MSCR_IO_297"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_298 { address = 0xfffc06e8; sn = "SIUL2_MSCR_IO_298"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_299 { address = 0xfffc06ec; sn = "SIUL2_MSCR_IO_299"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_300 { address = 0xfffc06f0; sn = "SIUL2_MSCR_IO_300"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_301 { address = 0xfffc06f4; sn = "SIUL2_MSCR_IO_301"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_302 { address = 0xfffc06f8; sn = "SIUL2_MSCR_IO_302"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_303 { address = 0xfffc06fc; sn = "SIUL2_MSCR_IO_303"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_304 { address = 0xfffc0700; sn = "SIUL2_MSCR_IO_304"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_305 { address = 0xfffc0704; sn = "SIUL2_MSCR_IO_305"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_306 { address = 0xfffc0708; sn = "SIUL2_MSCR_IO_306"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_307 { address = 0xfffc070c; sn = "SIUL2_MSCR_IO_307"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_308 { address = 0xfffc0710; sn = "SIUL2_MSCR_IO_308"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_309 { address = 0xfffc0714; sn = "SIUL2_MSCR_IO_309"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_310 { address = 0xfffc0718; sn = "SIUL2_MSCR_IO_310"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_311 { address = 0xfffc071c; sn = "SIUL2_MSCR_IO_311"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_312 { address = 0xfffc0720; sn = "SIUL2_MSCR_IO_312"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_313 { address = 0xfffc0724; sn = "SIUL2_MSCR_IO_313"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_314 { address = 0xfffc0728; sn = "SIUL2_MSCR_IO_314"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_315 { address = 0xfffc072c; sn = "SIUL2_MSCR_IO_315"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_316 { address = 0xfffc0730; sn = "SIUL2_MSCR_IO_316"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_317 { address = 0xfffc0734; sn = "SIUL2_MSCR_IO_317"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_318 { address = 0xfffc0738; sn = "SIUL2_MSCR_IO_318"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_319 { address = 0xfffc073c; sn = "SIUL2_MSCR_IO_319"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_320 { address = 0xfffc0740; sn = "SIUL2_MSCR_IO_320"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_321 { address = 0xfffc0744; sn = "SIUL2_MSCR_IO_321"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_322 { address = 0xfffc0748; sn = "SIUL2_MSCR_IO_322"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_323 { address = 0xfffc074c; sn = "SIUL2_MSCR_IO_323"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_324 { address = 0xfffc0750; sn = "SIUL2_MSCR_IO_324"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_325 { address = 0xfffc0754; sn = "SIUL2_MSCR_IO_325"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_326 { address = 0xfffc0758; sn = "SIUL2_MSCR_IO_326"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_327 { address = 0xfffc075c; sn = "SIUL2_MSCR_IO_327"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_328 { address = 0xfffc0760; sn = "SIUL2_MSCR_IO_328"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_329 { address = 0xfffc0764; sn = "SIUL2_MSCR_IO_329"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_330 { address = 0xfffc0768; sn = "SIUL2_MSCR_IO_330"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_331 { address = 0xfffc076c; sn = "SIUL2_MSCR_IO_331"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_332 { address = 0xfffc0770; sn = "SIUL2_MSCR_IO_332"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_333 { address = 0xfffc0774; sn = "SIUL2_MSCR_IO_333"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_334 { address = 0xfffc0778; sn = "SIUL2_MSCR_IO_334"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_335 { address = 0xfffc077c; sn = "SIUL2_MSCR_IO_335"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_336 { address = 0xfffc0780; sn = "SIUL2_MSCR_IO_336"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_337 { address = 0xfffc0784; sn = "SIUL2_MSCR_IO_337"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_338 { address = 0xfffc0788; sn = "SIUL2_MSCR_IO_338"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_339 { address = 0xfffc078c; sn = "SIUL2_MSCR_IO_339"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_340 { address = 0xfffc0790; sn = "SIUL2_MSCR_IO_340"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_341 { address = 0xfffc0794; sn = "SIUL2_MSCR_IO_341"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_342 { address = 0xfffc0798; sn = "SIUL2_MSCR_IO_342"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_343 { address = 0xfffc079c; sn = "SIUL2_MSCR_IO_343"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_344 { address = 0xfffc07a0; sn = "SIUL2_MSCR_IO_344"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_345 { address = 0xfffc07a4; sn = "SIUL2_MSCR_IO_345"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_346 { address = 0xfffc07a8; sn = "SIUL2_MSCR_IO_346"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_347 { address = 0xfffc07ac; sn = "SIUL2_MSCR_IO_347"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_348 { address = 0xfffc07b0; sn = "SIUL2_MSCR_IO_348"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_349 { address = 0xfffc07b4; sn = "SIUL2_MSCR_IO_349"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_350 { address = 0xfffc07b8; sn = "SIUL2_MSCR_IO_350"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_351 { address = 0xfffc07bc; sn = "SIUL2_MSCR_IO_351"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_352 { address = 0xfffc07c0; sn = "SIUL2_MSCR_IO_352"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_353 { address = 0xfffc07c4; sn = "SIUL2_MSCR_IO_353"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_354 { address = 0xfffc07c8; sn = "SIUL2_MSCR_IO_354"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_355 { address = 0xfffc07cc; sn = "SIUL2_MSCR_IO_355"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_356 { address = 0xfffc07d0; sn = "SIUL2_MSCR_IO_356"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_357 { address = 0xfffc07d4; sn = "SIUL2_MSCR_IO_357"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_358 { address = 0xfffc07d8; sn = "SIUL2_MSCR_IO_358"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_359 { address = 0xfffc07dc; sn = "SIUL2_MSCR_IO_359"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_360 { address = 0xfffc07e0; sn = "SIUL2_MSCR_IO_360"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_361 { address = 0xfffc07e4; sn = "SIUL2_MSCR_IO_361"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_362 { address = 0xfffc07e8; sn = "SIUL2_MSCR_IO_362"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_363 { address = 0xfffc07ec; sn = "SIUL2_MSCR_IO_363"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_364 { address = 0xfffc07f0; sn = "SIUL2_MSCR_IO_364"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_365 { address = 0xfffc07f4; sn = "SIUL2_MSCR_IO_365"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_366 { address = 0xfffc07f8; sn = "SIUL2_MSCR_IO_366"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_367 { address = 0xfffc07fc; sn = "SIUL2_MSCR_IO_367"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_368 { address = 0xfffc0800; sn = "SIUL2_MSCR_IO_368"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_369 { address = 0xfffc0804; sn = "SIUL2_MSCR_IO_369"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_370 { address = 0xfffc0808; sn = "SIUL2_MSCR_IO_370"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_371 { address = 0xfffc080c; sn = "SIUL2_MSCR_IO_371"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_372 { address = 0xfffc0810; sn = "SIUL2_MSCR_IO_372"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_373 { address = 0xfffc0814; sn = "SIUL2_MSCR_IO_373"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_374 { address = 0xfffc0818; sn = "SIUL2_MSCR_IO_374"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_375 { address = 0xfffc081c; sn = "SIUL2_MSCR_IO_375"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_376 { address = 0xfffc0820; sn = "SIUL2_MSCR_IO_376"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_377 { address = 0xfffc0824; sn = "SIUL2_MSCR_IO_377"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_378 { address = 0xfffc0828; sn = "SIUL2_MSCR_IO_378"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_379 { address = 0xfffc082c; sn = "SIUL2_MSCR_IO_379"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_380 { address = 0xfffc0830; sn = "SIUL2_MSCR_IO_380"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_381 { address = 0xfffc0834; sn = "SIUL2_MSCR_IO_381"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_382 { address = 0xfffc0838; sn = "SIUL2_MSCR_IO_382"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_383 { address = 0xfffc083c; sn = "SIUL2_MSCR_IO_383"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_384 { address = 0xfffc0840; sn = "SIUL2_MSCR_IO_384"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_385 { address = 0xfffc0844; sn = "SIUL2_MSCR_IO_385"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_386 { address = 0xfffc0848; sn = "SIUL2_MSCR_IO_386"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_387 { address = 0xfffc084c; sn = "SIUL2_MSCR_IO_387"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_388 { address = 0xfffc0850; sn = "SIUL2_MSCR_IO_388"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_389 { address = 0xfffc0854; sn = "SIUL2_MSCR_IO_389"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_390 { address = 0xfffc0858; sn = "SIUL2_MSCR_IO_390"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_391 { address = 0xfffc085c; sn = "SIUL2_MSCR_IO_391"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_392 { address = 0xfffc0860; sn = "SIUL2_MSCR_IO_392"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_393 { address = 0xfffc0864; sn = "SIUL2_MSCR_IO_393"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_394 { address = 0xfffc0868; sn = "SIUL2_MSCR_IO_394"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_395 { address = 0xfffc086c; sn = "SIUL2_MSCR_IO_395"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_396 { address = 0xfffc0870; sn = "SIUL2_MSCR_IO_396"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_397 { address = 0xfffc0874; sn = "SIUL2_MSCR_IO_397"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_398 { address = 0xfffc0878; sn = "SIUL2_MSCR_IO_398"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_399 { address = 0xfffc087c; sn = "SIUL2_MSCR_IO_399"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_400 { address = 0xfffc0880; sn = "SIUL2_MSCR_IO_400"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_401 { address = 0xfffc0884; sn = "SIUL2_MSCR_IO_401"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_402 { address = 0xfffc0888; sn = "SIUL2_MSCR_IO_402"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_403 { address = 0xfffc088c; sn = "SIUL2_MSCR_IO_403"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_404 { address = 0xfffc0890; sn = "SIUL2_MSCR_IO_404"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_405 { address = 0xfffc0894; sn = "SIUL2_MSCR_IO_405"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_406 { address = 0xfffc0898; sn = "SIUL2_MSCR_IO_406"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_407 { address = 0xfffc089c; sn = "SIUL2_MSCR_IO_407"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_408 { address = 0xfffc08a0; sn = "SIUL2_MSCR_IO_408"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_409 { address = 0xfffc08a4; sn = "SIUL2_MSCR_IO_409"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_410 { address = 0xfffc08a8; sn = "SIUL2_MSCR_IO_410"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_411 { address = 0xfffc08ac; sn = "SIUL2_MSCR_IO_411"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_412 { address = 0xfffc08b0; sn = "SIUL2_MSCR_IO_412"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_413 { address = 0xfffc08b4; sn = "SIUL2_MSCR_IO_413"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_414 { address = 0xfffc08b8; sn = "SIUL2_MSCR_IO_414"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_415 { address = 0xfffc08bc; sn = "SIUL2_MSCR_IO_415"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_416 { address = 0xfffc08c0; sn = "SIUL2_MSCR_IO_416"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_417 { address = 0xfffc08c4; sn = "SIUL2_MSCR_IO_417"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_418 { address = 0xfffc08c8; sn = "SIUL2_MSCR_IO_418"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_419 { address = 0xfffc08cc; sn = "SIUL2_MSCR_IO_419"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_420 { address = 0xfffc08d0; sn = "SIUL2_MSCR_IO_420"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_421 { address = 0xfffc08d4; sn = "SIUL2_MSCR_IO_421"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_422 { address = 0xfffc08d8; sn = "SIUL2_MSCR_IO_422"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_423 { address = 0xfffc08dc; sn = "SIUL2_MSCR_IO_423"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_424 { address = 0xfffc08e0; sn = "SIUL2_MSCR_IO_424"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_425 { address = 0xfffc08e4; sn = "SIUL2_MSCR_IO_425"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_426 { address = 0xfffc08e8; sn = "SIUL2_MSCR_IO_426"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_427 { address = 0xfffc08ec; sn = "SIUL2_MSCR_IO_427"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_428 { address = 0xfffc08f0; sn = "SIUL2_MSCR_IO_428"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_429 { address = 0xfffc08f4; sn = "SIUL2_MSCR_IO_429"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_430 { address = 0xfffc08f8; sn = "SIUL2_MSCR_IO_430"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_431 { address = 0xfffc08fc; sn = "SIUL2_MSCR_IO_431"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_432 { address = 0xfffc0900; sn = "SIUL2_MSCR_IO_432"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_433 { address = 0xfffc0904; sn = "SIUL2_MSCR_IO_433"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_434 { address = 0xfffc0908; sn = "SIUL2_MSCR_IO_434"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_435 { address = 0xfffc090c; sn = "SIUL2_MSCR_IO_435"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_436 { address = 0xfffc0910; sn = "SIUL2_MSCR_IO_436"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_437 { address = 0xfffc0914; sn = "SIUL2_MSCR_IO_437"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_438 { address = 0xfffc0918; sn = "SIUL2_MSCR_IO_438"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_439 { address = 0xfffc091c; sn = "SIUL2_MSCR_IO_439"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_440 { address = 0xfffc0920; sn = "SIUL2_MSCR_IO_440"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_441 { address = 0xfffc0924; sn = "SIUL2_MSCR_IO_441"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_442 { address = 0xfffc0928; sn = "SIUL2_MSCR_IO_442"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_443 { address = 0xfffc092c; sn = "SIUL2_MSCR_IO_443"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_444 { address = 0xfffc0930; sn = "SIUL2_MSCR_IO_444"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_445 { address = 0xfffc0934; sn = "SIUL2_MSCR_IO_445"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_446 { address = 0xfffc0938; sn = "SIUL2_MSCR_IO_446"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_447 { address = 0xfffc093c; sn = "SIUL2_MSCR_IO_447"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_448 { address = 0xfffc0940; sn = "SIUL2_MSCR_IO_448"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_449 { address = 0xfffc0944; sn = "SIUL2_MSCR_IO_449"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_450 { address = 0xfffc0948; sn = "SIUL2_MSCR_IO_450"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_451 { address = 0xfffc094c; sn = "SIUL2_MSCR_IO_451"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_452 { address = 0xfffc0950; sn = "SIUL2_MSCR_IO_452"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_453 { address = 0xfffc0954; sn = "SIUL2_MSCR_IO_453"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_454 { address = 0xfffc0958; sn = "SIUL2_MSCR_IO_454"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_455 { address = 0xfffc095c; sn = "SIUL2_MSCR_IO_455"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_456 { address = 0xfffc0960; sn = "SIUL2_MSCR_IO_456"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_457 { address = 0xfffc0964; sn = "SIUL2_MSCR_IO_457"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_458 { address = 0xfffc0968; sn = "SIUL2_MSCR_IO_458"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_459 { address = 0xfffc096c; sn = "SIUL2_MSCR_IO_459"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_460 { address = 0xfffc0970; sn = "SIUL2_MSCR_IO_460"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_461 { address = 0xfffc0974; sn = "SIUL2_MSCR_IO_461"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_462 { address = 0xfffc0978; sn = "SIUL2_MSCR_IO_462"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_463 { address = 0xfffc097c; sn = "SIUL2_MSCR_IO_463"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_464 { address = 0xfffc0980; sn = "SIUL2_MSCR_IO_464"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_465 { address = 0xfffc0984; sn = "SIUL2_MSCR_IO_465"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_466 { address = 0xfffc0988; sn = "SIUL2_MSCR_IO_466"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_467 { address = 0xfffc098c; sn = "SIUL2_MSCR_IO_467"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_468 { address = 0xfffc0990; sn = "SIUL2_MSCR_IO_468"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_469 { address = 0xfffc0994; sn = "SIUL2_MSCR_IO_469"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_470 { address = 0xfffc0998; sn = "SIUL2_MSCR_IO_470"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_471 { address = 0xfffc099c; sn = "SIUL2_MSCR_IO_471"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_472 { address = 0xfffc09a0; sn = "SIUL2_MSCR_IO_472"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_473 { address = 0xfffc09a4; sn = "SIUL2_MSCR_IO_473"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_474 { address = 0xfffc09a8; sn = "SIUL2_MSCR_IO_474"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_475 { address = 0xfffc09ac; sn = "SIUL2_MSCR_IO_475"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_476 { address = 0xfffc09b0; sn = "SIUL2_MSCR_IO_476"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_477 { address = 0xfffc09b4; sn = "SIUL2_MSCR_IO_477"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_478 { address = 0xfffc09b8; sn = "SIUL2_MSCR_IO_478"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_479 { address = 0xfffc09bc; sn = "SIUL2_MSCR_IO_479"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_480 { address = 0xfffc09c0; sn = "SIUL2_MSCR_IO_480"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_481 { address = 0xfffc09c4; sn = "SIUL2_MSCR_IO_481"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_482 { address = 0xfffc09c8; sn = "SIUL2_MSCR_IO_482"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_483 { address = 0xfffc09cc; sn = "SIUL2_MSCR_IO_483"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_484 { address = 0xfffc09d0; sn = "SIUL2_MSCR_IO_484"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_485 { address = 0xfffc09d4; sn = "SIUL2_MSCR_IO_485"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_486 { address = 0xfffc09d8; sn = "SIUL2_MSCR_IO_486"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_487 { address = 0xfffc09dc; sn = "SIUL2_MSCR_IO_487"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_488 { address = 0xfffc09e0; sn = "SIUL2_MSCR_IO_488"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_489 { address = 0xfffc09e4; sn = "SIUL2_MSCR_IO_489"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_490 { address = 0xfffc09e8; sn = "SIUL2_MSCR_IO_490"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_491 { address = 0xfffc09ec; sn = "SIUL2_MSCR_IO_491"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_492 { address = 0xfffc09f0; sn = "SIUL2_MSCR_IO_492"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_493 { address = 0xfffc09f4; sn = "SIUL2_MSCR_IO_493"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_494 { address = 0xfffc09f8; sn = "SIUL2_MSCR_IO_494"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_495 { address = 0xfffc09fc; sn = "SIUL2_MSCR_IO_495"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_496 { address = 0xfffc0a00; sn = "SIUL2_MSCR_IO_496"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_497 { address = 0xfffc0a04; sn = "SIUL2_MSCR_IO_497"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_498 { address = 0xfffc0a08; sn = "SIUL2_MSCR_IO_498"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_499 { address = 0xfffc0a0c; sn = "SIUL2_MSCR_IO_499"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_500 { address = 0xfffc0a10; sn = "SIUL2_MSCR_IO_500"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_501 { address = 0xfffc0a14; sn = "SIUL2_MSCR_IO_501"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_502 { address = 0xfffc0a18; sn = "SIUL2_MSCR_IO_502"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_503 { address = 0xfffc0a1c; sn = "SIUL2_MSCR_IO_503"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_504 { address = 0xfffc0a20; sn = "SIUL2_MSCR_IO_504"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_505 { address = 0xfffc0a24; sn = "SIUL2_MSCR_IO_505"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_506 { address = 0xfffc0a28; sn = "SIUL2_MSCR_IO_506"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_507 { address = 0xfffc0a2c; sn = "SIUL2_MSCR_IO_507"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_508 { address = 0xfffc0a30; sn = "SIUL2_MSCR_IO_508"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_509 { address = 0xfffc0a34; sn = "SIUL2_MSCR_IO_509"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_510 { address = 0xfffc0a38; sn = "SIUL2_MSCR_IO_510"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_IO_511 { address = 0xfffc0a3c; sn = "SIUL2_MSCR_IO_511"; access = "memorymapped"; width = 32; ${_DESC2148_}; type = "bitfield_SIUL2_MSCR_IO_0" } SIUL2_MSCR_MUX_512 { address = 0xfffc0a40; sn = "SIUL2_MSCR_MUX_512"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_513 { address = 0xfffc0a44; sn = "SIUL2_MSCR_MUX_513"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_514 { address = 0xfffc0a48; sn = "SIUL2_MSCR_MUX_514"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_515 { address = 0xfffc0a4c; sn = "SIUL2_MSCR_MUX_515"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_516 { address = 0xfffc0a50; sn = "SIUL2_MSCR_MUX_516"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_517 { address = 0xfffc0a54; sn = "SIUL2_MSCR_MUX_517"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_518 { address = 0xfffc0a58; sn = "SIUL2_MSCR_MUX_518"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_519 { address = 0xfffc0a5c; sn = "SIUL2_MSCR_MUX_519"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_520 { address = 0xfffc0a60; sn = "SIUL2_MSCR_MUX_520"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_521 { address = 0xfffc0a64; sn = "SIUL2_MSCR_MUX_521"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_522 { address = 0xfffc0a68; sn = "SIUL2_MSCR_MUX_522"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_523 { address = 0xfffc0a6c; sn = "SIUL2_MSCR_MUX_523"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_524 { address = 0xfffc0a70; sn = "SIUL2_MSCR_MUX_524"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_525 { address = 0xfffc0a74; sn = "SIUL2_MSCR_MUX_525"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_526 { address = 0xfffc0a78; sn = "SIUL2_MSCR_MUX_526"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_527 { address = 0xfffc0a7c; sn = "SIUL2_MSCR_MUX_527"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_528 { address = 0xfffc0a80; sn = "SIUL2_MSCR_MUX_528"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_529 { address = 0xfffc0a84; sn = "SIUL2_MSCR_MUX_529"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_530 { address = 0xfffc0a88; sn = "SIUL2_MSCR_MUX_530"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_531 { address = 0xfffc0a8c; sn = "SIUL2_MSCR_MUX_531"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_532 { address = 0xfffc0a90; sn = "SIUL2_MSCR_MUX_532"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_533 { address = 0xfffc0a94; sn = "SIUL2_MSCR_MUX_533"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_534 { address = 0xfffc0a98; sn = "SIUL2_MSCR_MUX_534"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_535 { address = 0xfffc0a9c; sn = "SIUL2_MSCR_MUX_535"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_536 { address = 0xfffc0aa0; sn = "SIUL2_MSCR_MUX_536"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_537 { address = 0xfffc0aa4; sn = "SIUL2_MSCR_MUX_537"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_538 { address = 0xfffc0aa8; sn = "SIUL2_MSCR_MUX_538"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_539 { address = 0xfffc0aac; sn = "SIUL2_MSCR_MUX_539"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_540 { address = 0xfffc0ab0; sn = "SIUL2_MSCR_MUX_540"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_541 { address = 0xfffc0ab4; sn = "SIUL2_MSCR_MUX_541"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_542 { address = 0xfffc0ab8; sn = "SIUL2_MSCR_MUX_542"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_543 { address = 0xfffc0abc; sn = "SIUL2_MSCR_MUX_543"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_544 { address = 0xfffc0ac0; sn = "SIUL2_MSCR_MUX_544"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_545 { address = 0xfffc0ac4; sn = "SIUL2_MSCR_MUX_545"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_546 { address = 0xfffc0ac8; sn = "SIUL2_MSCR_MUX_546"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_547 { address = 0xfffc0acc; sn = "SIUL2_MSCR_MUX_547"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_548 { address = 0xfffc0ad0; sn = "SIUL2_MSCR_MUX_548"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_549 { address = 0xfffc0ad4; sn = "SIUL2_MSCR_MUX_549"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_550 { address = 0xfffc0ad8; sn = "SIUL2_MSCR_MUX_550"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_551 { address = 0xfffc0adc; sn = "SIUL2_MSCR_MUX_551"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_552 { address = 0xfffc0ae0; sn = "SIUL2_MSCR_MUX_552"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_553 { address = 0xfffc0ae4; sn = "SIUL2_MSCR_MUX_553"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_554 { address = 0xfffc0ae8; sn = "SIUL2_MSCR_MUX_554"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_555 { address = 0xfffc0aec; sn = "SIUL2_MSCR_MUX_555"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_556 { address = 0xfffc0af0; sn = "SIUL2_MSCR_MUX_556"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_557 { address = 0xfffc0af4; sn = "SIUL2_MSCR_MUX_557"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_558 { address = 0xfffc0af8; sn = "SIUL2_MSCR_MUX_558"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_559 { address = 0xfffc0afc; sn = "SIUL2_MSCR_MUX_559"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_560 { address = 0xfffc0b00; sn = "SIUL2_MSCR_MUX_560"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_561 { address = 0xfffc0b04; sn = "SIUL2_MSCR_MUX_561"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_562 { address = 0xfffc0b08; sn = "SIUL2_MSCR_MUX_562"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_563 { address = 0xfffc0b0c; sn = "SIUL2_MSCR_MUX_563"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_564 { address = 0xfffc0b10; sn = "SIUL2_MSCR_MUX_564"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_565 { address = 0xfffc0b14; sn = "SIUL2_MSCR_MUX_565"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_566 { address = 0xfffc0b18; sn = "SIUL2_MSCR_MUX_566"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_567 { address = 0xfffc0b1c; sn = "SIUL2_MSCR_MUX_567"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_568 { address = 0xfffc0b20; sn = "SIUL2_MSCR_MUX_568"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_569 { address = 0xfffc0b24; sn = "SIUL2_MSCR_MUX_569"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_570 { address = 0xfffc0b28; sn = "SIUL2_MSCR_MUX_570"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_571 { address = 0xfffc0b2c; sn = "SIUL2_MSCR_MUX_571"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_572 { address = 0xfffc0b30; sn = "SIUL2_MSCR_MUX_572"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_573 { address = 0xfffc0b34; sn = "SIUL2_MSCR_MUX_573"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_574 { address = 0xfffc0b38; sn = "SIUL2_MSCR_MUX_574"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_575 { address = 0xfffc0b3c; sn = "SIUL2_MSCR_MUX_575"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_576 { address = 0xfffc0b40; sn = "SIUL2_MSCR_MUX_576"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_577 { address = 0xfffc0b44; sn = "SIUL2_MSCR_MUX_577"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_578 { address = 0xfffc0b48; sn = "SIUL2_MSCR_MUX_578"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_579 { address = 0xfffc0b4c; sn = "SIUL2_MSCR_MUX_579"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_580 { address = 0xfffc0b50; sn = "SIUL2_MSCR_MUX_580"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_581 { address = 0xfffc0b54; sn = "SIUL2_MSCR_MUX_581"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_582 { address = 0xfffc0b58; sn = "SIUL2_MSCR_MUX_582"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_583 { address = 0xfffc0b5c; sn = "SIUL2_MSCR_MUX_583"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_584 { address = 0xfffc0b60; sn = "SIUL2_MSCR_MUX_584"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_585 { address = 0xfffc0b64; sn = "SIUL2_MSCR_MUX_585"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_586 { address = 0xfffc0b68; sn = "SIUL2_MSCR_MUX_586"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_587 { address = 0xfffc0b6c; sn = "SIUL2_MSCR_MUX_587"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_588 { address = 0xfffc0b70; sn = "SIUL2_MSCR_MUX_588"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_589 { address = 0xfffc0b74; sn = "SIUL2_MSCR_MUX_589"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_590 { address = 0xfffc0b78; sn = "SIUL2_MSCR_MUX_590"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_591 { address = 0xfffc0b7c; sn = "SIUL2_MSCR_MUX_591"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_592 { address = 0xfffc0b80; sn = "SIUL2_MSCR_MUX_592"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_593 { address = 0xfffc0b84; sn = "SIUL2_MSCR_MUX_593"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_594 { address = 0xfffc0b88; sn = "SIUL2_MSCR_MUX_594"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_595 { address = 0xfffc0b8c; sn = "SIUL2_MSCR_MUX_595"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_596 { address = 0xfffc0b90; sn = "SIUL2_MSCR_MUX_596"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_597 { address = 0xfffc0b94; sn = "SIUL2_MSCR_MUX_597"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_598 { address = 0xfffc0b98; sn = "SIUL2_MSCR_MUX_598"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_599 { address = 0xfffc0b9c; sn = "SIUL2_MSCR_MUX_599"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_600 { address = 0xfffc0ba0; sn = "SIUL2_MSCR_MUX_600"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_601 { address = 0xfffc0ba4; sn = "SIUL2_MSCR_MUX_601"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_602 { address = 0xfffc0ba8; sn = "SIUL2_MSCR_MUX_602"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_603 { address = 0xfffc0bac; sn = "SIUL2_MSCR_MUX_603"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_604 { address = 0xfffc0bb0; sn = "SIUL2_MSCR_MUX_604"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_605 { address = 0xfffc0bb4; sn = "SIUL2_MSCR_MUX_605"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_606 { address = 0xfffc0bb8; sn = "SIUL2_MSCR_MUX_606"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_607 { address = 0xfffc0bbc; sn = "SIUL2_MSCR_MUX_607"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_608 { address = 0xfffc0bc0; sn = "SIUL2_MSCR_MUX_608"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_609 { address = 0xfffc0bc4; sn = "SIUL2_MSCR_MUX_609"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_610 { address = 0xfffc0bc8; sn = "SIUL2_MSCR_MUX_610"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_611 { address = 0xfffc0bcc; sn = "SIUL2_MSCR_MUX_611"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_612 { address = 0xfffc0bd0; sn = "SIUL2_MSCR_MUX_612"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_613 { address = 0xfffc0bd4; sn = "SIUL2_MSCR_MUX_613"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_614 { address = 0xfffc0bd8; sn = "SIUL2_MSCR_MUX_614"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_615 { address = 0xfffc0bdc; sn = "SIUL2_MSCR_MUX_615"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_616 { address = 0xfffc0be0; sn = "SIUL2_MSCR_MUX_616"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_617 { address = 0xfffc0be4; sn = "SIUL2_MSCR_MUX_617"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_618 { address = 0xfffc0be8; sn = "SIUL2_MSCR_MUX_618"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_619 { address = 0xfffc0bec; sn = "SIUL2_MSCR_MUX_619"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_620 { address = 0xfffc0bf0; sn = "SIUL2_MSCR_MUX_620"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_621 { address = 0xfffc0bf4; sn = "SIUL2_MSCR_MUX_621"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_622 { address = 0xfffc0bf8; sn = "SIUL2_MSCR_MUX_622"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_623 { address = 0xfffc0bfc; sn = "SIUL2_MSCR_MUX_623"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_624 { address = 0xfffc0c00; sn = "SIUL2_MSCR_MUX_624"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_625 { address = 0xfffc0c04; sn = "SIUL2_MSCR_MUX_625"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_626 { address = 0xfffc0c08; sn = "SIUL2_MSCR_MUX_626"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_627 { address = 0xfffc0c0c; sn = "SIUL2_MSCR_MUX_627"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_628 { address = 0xfffc0c10; sn = "SIUL2_MSCR_MUX_628"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_629 { address = 0xfffc0c14; sn = "SIUL2_MSCR_MUX_629"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_630 { address = 0xfffc0c18; sn = "SIUL2_MSCR_MUX_630"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_631 { address = 0xfffc0c1c; sn = "SIUL2_MSCR_MUX_631"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_632 { address = 0xfffc0c20; sn = "SIUL2_MSCR_MUX_632"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_633 { address = 0xfffc0c24; sn = "SIUL2_MSCR_MUX_633"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_634 { address = 0xfffc0c28; sn = "SIUL2_MSCR_MUX_634"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_635 { address = 0xfffc0c2c; sn = "SIUL2_MSCR_MUX_635"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_636 { address = 0xfffc0c30; sn = "SIUL2_MSCR_MUX_636"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_637 { address = 0xfffc0c34; sn = "SIUL2_MSCR_MUX_637"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_638 { address = 0xfffc0c38; sn = "SIUL2_MSCR_MUX_638"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_639 { address = 0xfffc0c3c; sn = "SIUL2_MSCR_MUX_639"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_640 { address = 0xfffc0c40; sn = "SIUL2_MSCR_MUX_640"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_641 { address = 0xfffc0c44; sn = "SIUL2_MSCR_MUX_641"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_642 { address = 0xfffc0c48; sn = "SIUL2_MSCR_MUX_642"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_643 { address = 0xfffc0c4c; sn = "SIUL2_MSCR_MUX_643"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_644 { address = 0xfffc0c50; sn = "SIUL2_MSCR_MUX_644"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_645 { address = 0xfffc0c54; sn = "SIUL2_MSCR_MUX_645"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_646 { address = 0xfffc0c58; sn = "SIUL2_MSCR_MUX_646"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_647 { address = 0xfffc0c5c; sn = "SIUL2_MSCR_MUX_647"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_648 { address = 0xfffc0c60; sn = "SIUL2_MSCR_MUX_648"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_649 { address = 0xfffc0c64; sn = "SIUL2_MSCR_MUX_649"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_650 { address = 0xfffc0c68; sn = "SIUL2_MSCR_MUX_650"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_651 { address = 0xfffc0c6c; sn = "SIUL2_MSCR_MUX_651"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_652 { address = 0xfffc0c70; sn = "SIUL2_MSCR_MUX_652"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_653 { address = 0xfffc0c74; sn = "SIUL2_MSCR_MUX_653"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_654 { address = 0xfffc0c78; sn = "SIUL2_MSCR_MUX_654"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_655 { address = 0xfffc0c7c; sn = "SIUL2_MSCR_MUX_655"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_656 { address = 0xfffc0c80; sn = "SIUL2_MSCR_MUX_656"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_657 { address = 0xfffc0c84; sn = "SIUL2_MSCR_MUX_657"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_658 { address = 0xfffc0c88; sn = "SIUL2_MSCR_MUX_658"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_659 { address = 0xfffc0c8c; sn = "SIUL2_MSCR_MUX_659"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_660 { address = 0xfffc0c90; sn = "SIUL2_MSCR_MUX_660"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_661 { address = 0xfffc0c94; sn = "SIUL2_MSCR_MUX_661"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_662 { address = 0xfffc0c98; sn = "SIUL2_MSCR_MUX_662"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_663 { address = 0xfffc0c9c; sn = "SIUL2_MSCR_MUX_663"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_664 { address = 0xfffc0ca0; sn = "SIUL2_MSCR_MUX_664"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_665 { address = 0xfffc0ca4; sn = "SIUL2_MSCR_MUX_665"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_666 { address = 0xfffc0ca8; sn = "SIUL2_MSCR_MUX_666"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_667 { address = 0xfffc0cac; sn = "SIUL2_MSCR_MUX_667"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_668 { address = 0xfffc0cb0; sn = "SIUL2_MSCR_MUX_668"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_669 { address = 0xfffc0cb4; sn = "SIUL2_MSCR_MUX_669"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_670 { address = 0xfffc0cb8; sn = "SIUL2_MSCR_MUX_670"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_671 { address = 0xfffc0cbc; sn = "SIUL2_MSCR_MUX_671"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_672 { address = 0xfffc0cc0; sn = "SIUL2_MSCR_MUX_672"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_673 { address = 0xfffc0cc4; sn = "SIUL2_MSCR_MUX_673"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_674 { address = 0xfffc0cc8; sn = "SIUL2_MSCR_MUX_674"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_675 { address = 0xfffc0ccc; sn = "SIUL2_MSCR_MUX_675"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_676 { address = 0xfffc0cd0; sn = "SIUL2_MSCR_MUX_676"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_677 { address = 0xfffc0cd4; sn = "SIUL2_MSCR_MUX_677"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_678 { address = 0xfffc0cd8; sn = "SIUL2_MSCR_MUX_678"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_679 { address = 0xfffc0cdc; sn = "SIUL2_MSCR_MUX_679"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_680 { address = 0xfffc0ce0; sn = "SIUL2_MSCR_MUX_680"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_681 { address = 0xfffc0ce4; sn = "SIUL2_MSCR_MUX_681"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_682 { address = 0xfffc0ce8; sn = "SIUL2_MSCR_MUX_682"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_683 { address = 0xfffc0cec; sn = "SIUL2_MSCR_MUX_683"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_684 { address = 0xfffc0cf0; sn = "SIUL2_MSCR_MUX_684"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_685 { address = 0xfffc0cf4; sn = "SIUL2_MSCR_MUX_685"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_686 { address = 0xfffc0cf8; sn = "SIUL2_MSCR_MUX_686"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_687 { address = 0xfffc0cfc; sn = "SIUL2_MSCR_MUX_687"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_688 { address = 0xfffc0d00; sn = "SIUL2_MSCR_MUX_688"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_689 { address = 0xfffc0d04; sn = "SIUL2_MSCR_MUX_689"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_690 { address = 0xfffc0d08; sn = "SIUL2_MSCR_MUX_690"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_691 { address = 0xfffc0d0c; sn = "SIUL2_MSCR_MUX_691"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_692 { address = 0xfffc0d10; sn = "SIUL2_MSCR_MUX_692"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_693 { address = 0xfffc0d14; sn = "SIUL2_MSCR_MUX_693"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_694 { address = 0xfffc0d18; sn = "SIUL2_MSCR_MUX_694"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_695 { address = 0xfffc0d1c; sn = "SIUL2_MSCR_MUX_695"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_696 { address = 0xfffc0d20; sn = "SIUL2_MSCR_MUX_696"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_697 { address = 0xfffc0d24; sn = "SIUL2_MSCR_MUX_697"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_698 { address = 0xfffc0d28; sn = "SIUL2_MSCR_MUX_698"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_699 { address = 0xfffc0d2c; sn = "SIUL2_MSCR_MUX_699"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_700 { address = 0xfffc0d30; sn = "SIUL2_MSCR_MUX_700"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_701 { address = 0xfffc0d34; sn = "SIUL2_MSCR_MUX_701"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_702 { address = 0xfffc0d38; sn = "SIUL2_MSCR_MUX_702"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_703 { address = 0xfffc0d3c; sn = "SIUL2_MSCR_MUX_703"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_704 { address = 0xfffc0d40; sn = "SIUL2_MSCR_MUX_704"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_705 { address = 0xfffc0d44; sn = "SIUL2_MSCR_MUX_705"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_706 { address = 0xfffc0d48; sn = "SIUL2_MSCR_MUX_706"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_707 { address = 0xfffc0d4c; sn = "SIUL2_MSCR_MUX_707"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_708 { address = 0xfffc0d50; sn = "SIUL2_MSCR_MUX_708"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_709 { address = 0xfffc0d54; sn = "SIUL2_MSCR_MUX_709"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_710 { address = 0xfffc0d58; sn = "SIUL2_MSCR_MUX_710"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_711 { address = 0xfffc0d5c; sn = "SIUL2_MSCR_MUX_711"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_712 { address = 0xfffc0d60; sn = "SIUL2_MSCR_MUX_712"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_713 { address = 0xfffc0d64; sn = "SIUL2_MSCR_MUX_713"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_714 { address = 0xfffc0d68; sn = "SIUL2_MSCR_MUX_714"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_715 { address = 0xfffc0d6c; sn = "SIUL2_MSCR_MUX_715"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_716 { address = 0xfffc0d70; sn = "SIUL2_MSCR_MUX_716"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_717 { address = 0xfffc0d74; sn = "SIUL2_MSCR_MUX_717"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_718 { address = 0xfffc0d78; sn = "SIUL2_MSCR_MUX_718"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_719 { address = 0xfffc0d7c; sn = "SIUL2_MSCR_MUX_719"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_720 { address = 0xfffc0d80; sn = "SIUL2_MSCR_MUX_720"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_721 { address = 0xfffc0d84; sn = "SIUL2_MSCR_MUX_721"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_722 { address = 0xfffc0d88; sn = "SIUL2_MSCR_MUX_722"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_723 { address = 0xfffc0d8c; sn = "SIUL2_MSCR_MUX_723"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_724 { address = 0xfffc0d90; sn = "SIUL2_MSCR_MUX_724"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_725 { address = 0xfffc0d94; sn = "SIUL2_MSCR_MUX_725"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_726 { address = 0xfffc0d98; sn = "SIUL2_MSCR_MUX_726"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_727 { address = 0xfffc0d9c; sn = "SIUL2_MSCR_MUX_727"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_728 { address = 0xfffc0da0; sn = "SIUL2_MSCR_MUX_728"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_729 { address = 0xfffc0da4; sn = "SIUL2_MSCR_MUX_729"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_730 { address = 0xfffc0da8; sn = "SIUL2_MSCR_MUX_730"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_731 { address = 0xfffc0dac; sn = "SIUL2_MSCR_MUX_731"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_732 { address = 0xfffc0db0; sn = "SIUL2_MSCR_MUX_732"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_733 { address = 0xfffc0db4; sn = "SIUL2_MSCR_MUX_733"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_734 { address = 0xfffc0db8; sn = "SIUL2_MSCR_MUX_734"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_735 { address = 0xfffc0dbc; sn = "SIUL2_MSCR_MUX_735"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_736 { address = 0xfffc0dc0; sn = "SIUL2_MSCR_MUX_736"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_737 { address = 0xfffc0dc4; sn = "SIUL2_MSCR_MUX_737"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_738 { address = 0xfffc0dc8; sn = "SIUL2_MSCR_MUX_738"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_739 { address = 0xfffc0dcc; sn = "SIUL2_MSCR_MUX_739"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_740 { address = 0xfffc0dd0; sn = "SIUL2_MSCR_MUX_740"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_741 { address = 0xfffc0dd4; sn = "SIUL2_MSCR_MUX_741"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_742 { address = 0xfffc0dd8; sn = "SIUL2_MSCR_MUX_742"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_743 { address = 0xfffc0ddc; sn = "SIUL2_MSCR_MUX_743"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_744 { address = 0xfffc0de0; sn = "SIUL2_MSCR_MUX_744"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_745 { address = 0xfffc0de4; sn = "SIUL2_MSCR_MUX_745"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_746 { address = 0xfffc0de8; sn = "SIUL2_MSCR_MUX_746"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_747 { address = 0xfffc0dec; sn = "SIUL2_MSCR_MUX_747"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_748 { address = 0xfffc0df0; sn = "SIUL2_MSCR_MUX_748"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_749 { address = 0xfffc0df4; sn = "SIUL2_MSCR_MUX_749"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_750 { address = 0xfffc0df8; sn = "SIUL2_MSCR_MUX_750"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_751 { address = 0xfffc0dfc; sn = "SIUL2_MSCR_MUX_751"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_752 { address = 0xfffc0e00; sn = "SIUL2_MSCR_MUX_752"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_753 { address = 0xfffc0e04; sn = "SIUL2_MSCR_MUX_753"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_754 { address = 0xfffc0e08; sn = "SIUL2_MSCR_MUX_754"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_755 { address = 0xfffc0e0c; sn = "SIUL2_MSCR_MUX_755"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_756 { address = 0xfffc0e10; sn = "SIUL2_MSCR_MUX_756"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_757 { address = 0xfffc0e14; sn = "SIUL2_MSCR_MUX_757"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_758 { address = 0xfffc0e18; sn = "SIUL2_MSCR_MUX_758"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_759 { address = 0xfffc0e1c; sn = "SIUL2_MSCR_MUX_759"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_760 { address = 0xfffc0e20; sn = "SIUL2_MSCR_MUX_760"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_761 { address = 0xfffc0e24; sn = "SIUL2_MSCR_MUX_761"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_762 { address = 0xfffc0e28; sn = "SIUL2_MSCR_MUX_762"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_763 { address = 0xfffc0e2c; sn = "SIUL2_MSCR_MUX_763"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_764 { address = 0xfffc0e30; sn = "SIUL2_MSCR_MUX_764"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_765 { address = 0xfffc0e34; sn = "SIUL2_MSCR_MUX_765"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_766 { address = 0xfffc0e38; sn = "SIUL2_MSCR_MUX_766"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_767 { address = 0xfffc0e3c; sn = "SIUL2_MSCR_MUX_767"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_768 { address = 0xfffc0e40; sn = "SIUL2_MSCR_MUX_768"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_769 { address = 0xfffc0e44; sn = "SIUL2_MSCR_MUX_769"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_770 { address = 0xfffc0e48; sn = "SIUL2_MSCR_MUX_770"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_771 { address = 0xfffc0e4c; sn = "SIUL2_MSCR_MUX_771"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_772 { address = 0xfffc0e50; sn = "SIUL2_MSCR_MUX_772"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_773 { address = 0xfffc0e54; sn = "SIUL2_MSCR_MUX_773"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_774 { address = 0xfffc0e58; sn = "SIUL2_MSCR_MUX_774"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_775 { address = 0xfffc0e5c; sn = "SIUL2_MSCR_MUX_775"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_776 { address = 0xfffc0e60; sn = "SIUL2_MSCR_MUX_776"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_777 { address = 0xfffc0e64; sn = "SIUL2_MSCR_MUX_777"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_778 { address = 0xfffc0e68; sn = "SIUL2_MSCR_MUX_778"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_779 { address = 0xfffc0e6c; sn = "SIUL2_MSCR_MUX_779"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_780 { address = 0xfffc0e70; sn = "SIUL2_MSCR_MUX_780"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_781 { address = 0xfffc0e74; sn = "SIUL2_MSCR_MUX_781"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_782 { address = 0xfffc0e78; sn = "SIUL2_MSCR_MUX_782"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_783 { address = 0xfffc0e7c; sn = "SIUL2_MSCR_MUX_783"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_784 { address = 0xfffc0e80; sn = "SIUL2_MSCR_MUX_784"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_785 { address = 0xfffc0e84; sn = "SIUL2_MSCR_MUX_785"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_786 { address = 0xfffc0e88; sn = "SIUL2_MSCR_MUX_786"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_787 { address = 0xfffc0e8c; sn = "SIUL2_MSCR_MUX_787"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_788 { address = 0xfffc0e90; sn = "SIUL2_MSCR_MUX_788"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_789 { address = 0xfffc0e94; sn = "SIUL2_MSCR_MUX_789"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_790 { address = 0xfffc0e98; sn = "SIUL2_MSCR_MUX_790"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_791 { address = 0xfffc0e9c; sn = "SIUL2_MSCR_MUX_791"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_792 { address = 0xfffc0ea0; sn = "SIUL2_MSCR_MUX_792"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_793 { address = 0xfffc0ea4; sn = "SIUL2_MSCR_MUX_793"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_794 { address = 0xfffc0ea8; sn = "SIUL2_MSCR_MUX_794"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_795 { address = 0xfffc0eac; sn = "SIUL2_MSCR_MUX_795"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_796 { address = 0xfffc0eb0; sn = "SIUL2_MSCR_MUX_796"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_797 { address = 0xfffc0eb4; sn = "SIUL2_MSCR_MUX_797"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_798 { address = 0xfffc0eb8; sn = "SIUL2_MSCR_MUX_798"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_799 { address = 0xfffc0ebc; sn = "SIUL2_MSCR_MUX_799"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_800 { address = 0xfffc0ec0; sn = "SIUL2_MSCR_MUX_800"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_801 { address = 0xfffc0ec4; sn = "SIUL2_MSCR_MUX_801"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_802 { address = 0xfffc0ec8; sn = "SIUL2_MSCR_MUX_802"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_803 { address = 0xfffc0ecc; sn = "SIUL2_MSCR_MUX_803"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_804 { address = 0xfffc0ed0; sn = "SIUL2_MSCR_MUX_804"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_805 { address = 0xfffc0ed4; sn = "SIUL2_MSCR_MUX_805"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_806 { address = 0xfffc0ed8; sn = "SIUL2_MSCR_MUX_806"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_807 { address = 0xfffc0edc; sn = "SIUL2_MSCR_MUX_807"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_808 { address = 0xfffc0ee0; sn = "SIUL2_MSCR_MUX_808"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_809 { address = 0xfffc0ee4; sn = "SIUL2_MSCR_MUX_809"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_810 { address = 0xfffc0ee8; sn = "SIUL2_MSCR_MUX_810"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_811 { address = 0xfffc0eec; sn = "SIUL2_MSCR_MUX_811"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_812 { address = 0xfffc0ef0; sn = "SIUL2_MSCR_MUX_812"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_813 { address = 0xfffc0ef4; sn = "SIUL2_MSCR_MUX_813"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_814 { address = 0xfffc0ef8; sn = "SIUL2_MSCR_MUX_814"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_815 { address = 0xfffc0efc; sn = "SIUL2_MSCR_MUX_815"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_816 { address = 0xfffc0f00; sn = "SIUL2_MSCR_MUX_816"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_817 { address = 0xfffc0f04; sn = "SIUL2_MSCR_MUX_817"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_818 { address = 0xfffc0f08; sn = "SIUL2_MSCR_MUX_818"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_819 { address = 0xfffc0f0c; sn = "SIUL2_MSCR_MUX_819"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_820 { address = 0xfffc0f10; sn = "SIUL2_MSCR_MUX_820"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_821 { address = 0xfffc0f14; sn = "SIUL2_MSCR_MUX_821"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_822 { address = 0xfffc0f18; sn = "SIUL2_MSCR_MUX_822"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_823 { address = 0xfffc0f1c; sn = "SIUL2_MSCR_MUX_823"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_824 { address = 0xfffc0f20; sn = "SIUL2_MSCR_MUX_824"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_825 { address = 0xfffc0f24; sn = "SIUL2_MSCR_MUX_825"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_826 { address = 0xfffc0f28; sn = "SIUL2_MSCR_MUX_826"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_827 { address = 0xfffc0f2c; sn = "SIUL2_MSCR_MUX_827"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_828 { address = 0xfffc0f30; sn = "SIUL2_MSCR_MUX_828"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_829 { address = 0xfffc0f34; sn = "SIUL2_MSCR_MUX_829"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_830 { address = 0xfffc0f38; sn = "SIUL2_MSCR_MUX_830"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_831 { address = 0xfffc0f3c; sn = "SIUL2_MSCR_MUX_831"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_832 { address = 0xfffc0f40; sn = "SIUL2_MSCR_MUX_832"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_833 { address = 0xfffc0f44; sn = "SIUL2_MSCR_MUX_833"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_834 { address = 0xfffc0f48; sn = "SIUL2_MSCR_MUX_834"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_835 { address = 0xfffc0f4c; sn = "SIUL2_MSCR_MUX_835"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_836 { address = 0xfffc0f50; sn = "SIUL2_MSCR_MUX_836"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_837 { address = 0xfffc0f54; sn = "SIUL2_MSCR_MUX_837"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_838 { address = 0xfffc0f58; sn = "SIUL2_MSCR_MUX_838"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_839 { address = 0xfffc0f5c; sn = "SIUL2_MSCR_MUX_839"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_840 { address = 0xfffc0f60; sn = "SIUL2_MSCR_MUX_840"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_841 { address = 0xfffc0f64; sn = "SIUL2_MSCR_MUX_841"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_842 { address = 0xfffc0f68; sn = "SIUL2_MSCR_MUX_842"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_843 { address = 0xfffc0f6c; sn = "SIUL2_MSCR_MUX_843"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_844 { address = 0xfffc0f70; sn = "SIUL2_MSCR_MUX_844"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_845 { address = 0xfffc0f74; sn = "SIUL2_MSCR_MUX_845"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_846 { address = 0xfffc0f78; sn = "SIUL2_MSCR_MUX_846"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_847 { address = 0xfffc0f7c; sn = "SIUL2_MSCR_MUX_847"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_848 { address = 0xfffc0f80; sn = "SIUL2_MSCR_MUX_848"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_849 { address = 0xfffc0f84; sn = "SIUL2_MSCR_MUX_849"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_850 { address = 0xfffc0f88; sn = "SIUL2_MSCR_MUX_850"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_851 { address = 0xfffc0f8c; sn = "SIUL2_MSCR_MUX_851"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_852 { address = 0xfffc0f90; sn = "SIUL2_MSCR_MUX_852"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_853 { address = 0xfffc0f94; sn = "SIUL2_MSCR_MUX_853"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_854 { address = 0xfffc0f98; sn = "SIUL2_MSCR_MUX_854"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_855 { address = 0xfffc0f9c; sn = "SIUL2_MSCR_MUX_855"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_856 { address = 0xfffc0fa0; sn = "SIUL2_MSCR_MUX_856"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_857 { address = 0xfffc0fa4; sn = "SIUL2_MSCR_MUX_857"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_858 { address = 0xfffc0fa8; sn = "SIUL2_MSCR_MUX_858"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_859 { address = 0xfffc0fac; sn = "SIUL2_MSCR_MUX_859"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_860 { address = 0xfffc0fb0; sn = "SIUL2_MSCR_MUX_860"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_861 { address = 0xfffc0fb4; sn = "SIUL2_MSCR_MUX_861"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_862 { address = 0xfffc0fb8; sn = "SIUL2_MSCR_MUX_862"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_863 { address = 0xfffc0fbc; sn = "SIUL2_MSCR_MUX_863"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_864 { address = 0xfffc0fc0; sn = "SIUL2_MSCR_MUX_864"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_865 { address = 0xfffc0fc4; sn = "SIUL2_MSCR_MUX_865"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_866 { address = 0xfffc0fc8; sn = "SIUL2_MSCR_MUX_866"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_867 { address = 0xfffc0fcc; sn = "SIUL2_MSCR_MUX_867"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_868 { address = 0xfffc0fd0; sn = "SIUL2_MSCR_MUX_868"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_869 { address = 0xfffc0fd4; sn = "SIUL2_MSCR_MUX_869"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_870 { address = 0xfffc0fd8; sn = "SIUL2_MSCR_MUX_870"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_871 { address = 0xfffc0fdc; sn = "SIUL2_MSCR_MUX_871"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_872 { address = 0xfffc0fe0; sn = "SIUL2_MSCR_MUX_872"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_873 { address = 0xfffc0fe4; sn = "SIUL2_MSCR_MUX_873"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_874 { address = 0xfffc0fe8; sn = "SIUL2_MSCR_MUX_874"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_875 { address = 0xfffc0fec; sn = "SIUL2_MSCR_MUX_875"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_876 { address = 0xfffc0ff0; sn = "SIUL2_MSCR_MUX_876"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_877 { address = 0xfffc0ff4; sn = "SIUL2_MSCR_MUX_877"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_878 { address = 0xfffc0ff8; sn = "SIUL2_MSCR_MUX_878"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_879 { address = 0xfffc0ffc; sn = "SIUL2_MSCR_MUX_879"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_880 { address = 0xfffc1000; sn = "SIUL2_MSCR_MUX_880"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_881 { address = 0xfffc1004; sn = "SIUL2_MSCR_MUX_881"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_882 { address = 0xfffc1008; sn = "SIUL2_MSCR_MUX_882"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_883 { address = 0xfffc100c; sn = "SIUL2_MSCR_MUX_883"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_884 { address = 0xfffc1010; sn = "SIUL2_MSCR_MUX_884"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_885 { address = 0xfffc1014; sn = "SIUL2_MSCR_MUX_885"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_886 { address = 0xfffc1018; sn = "SIUL2_MSCR_MUX_886"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_887 { address = 0xfffc101c; sn = "SIUL2_MSCR_MUX_887"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_888 { address = 0xfffc1020; sn = "SIUL2_MSCR_MUX_888"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_889 { address = 0xfffc1024; sn = "SIUL2_MSCR_MUX_889"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_890 { address = 0xfffc1028; sn = "SIUL2_MSCR_MUX_890"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_891 { address = 0xfffc102c; sn = "SIUL2_MSCR_MUX_891"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_892 { address = 0xfffc1030; sn = "SIUL2_MSCR_MUX_892"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_893 { address = 0xfffc1034; sn = "SIUL2_MSCR_MUX_893"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_894 { address = 0xfffc1038; sn = "SIUL2_MSCR_MUX_894"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_895 { address = 0xfffc103c; sn = "SIUL2_MSCR_MUX_895"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_896 { address = 0xfffc1040; sn = "SIUL2_MSCR_MUX_896"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_897 { address = 0xfffc1044; sn = "SIUL2_MSCR_MUX_897"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_898 { address = 0xfffc1048; sn = "SIUL2_MSCR_MUX_898"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_899 { address = 0xfffc104c; sn = "SIUL2_MSCR_MUX_899"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_900 { address = 0xfffc1050; sn = "SIUL2_MSCR_MUX_900"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_901 { address = 0xfffc1054; sn = "SIUL2_MSCR_MUX_901"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_902 { address = 0xfffc1058; sn = "SIUL2_MSCR_MUX_902"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_903 { address = 0xfffc105c; sn = "SIUL2_MSCR_MUX_903"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_904 { address = 0xfffc1060; sn = "SIUL2_MSCR_MUX_904"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_905 { address = 0xfffc1064; sn = "SIUL2_MSCR_MUX_905"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_906 { address = 0xfffc1068; sn = "SIUL2_MSCR_MUX_906"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_907 { address = 0xfffc106c; sn = "SIUL2_MSCR_MUX_907"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_908 { address = 0xfffc1070; sn = "SIUL2_MSCR_MUX_908"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_909 { address = 0xfffc1074; sn = "SIUL2_MSCR_MUX_909"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_910 { address = 0xfffc1078; sn = "SIUL2_MSCR_MUX_910"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_911 { address = 0xfffc107c; sn = "SIUL2_MSCR_MUX_911"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_912 { address = 0xfffc1080; sn = "SIUL2_MSCR_MUX_912"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_913 { address = 0xfffc1084; sn = "SIUL2_MSCR_MUX_913"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_914 { address = 0xfffc1088; sn = "SIUL2_MSCR_MUX_914"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_915 { address = 0xfffc108c; sn = "SIUL2_MSCR_MUX_915"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_916 { address = 0xfffc1090; sn = "SIUL2_MSCR_MUX_916"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_917 { address = 0xfffc1094; sn = "SIUL2_MSCR_MUX_917"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_918 { address = 0xfffc1098; sn = "SIUL2_MSCR_MUX_918"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_919 { address = 0xfffc109c; sn = "SIUL2_MSCR_MUX_919"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_920 { address = 0xfffc10a0; sn = "SIUL2_MSCR_MUX_920"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_921 { address = 0xfffc10a4; sn = "SIUL2_MSCR_MUX_921"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_922 { address = 0xfffc10a8; sn = "SIUL2_MSCR_MUX_922"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_923 { address = 0xfffc10ac; sn = "SIUL2_MSCR_MUX_923"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_924 { address = 0xfffc10b0; sn = "SIUL2_MSCR_MUX_924"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_925 { address = 0xfffc10b4; sn = "SIUL2_MSCR_MUX_925"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_926 { address = 0xfffc10b8; sn = "SIUL2_MSCR_MUX_926"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_927 { address = 0xfffc10bc; sn = "SIUL2_MSCR_MUX_927"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_928 { address = 0xfffc10c0; sn = "SIUL2_MSCR_MUX_928"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_929 { address = 0xfffc10c4; sn = "SIUL2_MSCR_MUX_929"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_930 { address = 0xfffc10c8; sn = "SIUL2_MSCR_MUX_930"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_931 { address = 0xfffc10cc; sn = "SIUL2_MSCR_MUX_931"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_932 { address = 0xfffc10d0; sn = "SIUL2_MSCR_MUX_932"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_933 { address = 0xfffc10d4; sn = "SIUL2_MSCR_MUX_933"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_934 { address = 0xfffc10d8; sn = "SIUL2_MSCR_MUX_934"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_935 { address = 0xfffc10dc; sn = "SIUL2_MSCR_MUX_935"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_936 { address = 0xfffc10e0; sn = "SIUL2_MSCR_MUX_936"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_937 { address = 0xfffc10e4; sn = "SIUL2_MSCR_MUX_937"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_938 { address = 0xfffc10e8; sn = "SIUL2_MSCR_MUX_938"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_939 { address = 0xfffc10ec; sn = "SIUL2_MSCR_MUX_939"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_940 { address = 0xfffc10f0; sn = "SIUL2_MSCR_MUX_940"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_941 { address = 0xfffc10f4; sn = "SIUL2_MSCR_MUX_941"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_942 { address = 0xfffc10f8; sn = "SIUL2_MSCR_MUX_942"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_943 { address = 0xfffc10fc; sn = "SIUL2_MSCR_MUX_943"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_944 { address = 0xfffc1100; sn = "SIUL2_MSCR_MUX_944"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_945 { address = 0xfffc1104; sn = "SIUL2_MSCR_MUX_945"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_946 { address = 0xfffc1108; sn = "SIUL2_MSCR_MUX_946"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_947 { address = 0xfffc110c; sn = "SIUL2_MSCR_MUX_947"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_948 { address = 0xfffc1110; sn = "SIUL2_MSCR_MUX_948"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_949 { address = 0xfffc1114; sn = "SIUL2_MSCR_MUX_949"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_950 { address = 0xfffc1118; sn = "SIUL2_MSCR_MUX_950"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_951 { address = 0xfffc111c; sn = "SIUL2_MSCR_MUX_951"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_952 { address = 0xfffc1120; sn = "SIUL2_MSCR_MUX_952"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_953 { address = 0xfffc1124; sn = "SIUL2_MSCR_MUX_953"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_954 { address = 0xfffc1128; sn = "SIUL2_MSCR_MUX_954"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_955 { address = 0xfffc112c; sn = "SIUL2_MSCR_MUX_955"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_956 { address = 0xfffc1130; sn = "SIUL2_MSCR_MUX_956"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_957 { address = 0xfffc1134; sn = "SIUL2_MSCR_MUX_957"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_958 { address = 0xfffc1138; sn = "SIUL2_MSCR_MUX_958"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_959 { address = 0xfffc113c; sn = "SIUL2_MSCR_MUX_959"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_960 { address = 0xfffc1140; sn = "SIUL2_MSCR_MUX_960"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_961 { address = 0xfffc1144; sn = "SIUL2_MSCR_MUX_961"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_962 { address = 0xfffc1148; sn = "SIUL2_MSCR_MUX_962"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_963 { address = 0xfffc114c; sn = "SIUL2_MSCR_MUX_963"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_964 { address = 0xfffc1150; sn = "SIUL2_MSCR_MUX_964"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_965 { address = 0xfffc1154; sn = "SIUL2_MSCR_MUX_965"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_966 { address = 0xfffc1158; sn = "SIUL2_MSCR_MUX_966"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_967 { address = 0xfffc115c; sn = "SIUL2_MSCR_MUX_967"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_968 { address = 0xfffc1160; sn = "SIUL2_MSCR_MUX_968"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_969 { address = 0xfffc1164; sn = "SIUL2_MSCR_MUX_969"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_970 { address = 0xfffc1168; sn = "SIUL2_MSCR_MUX_970"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_971 { address = 0xfffc116c; sn = "SIUL2_MSCR_MUX_971"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_972 { address = 0xfffc1170; sn = "SIUL2_MSCR_MUX_972"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_973 { address = 0xfffc1174; sn = "SIUL2_MSCR_MUX_973"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_974 { address = 0xfffc1178; sn = "SIUL2_MSCR_MUX_974"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_975 { address = 0xfffc117c; sn = "SIUL2_MSCR_MUX_975"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_976 { address = 0xfffc1180; sn = "SIUL2_MSCR_MUX_976"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_977 { address = 0xfffc1184; sn = "SIUL2_MSCR_MUX_977"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_978 { address = 0xfffc1188; sn = "SIUL2_MSCR_MUX_978"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_979 { address = 0xfffc118c; sn = "SIUL2_MSCR_MUX_979"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_980 { address = 0xfffc1190; sn = "SIUL2_MSCR_MUX_980"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_981 { address = 0xfffc1194; sn = "SIUL2_MSCR_MUX_981"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_982 { address = 0xfffc1198; sn = "SIUL2_MSCR_MUX_982"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_983 { address = 0xfffc119c; sn = "SIUL2_MSCR_MUX_983"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_984 { address = 0xfffc11a0; sn = "SIUL2_MSCR_MUX_984"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_985 { address = 0xfffc11a4; sn = "SIUL2_MSCR_MUX_985"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_986 { address = 0xfffc11a8; sn = "SIUL2_MSCR_MUX_986"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_987 { address = 0xfffc11ac; sn = "SIUL2_MSCR_MUX_987"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_988 { address = 0xfffc11b0; sn = "SIUL2_MSCR_MUX_988"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_989 { address = 0xfffc11b4; sn = "SIUL2_MSCR_MUX_989"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_990 { address = 0xfffc11b8; sn = "SIUL2_MSCR_MUX_990"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_991 { address = 0xfffc11bc; sn = "SIUL2_MSCR_MUX_991"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_992 { address = 0xfffc11c0; sn = "SIUL2_MSCR_MUX_992"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_993 { address = 0xfffc11c4; sn = "SIUL2_MSCR_MUX_993"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_994 { address = 0xfffc11c8; sn = "SIUL2_MSCR_MUX_994"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_995 { address = 0xfffc11cc; sn = "SIUL2_MSCR_MUX_995"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_996 { address = 0xfffc11d0; sn = "SIUL2_MSCR_MUX_996"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_997 { address = 0xfffc11d4; sn = "SIUL2_MSCR_MUX_997"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_998 { address = 0xfffc11d8; sn = "SIUL2_MSCR_MUX_998"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_999 { address = 0xfffc11dc; sn = "SIUL2_MSCR_MUX_999"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_1000 { address = 0xfffc11e0; sn = "SIUL2_MSCR_MUX_1000"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_1001 { address = 0xfffc11e4; sn = "SIUL2_MSCR_MUX_1001"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_1002 { address = 0xfffc11e8; sn = "SIUL2_MSCR_MUX_1002"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_1003 { address = 0xfffc11ec; sn = "SIUL2_MSCR_MUX_1003"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_1004 { address = 0xfffc11f0; sn = "SIUL2_MSCR_MUX_1004"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_1005 { address = 0xfffc11f4; sn = "SIUL2_MSCR_MUX_1005"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_1006 { address = 0xfffc11f8; sn = "SIUL2_MSCR_MUX_1006"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_1007 { address = 0xfffc11fc; sn = "SIUL2_MSCR_MUX_1007"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_1008 { address = 0xfffc1200; sn = "SIUL2_MSCR_MUX_1008"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_1009 { address = 0xfffc1204; sn = "SIUL2_MSCR_MUX_1009"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_1010 { address = 0xfffc1208; sn = "SIUL2_MSCR_MUX_1010"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_1011 { address = 0xfffc120c; sn = "SIUL2_MSCR_MUX_1011"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_1012 { address = 0xfffc1210; sn = "SIUL2_MSCR_MUX_1012"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_1013 { address = 0xfffc1214; sn = "SIUL2_MSCR_MUX_1013"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_1014 { address = 0xfffc1218; sn = "SIUL2_MSCR_MUX_1014"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_1015 { address = 0xfffc121c; sn = "SIUL2_MSCR_MUX_1015"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_1016 { address = 0xfffc1220; sn = "SIUL2_MSCR_MUX_1016"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_1017 { address = 0xfffc1224; sn = "SIUL2_MSCR_MUX_1017"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_1018 { address = 0xfffc1228; sn = "SIUL2_MSCR_MUX_1018"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_1019 { address = 0xfffc122c; sn = "SIUL2_MSCR_MUX_1019"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_1020 { address = 0xfffc1230; sn = "SIUL2_MSCR_MUX_1020"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_1021 { address = 0xfffc1234; sn = "SIUL2_MSCR_MUX_1021"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_1022 { address = 0xfffc1238; sn = "SIUL2_MSCR_MUX_1022"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_MSCR_MUX_1023 { address = 0xfffc123c; sn = "SIUL2_MSCR_MUX_1023"; access = "memorymapped"; width = 32; ${_DESC2160_}; type = "bitfield_SIUL2_MSCR_MUX_512" } SIUL2_GPDO0 { address = 0xfffc1300; sn = "SIUL2_GPDO0"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO1 { address = 0xfffc1301; sn = "SIUL2_GPDO1"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO2 { address = 0xfffc1302; sn = "SIUL2_GPDO2"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO3 { address = 0xfffc1303; sn = "SIUL2_GPDO3"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO4 { address = 0xfffc1304; sn = "SIUL2_GPDO4"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO5 { address = 0xfffc1305; sn = "SIUL2_GPDO5"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO6 { address = 0xfffc1306; sn = "SIUL2_GPDO6"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO7 { address = 0xfffc1307; sn = "SIUL2_GPDO7"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO8 { address = 0xfffc1308; sn = "SIUL2_GPDO8"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO9 { address = 0xfffc1309; sn = "SIUL2_GPDO9"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO10 { address = 0xfffc130a; sn = "SIUL2_GPDO10"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO11 { address = 0xfffc130b; sn = "SIUL2_GPDO11"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO12 { address = 0xfffc130c; sn = "SIUL2_GPDO12"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO13 { address = 0xfffc130d; sn = "SIUL2_GPDO13"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO14 { address = 0xfffc130e; sn = "SIUL2_GPDO14"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO15 { address = 0xfffc130f; sn = "SIUL2_GPDO15"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO16 { address = 0xfffc1310; sn = "SIUL2_GPDO16"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO17 { address = 0xfffc1311; sn = "SIUL2_GPDO17"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO18 { address = 0xfffc1312; sn = "SIUL2_GPDO18"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO19 { address = 0xfffc1313; sn = "SIUL2_GPDO19"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO20 { address = 0xfffc1314; sn = "SIUL2_GPDO20"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO21 { address = 0xfffc1315; sn = "SIUL2_GPDO21"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO22 { address = 0xfffc1316; sn = "SIUL2_GPDO22"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO23 { address = 0xfffc1317; sn = "SIUL2_GPDO23"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO24 { address = 0xfffc1318; sn = "SIUL2_GPDO24"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO25 { address = 0xfffc1319; sn = "SIUL2_GPDO25"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO26 { address = 0xfffc131a; sn = "SIUL2_GPDO26"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO27 { address = 0xfffc131b; sn = "SIUL2_GPDO27"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO28 { address = 0xfffc131c; sn = "SIUL2_GPDO28"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO29 { address = 0xfffc131d; sn = "SIUL2_GPDO29"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO30 { address = 0xfffc131e; sn = "SIUL2_GPDO30"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO31 { address = 0xfffc131f; sn = "SIUL2_GPDO31"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO32 { address = 0xfffc1320; sn = "SIUL2_GPDO32"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO33 { address = 0xfffc1321; sn = "SIUL2_GPDO33"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO34 { address = 0xfffc1322; sn = "SIUL2_GPDO34"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO35 { address = 0xfffc1323; sn = "SIUL2_GPDO35"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO36 { address = 0xfffc1324; sn = "SIUL2_GPDO36"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO37 { address = 0xfffc1325; sn = "SIUL2_GPDO37"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO38 { address = 0xfffc1326; sn = "SIUL2_GPDO38"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO39 { address = 0xfffc1327; sn = "SIUL2_GPDO39"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO40 { address = 0xfffc1328; sn = "SIUL2_GPDO40"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO41 { address = 0xfffc1329; sn = "SIUL2_GPDO41"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO42 { address = 0xfffc132a; sn = "SIUL2_GPDO42"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO43 { address = 0xfffc132b; sn = "SIUL2_GPDO43"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO44 { address = 0xfffc132c; sn = "SIUL2_GPDO44"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO45 { address = 0xfffc132d; sn = "SIUL2_GPDO45"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO46 { address = 0xfffc132e; sn = "SIUL2_GPDO46"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO47 { address = 0xfffc132f; sn = "SIUL2_GPDO47"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO48 { address = 0xfffc1330; sn = "SIUL2_GPDO48"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO49 { address = 0xfffc1331; sn = "SIUL2_GPDO49"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO50 { address = 0xfffc1332; sn = "SIUL2_GPDO50"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO51 { address = 0xfffc1333; sn = "SIUL2_GPDO51"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO52 { address = 0xfffc1334; sn = "SIUL2_GPDO52"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO53 { address = 0xfffc1335; sn = "SIUL2_GPDO53"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO54 { address = 0xfffc1336; sn = "SIUL2_GPDO54"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO55 { address = 0xfffc1337; sn = "SIUL2_GPDO55"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO56 { address = 0xfffc1338; sn = "SIUL2_GPDO56"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO57 { address = 0xfffc1339; sn = "SIUL2_GPDO57"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO58 { address = 0xfffc133a; sn = "SIUL2_GPDO58"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO59 { address = 0xfffc133b; sn = "SIUL2_GPDO59"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO60 { address = 0xfffc133c; sn = "SIUL2_GPDO60"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO61 { address = 0xfffc133d; sn = "SIUL2_GPDO61"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO62 { address = 0xfffc133e; sn = "SIUL2_GPDO62"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO63 { address = 0xfffc133f; sn = "SIUL2_GPDO63"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO64 { address = 0xfffc1340; sn = "SIUL2_GPDO64"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO65 { address = 0xfffc1341; sn = "SIUL2_GPDO65"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO66 { address = 0xfffc1342; sn = "SIUL2_GPDO66"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO67 { address = 0xfffc1343; sn = "SIUL2_GPDO67"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO68 { address = 0xfffc1344; sn = "SIUL2_GPDO68"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO69 { address = 0xfffc1345; sn = "SIUL2_GPDO69"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO70 { address = 0xfffc1346; sn = "SIUL2_GPDO70"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO71 { address = 0xfffc1347; sn = "SIUL2_GPDO71"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO72 { address = 0xfffc1348; sn = "SIUL2_GPDO72"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO73 { address = 0xfffc1349; sn = "SIUL2_GPDO73"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO74 { address = 0xfffc134a; sn = "SIUL2_GPDO74"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO75 { address = 0xfffc134b; sn = "SIUL2_GPDO75"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO76 { address = 0xfffc134c; sn = "SIUL2_GPDO76"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO77 { address = 0xfffc134d; sn = "SIUL2_GPDO77"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO78 { address = 0xfffc134e; sn = "SIUL2_GPDO78"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO79 { address = 0xfffc134f; sn = "SIUL2_GPDO79"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO80 { address = 0xfffc1350; sn = "SIUL2_GPDO80"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO81 { address = 0xfffc1351; sn = "SIUL2_GPDO81"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO82 { address = 0xfffc1352; sn = "SIUL2_GPDO82"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO83 { address = 0xfffc1353; sn = "SIUL2_GPDO83"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO84 { address = 0xfffc1354; sn = "SIUL2_GPDO84"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO85 { address = 0xfffc1355; sn = "SIUL2_GPDO85"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO86 { address = 0xfffc1356; sn = "SIUL2_GPDO86"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO87 { address = 0xfffc1357; sn = "SIUL2_GPDO87"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO88 { address = 0xfffc1358; sn = "SIUL2_GPDO88"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO89 { address = 0xfffc1359; sn = "SIUL2_GPDO89"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO90 { address = 0xfffc135a; sn = "SIUL2_GPDO90"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO91 { address = 0xfffc135b; sn = "SIUL2_GPDO91"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO92 { address = 0xfffc135c; sn = "SIUL2_GPDO92"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO93 { address = 0xfffc135d; sn = "SIUL2_GPDO93"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO94 { address = 0xfffc135e; sn = "SIUL2_GPDO94"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO95 { address = 0xfffc135f; sn = "SIUL2_GPDO95"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO96 { address = 0xfffc1360; sn = "SIUL2_GPDO96"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO97 { address = 0xfffc1361; sn = "SIUL2_GPDO97"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO98 { address = 0xfffc1362; sn = "SIUL2_GPDO98"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO99 { address = 0xfffc1363; sn = "SIUL2_GPDO99"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO100 { address = 0xfffc1364; sn = "SIUL2_GPDO100"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO101 { address = 0xfffc1365; sn = "SIUL2_GPDO101"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO102 { address = 0xfffc1366; sn = "SIUL2_GPDO102"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO103 { address = 0xfffc1367; sn = "SIUL2_GPDO103"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO104 { address = 0xfffc1368; sn = "SIUL2_GPDO104"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO105 { address = 0xfffc1369; sn = "SIUL2_GPDO105"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO106 { address = 0xfffc136a; sn = "SIUL2_GPDO106"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO107 { address = 0xfffc136b; sn = "SIUL2_GPDO107"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO108 { address = 0xfffc136c; sn = "SIUL2_GPDO108"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO109 { address = 0xfffc136d; sn = "SIUL2_GPDO109"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO110 { address = 0xfffc136e; sn = "SIUL2_GPDO110"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO111 { address = 0xfffc136f; sn = "SIUL2_GPDO111"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO112 { address = 0xfffc1370; sn = "SIUL2_GPDO112"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO113 { address = 0xfffc1371; sn = "SIUL2_GPDO113"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO114 { address = 0xfffc1372; sn = "SIUL2_GPDO114"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO115 { address = 0xfffc1373; sn = "SIUL2_GPDO115"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO116 { address = 0xfffc1374; sn = "SIUL2_GPDO116"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO117 { address = 0xfffc1375; sn = "SIUL2_GPDO117"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO118 { address = 0xfffc1376; sn = "SIUL2_GPDO118"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO119 { address = 0xfffc1377; sn = "SIUL2_GPDO119"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO120 { address = 0xfffc1378; sn = "SIUL2_GPDO120"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO121 { address = 0xfffc1379; sn = "SIUL2_GPDO121"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO122 { address = 0xfffc137a; sn = "SIUL2_GPDO122"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO123 { address = 0xfffc137b; sn = "SIUL2_GPDO123"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO124 { address = 0xfffc137c; sn = "SIUL2_GPDO124"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO125 { address = 0xfffc137d; sn = "SIUL2_GPDO125"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO126 { address = 0xfffc137e; sn = "SIUL2_GPDO126"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO127 { address = 0xfffc137f; sn = "SIUL2_GPDO127"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO128 { address = 0xfffc1380; sn = "SIUL2_GPDO128"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO129 { address = 0xfffc1381; sn = "SIUL2_GPDO129"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO130 { address = 0xfffc1382; sn = "SIUL2_GPDO130"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO131 { address = 0xfffc1383; sn = "SIUL2_GPDO131"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO132 { address = 0xfffc1384; sn = "SIUL2_GPDO132"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO133 { address = 0xfffc1385; sn = "SIUL2_GPDO133"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO134 { address = 0xfffc1386; sn = "SIUL2_GPDO134"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO135 { address = 0xfffc1387; sn = "SIUL2_GPDO135"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO136 { address = 0xfffc1388; sn = "SIUL2_GPDO136"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO137 { address = 0xfffc1389; sn = "SIUL2_GPDO137"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO138 { address = 0xfffc138a; sn = "SIUL2_GPDO138"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO139 { address = 0xfffc138b; sn = "SIUL2_GPDO139"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO140 { address = 0xfffc138c; sn = "SIUL2_GPDO140"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO141 { address = 0xfffc138d; sn = "SIUL2_GPDO141"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO142 { address = 0xfffc138e; sn = "SIUL2_GPDO142"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO143 { address = 0xfffc138f; sn = "SIUL2_GPDO143"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO144 { address = 0xfffc1390; sn = "SIUL2_GPDO144"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO145 { address = 0xfffc1391; sn = "SIUL2_GPDO145"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO146 { address = 0xfffc1392; sn = "SIUL2_GPDO146"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO147 { address = 0xfffc1393; sn = "SIUL2_GPDO147"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO148 { address = 0xfffc1394; sn = "SIUL2_GPDO148"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO149 { address = 0xfffc1395; sn = "SIUL2_GPDO149"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO150 { address = 0xfffc1396; sn = "SIUL2_GPDO150"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO151 { address = 0xfffc1397; sn = "SIUL2_GPDO151"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO152 { address = 0xfffc1398; sn = "SIUL2_GPDO152"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO153 { address = 0xfffc1399; sn = "SIUL2_GPDO153"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO154 { address = 0xfffc139a; sn = "SIUL2_GPDO154"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO155 { address = 0xfffc139b; sn = "SIUL2_GPDO155"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO156 { address = 0xfffc139c; sn = "SIUL2_GPDO156"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO157 { address = 0xfffc139d; sn = "SIUL2_GPDO157"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO158 { address = 0xfffc139e; sn = "SIUL2_GPDO158"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO159 { address = 0xfffc139f; sn = "SIUL2_GPDO159"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO160 { address = 0xfffc13a0; sn = "SIUL2_GPDO160"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO161 { address = 0xfffc13a1; sn = "SIUL2_GPDO161"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO162 { address = 0xfffc13a2; sn = "SIUL2_GPDO162"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO163 { address = 0xfffc13a3; sn = "SIUL2_GPDO163"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO164 { address = 0xfffc13a4; sn = "SIUL2_GPDO164"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO165 { address = 0xfffc13a5; sn = "SIUL2_GPDO165"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO166 { address = 0xfffc13a6; sn = "SIUL2_GPDO166"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO167 { address = 0xfffc13a7; sn = "SIUL2_GPDO167"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO168 { address = 0xfffc13a8; sn = "SIUL2_GPDO168"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO169 { address = 0xfffc13a9; sn = "SIUL2_GPDO169"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO170 { address = 0xfffc13aa; sn = "SIUL2_GPDO170"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO171 { address = 0xfffc13ab; sn = "SIUL2_GPDO171"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO172 { address = 0xfffc13ac; sn = "SIUL2_GPDO172"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO173 { address = 0xfffc13ad; sn = "SIUL2_GPDO173"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO174 { address = 0xfffc13ae; sn = "SIUL2_GPDO174"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO175 { address = 0xfffc13af; sn = "SIUL2_GPDO175"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO176 { address = 0xfffc13b0; sn = "SIUL2_GPDO176"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO177 { address = 0xfffc13b1; sn = "SIUL2_GPDO177"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO178 { address = 0xfffc13b2; sn = "SIUL2_GPDO178"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO179 { address = 0xfffc13b3; sn = "SIUL2_GPDO179"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO180 { address = 0xfffc13b4; sn = "SIUL2_GPDO180"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO181 { address = 0xfffc13b5; sn = "SIUL2_GPDO181"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO182 { address = 0xfffc13b6; sn = "SIUL2_GPDO182"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO183 { address = 0xfffc13b7; sn = "SIUL2_GPDO183"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO184 { address = 0xfffc13b8; sn = "SIUL2_GPDO184"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO185 { address = 0xfffc13b9; sn = "SIUL2_GPDO185"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO186 { address = 0xfffc13ba; sn = "SIUL2_GPDO186"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO187 { address = 0xfffc13bb; sn = "SIUL2_GPDO187"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO188 { address = 0xfffc13bc; sn = "SIUL2_GPDO188"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO189 { address = 0xfffc13bd; sn = "SIUL2_GPDO189"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO190 { address = 0xfffc13be; sn = "SIUL2_GPDO190"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO191 { address = 0xfffc13bf; sn = "SIUL2_GPDO191"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO192 { address = 0xfffc13c0; sn = "SIUL2_GPDO192"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO193 { address = 0xfffc13c1; sn = "SIUL2_GPDO193"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO194 { address = 0xfffc13c2; sn = "SIUL2_GPDO194"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO195 { address = 0xfffc13c3; sn = "SIUL2_GPDO195"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO196 { address = 0xfffc13c4; sn = "SIUL2_GPDO196"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO197 { address = 0xfffc13c5; sn = "SIUL2_GPDO197"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO198 { address = 0xfffc13c6; sn = "SIUL2_GPDO198"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO199 { address = 0xfffc13c7; sn = "SIUL2_GPDO199"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO200 { address = 0xfffc13c8; sn = "SIUL2_GPDO200"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO201 { address = 0xfffc13c9; sn = "SIUL2_GPDO201"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO202 { address = 0xfffc13ca; sn = "SIUL2_GPDO202"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO203 { address = 0xfffc13cb; sn = "SIUL2_GPDO203"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO204 { address = 0xfffc13cc; sn = "SIUL2_GPDO204"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO205 { address = 0xfffc13cd; sn = "SIUL2_GPDO205"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO206 { address = 0xfffc13ce; sn = "SIUL2_GPDO206"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO207 { address = 0xfffc13cf; sn = "SIUL2_GPDO207"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO208 { address = 0xfffc13d0; sn = "SIUL2_GPDO208"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO209 { address = 0xfffc13d1; sn = "SIUL2_GPDO209"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO210 { address = 0xfffc13d2; sn = "SIUL2_GPDO210"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO211 { address = 0xfffc13d3; sn = "SIUL2_GPDO211"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO212 { address = 0xfffc13d4; sn = "SIUL2_GPDO212"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO213 { address = 0xfffc13d5; sn = "SIUL2_GPDO213"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO214 { address = 0xfffc13d6; sn = "SIUL2_GPDO214"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO215 { address = 0xfffc13d7; sn = "SIUL2_GPDO215"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO216 { address = 0xfffc13d8; sn = "SIUL2_GPDO216"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO217 { address = 0xfffc13d9; sn = "SIUL2_GPDO217"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO218 { address = 0xfffc13da; sn = "SIUL2_GPDO218"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO219 { address = 0xfffc13db; sn = "SIUL2_GPDO219"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO220 { address = 0xfffc13dc; sn = "SIUL2_GPDO220"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO221 { address = 0xfffc13dd; sn = "SIUL2_GPDO221"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO222 { address = 0xfffc13de; sn = "SIUL2_GPDO222"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO223 { address = 0xfffc13df; sn = "SIUL2_GPDO223"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO224 { address = 0xfffc13e0; sn = "SIUL2_GPDO224"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO225 { address = 0xfffc13e1; sn = "SIUL2_GPDO225"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO226 { address = 0xfffc13e2; sn = "SIUL2_GPDO226"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO227 { address = 0xfffc13e3; sn = "SIUL2_GPDO227"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO228 { address = 0xfffc13e4; sn = "SIUL2_GPDO228"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO229 { address = 0xfffc13e5; sn = "SIUL2_GPDO229"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO230 { address = 0xfffc13e6; sn = "SIUL2_GPDO230"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO231 { address = 0xfffc13e7; sn = "SIUL2_GPDO231"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO232 { address = 0xfffc13e8; sn = "SIUL2_GPDO232"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO233 { address = 0xfffc13e9; sn = "SIUL2_GPDO233"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO234 { address = 0xfffc13ea; sn = "SIUL2_GPDO234"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO235 { address = 0xfffc13eb; sn = "SIUL2_GPDO235"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO236 { address = 0xfffc13ec; sn = "SIUL2_GPDO236"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO237 { address = 0xfffc13ed; sn = "SIUL2_GPDO237"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO238 { address = 0xfffc13ee; sn = "SIUL2_GPDO238"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO239 { address = 0xfffc13ef; sn = "SIUL2_GPDO239"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO240 { address = 0xfffc13f0; sn = "SIUL2_GPDO240"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO241 { address = 0xfffc13f1; sn = "SIUL2_GPDO241"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO242 { address = 0xfffc13f2; sn = "SIUL2_GPDO242"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO243 { address = 0xfffc13f3; sn = "SIUL2_GPDO243"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO244 { address = 0xfffc13f4; sn = "SIUL2_GPDO244"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO245 { address = 0xfffc13f5; sn = "SIUL2_GPDO245"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO246 { address = 0xfffc13f6; sn = "SIUL2_GPDO246"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO247 { address = 0xfffc13f7; sn = "SIUL2_GPDO247"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO248 { address = 0xfffc13f8; sn = "SIUL2_GPDO248"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO249 { address = 0xfffc13f9; sn = "SIUL2_GPDO249"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO250 { address = 0xfffc13fa; sn = "SIUL2_GPDO250"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO251 { address = 0xfffc13fb; sn = "SIUL2_GPDO251"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO252 { address = 0xfffc13fc; sn = "SIUL2_GPDO252"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO253 { address = 0xfffc13fd; sn = "SIUL2_GPDO253"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO254 { address = 0xfffc13fe; sn = "SIUL2_GPDO254"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO255 { address = 0xfffc13ff; sn = "SIUL2_GPDO255"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO256 { address = 0xfffc1400; sn = "SIUL2_GPDO256"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO257 { address = 0xfffc1401; sn = "SIUL2_GPDO257"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO258 { address = 0xfffc1402; sn = "SIUL2_GPDO258"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO259 { address = 0xfffc1403; sn = "SIUL2_GPDO259"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO260 { address = 0xfffc1404; sn = "SIUL2_GPDO260"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO261 { address = 0xfffc1405; sn = "SIUL2_GPDO261"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO262 { address = 0xfffc1406; sn = "SIUL2_GPDO262"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO263 { address = 0xfffc1407; sn = "SIUL2_GPDO263"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO264 { address = 0xfffc1408; sn = "SIUL2_GPDO264"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO265 { address = 0xfffc1409; sn = "SIUL2_GPDO265"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO266 { address = 0xfffc140a; sn = "SIUL2_GPDO266"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO267 { address = 0xfffc140b; sn = "SIUL2_GPDO267"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO268 { address = 0xfffc140c; sn = "SIUL2_GPDO268"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO269 { address = 0xfffc140d; sn = "SIUL2_GPDO269"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO270 { address = 0xfffc140e; sn = "SIUL2_GPDO270"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO271 { address = 0xfffc140f; sn = "SIUL2_GPDO271"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO272 { address = 0xfffc1410; sn = "SIUL2_GPDO272"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO273 { address = 0xfffc1411; sn = "SIUL2_GPDO273"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO274 { address = 0xfffc1412; sn = "SIUL2_GPDO274"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO275 { address = 0xfffc1413; sn = "SIUL2_GPDO275"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO276 { address = 0xfffc1414; sn = "SIUL2_GPDO276"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO277 { address = 0xfffc1415; sn = "SIUL2_GPDO277"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO278 { address = 0xfffc1416; sn = "SIUL2_GPDO278"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO279 { address = 0xfffc1417; sn = "SIUL2_GPDO279"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO280 { address = 0xfffc1418; sn = "SIUL2_GPDO280"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO281 { address = 0xfffc1419; sn = "SIUL2_GPDO281"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO282 { address = 0xfffc141a; sn = "SIUL2_GPDO282"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO283 { address = 0xfffc141b; sn = "SIUL2_GPDO283"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO284 { address = 0xfffc141c; sn = "SIUL2_GPDO284"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO285 { address = 0xfffc141d; sn = "SIUL2_GPDO285"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO286 { address = 0xfffc141e; sn = "SIUL2_GPDO286"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO287 { address = 0xfffc141f; sn = "SIUL2_GPDO287"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO288 { address = 0xfffc1420; sn = "SIUL2_GPDO288"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO289 { address = 0xfffc1421; sn = "SIUL2_GPDO289"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO290 { address = 0xfffc1422; sn = "SIUL2_GPDO290"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO291 { address = 0xfffc1423; sn = "SIUL2_GPDO291"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO292 { address = 0xfffc1424; sn = "SIUL2_GPDO292"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO293 { address = 0xfffc1425; sn = "SIUL2_GPDO293"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO294 { address = 0xfffc1426; sn = "SIUL2_GPDO294"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO295 { address = 0xfffc1427; sn = "SIUL2_GPDO295"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO296 { address = 0xfffc1428; sn = "SIUL2_GPDO296"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO297 { address = 0xfffc1429; sn = "SIUL2_GPDO297"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO298 { address = 0xfffc142a; sn = "SIUL2_GPDO298"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO299 { address = 0xfffc142b; sn = "SIUL2_GPDO299"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO300 { address = 0xfffc142c; sn = "SIUL2_GPDO300"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO301 { address = 0xfffc142d; sn = "SIUL2_GPDO301"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO302 { address = 0xfffc142e; sn = "SIUL2_GPDO302"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO303 { address = 0xfffc142f; sn = "SIUL2_GPDO303"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO304 { address = 0xfffc1430; sn = "SIUL2_GPDO304"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO305 { address = 0xfffc1431; sn = "SIUL2_GPDO305"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO306 { address = 0xfffc1432; sn = "SIUL2_GPDO306"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO307 { address = 0xfffc1433; sn = "SIUL2_GPDO307"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO308 { address = 0xfffc1434; sn = "SIUL2_GPDO308"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO309 { address = 0xfffc1435; sn = "SIUL2_GPDO309"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO310 { address = 0xfffc1436; sn = "SIUL2_GPDO310"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO311 { address = 0xfffc1437; sn = "SIUL2_GPDO311"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO312 { address = 0xfffc1438; sn = "SIUL2_GPDO312"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO313 { address = 0xfffc1439; sn = "SIUL2_GPDO313"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO314 { address = 0xfffc143a; sn = "SIUL2_GPDO314"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO315 { address = 0xfffc143b; sn = "SIUL2_GPDO315"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO316 { address = 0xfffc143c; sn = "SIUL2_GPDO316"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO317 { address = 0xfffc143d; sn = "SIUL2_GPDO317"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO318 { address = 0xfffc143e; sn = "SIUL2_GPDO318"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO319 { address = 0xfffc143f; sn = "SIUL2_GPDO319"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO320 { address = 0xfffc1440; sn = "SIUL2_GPDO320"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO321 { address = 0xfffc1441; sn = "SIUL2_GPDO321"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO322 { address = 0xfffc1442; sn = "SIUL2_GPDO322"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO323 { address = 0xfffc1443; sn = "SIUL2_GPDO323"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO324 { address = 0xfffc1444; sn = "SIUL2_GPDO324"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO325 { address = 0xfffc1445; sn = "SIUL2_GPDO325"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO326 { address = 0xfffc1446; sn = "SIUL2_GPDO326"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO327 { address = 0xfffc1447; sn = "SIUL2_GPDO327"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO328 { address = 0xfffc1448; sn = "SIUL2_GPDO328"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO329 { address = 0xfffc1449; sn = "SIUL2_GPDO329"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO330 { address = 0xfffc144a; sn = "SIUL2_GPDO330"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO331 { address = 0xfffc144b; sn = "SIUL2_GPDO331"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO332 { address = 0xfffc144c; sn = "SIUL2_GPDO332"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO333 { address = 0xfffc144d; sn = "SIUL2_GPDO333"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO334 { address = 0xfffc144e; sn = "SIUL2_GPDO334"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO335 { address = 0xfffc144f; sn = "SIUL2_GPDO335"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO336 { address = 0xfffc1450; sn = "SIUL2_GPDO336"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO337 { address = 0xfffc1451; sn = "SIUL2_GPDO337"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO338 { address = 0xfffc1452; sn = "SIUL2_GPDO338"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO339 { address = 0xfffc1453; sn = "SIUL2_GPDO339"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO340 { address = 0xfffc1454; sn = "SIUL2_GPDO340"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO341 { address = 0xfffc1455; sn = "SIUL2_GPDO341"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO342 { address = 0xfffc1456; sn = "SIUL2_GPDO342"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO343 { address = 0xfffc1457; sn = "SIUL2_GPDO343"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO344 { address = 0xfffc1458; sn = "SIUL2_GPDO344"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO345 { address = 0xfffc1459; sn = "SIUL2_GPDO345"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO346 { address = 0xfffc145a; sn = "SIUL2_GPDO346"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO347 { address = 0xfffc145b; sn = "SIUL2_GPDO347"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO348 { address = 0xfffc145c; sn = "SIUL2_GPDO348"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO349 { address = 0xfffc145d; sn = "SIUL2_GPDO349"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO350 { address = 0xfffc145e; sn = "SIUL2_GPDO350"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO351 { address = 0xfffc145f; sn = "SIUL2_GPDO351"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO352 { address = 0xfffc1460; sn = "SIUL2_GPDO352"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO353 { address = 0xfffc1461; sn = "SIUL2_GPDO353"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO354 { address = 0xfffc1462; sn = "SIUL2_GPDO354"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO355 { address = 0xfffc1463; sn = "SIUL2_GPDO355"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO356 { address = 0xfffc1464; sn = "SIUL2_GPDO356"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO357 { address = 0xfffc1465; sn = "SIUL2_GPDO357"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO358 { address = 0xfffc1466; sn = "SIUL2_GPDO358"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO359 { address = 0xfffc1467; sn = "SIUL2_GPDO359"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO360 { address = 0xfffc1468; sn = "SIUL2_GPDO360"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO361 { address = 0xfffc1469; sn = "SIUL2_GPDO361"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO362 { address = 0xfffc146a; sn = "SIUL2_GPDO362"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO363 { address = 0xfffc146b; sn = "SIUL2_GPDO363"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO364 { address = 0xfffc146c; sn = "SIUL2_GPDO364"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO365 { address = 0xfffc146d; sn = "SIUL2_GPDO365"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO366 { address = 0xfffc146e; sn = "SIUL2_GPDO366"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO367 { address = 0xfffc146f; sn = "SIUL2_GPDO367"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO368 { address = 0xfffc1470; sn = "SIUL2_GPDO368"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO369 { address = 0xfffc1471; sn = "SIUL2_GPDO369"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO370 { address = 0xfffc1472; sn = "SIUL2_GPDO370"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO371 { address = 0xfffc1473; sn = "SIUL2_GPDO371"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO372 { address = 0xfffc1474; sn = "SIUL2_GPDO372"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO373 { address = 0xfffc1475; sn = "SIUL2_GPDO373"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO374 { address = 0xfffc1476; sn = "SIUL2_GPDO374"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO375 { address = 0xfffc1477; sn = "SIUL2_GPDO375"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO376 { address = 0xfffc1478; sn = "SIUL2_GPDO376"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO377 { address = 0xfffc1479; sn = "SIUL2_GPDO377"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO378 { address = 0xfffc147a; sn = "SIUL2_GPDO378"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO379 { address = 0xfffc147b; sn = "SIUL2_GPDO379"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO380 { address = 0xfffc147c; sn = "SIUL2_GPDO380"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO381 { address = 0xfffc147d; sn = "SIUL2_GPDO381"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO382 { address = 0xfffc147e; sn = "SIUL2_GPDO382"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO383 { address = 0xfffc147f; sn = "SIUL2_GPDO383"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO384 { address = 0xfffc1480; sn = "SIUL2_GPDO384"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO385 { address = 0xfffc1481; sn = "SIUL2_GPDO385"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO386 { address = 0xfffc1482; sn = "SIUL2_GPDO386"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO387 { address = 0xfffc1483; sn = "SIUL2_GPDO387"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO388 { address = 0xfffc1484; sn = "SIUL2_GPDO388"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO389 { address = 0xfffc1485; sn = "SIUL2_GPDO389"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO390 { address = 0xfffc1486; sn = "SIUL2_GPDO390"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO391 { address = 0xfffc1487; sn = "SIUL2_GPDO391"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO392 { address = 0xfffc1488; sn = "SIUL2_GPDO392"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO393 { address = 0xfffc1489; sn = "SIUL2_GPDO393"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO394 { address = 0xfffc148a; sn = "SIUL2_GPDO394"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO395 { address = 0xfffc148b; sn = "SIUL2_GPDO395"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO396 { address = 0xfffc148c; sn = "SIUL2_GPDO396"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO397 { address = 0xfffc148d; sn = "SIUL2_GPDO397"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO398 { address = 0xfffc148e; sn = "SIUL2_GPDO398"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO399 { address = 0xfffc148f; sn = "SIUL2_GPDO399"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO400 { address = 0xfffc1490; sn = "SIUL2_GPDO400"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO401 { address = 0xfffc1491; sn = "SIUL2_GPDO401"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO402 { address = 0xfffc1492; sn = "SIUL2_GPDO402"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO403 { address = 0xfffc1493; sn = "SIUL2_GPDO403"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO404 { address = 0xfffc1494; sn = "SIUL2_GPDO404"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO405 { address = 0xfffc1495; sn = "SIUL2_GPDO405"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO406 { address = 0xfffc1496; sn = "SIUL2_GPDO406"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO407 { address = 0xfffc1497; sn = "SIUL2_GPDO407"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO408 { address = 0xfffc1498; sn = "SIUL2_GPDO408"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO409 { address = 0xfffc1499; sn = "SIUL2_GPDO409"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO410 { address = 0xfffc149a; sn = "SIUL2_GPDO410"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO411 { address = 0xfffc149b; sn = "SIUL2_GPDO411"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO412 { address = 0xfffc149c; sn = "SIUL2_GPDO412"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO413 { address = 0xfffc149d; sn = "SIUL2_GPDO413"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO414 { address = 0xfffc149e; sn = "SIUL2_GPDO414"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO415 { address = 0xfffc149f; sn = "SIUL2_GPDO415"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO416 { address = 0xfffc14a0; sn = "SIUL2_GPDO416"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO417 { address = 0xfffc14a1; sn = "SIUL2_GPDO417"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO418 { address = 0xfffc14a2; sn = "SIUL2_GPDO418"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO419 { address = 0xfffc14a3; sn = "SIUL2_GPDO419"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO420 { address = 0xfffc14a4; sn = "SIUL2_GPDO420"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO421 { address = 0xfffc14a5; sn = "SIUL2_GPDO421"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO422 { address = 0xfffc14a6; sn = "SIUL2_GPDO422"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO423 { address = 0xfffc14a7; sn = "SIUL2_GPDO423"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO424 { address = 0xfffc14a8; sn = "SIUL2_GPDO424"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO425 { address = 0xfffc14a9; sn = "SIUL2_GPDO425"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO426 { address = 0xfffc14aa; sn = "SIUL2_GPDO426"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO427 { address = 0xfffc14ab; sn = "SIUL2_GPDO427"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO428 { address = 0xfffc14ac; sn = "SIUL2_GPDO428"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO429 { address = 0xfffc14ad; sn = "SIUL2_GPDO429"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO430 { address = 0xfffc14ae; sn = "SIUL2_GPDO430"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO431 { address = 0xfffc14af; sn = "SIUL2_GPDO431"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO432 { address = 0xfffc14b0; sn = "SIUL2_GPDO432"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO433 { address = 0xfffc14b1; sn = "SIUL2_GPDO433"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO434 { address = 0xfffc14b2; sn = "SIUL2_GPDO434"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO435 { address = 0xfffc14b3; sn = "SIUL2_GPDO435"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO436 { address = 0xfffc14b4; sn = "SIUL2_GPDO436"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO437 { address = 0xfffc14b5; sn = "SIUL2_GPDO437"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO438 { address = 0xfffc14b6; sn = "SIUL2_GPDO438"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO439 { address = 0xfffc14b7; sn = "SIUL2_GPDO439"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO440 { address = 0xfffc14b8; sn = "SIUL2_GPDO440"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO441 { address = 0xfffc14b9; sn = "SIUL2_GPDO441"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO442 { address = 0xfffc14ba; sn = "SIUL2_GPDO442"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO443 { address = 0xfffc14bb; sn = "SIUL2_GPDO443"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO444 { address = 0xfffc14bc; sn = "SIUL2_GPDO444"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO445 { address = 0xfffc14bd; sn = "SIUL2_GPDO445"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO446 { address = 0xfffc14be; sn = "SIUL2_GPDO446"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO447 { address = 0xfffc14bf; sn = "SIUL2_GPDO447"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO448 { address = 0xfffc14c0; sn = "SIUL2_GPDO448"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO449 { address = 0xfffc14c1; sn = "SIUL2_GPDO449"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO450 { address = 0xfffc14c2; sn = "SIUL2_GPDO450"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO451 { address = 0xfffc14c3; sn = "SIUL2_GPDO451"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO452 { address = 0xfffc14c4; sn = "SIUL2_GPDO452"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO453 { address = 0xfffc14c5; sn = "SIUL2_GPDO453"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO454 { address = 0xfffc14c6; sn = "SIUL2_GPDO454"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO455 { address = 0xfffc14c7; sn = "SIUL2_GPDO455"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO456 { address = 0xfffc14c8; sn = "SIUL2_GPDO456"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO457 { address = 0xfffc14c9; sn = "SIUL2_GPDO457"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO458 { address = 0xfffc14ca; sn = "SIUL2_GPDO458"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO459 { address = 0xfffc14cb; sn = "SIUL2_GPDO459"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO460 { address = 0xfffc14cc; sn = "SIUL2_GPDO460"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO461 { address = 0xfffc14cd; sn = "SIUL2_GPDO461"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO462 { address = 0xfffc14ce; sn = "SIUL2_GPDO462"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO463 { address = 0xfffc14cf; sn = "SIUL2_GPDO463"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO464 { address = 0xfffc14d0; sn = "SIUL2_GPDO464"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO465 { address = 0xfffc14d1; sn = "SIUL2_GPDO465"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO466 { address = 0xfffc14d2; sn = "SIUL2_GPDO466"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO467 { address = 0xfffc14d3; sn = "SIUL2_GPDO467"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO468 { address = 0xfffc14d4; sn = "SIUL2_GPDO468"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO469 { address = 0xfffc14d5; sn = "SIUL2_GPDO469"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO470 { address = 0xfffc14d6; sn = "SIUL2_GPDO470"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO471 { address = 0xfffc14d7; sn = "SIUL2_GPDO471"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO472 { address = 0xfffc14d8; sn = "SIUL2_GPDO472"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO473 { address = 0xfffc14d9; sn = "SIUL2_GPDO473"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO474 { address = 0xfffc14da; sn = "SIUL2_GPDO474"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO475 { address = 0xfffc14db; sn = "SIUL2_GPDO475"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO476 { address = 0xfffc14dc; sn = "SIUL2_GPDO476"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO477 { address = 0xfffc14dd; sn = "SIUL2_GPDO477"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO478 { address = 0xfffc14de; sn = "SIUL2_GPDO478"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO479 { address = 0xfffc14df; sn = "SIUL2_GPDO479"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO480 { address = 0xfffc14e0; sn = "SIUL2_GPDO480"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO481 { address = 0xfffc14e1; sn = "SIUL2_GPDO481"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO482 { address = 0xfffc14e2; sn = "SIUL2_GPDO482"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO483 { address = 0xfffc14e3; sn = "SIUL2_GPDO483"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO484 { address = 0xfffc14e4; sn = "SIUL2_GPDO484"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO485 { address = 0xfffc14e5; sn = "SIUL2_GPDO485"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO486 { address = 0xfffc14e6; sn = "SIUL2_GPDO486"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO487 { address = 0xfffc14e7; sn = "SIUL2_GPDO487"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO488 { address = 0xfffc14e8; sn = "SIUL2_GPDO488"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO489 { address = 0xfffc14e9; sn = "SIUL2_GPDO489"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO490 { address = 0xfffc14ea; sn = "SIUL2_GPDO490"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO491 { address = 0xfffc14eb; sn = "SIUL2_GPDO491"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO492 { address = 0xfffc14ec; sn = "SIUL2_GPDO492"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO493 { address = 0xfffc14ed; sn = "SIUL2_GPDO493"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO494 { address = 0xfffc14ee; sn = "SIUL2_GPDO494"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO495 { address = 0xfffc14ef; sn = "SIUL2_GPDO495"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO496 { address = 0xfffc14f0; sn = "SIUL2_GPDO496"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO497 { address = 0xfffc14f1; sn = "SIUL2_GPDO497"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO498 { address = 0xfffc14f2; sn = "SIUL2_GPDO498"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO499 { address = 0xfffc14f3; sn = "SIUL2_GPDO499"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO500 { address = 0xfffc14f4; sn = "SIUL2_GPDO500"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO501 { address = 0xfffc14f5; sn = "SIUL2_GPDO501"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO502 { address = 0xfffc14f6; sn = "SIUL2_GPDO502"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO503 { address = 0xfffc14f7; sn = "SIUL2_GPDO503"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO504 { address = 0xfffc14f8; sn = "SIUL2_GPDO504"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO505 { address = 0xfffc14f9; sn = "SIUL2_GPDO505"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO506 { address = 0xfffc14fa; sn = "SIUL2_GPDO506"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO507 { address = 0xfffc14fb; sn = "SIUL2_GPDO507"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO508 { address = 0xfffc14fc; sn = "SIUL2_GPDO508"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO509 { address = 0xfffc14fd; sn = "SIUL2_GPDO509"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO510 { address = 0xfffc14fe; sn = "SIUL2_GPDO510"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDO511 { address = 0xfffc14ff; sn = "SIUL2_GPDO511"; access = "memorymapped"; width = 8; ${_DESC2161_}; type = "bitfield_SIUL2_GPDO0" } SIUL2_GPDI0 { address = 0xfffc1500; sn = "SIUL2_GPDI0"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI1 { address = 0xfffc1501; sn = "SIUL2_GPDI1"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI2 { address = 0xfffc1502; sn = "SIUL2_GPDI2"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI3 { address = 0xfffc1503; sn = "SIUL2_GPDI3"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI4 { address = 0xfffc1504; sn = "SIUL2_GPDI4"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI5 { address = 0xfffc1505; sn = "SIUL2_GPDI5"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI6 { address = 0xfffc1506; sn = "SIUL2_GPDI6"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI7 { address = 0xfffc1507; sn = "SIUL2_GPDI7"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI8 { address = 0xfffc1508; sn = "SIUL2_GPDI8"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI9 { address = 0xfffc1509; sn = "SIUL2_GPDI9"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI10 { address = 0xfffc150a; sn = "SIUL2_GPDI10"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI11 { address = 0xfffc150b; sn = "SIUL2_GPDI11"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI12 { address = 0xfffc150c; sn = "SIUL2_GPDI12"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI13 { address = 0xfffc150d; sn = "SIUL2_GPDI13"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI14 { address = 0xfffc150e; sn = "SIUL2_GPDI14"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI15 { address = 0xfffc150f; sn = "SIUL2_GPDI15"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI16 { address = 0xfffc1510; sn = "SIUL2_GPDI16"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI17 { address = 0xfffc1511; sn = "SIUL2_GPDI17"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI18 { address = 0xfffc1512; sn = "SIUL2_GPDI18"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI19 { address = 0xfffc1513; sn = "SIUL2_GPDI19"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI20 { address = 0xfffc1514; sn = "SIUL2_GPDI20"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI21 { address = 0xfffc1515; sn = "SIUL2_GPDI21"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI22 { address = 0xfffc1516; sn = "SIUL2_GPDI22"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI23 { address = 0xfffc1517; sn = "SIUL2_GPDI23"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI24 { address = 0xfffc1518; sn = "SIUL2_GPDI24"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI25 { address = 0xfffc1519; sn = "SIUL2_GPDI25"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI26 { address = 0xfffc151a; sn = "SIUL2_GPDI26"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI27 { address = 0xfffc151b; sn = "SIUL2_GPDI27"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI28 { address = 0xfffc151c; sn = "SIUL2_GPDI28"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI29 { address = 0xfffc151d; sn = "SIUL2_GPDI29"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI30 { address = 0xfffc151e; sn = "SIUL2_GPDI30"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI31 { address = 0xfffc151f; sn = "SIUL2_GPDI31"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI32 { address = 0xfffc1520; sn = "SIUL2_GPDI32"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI33 { address = 0xfffc1521; sn = "SIUL2_GPDI33"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI34 { address = 0xfffc1522; sn = "SIUL2_GPDI34"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI35 { address = 0xfffc1523; sn = "SIUL2_GPDI35"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI36 { address = 0xfffc1524; sn = "SIUL2_GPDI36"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI37 { address = 0xfffc1525; sn = "SIUL2_GPDI37"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI38 { address = 0xfffc1526; sn = "SIUL2_GPDI38"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI39 { address = 0xfffc1527; sn = "SIUL2_GPDI39"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI40 { address = 0xfffc1528; sn = "SIUL2_GPDI40"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI41 { address = 0xfffc1529; sn = "SIUL2_GPDI41"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI42 { address = 0xfffc152a; sn = "SIUL2_GPDI42"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI43 { address = 0xfffc152b; sn = "SIUL2_GPDI43"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI44 { address = 0xfffc152c; sn = "SIUL2_GPDI44"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI45 { address = 0xfffc152d; sn = "SIUL2_GPDI45"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI46 { address = 0xfffc152e; sn = "SIUL2_GPDI46"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI47 { address = 0xfffc152f; sn = "SIUL2_GPDI47"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI48 { address = 0xfffc1530; sn = "SIUL2_GPDI48"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI49 { address = 0xfffc1531; sn = "SIUL2_GPDI49"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI50 { address = 0xfffc1532; sn = "SIUL2_GPDI50"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI51 { address = 0xfffc1533; sn = "SIUL2_GPDI51"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI52 { address = 0xfffc1534; sn = "SIUL2_GPDI52"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI53 { address = 0xfffc1535; sn = "SIUL2_GPDI53"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI54 { address = 0xfffc1536; sn = "SIUL2_GPDI54"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI55 { address = 0xfffc1537; sn = "SIUL2_GPDI55"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI56 { address = 0xfffc1538; sn = "SIUL2_GPDI56"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI57 { address = 0xfffc1539; sn = "SIUL2_GPDI57"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI58 { address = 0xfffc153a; sn = "SIUL2_GPDI58"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI59 { address = 0xfffc153b; sn = "SIUL2_GPDI59"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI60 { address = 0xfffc153c; sn = "SIUL2_GPDI60"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI61 { address = 0xfffc153d; sn = "SIUL2_GPDI61"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI62 { address = 0xfffc153e; sn = "SIUL2_GPDI62"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI63 { address = 0xfffc153f; sn = "SIUL2_GPDI63"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI64 { address = 0xfffc1540; sn = "SIUL2_GPDI64"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI65 { address = 0xfffc1541; sn = "SIUL2_GPDI65"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI66 { address = 0xfffc1542; sn = "SIUL2_GPDI66"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI67 { address = 0xfffc1543; sn = "SIUL2_GPDI67"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI68 { address = 0xfffc1544; sn = "SIUL2_GPDI68"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI69 { address = 0xfffc1545; sn = "SIUL2_GPDI69"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI70 { address = 0xfffc1546; sn = "SIUL2_GPDI70"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI71 { address = 0xfffc1547; sn = "SIUL2_GPDI71"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI72 { address = 0xfffc1548; sn = "SIUL2_GPDI72"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI73 { address = 0xfffc1549; sn = "SIUL2_GPDI73"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI74 { address = 0xfffc154a; sn = "SIUL2_GPDI74"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI75 { address = 0xfffc154b; sn = "SIUL2_GPDI75"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI76 { address = 0xfffc154c; sn = "SIUL2_GPDI76"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI77 { address = 0xfffc154d; sn = "SIUL2_GPDI77"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI78 { address = 0xfffc154e; sn = "SIUL2_GPDI78"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI79 { address = 0xfffc154f; sn = "SIUL2_GPDI79"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI80 { address = 0xfffc1550; sn = "SIUL2_GPDI80"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI81 { address = 0xfffc1551; sn = "SIUL2_GPDI81"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI82 { address = 0xfffc1552; sn = "SIUL2_GPDI82"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI83 { address = 0xfffc1553; sn = "SIUL2_GPDI83"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI84 { address = 0xfffc1554; sn = "SIUL2_GPDI84"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI85 { address = 0xfffc1555; sn = "SIUL2_GPDI85"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI86 { address = 0xfffc1556; sn = "SIUL2_GPDI86"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI87 { address = 0xfffc1557; sn = "SIUL2_GPDI87"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI88 { address = 0xfffc1558; sn = "SIUL2_GPDI88"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI89 { address = 0xfffc1559; sn = "SIUL2_GPDI89"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI90 { address = 0xfffc155a; sn = "SIUL2_GPDI90"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI91 { address = 0xfffc155b; sn = "SIUL2_GPDI91"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI92 { address = 0xfffc155c; sn = "SIUL2_GPDI92"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI93 { address = 0xfffc155d; sn = "SIUL2_GPDI93"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI94 { address = 0xfffc155e; sn = "SIUL2_GPDI94"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI95 { address = 0xfffc155f; sn = "SIUL2_GPDI95"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI96 { address = 0xfffc1560; sn = "SIUL2_GPDI96"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI97 { address = 0xfffc1561; sn = "SIUL2_GPDI97"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI98 { address = 0xfffc1562; sn = "SIUL2_GPDI98"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI99 { address = 0xfffc1563; sn = "SIUL2_GPDI99"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI100 { address = 0xfffc1564; sn = "SIUL2_GPDI100"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI101 { address = 0xfffc1565; sn = "SIUL2_GPDI101"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI102 { address = 0xfffc1566; sn = "SIUL2_GPDI102"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI103 { address = 0xfffc1567; sn = "SIUL2_GPDI103"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI104 { address = 0xfffc1568; sn = "SIUL2_GPDI104"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI105 { address = 0xfffc1569; sn = "SIUL2_GPDI105"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI106 { address = 0xfffc156a; sn = "SIUL2_GPDI106"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI107 { address = 0xfffc156b; sn = "SIUL2_GPDI107"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI108 { address = 0xfffc156c; sn = "SIUL2_GPDI108"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI109 { address = 0xfffc156d; sn = "SIUL2_GPDI109"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI110 { address = 0xfffc156e; sn = "SIUL2_GPDI110"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI111 { address = 0xfffc156f; sn = "SIUL2_GPDI111"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI112 { address = 0xfffc1570; sn = "SIUL2_GPDI112"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI113 { address = 0xfffc1571; sn = "SIUL2_GPDI113"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI114 { address = 0xfffc1572; sn = "SIUL2_GPDI114"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI115 { address = 0xfffc1573; sn = "SIUL2_GPDI115"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI116 { address = 0xfffc1574; sn = "SIUL2_GPDI116"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI117 { address = 0xfffc1575; sn = "SIUL2_GPDI117"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI118 { address = 0xfffc1576; sn = "SIUL2_GPDI118"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI119 { address = 0xfffc1577; sn = "SIUL2_GPDI119"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI120 { address = 0xfffc1578; sn = "SIUL2_GPDI120"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI121 { address = 0xfffc1579; sn = "SIUL2_GPDI121"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI122 { address = 0xfffc157a; sn = "SIUL2_GPDI122"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI123 { address = 0xfffc157b; sn = "SIUL2_GPDI123"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI124 { address = 0xfffc157c; sn = "SIUL2_GPDI124"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI125 { address = 0xfffc157d; sn = "SIUL2_GPDI125"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI126 { address = 0xfffc157e; sn = "SIUL2_GPDI126"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI127 { address = 0xfffc157f; sn = "SIUL2_GPDI127"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI128 { address = 0xfffc1580; sn = "SIUL2_GPDI128"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI129 { address = 0xfffc1581; sn = "SIUL2_GPDI129"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI130 { address = 0xfffc1582; sn = "SIUL2_GPDI130"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI131 { address = 0xfffc1583; sn = "SIUL2_GPDI131"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI132 { address = 0xfffc1584; sn = "SIUL2_GPDI132"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI133 { address = 0xfffc1585; sn = "SIUL2_GPDI133"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI134 { address = 0xfffc1586; sn = "SIUL2_GPDI134"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI135 { address = 0xfffc1587; sn = "SIUL2_GPDI135"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI136 { address = 0xfffc1588; sn = "SIUL2_GPDI136"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI137 { address = 0xfffc1589; sn = "SIUL2_GPDI137"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI138 { address = 0xfffc158a; sn = "SIUL2_GPDI138"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI139 { address = 0xfffc158b; sn = "SIUL2_GPDI139"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI140 { address = 0xfffc158c; sn = "SIUL2_GPDI140"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI141 { address = 0xfffc158d; sn = "SIUL2_GPDI141"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI142 { address = 0xfffc158e; sn = "SIUL2_GPDI142"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI143 { address = 0xfffc158f; sn = "SIUL2_GPDI143"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI144 { address = 0xfffc1590; sn = "SIUL2_GPDI144"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI145 { address = 0xfffc1591; sn = "SIUL2_GPDI145"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI146 { address = 0xfffc1592; sn = "SIUL2_GPDI146"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI147 { address = 0xfffc1593; sn = "SIUL2_GPDI147"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI148 { address = 0xfffc1594; sn = "SIUL2_GPDI148"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI149 { address = 0xfffc1595; sn = "SIUL2_GPDI149"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI150 { address = 0xfffc1596; sn = "SIUL2_GPDI150"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI151 { address = 0xfffc1597; sn = "SIUL2_GPDI151"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI152 { address = 0xfffc1598; sn = "SIUL2_GPDI152"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI153 { address = 0xfffc1599; sn = "SIUL2_GPDI153"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI154 { address = 0xfffc159a; sn = "SIUL2_GPDI154"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI155 { address = 0xfffc159b; sn = "SIUL2_GPDI155"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI156 { address = 0xfffc159c; sn = "SIUL2_GPDI156"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI157 { address = 0xfffc159d; sn = "SIUL2_GPDI157"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI158 { address = 0xfffc159e; sn = "SIUL2_GPDI158"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI159 { address = 0xfffc159f; sn = "SIUL2_GPDI159"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI160 { address = 0xfffc15a0; sn = "SIUL2_GPDI160"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI161 { address = 0xfffc15a1; sn = "SIUL2_GPDI161"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI162 { address = 0xfffc15a2; sn = "SIUL2_GPDI162"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI163 { address = 0xfffc15a3; sn = "SIUL2_GPDI163"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI164 { address = 0xfffc15a4; sn = "SIUL2_GPDI164"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI165 { address = 0xfffc15a5; sn = "SIUL2_GPDI165"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI166 { address = 0xfffc15a6; sn = "SIUL2_GPDI166"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI167 { address = 0xfffc15a7; sn = "SIUL2_GPDI167"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI168 { address = 0xfffc15a8; sn = "SIUL2_GPDI168"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI169 { address = 0xfffc15a9; sn = "SIUL2_GPDI169"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI170 { address = 0xfffc15aa; sn = "SIUL2_GPDI170"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI171 { address = 0xfffc15ab; sn = "SIUL2_GPDI171"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI172 { address = 0xfffc15ac; sn = "SIUL2_GPDI172"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI173 { address = 0xfffc15ad; sn = "SIUL2_GPDI173"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI174 { address = 0xfffc15ae; sn = "SIUL2_GPDI174"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI175 { address = 0xfffc15af; sn = "SIUL2_GPDI175"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI176 { address = 0xfffc15b0; sn = "SIUL2_GPDI176"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI177 { address = 0xfffc15b1; sn = "SIUL2_GPDI177"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI178 { address = 0xfffc15b2; sn = "SIUL2_GPDI178"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI179 { address = 0xfffc15b3; sn = "SIUL2_GPDI179"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI180 { address = 0xfffc15b4; sn = "SIUL2_GPDI180"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI181 { address = 0xfffc15b5; sn = "SIUL2_GPDI181"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI182 { address = 0xfffc15b6; sn = "SIUL2_GPDI182"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI183 { address = 0xfffc15b7; sn = "SIUL2_GPDI183"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI184 { address = 0xfffc15b8; sn = "SIUL2_GPDI184"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI185 { address = 0xfffc15b9; sn = "SIUL2_GPDI185"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI186 { address = 0xfffc15ba; sn = "SIUL2_GPDI186"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI187 { address = 0xfffc15bb; sn = "SIUL2_GPDI187"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI188 { address = 0xfffc15bc; sn = "SIUL2_GPDI188"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI189 { address = 0xfffc15bd; sn = "SIUL2_GPDI189"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI190 { address = 0xfffc15be; sn = "SIUL2_GPDI190"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI191 { address = 0xfffc15bf; sn = "SIUL2_GPDI191"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI192 { address = 0xfffc15c0; sn = "SIUL2_GPDI192"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI193 { address = 0xfffc15c1; sn = "SIUL2_GPDI193"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI194 { address = 0xfffc15c2; sn = "SIUL2_GPDI194"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI195 { address = 0xfffc15c3; sn = "SIUL2_GPDI195"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI196 { address = 0xfffc15c4; sn = "SIUL2_GPDI196"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI197 { address = 0xfffc15c5; sn = "SIUL2_GPDI197"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI198 { address = 0xfffc15c6; sn = "SIUL2_GPDI198"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI199 { address = 0xfffc15c7; sn = "SIUL2_GPDI199"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI200 { address = 0xfffc15c8; sn = "SIUL2_GPDI200"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI201 { address = 0xfffc15c9; sn = "SIUL2_GPDI201"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI202 { address = 0xfffc15ca; sn = "SIUL2_GPDI202"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI203 { address = 0xfffc15cb; sn = "SIUL2_GPDI203"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI204 { address = 0xfffc15cc; sn = "SIUL2_GPDI204"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI205 { address = 0xfffc15cd; sn = "SIUL2_GPDI205"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI206 { address = 0xfffc15ce; sn = "SIUL2_GPDI206"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI207 { address = 0xfffc15cf; sn = "SIUL2_GPDI207"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI208 { address = 0xfffc15d0; sn = "SIUL2_GPDI208"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI209 { address = 0xfffc15d1; sn = "SIUL2_GPDI209"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI210 { address = 0xfffc15d2; sn = "SIUL2_GPDI210"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI211 { address = 0xfffc15d3; sn = "SIUL2_GPDI211"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI212 { address = 0xfffc15d4; sn = "SIUL2_GPDI212"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI213 { address = 0xfffc15d5; sn = "SIUL2_GPDI213"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI214 { address = 0xfffc15d6; sn = "SIUL2_GPDI214"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI215 { address = 0xfffc15d7; sn = "SIUL2_GPDI215"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI216 { address = 0xfffc15d8; sn = "SIUL2_GPDI216"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI217 { address = 0xfffc15d9; sn = "SIUL2_GPDI217"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI218 { address = 0xfffc15da; sn = "SIUL2_GPDI218"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI219 { address = 0xfffc15db; sn = "SIUL2_GPDI219"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI220 { address = 0xfffc15dc; sn = "SIUL2_GPDI220"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI221 { address = 0xfffc15dd; sn = "SIUL2_GPDI221"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI222 { address = 0xfffc15de; sn = "SIUL2_GPDI222"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI223 { address = 0xfffc15df; sn = "SIUL2_GPDI223"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI224 { address = 0xfffc15e0; sn = "SIUL2_GPDI224"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI225 { address = 0xfffc15e1; sn = "SIUL2_GPDI225"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI226 { address = 0xfffc15e2; sn = "SIUL2_GPDI226"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI227 { address = 0xfffc15e3; sn = "SIUL2_GPDI227"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI228 { address = 0xfffc15e4; sn = "SIUL2_GPDI228"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI229 { address = 0xfffc15e5; sn = "SIUL2_GPDI229"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI230 { address = 0xfffc15e6; sn = "SIUL2_GPDI230"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI231 { address = 0xfffc15e7; sn = "SIUL2_GPDI231"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI232 { address = 0xfffc15e8; sn = "SIUL2_GPDI232"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI233 { address = 0xfffc15e9; sn = "SIUL2_GPDI233"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI234 { address = 0xfffc15ea; sn = "SIUL2_GPDI234"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI235 { address = 0xfffc15eb; sn = "SIUL2_GPDI235"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI236 { address = 0xfffc15ec; sn = "SIUL2_GPDI236"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI237 { address = 0xfffc15ed; sn = "SIUL2_GPDI237"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI238 { address = 0xfffc15ee; sn = "SIUL2_GPDI238"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI239 { address = 0xfffc15ef; sn = "SIUL2_GPDI239"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI240 { address = 0xfffc15f0; sn = "SIUL2_GPDI240"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI241 { address = 0xfffc15f1; sn = "SIUL2_GPDI241"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI242 { address = 0xfffc15f2; sn = "SIUL2_GPDI242"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI243 { address = 0xfffc15f3; sn = "SIUL2_GPDI243"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI244 { address = 0xfffc15f4; sn = "SIUL2_GPDI244"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI245 { address = 0xfffc15f5; sn = "SIUL2_GPDI245"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI246 { address = 0xfffc15f6; sn = "SIUL2_GPDI246"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI247 { address = 0xfffc15f7; sn = "SIUL2_GPDI247"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI248 { address = 0xfffc15f8; sn = "SIUL2_GPDI248"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI249 { address = 0xfffc15f9; sn = "SIUL2_GPDI249"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI250 { address = 0xfffc15fa; sn = "SIUL2_GPDI250"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI251 { address = 0xfffc15fb; sn = "SIUL2_GPDI251"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI252 { address = 0xfffc15fc; sn = "SIUL2_GPDI252"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI253 { address = 0xfffc15fd; sn = "SIUL2_GPDI253"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI254 { address = 0xfffc15fe; sn = "SIUL2_GPDI254"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI255 { address = 0xfffc15ff; sn = "SIUL2_GPDI255"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI256 { address = 0xfffc1600; sn = "SIUL2_GPDI256"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI257 { address = 0xfffc1601; sn = "SIUL2_GPDI257"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI258 { address = 0xfffc1602; sn = "SIUL2_GPDI258"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI259 { address = 0xfffc1603; sn = "SIUL2_GPDI259"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI260 { address = 0xfffc1604; sn = "SIUL2_GPDI260"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI261 { address = 0xfffc1605; sn = "SIUL2_GPDI261"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI262 { address = 0xfffc1606; sn = "SIUL2_GPDI262"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI263 { address = 0xfffc1607; sn = "SIUL2_GPDI263"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI264 { address = 0xfffc1608; sn = "SIUL2_GPDI264"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI265 { address = 0xfffc1609; sn = "SIUL2_GPDI265"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI266 { address = 0xfffc160a; sn = "SIUL2_GPDI266"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI267 { address = 0xfffc160b; sn = "SIUL2_GPDI267"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI268 { address = 0xfffc160c; sn = "SIUL2_GPDI268"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI269 { address = 0xfffc160d; sn = "SIUL2_GPDI269"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI270 { address = 0xfffc160e; sn = "SIUL2_GPDI270"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI271 { address = 0xfffc160f; sn = "SIUL2_GPDI271"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI272 { address = 0xfffc1610; sn = "SIUL2_GPDI272"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI273 { address = 0xfffc1611; sn = "SIUL2_GPDI273"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI274 { address = 0xfffc1612; sn = "SIUL2_GPDI274"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI275 { address = 0xfffc1613; sn = "SIUL2_GPDI275"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI276 { address = 0xfffc1614; sn = "SIUL2_GPDI276"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI277 { address = 0xfffc1615; sn = "SIUL2_GPDI277"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI278 { address = 0xfffc1616; sn = "SIUL2_GPDI278"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI279 { address = 0xfffc1617; sn = "SIUL2_GPDI279"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI280 { address = 0xfffc1618; sn = "SIUL2_GPDI280"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI281 { address = 0xfffc1619; sn = "SIUL2_GPDI281"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI282 { address = 0xfffc161a; sn = "SIUL2_GPDI282"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI283 { address = 0xfffc161b; sn = "SIUL2_GPDI283"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI284 { address = 0xfffc161c; sn = "SIUL2_GPDI284"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI285 { address = 0xfffc161d; sn = "SIUL2_GPDI285"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI286 { address = 0xfffc161e; sn = "SIUL2_GPDI286"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI287 { address = 0xfffc161f; sn = "SIUL2_GPDI287"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI288 { address = 0xfffc1620; sn = "SIUL2_GPDI288"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI289 { address = 0xfffc1621; sn = "SIUL2_GPDI289"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI290 { address = 0xfffc1622; sn = "SIUL2_GPDI290"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI291 { address = 0xfffc1623; sn = "SIUL2_GPDI291"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI292 { address = 0xfffc1624; sn = "SIUL2_GPDI292"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI293 { address = 0xfffc1625; sn = "SIUL2_GPDI293"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI294 { address = 0xfffc1626; sn = "SIUL2_GPDI294"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI295 { address = 0xfffc1627; sn = "SIUL2_GPDI295"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI296 { address = 0xfffc1628; sn = "SIUL2_GPDI296"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI297 { address = 0xfffc1629; sn = "SIUL2_GPDI297"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI298 { address = 0xfffc162a; sn = "SIUL2_GPDI298"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI299 { address = 0xfffc162b; sn = "SIUL2_GPDI299"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI300 { address = 0xfffc162c; sn = "SIUL2_GPDI300"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI301 { address = 0xfffc162d; sn = "SIUL2_GPDI301"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI302 { address = 0xfffc162e; sn = "SIUL2_GPDI302"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI303 { address = 0xfffc162f; sn = "SIUL2_GPDI303"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI304 { address = 0xfffc1630; sn = "SIUL2_GPDI304"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI305 { address = 0xfffc1631; sn = "SIUL2_GPDI305"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI306 { address = 0xfffc1632; sn = "SIUL2_GPDI306"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI307 { address = 0xfffc1633; sn = "SIUL2_GPDI307"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI308 { address = 0xfffc1634; sn = "SIUL2_GPDI308"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI309 { address = 0xfffc1635; sn = "SIUL2_GPDI309"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI310 { address = 0xfffc1636; sn = "SIUL2_GPDI310"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI311 { address = 0xfffc1637; sn = "SIUL2_GPDI311"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI312 { address = 0xfffc1638; sn = "SIUL2_GPDI312"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI313 { address = 0xfffc1639; sn = "SIUL2_GPDI313"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI314 { address = 0xfffc163a; sn = "SIUL2_GPDI314"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI315 { address = 0xfffc163b; sn = "SIUL2_GPDI315"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI316 { address = 0xfffc163c; sn = "SIUL2_GPDI316"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI317 { address = 0xfffc163d; sn = "SIUL2_GPDI317"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI318 { address = 0xfffc163e; sn = "SIUL2_GPDI318"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI319 { address = 0xfffc163f; sn = "SIUL2_GPDI319"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI320 { address = 0xfffc1640; sn = "SIUL2_GPDI320"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI321 { address = 0xfffc1641; sn = "SIUL2_GPDI321"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI322 { address = 0xfffc1642; sn = "SIUL2_GPDI322"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI323 { address = 0xfffc1643; sn = "SIUL2_GPDI323"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI324 { address = 0xfffc1644; sn = "SIUL2_GPDI324"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI325 { address = 0xfffc1645; sn = "SIUL2_GPDI325"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI326 { address = 0xfffc1646; sn = "SIUL2_GPDI326"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI327 { address = 0xfffc1647; sn = "SIUL2_GPDI327"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI328 { address = 0xfffc1648; sn = "SIUL2_GPDI328"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI329 { address = 0xfffc1649; sn = "SIUL2_GPDI329"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI330 { address = 0xfffc164a; sn = "SIUL2_GPDI330"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI331 { address = 0xfffc164b; sn = "SIUL2_GPDI331"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI332 { address = 0xfffc164c; sn = "SIUL2_GPDI332"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI333 { address = 0xfffc164d; sn = "SIUL2_GPDI333"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI334 { address = 0xfffc164e; sn = "SIUL2_GPDI334"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI335 { address = 0xfffc164f; sn = "SIUL2_GPDI335"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI336 { address = 0xfffc1650; sn = "SIUL2_GPDI336"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI337 { address = 0xfffc1651; sn = "SIUL2_GPDI337"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI338 { address = 0xfffc1652; sn = "SIUL2_GPDI338"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI339 { address = 0xfffc1653; sn = "SIUL2_GPDI339"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI340 { address = 0xfffc1654; sn = "SIUL2_GPDI340"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI341 { address = 0xfffc1655; sn = "SIUL2_GPDI341"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI342 { address = 0xfffc1656; sn = "SIUL2_GPDI342"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI343 { address = 0xfffc1657; sn = "SIUL2_GPDI343"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI344 { address = 0xfffc1658; sn = "SIUL2_GPDI344"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI345 { address = 0xfffc1659; sn = "SIUL2_GPDI345"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI346 { address = 0xfffc165a; sn = "SIUL2_GPDI346"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI347 { address = 0xfffc165b; sn = "SIUL2_GPDI347"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI348 { address = 0xfffc165c; sn = "SIUL2_GPDI348"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI349 { address = 0xfffc165d; sn = "SIUL2_GPDI349"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI350 { address = 0xfffc165e; sn = "SIUL2_GPDI350"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI351 { address = 0xfffc165f; sn = "SIUL2_GPDI351"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI352 { address = 0xfffc1660; sn = "SIUL2_GPDI352"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI353 { address = 0xfffc1661; sn = "SIUL2_GPDI353"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI354 { address = 0xfffc1662; sn = "SIUL2_GPDI354"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI355 { address = 0xfffc1663; sn = "SIUL2_GPDI355"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI356 { address = 0xfffc1664; sn = "SIUL2_GPDI356"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI357 { address = 0xfffc1665; sn = "SIUL2_GPDI357"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI358 { address = 0xfffc1666; sn = "SIUL2_GPDI358"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI359 { address = 0xfffc1667; sn = "SIUL2_GPDI359"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI360 { address = 0xfffc1668; sn = "SIUL2_GPDI360"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI361 { address = 0xfffc1669; sn = "SIUL2_GPDI361"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI362 { address = 0xfffc166a; sn = "SIUL2_GPDI362"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI363 { address = 0xfffc166b; sn = "SIUL2_GPDI363"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI364 { address = 0xfffc166c; sn = "SIUL2_GPDI364"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI365 { address = 0xfffc166d; sn = "SIUL2_GPDI365"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI366 { address = 0xfffc166e; sn = "SIUL2_GPDI366"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI367 { address = 0xfffc166f; sn = "SIUL2_GPDI367"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI368 { address = 0xfffc1670; sn = "SIUL2_GPDI368"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI369 { address = 0xfffc1671; sn = "SIUL2_GPDI369"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI370 { address = 0xfffc1672; sn = "SIUL2_GPDI370"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI371 { address = 0xfffc1673; sn = "SIUL2_GPDI371"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI372 { address = 0xfffc1674; sn = "SIUL2_GPDI372"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI373 { address = 0xfffc1675; sn = "SIUL2_GPDI373"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI374 { address = 0xfffc1676; sn = "SIUL2_GPDI374"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI375 { address = 0xfffc1677; sn = "SIUL2_GPDI375"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI376 { address = 0xfffc1678; sn = "SIUL2_GPDI376"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI377 { address = 0xfffc1679; sn = "SIUL2_GPDI377"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI378 { address = 0xfffc167a; sn = "SIUL2_GPDI378"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI379 { address = 0xfffc167b; sn = "SIUL2_GPDI379"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI380 { address = 0xfffc167c; sn = "SIUL2_GPDI380"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI381 { address = 0xfffc167d; sn = "SIUL2_GPDI381"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI382 { address = 0xfffc167e; sn = "SIUL2_GPDI382"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI383 { address = 0xfffc167f; sn = "SIUL2_GPDI383"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI384 { address = 0xfffc1680; sn = "SIUL2_GPDI384"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI385 { address = 0xfffc1681; sn = "SIUL2_GPDI385"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI386 { address = 0xfffc1682; sn = "SIUL2_GPDI386"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI387 { address = 0xfffc1683; sn = "SIUL2_GPDI387"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI388 { address = 0xfffc1684; sn = "SIUL2_GPDI388"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI389 { address = 0xfffc1685; sn = "SIUL2_GPDI389"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI390 { address = 0xfffc1686; sn = "SIUL2_GPDI390"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI391 { address = 0xfffc1687; sn = "SIUL2_GPDI391"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI392 { address = 0xfffc1688; sn = "SIUL2_GPDI392"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI393 { address = 0xfffc1689; sn = "SIUL2_GPDI393"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI394 { address = 0xfffc168a; sn = "SIUL2_GPDI394"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI395 { address = 0xfffc168b; sn = "SIUL2_GPDI395"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI396 { address = 0xfffc168c; sn = "SIUL2_GPDI396"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI397 { address = 0xfffc168d; sn = "SIUL2_GPDI397"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI398 { address = 0xfffc168e; sn = "SIUL2_GPDI398"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI399 { address = 0xfffc168f; sn = "SIUL2_GPDI399"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI400 { address = 0xfffc1690; sn = "SIUL2_GPDI400"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI401 { address = 0xfffc1691; sn = "SIUL2_GPDI401"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI402 { address = 0xfffc1692; sn = "SIUL2_GPDI402"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI403 { address = 0xfffc1693; sn = "SIUL2_GPDI403"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI404 { address = 0xfffc1694; sn = "SIUL2_GPDI404"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI405 { address = 0xfffc1695; sn = "SIUL2_GPDI405"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI406 { address = 0xfffc1696; sn = "SIUL2_GPDI406"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI407 { address = 0xfffc1697; sn = "SIUL2_GPDI407"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI408 { address = 0xfffc1698; sn = "SIUL2_GPDI408"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI409 { address = 0xfffc1699; sn = "SIUL2_GPDI409"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI410 { address = 0xfffc169a; sn = "SIUL2_GPDI410"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI411 { address = 0xfffc169b; sn = "SIUL2_GPDI411"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI412 { address = 0xfffc169c; sn = "SIUL2_GPDI412"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI413 { address = 0xfffc169d; sn = "SIUL2_GPDI413"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI414 { address = 0xfffc169e; sn = "SIUL2_GPDI414"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI415 { address = 0xfffc169f; sn = "SIUL2_GPDI415"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI416 { address = 0xfffc16a0; sn = "SIUL2_GPDI416"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI417 { address = 0xfffc16a1; sn = "SIUL2_GPDI417"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI418 { address = 0xfffc16a2; sn = "SIUL2_GPDI418"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI419 { address = 0xfffc16a3; sn = "SIUL2_GPDI419"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI420 { address = 0xfffc16a4; sn = "SIUL2_GPDI420"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI421 { address = 0xfffc16a5; sn = "SIUL2_GPDI421"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI422 { address = 0xfffc16a6; sn = "SIUL2_GPDI422"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI423 { address = 0xfffc16a7; sn = "SIUL2_GPDI423"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI424 { address = 0xfffc16a8; sn = "SIUL2_GPDI424"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI425 { address = 0xfffc16a9; sn = "SIUL2_GPDI425"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI426 { address = 0xfffc16aa; sn = "SIUL2_GPDI426"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI427 { address = 0xfffc16ab; sn = "SIUL2_GPDI427"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI428 { address = 0xfffc16ac; sn = "SIUL2_GPDI428"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI429 { address = 0xfffc16ad; sn = "SIUL2_GPDI429"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI430 { address = 0xfffc16ae; sn = "SIUL2_GPDI430"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI431 { address = 0xfffc16af; sn = "SIUL2_GPDI431"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI432 { address = 0xfffc16b0; sn = "SIUL2_GPDI432"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI433 { address = 0xfffc16b1; sn = "SIUL2_GPDI433"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI434 { address = 0xfffc16b2; sn = "SIUL2_GPDI434"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI435 { address = 0xfffc16b3; sn = "SIUL2_GPDI435"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI436 { address = 0xfffc16b4; sn = "SIUL2_GPDI436"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI437 { address = 0xfffc16b5; sn = "SIUL2_GPDI437"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI438 { address = 0xfffc16b6; sn = "SIUL2_GPDI438"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI439 { address = 0xfffc16b7; sn = "SIUL2_GPDI439"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI440 { address = 0xfffc16b8; sn = "SIUL2_GPDI440"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI441 { address = 0xfffc16b9; sn = "SIUL2_GPDI441"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI442 { address = 0xfffc16ba; sn = "SIUL2_GPDI442"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI443 { address = 0xfffc16bb; sn = "SIUL2_GPDI443"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI444 { address = 0xfffc16bc; sn = "SIUL2_GPDI444"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI445 { address = 0xfffc16bd; sn = "SIUL2_GPDI445"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI446 { address = 0xfffc16be; sn = "SIUL2_GPDI446"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI447 { address = 0xfffc16bf; sn = "SIUL2_GPDI447"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI448 { address = 0xfffc16c0; sn = "SIUL2_GPDI448"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI449 { address = 0xfffc16c1; sn = "SIUL2_GPDI449"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI450 { address = 0xfffc16c2; sn = "SIUL2_GPDI450"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI451 { address = 0xfffc16c3; sn = "SIUL2_GPDI451"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI452 { address = 0xfffc16c4; sn = "SIUL2_GPDI452"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI453 { address = 0xfffc16c5; sn = "SIUL2_GPDI453"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI454 { address = 0xfffc16c6; sn = "SIUL2_GPDI454"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI455 { address = 0xfffc16c7; sn = "SIUL2_GPDI455"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI456 { address = 0xfffc16c8; sn = "SIUL2_GPDI456"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI457 { address = 0xfffc16c9; sn = "SIUL2_GPDI457"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI458 { address = 0xfffc16ca; sn = "SIUL2_GPDI458"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI459 { address = 0xfffc16cb; sn = "SIUL2_GPDI459"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI460 { address = 0xfffc16cc; sn = "SIUL2_GPDI460"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI461 { address = 0xfffc16cd; sn = "SIUL2_GPDI461"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI462 { address = 0xfffc16ce; sn = "SIUL2_GPDI462"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI463 { address = 0xfffc16cf; sn = "SIUL2_GPDI463"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI464 { address = 0xfffc16d0; sn = "SIUL2_GPDI464"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI465 { address = 0xfffc16d1; sn = "SIUL2_GPDI465"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI466 { address = 0xfffc16d2; sn = "SIUL2_GPDI466"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI467 { address = 0xfffc16d3; sn = "SIUL2_GPDI467"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI468 { address = 0xfffc16d4; sn = "SIUL2_GPDI468"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI469 { address = 0xfffc16d5; sn = "SIUL2_GPDI469"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI470 { address = 0xfffc16d6; sn = "SIUL2_GPDI470"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI471 { address = 0xfffc16d7; sn = "SIUL2_GPDI471"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI472 { address = 0xfffc16d8; sn = "SIUL2_GPDI472"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI473 { address = 0xfffc16d9; sn = "SIUL2_GPDI473"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI474 { address = 0xfffc16da; sn = "SIUL2_GPDI474"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI475 { address = 0xfffc16db; sn = "SIUL2_GPDI475"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI476 { address = 0xfffc16dc; sn = "SIUL2_GPDI476"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI477 { address = 0xfffc16dd; sn = "SIUL2_GPDI477"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI478 { address = 0xfffc16de; sn = "SIUL2_GPDI478"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI479 { address = 0xfffc16df; sn = "SIUL2_GPDI479"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI480 { address = 0xfffc16e0; sn = "SIUL2_GPDI480"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI481 { address = 0xfffc16e1; sn = "SIUL2_GPDI481"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI482 { address = 0xfffc16e2; sn = "SIUL2_GPDI482"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI483 { address = 0xfffc16e3; sn = "SIUL2_GPDI483"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI484 { address = 0xfffc16e4; sn = "SIUL2_GPDI484"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI485 { address = 0xfffc16e5; sn = "SIUL2_GPDI485"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI486 { address = 0xfffc16e6; sn = "SIUL2_GPDI486"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI487 { address = 0xfffc16e7; sn = "SIUL2_GPDI487"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI488 { address = 0xfffc16e8; sn = "SIUL2_GPDI488"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI489 { address = 0xfffc16e9; sn = "SIUL2_GPDI489"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI490 { address = 0xfffc16ea; sn = "SIUL2_GPDI490"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI491 { address = 0xfffc16eb; sn = "SIUL2_GPDI491"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI492 { address = 0xfffc16ec; sn = "SIUL2_GPDI492"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI493 { address = 0xfffc16ed; sn = "SIUL2_GPDI493"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI494 { address = 0xfffc16ee; sn = "SIUL2_GPDI494"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI495 { address = 0xfffc16ef; sn = "SIUL2_GPDI495"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI496 { address = 0xfffc16f0; sn = "SIUL2_GPDI496"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI497 { address = 0xfffc16f1; sn = "SIUL2_GPDI497"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI498 { address = 0xfffc16f2; sn = "SIUL2_GPDI498"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI499 { address = 0xfffc16f3; sn = "SIUL2_GPDI499"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI500 { address = 0xfffc16f4; sn = "SIUL2_GPDI500"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI501 { address = 0xfffc16f5; sn = "SIUL2_GPDI501"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI502 { address = 0xfffc16f6; sn = "SIUL2_GPDI502"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI503 { address = 0xfffc16f7; sn = "SIUL2_GPDI503"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI504 { address = 0xfffc16f8; sn = "SIUL2_GPDI504"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI505 { address = 0xfffc16f9; sn = "SIUL2_GPDI505"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI506 { address = 0xfffc16fa; sn = "SIUL2_GPDI506"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI507 { address = 0xfffc16fb; sn = "SIUL2_GPDI507"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI508 { address = 0xfffc16fc; sn = "SIUL2_GPDI508"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI509 { address = 0xfffc16fd; sn = "SIUL2_GPDI509"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI510 { address = 0xfffc16fe; sn = "SIUL2_GPDI510"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_GPDI511 { address = 0xfffc16ff; sn = "SIUL2_GPDI511"; access = "memorymapped"; width = 8; ${_DESC2163_}; type = "bitfield_SIUL2_GPDI0" permission = "write/none" } SIUL2_PGPDO0_1 { address = 0xfffc1700; sn = "SIUL2_PGPDO0_1"; access = "memorymapped"; width = 32; ${_DESC2165_}; type = "bitfield_SIUL2_PGPDO0_1" } SIUL2_PGPDO2_3 { address = 0xfffc1704; sn = "SIUL2_PGPDO2_3"; access = "memorymapped"; width = 32; ${_DESC2165_}; type = "bitfield_SIUL2_PGPDO0_1" } SIUL2_PGPDO4_5 { address = 0xfffc1708; sn = "SIUL2_PGPDO4_5"; access = "memorymapped"; width = 32; ${_DESC2165_}; type = "bitfield_SIUL2_PGPDO0_1" } SIUL2_PGPDO6_7 { address = 0xfffc170c; sn = "SIUL2_PGPDO6_7"; access = "memorymapped"; width = 32; ${_DESC2165_}; type = "bitfield_SIUL2_PGPDO0_1" } SIUL2_PGPDO8_9 { address = 0xfffc1710; sn = "SIUL2_PGPDO8_9"; access = "memorymapped"; width = 32; ${_DESC2165_}; type = "bitfield_SIUL2_PGPDO0_1" } SIUL2_PGPDO10_11 { address = 0xfffc1714; sn = "SIUL2_PGPDO10_11"; access = "memorymapped"; width = 32; ${_DESC2165_}; type = "bitfield_SIUL2_PGPDO0_1" } SIUL2_PGPDO12_13 { address = 0xfffc1718; sn = "SIUL2_PGPDO12_13"; access = "memorymapped"; width = 32; ${_DESC2165_}; type = "bitfield_SIUL2_PGPDO0_1" } SIUL2_PGPDO14_15 { address = 0xfffc171c; sn = "SIUL2_PGPDO14_15"; access = "memorymapped"; width = 32; ${_DESC2165_}; type = "bitfield_SIUL2_PGPDO0_1" } SIUL2_PGPDO16_17 { address = 0xfffc1720; sn = "SIUL2_PGPDO16_17"; access = "memorymapped"; width = 32; ${_DESC2165_}; type = "bitfield_SIUL2_PGPDO0_1" } SIUL2_PGPDO18_19 { address = 0xfffc1724; sn = "SIUL2_PGPDO18_19"; access = "memorymapped"; width = 32; ${_DESC2165_}; type = "bitfield_SIUL2_PGPDO0_1" } SIUL2_PGPDO20_21 { address = 0xfffc1728; sn = "SIUL2_PGPDO20_21"; access = "memorymapped"; width = 32; ${_DESC2165_}; type = "bitfield_SIUL2_PGPDO0_1" } SIUL2_PGPDO22_23 { address = 0xfffc172c; sn = "SIUL2_PGPDO22_23"; access = "memorymapped"; width = 32; ${_DESC2165_}; type = "bitfield_SIUL2_PGPDO0_1" } SIUL2_PGPDO24_25 { address = 0xfffc1730; sn = "SIUL2_PGPDO24_25"; access = "memorymapped"; width = 32; ${_DESC2165_}; type = "bitfield_SIUL2_PGPDO0_1" } SIUL2_PGPDO26_27 { address = 0xfffc1734; sn = "SIUL2_PGPDO26_27"; access = "memorymapped"; width = 32; ${_DESC2165_}; type = "bitfield_SIUL2_PGPDO0_1" } SIUL2_PGPDO28_29 { address = 0xfffc1738; sn = "SIUL2_PGPDO28_29"; access = "memorymapped"; width = 32; ${_DESC2165_}; type = "bitfield_SIUL2_PGPDO0_1" } SIUL2_PGPDO30_31 { address = 0xfffc173c; sn = "SIUL2_PGPDO30_31"; access = "memorymapped"; width = 32; ${_DESC2165_}; type = "bitfield_SIUL2_PGPDO0_1" } SIUL2_PGPDI0_1 { address = 0xfffc1740; sn = "SIUL2_PGPDI0_1"; access = "memorymapped"; width = 32; ${_DESC2167_}; type = "bitfield_SIUL2_PGPDI0_1" permission = "write/none" } SIUL2_PGPDI2_3 { address = 0xfffc1744; sn = "SIUL2_PGPDI2_3"; access = "memorymapped"; width = 32; ${_DESC2167_}; type = "bitfield_SIUL2_PGPDI0_1" permission = "write/none" } SIUL2_PGPDI4_5 { address = 0xfffc1748; sn = "SIUL2_PGPDI4_5"; access = "memorymapped"; width = 32; ${_DESC2167_}; type = "bitfield_SIUL2_PGPDI0_1" permission = "write/none" } SIUL2_PGPDI6_7 { address = 0xfffc174c; sn = "SIUL2_PGPDI6_7"; access = "memorymapped"; width = 32; ${_DESC2167_}; type = "bitfield_SIUL2_PGPDI0_1" permission = "write/none" } SIUL2_PGPDI8_9 { address = 0xfffc1750; sn = "SIUL2_PGPDI8_9"; access = "memorymapped"; width = 32; ${_DESC2167_}; type = "bitfield_SIUL2_PGPDI0_1" permission = "write/none" } SIUL2_PGPDI10_11 { address = 0xfffc1754; sn = "SIUL2_PGPDI10_11"; access = "memorymapped"; width = 32; ${_DESC2167_}; type = "bitfield_SIUL2_PGPDI0_1" permission = "write/none" } SIUL2_PGPDI12_13 { address = 0xfffc1758; sn = "SIUL2_PGPDI12_13"; access = "memorymapped"; width = 32; ${_DESC2167_}; type = "bitfield_SIUL2_PGPDI0_1" permission = "write/none" } SIUL2_PGPDI14_15 { address = 0xfffc175c; sn = "SIUL2_PGPDI14_15"; access = "memorymapped"; width = 32; ${_DESC2167_}; type = "bitfield_SIUL2_PGPDI0_1" permission = "write/none" } SIUL2_PGPDI16_17 { address = 0xfffc1760; sn = "SIUL2_PGPDI16_17"; access = "memorymapped"; width = 32; ${_DESC2167_}; type = "bitfield_SIUL2_PGPDI0_1" permission = "write/none" } SIUL2_PGPDI18_19 { address = 0xfffc1764; sn = "SIUL2_PGPDI18_19"; access = "memorymapped"; width = 32; ${_DESC2167_}; type = "bitfield_SIUL2_PGPDI0_1" permission = "write/none" } SIUL2_PGPDI20_21 { address = 0xfffc1768; sn = "SIUL2_PGPDI20_21"; access = "memorymapped"; width = 32; ${_DESC2167_}; type = "bitfield_SIUL2_PGPDI0_1" permission = "write/none" } SIUL2_PGPDI22_23 { address = 0xfffc176c; sn = "SIUL2_PGPDI22_23"; access = "memorymapped"; width = 32; ${_DESC2167_}; type = "bitfield_SIUL2_PGPDI0_1" permission = "write/none" } SIUL2_PGPDI24_25 { address = 0xfffc1770; sn = "SIUL2_PGPDI24_25"; access = "memorymapped"; width = 32; ${_DESC2167_}; type = "bitfield_SIUL2_PGPDI0_1" permission = "write/none" } SIUL2_PGPDI26_27 { address = 0xfffc1774; sn = "SIUL2_PGPDI26_27"; access = "memorymapped"; width = 32; ${_DESC2167_}; type = "bitfield_SIUL2_PGPDI0_1" permission = "write/none" } SIUL2_PGPDI28_29 { address = 0xfffc1778; sn = "SIUL2_PGPDI28_29"; access = "memorymapped"; width = 32; ${_DESC2167_}; type = "bitfield_SIUL2_PGPDI0_1" permission = "write/none" } SIUL2_PGPDI30_31 { address = 0xfffc177c; sn = "SIUL2_PGPDI30_31"; access = "memorymapped"; width = 32; ${_DESC2167_}; type = "bitfield_SIUL2_PGPDI0_1" permission = "write/none" } SIUL2_MPGPDO0 { address = 0xfffc1780; sn = "SIUL2_MPGPDO0"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO1 { address = 0xfffc1784; sn = "SIUL2_MPGPDO1"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO2 { address = 0xfffc1788; sn = "SIUL2_MPGPDO2"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO3 { address = 0xfffc178c; sn = "SIUL2_MPGPDO3"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO4 { address = 0xfffc1790; sn = "SIUL2_MPGPDO4"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO5 { address = 0xfffc1794; sn = "SIUL2_MPGPDO5"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO6 { address = 0xfffc1798; sn = "SIUL2_MPGPDO6"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO7 { address = 0xfffc179c; sn = "SIUL2_MPGPDO7"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO8 { address = 0xfffc17a0; sn = "SIUL2_MPGPDO8"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO9 { address = 0xfffc17a4; sn = "SIUL2_MPGPDO9"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO10 { address = 0xfffc17a8; sn = "SIUL2_MPGPDO10"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO11 { address = 0xfffc17ac; sn = "SIUL2_MPGPDO11"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO12 { address = 0xfffc17b0; sn = "SIUL2_MPGPDO12"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO13 { address = 0xfffc17b4; sn = "SIUL2_MPGPDO13"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO14 { address = 0xfffc17b8; sn = "SIUL2_MPGPDO14"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO15 { address = 0xfffc17bc; sn = "SIUL2_MPGPDO15"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO16 { address = 0xfffc17c0; sn = "SIUL2_MPGPDO16"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO17 { address = 0xfffc17c4; sn = "SIUL2_MPGPDO17"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO18 { address = 0xfffc17c8; sn = "SIUL2_MPGPDO18"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO19 { address = 0xfffc17cc; sn = "SIUL2_MPGPDO19"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO20 { address = 0xfffc17d0; sn = "SIUL2_MPGPDO20"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO21 { address = 0xfffc17d4; sn = "SIUL2_MPGPDO21"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO22 { address = 0xfffc17d8; sn = "SIUL2_MPGPDO22"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO23 { address = 0xfffc17dc; sn = "SIUL2_MPGPDO23"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO24 { address = 0xfffc17e0; sn = "SIUL2_MPGPDO24"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO25 { address = 0xfffc17e4; sn = "SIUL2_MPGPDO25"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO26 { address = 0xfffc17e8; sn = "SIUL2_MPGPDO26"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO27 { address = 0xfffc17ec; sn = "SIUL2_MPGPDO27"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO28 { address = 0xfffc17f0; sn = "SIUL2_MPGPDO28"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO29 { address = 0xfffc17f4; sn = "SIUL2_MPGPDO29"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO30 { address = 0xfffc17f8; sn = "SIUL2_MPGPDO30"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SIUL2_MPGPDO31 { address = 0xfffc17fc; sn = "SIUL2_MPGPDO31"; access = "memorymapped"; width = 32; ${_DESC2169_}; type = "bitfield_SIUL2_MPGPDO0" permission = "read/none" } SMPU_0_CESR0 { address = 0xfc010000; sn = "SMPU_0_CESR0"; access = "memorymapped"; width = 32; ${_DESC2172_}; type = "bitfield_SMPU_0_CESR0" } SMPU_0_CESR1 { address = 0xfc010004; sn = "SMPU_0_CESR1"; access = "memorymapped"; width = 32; ${_DESC2176_}; type = "bitfield_SMPU_0_CESR1" permission = "write/none" } SMPU_0_EAR0 { address = 0xfc010100; sn = "SMPU_0_EAR0"; access = "memorymapped"; width = 32; ${_DESC2179_}; type = "bitfield_SMPU_0_EAR0" permission = "write/none" } SMPU_0_EDR0 { address = 0xfc010104; sn = "SMPU_0_EDR0"; access = "memorymapped"; width = 32; ${_DESC2181_}; type = "bitfield_SMPU_0_EDR0" permission = "write/none" } SMPU_0_EAR1 { address = 0xfc010108; sn = "SMPU_0_EAR1"; access = "memorymapped"; width = 32; ${_DESC2179_}; type = "bitfield_SMPU_0_EAR0" permission = "write/none" } SMPU_0_EDR1 { address = 0xfc01010c; sn = "SMPU_0_EDR1"; access = "memorymapped"; width = 32; ${_DESC2181_}; type = "bitfield_SMPU_0_EDR0" permission = "write/none" } SMPU_0_EAR2 { address = 0xfc010110; sn = "SMPU_0_EAR2"; access = "memorymapped"; width = 32; ${_DESC2179_}; type = "bitfield_SMPU_0_EAR0" permission = "write/none" } SMPU_0_EDR2 { address = 0xfc010114; sn = "SMPU_0_EDR2"; access = "memorymapped"; width = 32; ${_DESC2181_}; type = "bitfield_SMPU_0_EDR0" permission = "write/none" } SMPU_0_EAR3 { address = 0xfc010118; sn = "SMPU_0_EAR3"; access = "memorymapped"; width = 32; ${_DESC2179_}; type = "bitfield_SMPU_0_EAR0" permission = "write/none" } SMPU_0_EDR3 { address = 0xfc01011c; sn = "SMPU_0_EDR3"; access = "memorymapped"; width = 32; ${_DESC2181_}; type = "bitfield_SMPU_0_EDR0" permission = "write/none" } SMPU_0_EAR4 { address = 0xfc010120; sn = "SMPU_0_EAR4"; access = "memorymapped"; width = 32; ${_DESC2179_}; type = "bitfield_SMPU_0_EAR0" permission = "write/none" } SMPU_0_EDR4 { address = 0xfc010124; sn = "SMPU_0_EDR4"; access = "memorymapped"; width = 32; ${_DESC2181_}; type = "bitfield_SMPU_0_EDR0" permission = "write/none" } SMPU_0_EAR5 { address = 0xfc010128; sn = "SMPU_0_EAR5"; access = "memorymapped"; width = 32; ${_DESC2179_}; type = "bitfield_SMPU_0_EAR0" permission = "write/none" } SMPU_0_EDR5 { address = 0xfc01012c; sn = "SMPU_0_EDR5"; access = "memorymapped"; width = 32; ${_DESC2181_}; type = "bitfield_SMPU_0_EDR0" permission = "write/none" } SMPU_0_EAR6 { address = 0xfc010130; sn = "SMPU_0_EAR6"; access = "memorymapped"; width = 32; ${_DESC2179_}; type = "bitfield_SMPU_0_EAR0" permission = "write/none" } SMPU_0_EDR6 { address = 0xfc010134; sn = "SMPU_0_EDR6"; access = "memorymapped"; width = 32; ${_DESC2181_}; type = "bitfield_SMPU_0_EDR0" permission = "write/none" } SMPU_0_EAR7 { address = 0xfc010138; sn = "SMPU_0_EAR7"; access = "memorymapped"; width = 32; ${_DESC2179_}; type = "bitfield_SMPU_0_EAR0" permission = "write/none" } SMPU_0_EDR7 { address = 0xfc01013c; sn = "SMPU_0_EDR7"; access = "memorymapped"; width = 32; ${_DESC2181_}; type = "bitfield_SMPU_0_EDR0" permission = "write/none" } SMPU_0_EAR8 { address = 0xfc010140; sn = "SMPU_0_EAR8"; access = "memorymapped"; width = 32; ${_DESC2179_}; type = "bitfield_SMPU_0_EAR0" permission = "write/none" } SMPU_0_EDR8 { address = 0xfc010144; sn = "SMPU_0_EDR8"; access = "memorymapped"; width = 32; ${_DESC2181_}; type = "bitfield_SMPU_0_EDR0" permission = "write/none" } SMPU_0_EAR9 { address = 0xfc010148; sn = "SMPU_0_EAR9"; access = "memorymapped"; width = 32; ${_DESC2179_}; type = "bitfield_SMPU_0_EAR0" permission = "write/none" } SMPU_0_EDR9 { address = 0xfc01014c; sn = "SMPU_0_EDR9"; access = "memorymapped"; width = 32; ${_DESC2181_}; type = "bitfield_SMPU_0_EDR0" permission = "write/none" } SMPU_0_EAR10 { address = 0xfc010150; sn = "SMPU_0_EAR10"; access = "memorymapped"; width = 32; ${_DESC2179_}; type = "bitfield_SMPU_0_EAR0" permission = "write/none" } SMPU_0_EDR10 { address = 0xfc010154; sn = "SMPU_0_EDR10"; access = "memorymapped"; width = 32; ${_DESC2181_}; type = "bitfield_SMPU_0_EDR0" permission = "write/none" } SMPU_0_EAR11 { address = 0xfc010158; sn = "SMPU_0_EAR11"; access = "memorymapped"; width = 32; ${_DESC2179_}; type = "bitfield_SMPU_0_EAR0" permission = "write/none" } SMPU_0_EDR11 { address = 0xfc01015c; sn = "SMPU_0_EDR11"; access = "memorymapped"; width = 32; ${_DESC2181_}; type = "bitfield_SMPU_0_EDR0" permission = "write/none" } SMPU_0_EAR12 { address = 0xfc010160; sn = "SMPU_0_EAR12"; access = "memorymapped"; width = 32; ${_DESC2179_}; type = "bitfield_SMPU_0_EAR0" permission = "write/none" } SMPU_0_EDR12 { address = 0xfc010164; sn = "SMPU_0_EDR12"; access = "memorymapped"; width = 32; ${_DESC2181_}; type = "bitfield_SMPU_0_EDR0" permission = "write/none" } SMPU_0_EAR13 { address = 0xfc010168; sn = "SMPU_0_EAR13"; access = "memorymapped"; width = 32; ${_DESC2179_}; type = "bitfield_SMPU_0_EAR0" permission = "write/none" } SMPU_0_EDR13 { address = 0xfc01016c; sn = "SMPU_0_EDR13"; access = "memorymapped"; width = 32; ${_DESC2181_}; type = "bitfield_SMPU_0_EDR0" permission = "write/none" } SMPU_0_EAR14 { address = 0xfc010170; sn = "SMPU_0_EAR14"; access = "memorymapped"; width = 32; ${_DESC2179_}; type = "bitfield_SMPU_0_EAR0" permission = "write/none" } SMPU_0_EDR14 { address = 0xfc010174; sn = "SMPU_0_EDR14"; access = "memorymapped"; width = 32; ${_DESC2181_}; type = "bitfield_SMPU_0_EDR0" permission = "write/none" } SMPU_0_EAR15 { address = 0xfc010178; sn = "SMPU_0_EAR15"; access = "memorymapped"; width = 32; ${_DESC2179_}; type = "bitfield_SMPU_0_EAR0" permission = "write/none" } SMPU_0_EDR15 { address = 0xfc01017c; sn = "SMPU_0_EDR15"; access = "memorymapped"; width = 32; ${_DESC2181_}; type = "bitfield_SMPU_0_EDR0" permission = "write/none" } SMPU_0_RGD0_WORD0 { address = 0xfc010400; sn = "SMPU_0_RGD0_WORD0"; access = "memorymapped"; width = 32; ${_DESC2187_}; type = "bitfield_SMPU_0_RGD0_WORD0" } SMPU_0_RGD0_WORD1 { address = 0xfc010404; sn = "SMPU_0_RGD0_WORD1"; access = "memorymapped"; width = 32; ${_DESC2189_}; type = "bitfield_SMPU_0_RGD0_WORD1" } SMPU_0_RGD0_WORD2_FMT0 { address = 0xfc010408; sn = "SMPU_0_RGD0_WORD2_FMT0"; access = "memorymapped"; width = 32; ${_DESC2191_}; type = "bitfield_SMPU_0_RGD0_WORD2_FMT0" } SMPU_0_RGD0_WORD2_FMT1 { address = 0xfc010408; sn = "SMPU_0_RGD0_WORD2_FMT1"; access = "memorymapped"; width = 32; ${_DESC2208_}; type = "bitfield_SMPU_0_RGD0_WORD2_FMT1" } SMPU_0_RGD0_WORD3 { address = 0xfc01040c; sn = "SMPU_0_RGD0_WORD3"; access = "memorymapped"; width = 32; ${_DESC2225_}; type = "bitfield_SMPU_0_RGD0_WORD3" } SMPU_0_RGD1_WORD0 { address = 0xfc010410; sn = "SMPU_0_RGD1_WORD0"; access = "memorymapped"; width = 32; ${_DESC2187_}; type = "bitfield_SMPU_0_RGD0_WORD0" } SMPU_0_RGD1_WORD1 { address = 0xfc010414; sn = "SMPU_0_RGD1_WORD1"; access = "memorymapped"; width = 32; ${_DESC2189_}; type = "bitfield_SMPU_0_RGD0_WORD1" } SMPU_0_RGD1_WORD2_FMT0 { address = 0xfc010418; sn = "SMPU_0_RGD1_WORD2_FMT0"; access = "memorymapped"; width = 32; ${_DESC2191_}; type = "bitfield_SMPU_0_RGD0_WORD2_FMT0" } SMPU_0_RGD1_WORD2_FMT1 { address = 0xfc010418; sn = "SMPU_0_RGD1_WORD2_FMT1"; access = "memorymapped"; width = 32; ${_DESC2208_}; type = "bitfield_SMPU_0_RGD0_WORD2_FMT1" } SMPU_0_RGD1_WORD3 { address = 0xfc01041c; sn = "SMPU_0_RGD1_WORD3"; access = "memorymapped"; width = 32; ${_DESC2225_}; type = "bitfield_SMPU_0_RGD0_WORD3" } SMPU_0_RGD2_WORD0 { address = 0xfc010420; sn = "SMPU_0_RGD2_WORD0"; access = "memorymapped"; width = 32; ${_DESC2187_}; type = "bitfield_SMPU_0_RGD0_WORD0" } SMPU_0_RGD2_WORD1 { address = 0xfc010424; sn = "SMPU_0_RGD2_WORD1"; access = "memorymapped"; width = 32; ${_DESC2189_}; type = "bitfield_SMPU_0_RGD0_WORD1" } SMPU_0_RGD2_WORD2_FMT0 { address = 0xfc010428; sn = "SMPU_0_RGD2_WORD2_FMT0"; access = "memorymapped"; width = 32; ${_DESC2191_}; type = "bitfield_SMPU_0_RGD0_WORD2_FMT0" } SMPU_0_RGD2_WORD2_FMT1 { address = 0xfc010428; sn = "SMPU_0_RGD2_WORD2_FMT1"; access = "memorymapped"; width = 32; ${_DESC2208_}; type = "bitfield_SMPU_0_RGD0_WORD2_FMT1" } SMPU_0_RGD2_WORD3 { address = 0xfc01042c; sn = "SMPU_0_RGD2_WORD3"; access = "memorymapped"; width = 32; ${_DESC2225_}; type = "bitfield_SMPU_0_RGD0_WORD3" } SMPU_0_RGD3_WORD0 { address = 0xfc010430; sn = "SMPU_0_RGD3_WORD0"; access = "memorymapped"; width = 32; ${_DESC2187_}; type = "bitfield_SMPU_0_RGD0_WORD0" } SMPU_0_RGD3_WORD1 { address = 0xfc010434; sn = "SMPU_0_RGD3_WORD1"; access = "memorymapped"; width = 32; ${_DESC2189_}; type = "bitfield_SMPU_0_RGD0_WORD1" } SMPU_0_RGD3_WORD2_FMT0 { address = 0xfc010438; sn = "SMPU_0_RGD3_WORD2_FMT0"; access = "memorymapped"; width = 32; ${_DESC2191_}; type = "bitfield_SMPU_0_RGD0_WORD2_FMT0" } SMPU_0_RGD3_WORD2_FMT1 { address = 0xfc010438; sn = "SMPU_0_RGD3_WORD2_FMT1"; access = "memorymapped"; width = 32; ${_DESC2208_}; type = "bitfield_SMPU_0_RGD0_WORD2_FMT1" } SMPU_0_RGD3_WORD3 { address = 0xfc01043c; sn = "SMPU_0_RGD3_WORD3"; access = "memorymapped"; width = 32; ${_DESC2225_}; type = "bitfield_SMPU_0_RGD0_WORD3" } SMPU_0_RGD4_WORD0 { address = 0xfc010440; sn = "SMPU_0_RGD4_WORD0"; access = "memorymapped"; width = 32; ${_DESC2187_}; type = "bitfield_SMPU_0_RGD0_WORD0" } SMPU_0_RGD4_WORD1 { address = 0xfc010444; sn = "SMPU_0_RGD4_WORD1"; access = "memorymapped"; width = 32; ${_DESC2189_}; type = "bitfield_SMPU_0_RGD0_WORD1" } SMPU_0_RGD4_WORD2_FMT0 { address = 0xfc010448; sn = "SMPU_0_RGD4_WORD2_FMT0"; access = "memorymapped"; width = 32; ${_DESC2191_}; type = "bitfield_SMPU_0_RGD0_WORD2_FMT0" } SMPU_0_RGD4_WORD2_FMT1 { address = 0xfc010448; sn = "SMPU_0_RGD4_WORD2_FMT1"; access = "memorymapped"; width = 32; ${_DESC2208_}; type = "bitfield_SMPU_0_RGD0_WORD2_FMT1" } SMPU_0_RGD4_WORD3 { address = 0xfc01044c; sn = "SMPU_0_RGD4_WORD3"; access = "memorymapped"; width = 32; ${_DESC2225_}; type = "bitfield_SMPU_0_RGD0_WORD3" } SMPU_0_RGD5_WORD0 { address = 0xfc010450; sn = "SMPU_0_RGD5_WORD0"; access = "memorymapped"; width = 32; ${_DESC2187_}; type = "bitfield_SMPU_0_RGD0_WORD0" } SMPU_0_RGD5_WORD1 { address = 0xfc010454; sn = "SMPU_0_RGD5_WORD1"; access = "memorymapped"; width = 32; ${_DESC2189_}; type = "bitfield_SMPU_0_RGD0_WORD1" } SMPU_0_RGD5_WORD2_FMT0 { address = 0xfc010458; sn = "SMPU_0_RGD5_WORD2_FMT0"; access = "memorymapped"; width = 32; ${_DESC2191_}; type = "bitfield_SMPU_0_RGD0_WORD2_FMT0" } SMPU_0_RGD5_WORD2_FMT1 { address = 0xfc010458; sn = "SMPU_0_RGD5_WORD2_FMT1"; access = "memorymapped"; width = 32; ${_DESC2208_}; type = "bitfield_SMPU_0_RGD0_WORD2_FMT1" } SMPU_0_RGD5_WORD3 { address = 0xfc01045c; sn = "SMPU_0_RGD5_WORD3"; access = "memorymapped"; width = 32; ${_DESC2225_}; type = "bitfield_SMPU_0_RGD0_WORD3" } SMPU_0_RGD6_WORD0 { address = 0xfc010460; sn = "SMPU_0_RGD6_WORD0"; access = "memorymapped"; width = 32; ${_DESC2187_}; type = "bitfield_SMPU_0_RGD0_WORD0" } SMPU_0_RGD6_WORD1 { address = 0xfc010464; sn = "SMPU_0_RGD6_WORD1"; access = "memorymapped"; width = 32; ${_DESC2189_}; type = "bitfield_SMPU_0_RGD0_WORD1" } SMPU_0_RGD6_WORD2_FMT0 { address = 0xfc010468; sn = "SMPU_0_RGD6_WORD2_FMT0"; access = "memorymapped"; width = 32; ${_DESC2191_}; type = "bitfield_SMPU_0_RGD0_WORD2_FMT0" } SMPU_0_RGD6_WORD2_FMT1 { address = 0xfc010468; sn = "SMPU_0_RGD6_WORD2_FMT1"; access = "memorymapped"; width = 32; ${_DESC2208_}; type = "bitfield_SMPU_0_RGD0_WORD2_FMT1" } SMPU_0_RGD6_WORD3 { address = 0xfc01046c; sn = "SMPU_0_RGD6_WORD3"; access = "memorymapped"; width = 32; ${_DESC2225_}; type = "bitfield_SMPU_0_RGD0_WORD3" } SMPU_0_RGD7_WORD0 { address = 0xfc010470; sn = "SMPU_0_RGD7_WORD0"; access = "memorymapped"; width = 32; ${_DESC2187_}; type = "bitfield_SMPU_0_RGD0_WORD0" } SMPU_0_RGD7_WORD1 { address = 0xfc010474; sn = "SMPU_0_RGD7_WORD1"; access = "memorymapped"; width = 32; ${_DESC2189_}; type = "bitfield_SMPU_0_RGD0_WORD1" } SMPU_0_RGD7_WORD2_FMT0 { address = 0xfc010478; sn = "SMPU_0_RGD7_WORD2_FMT0"; access = "memorymapped"; width = 32; ${_DESC2191_}; type = "bitfield_SMPU_0_RGD0_WORD2_FMT0" } SMPU_0_RGD7_WORD2_FMT1 { address = 0xfc010478; sn = "SMPU_0_RGD7_WORD2_FMT1"; access = "memorymapped"; width = 32; ${_DESC2208_}; type = "bitfield_SMPU_0_RGD0_WORD2_FMT1" } SMPU_0_RGD7_WORD3 { address = 0xfc01047c; sn = "SMPU_0_RGD7_WORD3"; access = "memorymapped"; width = 32; ${_DESC2225_}; type = "bitfield_SMPU_0_RGD0_WORD3" } SMPU_0_RGD8_WORD0 { address = 0xfc010480; sn = "SMPU_0_RGD8_WORD0"; access = "memorymapped"; width = 32; ${_DESC2187_}; type = "bitfield_SMPU_0_RGD0_WORD0" } SMPU_0_RGD8_WORD1 { address = 0xfc010484; sn = "SMPU_0_RGD8_WORD1"; access = "memorymapped"; width = 32; ${_DESC2189_}; type = "bitfield_SMPU_0_RGD0_WORD1" } SMPU_0_RGD8_WORD2_FMT0 { address = 0xfc010488; sn = "SMPU_0_RGD8_WORD2_FMT0"; access = "memorymapped"; width = 32; ${_DESC2191_}; type = "bitfield_SMPU_0_RGD0_WORD2_FMT0" } SMPU_0_RGD8_WORD2_FMT1 { address = 0xfc010488; sn = "SMPU_0_RGD8_WORD2_FMT1"; access = "memorymapped"; width = 32; ${_DESC2208_}; type = "bitfield_SMPU_0_RGD0_WORD2_FMT1" } SMPU_0_RGD8_WORD3 { address = 0xfc01048c; sn = "SMPU_0_RGD8_WORD3"; access = "memorymapped"; width = 32; ${_DESC2225_}; type = "bitfield_SMPU_0_RGD0_WORD3" } SMPU_0_RGD9_WORD0 { address = 0xfc010490; sn = "SMPU_0_RGD9_WORD0"; access = "memorymapped"; width = 32; ${_DESC2187_}; type = "bitfield_SMPU_0_RGD0_WORD0" } SMPU_0_RGD9_WORD1 { address = 0xfc010494; sn = "SMPU_0_RGD9_WORD1"; access = "memorymapped"; width = 32; ${_DESC2189_}; type = "bitfield_SMPU_0_RGD0_WORD1" } SMPU_0_RGD9_WORD2_FMT0 { address = 0xfc010498; sn = "SMPU_0_RGD9_WORD2_FMT0"; access = "memorymapped"; width = 32; ${_DESC2191_}; type = "bitfield_SMPU_0_RGD0_WORD2_FMT0" } SMPU_0_RGD9_WORD2_FMT1 { address = 0xfc010498; sn = "SMPU_0_RGD9_WORD2_FMT1"; access = "memorymapped"; width = 32; ${_DESC2208_}; type = "bitfield_SMPU_0_RGD0_WORD2_FMT1" } SMPU_0_RGD9_WORD3 { address = 0xfc01049c; sn = "SMPU_0_RGD9_WORD3"; access = "memorymapped"; width = 32; ${_DESC2225_}; type = "bitfield_SMPU_0_RGD0_WORD3" } SMPU_0_RGD10_WORD0 { address = 0xfc0104a0; sn = "SMPU_0_RGD10_WORD0"; access = "memorymapped"; width = 32; ${_DESC2187_}; type = "bitfield_SMPU_0_RGD0_WORD0" } SMPU_0_RGD10_WORD1 { address = 0xfc0104a4; sn = "SMPU_0_RGD10_WORD1"; access = "memorymapped"; width = 32; ${_DESC2189_}; type = "bitfield_SMPU_0_RGD0_WORD1" } SMPU_0_RGD10_WORD2_FMT0 { address = 0xfc0104a8; sn = "SMPU_0_RGD10_WORD2_FMT0"; access = "memorymapped"; width = 32; ${_DESC2191_}; type = "bitfield_SMPU_0_RGD0_WORD2_FMT0" } SMPU_0_RGD10_WORD2_FMT1 { address = 0xfc0104a8; sn = "SMPU_0_RGD10_WORD2_FMT1"; access = "memorymapped"; width = 32; ${_DESC2208_}; type = "bitfield_SMPU_0_RGD0_WORD2_FMT1" } SMPU_0_RGD10_WORD3 { address = 0xfc0104ac; sn = "SMPU_0_RGD10_WORD3"; access = "memorymapped"; width = 32; ${_DESC2225_}; type = "bitfield_SMPU_0_RGD0_WORD3" } SMPU_0_RGD11_WORD0 { address = 0xfc0104b0; sn = "SMPU_0_RGD11_WORD0"; access = "memorymapped"; width = 32; ${_DESC2187_}; type = "bitfield_SMPU_0_RGD0_WORD0" } SMPU_0_RGD11_WORD1 { address = 0xfc0104b4; sn = "SMPU_0_RGD11_WORD1"; access = "memorymapped"; width = 32; ${_DESC2189_}; type = "bitfield_SMPU_0_RGD0_WORD1" } SMPU_0_RGD11_WORD2_FMT0 { address = 0xfc0104b8; sn = "SMPU_0_RGD11_WORD2_FMT0"; access = "memorymapped"; width = 32; ${_DESC2191_}; type = "bitfield_SMPU_0_RGD0_WORD2_FMT0" } SMPU_0_RGD11_WORD2_FMT1 { address = 0xfc0104b8; sn = "SMPU_0_RGD11_WORD2_FMT1"; access = "memorymapped"; width = 32; ${_DESC2208_}; type = "bitfield_SMPU_0_RGD0_WORD2_FMT1" } SMPU_0_RGD11_WORD3 { address = 0xfc0104bc; sn = "SMPU_0_RGD11_WORD3"; access = "memorymapped"; width = 32; ${_DESC2225_}; type = "bitfield_SMPU_0_RGD0_WORD3" } SRX_0_GBL_CTRL { address = 0xffe5c000; sn = "SRX_0_GBL_CTRL"; access = "memorymapped"; width = 32; ${_DESC2233_}; type = "bitfield_SRX_0_GBL_CTRL" } SRX_0_CHNL_EN { address = 0xffe5c004; sn = "SRX_0_CHNL_EN"; access = "memorymapped"; width = 32; ${_DESC2240_}; type = "bitfield_SRX_0_CHNL_EN" } SRX_0_GBL_STATUS { address = 0xffe5c008; sn = "SRX_0_GBL_STATUS"; access = "memorymapped"; width = 32; ${_DESC2242_}; type = "bitfield_SRX_0_GBL_STATUS" } SRX_0_FMSG_RDY { address = 0xffe5c00c; sn = "SRX_0_FMSG_RDY"; access = "memorymapped"; width = 32; ${_DESC2245_}; type = "bitfield_SRX_0_FMSG_RDY" } SRX_0_SMSG_RDY { address = 0xffe5c010; sn = "SRX_0_SMSG_RDY"; access = "memorymapped"; width = 32; ${_DESC2247_}; type = "bitfield_SRX_0_SMSG_RDY" } SRX_0_DATA_CTRL1 { address = 0xffe5c018; sn = "SRX_0_DATA_CTRL1"; access = "memorymapped"; width = 32; ${_DESC2249_}; type = "bitfield_SRX_0_DATA_CTRL1" } SRX_0_DATA_CTRL2 { address = 0xffe5c01c; sn = "SRX_0_DATA_CTRL2"; access = "memorymapped"; width = 32; ${_DESC2258_}; type = "bitfield_SRX_0_DATA_CTRL2" } SRX_0_FDMA_CTRL { address = 0xffe5c028; sn = "SRX_0_FDMA_CTRL"; access = "memorymapped"; width = 32; ${_DESC2267_}; type = "bitfield_SRX_0_FDMA_CTRL" } SRX_0_SDMA_CTRL { address = 0xffe5c02c; sn = "SRX_0_SDMA_CTRL"; access = "memorymapped"; width = 32; ${_DESC2269_}; type = "bitfield_SRX_0_SDMA_CTRL" } SRX_0_FRDY_IE { address = 0xffe5c034; sn = "SRX_0_FRDY_IE"; access = "memorymapped"; width = 32; ${_DESC2271_}; type = "bitfield_SRX_0_FRDY_IE" } SRX_0_SRDY_IE { address = 0xffe5c038; sn = "SRX_0_SRDY_IE"; access = "memorymapped"; width = 32; ${_DESC2273_}; type = "bitfield_SRX_0_SRDY_IE" } SRX_0_DMA_FMSG_DATA { address = 0xffe5c040; sn = "SRX_0_DMA_FMSG_DATA"; access = "memorymapped"; width = 32; ${_DESC2275_}; type = "bitfield_SRX_0_DMA_FMSG_DATA" permission = "write/none" } SRX_0_DMA_FMSG_CRC { address = 0xffe5c044; sn = "SRX_0_DMA_FMSG_CRC"; access = "memorymapped"; width = 32; ${_DESC2284_}; type = "bitfield_SRX_0_DMA_FMSG_CRC" permission = "write/none" } SRX_0_DMA_FMSG_TS { address = 0xffe5c048; sn = "SRX_0_DMA_FMSG_TS"; access = "memorymapped"; width = 32; ${_DESC2286_}; type = "bitfield_SRX_0_DMA_FMSG_TS" permission = "write/none" } SRX_0_DMA_SMSG_BIT3 { address = 0xffe5c050; sn = "SRX_0_DMA_SMSG_BIT3"; access = "memorymapped"; width = 32; ${_DESC2288_}; type = "bitfield_SRX_0_DMA_SMSG_BIT3" permission = "write/none" } SRX_0_DMA_SMSG_BIT2 { address = 0xffe5c054; sn = "SRX_0_DMA_SMSG_BIT2"; access = "memorymapped"; width = 32; ${_DESC2295_}; type = "bitfield_SRX_0_DMA_SMSG_BIT2" permission = "write/none" } SRX_0_DMA_SMSG_TS { address = 0xffe5c058; sn = "SRX_0_DMA_SMSG_TS"; access = "memorymapped"; width = 32; ${_DESC2298_}; type = "bitfield_SRX_0_DMA_SMSG_TS" permission = "write/none" } SRX_0_CH0_CLK_CTRL { address = 0xffe5c060; sn = "SRX_0_CH0_CLK_CTRL"; access = "memorymapped"; width = 32; ${_DESC2300_}; type = "bitfield_SRX_0_CH0_CLK_CTRL" } SRX_0_CH0_STATUS { address = 0xffe5c064; sn = "SRX_0_CH0_STATUS"; access = "memorymapped"; width = 32; ${_DESC2304_}; type = "bitfield_SRX_0_CH0_STATUS" } SRX_0_CH0_CONFIG { address = 0xffe5c068; sn = "SRX_0_CH0_CONFIG"; access = "memorymapped"; width = 32; ${_DESC2317_}; type = "bitfield_SRX_0_CH0_CONFIG" } SRX_0_CH1_CLK_CTRL { address = 0xffe5c070; sn = "SRX_0_CH1_CLK_CTRL"; access = "memorymapped"; width = 32; ${_DESC2300_}; type = "bitfield_SRX_0_CH0_CLK_CTRL" } SRX_0_CH1_STATUS { address = 0xffe5c074; sn = "SRX_0_CH1_STATUS"; access = "memorymapped"; width = 32; ${_DESC2304_}; type = "bitfield_SRX_0_CH0_STATUS" } SRX_0_CH1_CONFIG { address = 0xffe5c078; sn = "SRX_0_CH1_CONFIG"; access = "memorymapped"; width = 32; ${_DESC2317_}; type = "bitfield_SRX_0_CH0_CONFIG" } SRX_0_CH2_CLK_CTRL { address = 0xffe5c080; sn = "SRX_0_CH2_CLK_CTRL"; access = "memorymapped"; width = 32; ${_DESC2300_}; type = "bitfield_SRX_0_CH0_CLK_CTRL" } SRX_0_CH2_STATUS { address = 0xffe5c084; sn = "SRX_0_CH2_STATUS"; access = "memorymapped"; width = 32; ${_DESC2304_}; type = "bitfield_SRX_0_CH0_STATUS" } SRX_0_CH2_CONFIG { address = 0xffe5c088; sn = "SRX_0_CH2_CONFIG"; access = "memorymapped"; width = 32; ${_DESC2317_}; type = "bitfield_SRX_0_CH0_CONFIG" } SRX_0_CH3_CLK_CTRL { address = 0xffe5c090; sn = "SRX_0_CH3_CLK_CTRL"; access = "memorymapped"; width = 32; ${_DESC2300_}; type = "bitfield_SRX_0_CH0_CLK_CTRL" } SRX_0_CH3_STATUS { address = 0xffe5c094; sn = "SRX_0_CH3_STATUS"; access = "memorymapped"; width = 32; ${_DESC2304_}; type = "bitfield_SRX_0_CH0_STATUS" } SRX_0_CH3_CONFIG { address = 0xffe5c098; sn = "SRX_0_CH3_CONFIG"; access = "memorymapped"; width = 32; ${_DESC2317_}; type = "bitfield_SRX_0_CH0_CONFIG" } SRX_0_CH0_FMSG_DATA { address = 0xffe5c160; sn = "SRX_0_CH0_FMSG_DATA"; access = "memorymapped"; width = 32; ${_DESC2340_}; type = "bitfield_SRX_0_DMA_FMSG_DATA" permission = "write/none" } SRX_0_CH0_FMSG_CRC { address = 0xffe5c164; sn = "SRX_0_CH0_FMSG_CRC"; access = "memorymapped"; width = 32; ${_DESC2341_}; type = "bitfield_SRX_0_DMA_FMSG_CRC" permission = "write/none" } SRX_0_CH0_FMSG_TS { address = 0xffe5c168; sn = "SRX_0_CH0_FMSG_TS"; access = "memorymapped"; width = 32; ${_DESC2342_}; type = "bitfield_SRX_0_DMA_FMSG_TS" permission = "write/none" } SRX_0_CH0_SMSG_BIT3 { address = 0xffe5c16c; sn = "SRX_0_CH0_SMSG_BIT3"; access = "memorymapped"; width = 32; ${_DESC2343_}; type = "bitfield_SRX_0_CH0_SMSG_BIT3" permission = "write/none" } SRX_0_CH0_SMSG_BIT2 { address = 0xffe5c170; sn = "SRX_0_CH0_SMSG_BIT2"; access = "memorymapped"; width = 32; ${_DESC2345_}; type = "bitfield_SRX_0_DMA_SMSG_BIT2" permission = "write/none" } SRX_0_CH0_SMSG_TS { address = 0xffe5c174; sn = "SRX_0_CH0_SMSG_TS"; access = "memorymapped"; width = 32; ${_DESC2346_}; type = "bitfield_SRX_0_DMA_SMSG_TS" permission = "write/none" } SRX_0_CH1_FMSG_DATA { address = 0xffe5c178; sn = "SRX_0_CH1_FMSG_DATA"; access = "memorymapped"; width = 32; ${_DESC2340_}; type = "bitfield_SRX_0_DMA_FMSG_DATA" permission = "write/none" } SRX_0_CH1_FMSG_CRC { address = 0xffe5c17c; sn = "SRX_0_CH1_FMSG_CRC"; access = "memorymapped"; width = 32; ${_DESC2341_}; type = "bitfield_SRX_0_DMA_FMSG_CRC" permission = "write/none" } SRX_0_CH1_FMSG_TS { address = 0xffe5c180; sn = "SRX_0_CH1_FMSG_TS"; access = "memorymapped"; width = 32; ${_DESC2342_}; type = "bitfield_SRX_0_DMA_FMSG_TS" permission = "write/none" } SRX_0_CH1_SMSG_BIT3 { address = 0xffe5c184; sn = "SRX_0_CH1_SMSG_BIT3"; access = "memorymapped"; width = 32; ${_DESC2343_}; type = "bitfield_SRX_0_CH0_SMSG_BIT3" permission = "write/none" } SRX_0_CH1_SMSG_BIT2 { address = 0xffe5c188; sn = "SRX_0_CH1_SMSG_BIT2"; access = "memorymapped"; width = 32; ${_DESC2345_}; type = "bitfield_SRX_0_DMA_SMSG_BIT2" permission = "write/none" } SRX_0_CH1_SMSG_TS { address = 0xffe5c18c; sn = "SRX_0_CH1_SMSG_TS"; access = "memorymapped"; width = 32; ${_DESC2346_}; type = "bitfield_SRX_0_DMA_SMSG_TS" permission = "write/none" } SRX_0_CH2_FMSG_DATA { address = 0xffe5c190; sn = "SRX_0_CH2_FMSG_DATA"; access = "memorymapped"; width = 32; ${_DESC2340_}; type = "bitfield_SRX_0_DMA_FMSG_DATA" permission = "write/none" } SRX_0_CH2_FMSG_CRC { address = 0xffe5c194; sn = "SRX_0_CH2_FMSG_CRC"; access = "memorymapped"; width = 32; ${_DESC2341_}; type = "bitfield_SRX_0_DMA_FMSG_CRC" permission = "write/none" } SRX_0_CH2_FMSG_TS { address = 0xffe5c198; sn = "SRX_0_CH2_FMSG_TS"; access = "memorymapped"; width = 32; ${_DESC2342_}; type = "bitfield_SRX_0_DMA_FMSG_TS" permission = "write/none" } SRX_0_CH2_SMSG_BIT3 { address = 0xffe5c19c; sn = "SRX_0_CH2_SMSG_BIT3"; access = "memorymapped"; width = 32; ${_DESC2343_}; type = "bitfield_SRX_0_CH0_SMSG_BIT3" permission = "write/none" } SRX_0_CH2_SMSG_BIT2 { address = 0xffe5c1a0; sn = "SRX_0_CH2_SMSG_BIT2"; access = "memorymapped"; width = 32; ${_DESC2345_}; type = "bitfield_SRX_0_DMA_SMSG_BIT2" permission = "write/none" } SRX_0_CH2_SMSG_TS { address = 0xffe5c1a4; sn = "SRX_0_CH2_SMSG_TS"; access = "memorymapped"; width = 32; ${_DESC2346_}; type = "bitfield_SRX_0_DMA_SMSG_TS" permission = "write/none" } SRX_0_CH3_FMSG_DATA { address = 0xffe5c1a8; sn = "SRX_0_CH3_FMSG_DATA"; access = "memorymapped"; width = 32; ${_DESC2340_}; type = "bitfield_SRX_0_DMA_FMSG_DATA" permission = "write/none" } SRX_0_CH3_FMSG_CRC { address = 0xffe5c1ac; sn = "SRX_0_CH3_FMSG_CRC"; access = "memorymapped"; width = 32; ${_DESC2341_}; type = "bitfield_SRX_0_DMA_FMSG_CRC" permission = "write/none" } SRX_0_CH3_FMSG_TS { address = 0xffe5c1b0; sn = "SRX_0_CH3_FMSG_TS"; access = "memorymapped"; width = 32; ${_DESC2342_}; type = "bitfield_SRX_0_DMA_FMSG_TS" permission = "write/none" } SRX_0_CH3_SMSG_BIT3 { address = 0xffe5c1b4; sn = "SRX_0_CH3_SMSG_BIT3"; access = "memorymapped"; width = 32; ${_DESC2343_}; type = "bitfield_SRX_0_CH0_SMSG_BIT3" permission = "write/none" } SRX_0_CH3_SMSG_BIT2 { address = 0xffe5c1b8; sn = "SRX_0_CH3_SMSG_BIT2"; access = "memorymapped"; width = 32; ${_DESC2345_}; type = "bitfield_SRX_0_DMA_SMSG_BIT2" permission = "write/none" } SRX_0_CH3_SMSG_TS { address = 0xffe5c1bc; sn = "SRX_0_CH3_SMSG_TS"; access = "memorymapped"; width = 32; ${_DESC2346_}; type = "bitfield_SRX_0_DMA_SMSG_TS" permission = "write/none" } SSCM_STATUS { address = 0xffff8000; sn = "SSCM_STATUS"; access = "memorymapped"; width = 16; ${_DESC2347_}; type = "bitfield_SSCM_STATUS" permission = "write/none" } SSCM_MEMCONFIG { address = 0xffff8002; sn = "SSCM_MEMCONFIG"; access = "memorymapped"; width = 16; ${_DESC2352_}; type = "bitfield_SSCM_MEMCONFIG" permission = "write/none" } SSCM_ERROR { address = 0xffff8006; sn = "SSCM_ERROR"; access = "memorymapped"; width = 16; ${_DESC2354_}; type = "bitfield_SSCM_ERROR" } SSCM_PSA { address = 0xffff8028; sn = "SSCM_PSA"; access = "memorymapped"; width = 32; ${_DESC2357_}; type = "bitfield_SSCM_PSA" permission = "write/none" } SSCM_LCSTAT { address = 0xffff8034; sn = "SSCM_LCSTAT"; access = "memorymapped"; width = 32; ${_DESC2359_}; type = "bitfield_SSCM_LCSTAT" } STM_2_CR { address = 0xfc070000; sn = "STM_2_CR"; access = "memorymapped"; width = 32; ${_DESC2362_}; type = "bitfield_STM_2_CR" } STM_2_CNT { address = 0xfc070004; sn = "STM_2_CNT"; access = "memorymapped"; width = 32; ${_DESC2365_}; type = "bitfield_STM_2_CNT" } STM_2_CCR0 { address = 0xfc070010; sn = "STM_2_CCR0"; access = "memorymapped"; width = 32; ${_DESC2367_}; type = "bitfield_STM_2_CCR0" } STM_2_CIR0 { address = 0xfc070014; sn = "STM_2_CIR0"; access = "memorymapped"; width = 32; ${_DESC2368_}; type = "bitfield_STM_2_CIR0" } STM_2_CMP0 { address = 0xfc070018; sn = "STM_2_CMP0"; access = "memorymapped"; width = 32; ${_DESC2369_}; type = "bitfield_STM_2_CMP0" } STM_2_CCR1 { address = 0xfc070020; sn = "STM_2_CCR1"; access = "memorymapped"; width = 32; ${_DESC2367_}; type = "bitfield_STM_2_CCR0" } STM_2_CIR1 { address = 0xfc070024; sn = "STM_2_CIR1"; access = "memorymapped"; width = 32; ${_DESC2368_}; type = "bitfield_STM_2_CIR0" } STM_2_CMP1 { address = 0xfc070028; sn = "STM_2_CMP1"; access = "memorymapped"; width = 32; ${_DESC2369_}; type = "bitfield_STM_2_CMP0" } STM_2_CCR2 { address = 0xfc070030; sn = "STM_2_CCR2"; access = "memorymapped"; width = 32; ${_DESC2367_}; type = "bitfield_STM_2_CCR0" } STM_2_CIR2 { address = 0xfc070034; sn = "STM_2_CIR2"; access = "memorymapped"; width = 32; ${_DESC2368_}; type = "bitfield_STM_2_CIR0" } STM_2_CMP2 { address = 0xfc070038; sn = "STM_2_CMP2"; access = "memorymapped"; width = 32; ${_DESC2369_}; type = "bitfield_STM_2_CMP0" } STM_2_CCR3 { address = 0xfc070040; sn = "STM_2_CCR3"; access = "memorymapped"; width = 32; ${_DESC2367_}; type = "bitfield_STM_2_CCR0" } STM_2_CIR3 { address = 0xfc070044; sn = "STM_2_CIR3"; access = "memorymapped"; width = 32; ${_DESC2368_}; type = "bitfield_STM_2_CIR0" } STM_2_CMP3 { address = 0xfc070048; sn = "STM_2_CMP3"; access = "memorymapped"; width = 32; ${_DESC2369_}; type = "bitfield_STM_2_CMP0" } SWT_2_CR { address = 0xfc058000; sn = "SWT_2_CR"; access = "memorymapped"; width = 32; ${_DESC2371_}; type = "bitfield_SWT_2_CR" } SWT_2_IR { address = 0xfc058004; sn = "SWT_2_IR"; access = "memorymapped"; width = 32; ${_DESC2389_}; type = "bitfield_SWT_2_IR" } SWT_2_TO { address = 0xfc058008; sn = "SWT_2_TO"; access = "memorymapped"; width = 32; ${_DESC2391_}; type = "bitfield_SWT_2_TO" } SWT_2_WN { address = 0xfc05800c; sn = "SWT_2_WN"; access = "memorymapped"; width = 32; ${_DESC2393_}; type = "bitfield_SWT_2_WN" } SWT_2_SR { address = 0xfc058010; sn = "SWT_2_SR"; access = "memorymapped"; width = 32; ${_DESC2395_}; type = "bitfield_SWT_2_SR" permission = "read/none" } SWT_2_CO { address = 0xfc058014; sn = "SWT_2_CO"; access = "memorymapped"; width = 32; ${_DESC2397_}; type = "bitfield_SWT_2_CO" permission = "write/none" } SWT_2_SK { address = 0xfc058018; sn = "SWT_2_SK"; access = "memorymapped"; width = 32; ${_DESC2399_}; type = "bitfield_SWT_2_SK" } SWT_3_CR { address = 0xfc05c000; sn = "SWT_3_CR"; access = "memorymapped"; width = 32; ${_DESC2371_}; type = "bitfield_SWT_2_CR" } SWT_3_IR { address = 0xfc05c004; sn = "SWT_3_IR"; access = "memorymapped"; width = 32; ${_DESC2389_}; type = "bitfield_SWT_2_IR" } SWT_3_TO { address = 0xfc05c008; sn = "SWT_3_TO"; access = "memorymapped"; width = 32; ${_DESC2391_}; type = "bitfield_SWT_2_TO" } SWT_3_WN { address = 0xfc05c00c; sn = "SWT_3_WN"; access = "memorymapped"; width = 32; ${_DESC2393_}; type = "bitfield_SWT_2_WN" } SWT_3_SR { address = 0xfc05c010; sn = "SWT_3_SR"; access = "memorymapped"; width = 32; ${_DESC2395_}; type = "bitfield_SWT_2_SR" permission = "read/none" } SWT_3_CO { address = 0xfc05c014; sn = "SWT_3_CO"; access = "memorymapped"; width = 32; ${_DESC2397_}; type = "bitfield_SWT_2_CO" permission = "write/none" } SWT_3_SK { address = 0xfc05c018; sn = "SWT_3_SK"; access = "memorymapped"; width = 32; ${_DESC2399_}; type = "bitfield_SWT_2_SK" } WKPU_NSR { address = 0xfff98000; sn = "WKPU_NSR"; access = "memorymapped"; width = 32; ${_DESC2401_}; type = "bitfield_WKPU_NSR" } WKPU_NCR { address = 0xfff98008; sn = "WKPU_NCR"; access = "memorymapped"; width = 32; ${_DESC2406_}; type = "bitfield_WKPU_NCR" } WKPU_WISR { address = 0xfff98014; sn = "WKPU_WISR"; access = "memorymapped"; width = 32; ${_DESC2407_}; type = "bitfield_WKPU_WISR" } WKPU_IRER { address = 0xfff98018; sn = "WKPU_IRER"; access = "memorymapped"; width = 32; ${_DESC2408_}; type = "bitfield_WKPU_IRER" } WKPU_WIREER { address = 0xfff98028; sn = "WKPU_WIREER"; access = "memorymapped"; width = 32; ${_DESC2409_}; type = "bitfield_WKPU_WIREER" } WKPU_WIFEER { address = 0xfff9802c; sn = "WKPU_WIFEER"; access = "memorymapped"; width = 32; ${_DESC2410_}; type = "bitfield_WKPU_WIFEER" } XBAR_0_PRS0 { address = 0xfc004000; sn = "XBAR_0_PRS0"; access = "memorymapped"; width = 32; ${_DESC2411_}; type = "bitfield_XBAR_0_PRS0" permission = "write/none" } XBAR_0_CRS0 { address = 0xfc004010; sn = "XBAR_0_CRS0"; access = "memorymapped"; width = 32; ${_DESC2415_}; type = "bitfield_XBAR_0_CRS0" } XBAR_0_PRS1 { address = 0xfc004100; sn = "XBAR_0_PRS1"; access = "memorymapped"; width = 32; ${_DESC2411_}; type = "bitfield_XBAR_0_PRS0" permission = "write/none" } XBAR_0_CRS1 { address = 0xfc004110; sn = "XBAR_0_CRS1"; access = "memorymapped"; width = 32; ${_DESC2415_}; type = "bitfield_XBAR_0_CRS0" } XBAR_0_PRS2 { address = 0xfc004200; sn = "XBAR_0_PRS2"; access = "memorymapped"; width = 32; ${_DESC2411_}; type = "bitfield_XBAR_0_PRS0" permission = "write/none" } XBAR_0_CRS2 { address = 0xfc004210; sn = "XBAR_0_CRS2"; access = "memorymapped"; width = 32; ${_DESC2415_}; type = "bitfield_XBAR_0_CRS0" } XOSC_CTL { address = 0xfffb0080; sn = "XOSC_CTL"; access = "memorymapped"; width = 32; ${_DESC2424_}; type = "bitfield_XOSC_CTL" } eDMA_0_CR { address = 0xfc0a0000; sn = "eDMA_0_CR"; access = "memorymapped"; width = 32; ${_DESC2429_}; type = "bitfield_eDMA_0_CR" } eDMA_0_ES { address = 0xfc0a0004; sn = "eDMA_0_ES"; access = "memorymapped"; width = 32; ${_DESC2439_}; type = "bitfield_eDMA_0_ES" permission = "write/none" } eDMA_0_ERQL { address = 0xfc0a000c; sn = "eDMA_0_ERQL"; access = "memorymapped"; width = 32; ${_DESC2453_}; type = "bitfield_eDMA_0_ERQL" } eDMA_0_EEIL { address = 0xfc0a0014; sn = "eDMA_0_EEIL"; access = "memorymapped"; width = 32; ${_DESC2470_}; type = "bitfield_eDMA_0_EEIL" } eDMA_0_SERQ { address = 0xfc0a0018; sn = "eDMA_0_SERQ"; access = "memorymapped"; width = 8; ${_DESC2487_}; type = "bitfield_eDMA_0_SERQ" permission = "read/none" } eDMA_0_CERQ { address = 0xfc0a0019; sn = "eDMA_0_CERQ"; access = "memorymapped"; width = 8; ${_DESC2491_}; type = "bitfield_eDMA_0_CERQ" permission = "read/none" } eDMA_0_SEEI { address = 0xfc0a001a; sn = "eDMA_0_SEEI"; access = "memorymapped"; width = 8; ${_DESC2494_}; type = "bitfield_eDMA_0_SEEI" permission = "read/none" } eDMA_0_CEEI { address = 0xfc0a001b; sn = "eDMA_0_CEEI"; access = "memorymapped"; width = 8; ${_DESC2497_}; type = "bitfield_eDMA_0_CEEI" permission = "read/none" } eDMA_0_CINT { address = 0xfc0a001c; sn = "eDMA_0_CINT"; access = "memorymapped"; width = 8; ${_DESC2500_}; type = "bitfield_eDMA_0_CINT" permission = "read/none" } eDMA_0_CERR { address = 0xfc0a001d; sn = "eDMA_0_CERR"; access = "memorymapped"; width = 8; ${_DESC2503_}; type = "bitfield_eDMA_0_CERR" permission = "read/none" } eDMA_0_SSRT { address = 0xfc0a001e; sn = "eDMA_0_SSRT"; access = "memorymapped"; width = 8; ${_DESC2506_}; type = "bitfield_eDMA_0_SSRT" permission = "read/none" } eDMA_0_CDNE { address = 0xfc0a001f; sn = "eDMA_0_CDNE"; access = "memorymapped"; width = 8; ${_DESC2509_}; type = "bitfield_eDMA_0_CDNE" permission = "read/none" } eDMA_0_INTL { address = 0xfc0a0024; sn = "eDMA_0_INTL"; access = "memorymapped"; width = 32; ${_DESC2512_}; type = "bitfield_eDMA_0_INTL" } eDMA_0_ERRL { address = 0xfc0a002c; sn = "eDMA_0_ERRL"; access = "memorymapped"; width = 32; ${_DESC2529_}; type = "bitfield_eDMA_0_ERRL" } eDMA_0_HRSL { address = 0xfc0a0034; sn = "eDMA_0_HRSL"; access = "memorymapped"; width = 32; ${_DESC2546_}; type = "bitfield_eDMA_0_HRSL" } eDMA_0_DCHPRI0 { address = 0xfc0a0100; sn = "eDMA_0_DCHPRI0"; access = "memorymapped"; width = 8; ${_DESC2563_}; type = "bitfield_eDMA_0_DCHPRI0" } eDMA_0_DCHPRI1 { address = 0xfc0a0101; sn = "eDMA_0_DCHPRI1"; access = "memorymapped"; width = 8; ${_DESC2563_}; type = "bitfield_eDMA_0_DCHPRI0" } eDMA_0_DCHPRI2 { address = 0xfc0a0102; sn = "eDMA_0_DCHPRI2"; access = "memorymapped"; width = 8; ${_DESC2563_}; type = "bitfield_eDMA_0_DCHPRI0" } eDMA_0_DCHPRI3 { address = 0xfc0a0103; sn = "eDMA_0_DCHPRI3"; access = "memorymapped"; width = 8; ${_DESC2563_}; type = "bitfield_eDMA_0_DCHPRI0" } eDMA_0_DCHPRI4 { address = 0xfc0a0104; sn = "eDMA_0_DCHPRI4"; access = "memorymapped"; width = 8; ${_DESC2563_}; type = "bitfield_eDMA_0_DCHPRI0" } eDMA_0_DCHPRI5 { address = 0xfc0a0105; sn = "eDMA_0_DCHPRI5"; access = "memorymapped"; width = 8; ${_DESC2563_}; type = "bitfield_eDMA_0_DCHPRI0" } eDMA_0_DCHPRI6 { address = 0xfc0a0106; sn = "eDMA_0_DCHPRI6"; access = "memorymapped"; width = 8; ${_DESC2563_}; type = "bitfield_eDMA_0_DCHPRI0" } eDMA_0_DCHPRI7 { address = 0xfc0a0107; sn = "eDMA_0_DCHPRI7"; access = "memorymapped"; width = 8; ${_DESC2563_}; type = "bitfield_eDMA_0_DCHPRI0" } eDMA_0_DCHPRI8 { address = 0xfc0a0108; sn = "eDMA_0_DCHPRI8"; access = "memorymapped"; width = 8; ${_DESC2563_}; type = "bitfield_eDMA_0_DCHPRI0" } eDMA_0_DCHPRI9 { address = 0xfc0a0109; sn = "eDMA_0_DCHPRI9"; access = "memorymapped"; width = 8; ${_DESC2563_}; type = "bitfield_eDMA_0_DCHPRI0" } eDMA_0_DCHPRI10 { address = 0xfc0a010a; sn = "eDMA_0_DCHPRI10"; access = "memorymapped"; width = 8; ${_DESC2563_}; type = "bitfield_eDMA_0_DCHPRI0" } eDMA_0_DCHPRI11 { address = 0xfc0a010b; sn = "eDMA_0_DCHPRI11"; access = "memorymapped"; width = 8; ${_DESC2563_}; type = "bitfield_eDMA_0_DCHPRI0" } eDMA_0_DCHPRI12 { address = 0xfc0a010c; sn = "eDMA_0_DCHPRI12"; access = "memorymapped"; width = 8; ${_DESC2563_}; type = "bitfield_eDMA_0_DCHPRI0" } eDMA_0_DCHPRI13 { address = 0xfc0a010d; sn = "eDMA_0_DCHPRI13"; access = "memorymapped"; width = 8; ${_DESC2563_}; type = "bitfield_eDMA_0_DCHPRI0" } eDMA_0_DCHPRI14 { address = 0xfc0a010e; sn = "eDMA_0_DCHPRI14"; access = "memorymapped"; width = 8; ${_DESC2563_}; type = "bitfield_eDMA_0_DCHPRI0" } eDMA_0_DCHPRI15 { address = 0xfc0a010f; sn = "eDMA_0_DCHPRI15"; access = "memorymapped"; width = 8; ${_DESC2563_}; type = "bitfield_eDMA_0_DCHPRI0" } eDMA_0_DCHMID0 { address = 0xfc0a0140; sn = "eDMA_0_DCHMID0"; access = "memorymapped"; width = 8; ${_DESC2567_}; type = "bitfield_eDMA_0_DCHMID0" } eDMA_0_DCHMID1 { address = 0xfc0a0141; sn = "eDMA_0_DCHMID1"; access = "memorymapped"; width = 8; ${_DESC2567_}; type = "bitfield_eDMA_0_DCHMID0" } eDMA_0_DCHMID2 { address = 0xfc0a0142; sn = "eDMA_0_DCHMID2"; access = "memorymapped"; width = 8; ${_DESC2567_}; type = "bitfield_eDMA_0_DCHMID0" } eDMA_0_DCHMID3 { address = 0xfc0a0143; sn = "eDMA_0_DCHMID3"; access = "memorymapped"; width = 8; ${_DESC2567_}; type = "bitfield_eDMA_0_DCHMID0" } eDMA_0_DCHMID4 { address = 0xfc0a0144; sn = "eDMA_0_DCHMID4"; access = "memorymapped"; width = 8; ${_DESC2567_}; type = "bitfield_eDMA_0_DCHMID0" } eDMA_0_DCHMID5 { address = 0xfc0a0145; sn = "eDMA_0_DCHMID5"; access = "memorymapped"; width = 8; ${_DESC2567_}; type = "bitfield_eDMA_0_DCHMID0" } eDMA_0_DCHMID6 { address = 0xfc0a0146; sn = "eDMA_0_DCHMID6"; access = "memorymapped"; width = 8; ${_DESC2567_}; type = "bitfield_eDMA_0_DCHMID0" } eDMA_0_DCHMID7 { address = 0xfc0a0147; sn = "eDMA_0_DCHMID7"; access = "memorymapped"; width = 8; ${_DESC2567_}; type = "bitfield_eDMA_0_DCHMID0" } eDMA_0_DCHMID8 { address = 0xfc0a0148; sn = "eDMA_0_DCHMID8"; access = "memorymapped"; width = 8; ${_DESC2567_}; type = "bitfield_eDMA_0_DCHMID0" } eDMA_0_DCHMID9 { address = 0xfc0a0149; sn = "eDMA_0_DCHMID9"; access = "memorymapped"; width = 8; ${_DESC2567_}; type = "bitfield_eDMA_0_DCHMID0" } eDMA_0_DCHMID10 { address = 0xfc0a014a; sn = "eDMA_0_DCHMID10"; access = "memorymapped"; width = 8; ${_DESC2567_}; type = "bitfield_eDMA_0_DCHMID0" } eDMA_0_DCHMID11 { address = 0xfc0a014b; sn = "eDMA_0_DCHMID11"; access = "memorymapped"; width = 8; ${_DESC2567_}; type = "bitfield_eDMA_0_DCHMID0" } eDMA_0_DCHMID12 { address = 0xfc0a014c; sn = "eDMA_0_DCHMID12"; access = "memorymapped"; width = 8; ${_DESC2567_}; type = "bitfield_eDMA_0_DCHMID0" } eDMA_0_DCHMID13 { address = 0xfc0a014d; sn = "eDMA_0_DCHMID13"; access = "memorymapped"; width = 8; ${_DESC2567_}; type = "bitfield_eDMA_0_DCHMID0" } eDMA_0_DCHMID14 { address = 0xfc0a014e; sn = "eDMA_0_DCHMID14"; access = "memorymapped"; width = 8; ${_DESC2567_}; type = "bitfield_eDMA_0_DCHMID0" } eDMA_0_DCHMID15 { address = 0xfc0a014f; sn = "eDMA_0_DCHMID15"; access = "memorymapped"; width = 8; ${_DESC2567_}; type = "bitfield_eDMA_0_DCHMID0" } eDMA_0_TCD0_SADDR { address = 0xfc0a1000; sn = "eDMA_0_TCD0_SADDR"; access = "memorymapped"; width = 32; ${_DESC2571_}; type = "bitfield_eDMA_0_TCD0_SADDR" } eDMA_0_TCD0_ATTR { address = 0xfc0a1004; sn = "eDMA_0_TCD0_ATTR"; access = "memorymapped"; width = 16; ${_DESC2573_}; type = "bitfield_eDMA_0_TCD0_ATTR" } eDMA_0_TCD0_SOFF { address = 0xfc0a1006; sn = "eDMA_0_TCD0_SOFF"; access = "memorymapped"; width = 16; ${_DESC2578_}; type = "bitfield_eDMA_0_TCD0_SOFF" } eDMA_0_TCD0_NBYTES_MLNO { address = 0xfc0a1008; sn = "eDMA_0_TCD0_NBYTES_MLNO"; access = "memorymapped"; width = 32; ${_DESC2580_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLNO" } eDMA_0_TCD0_NBYTES_MLOFFNO { address = 0xfc0a1008; sn = "eDMA_0_TCD0_NBYTES_MLOFFNO"; access = "memorymapped"; width = 32; ${_DESC2582_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFNO" } eDMA_0_TCD0_NBYTES_MLOFFYES { address = 0xfc0a1008; sn = "eDMA_0_TCD0_NBYTES_MLOFFYES"; access = "memorymapped"; width = 32; ${_DESC2586_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFYES" } eDMA_0_TCD0_SLAST { address = 0xfc0a100c; sn = "eDMA_0_TCD0_SLAST"; access = "memorymapped"; width = 32; ${_DESC2588_}; type = "bitfield_eDMA_0_TCD0_SLAST" } eDMA_0_TCD0_DADDR { address = 0xfc0a1010; sn = "eDMA_0_TCD0_DADDR"; access = "memorymapped"; width = 32; ${_DESC2590_}; type = "bitfield_eDMA_0_TCD0_DADDR" } eDMA_0_TCD0_CITER_ELINKYES { address = 0xfc0a1014; sn = "eDMA_0_TCD0_CITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2592_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKYES" } eDMA_0_TCD0_CITER_ELINKNO { address = 0xfc0a1014; sn = "eDMA_0_TCD0_CITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2596_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKNO" } eDMA_0_TCD0_DOFF { address = 0xfc0a1016; sn = "eDMA_0_TCD0_DOFF"; access = "memorymapped"; width = 16; ${_DESC2599_}; type = "bitfield_eDMA_0_TCD0_DOFF" } eDMA_0_TCD0_DLASTSGA { address = 0xfc0a1018; sn = "eDMA_0_TCD0_DLASTSGA"; access = "memorymapped"; width = 32; ${_DESC2601_}; type = "bitfield_eDMA_0_TCD0_DLASTSGA" } eDMA_0_TCD0_BITER_ELINKYES { address = 0xfc0a101c; sn = "eDMA_0_TCD0_BITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2603_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKYES" } eDMA_0_TCD0_BITER_ELINKNO { address = 0xfc0a101c; sn = "eDMA_0_TCD0_BITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2607_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKNO" } eDMA_0_TCD0_CSR { address = 0xfc0a101e; sn = "eDMA_0_TCD0_CSR"; access = "memorymapped"; width = 16; ${_DESC2608_}; type = "bitfield_eDMA_0_TCD0_CSR" } eDMA_0_TCD1_SADDR { address = 0xfc0a1020; sn = "eDMA_0_TCD1_SADDR"; access = "memorymapped"; width = 32; ${_DESC2571_}; type = "bitfield_eDMA_0_TCD0_SADDR" } eDMA_0_TCD1_ATTR { address = 0xfc0a1024; sn = "eDMA_0_TCD1_ATTR"; access = "memorymapped"; width = 16; ${_DESC2573_}; type = "bitfield_eDMA_0_TCD0_ATTR" } eDMA_0_TCD1_SOFF { address = 0xfc0a1026; sn = "eDMA_0_TCD1_SOFF"; access = "memorymapped"; width = 16; ${_DESC2578_}; type = "bitfield_eDMA_0_TCD0_SOFF" } eDMA_0_TCD1_NBYTES_MLNO { address = 0xfc0a1028; sn = "eDMA_0_TCD1_NBYTES_MLNO"; access = "memorymapped"; width = 32; ${_DESC2580_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLNO" } eDMA_0_TCD1_NBYTES_MLOFFNO { address = 0xfc0a1028; sn = "eDMA_0_TCD1_NBYTES_MLOFFNO"; access = "memorymapped"; width = 32; ${_DESC2582_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFNO" } eDMA_0_TCD1_NBYTES_MLOFFYES { address = 0xfc0a1028; sn = "eDMA_0_TCD1_NBYTES_MLOFFYES"; access = "memorymapped"; width = 32; ${_DESC2586_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFYES" } eDMA_0_TCD1_SLAST { address = 0xfc0a102c; sn = "eDMA_0_TCD1_SLAST"; access = "memorymapped"; width = 32; ${_DESC2588_}; type = "bitfield_eDMA_0_TCD0_SLAST" } eDMA_0_TCD1_DADDR { address = 0xfc0a1030; sn = "eDMA_0_TCD1_DADDR"; access = "memorymapped"; width = 32; ${_DESC2590_}; type = "bitfield_eDMA_0_TCD0_DADDR" } eDMA_0_TCD1_CITER_ELINKYES { address = 0xfc0a1034; sn = "eDMA_0_TCD1_CITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2592_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKYES" } eDMA_0_TCD1_CITER_ELINKNO { address = 0xfc0a1034; sn = "eDMA_0_TCD1_CITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2596_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKNO" } eDMA_0_TCD1_DOFF { address = 0xfc0a1036; sn = "eDMA_0_TCD1_DOFF"; access = "memorymapped"; width = 16; ${_DESC2599_}; type = "bitfield_eDMA_0_TCD0_DOFF" } eDMA_0_TCD1_DLASTSGA { address = 0xfc0a1038; sn = "eDMA_0_TCD1_DLASTSGA"; access = "memorymapped"; width = 32; ${_DESC2601_}; type = "bitfield_eDMA_0_TCD0_DLASTSGA" } eDMA_0_TCD1_BITER_ELINKYES { address = 0xfc0a103c; sn = "eDMA_0_TCD1_BITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2603_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKYES" } eDMA_0_TCD1_BITER_ELINKNO { address = 0xfc0a103c; sn = "eDMA_0_TCD1_BITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2607_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKNO" } eDMA_0_TCD1_CSR { address = 0xfc0a103e; sn = "eDMA_0_TCD1_CSR"; access = "memorymapped"; width = 16; ${_DESC2608_}; type = "bitfield_eDMA_0_TCD0_CSR" } eDMA_0_TCD2_SADDR { address = 0xfc0a1040; sn = "eDMA_0_TCD2_SADDR"; access = "memorymapped"; width = 32; ${_DESC2571_}; type = "bitfield_eDMA_0_TCD0_SADDR" } eDMA_0_TCD2_ATTR { address = 0xfc0a1044; sn = "eDMA_0_TCD2_ATTR"; access = "memorymapped"; width = 16; ${_DESC2573_}; type = "bitfield_eDMA_0_TCD0_ATTR" } eDMA_0_TCD2_SOFF { address = 0xfc0a1046; sn = "eDMA_0_TCD2_SOFF"; access = "memorymapped"; width = 16; ${_DESC2578_}; type = "bitfield_eDMA_0_TCD0_SOFF" } eDMA_0_TCD2_NBYTES_MLNO { address = 0xfc0a1048; sn = "eDMA_0_TCD2_NBYTES_MLNO"; access = "memorymapped"; width = 32; ${_DESC2580_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLNO" } eDMA_0_TCD2_NBYTES_MLOFFNO { address = 0xfc0a1048; sn = "eDMA_0_TCD2_NBYTES_MLOFFNO"; access = "memorymapped"; width = 32; ${_DESC2582_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFNO" } eDMA_0_TCD2_NBYTES_MLOFFYES { address = 0xfc0a1048; sn = "eDMA_0_TCD2_NBYTES_MLOFFYES"; access = "memorymapped"; width = 32; ${_DESC2586_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFYES" } eDMA_0_TCD2_SLAST { address = 0xfc0a104c; sn = "eDMA_0_TCD2_SLAST"; access = "memorymapped"; width = 32; ${_DESC2588_}; type = "bitfield_eDMA_0_TCD0_SLAST" } eDMA_0_TCD2_DADDR { address = 0xfc0a1050; sn = "eDMA_0_TCD2_DADDR"; access = "memorymapped"; width = 32; ${_DESC2590_}; type = "bitfield_eDMA_0_TCD0_DADDR" } eDMA_0_TCD2_CITER_ELINKYES { address = 0xfc0a1054; sn = "eDMA_0_TCD2_CITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2592_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKYES" } eDMA_0_TCD2_CITER_ELINKNO { address = 0xfc0a1054; sn = "eDMA_0_TCD2_CITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2596_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKNO" } eDMA_0_TCD2_DOFF { address = 0xfc0a1056; sn = "eDMA_0_TCD2_DOFF"; access = "memorymapped"; width = 16; ${_DESC2599_}; type = "bitfield_eDMA_0_TCD0_DOFF" } eDMA_0_TCD2_DLASTSGA { address = 0xfc0a1058; sn = "eDMA_0_TCD2_DLASTSGA"; access = "memorymapped"; width = 32; ${_DESC2601_}; type = "bitfield_eDMA_0_TCD0_DLASTSGA" } eDMA_0_TCD2_BITER_ELINKYES { address = 0xfc0a105c; sn = "eDMA_0_TCD2_BITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2603_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKYES" } eDMA_0_TCD2_BITER_ELINKNO { address = 0xfc0a105c; sn = "eDMA_0_TCD2_BITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2607_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKNO" } eDMA_0_TCD2_CSR { address = 0xfc0a105e; sn = "eDMA_0_TCD2_CSR"; access = "memorymapped"; width = 16; ${_DESC2608_}; type = "bitfield_eDMA_0_TCD0_CSR" } eDMA_0_TCD3_SADDR { address = 0xfc0a1060; sn = "eDMA_0_TCD3_SADDR"; access = "memorymapped"; width = 32; ${_DESC2571_}; type = "bitfield_eDMA_0_TCD0_SADDR" } eDMA_0_TCD3_ATTR { address = 0xfc0a1064; sn = "eDMA_0_TCD3_ATTR"; access = "memorymapped"; width = 16; ${_DESC2573_}; type = "bitfield_eDMA_0_TCD0_ATTR" } eDMA_0_TCD3_SOFF { address = 0xfc0a1066; sn = "eDMA_0_TCD3_SOFF"; access = "memorymapped"; width = 16; ${_DESC2578_}; type = "bitfield_eDMA_0_TCD0_SOFF" } eDMA_0_TCD3_NBYTES_MLNO { address = 0xfc0a1068; sn = "eDMA_0_TCD3_NBYTES_MLNO"; access = "memorymapped"; width = 32; ${_DESC2580_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLNO" } eDMA_0_TCD3_NBYTES_MLOFFNO { address = 0xfc0a1068; sn = "eDMA_0_TCD3_NBYTES_MLOFFNO"; access = "memorymapped"; width = 32; ${_DESC2582_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFNO" } eDMA_0_TCD3_NBYTES_MLOFFYES { address = 0xfc0a1068; sn = "eDMA_0_TCD3_NBYTES_MLOFFYES"; access = "memorymapped"; width = 32; ${_DESC2586_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFYES" } eDMA_0_TCD3_SLAST { address = 0xfc0a106c; sn = "eDMA_0_TCD3_SLAST"; access = "memorymapped"; width = 32; ${_DESC2588_}; type = "bitfield_eDMA_0_TCD0_SLAST" } eDMA_0_TCD3_DADDR { address = 0xfc0a1070; sn = "eDMA_0_TCD3_DADDR"; access = "memorymapped"; width = 32; ${_DESC2590_}; type = "bitfield_eDMA_0_TCD0_DADDR" } eDMA_0_TCD3_CITER_ELINKYES { address = 0xfc0a1074; sn = "eDMA_0_TCD3_CITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2592_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKYES" } eDMA_0_TCD3_CITER_ELINKNO { address = 0xfc0a1074; sn = "eDMA_0_TCD3_CITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2596_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKNO" } eDMA_0_TCD3_DOFF { address = 0xfc0a1076; sn = "eDMA_0_TCD3_DOFF"; access = "memorymapped"; width = 16; ${_DESC2599_}; type = "bitfield_eDMA_0_TCD0_DOFF" } eDMA_0_TCD3_DLASTSGA { address = 0xfc0a1078; sn = "eDMA_0_TCD3_DLASTSGA"; access = "memorymapped"; width = 32; ${_DESC2601_}; type = "bitfield_eDMA_0_TCD0_DLASTSGA" } eDMA_0_TCD3_BITER_ELINKYES { address = 0xfc0a107c; sn = "eDMA_0_TCD3_BITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2603_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKYES" } eDMA_0_TCD3_BITER_ELINKNO { address = 0xfc0a107c; sn = "eDMA_0_TCD3_BITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2607_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKNO" } eDMA_0_TCD3_CSR { address = 0xfc0a107e; sn = "eDMA_0_TCD3_CSR"; access = "memorymapped"; width = 16; ${_DESC2608_}; type = "bitfield_eDMA_0_TCD0_CSR" } eDMA_0_TCD4_SADDR { address = 0xfc0a1080; sn = "eDMA_0_TCD4_SADDR"; access = "memorymapped"; width = 32; ${_DESC2571_}; type = "bitfield_eDMA_0_TCD0_SADDR" } eDMA_0_TCD4_ATTR { address = 0xfc0a1084; sn = "eDMA_0_TCD4_ATTR"; access = "memorymapped"; width = 16; ${_DESC2573_}; type = "bitfield_eDMA_0_TCD0_ATTR" } eDMA_0_TCD4_SOFF { address = 0xfc0a1086; sn = "eDMA_0_TCD4_SOFF"; access = "memorymapped"; width = 16; ${_DESC2578_}; type = "bitfield_eDMA_0_TCD0_SOFF" } eDMA_0_TCD4_NBYTES_MLNO { address = 0xfc0a1088; sn = "eDMA_0_TCD4_NBYTES_MLNO"; access = "memorymapped"; width = 32; ${_DESC2580_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLNO" } eDMA_0_TCD4_NBYTES_MLOFFNO { address = 0xfc0a1088; sn = "eDMA_0_TCD4_NBYTES_MLOFFNO"; access = "memorymapped"; width = 32; ${_DESC2582_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFNO" } eDMA_0_TCD4_NBYTES_MLOFFYES { address = 0xfc0a1088; sn = "eDMA_0_TCD4_NBYTES_MLOFFYES"; access = "memorymapped"; width = 32; ${_DESC2586_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFYES" } eDMA_0_TCD4_SLAST { address = 0xfc0a108c; sn = "eDMA_0_TCD4_SLAST"; access = "memorymapped"; width = 32; ${_DESC2588_}; type = "bitfield_eDMA_0_TCD0_SLAST" } eDMA_0_TCD4_DADDR { address = 0xfc0a1090; sn = "eDMA_0_TCD4_DADDR"; access = "memorymapped"; width = 32; ${_DESC2590_}; type = "bitfield_eDMA_0_TCD0_DADDR" } eDMA_0_TCD4_CITER_ELINKYES { address = 0xfc0a1094; sn = "eDMA_0_TCD4_CITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2592_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKYES" } eDMA_0_TCD4_CITER_ELINKNO { address = 0xfc0a1094; sn = "eDMA_0_TCD4_CITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2596_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKNO" } eDMA_0_TCD4_DOFF { address = 0xfc0a1096; sn = "eDMA_0_TCD4_DOFF"; access = "memorymapped"; width = 16; ${_DESC2599_}; type = "bitfield_eDMA_0_TCD0_DOFF" } eDMA_0_TCD4_DLASTSGA { address = 0xfc0a1098; sn = "eDMA_0_TCD4_DLASTSGA"; access = "memorymapped"; width = 32; ${_DESC2601_}; type = "bitfield_eDMA_0_TCD0_DLASTSGA" } eDMA_0_TCD4_BITER_ELINKYES { address = 0xfc0a109c; sn = "eDMA_0_TCD4_BITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2603_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKYES" } eDMA_0_TCD4_BITER_ELINKNO { address = 0xfc0a109c; sn = "eDMA_0_TCD4_BITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2607_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKNO" } eDMA_0_TCD4_CSR { address = 0xfc0a109e; sn = "eDMA_0_TCD4_CSR"; access = "memorymapped"; width = 16; ${_DESC2608_}; type = "bitfield_eDMA_0_TCD0_CSR" } eDMA_0_TCD5_SADDR { address = 0xfc0a10a0; sn = "eDMA_0_TCD5_SADDR"; access = "memorymapped"; width = 32; ${_DESC2571_}; type = "bitfield_eDMA_0_TCD0_SADDR" } eDMA_0_TCD5_ATTR { address = 0xfc0a10a4; sn = "eDMA_0_TCD5_ATTR"; access = "memorymapped"; width = 16; ${_DESC2573_}; type = "bitfield_eDMA_0_TCD0_ATTR" } eDMA_0_TCD5_SOFF { address = 0xfc0a10a6; sn = "eDMA_0_TCD5_SOFF"; access = "memorymapped"; width = 16; ${_DESC2578_}; type = "bitfield_eDMA_0_TCD0_SOFF" } eDMA_0_TCD5_NBYTES_MLNO { address = 0xfc0a10a8; sn = "eDMA_0_TCD5_NBYTES_MLNO"; access = "memorymapped"; width = 32; ${_DESC2580_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLNO" } eDMA_0_TCD5_NBYTES_MLOFFNO { address = 0xfc0a10a8; sn = "eDMA_0_TCD5_NBYTES_MLOFFNO"; access = "memorymapped"; width = 32; ${_DESC2582_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFNO" } eDMA_0_TCD5_NBYTES_MLOFFYES { address = 0xfc0a10a8; sn = "eDMA_0_TCD5_NBYTES_MLOFFYES"; access = "memorymapped"; width = 32; ${_DESC2586_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFYES" } eDMA_0_TCD5_SLAST { address = 0xfc0a10ac; sn = "eDMA_0_TCD5_SLAST"; access = "memorymapped"; width = 32; ${_DESC2588_}; type = "bitfield_eDMA_0_TCD0_SLAST" } eDMA_0_TCD5_DADDR { address = 0xfc0a10b0; sn = "eDMA_0_TCD5_DADDR"; access = "memorymapped"; width = 32; ${_DESC2590_}; type = "bitfield_eDMA_0_TCD0_DADDR" } eDMA_0_TCD5_CITER_ELINKYES { address = 0xfc0a10b4; sn = "eDMA_0_TCD5_CITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2592_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKYES" } eDMA_0_TCD5_CITER_ELINKNO { address = 0xfc0a10b4; sn = "eDMA_0_TCD5_CITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2596_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKNO" } eDMA_0_TCD5_DOFF { address = 0xfc0a10b6; sn = "eDMA_0_TCD5_DOFF"; access = "memorymapped"; width = 16; ${_DESC2599_}; type = "bitfield_eDMA_0_TCD0_DOFF" } eDMA_0_TCD5_DLASTSGA { address = 0xfc0a10b8; sn = "eDMA_0_TCD5_DLASTSGA"; access = "memorymapped"; width = 32; ${_DESC2601_}; type = "bitfield_eDMA_0_TCD0_DLASTSGA" } eDMA_0_TCD5_BITER_ELINKYES { address = 0xfc0a10bc; sn = "eDMA_0_TCD5_BITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2603_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKYES" } eDMA_0_TCD5_BITER_ELINKNO { address = 0xfc0a10bc; sn = "eDMA_0_TCD5_BITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2607_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKNO" } eDMA_0_TCD5_CSR { address = 0xfc0a10be; sn = "eDMA_0_TCD5_CSR"; access = "memorymapped"; width = 16; ${_DESC2608_}; type = "bitfield_eDMA_0_TCD0_CSR" } eDMA_0_TCD6_SADDR { address = 0xfc0a10c0; sn = "eDMA_0_TCD6_SADDR"; access = "memorymapped"; width = 32; ${_DESC2571_}; type = "bitfield_eDMA_0_TCD0_SADDR" } eDMA_0_TCD6_ATTR { address = 0xfc0a10c4; sn = "eDMA_0_TCD6_ATTR"; access = "memorymapped"; width = 16; ${_DESC2573_}; type = "bitfield_eDMA_0_TCD0_ATTR" } eDMA_0_TCD6_SOFF { address = 0xfc0a10c6; sn = "eDMA_0_TCD6_SOFF"; access = "memorymapped"; width = 16; ${_DESC2578_}; type = "bitfield_eDMA_0_TCD0_SOFF" } eDMA_0_TCD6_NBYTES_MLNO { address = 0xfc0a10c8; sn = "eDMA_0_TCD6_NBYTES_MLNO"; access = "memorymapped"; width = 32; ${_DESC2580_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLNO" } eDMA_0_TCD6_NBYTES_MLOFFNO { address = 0xfc0a10c8; sn = "eDMA_0_TCD6_NBYTES_MLOFFNO"; access = "memorymapped"; width = 32; ${_DESC2582_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFNO" } eDMA_0_TCD6_NBYTES_MLOFFYES { address = 0xfc0a10c8; sn = "eDMA_0_TCD6_NBYTES_MLOFFYES"; access = "memorymapped"; width = 32; ${_DESC2586_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFYES" } eDMA_0_TCD6_SLAST { address = 0xfc0a10cc; sn = "eDMA_0_TCD6_SLAST"; access = "memorymapped"; width = 32; ${_DESC2588_}; type = "bitfield_eDMA_0_TCD0_SLAST" } eDMA_0_TCD6_DADDR { address = 0xfc0a10d0; sn = "eDMA_0_TCD6_DADDR"; access = "memorymapped"; width = 32; ${_DESC2590_}; type = "bitfield_eDMA_0_TCD0_DADDR" } eDMA_0_TCD6_CITER_ELINKYES { address = 0xfc0a10d4; sn = "eDMA_0_TCD6_CITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2592_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKYES" } eDMA_0_TCD6_CITER_ELINKNO { address = 0xfc0a10d4; sn = "eDMA_0_TCD6_CITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2596_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKNO" } eDMA_0_TCD6_DOFF { address = 0xfc0a10d6; sn = "eDMA_0_TCD6_DOFF"; access = "memorymapped"; width = 16; ${_DESC2599_}; type = "bitfield_eDMA_0_TCD0_DOFF" } eDMA_0_TCD6_DLASTSGA { address = 0xfc0a10d8; sn = "eDMA_0_TCD6_DLASTSGA"; access = "memorymapped"; width = 32; ${_DESC2601_}; type = "bitfield_eDMA_0_TCD0_DLASTSGA" } eDMA_0_TCD6_BITER_ELINKYES { address = 0xfc0a10dc; sn = "eDMA_0_TCD6_BITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2603_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKYES" } eDMA_0_TCD6_BITER_ELINKNO { address = 0xfc0a10dc; sn = "eDMA_0_TCD6_BITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2607_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKNO" } eDMA_0_TCD6_CSR { address = 0xfc0a10de; sn = "eDMA_0_TCD6_CSR"; access = "memorymapped"; width = 16; ${_DESC2608_}; type = "bitfield_eDMA_0_TCD0_CSR" } eDMA_0_TCD7_SADDR { address = 0xfc0a10e0; sn = "eDMA_0_TCD7_SADDR"; access = "memorymapped"; width = 32; ${_DESC2571_}; type = "bitfield_eDMA_0_TCD0_SADDR" } eDMA_0_TCD7_ATTR { address = 0xfc0a10e4; sn = "eDMA_0_TCD7_ATTR"; access = "memorymapped"; width = 16; ${_DESC2573_}; type = "bitfield_eDMA_0_TCD0_ATTR" } eDMA_0_TCD7_SOFF { address = 0xfc0a10e6; sn = "eDMA_0_TCD7_SOFF"; access = "memorymapped"; width = 16; ${_DESC2578_}; type = "bitfield_eDMA_0_TCD0_SOFF" } eDMA_0_TCD7_NBYTES_MLNO { address = 0xfc0a10e8; sn = "eDMA_0_TCD7_NBYTES_MLNO"; access = "memorymapped"; width = 32; ${_DESC2580_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLNO" } eDMA_0_TCD7_NBYTES_MLOFFNO { address = 0xfc0a10e8; sn = "eDMA_0_TCD7_NBYTES_MLOFFNO"; access = "memorymapped"; width = 32; ${_DESC2582_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFNO" } eDMA_0_TCD7_NBYTES_MLOFFYES { address = 0xfc0a10e8; sn = "eDMA_0_TCD7_NBYTES_MLOFFYES"; access = "memorymapped"; width = 32; ${_DESC2586_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFYES" } eDMA_0_TCD7_SLAST { address = 0xfc0a10ec; sn = "eDMA_0_TCD7_SLAST"; access = "memorymapped"; width = 32; ${_DESC2588_}; type = "bitfield_eDMA_0_TCD0_SLAST" } eDMA_0_TCD7_DADDR { address = 0xfc0a10f0; sn = "eDMA_0_TCD7_DADDR"; access = "memorymapped"; width = 32; ${_DESC2590_}; type = "bitfield_eDMA_0_TCD0_DADDR" } eDMA_0_TCD7_CITER_ELINKYES { address = 0xfc0a10f4; sn = "eDMA_0_TCD7_CITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2592_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKYES" } eDMA_0_TCD7_CITER_ELINKNO { address = 0xfc0a10f4; sn = "eDMA_0_TCD7_CITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2596_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKNO" } eDMA_0_TCD7_DOFF { address = 0xfc0a10f6; sn = "eDMA_0_TCD7_DOFF"; access = "memorymapped"; width = 16; ${_DESC2599_}; type = "bitfield_eDMA_0_TCD0_DOFF" } eDMA_0_TCD7_DLASTSGA { address = 0xfc0a10f8; sn = "eDMA_0_TCD7_DLASTSGA"; access = "memorymapped"; width = 32; ${_DESC2601_}; type = "bitfield_eDMA_0_TCD0_DLASTSGA" } eDMA_0_TCD7_BITER_ELINKYES { address = 0xfc0a10fc; sn = "eDMA_0_TCD7_BITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2603_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKYES" } eDMA_0_TCD7_BITER_ELINKNO { address = 0xfc0a10fc; sn = "eDMA_0_TCD7_BITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2607_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKNO" } eDMA_0_TCD7_CSR { address = 0xfc0a10fe; sn = "eDMA_0_TCD7_CSR"; access = "memorymapped"; width = 16; ${_DESC2608_}; type = "bitfield_eDMA_0_TCD0_CSR" } eDMA_0_TCD8_SADDR { address = 0xfc0a1100; sn = "eDMA_0_TCD8_SADDR"; access = "memorymapped"; width = 32; ${_DESC2571_}; type = "bitfield_eDMA_0_TCD0_SADDR" } eDMA_0_TCD8_ATTR { address = 0xfc0a1104; sn = "eDMA_0_TCD8_ATTR"; access = "memorymapped"; width = 16; ${_DESC2573_}; type = "bitfield_eDMA_0_TCD0_ATTR" } eDMA_0_TCD8_SOFF { address = 0xfc0a1106; sn = "eDMA_0_TCD8_SOFF"; access = "memorymapped"; width = 16; ${_DESC2578_}; type = "bitfield_eDMA_0_TCD0_SOFF" } eDMA_0_TCD8_NBYTES_MLNO { address = 0xfc0a1108; sn = "eDMA_0_TCD8_NBYTES_MLNO"; access = "memorymapped"; width = 32; ${_DESC2580_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLNO" } eDMA_0_TCD8_NBYTES_MLOFFNO { address = 0xfc0a1108; sn = "eDMA_0_TCD8_NBYTES_MLOFFNO"; access = "memorymapped"; width = 32; ${_DESC2582_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFNO" } eDMA_0_TCD8_NBYTES_MLOFFYES { address = 0xfc0a1108; sn = "eDMA_0_TCD8_NBYTES_MLOFFYES"; access = "memorymapped"; width = 32; ${_DESC2586_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFYES" } eDMA_0_TCD8_SLAST { address = 0xfc0a110c; sn = "eDMA_0_TCD8_SLAST"; access = "memorymapped"; width = 32; ${_DESC2588_}; type = "bitfield_eDMA_0_TCD0_SLAST" } eDMA_0_TCD8_DADDR { address = 0xfc0a1110; sn = "eDMA_0_TCD8_DADDR"; access = "memorymapped"; width = 32; ${_DESC2590_}; type = "bitfield_eDMA_0_TCD0_DADDR" } eDMA_0_TCD8_CITER_ELINKYES { address = 0xfc0a1114; sn = "eDMA_0_TCD8_CITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2592_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKYES" } eDMA_0_TCD8_CITER_ELINKNO { address = 0xfc0a1114; sn = "eDMA_0_TCD8_CITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2596_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKNO" } eDMA_0_TCD8_DOFF { address = 0xfc0a1116; sn = "eDMA_0_TCD8_DOFF"; access = "memorymapped"; width = 16; ${_DESC2599_}; type = "bitfield_eDMA_0_TCD0_DOFF" } eDMA_0_TCD8_DLASTSGA { address = 0xfc0a1118; sn = "eDMA_0_TCD8_DLASTSGA"; access = "memorymapped"; width = 32; ${_DESC2601_}; type = "bitfield_eDMA_0_TCD0_DLASTSGA" } eDMA_0_TCD8_BITER_ELINKYES { address = 0xfc0a111c; sn = "eDMA_0_TCD8_BITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2603_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKYES" } eDMA_0_TCD8_BITER_ELINKNO { address = 0xfc0a111c; sn = "eDMA_0_TCD8_BITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2607_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKNO" } eDMA_0_TCD8_CSR { address = 0xfc0a111e; sn = "eDMA_0_TCD8_CSR"; access = "memorymapped"; width = 16; ${_DESC2608_}; type = "bitfield_eDMA_0_TCD0_CSR" } eDMA_0_TCD9_SADDR { address = 0xfc0a1120; sn = "eDMA_0_TCD9_SADDR"; access = "memorymapped"; width = 32; ${_DESC2571_}; type = "bitfield_eDMA_0_TCD0_SADDR" } eDMA_0_TCD9_ATTR { address = 0xfc0a1124; sn = "eDMA_0_TCD9_ATTR"; access = "memorymapped"; width = 16; ${_DESC2573_}; type = "bitfield_eDMA_0_TCD0_ATTR" } eDMA_0_TCD9_SOFF { address = 0xfc0a1126; sn = "eDMA_0_TCD9_SOFF"; access = "memorymapped"; width = 16; ${_DESC2578_}; type = "bitfield_eDMA_0_TCD0_SOFF" } eDMA_0_TCD9_NBYTES_MLNO { address = 0xfc0a1128; sn = "eDMA_0_TCD9_NBYTES_MLNO"; access = "memorymapped"; width = 32; ${_DESC2580_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLNO" } eDMA_0_TCD9_NBYTES_MLOFFNO { address = 0xfc0a1128; sn = "eDMA_0_TCD9_NBYTES_MLOFFNO"; access = "memorymapped"; width = 32; ${_DESC2582_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFNO" } eDMA_0_TCD9_NBYTES_MLOFFYES { address = 0xfc0a1128; sn = "eDMA_0_TCD9_NBYTES_MLOFFYES"; access = "memorymapped"; width = 32; ${_DESC2586_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFYES" } eDMA_0_TCD9_SLAST { address = 0xfc0a112c; sn = "eDMA_0_TCD9_SLAST"; access = "memorymapped"; width = 32; ${_DESC2588_}; type = "bitfield_eDMA_0_TCD0_SLAST" } eDMA_0_TCD9_DADDR { address = 0xfc0a1130; sn = "eDMA_0_TCD9_DADDR"; access = "memorymapped"; width = 32; ${_DESC2590_}; type = "bitfield_eDMA_0_TCD0_DADDR" } eDMA_0_TCD9_CITER_ELINKYES { address = 0xfc0a1134; sn = "eDMA_0_TCD9_CITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2592_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKYES" } eDMA_0_TCD9_CITER_ELINKNO { address = 0xfc0a1134; sn = "eDMA_0_TCD9_CITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2596_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKNO" } eDMA_0_TCD9_DOFF { address = 0xfc0a1136; sn = "eDMA_0_TCD9_DOFF"; access = "memorymapped"; width = 16; ${_DESC2599_}; type = "bitfield_eDMA_0_TCD0_DOFF" } eDMA_0_TCD9_DLASTSGA { address = 0xfc0a1138; sn = "eDMA_0_TCD9_DLASTSGA"; access = "memorymapped"; width = 32; ${_DESC2601_}; type = "bitfield_eDMA_0_TCD0_DLASTSGA" } eDMA_0_TCD9_BITER_ELINKYES { address = 0xfc0a113c; sn = "eDMA_0_TCD9_BITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2603_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKYES" } eDMA_0_TCD9_BITER_ELINKNO { address = 0xfc0a113c; sn = "eDMA_0_TCD9_BITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2607_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKNO" } eDMA_0_TCD9_CSR { address = 0xfc0a113e; sn = "eDMA_0_TCD9_CSR"; access = "memorymapped"; width = 16; ${_DESC2608_}; type = "bitfield_eDMA_0_TCD0_CSR" } eDMA_0_TCD10_SADDR { address = 0xfc0a1140; sn = "eDMA_0_TCD10_SADDR"; access = "memorymapped"; width = 32; ${_DESC2571_}; type = "bitfield_eDMA_0_TCD0_SADDR" } eDMA_0_TCD10_ATTR { address = 0xfc0a1144; sn = "eDMA_0_TCD10_ATTR"; access = "memorymapped"; width = 16; ${_DESC2573_}; type = "bitfield_eDMA_0_TCD0_ATTR" } eDMA_0_TCD10_SOFF { address = 0xfc0a1146; sn = "eDMA_0_TCD10_SOFF"; access = "memorymapped"; width = 16; ${_DESC2578_}; type = "bitfield_eDMA_0_TCD0_SOFF" } eDMA_0_TCD10_NBYTES_MLNO { address = 0xfc0a1148; sn = "eDMA_0_TCD10_NBYTES_MLNO"; access = "memorymapped"; width = 32; ${_DESC2580_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLNO" } eDMA_0_TCD10_NBYTES_MLOFFNO { address = 0xfc0a1148; sn = "eDMA_0_TCD10_NBYTES_MLOFFNO"; access = "memorymapped"; width = 32; ${_DESC2582_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFNO" } eDMA_0_TCD10_NBYTES_MLOFFYES { address = 0xfc0a1148; sn = "eDMA_0_TCD10_NBYTES_MLOFFYES"; access = "memorymapped"; width = 32; ${_DESC2586_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFYES" } eDMA_0_TCD10_SLAST { address = 0xfc0a114c; sn = "eDMA_0_TCD10_SLAST"; access = "memorymapped"; width = 32; ${_DESC2588_}; type = "bitfield_eDMA_0_TCD0_SLAST" } eDMA_0_TCD10_DADDR { address = 0xfc0a1150; sn = "eDMA_0_TCD10_DADDR"; access = "memorymapped"; width = 32; ${_DESC2590_}; type = "bitfield_eDMA_0_TCD0_DADDR" } eDMA_0_TCD10_CITER_ELINKYES { address = 0xfc0a1154; sn = "eDMA_0_TCD10_CITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2592_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKYES" } eDMA_0_TCD10_CITER_ELINKNO { address = 0xfc0a1154; sn = "eDMA_0_TCD10_CITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2596_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKNO" } eDMA_0_TCD10_DOFF { address = 0xfc0a1156; sn = "eDMA_0_TCD10_DOFF"; access = "memorymapped"; width = 16; ${_DESC2599_}; type = "bitfield_eDMA_0_TCD0_DOFF" } eDMA_0_TCD10_DLASTSGA { address = 0xfc0a1158; sn = "eDMA_0_TCD10_DLASTSGA"; access = "memorymapped"; width = 32; ${_DESC2601_}; type = "bitfield_eDMA_0_TCD0_DLASTSGA" } eDMA_0_TCD10_BITER_ELINKYES { address = 0xfc0a115c; sn = "eDMA_0_TCD10_BITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2603_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKYES" } eDMA_0_TCD10_BITER_ELINKNO { address = 0xfc0a115c; sn = "eDMA_0_TCD10_BITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2607_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKNO" } eDMA_0_TCD10_CSR { address = 0xfc0a115e; sn = "eDMA_0_TCD10_CSR"; access = "memorymapped"; width = 16; ${_DESC2608_}; type = "bitfield_eDMA_0_TCD0_CSR" } eDMA_0_TCD11_SADDR { address = 0xfc0a1160; sn = "eDMA_0_TCD11_SADDR"; access = "memorymapped"; width = 32; ${_DESC2571_}; type = "bitfield_eDMA_0_TCD0_SADDR" } eDMA_0_TCD11_ATTR { address = 0xfc0a1164; sn = "eDMA_0_TCD11_ATTR"; access = "memorymapped"; width = 16; ${_DESC2573_}; type = "bitfield_eDMA_0_TCD0_ATTR" } eDMA_0_TCD11_SOFF { address = 0xfc0a1166; sn = "eDMA_0_TCD11_SOFF"; access = "memorymapped"; width = 16; ${_DESC2578_}; type = "bitfield_eDMA_0_TCD0_SOFF" } eDMA_0_TCD11_NBYTES_MLNO { address = 0xfc0a1168; sn = "eDMA_0_TCD11_NBYTES_MLNO"; access = "memorymapped"; width = 32; ${_DESC2580_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLNO" } eDMA_0_TCD11_NBYTES_MLOFFNO { address = 0xfc0a1168; sn = "eDMA_0_TCD11_NBYTES_MLOFFNO"; access = "memorymapped"; width = 32; ${_DESC2582_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFNO" } eDMA_0_TCD11_NBYTES_MLOFFYES { address = 0xfc0a1168; sn = "eDMA_0_TCD11_NBYTES_MLOFFYES"; access = "memorymapped"; width = 32; ${_DESC2586_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFYES" } eDMA_0_TCD11_SLAST { address = 0xfc0a116c; sn = "eDMA_0_TCD11_SLAST"; access = "memorymapped"; width = 32; ${_DESC2588_}; type = "bitfield_eDMA_0_TCD0_SLAST" } eDMA_0_TCD11_DADDR { address = 0xfc0a1170; sn = "eDMA_0_TCD11_DADDR"; access = "memorymapped"; width = 32; ${_DESC2590_}; type = "bitfield_eDMA_0_TCD0_DADDR" } eDMA_0_TCD11_CITER_ELINKYES { address = 0xfc0a1174; sn = "eDMA_0_TCD11_CITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2592_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKYES" } eDMA_0_TCD11_CITER_ELINKNO { address = 0xfc0a1174; sn = "eDMA_0_TCD11_CITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2596_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKNO" } eDMA_0_TCD11_DOFF { address = 0xfc0a1176; sn = "eDMA_0_TCD11_DOFF"; access = "memorymapped"; width = 16; ${_DESC2599_}; type = "bitfield_eDMA_0_TCD0_DOFF" } eDMA_0_TCD11_DLASTSGA { address = 0xfc0a1178; sn = "eDMA_0_TCD11_DLASTSGA"; access = "memorymapped"; width = 32; ${_DESC2601_}; type = "bitfield_eDMA_0_TCD0_DLASTSGA" } eDMA_0_TCD11_BITER_ELINKYES { address = 0xfc0a117c; sn = "eDMA_0_TCD11_BITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2603_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKYES" } eDMA_0_TCD11_BITER_ELINKNO { address = 0xfc0a117c; sn = "eDMA_0_TCD11_BITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2607_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKNO" } eDMA_0_TCD11_CSR { address = 0xfc0a117e; sn = "eDMA_0_TCD11_CSR"; access = "memorymapped"; width = 16; ${_DESC2608_}; type = "bitfield_eDMA_0_TCD0_CSR" } eDMA_0_TCD12_SADDR { address = 0xfc0a1180; sn = "eDMA_0_TCD12_SADDR"; access = "memorymapped"; width = 32; ${_DESC2571_}; type = "bitfield_eDMA_0_TCD0_SADDR" } eDMA_0_TCD12_ATTR { address = 0xfc0a1184; sn = "eDMA_0_TCD12_ATTR"; access = "memorymapped"; width = 16; ${_DESC2573_}; type = "bitfield_eDMA_0_TCD0_ATTR" } eDMA_0_TCD12_SOFF { address = 0xfc0a1186; sn = "eDMA_0_TCD12_SOFF"; access = "memorymapped"; width = 16; ${_DESC2578_}; type = "bitfield_eDMA_0_TCD0_SOFF" } eDMA_0_TCD12_NBYTES_MLNO { address = 0xfc0a1188; sn = "eDMA_0_TCD12_NBYTES_MLNO"; access = "memorymapped"; width = 32; ${_DESC2580_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLNO" } eDMA_0_TCD12_NBYTES_MLOFFNO { address = 0xfc0a1188; sn = "eDMA_0_TCD12_NBYTES_MLOFFNO"; access = "memorymapped"; width = 32; ${_DESC2582_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFNO" } eDMA_0_TCD12_NBYTES_MLOFFYES { address = 0xfc0a1188; sn = "eDMA_0_TCD12_NBYTES_MLOFFYES"; access = "memorymapped"; width = 32; ${_DESC2586_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFYES" } eDMA_0_TCD12_SLAST { address = 0xfc0a118c; sn = "eDMA_0_TCD12_SLAST"; access = "memorymapped"; width = 32; ${_DESC2588_}; type = "bitfield_eDMA_0_TCD0_SLAST" } eDMA_0_TCD12_DADDR { address = 0xfc0a1190; sn = "eDMA_0_TCD12_DADDR"; access = "memorymapped"; width = 32; ${_DESC2590_}; type = "bitfield_eDMA_0_TCD0_DADDR" } eDMA_0_TCD12_CITER_ELINKYES { address = 0xfc0a1194; sn = "eDMA_0_TCD12_CITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2592_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKYES" } eDMA_0_TCD12_CITER_ELINKNO { address = 0xfc0a1194; sn = "eDMA_0_TCD12_CITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2596_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKNO" } eDMA_0_TCD12_DOFF { address = 0xfc0a1196; sn = "eDMA_0_TCD12_DOFF"; access = "memorymapped"; width = 16; ${_DESC2599_}; type = "bitfield_eDMA_0_TCD0_DOFF" } eDMA_0_TCD12_DLASTSGA { address = 0xfc0a1198; sn = "eDMA_0_TCD12_DLASTSGA"; access = "memorymapped"; width = 32; ${_DESC2601_}; type = "bitfield_eDMA_0_TCD0_DLASTSGA" } eDMA_0_TCD12_BITER_ELINKYES { address = 0xfc0a119c; sn = "eDMA_0_TCD12_BITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2603_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKYES" } eDMA_0_TCD12_BITER_ELINKNO { address = 0xfc0a119c; sn = "eDMA_0_TCD12_BITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2607_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKNO" } eDMA_0_TCD12_CSR { address = 0xfc0a119e; sn = "eDMA_0_TCD12_CSR"; access = "memorymapped"; width = 16; ${_DESC2608_}; type = "bitfield_eDMA_0_TCD0_CSR" } eDMA_0_TCD13_SADDR { address = 0xfc0a11a0; sn = "eDMA_0_TCD13_SADDR"; access = "memorymapped"; width = 32; ${_DESC2571_}; type = "bitfield_eDMA_0_TCD0_SADDR" } eDMA_0_TCD13_ATTR { address = 0xfc0a11a4; sn = "eDMA_0_TCD13_ATTR"; access = "memorymapped"; width = 16; ${_DESC2573_}; type = "bitfield_eDMA_0_TCD0_ATTR" } eDMA_0_TCD13_SOFF { address = 0xfc0a11a6; sn = "eDMA_0_TCD13_SOFF"; access = "memorymapped"; width = 16; ${_DESC2578_}; type = "bitfield_eDMA_0_TCD0_SOFF" } eDMA_0_TCD13_NBYTES_MLNO { address = 0xfc0a11a8; sn = "eDMA_0_TCD13_NBYTES_MLNO"; access = "memorymapped"; width = 32; ${_DESC2580_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLNO" } eDMA_0_TCD13_NBYTES_MLOFFNO { address = 0xfc0a11a8; sn = "eDMA_0_TCD13_NBYTES_MLOFFNO"; access = "memorymapped"; width = 32; ${_DESC2582_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFNO" } eDMA_0_TCD13_NBYTES_MLOFFYES { address = 0xfc0a11a8; sn = "eDMA_0_TCD13_NBYTES_MLOFFYES"; access = "memorymapped"; width = 32; ${_DESC2586_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFYES" } eDMA_0_TCD13_SLAST { address = 0xfc0a11ac; sn = "eDMA_0_TCD13_SLAST"; access = "memorymapped"; width = 32; ${_DESC2588_}; type = "bitfield_eDMA_0_TCD0_SLAST" } eDMA_0_TCD13_DADDR { address = 0xfc0a11b0; sn = "eDMA_0_TCD13_DADDR"; access = "memorymapped"; width = 32; ${_DESC2590_}; type = "bitfield_eDMA_0_TCD0_DADDR" } eDMA_0_TCD13_CITER_ELINKYES { address = 0xfc0a11b4; sn = "eDMA_0_TCD13_CITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2592_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKYES" } eDMA_0_TCD13_CITER_ELINKNO { address = 0xfc0a11b4; sn = "eDMA_0_TCD13_CITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2596_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKNO" } eDMA_0_TCD13_DOFF { address = 0xfc0a11b6; sn = "eDMA_0_TCD13_DOFF"; access = "memorymapped"; width = 16; ${_DESC2599_}; type = "bitfield_eDMA_0_TCD0_DOFF" } eDMA_0_TCD13_DLASTSGA { address = 0xfc0a11b8; sn = "eDMA_0_TCD13_DLASTSGA"; access = "memorymapped"; width = 32; ${_DESC2601_}; type = "bitfield_eDMA_0_TCD0_DLASTSGA" } eDMA_0_TCD13_BITER_ELINKYES { address = 0xfc0a11bc; sn = "eDMA_0_TCD13_BITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2603_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKYES" } eDMA_0_TCD13_BITER_ELINKNO { address = 0xfc0a11bc; sn = "eDMA_0_TCD13_BITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2607_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKNO" } eDMA_0_TCD13_CSR { address = 0xfc0a11be; sn = "eDMA_0_TCD13_CSR"; access = "memorymapped"; width = 16; ${_DESC2608_}; type = "bitfield_eDMA_0_TCD0_CSR" } eDMA_0_TCD14_SADDR { address = 0xfc0a11c0; sn = "eDMA_0_TCD14_SADDR"; access = "memorymapped"; width = 32; ${_DESC2571_}; type = "bitfield_eDMA_0_TCD0_SADDR" } eDMA_0_TCD14_ATTR { address = 0xfc0a11c4; sn = "eDMA_0_TCD14_ATTR"; access = "memorymapped"; width = 16; ${_DESC2573_}; type = "bitfield_eDMA_0_TCD0_ATTR" } eDMA_0_TCD14_SOFF { address = 0xfc0a11c6; sn = "eDMA_0_TCD14_SOFF"; access = "memorymapped"; width = 16; ${_DESC2578_}; type = "bitfield_eDMA_0_TCD0_SOFF" } eDMA_0_TCD14_NBYTES_MLNO { address = 0xfc0a11c8; sn = "eDMA_0_TCD14_NBYTES_MLNO"; access = "memorymapped"; width = 32; ${_DESC2580_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLNO" } eDMA_0_TCD14_NBYTES_MLOFFNO { address = 0xfc0a11c8; sn = "eDMA_0_TCD14_NBYTES_MLOFFNO"; access = "memorymapped"; width = 32; ${_DESC2582_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFNO" } eDMA_0_TCD14_NBYTES_MLOFFYES { address = 0xfc0a11c8; sn = "eDMA_0_TCD14_NBYTES_MLOFFYES"; access = "memorymapped"; width = 32; ${_DESC2586_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFYES" } eDMA_0_TCD14_SLAST { address = 0xfc0a11cc; sn = "eDMA_0_TCD14_SLAST"; access = "memorymapped"; width = 32; ${_DESC2588_}; type = "bitfield_eDMA_0_TCD0_SLAST" } eDMA_0_TCD14_DADDR { address = 0xfc0a11d0; sn = "eDMA_0_TCD14_DADDR"; access = "memorymapped"; width = 32; ${_DESC2590_}; type = "bitfield_eDMA_0_TCD0_DADDR" } eDMA_0_TCD14_CITER_ELINKYES { address = 0xfc0a11d4; sn = "eDMA_0_TCD14_CITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2592_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKYES" } eDMA_0_TCD14_CITER_ELINKNO { address = 0xfc0a11d4; sn = "eDMA_0_TCD14_CITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2596_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKNO" } eDMA_0_TCD14_DOFF { address = 0xfc0a11d6; sn = "eDMA_0_TCD14_DOFF"; access = "memorymapped"; width = 16; ${_DESC2599_}; type = "bitfield_eDMA_0_TCD0_DOFF" } eDMA_0_TCD14_DLASTSGA { address = 0xfc0a11d8; sn = "eDMA_0_TCD14_DLASTSGA"; access = "memorymapped"; width = 32; ${_DESC2601_}; type = "bitfield_eDMA_0_TCD0_DLASTSGA" } eDMA_0_TCD14_BITER_ELINKYES { address = 0xfc0a11dc; sn = "eDMA_0_TCD14_BITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2603_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKYES" } eDMA_0_TCD14_BITER_ELINKNO { address = 0xfc0a11dc; sn = "eDMA_0_TCD14_BITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2607_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKNO" } eDMA_0_TCD14_CSR { address = 0xfc0a11de; sn = "eDMA_0_TCD14_CSR"; access = "memorymapped"; width = 16; ${_DESC2608_}; type = "bitfield_eDMA_0_TCD0_CSR" } eDMA_0_TCD15_SADDR { address = 0xfc0a11e0; sn = "eDMA_0_TCD15_SADDR"; access = "memorymapped"; width = 32; ${_DESC2571_}; type = "bitfield_eDMA_0_TCD0_SADDR" } eDMA_0_TCD15_ATTR { address = 0xfc0a11e4; sn = "eDMA_0_TCD15_ATTR"; access = "memorymapped"; width = 16; ${_DESC2573_}; type = "bitfield_eDMA_0_TCD0_ATTR" } eDMA_0_TCD15_SOFF { address = 0xfc0a11e6; sn = "eDMA_0_TCD15_SOFF"; access = "memorymapped"; width = 16; ${_DESC2578_}; type = "bitfield_eDMA_0_TCD0_SOFF" } eDMA_0_TCD15_NBYTES_MLNO { address = 0xfc0a11e8; sn = "eDMA_0_TCD15_NBYTES_MLNO"; access = "memorymapped"; width = 32; ${_DESC2580_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLNO" } eDMA_0_TCD15_NBYTES_MLOFFNO { address = 0xfc0a11e8; sn = "eDMA_0_TCD15_NBYTES_MLOFFNO"; access = "memorymapped"; width = 32; ${_DESC2582_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFNO" } eDMA_0_TCD15_NBYTES_MLOFFYES { address = 0xfc0a11e8; sn = "eDMA_0_TCD15_NBYTES_MLOFFYES"; access = "memorymapped"; width = 32; ${_DESC2586_}; type = "bitfield_eDMA_0_TCD0_NBYTES_MLOFFYES" } eDMA_0_TCD15_SLAST { address = 0xfc0a11ec; sn = "eDMA_0_TCD15_SLAST"; access = "memorymapped"; width = 32; ${_DESC2588_}; type = "bitfield_eDMA_0_TCD0_SLAST" } eDMA_0_TCD15_DADDR { address = 0xfc0a11f0; sn = "eDMA_0_TCD15_DADDR"; access = "memorymapped"; width = 32; ${_DESC2590_}; type = "bitfield_eDMA_0_TCD0_DADDR" } eDMA_0_TCD15_CITER_ELINKYES { address = 0xfc0a11f4; sn = "eDMA_0_TCD15_CITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2592_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKYES" } eDMA_0_TCD15_CITER_ELINKNO { address = 0xfc0a11f4; sn = "eDMA_0_TCD15_CITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2596_}; type = "bitfield_eDMA_0_TCD0_CITER_ELINKNO" } eDMA_0_TCD15_DOFF { address = 0xfc0a11f6; sn = "eDMA_0_TCD15_DOFF"; access = "memorymapped"; width = 16; ${_DESC2599_}; type = "bitfield_eDMA_0_TCD0_DOFF" } eDMA_0_TCD15_DLASTSGA { address = 0xfc0a11f8; sn = "eDMA_0_TCD15_DLASTSGA"; access = "memorymapped"; width = 32; ${_DESC2601_}; type = "bitfield_eDMA_0_TCD0_DLASTSGA" } eDMA_0_TCD15_BITER_ELINKYES { address = 0xfc0a11fc; sn = "eDMA_0_TCD15_BITER_ELINKYES"; access = "memorymapped"; width = 16; ${_DESC2603_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKYES" } eDMA_0_TCD15_BITER_ELINKNO { address = 0xfc0a11fc; sn = "eDMA_0_TCD15_BITER_ELINKNO"; access = "memorymapped"; width = 16; ${_DESC2607_}; type = "bitfield_eDMA_0_TCD0_BITER_ELINKNO" } eDMA_0_TCD15_CSR { address = 0xfc0a11fe; sn = "eDMA_0_TCD15_CSR"; access = "memorymapped"; width = 16; ${_DESC2608_}; type = "bitfield_eDMA_0_TCD0_CSR" } } group { CMU_PLL { sn = "CMU_PLL" ln = "CMU_PLL" hk = "CMU_PLL" collapse = true register += {"CMU_PLL_CSR", "CMU_PLL_FDR", "CMU_PLL_HFREFR", "CMU_PLL_LFREFR", "CMU_PLL_ISR"} register += {"CMU_PLL_MDR"} } DECFILTER { sn = "DECFILTER" ln = "DECFILTER" hk = "DECFILTER" collapse = true register += {"DECFILTER_MCR", "DECFILTER_MSR", "DECFILTER_MXCR", "DECFILTER_MXSR"} register += {"DECFILTER_IB", "DECFILTER_OB", "DECFILTER_COEF0", "DECFILTER_COEF1"} register += {"DECFILTER_COEF2", "DECFILTER_COEF3", "DECFILTER_COEF4", "DECFILTER_COEF5"} register += {"DECFILTER_COEF6", "DECFILTER_COEF7", "DECFILTER_COEF8", "DECFILTER_TAP0"} register += {"DECFILTER_TAP1", "DECFILTER_TAP2", "DECFILTER_TAP3", "DECFILTER_TAP4"} register += {"DECFILTER_TAP5", "DECFILTER_TAP6", "DECFILTER_TAP7", "DECFILTER_FINTVAL"} register += {"DECFILTER_FINTCNT", "DECFILTER_CINTVAL", "DECFILTER_CINTCNT"} } DMAMUX_0 { sn = "DMAMUX_0" ln = "DMAMUX_0" hk = "DMAMUX_0" collapse = true register += {"DMAMUX_0_CHCFG0", "DMAMUX_0_CHCFG1", "DMAMUX_0_CHCFG2", "DMAMUX_0_CHCFG3"} register += {"DMAMUX_0_CHCFG4", "DMAMUX_0_CHCFG5", "DMAMUX_0_CHCFG6", "DMAMUX_0_CHCFG7"} } DMAMUX_1 { sn = "DMAMUX_1" ln = "DMAMUX_1" hk = "DMAMUX_1" collapse = true register += {"DMAMUX_1_CHCFG0", "DMAMUX_1_CHCFG1", "DMAMUX_1_CHCFG2", "DMAMUX_1_CHCFG3"} register += {"DMAMUX_1_CHCFG4", "DMAMUX_1_CHCFG5", "DMAMUX_1_CHCFG6", "DMAMUX_1_CHCFG7"} } DSPI_0_RXFRn { sn = "DSPI_0_RXFRn" ln = "DSPI Receive FIFO Registers" hk = "DSPI_0_RXFRn" collapse = true register += {"DSPI_0_RXFR0", "DSPI_0_RXFR1", "DSPI_0_RXFR2", "DSPI_0_RXFR3"} } DSPI_0 { sn = "DSPI_0" ln = "DSPI_0" hk = "DSPI_0" collapse = true register += {"DSPI_0_MCR", "DSPI_0_TCR", "DSPI_0_CTAR0", "DSPI_0_CTAR_SLAVE0"} register += {"DSPI_0_CTAR1", "DSPI_0_CTAR_SLAVE1", "DSPI_0_CTAR2", "DSPI_0_CTAR3"} register += {"DSPI_0_CTAR4", "DSPI_0_CTAR5", "DSPI_0_CTAR6", "DSPI_0_CTAR7", "DSPI_0_SR"} register += {"DSPI_0_RSER", "DSPI_0_PUSHR", "DSPI_0_PUSHR_SLAVE", "DSPI_0_POPR"} register += {"DSPI_0_TXFR0", "DSPI_0_TXFR1", "DSPI_0_TXFR2", "DSPI_0_TXFR3", "DSPI_0_DSICR0"} register += {"DSPI_0_SDR0", "DSPI_0_ASDR0", "DSPI_0_COMPR0", "DSPI_0_DDR0", "DSPI_0_DSICR1"} register += {"DSPI_0_SSR0", "DSPI_0_PISR0", "DSPI_0_PISR1", "DSPI_0_PISR2", "DSPI_0_PISR3"} register += {"DSPI_0_DIMR0", "DSPI_0_DPIR0", "DSPI_0_SDR1", "DSPI_0_ASDR1", "DSPI_0_COMPR1"} register += {"DSPI_0_DDR1", "DSPI_0_SSR1", "DSPI_0_PISR4", "DSPI_0_PISR5", "DSPI_0_PISR6"} register += {"DSPI_0_PISR7", "DSPI_0_DIMR1", "DSPI_0_DPIR1", "DSPI_0_CTARE0"} register += {"DSPI_0_CTARE1", "DSPI_0_CTARE2", "DSPI_0_CTARE3", "DSPI_0_CTARE4"} register += {"DSPI_0_CTARE5", "DSPI_0_CTARE6", "DSPI_0_CTARE7", "DSPI_0_SREX"} group += {"DSPI_0_RXFRn"} } DSPI_4_RXFRn { sn = "DSPI_4_RXFRn" ln = "DSPI Receive FIFO Registers" hk = "DSPI_4_RXFRn" collapse = true register += {"DSPI_4_RXFR0", "DSPI_4_RXFR1", "DSPI_4_RXFR2", "DSPI_4_RXFR3"} } DSPI_4 { sn = "DSPI_4" ln = "DSPI_4" hk = "DSPI_4" collapse = true register += {"DSPI_4_MCR", "DSPI_4_TCR", "DSPI_4_CTAR0", "DSPI_4_CTAR_SLAVE0"} register += {"DSPI_4_CTAR1", "DSPI_4_CTAR_SLAVE1", "DSPI_4_CTAR2", "DSPI_4_CTAR3"} register += {"DSPI_4_CTAR4", "DSPI_4_CTAR5", "DSPI_4_CTAR6", "DSPI_4_CTAR7", "DSPI_4_SR"} register += {"DSPI_4_RSER", "DSPI_4_PUSHR", "DSPI_4_PUSHR_SLAVE", "DSPI_4_POPR"} register += {"DSPI_4_TXFR0", "DSPI_4_TXFR1", "DSPI_4_TXFR2", "DSPI_4_TXFR3", "DSPI_4_DSICR0"} register += {"DSPI_4_SDR0", "DSPI_4_ASDR0", "DSPI_4_COMPR0", "DSPI_4_DDR0", "DSPI_4_DSICR1"} register += {"DSPI_4_SSR0", "DSPI_4_PISR0", "DSPI_4_PISR1", "DSPI_4_PISR2", "DSPI_4_PISR3"} register += {"DSPI_4_DIMR0", "DSPI_4_DPIR0", "DSPI_4_SDR1", "DSPI_4_ASDR1", "DSPI_4_COMPR1"} register += {"DSPI_4_DDR1", "DSPI_4_SSR1", "DSPI_4_PISR4", "DSPI_4_PISR5", "DSPI_4_PISR6"} register += {"DSPI_4_PISR7", "DSPI_4_DIMR1", "DSPI_4_DPIR1", "DSPI_4_CTARE0"} register += {"DSPI_4_CTARE1", "DSPI_4_CTARE2", "DSPI_4_CTARE3", "DSPI_4_CTARE4"} register += {"DSPI_4_CTARE5", "DSPI_4_CTARE6", "DSPI_4_CTARE7", "DSPI_4_SREX"} group += {"DSPI_4_RXFRn"} } DTS { sn = "DTS" ln = "DTS" hk = "DTS" collapse = true register += {"DTS_ENABLE", "DTS_STARTUP", "DTS_SEMAPHORE", "DTS_SEMAPHORE_B"} } EIM { sn = "EIM" ln = "EIM" hk = "EIM" collapse = true register += {"EIMCR", "EIM_EICHEN", "EIM_EICHD0_Word0", "EIM_EICHD0_Word1"} register += {"EIM_EICHD0_Word2", "EIM_EICHD1_Word0", "EIM_EICHD1_Word1", "EIM_EICHD1_Word2"} register += {"EIM_EICHD2_Word0", "EIM_EICHD2_Word1", "EIM_EICHD2_Word2", "EIM_EICHD3_Word0"} register += {"EIM_EICHD3_Word1", "EIM_EICHD3_Word2", "EIM_EICHD4_Word0", "EIM_EICHD4_Word1"} register += {"EIM_EICHD4_Word2", "EIM_EICHD5_Word0", "EIM_EICHD5_Word1", "EIM_EICHD5_Word2"} } ERM { sn = "ERM" ln = "ERM" hk = "ERM" collapse = true register += {"ERM_CR", "ERM_SR", "ERM_EAR0", "ERM_SYN0", "ERM_EAR1", "ERM_SYN1", "ERM_EAR2"} register += {"ERM_SYN2", "ERM_EAR3", "ERM_SYN3", "ERM_EAR4", "ERM_SYN4", "ERM_EAR5"} register += {"ERM_SYN5", "ERM_EAR6", "ERM_SYN6", "ERM_EAR7", "ERM_SYN7"} } FEC { sn = "FEC" ln = "FEC" hk = "FEC" collapse = true register += {"FEC_EIR", "FEC_EIMR", "FEC_RDAR", "FEC_TDAR", "FEC_ECR", "FEC_MMFR"} register += {"FEC_MSCR", "FEC_MIBC", "FEC_RCR", "FEC_TCR", "FEC_PALR", "FEC_PAUR", "FEC_OPD"} register += {"FEC_IAUR", "FEC_IALR", "FEC_GAUR", "FEC_GALR", "FEC_TFWR", "FEC_FRBR"} register += {"FEC_FRSR", "FEC_ERDSR", "FEC_ETDSR", "FEC_EMRBR", "FEC_RMON_T_DROP"} register += {"FEC_RMON_T_PACKETS", "FEC_RMON_T_BC_PKT", "FEC_RMON_T_MC_PKT"} register += {"FEC_RMON_T_CRC_ALIGN", "FEC_RMON_T_UNDERSIZE", "FEC_RMON_T_OVERSIZE"} register += {"FEC_RMON_T_FRAG", "FEC_RMON_T_JAB", "FEC_RMON_T_COL", "FEC_RMON_T_P64"} register += {"FEC_RMON_T_P65TO127", "FEC_RMON_T_P128TO255", "FEC_RMON_T_P256TO511"} register += {"FEC_RMON_T_P512TO1023", "FEC_RMON_T_P1024TO2047", "FEC_RMON_T_P_GTE2048"} register += {"FEC_RMON_T_OCTETS", "FEC_IEEE_T_DROP", "FEC_IEEE_T_FRAME_OK"} register += {"FEC_IEEE_T_1COL", "FEC_IEEE_T_MCOL", "FEC_IEEE_T_DEF", "FEC_IEEE_T_LCOL"} register += {"FEC_IEEE_T_EXCOL", "FEC_IEEE_T_MACERR", "FEC_IEEE_T_CSERR", "FEC_IEEE_T_SQE"} register += {"FEC_IEEE_T_FDXFC", "FEC_IEEE_T_OCTETS_OK", "FEC_RMON_R_DROP"} register += {"FEC_RMON_R_PACKETS", "FEC_RMON_R_BC_PKT", "FEC_RMON_R_MC_PKT"} register += {"FEC_RMON_R_CRC_ALIGN", "FEC_RMON_R_UNDERSIZE", "FEC_RMON_R_OVERSIZE"} register += {"FEC_RMON_R_FRAG", "FEC_RMON_R_JAB", "FEC_RMON_R_RESVD_0", "FEC_RMON_R_P64"} register += {"FEC_RMON_R_P65TO127", "FEC_RMON_R_P128TO255", "FEC_RMON_R_P256TO511"} register += {"FEC_RMON_R_P512TO1023", "FEC_RMON_R_P1024TO2047", "FEC_RMON_R_P_GTE2048"} register += {"FEC_RMON_R_OCTETS", "FEC_IEEE_R_DROP", "FEC_IEEE_R_FRAME_OK", "FEC_IEEE_R_CRC"} register += {"FEC_IEEE_R_ALIGN", "FEC_IEEE_R_MACERR", "FEC_IEEE_R_FDXFC"} register += {"FEC_IEEE_R_OCTETS_OK"} } GTMINT { sn = "GTMINT" ln = "GTMINT" hk = "GTMINT" collapse = true register += {"GTMINT_GTMMCR", "GTMINTCLR", "GTMINT_GTMMAEICR"} } INTC_0 { sn = "INTC_0" ln = "INTC_0" hk = "INTC_0" collapse = true register += {"INTC_0_BCR", "INTC_0_CPR0", "INTC_0_IACKR0", "INTC_0_EOIR0", "INTC_0_SSCIR0"} register += {"INTC_0_SSCIR1", "INTC_0_SSCIR2", "INTC_0_SSCIR3", "INTC_0_SSCIR4"} register += {"INTC_0_SSCIR5", "INTC_0_SSCIR6", "INTC_0_SSCIR7", "INTC_0_SSCIR8"} register += {"INTC_0_SSCIR9", "INTC_0_SSCIR10", "INTC_0_SSCIR11", "INTC_0_SSCIR12"} register += {"INTC_0_SSCIR13", "INTC_0_SSCIR14", "INTC_0_SSCIR15", "INTC_0_SSCIR16"} register += {"INTC_0_SSCIR17", "INTC_0_SSCIR18", "INTC_0_SSCIR19", "INTC_0_SSCIR20"} register += {"INTC_0_SSCIR21", "INTC_0_SSCIR22", "INTC_0_SSCIR23", "INTC_0_SSCIR24"} register += {"INTC_0_SSCIR25", "INTC_0_SSCIR26", "INTC_0_SSCIR27", "INTC_0_SSCIR28"} register += {"INTC_0_SSCIR29", "INTC_0_SSCIR30", "INTC_0_SSCIR31", "INTC_0_PSR0"} register += {"INTC_0_PSR1", "INTC_0_PSR2", "INTC_0_PSR3", "INTC_0_PSR4", "INTC_0_PSR5"} register += {"INTC_0_PSR6", "INTC_0_PSR7", "INTC_0_PSR8", "INTC_0_PSR9", "INTC_0_PSR10"} register += {"INTC_0_PSR11", "INTC_0_PSR12", "INTC_0_PSR13", "INTC_0_PSR14", "INTC_0_PSR15"} register += {"INTC_0_PSR16", "INTC_0_PSR17", "INTC_0_PSR18", "INTC_0_PSR19", "INTC_0_PSR20"} register += {"INTC_0_PSR21", "INTC_0_PSR22", "INTC_0_PSR23", "INTC_0_PSR24", "INTC_0_PSR25"} register += {"INTC_0_PSR26", "INTC_0_PSR27", "INTC_0_PSR28", "INTC_0_PSR29", "INTC_0_PSR30"} register += {"INTC_0_PSR31", "INTC_0_PSR32", "INTC_0_PSR33", "INTC_0_PSR34", "INTC_0_PSR35"} register += {"INTC_0_PSR36", "INTC_0_PSR37", "INTC_0_PSR38", "INTC_0_PSR39", "INTC_0_PSR40"} register += {"INTC_0_PSR41", "INTC_0_PSR42", "INTC_0_PSR43", "INTC_0_PSR44", "INTC_0_PSR45"} register += {"INTC_0_PSR46", "INTC_0_PSR47", "INTC_0_PSR48", "INTC_0_PSR49", "INTC_0_PSR50"} register += {"INTC_0_PSR51", "INTC_0_PSR52", "INTC_0_PSR53", "INTC_0_PSR54", "INTC_0_PSR55"} register += {"INTC_0_PSR56", "INTC_0_PSR57", "INTC_0_PSR58", "INTC_0_PSR59", "INTC_0_PSR60"} register += {"INTC_0_PSR61", "INTC_0_PSR62", "INTC_0_PSR63", "INTC_0_PSR64", "INTC_0_PSR65"} register += {"INTC_0_PSR66", "INTC_0_PSR67", "INTC_0_PSR68", "INTC_0_PSR69", "INTC_0_PSR70"} register += {"INTC_0_PSR71", "INTC_0_PSR72", "INTC_0_PSR73", "INTC_0_PSR74", "INTC_0_PSR75"} register += {"INTC_0_PSR76", "INTC_0_PSR77", "INTC_0_PSR78", "INTC_0_PSR79", "INTC_0_PSR80"} register += {"INTC_0_PSR81", "INTC_0_PSR82", "INTC_0_PSR83", "INTC_0_PSR84", "INTC_0_PSR85"} register += {"INTC_0_PSR86", "INTC_0_PSR87", "INTC_0_PSR88", "INTC_0_PSR89", "INTC_0_PSR90"} register += {"INTC_0_PSR91", "INTC_0_PSR92", "INTC_0_PSR93", "INTC_0_PSR94", "INTC_0_PSR95"} register += {"INTC_0_PSR96", "INTC_0_PSR97", "INTC_0_PSR98", "INTC_0_PSR99", "INTC_0_PSR100"} register += {"INTC_0_PSR101", "INTC_0_PSR102", "INTC_0_PSR103", "INTC_0_PSR104"} register += {"INTC_0_PSR105", "INTC_0_PSR106", "INTC_0_PSR107", "INTC_0_PSR108"} register += {"INTC_0_PSR109", "INTC_0_PSR110", "INTC_0_PSR111", "INTC_0_PSR112"} register += {"INTC_0_PSR113", "INTC_0_PSR114", "INTC_0_PSR115", "INTC_0_PSR116"} register += {"INTC_0_PSR117", "INTC_0_PSR118", "INTC_0_PSR119", "INTC_0_PSR120"} register += {"INTC_0_PSR121", "INTC_0_PSR122", "INTC_0_PSR123", "INTC_0_PSR124"} register += {"INTC_0_PSR125", "INTC_0_PSR126", "INTC_0_PSR127", "INTC_0_PSR128"} register += {"INTC_0_PSR129", "INTC_0_PSR130", "INTC_0_PSR131", "INTC_0_PSR132"} register += {"INTC_0_PSR133", "INTC_0_PSR134", "INTC_0_PSR135", "INTC_0_PSR136"} register += {"INTC_0_PSR137", "INTC_0_PSR138", "INTC_0_PSR139", "INTC_0_PSR140"} register += {"INTC_0_PSR141", "INTC_0_PSR142", "INTC_0_PSR143", "INTC_0_PSR144"} register += {"INTC_0_PSR145", "INTC_0_PSR146", "INTC_0_PSR147", "INTC_0_PSR148"} register += {"INTC_0_PSR149", "INTC_0_PSR150", "INTC_0_PSR151", "INTC_0_PSR152"} register += {"INTC_0_PSR153", "INTC_0_PSR154", "INTC_0_PSR155", "INTC_0_PSR156"} register += {"INTC_0_PSR157", "INTC_0_PSR158", "INTC_0_PSR159", "INTC_0_PSR160"} register += {"INTC_0_PSR161", "INTC_0_PSR162", "INTC_0_PSR163", "INTC_0_PSR164"} register += {"INTC_0_PSR165", "INTC_0_PSR166", "INTC_0_PSR167", "INTC_0_PSR168"} register += {"INTC_0_PSR169", "INTC_0_PSR170", "INTC_0_PSR171", "INTC_0_PSR172"} register += {"INTC_0_PSR173", "INTC_0_PSR174", "INTC_0_PSR175", "INTC_0_PSR176"} register += {"INTC_0_PSR177", "INTC_0_PSR178", "INTC_0_PSR179", "INTC_0_PSR180"} register += {"INTC_0_PSR181", "INTC_0_PSR182", "INTC_0_PSR183", "INTC_0_PSR184"} register += {"INTC_0_PSR185", "INTC_0_PSR186", "INTC_0_PSR187", "INTC_0_PSR188"} register += {"INTC_0_PSR189", "INTC_0_PSR190", "INTC_0_PSR191", "INTC_0_PSR192"} register += {"INTC_0_PSR193", "INTC_0_PSR194", "INTC_0_PSR195", "INTC_0_PSR196"} register += {"INTC_0_PSR197", "INTC_0_PSR198", "INTC_0_PSR199", "INTC_0_PSR200"} register += {"INTC_0_PSR201", "INTC_0_PSR202", "INTC_0_PSR203", "INTC_0_PSR204"} register += {"INTC_0_PSR205", "INTC_0_PSR206", "INTC_0_PSR207", "INTC_0_PSR208"} register += {"INTC_0_PSR209", "INTC_0_PSR210", "INTC_0_PSR211", "INTC_0_PSR212"} register += {"INTC_0_PSR213", "INTC_0_PSR214", "INTC_0_PSR215", "INTC_0_PSR216"} register += {"INTC_0_PSR217", "INTC_0_PSR218", "INTC_0_PSR219", "INTC_0_PSR220"} register += {"INTC_0_PSR221", "INTC_0_PSR222", "INTC_0_PSR223", "INTC_0_PSR224"} register += {"INTC_0_PSR225", "INTC_0_PSR226", "INTC_0_PSR227", "INTC_0_PSR228"} register += {"INTC_0_PSR229", "INTC_0_PSR230", "INTC_0_PSR231", "INTC_0_PSR232"} register += {"INTC_0_PSR233", "INTC_0_PSR234", "INTC_0_PSR235", "INTC_0_PSR236"} register += {"INTC_0_PSR237", "INTC_0_PSR238", "INTC_0_PSR239", "INTC_0_PSR240"} register += {"INTC_0_PSR241", "INTC_0_PSR242", "INTC_0_PSR243", "INTC_0_PSR244"} register += {"INTC_0_PSR245", "INTC_0_PSR246", "INTC_0_PSR247", "INTC_0_PSR248"} register += {"INTC_0_PSR249", "INTC_0_PSR250", "INTC_0_PSR251", "INTC_0_PSR252"} register += {"INTC_0_PSR253", "INTC_0_PSR254", "INTC_0_PSR255", "INTC_0_PSR256"} register += {"INTC_0_PSR257", "INTC_0_PSR258", "INTC_0_PSR259", "INTC_0_PSR260"} register += {"INTC_0_PSR261", "INTC_0_PSR262", "INTC_0_PSR263", "INTC_0_PSR264"} register += {"INTC_0_PSR265", "INTC_0_PSR266", "INTC_0_PSR267", "INTC_0_PSR268"} register += {"INTC_0_PSR269", "INTC_0_PSR270", "INTC_0_PSR271", "INTC_0_PSR272"} register += {"INTC_0_PSR273", "INTC_0_PSR274", "INTC_0_PSR275", "INTC_0_PSR276"} register += {"INTC_0_PSR277", "INTC_0_PSR278", "INTC_0_PSR279", "INTC_0_PSR280"} register += {"INTC_0_PSR281", "INTC_0_PSR282", "INTC_0_PSR283", "INTC_0_PSR284"} register += {"INTC_0_PSR285", "INTC_0_PSR286", "INTC_0_PSR287", "INTC_0_PSR288"} register += {"INTC_0_PSR289", "INTC_0_PSR290", "INTC_0_PSR291", "INTC_0_PSR292"} register += {"INTC_0_PSR293", "INTC_0_PSR294", "INTC_0_PSR295", "INTC_0_PSR296"} register += {"INTC_0_PSR297", "INTC_0_PSR298", "INTC_0_PSR299", "INTC_0_PSR300"} register += {"INTC_0_PSR301", "INTC_0_PSR302", "INTC_0_PSR303", "INTC_0_PSR304"} register += {"INTC_0_PSR305", "INTC_0_PSR306", "INTC_0_PSR307", "INTC_0_PSR308"} register += {"INTC_0_PSR309", "INTC_0_PSR310", "INTC_0_PSR311", "INTC_0_PSR312"} register += {"INTC_0_PSR313", "INTC_0_PSR314", "INTC_0_PSR315", "INTC_0_PSR316"} register += {"INTC_0_PSR317", "INTC_0_PSR318", "INTC_0_PSR319", "INTC_0_PSR320"} register += {"INTC_0_PSR321", "INTC_0_PSR322", "INTC_0_PSR323", "INTC_0_PSR324"} register += {"INTC_0_PSR325", "INTC_0_PSR326", "INTC_0_PSR327", "INTC_0_PSR328"} register += {"INTC_0_PSR329", "INTC_0_PSR330", "INTC_0_PSR331", "INTC_0_PSR332"} register += {"INTC_0_PSR333", "INTC_0_PSR334", "INTC_0_PSR335", "INTC_0_PSR336"} register += {"INTC_0_PSR337", "INTC_0_PSR338", "INTC_0_PSR339", "INTC_0_PSR340"} register += {"INTC_0_PSR341", "INTC_0_PSR342", "INTC_0_PSR343", "INTC_0_PSR344"} register += {"INTC_0_PSR345", "INTC_0_PSR346", "INTC_0_PSR347", "INTC_0_PSR348"} register += {"INTC_0_PSR349", "INTC_0_PSR350", "INTC_0_PSR351", "INTC_0_PSR352"} register += {"INTC_0_PSR353", "INTC_0_PSR354", "INTC_0_PSR355", "INTC_0_PSR356"} register += {"INTC_0_PSR357", "INTC_0_PSR358", "INTC_0_PSR359", "INTC_0_PSR360"} register += {"INTC_0_PSR361", "INTC_0_PSR362", "INTC_0_PSR363", "INTC_0_PSR364"} register += {"INTC_0_PSR365", "INTC_0_PSR366", "INTC_0_PSR367", "INTC_0_PSR368"} register += {"INTC_0_PSR369", "INTC_0_PSR370", "INTC_0_PSR371", "INTC_0_PSR372"} register += {"INTC_0_PSR373", "INTC_0_PSR374", "INTC_0_PSR375", "INTC_0_PSR376"} register += {"INTC_0_PSR377", "INTC_0_PSR378", "INTC_0_PSR379", "INTC_0_PSR380"} register += {"INTC_0_PSR381", "INTC_0_PSR382", "INTC_0_PSR383", "INTC_0_PSR384"} register += {"INTC_0_PSR385", "INTC_0_PSR386", "INTC_0_PSR387", "INTC_0_PSR388"} register += {"INTC_0_PSR389", "INTC_0_PSR390", "INTC_0_PSR391", "INTC_0_PSR392"} register += {"INTC_0_PSR393", "INTC_0_PSR394", "INTC_0_PSR395", "INTC_0_PSR396"} register += {"INTC_0_PSR397", "INTC_0_PSR398", "INTC_0_PSR399", "INTC_0_PSR400"} register += {"INTC_0_PSR401", "INTC_0_PSR402", "INTC_0_PSR403", "INTC_0_PSR404"} register += {"INTC_0_PSR405", "INTC_0_PSR406", "INTC_0_PSR407", "INTC_0_PSR408"} register += {"INTC_0_PSR409", "INTC_0_PSR410", "INTC_0_PSR411", "INTC_0_PSR412"} register += {"INTC_0_PSR413", "INTC_0_PSR414", "INTC_0_PSR415", "INTC_0_PSR416"} register += {"INTC_0_PSR417", "INTC_0_PSR418", "INTC_0_PSR419", "INTC_0_PSR420"} register += {"INTC_0_PSR421", "INTC_0_PSR422", "INTC_0_PSR423", "INTC_0_PSR424"} register += {"INTC_0_PSR425", "INTC_0_PSR426", "INTC_0_PSR427", "INTC_0_PSR428"} register += {"INTC_0_PSR429", "INTC_0_PSR430", "INTC_0_PSR431", "INTC_0_PSR432"} register += {"INTC_0_PSR433", "INTC_0_PSR434", "INTC_0_PSR435", "INTC_0_PSR436"} register += {"INTC_0_PSR437", "INTC_0_PSR438", "INTC_0_PSR439", "INTC_0_PSR440"} register += {"INTC_0_PSR441", "INTC_0_PSR442", "INTC_0_PSR443", "INTC_0_PSR444"} register += {"INTC_0_PSR445", "INTC_0_PSR446", "INTC_0_PSR447", "INTC_0_PSR448"} register += {"INTC_0_PSR449", "INTC_0_PSR450", "INTC_0_PSR451", "INTC_0_PSR452"} register += {"INTC_0_PSR453", "INTC_0_PSR454", "INTC_0_PSR455", "INTC_0_PSR456"} register += {"INTC_0_PSR457", "INTC_0_PSR458", "INTC_0_PSR459", "INTC_0_PSR460"} register += {"INTC_0_PSR461", "INTC_0_PSR462", "INTC_0_PSR463", "INTC_0_PSR464"} register += {"INTC_0_PSR465", "INTC_0_PSR466", "INTC_0_PSR467", "INTC_0_PSR468"} register += {"INTC_0_PSR469", "INTC_0_PSR470", "INTC_0_PSR471", "INTC_0_PSR472"} register += {"INTC_0_PSR473", "INTC_0_PSR474", "INTC_0_PSR475", "INTC_0_PSR476"} register += {"INTC_0_PSR477", "INTC_0_PSR478", "INTC_0_PSR479", "INTC_0_PSR480"} register += {"INTC_0_PSR481", "INTC_0_PSR482", "INTC_0_PSR483", "INTC_0_PSR484"} register += {"INTC_0_PSR485", "INTC_0_PSR486", "INTC_0_PSR487", "INTC_0_PSR488"} register += {"INTC_0_PSR489", "INTC_0_PSR490", "INTC_0_PSR491", "INTC_0_PSR492"} register += {"INTC_0_PSR493", "INTC_0_PSR494", "INTC_0_PSR495", "INTC_0_PSR496"} register += {"INTC_0_PSR497", "INTC_0_PSR498", "INTC_0_PSR499", "INTC_0_PSR500"} register += {"INTC_0_PSR501", "INTC_0_PSR502", "INTC_0_PSR503", "INTC_0_PSR504"} register += {"INTC_0_PSR505", "INTC_0_PSR506", "INTC_0_PSR507", "INTC_0_PSR508"} register += {"INTC_0_PSR509", "INTC_0_PSR510", "INTC_0_PSR511", "INTC_0_PSR512"} register += {"INTC_0_PSR513", "INTC_0_PSR514", "INTC_0_PSR515", "INTC_0_PSR516"} register += {"INTC_0_PSR517", "INTC_0_PSR518", "INTC_0_PSR519", "INTC_0_PSR520"} register += {"INTC_0_PSR521", "INTC_0_PSR522", "INTC_0_PSR523", "INTC_0_PSR524"} register += {"INTC_0_PSR525", "INTC_0_PSR526", "INTC_0_PSR527", "INTC_0_PSR528"} register += {"INTC_0_PSR529", "INTC_0_PSR530", "INTC_0_PSR531", "INTC_0_PSR532"} register += {"INTC_0_PSR533", "INTC_0_PSR534", "INTC_0_PSR535", "INTC_0_PSR536"} register += {"INTC_0_PSR537", "INTC_0_PSR538", "INTC_0_PSR539", "INTC_0_PSR540"} register += {"INTC_0_PSR541", "INTC_0_PSR542", "INTC_0_PSR543", "INTC_0_PSR544"} register += {"INTC_0_PSR545", "INTC_0_PSR546", "INTC_0_PSR547", "INTC_0_PSR548"} register += {"INTC_0_PSR549", "INTC_0_PSR550", "INTC_0_PSR551", "INTC_0_PSR552"} register += {"INTC_0_PSR553", "INTC_0_PSR554", "INTC_0_PSR555", "INTC_0_PSR556"} register += {"INTC_0_PSR557", "INTC_0_PSR558", "INTC_0_PSR559", "INTC_0_PSR560"} register += {"INTC_0_PSR561", "INTC_0_PSR562", "INTC_0_PSR563", "INTC_0_PSR564"} register += {"INTC_0_PSR565", "INTC_0_PSR566", "INTC_0_PSR567", "INTC_0_PSR568"} register += {"INTC_0_PSR569", "INTC_0_PSR570", "INTC_0_PSR571", "INTC_0_PSR572"} register += {"INTC_0_PSR573", "INTC_0_PSR574", "INTC_0_PSR575", "INTC_0_PSR576"} register += {"INTC_0_PSR577", "INTC_0_PSR578", "INTC_0_PSR579", "INTC_0_PSR580"} register += {"INTC_0_PSR581", "INTC_0_PSR582", "INTC_0_PSR583", "INTC_0_PSR584"} register += {"INTC_0_PSR585", "INTC_0_PSR586", "INTC_0_PSR587", "INTC_0_PSR588"} register += {"INTC_0_PSR589", "INTC_0_PSR590", "INTC_0_PSR591", "INTC_0_PSR592"} register += {"INTC_0_PSR593", "INTC_0_PSR594", "INTC_0_PSR595", "INTC_0_PSR596"} register += {"INTC_0_PSR597", "INTC_0_PSR598", "INTC_0_PSR599", "INTC_0_PSR600"} register += {"INTC_0_PSR601", "INTC_0_PSR602", "INTC_0_PSR603", "INTC_0_PSR604"} register += {"INTC_0_PSR605", "INTC_0_PSR606", "INTC_0_PSR607", "INTC_0_PSR608"} register += {"INTC_0_PSR609", "INTC_0_PSR610", "INTC_0_PSR611", "INTC_0_PSR612"} register += {"INTC_0_PSR613", "INTC_0_PSR614", "INTC_0_PSR615", "INTC_0_PSR616"} register += {"INTC_0_PSR617", "INTC_0_PSR618", "INTC_0_PSR619", "INTC_0_PSR620"} register += {"INTC_0_PSR621", "INTC_0_PSR622", "INTC_0_PSR623", "INTC_0_PSR624"} register += {"INTC_0_PSR625", "INTC_0_PSR626", "INTC_0_PSR627", "INTC_0_PSR628"} register += {"INTC_0_PSR629", "INTC_0_PSR630", "INTC_0_PSR631", "INTC_0_PSR632"} register += {"INTC_0_PSR633", "INTC_0_PSR634", "INTC_0_PSR635", "INTC_0_PSR636"} register += {"INTC_0_PSR637", "INTC_0_PSR638", "INTC_0_PSR639", "INTC_0_PSR640"} register += {"INTC_0_PSR641", "INTC_0_PSR642", "INTC_0_PSR643", "INTC_0_PSR644"} register += {"INTC_0_PSR645", "INTC_0_PSR646", "INTC_0_PSR647", "INTC_0_PSR648"} register += {"INTC_0_PSR649", "INTC_0_PSR650", "INTC_0_PSR651", "INTC_0_PSR652"} register += {"INTC_0_PSR653", "INTC_0_PSR654", "INTC_0_PSR655", "INTC_0_PSR656"} register += {"INTC_0_PSR657", "INTC_0_PSR658", "INTC_0_PSR659", "INTC_0_PSR660"} register += {"INTC_0_PSR661", "INTC_0_PSR662", "INTC_0_PSR663", "INTC_0_PSR664"} register += {"INTC_0_PSR665", "INTC_0_PSR666", "INTC_0_PSR667", "INTC_0_PSR668"} register += {"INTC_0_PSR669", "INTC_0_PSR670", "INTC_0_PSR671", "INTC_0_PSR672"} register += {"INTC_0_PSR673", "INTC_0_PSR674", "INTC_0_PSR675", "INTC_0_PSR676"} register += {"INTC_0_PSR677", "INTC_0_PSR678", "INTC_0_PSR679", "INTC_0_PSR680"} register += {"INTC_0_PSR681", "INTC_0_PSR682", "INTC_0_PSR683", "INTC_0_PSR684"} register += {"INTC_0_PSR685", "INTC_0_PSR686", "INTC_0_PSR687", "INTC_0_PSR688"} register += {"INTC_0_PSR689", "INTC_0_PSR690", "INTC_0_PSR691", "INTC_0_PSR692"} register += {"INTC_0_PSR693", "INTC_0_PSR694", "INTC_0_PSR695", "INTC_0_PSR696"} register += {"INTC_0_PSR697", "INTC_0_PSR698", "INTC_0_PSR699", "INTC_0_PSR700"} register += {"INTC_0_PSR701", "INTC_0_PSR702", "INTC_0_PSR703", "INTC_0_PSR704"} register += {"INTC_0_PSR705", "INTC_0_PSR706", "INTC_0_PSR707", "INTC_0_PSR708"} register += {"INTC_0_PSR709", "INTC_0_PSR710", "INTC_0_PSR711", "INTC_0_PSR712"} register += {"INTC_0_PSR713", "INTC_0_PSR714", "INTC_0_PSR715", "INTC_0_PSR716"} register += {"INTC_0_PSR717", "INTC_0_PSR718", "INTC_0_PSR719", "INTC_0_PSR720"} register += {"INTC_0_PSR721", "INTC_0_PSR722", "INTC_0_PSR723", "INTC_0_PSR724"} register += {"INTC_0_PSR725", "INTC_0_PSR726", "INTC_0_PSR727", "INTC_0_PSR728"} register += {"INTC_0_PSR729", "INTC_0_PSR730", "INTC_0_PSR731", "INTC_0_PSR732"} register += {"INTC_0_PSR733", "INTC_0_PSR734", "INTC_0_PSR735", "INTC_0_PSR736"} register += {"INTC_0_PSR737", "INTC_0_PSR738", "INTC_0_PSR739", "INTC_0_PSR740"} register += {"INTC_0_PSR741", "INTC_0_PSR742", "INTC_0_PSR743", "INTC_0_PSR744"} register += {"INTC_0_PSR745", "INTC_0_PSR746", "INTC_0_PSR747", "INTC_0_PSR748"} register += {"INTC_0_PSR749", "INTC_0_PSR750", "INTC_0_PSR751", "INTC_0_PSR752"} register += {"INTC_0_PSR753", "INTC_0_PSR754", "INTC_0_PSR755", "INTC_0_PSR756"} register += {"INTC_0_PSR757", "INTC_0_PSR758", "INTC_0_PSR759", "INTC_0_PSR760"} register += {"INTC_0_PSR761", "INTC_0_PSR762", "INTC_0_PSR763", "INTC_0_PSR764"} register += {"INTC_0_PSR765", "INTC_0_PSR766", "INTC_0_PSR767", "INTC_0_PSR768"} register += {"INTC_0_PSR769", "INTC_0_PSR770", "INTC_0_PSR771", "INTC_0_PSR772"} register += {"INTC_0_PSR773", "INTC_0_PSR774", "INTC_0_PSR775", "INTC_0_PSR776"} register += {"INTC_0_PSR777", "INTC_0_PSR778", "INTC_0_PSR779", "INTC_0_PSR780"} register += {"INTC_0_PSR781", "INTC_0_PSR782", "INTC_0_PSR783", "INTC_0_PSR784"} register += {"INTC_0_PSR785", "INTC_0_PSR786", "INTC_0_PSR787", "INTC_0_PSR788"} register += {"INTC_0_PSR789", "INTC_0_PSR790", "INTC_0_PSR791", "INTC_0_PSR792"} register += {"INTC_0_PSR793", "INTC_0_PSR794", "INTC_0_PSR795", "INTC_0_PSR796"} register += {"INTC_0_PSR797", "INTC_0_PSR798", "INTC_0_PSR799", "INTC_0_PSR800"} register += {"INTC_0_PSR801", "INTC_0_PSR802", "INTC_0_PSR803", "INTC_0_PSR804"} register += {"INTC_0_PSR805", "INTC_0_PSR806", "INTC_0_PSR807", "INTC_0_PSR808"} register += {"INTC_0_PSR809", "INTC_0_PSR810", "INTC_0_PSR811", "INTC_0_PSR812"} register += {"INTC_0_PSR813", "INTC_0_PSR814", "INTC_0_PSR815", "INTC_0_PSR816"} register += {"INTC_0_PSR817", "INTC_0_PSR818", "INTC_0_PSR819", "INTC_0_PSR820"} register += {"INTC_0_PSR821", "INTC_0_PSR822", "INTC_0_PSR823", "INTC_0_PSR824"} register += {"INTC_0_PSR825", "INTC_0_PSR826", "INTC_0_PSR827", "INTC_0_PSR828"} register += {"INTC_0_PSR829", "INTC_0_PSR830", "INTC_0_PSR831", "INTC_0_PSR832"} register += {"INTC_0_PSR833", "INTC_0_PSR834", "INTC_0_PSR835", "INTC_0_PSR836"} register += {"INTC_0_PSR837", "INTC_0_PSR838", "INTC_0_PSR839", "INTC_0_PSR840"} register += {"INTC_0_PSR841", "INTC_0_PSR842", "INTC_0_PSR843", "INTC_0_PSR844"} register += {"INTC_0_PSR845", "INTC_0_PSR846", "INTC_0_PSR847", "INTC_0_PSR848"} register += {"INTC_0_PSR849", "INTC_0_PSR850", "INTC_0_PSR851", "INTC_0_PSR852"} register += {"INTC_0_PSR853", "INTC_0_PSR854", "INTC_0_PSR855", "INTC_0_PSR856"} register += {"INTC_0_PSR857", "INTC_0_PSR858", "INTC_0_PSR859", "INTC_0_PSR860"} register += {"INTC_0_PSR861", "INTC_0_PSR862", "INTC_0_PSR863", "INTC_0_PSR864"} register += {"INTC_0_PSR865", "INTC_0_PSR866", "INTC_0_PSR867", "INTC_0_PSR868"} register += {"INTC_0_PSR869", "INTC_0_PSR870", "INTC_0_PSR871", "INTC_0_PSR872"} register += {"INTC_0_PSR873", "INTC_0_PSR874", "INTC_0_PSR875", "INTC_0_PSR876"} register += {"INTC_0_PSR877", "INTC_0_PSR878", "INTC_0_PSR879", "INTC_0_PSR880"} register += {"INTC_0_PSR881", "INTC_0_PSR882", "INTC_0_PSR883", "INTC_0_PSR884"} register += {"INTC_0_PSR885", "INTC_0_PSR886", "INTC_0_PSR887", "INTC_0_PSR888"} register += {"INTC_0_PSR889", "INTC_0_PSR890", "INTC_0_PSR891", "INTC_0_PSR892"} register += {"INTC_0_PSR893", "INTC_0_PSR894", "INTC_0_PSR895", "INTC_0_PSR896"} register += {"INTC_0_PSR897", "INTC_0_PSR898", "INTC_0_PSR899", "INTC_0_PSR900"} register += {"INTC_0_PSR901", "INTC_0_PSR902", "INTC_0_PSR903", "INTC_0_PSR904"} register += {"INTC_0_PSR905", "INTC_0_PSR906", "INTC_0_PSR907", "INTC_0_PSR908"} register += {"INTC_0_PSR909", "INTC_0_PSR910", "INTC_0_PSR911", "INTC_0_PSR912"} register += {"INTC_0_PSR913", "INTC_0_PSR914", "INTC_0_PSR915", "INTC_0_PSR916"} register += {"INTC_0_PSR917", "INTC_0_PSR918", "INTC_0_PSR919", "INTC_0_PSR920"} register += {"INTC_0_PSR921", "INTC_0_PSR922", "INTC_0_PSR923", "INTC_0_PSR924"} register += {"INTC_0_PSR925", "INTC_0_PSR926", "INTC_0_PSR927", "INTC_0_PSR928"} register += {"INTC_0_PSR929", "INTC_0_PSR930", "INTC_0_PSR931", "INTC_0_PSR932"} register += {"INTC_0_PSR933", "INTC_0_PSR934", "INTC_0_PSR935", "INTC_0_PSR936"} register += {"INTC_0_PSR937", "INTC_0_PSR938", "INTC_0_PSR939", "INTC_0_PSR940"} register += {"INTC_0_PSR941", "INTC_0_PSR942", "INTC_0_PSR943", "INTC_0_PSR944"} register += {"INTC_0_PSR945", "INTC_0_PSR946", "INTC_0_PSR947", "INTC_0_PSR948"} register += {"INTC_0_PSR949", "INTC_0_PSR950", "INTC_0_PSR951", "INTC_0_PSR952"} register += {"INTC_0_PSR953", "INTC_0_PSR954", "INTC_0_PSR955", "INTC_0_PSR956"} register += {"INTC_0_PSR957", "INTC_0_PSR958", "INTC_0_PSR959", "INTC_0_PSR960"} register += {"INTC_0_PSR961", "INTC_0_PSR962", "INTC_0_PSR963", "INTC_0_PSR964"} register += {"INTC_0_PSR965", "INTC_0_PSR966", "INTC_0_PSR967", "INTC_0_PSR968"} register += {"INTC_0_PSR969", "INTC_0_PSR970", "INTC_0_PSR971", "INTC_0_PSR972"} register += {"INTC_0_PSR973", "INTC_0_PSR974", "INTC_0_PSR975", "INTC_0_PSR976"} register += {"INTC_0_PSR977", "INTC_0_PSR978", "INTC_0_PSR979", "INTC_0_PSR980"} register += {"INTC_0_PSR981", "INTC_0_PSR982", "INTC_0_PSR983", "INTC_0_PSR984"} register += {"INTC_0_PSR985", "INTC_0_PSR986", "INTC_0_PSR987", "INTC_0_PSR988"} register += {"INTC_0_PSR989", "INTC_0_PSR990", "INTC_0_PSR991", "INTC_0_PSR992"} register += {"INTC_0_PSR993", "INTC_0_PSR994", "INTC_0_PSR995", "INTC_0_PSR996"} register += {"INTC_0_PSR997", "INTC_0_PSR998", "INTC_0_PSR999", "INTC_0_PSR1000"} register += {"INTC_0_PSR1001", "INTC_0_PSR1002", "INTC_0_PSR1003", "INTC_0_PSR1004"} register += {"INTC_0_PSR1005", "INTC_0_PSR1006", "INTC_0_PSR1007", "INTC_0_PSR1008"} register += {"INTC_0_PSR1009", "INTC_0_PSR1010", "INTC_0_PSR1011", "INTC_0_PSR1012"} register += {"INTC_0_PSR1013", "INTC_0_PSR1014", "INTC_0_PSR1015", "INTC_0_PSR1016"} register += {"INTC_0_PSR1017", "INTC_0_PSR1018", "INTC_0_PSR1019", "INTC_0_PSR1020"} register += {"INTC_0_PSR1021", "INTC_0_PSR1022", "INTC_0_PSR1023"} } IRCOSC { sn = "IRCOSC" ln = "IRCOSC" hk = "IRCOSC" collapse = true register += {"IRCOSC_CTL", "IRCOSC_NT", "IRCOSC_TT"} } LFAST_0 { sn = "LFAST_0" ln = "LFAST_0" hk = "LFAST_0" collapse = true register += {"LFAST_0_MCR", "LFAST_0_SCR", "LFAST_0_COCR", "LFAST_0_TMCR", "LFAST_0_ALCR"} register += {"LFAST_0_RCDCR", "LFAST_0_SLCR", "LFAST_0_ICR", "LFAST_0_PICR", "LFAST_0_RFCR"} register += {"LFAST_0_TIER", "LFAST_0_RIER", "LFAST_0_RIIER", "LFAST_0_LCR"} register += {"LFAST_0_UNSTCR", "LFAST_0_UNSTDR8", "LFAST_0_UNSTDR7", "LFAST_0_UNSTDR6"} register += {"LFAST_0_UNSTDR5", "LFAST_0_UNSTDR4", "LFAST_0_UNSTDR3", "LFAST_0_UNSTDR2"} register += {"LFAST_0_UNSTDR1", "LFAST_0_UNSTDR0", "LFAST_0_GSR", "LFAST_0_PISR"} register += {"LFAST_0_DFSR", "LFAST_0_TISR", "LFAST_0_RISR", "LFAST_0_RIISR"} register += {"LFAST_0_PLLLSR", "LFAST_0_UNSRSR", "LFAST_0_UNSRDR8", "LFAST_0_UNSRDR7"} register += {"LFAST_0_UNSRDR6", "LFAST_0_UNSRDR5", "LFAST_0_UNSRDR4", "LFAST_0_UNSRDR3"} register += {"LFAST_0_UNSRDR2", "LFAST_0_UNSRDR1", "LFAST_0_UNSRDR0"} } LINFlexD_0 { sn = "LINFlexD_0" ln = "LINFlexD_0" hk = "LINFlexD_0" collapse = true register += {"LINFlexD_0_LINCR1", "LINFlexD_0_LINIER", "LINFlexD_0_LINSR"} register += {"LINFlexD_0_LINESR", "LINFlexD_0_UARTCR", "LINFlexD_0_UARTSR"} register += {"LINFlexD_0_LINTCSR", "LINFlexD_0_LINOCR", "LINFlexD_0_LINTOCR"} register += {"LINFlexD_0_LINFBRR", "LINFlexD_0_LINIBRR", "LINFlexD_0_LINCFR"} register += {"LINFlexD_0_LINCR2", "LINFlexD_0_BIDR", "LINFlexD_0_BDRL", "LINFlexD_0_BDRM"} register += {"LINFlexD_0_IFER", "LINFlexD_0_IFMI", "LINFlexD_0_IFMR", "LINFlexD_0_IFCR0"} register += {"LINFlexD_0_IFCR1", "LINFlexD_0_IFCR2", "LINFlexD_0_IFCR3", "LINFlexD_0_IFCR4"} register += {"LINFlexD_0_IFCR5", "LINFlexD_0_IFCR6", "LINFlexD_0_IFCR7", "LINFlexD_0_IFCR8"} register += {"LINFlexD_0_IFCR9", "LINFlexD_0_IFCR10", "LINFlexD_0_IFCR11"} register += {"LINFlexD_0_IFCR12", "LINFlexD_0_IFCR13", "LINFlexD_0_IFCR14"} register += {"LINFlexD_0_IFCR15", "LINFlexD_0_GCR", "LINFlexD_0_UARTPTO"} register += {"LINFlexD_0_UARTCTO", "LINFlexD_0_DMATXE", "LINFlexD_0_DMARXE"} } LINFlexD_1 { sn = "LINFlexD_1" ln = "LINFlexD_1" hk = "LINFlexD_1" collapse = true register += {"LINFlexD_1_LINCR1", "LINFlexD_1_LINIER", "LINFlexD_1_LINSR"} register += {"LINFlexD_1_LINESR", "LINFlexD_1_UARTCR", "LINFlexD_1_UARTSR"} register += {"LINFlexD_1_LINTCSR", "LINFlexD_1_LINOCR", "LINFlexD_1_LINTOCR"} register += {"LINFlexD_1_LINFBRR", "LINFlexD_1_LINIBRR", "LINFlexD_1_LINCFR"} register += {"LINFlexD_1_LINCR2", "LINFlexD_1_BIDR", "LINFlexD_1_BDRL", "LINFlexD_1_BDRM"} register += {"LINFlexD_1_IFER", "LINFlexD_1_IFMI", "LINFlexD_1_IFMR", "LINFlexD_1_GCR"} register += {"LINFlexD_1_UARTPTO", "LINFlexD_1_UARTCTO", "LINFlexD_1_DMATXE"} register += {"LINFlexD_1_DMARXE"} } LINFlexD_14 { sn = "LINFlexD_14" ln = "LINFlexD_14" hk = "LINFlexD_14" collapse = true register += {"LINFlexD_14_LINCR1", "LINFlexD_14_LINIER", "LINFlexD_14_LINSR"} register += {"LINFlexD_14_LINESR", "LINFlexD_14_UARTCR", "LINFlexD_14_UARTSR"} register += {"LINFlexD_14_LINTCSR", "LINFlexD_14_LINOCR", "LINFlexD_14_LINTOCR"} register += {"LINFlexD_14_LINFBRR", "LINFlexD_14_LINIBRR", "LINFlexD_14_LINCFR"} register += {"LINFlexD_14_LINCR2", "LINFlexD_14_BIDR", "LINFlexD_14_BDRL"} register += {"LINFlexD_14_BDRM", "LINFlexD_14_IFER", "LINFlexD_14_IFMI", "LINFlexD_14_IFMR"} register += {"LINFlexD_14_GCR", "LINFlexD_14_UARTPTO", "LINFlexD_14_UARTCTO"} register += {"LINFlexD_14_DMATXE", "LINFlexD_14_DMARXE"} } MC_CGM { sn = "MC_CGM" ln = "MC_CGM" hk = "MC_CGM" collapse = true register += {"MC_CGM_PCS_SDUR", "MC_CGM_PCS_DIVC1", "MC_CGM_PCS_DIVS1", "MC_CGM_PCS_DIVE1"} register += {"MC_CGM_PCS_DIVC2", "MC_CGM_PCS_DIVS2", "MC_CGM_PCS_DIVE2", "MC_CGM_PCS_DIVC3"} register += {"MC_CGM_PCS_DIVS3", "MC_CGM_PCS_DIVE3", "MC_CGM_SC_SS", "MC_CGM_SC_DC0"} register += {"MC_CGM_SC_DC1", "MC_CGM_AC0_SC", "MC_CGM_AC0_SS", "MC_CGM_AC0_DC0"} register += {"MC_CGM_AC0_DC1", "MC_CGM_AC0_DC2", "MC_CGM_AC1_SC", "MC_CGM_AC1_SS"} register += {"MC_CGM_AC1_DC0", "MC_CGM_AC2_DC0", "MC_CGM_AC3_SC", "MC_CGM_AC3_SS"} register += {"MC_CGM_AC7_SC", "MC_CGM_AC7_SS", "MC_CGM_AC7_DC0", "MC_CGM_AC8_SC"} register += {"MC_CGM_AC8_SS", "MC_CGM_AC8_DC0", "MC_CGM_AC10_SC", "MC_CGM_AC10_SS"} register += {"MC_CGM_AC10_DC0", "MC_CGM_AC11_SC", "MC_CGM_AC11_SS", "MC_CGM_AC11_DC0"} register += {"MC_CGM_AC11_DC1"} } MC_ME { sn = "MC_ME" ln = "MC_ME" hk = "MC_ME" collapse = true register += {"MC_ME_GS", "MC_ME_MCTL", "MC_ME_ME", "MC_ME_IS", "MC_ME_IM", "MC_ME_IMTS"} register += {"MC_ME_DMTS", "MC_ME_RESET_MC", "MC_ME_TEST_MC", "MC_ME_SAFE_MC"} register += {"MC_ME_DRUN_MC", "MC_ME_RUN0_MC", "MC_ME_RUN1_MC", "MC_ME_RUN2_MC"} register += {"MC_ME_RUN3_MC", "MC_ME_HALT0_MC", "MC_ME_STOP0_MC", "MC_ME_PS0", "MC_ME_PS1"} register += {"MC_ME_PS2", "MC_ME_PS3", "MC_ME_PS4", "MC_ME_RUN_PC0", "MC_ME_RUN_PC1"} register += {"MC_ME_RUN_PC2", "MC_ME_RUN_PC3", "MC_ME_RUN_PC4", "MC_ME_RUN_PC5"} register += {"MC_ME_RUN_PC6", "MC_ME_RUN_PC7", "MC_ME_LP_PC0", "MC_ME_LP_PC1"} register += {"MC_ME_LP_PC2", "MC_ME_LP_PC3", "MC_ME_LP_PC4", "MC_ME_LP_PC5", "MC_ME_LP_PC6"} register += {"MC_ME_LP_PC7", "MC_ME_PCTL9", "MC_ME_PCTL11", "MC_ME_PCTL29", "MC_ME_PCTL30"} register += {"MC_ME_PCTL31", "MC_ME_PCTL36", "MC_ME_PCTL59", "MC_ME_PCTL69", "MC_ME_PCTL70"} register += {"MC_ME_PCTL73", "MC_ME_PCTL74", "MC_ME_PCTL85", "MC_ME_PCTL91", "MC_ME_PCTL92"} register += {"MC_ME_PCTL97", "MC_ME_PCTL99", "MC_ME_PCTL104", "MC_ME_PCTL112"} register += {"MC_ME_PCTL123", "MC_ME_PCTL127", "MC_ME_PCTL128", "MC_ME_CS", "MC_ME_CCTL0"} register += {"MC_ME_CADDR0"} } MC_PCU { sn = "MC_PCU" ln = "MC_PCU" hk = "MC_PCU" collapse = true register += {"MC_PCU_PSTAT"} } MC_RGM { sn = "MC_RGM" ln = "MC_RGM" hk = "MC_RGM" collapse = true register += {"MC_RGM_DES", "MC_RGM_DERD", "MC_RGM_DEAR", "MC_RGM_DBRE", "MC_RGM_FES"} register += {"MC_RGM_FERD", "MC_RGM_FEAR", "MC_RGM_FBRE", "MC_RGM_FESS", "MC_RGM_FRET"} register += {"MC_RGM_DRET", "MC_RGM_EROEC", "MC_RGM_PRST0", "MC_RGM_PRST1", "MC_RGM_PRST2"} register += {"MC_RGM_PRST3", "MC_RGM_PRST4"} } MP55 { sn = "MP55" ln = "MP55" hk = "MP55" collapse = true register += {"MP55_MCR", "MP55_MCRE", "MP55_LOCK0", "MP55_LOCK1", "MP55_LOCK2", "MP55_SEL0"} register += {"MP55_SEL1", "MP55_SEL2", "MP55_ADR", "MP55_UT0", "MP55_UMISR0", "MP55_UMISR1"} register += {"MP55_UMISR2", "MP55_UMISR3", "MP55_UMISR8", "MP55_UMISR9", "MP55_OPP0"} register += {"MP55_OPP1", "MP55_OPP2", "MP55_TDMPC"} } M_CAN_1 { sn = "M_CAN_1" ln = "M_CAN_1" hk = "M_CAN_1" collapse = true register += {"M_CAN_1_CREL", "M_CAN_1_ENDN", "M_CAN_1_FBTP", "M_CAN_1_TEST", "M_CAN_1_RWD"} register += {"M_CAN_1_CCCR", "M_CAN_1_BTP", "M_CAN_1_TSCC", "M_CAN_1_TSCV", "M_CAN_1_TOCC"} register += {"M_CAN_1_TOCV", "M_CAN_1_ECR", "M_CAN_1_PSR", "M_CAN_1_IR", "M_CAN_1_IE"} register += {"M_CAN_1_ILS", "M_CAN_1_ILE", "M_CAN_1_GFC", "M_CAN_1_SIDFC", "M_CAN_1_XIDFC"} register += {"M_CAN_1_XIDAM", "M_CAN_1_HPMS", "M_CAN_1_NDAT1", "M_CAN_1_NDAT2"} register += {"M_CAN_1_RXF0C", "M_CAN_1_RXF0S", "M_CAN_1_RXF0A", "M_CAN_1_RXBC"} register += {"M_CAN_1_RXF1C", "M_CAN_1_RXF1S", "M_CAN_1_RXF1A", "M_CAN_1_TXBC"} register += {"M_CAN_1_TXFQS", "M_CAN_1_TXBRP", "M_CAN_1_TXBAR", "M_CAN_1_TXBCR"} register += {"M_CAN_1_TXBTO", "M_CAN_1_TXBCF", "M_CAN_1_TXBTIE", "M_CAN_1_TXBCIE"} register += {"M_CAN_1_TXEFC", "M_CAN_1_TXEFS", "M_CAN_1_TXEFA"} } M_CAN_2 { sn = "M_CAN_2" ln = "M_CAN_2" hk = "M_CAN_2" collapse = true register += {"M_CAN_2_CREL", "M_CAN_2_ENDN", "M_CAN_2_FBTP", "M_CAN_2_TEST", "M_CAN_2_RWD"} register += {"M_CAN_2_CCCR", "M_CAN_2_BTP", "M_CAN_2_TSCC", "M_CAN_2_TSCV", "M_CAN_2_TOCC"} register += {"M_CAN_2_TOCV", "M_CAN_2_ECR", "M_CAN_2_PSR", "M_CAN_2_IR", "M_CAN_2_IE"} register += {"M_CAN_2_ILS", "M_CAN_2_ILE", "M_CAN_2_GFC", "M_CAN_2_SIDFC", "M_CAN_2_XIDFC"} register += {"M_CAN_2_XIDAM", "M_CAN_2_HPMS", "M_CAN_2_NDAT1", "M_CAN_2_NDAT2"} register += {"M_CAN_2_RXF0C", "M_CAN_2_RXF0S", "M_CAN_2_RXF0A", "M_CAN_2_RXBC"} register += {"M_CAN_2_RXF1C", "M_CAN_2_RXF1S", "M_CAN_2_RXF1A", "M_CAN_2_TXBC"} register += {"M_CAN_2_TXFQS", "M_CAN_2_TXBRP", "M_CAN_2_TXBAR", "M_CAN_2_TXBCR"} register += {"M_CAN_2_TXBTO", "M_CAN_2_TXBCF", "M_CAN_2_TXBTIE", "M_CAN_2_TXBCIE"} register += {"M_CAN_2_TXEFC", "M_CAN_2_TXEFS", "M_CAN_2_TXEFA"} } PASS { sn = "PASS" ln = "PASS" hk = "PASS" collapse = true register += {"PASS_LCSTAT", "PASS_CHSEL", "PASS_CSTAT", "PASS_CIN0", "PASS_CIN1"} register += {"PASS_CIN2", "PASS_CIN3", "PASS_CIN4", "PASS_CIN5", "PASS_CIN6", "PASS_CIN7"} register += {"PASS_LOCK0_PG0", "PASS_LOCK1_PG0", "PASS_LOCK2_PG0", "PASS_LOCK3_PG0"} register += {"PASS_LOCK0_PG1", "PASS_LOCK1_PG1", "PASS_LOCK2_PG1", "PASS_LOCK3_PG1"} register += {"PASS_LOCK0_PG2", "PASS_LOCK1_PG2", "PASS_LOCK2_PG2", "PASS_LOCK3_PG2"} register += {"PASS_LOCK0_PG3", "PASS_LOCK1_PG3", "PASS_LOCK2_PG3", "PASS_LOCK3_PG3"} } PBRIDGE_A { sn = "PBRIDGE_A" ln = "PBRIDGE_A" hk = "PBRIDGE_A" collapse = true register += {"PBRIDGE_A_MPRA", "PBRIDGE_A_PACRA", "PBRIDGE_A_PACRB", "PBRIDGE_A_PACRC"} register += {"PBRIDGE_A_PACRD", "PBRIDGE_A_PACRF", "PBRIDGE_A_PACRG", "PBRIDGE_A_PACRH"} register += {"PBRIDGE_A_OPACRA", "PBRIDGE_A_OPACRB", "PBRIDGE_A_OPACRC", "PBRIDGE_A_OPACRD"} register += {"PBRIDGE_A_OPACRE", "PBRIDGE_A_OPACRF", "PBRIDGE_A_OPACRG", "PBRIDGE_A_OPACRH"} register += {"PBRIDGE_A_OPACRI", "PBRIDGE_A_OPACRJ", "PBRIDGE_A_OPACRK", "PBRIDGE_A_OPACRL"} register += {"PBRIDGE_A_OPACRM", "PBRIDGE_A_OPACRN", "PBRIDGE_A_OPACRO", "PBRIDGE_A_OPACRP"} register += {"PBRIDGE_A_OPACRQ", "PBRIDGE_A_OPACRR", "PBRIDGE_A_OPACRS", "PBRIDGE_A_OPACRT"} register += {"PBRIDGE_A_OPACRU", "PBRIDGE_A_OPACRV", "PBRIDGE_A_OPACRW", "PBRIDGE_A_OPACRX"} register += {"PBRIDGE_A_OPACRY", "PBRIDGE_A_OPACRZ", "PBRIDGE_A_OPACRAA"} register += {"PBRIDGE_A_OPACRAB", "PBRIDGE_A_OPACRAC", "PBRIDGE_A_OPACRAD"} register += {"PBRIDGE_A_OPACRAE", "PBRIDGE_A_OPACRAF"} } PFLASH { sn = "PFLASH" ln = "PFLASH" hk = "PFLASH" collapse = true register += {"PFLASH_PFCR1", "PFLASH_PFCR3", "PFLASH_PFAPR", "PFLASH_PFCRCR"} register += {"PFLASH_PFCRDE", "PFLASH_PFCRD0_W0", "PFLASH_PFCRD0_W1", "PFLASH_PFCRD0_W2"} register += {"PFLASH_PFCRD1_W0", "PFLASH_PFCRD1_W1", "PFLASH_PFCRD1_W2", "PFLASH_PFCRD2_W0"} register += {"PFLASH_PFCRD2_W1", "PFLASH_PFCRD2_W2", "PFLASH_PFCRD3_W0", "PFLASH_PFCRD3_W1"} register += {"PFLASH_PFCRD3_W2", "PFLASH_PFCRD4_W0", "PFLASH_PFCRD4_W1", "PFLASH_PFCRD4_W2"} register += {"PFLASH_PFCRD5_W0", "PFLASH_PFCRD5_W1", "PFLASH_PFCRD5_W2", "PFLASH_PFCRD6_W0"} register += {"PFLASH_PFCRD6_W1", "PFLASH_PFCRD6_W2", "PFLASH_PFCRD7_W0", "PFLASH_PFCRD7_W1"} register += {"PFLASH_PFCRD7_W2", "PFLASH_PFCRD8_W0", "PFLASH_PFCRD8_W1", "PFLASH_PFCRD8_W2"} register += {"PFLASH_PFCRD9_W0", "PFLASH_PFCRD9_W1", "PFLASH_PFCRD9_W2", "PFLASH_PFCRD10_W0"} register += {"PFLASH_PFCRD10_W1", "PFLASH_PFCRD10_W2", "PFLASH_PFCRD11_W0"} register += {"PFLASH_PFCRD11_W1", "PFLASH_PFCRD11_W2", "PFLASH_PFCRD12_W0"} register += {"PFLASH_PFCRD12_W1", "PFLASH_PFCRD12_W2", "PFLASH_PFCRD13_W0"} register += {"PFLASH_PFCRD13_W1", "PFLASH_PFCRD13_W2", "PFLASH_PFCRD14_W0"} register += {"PFLASH_PFCRD14_W1", "PFLASH_PFCRD14_W2", "PFLASH_PFCRD15_W0"} register += {"PFLASH_PFCRD15_W1", "PFLASH_PFCRD15_W2", "PFLASH_PFCRD16_W0"} register += {"PFLASH_PFCRD16_W1", "PFLASH_PFCRD16_W2", "PFLASH_PFCRD17_W0"} register += {"PFLASH_PFCRD17_W1", "PFLASH_PFCRD17_W2", "PFLASH_PFCRD18_W0"} register += {"PFLASH_PFCRD18_W1", "PFLASH_PFCRD18_W2", "PFLASH_PFCRD19_W0"} register += {"PFLASH_PFCRD19_W1", "PFLASH_PFCRD19_W2", "PFLASH_PFCRD20_W0"} register += {"PFLASH_PFCRD20_W1", "PFLASH_PFCRD20_W2", "PFLASH_PFCRD21_W0"} register += {"PFLASH_PFCRD21_W1", "PFLASH_PFCRD21_W2", "PFLASH_PFCRD22_W0"} register += {"PFLASH_PFCRD22_W1", "PFLASH_PFCRD22_W2", "PFLASH_PFCRD23_W0"} register += {"PFLASH_PFCRD23_W1", "PFLASH_PFCRD23_W2", "PFLASH_PFCRD24_W0"} register += {"PFLASH_PFCRD24_W1", "PFLASH_PFCRD24_W2", "PFLASH_PFCRD25_W0"} register += {"PFLASH_PFCRD25_W1", "PFLASH_PFCRD25_W2", "PFLASH_PFCRD26_W0"} register += {"PFLASH_PFCRD26_W1", "PFLASH_PFCRD26_W2", "PFLASH_PFCRD27_W0"} register += {"PFLASH_PFCRD27_W1", "PFLASH_PFCRD27_W2", "PFLASH_PFCRD28_W0"} register += {"PFLASH_PFCRD28_W1", "PFLASH_PFCRD28_W2", "PFLASH_PFCRD29_W0"} register += {"PFLASH_PFCRD29_W1", "PFLASH_PFCRD29_W2", "PFLASH_PFCRD30_W0"} register += {"PFLASH_PFCRD30_W1", "PFLASH_PFCRD30_W2", "PFLASH_PFCRD31_W0"} register += {"PFLASH_PFCRD31_W1", "PFLASH_PFCRD31_W2"} } PIT_0 { sn = "PIT_0" ln = "PIT_0" hk = "PIT_0" collapse = true register += {"PIT_0_MCR", "PIT_0_LTMR64H", "PIT_0_LTMR64L", "PIT_0_LDVAL0", "PIT_0_CVAL0"} register += {"PIT_0_TCTRL0", "PIT_0_TFLG0", "PIT_0_LDVAL1", "PIT_0_CVAL1", "PIT_0_TCTRL1"} register += {"PIT_0_TFLG1", "PIT_0_LDVAL2", "PIT_0_CVAL2", "PIT_0_TCTRL2", "PIT_0_TFLG2"} register += {"PIT_0_LDVAL3", "PIT_0_CVAL3", "PIT_0_TCTRL3", "PIT_0_TFLG3", "PIT_0_LDVAL4"} register += {"PIT_0_CVAL4", "PIT_0_TCTRL4", "PIT_0_TFLG4", "PIT_0_LDVAL5", "PIT_0_CVAL5"} register += {"PIT_0_TCTRL5", "PIT_0_TFLG5", "PIT_0_LDVAL6", "PIT_0_CVAL6", "PIT_0_TCTRL6"} register += {"PIT_0_TFLG6", "PIT_0_LDVAL7", "PIT_0_CVAL7", "PIT_0_TCTRL7", "PIT_0_TFLG7"} } PIT_1 { sn = "PIT_1" ln = "PIT_1" hk = "PIT_1" collapse = true register += {"PIT_1_MCR", "PIT_1_LTMR64H", "PIT_1_LTMR64L", "PIT_1_LDVAL0", "PIT_1_CVAL0"} register += {"PIT_1_TCTRL0", "PIT_1_TFLG0", "PIT_1_LDVAL1", "PIT_1_CVAL1", "PIT_1_TCTRL1"} register += {"PIT_1_TFLG1", "PIT_1_LDVAL2", "PIT_1_CVAL2", "PIT_1_TCTRL2", "PIT_1_TFLG2"} register += {"PIT_1_LDVAL3", "PIT_1_CVAL3", "PIT_1_TCTRL3", "PIT_1_TFLG3", "PIT_1_LDVAL4"} register += {"PIT_1_CVAL4", "PIT_1_TCTRL4", "PIT_1_TFLG4", "PIT_1_LDVAL5", "PIT_1_CVAL5"} register += {"PIT_1_TCTRL5", "PIT_1_TFLG5", "PIT_1_LDVAL6", "PIT_1_CVAL6", "PIT_1_TCTRL6"} register += {"PIT_1_TFLG6", "PIT_1_LDVAL7", "PIT_1_CVAL7", "PIT_1_TCTRL7", "PIT_1_TFLG7"} } PLLDIG { sn = "PLLDIG" ln = "PLLDIG" hk = "PLLDIG" collapse = true register += {"PLLDIG_PLLCR", "PLLDIG_PLLSR", "PLLDIG_PLLDV"} } PMCDIG { sn = "PMCDIG" ln = "PMCDIG" hk = "PMCDIG" collapse = true register += {"PMCDIG_GR_S", "PMCDIG_GR_P", "PMCDIG_IE_P", "PMCDIG_EPR_VD3", "PMCDIG_REE_VD3"} register += {"PMCDIG_RES_VD3", "PMCDIG_EPR_VD9", "PMCDIG_EPR_VD10", "PMCDIG_REE_VD10"} register += {"PMCDIG_RES_VD10", "PMCDIG_EPR_VD14", "PMCDIG_REE_VD14", "PMCDIG_RES_VD14"} register += {"PMCDIG_VSIO", "PMCDIG_MREG_CTRL", "PMCDIG_EPR_TD", "PMCDIG_REE_TD"} register += {"PMCDIG_RES_TD", "PMCDIG_CTL_TD"} } PRAMC { sn = "PRAMC" ln = "PRAMC" hk = "PRAMC" collapse = true register += {"PRAMC_PRCR1"} } SARADC_0 { sn = "SARADC_0" ln = "SARADC_0" hk = "SARADC_0" collapse = true register += {"SARADC_0_MCR", "SARADC_0_MSR", "SARADC_0_ISR", "SARADC_0_ICIPR0"} register += {"SARADC_0_ICIPR1", "SARADC_0_ICIPR2", "SARADC_0_IMR", "SARADC_0_ICIMR0"} register += {"SARADC_0_ICIMR1", "SARADC_0_ICIMR2", "SARADC_0_WTISR", "SARADC_0_WTIMR"} register += {"SARADC_0_DMAE", "SARADC_0_ICDSR0", "SARADC_0_ICDSR1", "SARADC_0_ICDSR2"} register += {"SARADC_0_WTHRHLR0", "SARADC_0_WTHRHLR1", "SARADC_0_WTHRHLR2"} register += {"SARADC_0_WTHRHLR3", "SARADC_0_CTR0", "SARADC_0_CTR1", "SARADC_0_CTR2"} register += {"SARADC_0_CTR3", "SARADC_0_ICNCMR0", "SARADC_0_ICNCMR1", "SARADC_0_ICNCMR2"} register += {"SARADC_0_ICJCMR0", "SARADC_0_ICJCMR1", "SARADC_0_ICJCMR2", "SARADC_0_PDEDR"} register += {"SARADC_0_ICDR0", "SARADC_0_ICDR1", "SARADC_0_ICDR2", "SARADC_0_ICDR3"} register += {"SARADC_0_ICDR4", "SARADC_0_ICDR5", "SARADC_0_ICDR6", "SARADC_0_ICDR7"} register += {"SARADC_0_ICDR8", "SARADC_0_ICDR9", "SARADC_0_ICDR10", "SARADC_0_ICDR11"} register += {"SARADC_0_ICDR12", "SARADC_0_ICDR13", "SARADC_0_ICDR14", "SARADC_0_ICDR15"} register += {"SARADC_0_ICDR16", "SARADC_0_ICDR17", "SARADC_0_ICDR18", "SARADC_0_ICDR19"} register += {"SARADC_0_ICDR20", "SARADC_0_ICDR21", "SARADC_0_ICDR22", "SARADC_0_ICDR23"} register += {"SARADC_0_ICDR24", "SARADC_0_ICDR25", "SARADC_0_ICDR26", "SARADC_0_ICDR27"} register += {"SARADC_0_ICDR28", "SARADC_0_ICDR29", "SARADC_0_ICDR30", "SARADC_0_ICDR31"} register += {"SARADC_0_ICDR32", "SARADC_0_ICDR33", "SARADC_0_ICDR34", "SARADC_0_ICDR35"} register += {"SARADC_0_ICDR36", "SARADC_0_ICDR37", "SARADC_0_ICDR38", "SARADC_0_ICDR39"} register += {"SARADC_0_ICDR40", "SARADC_0_ICDR41", "SARADC_0_ICDR42", "SARADC_0_ICDR43"} register += {"SARADC_0_ICDR44", "SARADC_0_ICDR45", "SARADC_0_ICDR46", "SARADC_0_ICDR47"} register += {"SARADC_0_ICDR48", "SARADC_0_ICDR49", "SARADC_0_ICDR50", "SARADC_0_ICDR51"} register += {"SARADC_0_ICDR52", "SARADC_0_ICDR53", "SARADC_0_ICDR54", "SARADC_0_ICDR55"} register += {"SARADC_0_ICDR56", "SARADC_0_ICDR57", "SARADC_0_ICDR58", "SARADC_0_ICDR59"} register += {"SARADC_0_ICDR60", "SARADC_0_ICDR61", "SARADC_0_ICDR62", "SARADC_0_ICDR63"} register += {"SARADC_0_ICDR64", "SARADC_0_ICDR65", "SARADC_0_ICDR66", "SARADC_0_ICDR67"} register += {"SARADC_0_ICDR68", "SARADC_0_ICDR69", "SARADC_0_ICDR70", "SARADC_0_ICDR71"} register += {"SARADC_0_ICDR72", "SARADC_0_ICDR73", "SARADC_0_ICDR74", "SARADC_0_ICDR75"} register += {"SARADC_0_ICDR76", "SARADC_0_ICDR77", "SARADC_0_ICDR78", "SARADC_0_ICDR79"} register += {"SARADC_0_ICDR80", "SARADC_0_ICDR81", "SARADC_0_ICDR82", "SARADC_0_ICDR83"} register += {"SARADC_0_ICDR84", "SARADC_0_ICDR85", "SARADC_0_ICDR86", "SARADC_0_ICDR87"} register += {"SARADC_0_ICDR88", "SARADC_0_ICDR89", "SARADC_0_ICDR90", "SARADC_0_ICDR91"} register += {"SARADC_0_ICDR92", "SARADC_0_ICDR93", "SARADC_0_ICDR94", "SARADC_0_ICDR95"} register += {"SARADC_0_ICWSELR0", "SARADC_0_ICWSELR1", "SARADC_0_ICWSELR2"} register += {"SARADC_0_ICWSELR3", "SARADC_0_ICWSELR4", "SARADC_0_ICWSELR5"} register += {"SARADC_0_ICWSELR6", "SARADC_0_ICWSELR7", "SARADC_0_ICWSELR8"} register += {"SARADC_0_ICWSELR9", "SARADC_0_ICWSELR10", "SARADC_0_ICWSELR11"} register += {"SARADC_0_ICWENR0", "SARADC_0_ICWENR1", "SARADC_0_ICWENR2", "SARADC_0_ICAWORR0"} register += {"SARADC_0_ICAWORR1", "SARADC_0_ICAWORR2", "SARADC_0_TCIPR", "SARADC_0_TCIMR"} register += {"SARADC_0_TCDSR", "SARADC_0_TCNCMR", "SARADC_0_TCJCMR", "SARADC_0_TCWSELR0"} register += {"SARADC_0_TCWSELR1", "SARADC_0_TCWSELR2", "SARADC_0_TCWSELR3"} register += {"SARADC_0_TCWENR", "SARADC_0_TCAWORR", "SARADC_0_TCCAPR0", "SARADC_0_TCCAPR1"} register += {"SARADC_0_TCCAPR2", "SARADC_0_TCCAPR3", "SARADC_0_TCCAPR4", "SARADC_0_TCCAPR5"} register += {"SARADC_0_TCCAPR6", "SARADC_0_TCCAPR7", "SARADC_0_TCDR96", "SARADC_0_TCDR97"} register += {"SARADC_0_TCDR98", "SARADC_0_TCDR99", "SARADC_0_TCDR100", "SARADC_0_TCDR101"} register += {"SARADC_0_TCDR102", "SARADC_0_TCDR103", "SARADC_0_TCDR104", "SARADC_0_TCDR105"} register += {"SARADC_0_TCDR106", "SARADC_0_TCDR107", "SARADC_0_TCDR108", "SARADC_0_TCDR109"} register += {"SARADC_0_TCDR110", "SARADC_0_TCDR111", "SARADC_0_TCDR112", "SARADC_0_TCDR113"} register += {"SARADC_0_TCDR114", "SARADC_0_TCDR115", "SARADC_0_TCDR116", "SARADC_0_TCDR117"} register += {"SARADC_0_TCDR118", "SARADC_0_TCDR119", "SARADC_0_TCDR120", "SARADC_0_TCDR121"} register += {"SARADC_0_TCDR122", "SARADC_0_TCDR123", "SARADC_0_TCDR124", "SARADC_0_TCDR125"} register += {"SARADC_0_TCDR126", "SARADC_0_TCDR127", "SARADC_0_ECDSDR", "SARADC_0_ECIPR0"} register += {"SARADC_0_ECIPR1", "SARADC_0_ECIPR2", "SARADC_0_ECIPR3", "SARADC_0_ECIMR0"} register += {"SARADC_0_ECIMR1", "SARADC_0_ECIMR2", "SARADC_0_ECIMR3", "SARADC_0_ECDSR0"} register += {"SARADC_0_ECDSR1", "SARADC_0_ECDSR2", "SARADC_0_ECDSR3", "SARADC_0_ECNCMR0"} register += {"SARADC_0_ECNCMR1", "SARADC_0_ECNCMR2", "SARADC_0_ECNCMR3", "SARADC_0_ECJCMR0"} register += {"SARADC_0_ECJCMR1", "SARADC_0_ECJCMR2", "SARADC_0_ECJCMR3", "SARADC_0_ECWSELR0"} register += {"SARADC_0_ECWSELR1", "SARADC_0_ECWSELR2", "SARADC_0_ECWSELR3"} register += {"SARADC_0_ECWSELR4", "SARADC_0_ECWSELR5", "SARADC_0_ECWSELR6"} register += {"SARADC_0_ECWSELR7", "SARADC_0_ECWSELR8", "SARADC_0_ECWSELR9"} register += {"SARADC_0_ECWSELR10", "SARADC_0_ECWSELR11", "SARADC_0_ECWSELR12"} register += {"SARADC_0_ECWSELR13", "SARADC_0_ECWSELR14", "SARADC_0_ECWSELR15"} register += {"SARADC_0_ECWENR0", "SARADC_0_ECWENR1", "SARADC_0_ECWENR2", "SARADC_0_ECWENR3"} register += {"SARADC_0_ECAWORR0", "SARADC_0_ECAWORR1", "SARADC_0_ECAWORR2"} register += {"SARADC_0_ECAWORR3", "SARADC_0_ECMICR0", "SARADC_0_ECMICR1", "SARADC_0_ECMICR2"} register += {"SARADC_0_ECMICR3", "SARADC_0_ECDR128", "SARADC_0_ECDR129", "SARADC_0_ECDR130"} register += {"SARADC_0_ECDR131", "SARADC_0_ECDR132", "SARADC_0_ECDR133", "SARADC_0_ECDR134"} register += {"SARADC_0_ECDR135", "SARADC_0_ECDR136", "SARADC_0_ECDR137", "SARADC_0_ECDR138"} register += {"SARADC_0_ECDR139", "SARADC_0_ECDR140", "SARADC_0_ECDR141", "SARADC_0_ECDR142"} register += {"SARADC_0_ECDR143", "SARADC_0_ECDR144", "SARADC_0_ECDR145", "SARADC_0_ECDR146"} register += {"SARADC_0_ECDR147", "SARADC_0_ECDR148", "SARADC_0_ECDR149", "SARADC_0_ECDR150"} register += {"SARADC_0_ECDR151", "SARADC_0_ECDR152", "SARADC_0_ECDR153", "SARADC_0_ECDR154"} register += {"SARADC_0_ECDR155", "SARADC_0_ECDR156", "SARADC_0_ECDR157", "SARADC_0_ECDR158"} register += {"SARADC_0_ECDR159", "SARADC_0_ECDR160", "SARADC_0_ECDR161", "SARADC_0_ECDR162"} register += {"SARADC_0_ECDR163", "SARADC_0_ECDR164", "SARADC_0_ECDR165", "SARADC_0_ECDR166"} register += {"SARADC_0_ECDR167", "SARADC_0_ECDR168", "SARADC_0_ECDR169", "SARADC_0_ECDR170"} register += {"SARADC_0_ECDR171", "SARADC_0_ECDR172", "SARADC_0_ECDR173", "SARADC_0_ECDR174"} register += {"SARADC_0_ECDR175", "SARADC_0_ECDR176", "SARADC_0_ECDR177", "SARADC_0_ECDR178"} register += {"SARADC_0_ECDR179", "SARADC_0_ECDR180", "SARADC_0_ECDR181", "SARADC_0_ECDR182"} register += {"SARADC_0_ECDR183", "SARADC_0_ECDR184", "SARADC_0_ECDR185", "SARADC_0_ECDR186"} register += {"SARADC_0_ECDR187", "SARADC_0_ECDR188", "SARADC_0_ECDR189", "SARADC_0_ECDR190"} register += {"SARADC_0_ECDR191", "SARADC_0_ECDR192", "SARADC_0_ECDR193", "SARADC_0_ECDR194"} register += {"SARADC_0_ECDR195", "SARADC_0_ECDR196", "SARADC_0_ECDR197", "SARADC_0_ECDR198"} register += {"SARADC_0_ECDR199", "SARADC_0_ECDR200", "SARADC_0_ECDR201", "SARADC_0_ECDR202"} register += {"SARADC_0_ECDR203", "SARADC_0_ECDR204", "SARADC_0_ECDR205", "SARADC_0_ECDR206"} register += {"SARADC_0_ECDR207", "SARADC_0_ECDR208", "SARADC_0_ECDR209", "SARADC_0_ECDR210"} register += {"SARADC_0_ECDR211", "SARADC_0_ECDR212", "SARADC_0_ECDR213", "SARADC_0_ECDR214"} register += {"SARADC_0_ECDR215", "SARADC_0_ECDR216", "SARADC_0_ECDR217", "SARADC_0_ECDR218"} register += {"SARADC_0_ECDR219", "SARADC_0_ECDR220", "SARADC_0_ECDR221", "SARADC_0_ECDR222"} register += {"SARADC_0_ECDR223", "SARADC_0_ECDR224", "SARADC_0_ECDR225", "SARADC_0_ECDR226"} register += {"SARADC_0_ECDR227", "SARADC_0_ECDR228", "SARADC_0_ECDR229", "SARADC_0_ECDR230"} register += {"SARADC_0_ECDR231", "SARADC_0_ECDR232", "SARADC_0_ECDR233", "SARADC_0_ECDR234"} register += {"SARADC_0_ECDR235", "SARADC_0_ECDR236", "SARADC_0_ECDR237", "SARADC_0_ECDR238"} register += {"SARADC_0_ECDR239", "SARADC_0_ECDR240", "SARADC_0_ECDR241", "SARADC_0_ECDR242"} register += {"SARADC_0_ECDR243", "SARADC_0_ECDR244", "SARADC_0_ECDR245", "SARADC_0_ECDR246"} register += {"SARADC_0_ECDR247", "SARADC_0_ECDR248", "SARADC_0_ECDR249", "SARADC_0_ECDR250"} register += {"SARADC_0_ECDR251", "SARADC_0_ECDR252", "SARADC_0_ECDR253", "SARADC_0_ECDR254"} register += {"SARADC_0_ECDR255"} } SARADC_4 { sn = "SARADC_4" ln = "SARADC_4" hk = "SARADC_4" collapse = true register += {"SARADC_4_MCR", "SARADC_4_MSR", "SARADC_4_ISR", "SARADC_4_ICIPR0"} register += {"SARADC_4_ICIPR1", "SARADC_4_ICIPR2", "SARADC_4_IMR", "SARADC_4_ICIMR0"} register += {"SARADC_4_ICIMR1", "SARADC_4_ICIMR2", "SARADC_4_WTISR", "SARADC_4_WTIMR"} register += {"SARADC_4_DMAE", "SARADC_4_ICDSR0", "SARADC_4_ICDSR1", "SARADC_4_ICDSR2"} register += {"SARADC_4_WTHRHLR0", "SARADC_4_WTHRHLR1", "SARADC_4_WTHRHLR2"} register += {"SARADC_4_WTHRHLR3", "SARADC_4_CTR0", "SARADC_4_CTR1", "SARADC_4_CTR2"} register += {"SARADC_4_CTR3", "SARADC_4_ICNCMR0", "SARADC_4_ICNCMR1", "SARADC_4_ICNCMR2"} register += {"SARADC_4_ICJCMR0", "SARADC_4_ICJCMR1", "SARADC_4_ICJCMR2", "SARADC_4_PDEDR"} register += {"SARADC_4_ICDR0", "SARADC_4_ICDR1", "SARADC_4_ICDR2", "SARADC_4_ICDR3"} register += {"SARADC_4_ICDR4", "SARADC_4_ICDR5", "SARADC_4_ICDR6", "SARADC_4_ICDR7"} register += {"SARADC_4_ICDR8", "SARADC_4_ICDR9", "SARADC_4_ICDR10", "SARADC_4_ICDR11"} register += {"SARADC_4_ICDR12", "SARADC_4_ICDR13", "SARADC_4_ICDR14", "SARADC_4_ICDR15"} register += {"SARADC_4_ICDR16", "SARADC_4_ICDR17", "SARADC_4_ICDR18", "SARADC_4_ICDR19"} register += {"SARADC_4_ICDR20", "SARADC_4_ICDR21", "SARADC_4_ICDR22", "SARADC_4_ICDR23"} register += {"SARADC_4_ICDR24", "SARADC_4_ICDR25", "SARADC_4_ICDR26", "SARADC_4_ICDR27"} register += {"SARADC_4_ICDR28", "SARADC_4_ICDR29", "SARADC_4_ICDR30", "SARADC_4_ICDR31"} register += {"SARADC_4_ICDR32", "SARADC_4_ICDR33", "SARADC_4_ICDR34", "SARADC_4_ICDR35"} register += {"SARADC_4_ICDR36", "SARADC_4_ICDR37", "SARADC_4_ICDR38", "SARADC_4_ICDR39"} register += {"SARADC_4_ICDR40", "SARADC_4_ICDR41", "SARADC_4_ICDR42", "SARADC_4_ICDR43"} register += {"SARADC_4_ICDR44", "SARADC_4_ICDR45", "SARADC_4_ICDR46", "SARADC_4_ICDR47"} register += {"SARADC_4_ICDR48", "SARADC_4_ICDR49", "SARADC_4_ICDR50", "SARADC_4_ICDR51"} register += {"SARADC_4_ICDR52", "SARADC_4_ICDR53", "SARADC_4_ICDR54", "SARADC_4_ICDR55"} register += {"SARADC_4_ICDR56", "SARADC_4_ICDR57", "SARADC_4_ICDR58", "SARADC_4_ICDR59"} register += {"SARADC_4_ICDR60", "SARADC_4_ICDR61", "SARADC_4_ICDR62", "SARADC_4_ICDR63"} register += {"SARADC_4_ICDR64", "SARADC_4_ICDR65", "SARADC_4_ICDR66", "SARADC_4_ICDR67"} register += {"SARADC_4_ICDR68", "SARADC_4_ICDR69", "SARADC_4_ICDR70", "SARADC_4_ICDR71"} register += {"SARADC_4_ICDR72", "SARADC_4_ICDR73", "SARADC_4_ICDR74", "SARADC_4_ICDR75"} register += {"SARADC_4_ICDR76", "SARADC_4_ICDR77", "SARADC_4_ICDR78", "SARADC_4_ICDR79"} register += {"SARADC_4_ICDR80", "SARADC_4_ICDR81", "SARADC_4_ICDR82", "SARADC_4_ICDR83"} register += {"SARADC_4_ICDR84", "SARADC_4_ICDR85", "SARADC_4_ICDR86", "SARADC_4_ICDR87"} register += {"SARADC_4_ICDR88", "SARADC_4_ICDR89", "SARADC_4_ICDR90", "SARADC_4_ICDR91"} register += {"SARADC_4_ICDR92", "SARADC_4_ICDR93", "SARADC_4_ICDR94", "SARADC_4_ICDR95"} register += {"SARADC_4_ICWSELR0", "SARADC_4_ICWSELR1", "SARADC_4_ICWSELR2"} register += {"SARADC_4_ICWSELR3", "SARADC_4_ICWSELR4", "SARADC_4_ICWSELR5"} register += {"SARADC_4_ICWSELR6", "SARADC_4_ICWSELR7", "SARADC_4_ICWSELR8"} register += {"SARADC_4_ICWSELR9", "SARADC_4_ICWSELR10", "SARADC_4_ICWSELR11"} register += {"SARADC_4_ICWENR0", "SARADC_4_ICWENR1", "SARADC_4_ICWENR2", "SARADC_4_ICAWORR0"} register += {"SARADC_4_ICAWORR1", "SARADC_4_ICAWORR2", "SARADC_4_TCIPR", "SARADC_4_TCIMR"} register += {"SARADC_4_TCDSR", "SARADC_4_TCNCMR", "SARADC_4_TCJCMR", "SARADC_4_TCWSELR0"} register += {"SARADC_4_TCWSELR1", "SARADC_4_TCWSELR2", "SARADC_4_TCWSELR3"} register += {"SARADC_4_TCWENR", "SARADC_4_TCAWORR", "SARADC_4_TCCAPR0", "SARADC_4_TCCAPR1"} register += {"SARADC_4_TCCAPR2", "SARADC_4_TCCAPR3", "SARADC_4_TCCAPR4", "SARADC_4_TCCAPR5"} register += {"SARADC_4_TCCAPR6", "SARADC_4_TCCAPR7", "SARADC_4_TCDR96", "SARADC_4_TCDR97"} register += {"SARADC_4_TCDR98", "SARADC_4_TCDR99", "SARADC_4_TCDR100", "SARADC_4_TCDR101"} register += {"SARADC_4_TCDR102", "SARADC_4_TCDR103", "SARADC_4_TCDR104", "SARADC_4_TCDR105"} register += {"SARADC_4_TCDR106", "SARADC_4_TCDR107", "SARADC_4_TCDR108", "SARADC_4_TCDR109"} register += {"SARADC_4_TCDR110", "SARADC_4_TCDR111", "SARADC_4_TCDR112", "SARADC_4_TCDR113"} register += {"SARADC_4_TCDR114", "SARADC_4_TCDR115", "SARADC_4_TCDR116", "SARADC_4_TCDR117"} register += {"SARADC_4_TCDR118", "SARADC_4_TCDR119", "SARADC_4_TCDR120", "SARADC_4_TCDR121"} register += {"SARADC_4_TCDR122", "SARADC_4_TCDR123", "SARADC_4_TCDR124", "SARADC_4_TCDR125"} register += {"SARADC_4_TCDR126", "SARADC_4_TCDR127", "SARADC_4_ECDSDR", "SARADC_4_ECIPR0"} register += {"SARADC_4_ECIPR1", "SARADC_4_ECIPR2", "SARADC_4_ECIPR3", "SARADC_4_ECIMR0"} register += {"SARADC_4_ECIMR1", "SARADC_4_ECIMR2", "SARADC_4_ECIMR3", "SARADC_4_ECDSR0"} register += {"SARADC_4_ECDSR1", "SARADC_4_ECDSR2", "SARADC_4_ECDSR3", "SARADC_4_ECNCMR0"} register += {"SARADC_4_ECNCMR1", "SARADC_4_ECNCMR2", "SARADC_4_ECNCMR3", "SARADC_4_ECJCMR0"} register += {"SARADC_4_ECJCMR1", "SARADC_4_ECJCMR2", "SARADC_4_ECJCMR3", "SARADC_4_ECWSELR0"} register += {"SARADC_4_ECWSELR1", "SARADC_4_ECWSELR2", "SARADC_4_ECWSELR3"} register += {"SARADC_4_ECWSELR4", "SARADC_4_ECWSELR5", "SARADC_4_ECWSELR6"} register += {"SARADC_4_ECWSELR7", "SARADC_4_ECWSELR8", "SARADC_4_ECWSELR9"} register += {"SARADC_4_ECWSELR10", "SARADC_4_ECWSELR11", "SARADC_4_ECWSELR12"} register += {"SARADC_4_ECWSELR13", "SARADC_4_ECWSELR14", "SARADC_4_ECWSELR15"} register += {"SARADC_4_ECWENR0", "SARADC_4_ECWENR1", "SARADC_4_ECWENR2", "SARADC_4_ECWENR3"} register += {"SARADC_4_ECAWORR0", "SARADC_4_ECAWORR1", "SARADC_4_ECAWORR2"} register += {"SARADC_4_ECAWORR3", "SARADC_4_ECMICR0", "SARADC_4_ECMICR1", "SARADC_4_ECMICR2"} register += {"SARADC_4_ECMICR3", "SARADC_4_ECDR128", "SARADC_4_ECDR129", "SARADC_4_ECDR130"} register += {"SARADC_4_ECDR131", "SARADC_4_ECDR132", "SARADC_4_ECDR133", "SARADC_4_ECDR134"} register += {"SARADC_4_ECDR135", "SARADC_4_ECDR136", "SARADC_4_ECDR137", "SARADC_4_ECDR138"} register += {"SARADC_4_ECDR139", "SARADC_4_ECDR140", "SARADC_4_ECDR141", "SARADC_4_ECDR142"} register += {"SARADC_4_ECDR143", "SARADC_4_ECDR144", "SARADC_4_ECDR145", "SARADC_4_ECDR146"} register += {"SARADC_4_ECDR147", "SARADC_4_ECDR148", "SARADC_4_ECDR149", "SARADC_4_ECDR150"} register += {"SARADC_4_ECDR151", "SARADC_4_ECDR152", "SARADC_4_ECDR153", "SARADC_4_ECDR154"} register += {"SARADC_4_ECDR155", "SARADC_4_ECDR156", "SARADC_4_ECDR157", "SARADC_4_ECDR158"} register += {"SARADC_4_ECDR159", "SARADC_4_ECDR160", "SARADC_4_ECDR161", "SARADC_4_ECDR162"} register += {"SARADC_4_ECDR163", "SARADC_4_ECDR164", "SARADC_4_ECDR165", "SARADC_4_ECDR166"} register += {"SARADC_4_ECDR167", "SARADC_4_ECDR168", "SARADC_4_ECDR169", "SARADC_4_ECDR170"} register += {"SARADC_4_ECDR171", "SARADC_4_ECDR172", "SARADC_4_ECDR173", "SARADC_4_ECDR174"} register += {"SARADC_4_ECDR175", "SARADC_4_ECDR176", "SARADC_4_ECDR177", "SARADC_4_ECDR178"} register += {"SARADC_4_ECDR179", "SARADC_4_ECDR180", "SARADC_4_ECDR181", "SARADC_4_ECDR182"} register += {"SARADC_4_ECDR183", "SARADC_4_ECDR184", "SARADC_4_ECDR185", "SARADC_4_ECDR186"} register += {"SARADC_4_ECDR187", "SARADC_4_ECDR188", "SARADC_4_ECDR189", "SARADC_4_ECDR190"} register += {"SARADC_4_ECDR191", "SARADC_4_ECDR192", "SARADC_4_ECDR193", "SARADC_4_ECDR194"} register += {"SARADC_4_ECDR195", "SARADC_4_ECDR196", "SARADC_4_ECDR197", "SARADC_4_ECDR198"} register += {"SARADC_4_ECDR199", "SARADC_4_ECDR200", "SARADC_4_ECDR201", "SARADC_4_ECDR202"} register += {"SARADC_4_ECDR203", "SARADC_4_ECDR204", "SARADC_4_ECDR205", "SARADC_4_ECDR206"} register += {"SARADC_4_ECDR207", "SARADC_4_ECDR208", "SARADC_4_ECDR209", "SARADC_4_ECDR210"} register += {"SARADC_4_ECDR211", "SARADC_4_ECDR212", "SARADC_4_ECDR213", "SARADC_4_ECDR214"} register += {"SARADC_4_ECDR215", "SARADC_4_ECDR216", "SARADC_4_ECDR217", "SARADC_4_ECDR218"} register += {"SARADC_4_ECDR219", "SARADC_4_ECDR220", "SARADC_4_ECDR221", "SARADC_4_ECDR222"} register += {"SARADC_4_ECDR223", "SARADC_4_ECDR224", "SARADC_4_ECDR225", "SARADC_4_ECDR226"} register += {"SARADC_4_ECDR227", "SARADC_4_ECDR228", "SARADC_4_ECDR229", "SARADC_4_ECDR230"} register += {"SARADC_4_ECDR231", "SARADC_4_ECDR232", "SARADC_4_ECDR233", "SARADC_4_ECDR234"} register += {"SARADC_4_ECDR235", "SARADC_4_ECDR236", "SARADC_4_ECDR237", "SARADC_4_ECDR238"} register += {"SARADC_4_ECDR239", "SARADC_4_ECDR240", "SARADC_4_ECDR241", "SARADC_4_ECDR242"} register += {"SARADC_4_ECDR243", "SARADC_4_ECDR244", "SARADC_4_ECDR245", "SARADC_4_ECDR246"} register += {"SARADC_4_ECDR247", "SARADC_4_ECDR248", "SARADC_4_ECDR249", "SARADC_4_ECDR250"} register += {"SARADC_4_ECDR251", "SARADC_4_ECDR252", "SARADC_4_ECDR253", "SARADC_4_ECDR254"} register += {"SARADC_4_ECDR255"} } SARADC_B { sn = "SARADC_B" ln = "SARADC_B" hk = "SARADC_B" collapse = true register += {"SARADC_B_MCR", "SARADC_B_MSR", "SARADC_B_ISR", "SARADC_B_ICIPR0"} register += {"SARADC_B_ICIPR1", "SARADC_B_ICIPR2", "SARADC_B_IMR", "SARADC_B_ICIMR0"} register += {"SARADC_B_ICIMR1", "SARADC_B_ICIMR2", "SARADC_B_WTISR", "SARADC_B_WTIMR"} register += {"SARADC_B_DMAE", "SARADC_B_ICDSR0", "SARADC_B_ICDSR1", "SARADC_B_ICDSR2"} register += {"SARADC_B_WTHRHLR0", "SARADC_B_WTHRHLR1", "SARADC_B_WTHRHLR2"} register += {"SARADC_B_WTHRHLR3", "SARADC_B_CTR0", "SARADC_B_CTR1", "SARADC_B_CTR2"} register += {"SARADC_B_CTR3", "SARADC_B_ICNCMR0", "SARADC_B_ICNCMR1", "SARADC_B_ICNCMR2"} register += {"SARADC_B_ICJCMR0", "SARADC_B_ICJCMR1", "SARADC_B_ICJCMR2", "SARADC_B_PDEDR"} register += {"SARADC_B_ICDR0", "SARADC_B_ICDR1", "SARADC_B_ICDR2", "SARADC_B_ICDR3"} register += {"SARADC_B_ICDR4", "SARADC_B_ICDR5", "SARADC_B_ICDR6", "SARADC_B_ICDR7"} register += {"SARADC_B_ICDR8", "SARADC_B_ICDR9", "SARADC_B_ICDR10", "SARADC_B_ICDR11"} register += {"SARADC_B_ICDR12", "SARADC_B_ICDR13", "SARADC_B_ICDR14", "SARADC_B_ICDR15"} register += {"SARADC_B_ICDR16", "SARADC_B_ICDR17", "SARADC_B_ICDR18", "SARADC_B_ICDR19"} register += {"SARADC_B_ICDR20", "SARADC_B_ICDR21", "SARADC_B_ICDR22", "SARADC_B_ICDR23"} register += {"SARADC_B_ICDR24", "SARADC_B_ICDR25", "SARADC_B_ICDR26", "SARADC_B_ICDR27"} register += {"SARADC_B_ICDR28", "SARADC_B_ICDR29", "SARADC_B_ICDR30", "SARADC_B_ICDR31"} register += {"SARADC_B_ICDR32", "SARADC_B_ICDR33", "SARADC_B_ICDR34", "SARADC_B_ICDR35"} register += {"SARADC_B_ICDR36", "SARADC_B_ICDR37", "SARADC_B_ICDR38", "SARADC_B_ICDR39"} register += {"SARADC_B_ICDR40", "SARADC_B_ICDR41", "SARADC_B_ICDR42", "SARADC_B_ICDR43"} register += {"SARADC_B_ICDR44", "SARADC_B_ICDR45", "SARADC_B_ICDR46", "SARADC_B_ICDR47"} register += {"SARADC_B_ICDR48", "SARADC_B_ICDR49", "SARADC_B_ICDR50", "SARADC_B_ICDR51"} register += {"SARADC_B_ICDR52", "SARADC_B_ICDR53", "SARADC_B_ICDR54", "SARADC_B_ICDR55"} register += {"SARADC_B_ICDR56", "SARADC_B_ICDR57", "SARADC_B_ICDR58", "SARADC_B_ICDR59"} register += {"SARADC_B_ICDR60", "SARADC_B_ICDR61", "SARADC_B_ICDR62", "SARADC_B_ICDR63"} register += {"SARADC_B_ICDR64", "SARADC_B_ICDR65", "SARADC_B_ICDR66", "SARADC_B_ICDR67"} register += {"SARADC_B_ICDR68", "SARADC_B_ICDR69", "SARADC_B_ICDR70", "SARADC_B_ICDR71"} register += {"SARADC_B_ICDR72", "SARADC_B_ICDR73", "SARADC_B_ICDR74", "SARADC_B_ICDR75"} register += {"SARADC_B_ICDR76", "SARADC_B_ICDR77", "SARADC_B_ICDR78", "SARADC_B_ICDR79"} register += {"SARADC_B_ICDR80", "SARADC_B_ICDR81", "SARADC_B_ICDR82", "SARADC_B_ICDR83"} register += {"SARADC_B_ICDR84", "SARADC_B_ICDR85", "SARADC_B_ICDR86", "SARADC_B_ICDR87"} register += {"SARADC_B_ICDR88", "SARADC_B_ICDR89", "SARADC_B_ICDR90", "SARADC_B_ICDR91"} register += {"SARADC_B_ICDR92", "SARADC_B_ICDR93", "SARADC_B_ICDR94", "SARADC_B_ICDR95"} register += {"SARADC_B_ICWSELR0", "SARADC_B_ICWSELR1", "SARADC_B_ICWSELR2"} register += {"SARADC_B_ICWSELR3", "SARADC_B_ICWSELR4", "SARADC_B_ICWSELR5"} register += {"SARADC_B_ICWSELR6", "SARADC_B_ICWSELR7", "SARADC_B_ICWSELR8"} register += {"SARADC_B_ICWSELR9", "SARADC_B_ICWSELR10", "SARADC_B_ICWSELR11"} register += {"SARADC_B_ICWENR0", "SARADC_B_ICWENR1", "SARADC_B_ICWENR2", "SARADC_B_ICAWORR0"} register += {"SARADC_B_ICAWORR1", "SARADC_B_ICAWORR2", "SARADC_B_TCIPR", "SARADC_B_TCIMR"} register += {"SARADC_B_TCDSR", "SARADC_B_TCNCMR", "SARADC_B_TCJCMR", "SARADC_B_TCWSELR0"} register += {"SARADC_B_TCWSELR1", "SARADC_B_TCWSELR2", "SARADC_B_TCWSELR3"} register += {"SARADC_B_TCWENR", "SARADC_B_TCAWORR", "SARADC_B_TCCAPR0", "SARADC_B_TCCAPR1"} register += {"SARADC_B_TCCAPR2", "SARADC_B_TCCAPR3", "SARADC_B_TCCAPR4", "SARADC_B_TCCAPR5"} register += {"SARADC_B_TCCAPR6", "SARADC_B_TCCAPR7", "SARADC_B_TCDR96", "SARADC_B_TCDR97"} register += {"SARADC_B_TCDR98", "SARADC_B_TCDR99", "SARADC_B_TCDR100", "SARADC_B_TCDR101"} register += {"SARADC_B_TCDR102", "SARADC_B_TCDR103", "SARADC_B_TCDR104", "SARADC_B_TCDR105"} register += {"SARADC_B_TCDR106", "SARADC_B_TCDR107", "SARADC_B_TCDR108", "SARADC_B_TCDR109"} register += {"SARADC_B_TCDR110", "SARADC_B_TCDR111", "SARADC_B_TCDR112", "SARADC_B_TCDR113"} register += {"SARADC_B_TCDR114", "SARADC_B_TCDR115", "SARADC_B_TCDR116", "SARADC_B_TCDR117"} register += {"SARADC_B_TCDR118", "SARADC_B_TCDR119", "SARADC_B_TCDR120", "SARADC_B_TCDR121"} register += {"SARADC_B_TCDR122", "SARADC_B_TCDR123", "SARADC_B_TCDR124", "SARADC_B_TCDR125"} register += {"SARADC_B_TCDR126", "SARADC_B_TCDR127", "SARADC_B_ECDSDR", "SARADC_B_ECIPR0"} register += {"SARADC_B_ECIPR1", "SARADC_B_ECIPR2", "SARADC_B_ECIPR3", "SARADC_B_ECIMR0"} register += {"SARADC_B_ECIMR1", "SARADC_B_ECIMR2", "SARADC_B_ECIMR3", "SARADC_B_ECDSR0"} register += {"SARADC_B_ECDSR1", "SARADC_B_ECDSR2", "SARADC_B_ECDSR3", "SARADC_B_ECNCMR0"} register += {"SARADC_B_ECNCMR1", "SARADC_B_ECNCMR2", "SARADC_B_ECNCMR3", "SARADC_B_ECJCMR0"} register += {"SARADC_B_ECJCMR1", "SARADC_B_ECJCMR2", "SARADC_B_ECJCMR3", "SARADC_B_ECWSELR0"} register += {"SARADC_B_ECWSELR1", "SARADC_B_ECWSELR2", "SARADC_B_ECWSELR3"} register += {"SARADC_B_ECWSELR4", "SARADC_B_ECWSELR5", "SARADC_B_ECWSELR6"} register += {"SARADC_B_ECWSELR7", "SARADC_B_ECWSELR8", "SARADC_B_ECWSELR9"} register += {"SARADC_B_ECWSELR10", "SARADC_B_ECWSELR11", "SARADC_B_ECWSELR12"} register += {"SARADC_B_ECWSELR13", "SARADC_B_ECWSELR14", "SARADC_B_ECWSELR15"} register += {"SARADC_B_ECWENR0", "SARADC_B_ECWENR1", "SARADC_B_ECWENR2", "SARADC_B_ECWENR3"} register += {"SARADC_B_ECAWORR0", "SARADC_B_ECAWORR1", "SARADC_B_ECAWORR2"} register += {"SARADC_B_ECAWORR3", "SARADC_B_ECMICR0", "SARADC_B_ECMICR1", "SARADC_B_ECMICR2"} register += {"SARADC_B_ECMICR3", "SARADC_B_ECDR128", "SARADC_B_ECDR129", "SARADC_B_ECDR130"} register += {"SARADC_B_ECDR131", "SARADC_B_ECDR132", "SARADC_B_ECDR133", "SARADC_B_ECDR134"} register += {"SARADC_B_ECDR135", "SARADC_B_ECDR136", "SARADC_B_ECDR137", "SARADC_B_ECDR138"} register += {"SARADC_B_ECDR139", "SARADC_B_ECDR140", "SARADC_B_ECDR141", "SARADC_B_ECDR142"} register += {"SARADC_B_ECDR143", "SARADC_B_ECDR144", "SARADC_B_ECDR145", "SARADC_B_ECDR146"} register += {"SARADC_B_ECDR147", "SARADC_B_ECDR148", "SARADC_B_ECDR149", "SARADC_B_ECDR150"} register += {"SARADC_B_ECDR151", "SARADC_B_ECDR152", "SARADC_B_ECDR153", "SARADC_B_ECDR154"} register += {"SARADC_B_ECDR155", "SARADC_B_ECDR156", "SARADC_B_ECDR157", "SARADC_B_ECDR158"} register += {"SARADC_B_ECDR159", "SARADC_B_ECDR160", "SARADC_B_ECDR161", "SARADC_B_ECDR162"} register += {"SARADC_B_ECDR163", "SARADC_B_ECDR164", "SARADC_B_ECDR165", "SARADC_B_ECDR166"} register += {"SARADC_B_ECDR167", "SARADC_B_ECDR168", "SARADC_B_ECDR169", "SARADC_B_ECDR170"} register += {"SARADC_B_ECDR171", "SARADC_B_ECDR172", "SARADC_B_ECDR173", "SARADC_B_ECDR174"} register += {"SARADC_B_ECDR175", "SARADC_B_ECDR176", "SARADC_B_ECDR177", "SARADC_B_ECDR178"} register += {"SARADC_B_ECDR179", "SARADC_B_ECDR180", "SARADC_B_ECDR181", "SARADC_B_ECDR182"} register += {"SARADC_B_ECDR183", "SARADC_B_ECDR184", "SARADC_B_ECDR185", "SARADC_B_ECDR186"} register += {"SARADC_B_ECDR187", "SARADC_B_ECDR188", "SARADC_B_ECDR189", "SARADC_B_ECDR190"} register += {"SARADC_B_ECDR191", "SARADC_B_ECDR192", "SARADC_B_ECDR193", "SARADC_B_ECDR194"} register += {"SARADC_B_ECDR195", "SARADC_B_ECDR196", "SARADC_B_ECDR197", "SARADC_B_ECDR198"} register += {"SARADC_B_ECDR199", "SARADC_B_ECDR200", "SARADC_B_ECDR201", "SARADC_B_ECDR202"} register += {"SARADC_B_ECDR203", "SARADC_B_ECDR204", "SARADC_B_ECDR205", "SARADC_B_ECDR206"} register += {"SARADC_B_ECDR207", "SARADC_B_ECDR208", "SARADC_B_ECDR209", "SARADC_B_ECDR210"} register += {"SARADC_B_ECDR211", "SARADC_B_ECDR212", "SARADC_B_ECDR213", "SARADC_B_ECDR214"} register += {"SARADC_B_ECDR215", "SARADC_B_ECDR216", "SARADC_B_ECDR217", "SARADC_B_ECDR218"} register += {"SARADC_B_ECDR219", "SARADC_B_ECDR220", "SARADC_B_ECDR221", "SARADC_B_ECDR222"} register += {"SARADC_B_ECDR223", "SARADC_B_ECDR224", "SARADC_B_ECDR225", "SARADC_B_ECDR226"} register += {"SARADC_B_ECDR227", "SARADC_B_ECDR228", "SARADC_B_ECDR229", "SARADC_B_ECDR230"} register += {"SARADC_B_ECDR231", "SARADC_B_ECDR232", "SARADC_B_ECDR233", "SARADC_B_ECDR234"} register += {"SARADC_B_ECDR235", "SARADC_B_ECDR236", "SARADC_B_ECDR237", "SARADC_B_ECDR238"} register += {"SARADC_B_ECDR239", "SARADC_B_ECDR240", "SARADC_B_ECDR241", "SARADC_B_ECDR242"} register += {"SARADC_B_ECDR243", "SARADC_B_ECDR244", "SARADC_B_ECDR245", "SARADC_B_ECDR246"} register += {"SARADC_B_ECDR247", "SARADC_B_ECDR248", "SARADC_B_ECDR249", "SARADC_B_ECDR250"} register += {"SARADC_B_ECDR251", "SARADC_B_ECDR252", "SARADC_B_ECDR253", "SARADC_B_ECDR254"} register += {"SARADC_B_ECDR255"} } SDADC_3 { sn = "SDADC_3" ln = "SDADC_3" hk = "SDADC_3" collapse = true register += {"SDADC_3_MCR", "SDADC_3_CSR", "SDADC_3_RKR", "SDADC_3_SFR", "SDADC_3_RSER"} register += {"SDADC_3_OSDR", "SDADC_3_FCR", "SDADC_3_STKR", "SDADC_3_CDR", "SDADC_3_WTHHLR"} } SIPI_0 { sn = "SIPI_0" ln = "SIPI_0" hk = "SIPI_0" collapse = true register += {"SIPI_0_CCR0", "SIPI_0_CSR0", "SIPI_0_CIR0", "SIPI_0_CTOR0", "SIPI_0_CCRC0"} register += {"SIPI_0_CAR0", "SIPI_0_CDR0", "SIPI_0_CCR1", "SIPI_0_CSR1", "SIPI_0_CIR1"} register += {"SIPI_0_CTOR1", "SIPI_0_CCRC1", "SIPI_0_CAR1", "SIPI_0_CDR1", "SIPI_0_CCR2"} register += {"SIPI_0_CSR2", "SIPI_0_CIR2", "SIPI_0_CTOR2", "SIPI_0_CCRC2", "SIPI_0_CAR2"} register += {"SIPI_0_CDR2_0", "SIPI_0_CDR2_1", "SIPI_0_CDR2_2", "SIPI_0_CDR2_3"} register += {"SIPI_0_CDR2_4", "SIPI_0_CDR2_5", "SIPI_0_CDR2_6", "SIPI_0_CDR2_7"} register += {"SIPI_0_CCR3", "SIPI_0_CSR3", "SIPI_0_CIR3", "SIPI_0_CTOR3", "SIPI_0_CCRC3"} register += {"SIPI_0_CAR3", "SIPI_0_CDR3", "SIPI_0_MCR", "SIPI_0_SR", "SIPI_0_MAXCR"} register += {"SIPI_0_ARR", "SIPI_0_ACR", "SIPI_0_ERR"} } SIUL2 { sn = "SIUL2" ln = "SIUL2" hk = "SIUL2" collapse = true register += {"SIUL2_MIDR1", "SIUL2_MIDR2", "SIUL2_DISR0", "SIUL2_DIRER0", "SIUL2_DIRSR0"} register += {"SIUL2_IREER0", "SIUL2_IFEER0", "SIUL2_IFER0", "SIUL2_IFMCR0", "SIUL2_IFMCR1"} register += {"SIUL2_IFMCR2", "SIUL2_IFMCR3", "SIUL2_IFMCR4", "SIUL2_IFMCR5", "SIUL2_IFMCR6"} register += {"SIUL2_IFMCR7", "SIUL2_IFMCR8", "SIUL2_IFMCR9", "SIUL2_IFMCR10"} register += {"SIUL2_IFMCR11", "SIUL2_IFMCR12", "SIUL2_IFMCR13", "SIUL2_IFMCR14"} register += {"SIUL2_IFMCR15", "SIUL2_IFMCR16", "SIUL2_IFMCR17", "SIUL2_IFMCR18"} register += {"SIUL2_IFMCR19", "SIUL2_IFMCR20", "SIUL2_IFMCR21", "SIUL2_IFMCR22"} register += {"SIUL2_IFMCR23", "SIUL2_IFMCR24", "SIUL2_IFMCR25", "SIUL2_IFMCR26"} register += {"SIUL2_IFMCR27", "SIUL2_IFMCR28", "SIUL2_IFMCR29", "SIUL2_IFMCR30"} register += {"SIUL2_IFMCR31", "SIUL2_IFCPR", "SIUL2_MSCR_IO_0", "SIUL2_MSCR_IO_1"} register += {"SIUL2_MSCR_IO_2", "SIUL2_MSCR_IO_3", "SIUL2_MSCR_IO_4", "SIUL2_MSCR_IO_5"} register += {"SIUL2_MSCR_IO_6", "SIUL2_MSCR_IO_7", "SIUL2_MSCR_IO_8", "SIUL2_MSCR_IO_9"} register += {"SIUL2_MSCR_IO_10", "SIUL2_MSCR_IO_11", "SIUL2_MSCR_IO_12", "SIUL2_MSCR_IO_13"} register += {"SIUL2_MSCR_IO_14", "SIUL2_MSCR_IO_15", "SIUL2_MSCR_IO_16", "SIUL2_MSCR_IO_17"} register += {"SIUL2_MSCR_IO_18", "SIUL2_MSCR_IO_19", "SIUL2_MSCR_IO_20", "SIUL2_MSCR_IO_21"} register += {"SIUL2_MSCR_IO_22", "SIUL2_MSCR_IO_23", "SIUL2_MSCR_IO_24", "SIUL2_MSCR_IO_25"} register += {"SIUL2_MSCR_IO_26", "SIUL2_MSCR_IO_27", "SIUL2_MSCR_IO_28", "SIUL2_MSCR_IO_29"} register += {"SIUL2_MSCR_IO_30", "SIUL2_MSCR_IO_31", "SIUL2_MSCR_IO_32", "SIUL2_MSCR_IO_33"} register += {"SIUL2_MSCR_IO_34", "SIUL2_MSCR_IO_35", "SIUL2_MSCR_IO_36", "SIUL2_MSCR_IO_37"} register += {"SIUL2_MSCR_IO_38", "SIUL2_MSCR_IO_39", "SIUL2_MSCR_IO_40", "SIUL2_MSCR_IO_41"} register += {"SIUL2_MSCR_IO_42", "SIUL2_MSCR_IO_43", "SIUL2_MSCR_IO_44", "SIUL2_MSCR_IO_45"} register += {"SIUL2_MSCR_IO_46", "SIUL2_MSCR_IO_47", "SIUL2_MSCR_IO_48", "SIUL2_MSCR_IO_49"} register += {"SIUL2_MSCR_IO_50", "SIUL2_MSCR_IO_51", "SIUL2_MSCR_IO_52", "SIUL2_MSCR_IO_53"} register += {"SIUL2_MSCR_IO_54", "SIUL2_MSCR_IO_55", "SIUL2_MSCR_IO_56", "SIUL2_MSCR_IO_57"} register += {"SIUL2_MSCR_IO_58", "SIUL2_MSCR_IO_59", "SIUL2_MSCR_IO_60", "SIUL2_MSCR_IO_61"} register += {"SIUL2_MSCR_IO_62", "SIUL2_MSCR_IO_63", "SIUL2_MSCR_IO_64", "SIUL2_MSCR_IO_65"} register += {"SIUL2_MSCR_IO_66", "SIUL2_MSCR_IO_67", "SIUL2_MSCR_IO_68", "SIUL2_MSCR_IO_69"} register += {"SIUL2_MSCR_IO_70", "SIUL2_MSCR_IO_71", "SIUL2_MSCR_IO_72", "SIUL2_MSCR_IO_73"} register += {"SIUL2_MSCR_IO_74", "SIUL2_MSCR_IO_75", "SIUL2_MSCR_IO_76", "SIUL2_MSCR_IO_77"} register += {"SIUL2_MSCR_IO_78", "SIUL2_MSCR_IO_79", "SIUL2_MSCR_IO_80", "SIUL2_MSCR_IO_81"} register += {"SIUL2_MSCR_IO_82", "SIUL2_MSCR_IO_83", "SIUL2_MSCR_IO_84", "SIUL2_MSCR_IO_85"} register += {"SIUL2_MSCR_IO_86", "SIUL2_MSCR_IO_87", "SIUL2_MSCR_IO_88", "SIUL2_MSCR_IO_89"} register += {"SIUL2_MSCR_IO_90", "SIUL2_MSCR_IO_91", "SIUL2_MSCR_IO_92", "SIUL2_MSCR_IO_93"} register += {"SIUL2_MSCR_IO_94", "SIUL2_MSCR_IO_95", "SIUL2_MSCR_IO_96", "SIUL2_MSCR_IO_97"} register += {"SIUL2_MSCR_IO_98", "SIUL2_MSCR_IO_99", "SIUL2_MSCR_IO_100"} register += {"SIUL2_MSCR_IO_101", "SIUL2_MSCR_IO_102", "SIUL2_MSCR_IO_103"} register += {"SIUL2_MSCR_IO_104", "SIUL2_MSCR_IO_105", "SIUL2_MSCR_IO_106"} register += {"SIUL2_MSCR_IO_107", "SIUL2_MSCR_IO_108", "SIUL2_MSCR_IO_109"} register += {"SIUL2_MSCR_IO_110", "SIUL2_MSCR_IO_111", "SIUL2_MSCR_IO_112"} register += {"SIUL2_MSCR_IO_113", "SIUL2_MSCR_IO_114", "SIUL2_MSCR_IO_115"} register += {"SIUL2_MSCR_IO_116", "SIUL2_MSCR_IO_117", "SIUL2_MSCR_IO_118"} register += {"SIUL2_MSCR_IO_119", "SIUL2_MSCR_IO_120", "SIUL2_MSCR_IO_121"} register += {"SIUL2_MSCR_IO_122", "SIUL2_MSCR_IO_123", "SIUL2_MSCR_IO_124"} register += {"SIUL2_MSCR_IO_125", "SIUL2_MSCR_IO_126", "SIUL2_MSCR_IO_127"} register += {"SIUL2_MSCR_IO_128", "SIUL2_MSCR_IO_129", "SIUL2_MSCR_IO_130"} register += {"SIUL2_MSCR_IO_131", "SIUL2_MSCR_IO_132", "SIUL2_MSCR_IO_133"} register += {"SIUL2_MSCR_IO_134", "SIUL2_MSCR_IO_135", "SIUL2_MSCR_IO_136"} register += {"SIUL2_MSCR_IO_137", "SIUL2_MSCR_IO_138", "SIUL2_MSCR_IO_139"} register += {"SIUL2_MSCR_IO_140", "SIUL2_MSCR_IO_141", "SIUL2_MSCR_IO_142"} register += {"SIUL2_MSCR_IO_143", "SIUL2_MSCR_IO_144", "SIUL2_MSCR_IO_145"} register += {"SIUL2_MSCR_IO_146", "SIUL2_MSCR_IO_147", "SIUL2_MSCR_IO_148"} register += {"SIUL2_MSCR_IO_149", "SIUL2_MSCR_IO_150", "SIUL2_MSCR_IO_151"} register += {"SIUL2_MSCR_IO_152", "SIUL2_MSCR_IO_153", "SIUL2_MSCR_IO_154"} register += {"SIUL2_MSCR_IO_155", "SIUL2_MSCR_IO_156", "SIUL2_MSCR_IO_157"} register += {"SIUL2_MSCR_IO_158", "SIUL2_MSCR_IO_159", "SIUL2_MSCR_IO_160"} register += {"SIUL2_MSCR_IO_161", "SIUL2_MSCR_IO_162", "SIUL2_MSCR_IO_163"} register += {"SIUL2_MSCR_IO_164", "SIUL2_MSCR_IO_165", "SIUL2_MSCR_IO_166"} register += {"SIUL2_MSCR_IO_167", "SIUL2_MSCR_IO_168", "SIUL2_MSCR_IO_169"} register += {"SIUL2_MSCR_IO_170", "SIUL2_MSCR_IO_171", "SIUL2_MSCR_IO_172"} register += {"SIUL2_MSCR_IO_173", "SIUL2_MSCR_IO_174", "SIUL2_MSCR_IO_175"} register += {"SIUL2_MSCR_IO_176", "SIUL2_MSCR_IO_177", "SIUL2_MSCR_IO_178"} register += {"SIUL2_MSCR_IO_179", "SIUL2_MSCR_IO_180", "SIUL2_MSCR_IO_181"} register += {"SIUL2_MSCR_IO_182", "SIUL2_MSCR_IO_183", "SIUL2_MSCR_IO_184"} register += {"SIUL2_MSCR_IO_185", "SIUL2_MSCR_IO_186", "SIUL2_MSCR_IO_187"} register += {"SIUL2_MSCR_IO_188", "SIUL2_MSCR_IO_189", "SIUL2_MSCR_IO_190"} register += {"SIUL2_MSCR_IO_191", "SIUL2_MSCR_IO_192", "SIUL2_MSCR_IO_193"} register += {"SIUL2_MSCR_IO_194", "SIUL2_MSCR_IO_195", "SIUL2_MSCR_IO_196"} register += {"SIUL2_MSCR_IO_197", "SIUL2_MSCR_IO_198", "SIUL2_MSCR_IO_199"} register += {"SIUL2_MSCR_IO_200", "SIUL2_MSCR_IO_201", "SIUL2_MSCR_IO_202"} register += {"SIUL2_MSCR_IO_203", "SIUL2_MSCR_IO_204", "SIUL2_MSCR_IO_205"} register += {"SIUL2_MSCR_IO_206", "SIUL2_MSCR_IO_207", "SIUL2_MSCR_IO_208"} register += {"SIUL2_MSCR_IO_209", "SIUL2_MSCR_IO_210", "SIUL2_MSCR_IO_211"} register += {"SIUL2_MSCR_IO_212", "SIUL2_MSCR_IO_213", "SIUL2_MSCR_IO_214"} register += {"SIUL2_MSCR_IO_215", "SIUL2_MSCR_IO_216", "SIUL2_MSCR_IO_217"} register += {"SIUL2_MSCR_IO_218", "SIUL2_MSCR_IO_219", "SIUL2_MSCR_IO_220"} register += {"SIUL2_MSCR_IO_221", "SIUL2_MSCR_IO_222", "SIUL2_MSCR_IO_223"} register += {"SIUL2_MSCR_IO_224", "SIUL2_MSCR_IO_225", "SIUL2_MSCR_IO_226"} register += {"SIUL2_MSCR_IO_227", "SIUL2_MSCR_IO_228", "SIUL2_MSCR_IO_229"} register += {"SIUL2_MSCR_IO_230", "SIUL2_MSCR_IO_231", "SIUL2_MSCR_IO_232"} register += {"SIUL2_MSCR_IO_233", "SIUL2_MSCR_IO_234", "SIUL2_MSCR_IO_235"} register += {"SIUL2_MSCR_IO_236", "SIUL2_MSCR_IO_237", "SIUL2_MSCR_IO_238"} register += {"SIUL2_MSCR_IO_239", "SIUL2_MSCR_IO_240", "SIUL2_MSCR_IO_241"} register += {"SIUL2_MSCR_IO_242", "SIUL2_MSCR_IO_243", "SIUL2_MSCR_IO_244"} register += {"SIUL2_MSCR_IO_245", "SIUL2_MSCR_IO_246", "SIUL2_MSCR_IO_247"} register += {"SIUL2_MSCR_IO_248", "SIUL2_MSCR_IO_249", "SIUL2_MSCR_IO_250"} register += {"SIUL2_MSCR_IO_251", "SIUL2_MSCR_IO_252", "SIUL2_MSCR_IO_253"} register += {"SIUL2_MSCR_IO_254", "SIUL2_MSCR_IO_255", "SIUL2_MSCR_IO_256"} register += {"SIUL2_MSCR_IO_257", "SIUL2_MSCR_IO_258", "SIUL2_MSCR_IO_259"} register += {"SIUL2_MSCR_IO_260", "SIUL2_MSCR_IO_261", "SIUL2_MSCR_IO_262"} register += {"SIUL2_MSCR_IO_263", "SIUL2_MSCR_IO_264", "SIUL2_MSCR_IO_265"} register += {"SIUL2_MSCR_IO_266", "SIUL2_MSCR_IO_267", "SIUL2_MSCR_IO_268"} register += {"SIUL2_MSCR_IO_269", "SIUL2_MSCR_IO_270", "SIUL2_MSCR_IO_271"} register += {"SIUL2_MSCR_IO_272", "SIUL2_MSCR_IO_273", "SIUL2_MSCR_IO_274"} register += {"SIUL2_MSCR_IO_275", "SIUL2_MSCR_IO_276", "SIUL2_MSCR_IO_277"} register += {"SIUL2_MSCR_IO_278", "SIUL2_MSCR_IO_279", "SIUL2_MSCR_IO_280"} register += {"SIUL2_MSCR_IO_281", "SIUL2_MSCR_IO_282", "SIUL2_MSCR_IO_283"} register += {"SIUL2_MSCR_IO_284", "SIUL2_MSCR_IO_285", "SIUL2_MSCR_IO_286"} register += {"SIUL2_MSCR_IO_287", "SIUL2_MSCR_IO_288", "SIUL2_MSCR_IO_289"} register += {"SIUL2_MSCR_IO_290", "SIUL2_MSCR_IO_291", "SIUL2_MSCR_IO_292"} register += {"SIUL2_MSCR_IO_293", "SIUL2_MSCR_IO_294", "SIUL2_MSCR_IO_295"} register += {"SIUL2_MSCR_IO_296", "SIUL2_MSCR_IO_297", "SIUL2_MSCR_IO_298"} register += {"SIUL2_MSCR_IO_299", "SIUL2_MSCR_IO_300", "SIUL2_MSCR_IO_301"} register += {"SIUL2_MSCR_IO_302", "SIUL2_MSCR_IO_303", "SIUL2_MSCR_IO_304"} register += {"SIUL2_MSCR_IO_305", "SIUL2_MSCR_IO_306", "SIUL2_MSCR_IO_307"} register += {"SIUL2_MSCR_IO_308", "SIUL2_MSCR_IO_309", "SIUL2_MSCR_IO_310"} register += {"SIUL2_MSCR_IO_311", "SIUL2_MSCR_IO_312", "SIUL2_MSCR_IO_313"} register += {"SIUL2_MSCR_IO_314", "SIUL2_MSCR_IO_315", "SIUL2_MSCR_IO_316"} register += {"SIUL2_MSCR_IO_317", "SIUL2_MSCR_IO_318", "SIUL2_MSCR_IO_319"} register += {"SIUL2_MSCR_IO_320", "SIUL2_MSCR_IO_321", "SIUL2_MSCR_IO_322"} register += {"SIUL2_MSCR_IO_323", "SIUL2_MSCR_IO_324", "SIUL2_MSCR_IO_325"} register += {"SIUL2_MSCR_IO_326", "SIUL2_MSCR_IO_327", "SIUL2_MSCR_IO_328"} register += {"SIUL2_MSCR_IO_329", "SIUL2_MSCR_IO_330", "SIUL2_MSCR_IO_331"} register += {"SIUL2_MSCR_IO_332", "SIUL2_MSCR_IO_333", "SIUL2_MSCR_IO_334"} register += {"SIUL2_MSCR_IO_335", "SIUL2_MSCR_IO_336", "SIUL2_MSCR_IO_337"} register += {"SIUL2_MSCR_IO_338", "SIUL2_MSCR_IO_339", "SIUL2_MSCR_IO_340"} register += {"SIUL2_MSCR_IO_341", "SIUL2_MSCR_IO_342", "SIUL2_MSCR_IO_343"} register += {"SIUL2_MSCR_IO_344", "SIUL2_MSCR_IO_345", "SIUL2_MSCR_IO_346"} register += {"SIUL2_MSCR_IO_347", "SIUL2_MSCR_IO_348", "SIUL2_MSCR_IO_349"} register += {"SIUL2_MSCR_IO_350", "SIUL2_MSCR_IO_351", "SIUL2_MSCR_IO_352"} register += {"SIUL2_MSCR_IO_353", "SIUL2_MSCR_IO_354", "SIUL2_MSCR_IO_355"} register += {"SIUL2_MSCR_IO_356", "SIUL2_MSCR_IO_357", "SIUL2_MSCR_IO_358"} register += {"SIUL2_MSCR_IO_359", "SIUL2_MSCR_IO_360", "SIUL2_MSCR_IO_361"} register += {"SIUL2_MSCR_IO_362", "SIUL2_MSCR_IO_363", "SIUL2_MSCR_IO_364"} register += {"SIUL2_MSCR_IO_365", "SIUL2_MSCR_IO_366", "SIUL2_MSCR_IO_367"} register += {"SIUL2_MSCR_IO_368", "SIUL2_MSCR_IO_369", "SIUL2_MSCR_IO_370"} register += {"SIUL2_MSCR_IO_371", "SIUL2_MSCR_IO_372", "SIUL2_MSCR_IO_373"} register += {"SIUL2_MSCR_IO_374", "SIUL2_MSCR_IO_375", "SIUL2_MSCR_IO_376"} register += {"SIUL2_MSCR_IO_377", "SIUL2_MSCR_IO_378", "SIUL2_MSCR_IO_379"} register += {"SIUL2_MSCR_IO_380", "SIUL2_MSCR_IO_381", "SIUL2_MSCR_IO_382"} register += {"SIUL2_MSCR_IO_383", "SIUL2_MSCR_IO_384", "SIUL2_MSCR_IO_385"} register += {"SIUL2_MSCR_IO_386", "SIUL2_MSCR_IO_387", "SIUL2_MSCR_IO_388"} register += {"SIUL2_MSCR_IO_389", "SIUL2_MSCR_IO_390", "SIUL2_MSCR_IO_391"} register += {"SIUL2_MSCR_IO_392", "SIUL2_MSCR_IO_393", "SIUL2_MSCR_IO_394"} register += {"SIUL2_MSCR_IO_395", "SIUL2_MSCR_IO_396", "SIUL2_MSCR_IO_397"} register += {"SIUL2_MSCR_IO_398", "SIUL2_MSCR_IO_399", "SIUL2_MSCR_IO_400"} register += {"SIUL2_MSCR_IO_401", "SIUL2_MSCR_IO_402", "SIUL2_MSCR_IO_403"} register += {"SIUL2_MSCR_IO_404", "SIUL2_MSCR_IO_405", "SIUL2_MSCR_IO_406"} register += {"SIUL2_MSCR_IO_407", "SIUL2_MSCR_IO_408", "SIUL2_MSCR_IO_409"} register += {"SIUL2_MSCR_IO_410", "SIUL2_MSCR_IO_411", "SIUL2_MSCR_IO_412"} register += {"SIUL2_MSCR_IO_413", "SIUL2_MSCR_IO_414", "SIUL2_MSCR_IO_415"} register += {"SIUL2_MSCR_IO_416", "SIUL2_MSCR_IO_417", "SIUL2_MSCR_IO_418"} register += {"SIUL2_MSCR_IO_419", "SIUL2_MSCR_IO_420", "SIUL2_MSCR_IO_421"} register += {"SIUL2_MSCR_IO_422", "SIUL2_MSCR_IO_423", "SIUL2_MSCR_IO_424"} register += {"SIUL2_MSCR_IO_425", "SIUL2_MSCR_IO_426", "SIUL2_MSCR_IO_427"} register += {"SIUL2_MSCR_IO_428", "SIUL2_MSCR_IO_429", "SIUL2_MSCR_IO_430"} register += {"SIUL2_MSCR_IO_431", "SIUL2_MSCR_IO_432", "SIUL2_MSCR_IO_433"} register += {"SIUL2_MSCR_IO_434", "SIUL2_MSCR_IO_435", "SIUL2_MSCR_IO_436"} register += {"SIUL2_MSCR_IO_437", "SIUL2_MSCR_IO_438", "SIUL2_MSCR_IO_439"} register += {"SIUL2_MSCR_IO_440", "SIUL2_MSCR_IO_441", "SIUL2_MSCR_IO_442"} register += {"SIUL2_MSCR_IO_443", "SIUL2_MSCR_IO_444", "SIUL2_MSCR_IO_445"} register += {"SIUL2_MSCR_IO_446", "SIUL2_MSCR_IO_447", "SIUL2_MSCR_IO_448"} register += {"SIUL2_MSCR_IO_449", "SIUL2_MSCR_IO_450", "SIUL2_MSCR_IO_451"} register += {"SIUL2_MSCR_IO_452", "SIUL2_MSCR_IO_453", "SIUL2_MSCR_IO_454"} register += {"SIUL2_MSCR_IO_455", "SIUL2_MSCR_IO_456", "SIUL2_MSCR_IO_457"} register += {"SIUL2_MSCR_IO_458", "SIUL2_MSCR_IO_459", "SIUL2_MSCR_IO_460"} register += {"SIUL2_MSCR_IO_461", "SIUL2_MSCR_IO_462", "SIUL2_MSCR_IO_463"} register += {"SIUL2_MSCR_IO_464", "SIUL2_MSCR_IO_465", "SIUL2_MSCR_IO_466"} register += {"SIUL2_MSCR_IO_467", "SIUL2_MSCR_IO_468", "SIUL2_MSCR_IO_469"} register += {"SIUL2_MSCR_IO_470", "SIUL2_MSCR_IO_471", "SIUL2_MSCR_IO_472"} register += {"SIUL2_MSCR_IO_473", "SIUL2_MSCR_IO_474", "SIUL2_MSCR_IO_475"} register += {"SIUL2_MSCR_IO_476", "SIUL2_MSCR_IO_477", "SIUL2_MSCR_IO_478"} register += {"SIUL2_MSCR_IO_479", "SIUL2_MSCR_IO_480", "SIUL2_MSCR_IO_481"} register += {"SIUL2_MSCR_IO_482", "SIUL2_MSCR_IO_483", "SIUL2_MSCR_IO_484"} register += {"SIUL2_MSCR_IO_485", "SIUL2_MSCR_IO_486", "SIUL2_MSCR_IO_487"} register += {"SIUL2_MSCR_IO_488", "SIUL2_MSCR_IO_489", "SIUL2_MSCR_IO_490"} register += {"SIUL2_MSCR_IO_491", "SIUL2_MSCR_IO_492", "SIUL2_MSCR_IO_493"} register += {"SIUL2_MSCR_IO_494", "SIUL2_MSCR_IO_495", "SIUL2_MSCR_IO_496"} register += {"SIUL2_MSCR_IO_497", "SIUL2_MSCR_IO_498", "SIUL2_MSCR_IO_499"} register += {"SIUL2_MSCR_IO_500", "SIUL2_MSCR_IO_501", "SIUL2_MSCR_IO_502"} register += {"SIUL2_MSCR_IO_503", "SIUL2_MSCR_IO_504", "SIUL2_MSCR_IO_505"} register += {"SIUL2_MSCR_IO_506", "SIUL2_MSCR_IO_507", "SIUL2_MSCR_IO_508"} register += {"SIUL2_MSCR_IO_509", "SIUL2_MSCR_IO_510", "SIUL2_MSCR_IO_511"} register += {"SIUL2_MSCR_MUX_512", "SIUL2_MSCR_MUX_513", "SIUL2_MSCR_MUX_514"} register += {"SIUL2_MSCR_MUX_515", "SIUL2_MSCR_MUX_516", "SIUL2_MSCR_MUX_517"} register += {"SIUL2_MSCR_MUX_518", "SIUL2_MSCR_MUX_519", "SIUL2_MSCR_MUX_520"} register += {"SIUL2_MSCR_MUX_521", "SIUL2_MSCR_MUX_522", "SIUL2_MSCR_MUX_523"} register += {"SIUL2_MSCR_MUX_524", "SIUL2_MSCR_MUX_525", "SIUL2_MSCR_MUX_526"} register += {"SIUL2_MSCR_MUX_527", "SIUL2_MSCR_MUX_528", "SIUL2_MSCR_MUX_529"} register += {"SIUL2_MSCR_MUX_530", "SIUL2_MSCR_MUX_531", "SIUL2_MSCR_MUX_532"} register += {"SIUL2_MSCR_MUX_533", "SIUL2_MSCR_MUX_534", "SIUL2_MSCR_MUX_535"} register += {"SIUL2_MSCR_MUX_536", "SIUL2_MSCR_MUX_537", "SIUL2_MSCR_MUX_538"} register += {"SIUL2_MSCR_MUX_539", "SIUL2_MSCR_MUX_540", "SIUL2_MSCR_MUX_541"} register += {"SIUL2_MSCR_MUX_542", "SIUL2_MSCR_MUX_543", "SIUL2_MSCR_MUX_544"} register += {"SIUL2_MSCR_MUX_545", "SIUL2_MSCR_MUX_546", "SIUL2_MSCR_MUX_547"} register += {"SIUL2_MSCR_MUX_548", "SIUL2_MSCR_MUX_549", "SIUL2_MSCR_MUX_550"} register += {"SIUL2_MSCR_MUX_551", "SIUL2_MSCR_MUX_552", "SIUL2_MSCR_MUX_553"} register += {"SIUL2_MSCR_MUX_554", "SIUL2_MSCR_MUX_555", "SIUL2_MSCR_MUX_556"} register += {"SIUL2_MSCR_MUX_557", "SIUL2_MSCR_MUX_558", "SIUL2_MSCR_MUX_559"} register += {"SIUL2_MSCR_MUX_560", "SIUL2_MSCR_MUX_561", "SIUL2_MSCR_MUX_562"} register += {"SIUL2_MSCR_MUX_563", "SIUL2_MSCR_MUX_564", "SIUL2_MSCR_MUX_565"} register += {"SIUL2_MSCR_MUX_566", "SIUL2_MSCR_MUX_567", "SIUL2_MSCR_MUX_568"} register += {"SIUL2_MSCR_MUX_569", "SIUL2_MSCR_MUX_570", "SIUL2_MSCR_MUX_571"} register += {"SIUL2_MSCR_MUX_572", "SIUL2_MSCR_MUX_573", "SIUL2_MSCR_MUX_574"} register += {"SIUL2_MSCR_MUX_575", "SIUL2_MSCR_MUX_576", "SIUL2_MSCR_MUX_577"} register += {"SIUL2_MSCR_MUX_578", "SIUL2_MSCR_MUX_579", "SIUL2_MSCR_MUX_580"} register += {"SIUL2_MSCR_MUX_581", "SIUL2_MSCR_MUX_582", "SIUL2_MSCR_MUX_583"} register += {"SIUL2_MSCR_MUX_584", "SIUL2_MSCR_MUX_585", "SIUL2_MSCR_MUX_586"} register += {"SIUL2_MSCR_MUX_587", "SIUL2_MSCR_MUX_588", "SIUL2_MSCR_MUX_589"} register += {"SIUL2_MSCR_MUX_590", "SIUL2_MSCR_MUX_591", "SIUL2_MSCR_MUX_592"} register += {"SIUL2_MSCR_MUX_593", "SIUL2_MSCR_MUX_594", "SIUL2_MSCR_MUX_595"} register += {"SIUL2_MSCR_MUX_596", "SIUL2_MSCR_MUX_597", "SIUL2_MSCR_MUX_598"} register += {"SIUL2_MSCR_MUX_599", "SIUL2_MSCR_MUX_600", "SIUL2_MSCR_MUX_601"} register += {"SIUL2_MSCR_MUX_602", "SIUL2_MSCR_MUX_603", "SIUL2_MSCR_MUX_604"} register += {"SIUL2_MSCR_MUX_605", "SIUL2_MSCR_MUX_606", "SIUL2_MSCR_MUX_607"} register += {"SIUL2_MSCR_MUX_608", "SIUL2_MSCR_MUX_609", "SIUL2_MSCR_MUX_610"} register += {"SIUL2_MSCR_MUX_611", "SIUL2_MSCR_MUX_612", "SIUL2_MSCR_MUX_613"} register += {"SIUL2_MSCR_MUX_614", "SIUL2_MSCR_MUX_615", "SIUL2_MSCR_MUX_616"} register += {"SIUL2_MSCR_MUX_617", "SIUL2_MSCR_MUX_618", "SIUL2_MSCR_MUX_619"} register += {"SIUL2_MSCR_MUX_620", "SIUL2_MSCR_MUX_621", "SIUL2_MSCR_MUX_622"} register += {"SIUL2_MSCR_MUX_623", "SIUL2_MSCR_MUX_624", "SIUL2_MSCR_MUX_625"} register += {"SIUL2_MSCR_MUX_626", "SIUL2_MSCR_MUX_627", "SIUL2_MSCR_MUX_628"} register += {"SIUL2_MSCR_MUX_629", "SIUL2_MSCR_MUX_630", "SIUL2_MSCR_MUX_631"} register += {"SIUL2_MSCR_MUX_632", "SIUL2_MSCR_MUX_633", "SIUL2_MSCR_MUX_634"} register += {"SIUL2_MSCR_MUX_635", "SIUL2_MSCR_MUX_636", "SIUL2_MSCR_MUX_637"} register += {"SIUL2_MSCR_MUX_638", "SIUL2_MSCR_MUX_639", "SIUL2_MSCR_MUX_640"} register += {"SIUL2_MSCR_MUX_641", "SIUL2_MSCR_MUX_642", "SIUL2_MSCR_MUX_643"} register += {"SIUL2_MSCR_MUX_644", "SIUL2_MSCR_MUX_645", "SIUL2_MSCR_MUX_646"} register += {"SIUL2_MSCR_MUX_647", "SIUL2_MSCR_MUX_648", "SIUL2_MSCR_MUX_649"} register += {"SIUL2_MSCR_MUX_650", "SIUL2_MSCR_MUX_651", "SIUL2_MSCR_MUX_652"} register += {"SIUL2_MSCR_MUX_653", "SIUL2_MSCR_MUX_654", "SIUL2_MSCR_MUX_655"} register += {"SIUL2_MSCR_MUX_656", "SIUL2_MSCR_MUX_657", "SIUL2_MSCR_MUX_658"} register += {"SIUL2_MSCR_MUX_659", "SIUL2_MSCR_MUX_660", "SIUL2_MSCR_MUX_661"} register += {"SIUL2_MSCR_MUX_662", "SIUL2_MSCR_MUX_663", "SIUL2_MSCR_MUX_664"} register += {"SIUL2_MSCR_MUX_665", "SIUL2_MSCR_MUX_666", "SIUL2_MSCR_MUX_667"} register += {"SIUL2_MSCR_MUX_668", "SIUL2_MSCR_MUX_669", "SIUL2_MSCR_MUX_670"} register += {"SIUL2_MSCR_MUX_671", "SIUL2_MSCR_MUX_672", "SIUL2_MSCR_MUX_673"} register += {"SIUL2_MSCR_MUX_674", "SIUL2_MSCR_MUX_675", "SIUL2_MSCR_MUX_676"} register += {"SIUL2_MSCR_MUX_677", "SIUL2_MSCR_MUX_678", "SIUL2_MSCR_MUX_679"} register += {"SIUL2_MSCR_MUX_680", "SIUL2_MSCR_MUX_681", "SIUL2_MSCR_MUX_682"} register += {"SIUL2_MSCR_MUX_683", "SIUL2_MSCR_MUX_684", "SIUL2_MSCR_MUX_685"} register += {"SIUL2_MSCR_MUX_686", "SIUL2_MSCR_MUX_687", "SIUL2_MSCR_MUX_688"} register += {"SIUL2_MSCR_MUX_689", "SIUL2_MSCR_MUX_690", "SIUL2_MSCR_MUX_691"} register += {"SIUL2_MSCR_MUX_692", "SIUL2_MSCR_MUX_693", "SIUL2_MSCR_MUX_694"} register += {"SIUL2_MSCR_MUX_695", "SIUL2_MSCR_MUX_696", "SIUL2_MSCR_MUX_697"} register += {"SIUL2_MSCR_MUX_698", "SIUL2_MSCR_MUX_699", "SIUL2_MSCR_MUX_700"} register += {"SIUL2_MSCR_MUX_701", "SIUL2_MSCR_MUX_702", "SIUL2_MSCR_MUX_703"} register += {"SIUL2_MSCR_MUX_704", "SIUL2_MSCR_MUX_705", "SIUL2_MSCR_MUX_706"} register += {"SIUL2_MSCR_MUX_707", "SIUL2_MSCR_MUX_708", "SIUL2_MSCR_MUX_709"} register += {"SIUL2_MSCR_MUX_710", "SIUL2_MSCR_MUX_711", "SIUL2_MSCR_MUX_712"} register += {"SIUL2_MSCR_MUX_713", "SIUL2_MSCR_MUX_714", "SIUL2_MSCR_MUX_715"} register += {"SIUL2_MSCR_MUX_716", "SIUL2_MSCR_MUX_717", "SIUL2_MSCR_MUX_718"} register += {"SIUL2_MSCR_MUX_719", "SIUL2_MSCR_MUX_720", "SIUL2_MSCR_MUX_721"} register += {"SIUL2_MSCR_MUX_722", "SIUL2_MSCR_MUX_723", "SIUL2_MSCR_MUX_724"} register += {"SIUL2_MSCR_MUX_725", "SIUL2_MSCR_MUX_726", "SIUL2_MSCR_MUX_727"} register += {"SIUL2_MSCR_MUX_728", "SIUL2_MSCR_MUX_729", "SIUL2_MSCR_MUX_730"} register += {"SIUL2_MSCR_MUX_731", "SIUL2_MSCR_MUX_732", "SIUL2_MSCR_MUX_733"} register += {"SIUL2_MSCR_MUX_734", "SIUL2_MSCR_MUX_735", "SIUL2_MSCR_MUX_736"} register += {"SIUL2_MSCR_MUX_737", "SIUL2_MSCR_MUX_738", "SIUL2_MSCR_MUX_739"} register += {"SIUL2_MSCR_MUX_740", "SIUL2_MSCR_MUX_741", "SIUL2_MSCR_MUX_742"} register += {"SIUL2_MSCR_MUX_743", "SIUL2_MSCR_MUX_744", "SIUL2_MSCR_MUX_745"} register += {"SIUL2_MSCR_MUX_746", "SIUL2_MSCR_MUX_747", "SIUL2_MSCR_MUX_748"} register += {"SIUL2_MSCR_MUX_749", "SIUL2_MSCR_MUX_750", "SIUL2_MSCR_MUX_751"} register += {"SIUL2_MSCR_MUX_752", "SIUL2_MSCR_MUX_753", "SIUL2_MSCR_MUX_754"} register += {"SIUL2_MSCR_MUX_755", "SIUL2_MSCR_MUX_756", "SIUL2_MSCR_MUX_757"} register += {"SIUL2_MSCR_MUX_758", "SIUL2_MSCR_MUX_759", "SIUL2_MSCR_MUX_760"} register += {"SIUL2_MSCR_MUX_761", "SIUL2_MSCR_MUX_762", "SIUL2_MSCR_MUX_763"} register += {"SIUL2_MSCR_MUX_764", "SIUL2_MSCR_MUX_765", "SIUL2_MSCR_MUX_766"} register += {"SIUL2_MSCR_MUX_767", "SIUL2_MSCR_MUX_768", "SIUL2_MSCR_MUX_769"} register += {"SIUL2_MSCR_MUX_770", "SIUL2_MSCR_MUX_771", "SIUL2_MSCR_MUX_772"} register += {"SIUL2_MSCR_MUX_773", "SIUL2_MSCR_MUX_774", "SIUL2_MSCR_MUX_775"} register += {"SIUL2_MSCR_MUX_776", "SIUL2_MSCR_MUX_777", "SIUL2_MSCR_MUX_778"} register += {"SIUL2_MSCR_MUX_779", "SIUL2_MSCR_MUX_780", "SIUL2_MSCR_MUX_781"} register += {"SIUL2_MSCR_MUX_782", "SIUL2_MSCR_MUX_783", "SIUL2_MSCR_MUX_784"} register += {"SIUL2_MSCR_MUX_785", "SIUL2_MSCR_MUX_786", "SIUL2_MSCR_MUX_787"} register += {"SIUL2_MSCR_MUX_788", "SIUL2_MSCR_MUX_789", "SIUL2_MSCR_MUX_790"} register += {"SIUL2_MSCR_MUX_791", "SIUL2_MSCR_MUX_792", "SIUL2_MSCR_MUX_793"} register += {"SIUL2_MSCR_MUX_794", "SIUL2_MSCR_MUX_795", "SIUL2_MSCR_MUX_796"} register += {"SIUL2_MSCR_MUX_797", "SIUL2_MSCR_MUX_798", "SIUL2_MSCR_MUX_799"} register += {"SIUL2_MSCR_MUX_800", "SIUL2_MSCR_MUX_801", "SIUL2_MSCR_MUX_802"} register += {"SIUL2_MSCR_MUX_803", "SIUL2_MSCR_MUX_804", "SIUL2_MSCR_MUX_805"} register += {"SIUL2_MSCR_MUX_806", "SIUL2_MSCR_MUX_807", "SIUL2_MSCR_MUX_808"} register += {"SIUL2_MSCR_MUX_809", "SIUL2_MSCR_MUX_810", "SIUL2_MSCR_MUX_811"} register += {"SIUL2_MSCR_MUX_812", "SIUL2_MSCR_MUX_813", "SIUL2_MSCR_MUX_814"} register += {"SIUL2_MSCR_MUX_815", "SIUL2_MSCR_MUX_816", "SIUL2_MSCR_MUX_817"} register += {"SIUL2_MSCR_MUX_818", "SIUL2_MSCR_MUX_819", "SIUL2_MSCR_MUX_820"} register += {"SIUL2_MSCR_MUX_821", "SIUL2_MSCR_MUX_822", "SIUL2_MSCR_MUX_823"} register += {"SIUL2_MSCR_MUX_824", "SIUL2_MSCR_MUX_825", "SIUL2_MSCR_MUX_826"} register += {"SIUL2_MSCR_MUX_827", "SIUL2_MSCR_MUX_828", "SIUL2_MSCR_MUX_829"} register += {"SIUL2_MSCR_MUX_830", "SIUL2_MSCR_MUX_831", "SIUL2_MSCR_MUX_832"} register += {"SIUL2_MSCR_MUX_833", "SIUL2_MSCR_MUX_834", "SIUL2_MSCR_MUX_835"} register += {"SIUL2_MSCR_MUX_836", "SIUL2_MSCR_MUX_837", "SIUL2_MSCR_MUX_838"} register += {"SIUL2_MSCR_MUX_839", "SIUL2_MSCR_MUX_840", "SIUL2_MSCR_MUX_841"} register += {"SIUL2_MSCR_MUX_842", "SIUL2_MSCR_MUX_843", "SIUL2_MSCR_MUX_844"} register += {"SIUL2_MSCR_MUX_845", "SIUL2_MSCR_MUX_846", "SIUL2_MSCR_MUX_847"} register += {"SIUL2_MSCR_MUX_848", "SIUL2_MSCR_MUX_849", "SIUL2_MSCR_MUX_850"} register += {"SIUL2_MSCR_MUX_851", "SIUL2_MSCR_MUX_852", "SIUL2_MSCR_MUX_853"} register += {"SIUL2_MSCR_MUX_854", "SIUL2_MSCR_MUX_855", "SIUL2_MSCR_MUX_856"} register += {"SIUL2_MSCR_MUX_857", "SIUL2_MSCR_MUX_858", "SIUL2_MSCR_MUX_859"} register += {"SIUL2_MSCR_MUX_860", "SIUL2_MSCR_MUX_861", "SIUL2_MSCR_MUX_862"} register += {"SIUL2_MSCR_MUX_863", "SIUL2_MSCR_MUX_864", "SIUL2_MSCR_MUX_865"} register += {"SIUL2_MSCR_MUX_866", "SIUL2_MSCR_MUX_867", "SIUL2_MSCR_MUX_868"} register += {"SIUL2_MSCR_MUX_869", "SIUL2_MSCR_MUX_870", "SIUL2_MSCR_MUX_871"} register += {"SIUL2_MSCR_MUX_872", "SIUL2_MSCR_MUX_873", "SIUL2_MSCR_MUX_874"} register += {"SIUL2_MSCR_MUX_875", "SIUL2_MSCR_MUX_876", "SIUL2_MSCR_MUX_877"} register += {"SIUL2_MSCR_MUX_878", "SIUL2_MSCR_MUX_879", "SIUL2_MSCR_MUX_880"} register += {"SIUL2_MSCR_MUX_881", "SIUL2_MSCR_MUX_882", "SIUL2_MSCR_MUX_883"} register += {"SIUL2_MSCR_MUX_884", "SIUL2_MSCR_MUX_885", "SIUL2_MSCR_MUX_886"} register += {"SIUL2_MSCR_MUX_887", "SIUL2_MSCR_MUX_888", "SIUL2_MSCR_MUX_889"} register += {"SIUL2_MSCR_MUX_890", "SIUL2_MSCR_MUX_891", "SIUL2_MSCR_MUX_892"} register += {"SIUL2_MSCR_MUX_893", "SIUL2_MSCR_MUX_894", "SIUL2_MSCR_MUX_895"} register += {"SIUL2_MSCR_MUX_896", "SIUL2_MSCR_MUX_897", "SIUL2_MSCR_MUX_898"} register += {"SIUL2_MSCR_MUX_899", "SIUL2_MSCR_MUX_900", "SIUL2_MSCR_MUX_901"} register += {"SIUL2_MSCR_MUX_902", "SIUL2_MSCR_MUX_903", "SIUL2_MSCR_MUX_904"} register += {"SIUL2_MSCR_MUX_905", "SIUL2_MSCR_MUX_906", "SIUL2_MSCR_MUX_907"} register += {"SIUL2_MSCR_MUX_908", "SIUL2_MSCR_MUX_909", "SIUL2_MSCR_MUX_910"} register += {"SIUL2_MSCR_MUX_911", "SIUL2_MSCR_MUX_912", "SIUL2_MSCR_MUX_913"} register += {"SIUL2_MSCR_MUX_914", "SIUL2_MSCR_MUX_915", "SIUL2_MSCR_MUX_916"} register += {"SIUL2_MSCR_MUX_917", "SIUL2_MSCR_MUX_918", "SIUL2_MSCR_MUX_919"} register += {"SIUL2_MSCR_MUX_920", "SIUL2_MSCR_MUX_921", "SIUL2_MSCR_MUX_922"} register += {"SIUL2_MSCR_MUX_923", "SIUL2_MSCR_MUX_924", "SIUL2_MSCR_MUX_925"} register += {"SIUL2_MSCR_MUX_926", "SIUL2_MSCR_MUX_927", "SIUL2_MSCR_MUX_928"} register += {"SIUL2_MSCR_MUX_929", "SIUL2_MSCR_MUX_930", "SIUL2_MSCR_MUX_931"} register += {"SIUL2_MSCR_MUX_932", "SIUL2_MSCR_MUX_933", "SIUL2_MSCR_MUX_934"} register += {"SIUL2_MSCR_MUX_935", "SIUL2_MSCR_MUX_936", "SIUL2_MSCR_MUX_937"} register += {"SIUL2_MSCR_MUX_938", "SIUL2_MSCR_MUX_939", "SIUL2_MSCR_MUX_940"} register += {"SIUL2_MSCR_MUX_941", "SIUL2_MSCR_MUX_942", "SIUL2_MSCR_MUX_943"} register += {"SIUL2_MSCR_MUX_944", "SIUL2_MSCR_MUX_945", "SIUL2_MSCR_MUX_946"} register += {"SIUL2_MSCR_MUX_947", "SIUL2_MSCR_MUX_948", "SIUL2_MSCR_MUX_949"} register += {"SIUL2_MSCR_MUX_950", "SIUL2_MSCR_MUX_951", "SIUL2_MSCR_MUX_952"} register += {"SIUL2_MSCR_MUX_953", "SIUL2_MSCR_MUX_954", "SIUL2_MSCR_MUX_955"} register += {"SIUL2_MSCR_MUX_956", "SIUL2_MSCR_MUX_957", "SIUL2_MSCR_MUX_958"} register += {"SIUL2_MSCR_MUX_959", "SIUL2_MSCR_MUX_960", "SIUL2_MSCR_MUX_961"} register += {"SIUL2_MSCR_MUX_962", "SIUL2_MSCR_MUX_963", "SIUL2_MSCR_MUX_964"} register += {"SIUL2_MSCR_MUX_965", "SIUL2_MSCR_MUX_966", "SIUL2_MSCR_MUX_967"} register += {"SIUL2_MSCR_MUX_968", "SIUL2_MSCR_MUX_969", "SIUL2_MSCR_MUX_970"} register += {"SIUL2_MSCR_MUX_971", "SIUL2_MSCR_MUX_972", "SIUL2_MSCR_MUX_973"} register += {"SIUL2_MSCR_MUX_974", "SIUL2_MSCR_MUX_975", "SIUL2_MSCR_MUX_976"} register += {"SIUL2_MSCR_MUX_977", "SIUL2_MSCR_MUX_978", "SIUL2_MSCR_MUX_979"} register += {"SIUL2_MSCR_MUX_980", "SIUL2_MSCR_MUX_981", "SIUL2_MSCR_MUX_982"} register += {"SIUL2_MSCR_MUX_983", "SIUL2_MSCR_MUX_984", "SIUL2_MSCR_MUX_985"} register += {"SIUL2_MSCR_MUX_986", "SIUL2_MSCR_MUX_987", "SIUL2_MSCR_MUX_988"} register += {"SIUL2_MSCR_MUX_989", "SIUL2_MSCR_MUX_990", "SIUL2_MSCR_MUX_991"} register += {"SIUL2_MSCR_MUX_992", "SIUL2_MSCR_MUX_993", "SIUL2_MSCR_MUX_994"} register += {"SIUL2_MSCR_MUX_995", "SIUL2_MSCR_MUX_996", "SIUL2_MSCR_MUX_997"} register += {"SIUL2_MSCR_MUX_998", "SIUL2_MSCR_MUX_999", "SIUL2_MSCR_MUX_1000"} register += {"SIUL2_MSCR_MUX_1001", "SIUL2_MSCR_MUX_1002", "SIUL2_MSCR_MUX_1003"} register += {"SIUL2_MSCR_MUX_1004", "SIUL2_MSCR_MUX_1005", "SIUL2_MSCR_MUX_1006"} register += {"SIUL2_MSCR_MUX_1007", "SIUL2_MSCR_MUX_1008", "SIUL2_MSCR_MUX_1009"} register += {"SIUL2_MSCR_MUX_1010", "SIUL2_MSCR_MUX_1011", "SIUL2_MSCR_MUX_1012"} register += {"SIUL2_MSCR_MUX_1013", "SIUL2_MSCR_MUX_1014", "SIUL2_MSCR_MUX_1015"} register += {"SIUL2_MSCR_MUX_1016", "SIUL2_MSCR_MUX_1017", "SIUL2_MSCR_MUX_1018"} register += {"SIUL2_MSCR_MUX_1019", "SIUL2_MSCR_MUX_1020", "SIUL2_MSCR_MUX_1021"} register += {"SIUL2_MSCR_MUX_1022", "SIUL2_MSCR_MUX_1023", "SIUL2_GPDO0", "SIUL2_GPDO1"} register += {"SIUL2_GPDO2", "SIUL2_GPDO3", "SIUL2_GPDO4", "SIUL2_GPDO5", "SIUL2_GPDO6"} register += {"SIUL2_GPDO7", "SIUL2_GPDO8", "SIUL2_GPDO9", "SIUL2_GPDO10", "SIUL2_GPDO11"} register += {"SIUL2_GPDO12", "SIUL2_GPDO13", "SIUL2_GPDO14", "SIUL2_GPDO15", "SIUL2_GPDO16"} register += {"SIUL2_GPDO17", "SIUL2_GPDO18", "SIUL2_GPDO19", "SIUL2_GPDO20", "SIUL2_GPDO21"} register += {"SIUL2_GPDO22", "SIUL2_GPDO23", "SIUL2_GPDO24", "SIUL2_GPDO25", "SIUL2_GPDO26"} register += {"SIUL2_GPDO27", "SIUL2_GPDO28", "SIUL2_GPDO29", "SIUL2_GPDO30", "SIUL2_GPDO31"} register += {"SIUL2_GPDO32", "SIUL2_GPDO33", "SIUL2_GPDO34", "SIUL2_GPDO35", "SIUL2_GPDO36"} register += {"SIUL2_GPDO37", "SIUL2_GPDO38", "SIUL2_GPDO39", "SIUL2_GPDO40", "SIUL2_GPDO41"} register += {"SIUL2_GPDO42", "SIUL2_GPDO43", "SIUL2_GPDO44", "SIUL2_GPDO45", "SIUL2_GPDO46"} register += {"SIUL2_GPDO47", "SIUL2_GPDO48", "SIUL2_GPDO49", "SIUL2_GPDO50", "SIUL2_GPDO51"} register += {"SIUL2_GPDO52", "SIUL2_GPDO53", "SIUL2_GPDO54", "SIUL2_GPDO55", "SIUL2_GPDO56"} register += {"SIUL2_GPDO57", "SIUL2_GPDO58", "SIUL2_GPDO59", "SIUL2_GPDO60", "SIUL2_GPDO61"} register += {"SIUL2_GPDO62", "SIUL2_GPDO63", "SIUL2_GPDO64", "SIUL2_GPDO65", "SIUL2_GPDO66"} register += {"SIUL2_GPDO67", "SIUL2_GPDO68", "SIUL2_GPDO69", "SIUL2_GPDO70", "SIUL2_GPDO71"} register += {"SIUL2_GPDO72", "SIUL2_GPDO73", "SIUL2_GPDO74", "SIUL2_GPDO75", "SIUL2_GPDO76"} register += {"SIUL2_GPDO77", "SIUL2_GPDO78", "SIUL2_GPDO79", "SIUL2_GPDO80", "SIUL2_GPDO81"} register += {"SIUL2_GPDO82", "SIUL2_GPDO83", "SIUL2_GPDO84", "SIUL2_GPDO85", "SIUL2_GPDO86"} register += {"SIUL2_GPDO87", "SIUL2_GPDO88", "SIUL2_GPDO89", "SIUL2_GPDO90", "SIUL2_GPDO91"} register += {"SIUL2_GPDO92", "SIUL2_GPDO93", "SIUL2_GPDO94", "SIUL2_GPDO95", "SIUL2_GPDO96"} register += {"SIUL2_GPDO97", "SIUL2_GPDO98", "SIUL2_GPDO99", "SIUL2_GPDO100"} register += {"SIUL2_GPDO101", "SIUL2_GPDO102", "SIUL2_GPDO103", "SIUL2_GPDO104"} register += {"SIUL2_GPDO105", "SIUL2_GPDO106", "SIUL2_GPDO107", "SIUL2_GPDO108"} register += {"SIUL2_GPDO109", "SIUL2_GPDO110", "SIUL2_GPDO111", "SIUL2_GPDO112"} register += {"SIUL2_GPDO113", "SIUL2_GPDO114", "SIUL2_GPDO115", "SIUL2_GPDO116"} register += {"SIUL2_GPDO117", "SIUL2_GPDO118", "SIUL2_GPDO119", "SIUL2_GPDO120"} register += {"SIUL2_GPDO121", "SIUL2_GPDO122", "SIUL2_GPDO123", "SIUL2_GPDO124"} register += {"SIUL2_GPDO125", "SIUL2_GPDO126", "SIUL2_GPDO127", "SIUL2_GPDO128"} register += {"SIUL2_GPDO129", "SIUL2_GPDO130", "SIUL2_GPDO131", "SIUL2_GPDO132"} register += {"SIUL2_GPDO133", "SIUL2_GPDO134", "SIUL2_GPDO135", "SIUL2_GPDO136"} register += {"SIUL2_GPDO137", "SIUL2_GPDO138", "SIUL2_GPDO139", "SIUL2_GPDO140"} register += {"SIUL2_GPDO141", "SIUL2_GPDO142", "SIUL2_GPDO143", "SIUL2_GPDO144"} register += {"SIUL2_GPDO145", "SIUL2_GPDO146", "SIUL2_GPDO147", "SIUL2_GPDO148"} register += {"SIUL2_GPDO149", "SIUL2_GPDO150", "SIUL2_GPDO151", "SIUL2_GPDO152"} register += {"SIUL2_GPDO153", "SIUL2_GPDO154", "SIUL2_GPDO155", "SIUL2_GPDO156"} register += {"SIUL2_GPDO157", "SIUL2_GPDO158", "SIUL2_GPDO159", "SIUL2_GPDO160"} register += {"SIUL2_GPDO161", "SIUL2_GPDO162", "SIUL2_GPDO163", "SIUL2_GPDO164"} register += {"SIUL2_GPDO165", "SIUL2_GPDO166", "SIUL2_GPDO167", "SIUL2_GPDO168"} register += {"SIUL2_GPDO169", "SIUL2_GPDO170", "SIUL2_GPDO171", "SIUL2_GPDO172"} register += {"SIUL2_GPDO173", "SIUL2_GPDO174", "SIUL2_GPDO175", "SIUL2_GPDO176"} register += {"SIUL2_GPDO177", "SIUL2_GPDO178", "SIUL2_GPDO179", "SIUL2_GPDO180"} register += {"SIUL2_GPDO181", "SIUL2_GPDO182", "SIUL2_GPDO183", "SIUL2_GPDO184"} register += {"SIUL2_GPDO185", "SIUL2_GPDO186", "SIUL2_GPDO187", "SIUL2_GPDO188"} register += {"SIUL2_GPDO189", "SIUL2_GPDO190", "SIUL2_GPDO191", "SIUL2_GPDO192"} register += {"SIUL2_GPDO193", "SIUL2_GPDO194", "SIUL2_GPDO195", "SIUL2_GPDO196"} register += {"SIUL2_GPDO197", "SIUL2_GPDO198", "SIUL2_GPDO199", "SIUL2_GPDO200"} register += {"SIUL2_GPDO201", "SIUL2_GPDO202", "SIUL2_GPDO203", "SIUL2_GPDO204"} register += {"SIUL2_GPDO205", "SIUL2_GPDO206", "SIUL2_GPDO207", "SIUL2_GPDO208"} register += {"SIUL2_GPDO209", "SIUL2_GPDO210", "SIUL2_GPDO211", "SIUL2_GPDO212"} register += {"SIUL2_GPDO213", "SIUL2_GPDO214", "SIUL2_GPDO215", "SIUL2_GPDO216"} register += {"SIUL2_GPDO217", "SIUL2_GPDO218", "SIUL2_GPDO219", "SIUL2_GPDO220"} register += {"SIUL2_GPDO221", "SIUL2_GPDO222", "SIUL2_GPDO223", "SIUL2_GPDO224"} register += {"SIUL2_GPDO225", "SIUL2_GPDO226", "SIUL2_GPDO227", "SIUL2_GPDO228"} register += {"SIUL2_GPDO229", "SIUL2_GPDO230", "SIUL2_GPDO231", "SIUL2_GPDO232"} register += {"SIUL2_GPDO233", "SIUL2_GPDO234", "SIUL2_GPDO235", "SIUL2_GPDO236"} register += {"SIUL2_GPDO237", "SIUL2_GPDO238", "SIUL2_GPDO239", "SIUL2_GPDO240"} register += {"SIUL2_GPDO241", "SIUL2_GPDO242", "SIUL2_GPDO243", "SIUL2_GPDO244"} register += {"SIUL2_GPDO245", "SIUL2_GPDO246", "SIUL2_GPDO247", "SIUL2_GPDO248"} register += {"SIUL2_GPDO249", "SIUL2_GPDO250", "SIUL2_GPDO251", "SIUL2_GPDO252"} register += {"SIUL2_GPDO253", "SIUL2_GPDO254", "SIUL2_GPDO255", "SIUL2_GPDO256"} register += {"SIUL2_GPDO257", "SIUL2_GPDO258", "SIUL2_GPDO259", "SIUL2_GPDO260"} register += {"SIUL2_GPDO261", "SIUL2_GPDO262", "SIUL2_GPDO263", "SIUL2_GPDO264"} register += {"SIUL2_GPDO265", "SIUL2_GPDO266", "SIUL2_GPDO267", "SIUL2_GPDO268"} register += {"SIUL2_GPDO269", "SIUL2_GPDO270", "SIUL2_GPDO271", "SIUL2_GPDO272"} register += {"SIUL2_GPDO273", "SIUL2_GPDO274", "SIUL2_GPDO275", "SIUL2_GPDO276"} register += {"SIUL2_GPDO277", "SIUL2_GPDO278", "SIUL2_GPDO279", "SIUL2_GPDO280"} register += {"SIUL2_GPDO281", "SIUL2_GPDO282", "SIUL2_GPDO283", "SIUL2_GPDO284"} register += {"SIUL2_GPDO285", "SIUL2_GPDO286", "SIUL2_GPDO287", "SIUL2_GPDO288"} register += {"SIUL2_GPDO289", "SIUL2_GPDO290", "SIUL2_GPDO291", "SIUL2_GPDO292"} register += {"SIUL2_GPDO293", "SIUL2_GPDO294", "SIUL2_GPDO295", "SIUL2_GPDO296"} register += {"SIUL2_GPDO297", "SIUL2_GPDO298", "SIUL2_GPDO299", "SIUL2_GPDO300"} register += {"SIUL2_GPDO301", "SIUL2_GPDO302", "SIUL2_GPDO303", "SIUL2_GPDO304"} register += {"SIUL2_GPDO305", "SIUL2_GPDO306", "SIUL2_GPDO307", "SIUL2_GPDO308"} register += {"SIUL2_GPDO309", "SIUL2_GPDO310", "SIUL2_GPDO311", "SIUL2_GPDO312"} register += {"SIUL2_GPDO313", "SIUL2_GPDO314", "SIUL2_GPDO315", "SIUL2_GPDO316"} register += {"SIUL2_GPDO317", "SIUL2_GPDO318", "SIUL2_GPDO319", "SIUL2_GPDO320"} register += {"SIUL2_GPDO321", "SIUL2_GPDO322", "SIUL2_GPDO323", "SIUL2_GPDO324"} register += {"SIUL2_GPDO325", "SIUL2_GPDO326", "SIUL2_GPDO327", "SIUL2_GPDO328"} register += {"SIUL2_GPDO329", "SIUL2_GPDO330", "SIUL2_GPDO331", "SIUL2_GPDO332"} register += {"SIUL2_GPDO333", "SIUL2_GPDO334", "SIUL2_GPDO335", "SIUL2_GPDO336"} register += {"SIUL2_GPDO337", "SIUL2_GPDO338", "SIUL2_GPDO339", "SIUL2_GPDO340"} register += {"SIUL2_GPDO341", "SIUL2_GPDO342", "SIUL2_GPDO343", "SIUL2_GPDO344"} register += {"SIUL2_GPDO345", "SIUL2_GPDO346", "SIUL2_GPDO347", "SIUL2_GPDO348"} register += {"SIUL2_GPDO349", "SIUL2_GPDO350", "SIUL2_GPDO351", "SIUL2_GPDO352"} register += {"SIUL2_GPDO353", "SIUL2_GPDO354", "SIUL2_GPDO355", "SIUL2_GPDO356"} register += {"SIUL2_GPDO357", "SIUL2_GPDO358", "SIUL2_GPDO359", "SIUL2_GPDO360"} register += {"SIUL2_GPDO361", "SIUL2_GPDO362", "SIUL2_GPDO363", "SIUL2_GPDO364"} register += {"SIUL2_GPDO365", "SIUL2_GPDO366", "SIUL2_GPDO367", "SIUL2_GPDO368"} register += {"SIUL2_GPDO369", "SIUL2_GPDO370", "SIUL2_GPDO371", "SIUL2_GPDO372"} register += {"SIUL2_GPDO373", "SIUL2_GPDO374", "SIUL2_GPDO375", "SIUL2_GPDO376"} register += {"SIUL2_GPDO377", "SIUL2_GPDO378", "SIUL2_GPDO379", "SIUL2_GPDO380"} register += {"SIUL2_GPDO381", "SIUL2_GPDO382", "SIUL2_GPDO383", "SIUL2_GPDO384"} register += {"SIUL2_GPDO385", "SIUL2_GPDO386", "SIUL2_GPDO387", "SIUL2_GPDO388"} register += {"SIUL2_GPDO389", "SIUL2_GPDO390", "SIUL2_GPDO391", "SIUL2_GPDO392"} register += {"SIUL2_GPDO393", "SIUL2_GPDO394", "SIUL2_GPDO395", "SIUL2_GPDO396"} register += {"SIUL2_GPDO397", "SIUL2_GPDO398", "SIUL2_GPDO399", "SIUL2_GPDO400"} register += {"SIUL2_GPDO401", "SIUL2_GPDO402", "SIUL2_GPDO403", "SIUL2_GPDO404"} register += {"SIUL2_GPDO405", "SIUL2_GPDO406", "SIUL2_GPDO407", "SIUL2_GPDO408"} register += {"SIUL2_GPDO409", "SIUL2_GPDO410", "SIUL2_GPDO411", "SIUL2_GPDO412"} register += {"SIUL2_GPDO413", "SIUL2_GPDO414", "SIUL2_GPDO415", "SIUL2_GPDO416"} register += {"SIUL2_GPDO417", "SIUL2_GPDO418", "SIUL2_GPDO419", "SIUL2_GPDO420"} register += {"SIUL2_GPDO421", "SIUL2_GPDO422", "SIUL2_GPDO423", "SIUL2_GPDO424"} register += {"SIUL2_GPDO425", "SIUL2_GPDO426", "SIUL2_GPDO427", "SIUL2_GPDO428"} register += {"SIUL2_GPDO429", "SIUL2_GPDO430", "SIUL2_GPDO431", "SIUL2_GPDO432"} register += {"SIUL2_GPDO433", "SIUL2_GPDO434", "SIUL2_GPDO435", "SIUL2_GPDO436"} register += {"SIUL2_GPDO437", "SIUL2_GPDO438", "SIUL2_GPDO439", "SIUL2_GPDO440"} register += {"SIUL2_GPDO441", "SIUL2_GPDO442", "SIUL2_GPDO443", "SIUL2_GPDO444"} register += {"SIUL2_GPDO445", "SIUL2_GPDO446", "SIUL2_GPDO447", "SIUL2_GPDO448"} register += {"SIUL2_GPDO449", "SIUL2_GPDO450", "SIUL2_GPDO451", "SIUL2_GPDO452"} register += {"SIUL2_GPDO453", "SIUL2_GPDO454", "SIUL2_GPDO455", "SIUL2_GPDO456"} register += {"SIUL2_GPDO457", "SIUL2_GPDO458", "SIUL2_GPDO459", "SIUL2_GPDO460"} register += {"SIUL2_GPDO461", "SIUL2_GPDO462", "SIUL2_GPDO463", "SIUL2_GPDO464"} register += {"SIUL2_GPDO465", "SIUL2_GPDO466", "SIUL2_GPDO467", "SIUL2_GPDO468"} register += {"SIUL2_GPDO469", "SIUL2_GPDO470", "SIUL2_GPDO471", "SIUL2_GPDO472"} register += {"SIUL2_GPDO473", "SIUL2_GPDO474", "SIUL2_GPDO475", "SIUL2_GPDO476"} register += {"SIUL2_GPDO477", "SIUL2_GPDO478", "SIUL2_GPDO479", "SIUL2_GPDO480"} register += {"SIUL2_GPDO481", "SIUL2_GPDO482", "SIUL2_GPDO483", "SIUL2_GPDO484"} register += {"SIUL2_GPDO485", "SIUL2_GPDO486", "SIUL2_GPDO487", "SIUL2_GPDO488"} register += {"SIUL2_GPDO489", "SIUL2_GPDO490", "SIUL2_GPDO491", "SIUL2_GPDO492"} register += {"SIUL2_GPDO493", "SIUL2_GPDO494", "SIUL2_GPDO495", "SIUL2_GPDO496"} register += {"SIUL2_GPDO497", "SIUL2_GPDO498", "SIUL2_GPDO499", "SIUL2_GPDO500"} register += {"SIUL2_GPDO501", "SIUL2_GPDO502", "SIUL2_GPDO503", "SIUL2_GPDO504"} register += {"SIUL2_GPDO505", "SIUL2_GPDO506", "SIUL2_GPDO507", "SIUL2_GPDO508"} register += {"SIUL2_GPDO509", "SIUL2_GPDO510", "SIUL2_GPDO511", "SIUL2_GPDI0", "SIUL2_GPDI1"} register += {"SIUL2_GPDI2", "SIUL2_GPDI3", "SIUL2_GPDI4", "SIUL2_GPDI5", "SIUL2_GPDI6"} register += {"SIUL2_GPDI7", "SIUL2_GPDI8", "SIUL2_GPDI9", "SIUL2_GPDI10", "SIUL2_GPDI11"} register += {"SIUL2_GPDI12", "SIUL2_GPDI13", "SIUL2_GPDI14", "SIUL2_GPDI15", "SIUL2_GPDI16"} register += {"SIUL2_GPDI17", "SIUL2_GPDI18", "SIUL2_GPDI19", "SIUL2_GPDI20", "SIUL2_GPDI21"} register += {"SIUL2_GPDI22", "SIUL2_GPDI23", "SIUL2_GPDI24", "SIUL2_GPDI25", "SIUL2_GPDI26"} register += {"SIUL2_GPDI27", "SIUL2_GPDI28", "SIUL2_GPDI29", "SIUL2_GPDI30", "SIUL2_GPDI31"} register += {"SIUL2_GPDI32", "SIUL2_GPDI33", "SIUL2_GPDI34", "SIUL2_GPDI35", "SIUL2_GPDI36"} register += {"SIUL2_GPDI37", "SIUL2_GPDI38", "SIUL2_GPDI39", "SIUL2_GPDI40", "SIUL2_GPDI41"} register += {"SIUL2_GPDI42", "SIUL2_GPDI43", "SIUL2_GPDI44", "SIUL2_GPDI45", "SIUL2_GPDI46"} register += {"SIUL2_GPDI47", "SIUL2_GPDI48", "SIUL2_GPDI49", "SIUL2_GPDI50", "SIUL2_GPDI51"} register += {"SIUL2_GPDI52", "SIUL2_GPDI53", "SIUL2_GPDI54", "SIUL2_GPDI55", "SIUL2_GPDI56"} register += {"SIUL2_GPDI57", "SIUL2_GPDI58", "SIUL2_GPDI59", "SIUL2_GPDI60", "SIUL2_GPDI61"} register += {"SIUL2_GPDI62", "SIUL2_GPDI63", "SIUL2_GPDI64", "SIUL2_GPDI65", "SIUL2_GPDI66"} register += {"SIUL2_GPDI67", "SIUL2_GPDI68", "SIUL2_GPDI69", "SIUL2_GPDI70", "SIUL2_GPDI71"} register += {"SIUL2_GPDI72", "SIUL2_GPDI73", "SIUL2_GPDI74", "SIUL2_GPDI75", "SIUL2_GPDI76"} register += {"SIUL2_GPDI77", "SIUL2_GPDI78", "SIUL2_GPDI79", "SIUL2_GPDI80", "SIUL2_GPDI81"} register += {"SIUL2_GPDI82", "SIUL2_GPDI83", "SIUL2_GPDI84", "SIUL2_GPDI85", "SIUL2_GPDI86"} register += {"SIUL2_GPDI87", "SIUL2_GPDI88", "SIUL2_GPDI89", "SIUL2_GPDI90", "SIUL2_GPDI91"} register += {"SIUL2_GPDI92", "SIUL2_GPDI93", "SIUL2_GPDI94", "SIUL2_GPDI95", "SIUL2_GPDI96"} register += {"SIUL2_GPDI97", "SIUL2_GPDI98", "SIUL2_GPDI99", "SIUL2_GPDI100"} register += {"SIUL2_GPDI101", "SIUL2_GPDI102", "SIUL2_GPDI103", "SIUL2_GPDI104"} register += {"SIUL2_GPDI105", "SIUL2_GPDI106", "SIUL2_GPDI107", "SIUL2_GPDI108"} register += {"SIUL2_GPDI109", "SIUL2_GPDI110", "SIUL2_GPDI111", "SIUL2_GPDI112"} register += {"SIUL2_GPDI113", "SIUL2_GPDI114", "SIUL2_GPDI115", "SIUL2_GPDI116"} register += {"SIUL2_GPDI117", "SIUL2_GPDI118", "SIUL2_GPDI119", "SIUL2_GPDI120"} register += {"SIUL2_GPDI121", "SIUL2_GPDI122", "SIUL2_GPDI123", "SIUL2_GPDI124"} register += {"SIUL2_GPDI125", "SIUL2_GPDI126", "SIUL2_GPDI127", "SIUL2_GPDI128"} register += {"SIUL2_GPDI129", "SIUL2_GPDI130", "SIUL2_GPDI131", "SIUL2_GPDI132"} register += {"SIUL2_GPDI133", "SIUL2_GPDI134", "SIUL2_GPDI135", "SIUL2_GPDI136"} register += {"SIUL2_GPDI137", "SIUL2_GPDI138", "SIUL2_GPDI139", "SIUL2_GPDI140"} register += {"SIUL2_GPDI141", "SIUL2_GPDI142", "SIUL2_GPDI143", "SIUL2_GPDI144"} register += {"SIUL2_GPDI145", "SIUL2_GPDI146", "SIUL2_GPDI147", "SIUL2_GPDI148"} register += {"SIUL2_GPDI149", "SIUL2_GPDI150", "SIUL2_GPDI151", "SIUL2_GPDI152"} register += {"SIUL2_GPDI153", "SIUL2_GPDI154", "SIUL2_GPDI155", "SIUL2_GPDI156"} register += {"SIUL2_GPDI157", "SIUL2_GPDI158", "SIUL2_GPDI159", "SIUL2_GPDI160"} register += {"SIUL2_GPDI161", "SIUL2_GPDI162", "SIUL2_GPDI163", "SIUL2_GPDI164"} register += {"SIUL2_GPDI165", "SIUL2_GPDI166", "SIUL2_GPDI167", "SIUL2_GPDI168"} register += {"SIUL2_GPDI169", "SIUL2_GPDI170", "SIUL2_GPDI171", "SIUL2_GPDI172"} register += {"SIUL2_GPDI173", "SIUL2_GPDI174", "SIUL2_GPDI175", "SIUL2_GPDI176"} register += {"SIUL2_GPDI177", "SIUL2_GPDI178", "SIUL2_GPDI179", "SIUL2_GPDI180"} register += {"SIUL2_GPDI181", "SIUL2_GPDI182", "SIUL2_GPDI183", "SIUL2_GPDI184"} register += {"SIUL2_GPDI185", "SIUL2_GPDI186", "SIUL2_GPDI187", "SIUL2_GPDI188"} register += {"SIUL2_GPDI189", "SIUL2_GPDI190", "SIUL2_GPDI191", "SIUL2_GPDI192"} register += {"SIUL2_GPDI193", "SIUL2_GPDI194", "SIUL2_GPDI195", "SIUL2_GPDI196"} register += {"SIUL2_GPDI197", "SIUL2_GPDI198", "SIUL2_GPDI199", "SIUL2_GPDI200"} register += {"SIUL2_GPDI201", "SIUL2_GPDI202", "SIUL2_GPDI203", "SIUL2_GPDI204"} register += {"SIUL2_GPDI205", "SIUL2_GPDI206", "SIUL2_GPDI207", "SIUL2_GPDI208"} register += {"SIUL2_GPDI209", "SIUL2_GPDI210", "SIUL2_GPDI211", "SIUL2_GPDI212"} register += {"SIUL2_GPDI213", "SIUL2_GPDI214", "SIUL2_GPDI215", "SIUL2_GPDI216"} register += {"SIUL2_GPDI217", "SIUL2_GPDI218", "SIUL2_GPDI219", "SIUL2_GPDI220"} register += {"SIUL2_GPDI221", "SIUL2_GPDI222", "SIUL2_GPDI223", "SIUL2_GPDI224"} register += {"SIUL2_GPDI225", "SIUL2_GPDI226", "SIUL2_GPDI227", "SIUL2_GPDI228"} register += {"SIUL2_GPDI229", "SIUL2_GPDI230", "SIUL2_GPDI231", "SIUL2_GPDI232"} register += {"SIUL2_GPDI233", "SIUL2_GPDI234", "SIUL2_GPDI235", "SIUL2_GPDI236"} register += {"SIUL2_GPDI237", "SIUL2_GPDI238", "SIUL2_GPDI239", "SIUL2_GPDI240"} register += {"SIUL2_GPDI241", "SIUL2_GPDI242", "SIUL2_GPDI243", "SIUL2_GPDI244"} register += {"SIUL2_GPDI245", "SIUL2_GPDI246", "SIUL2_GPDI247", "SIUL2_GPDI248"} register += {"SIUL2_GPDI249", "SIUL2_GPDI250", "SIUL2_GPDI251", "SIUL2_GPDI252"} register += {"SIUL2_GPDI253", "SIUL2_GPDI254", "SIUL2_GPDI255", "SIUL2_GPDI256"} register += {"SIUL2_GPDI257", "SIUL2_GPDI258", "SIUL2_GPDI259", "SIUL2_GPDI260"} register += {"SIUL2_GPDI261", "SIUL2_GPDI262", "SIUL2_GPDI263", "SIUL2_GPDI264"} register += {"SIUL2_GPDI265", "SIUL2_GPDI266", "SIUL2_GPDI267", "SIUL2_GPDI268"} register += {"SIUL2_GPDI269", "SIUL2_GPDI270", "SIUL2_GPDI271", "SIUL2_GPDI272"} register += {"SIUL2_GPDI273", "SIUL2_GPDI274", "SIUL2_GPDI275", "SIUL2_GPDI276"} register += {"SIUL2_GPDI277", "SIUL2_GPDI278", "SIUL2_GPDI279", "SIUL2_GPDI280"} register += {"SIUL2_GPDI281", "SIUL2_GPDI282", "SIUL2_GPDI283", "SIUL2_GPDI284"} register += {"SIUL2_GPDI285", "SIUL2_GPDI286", "SIUL2_GPDI287", "SIUL2_GPDI288"} register += {"SIUL2_GPDI289", "SIUL2_GPDI290", "SIUL2_GPDI291", "SIUL2_GPDI292"} register += {"SIUL2_GPDI293", "SIUL2_GPDI294", "SIUL2_GPDI295", "SIUL2_GPDI296"} register += {"SIUL2_GPDI297", "SIUL2_GPDI298", "SIUL2_GPDI299", "SIUL2_GPDI300"} register += {"SIUL2_GPDI301", "SIUL2_GPDI302", "SIUL2_GPDI303", "SIUL2_GPDI304"} register += {"SIUL2_GPDI305", "SIUL2_GPDI306", "SIUL2_GPDI307", "SIUL2_GPDI308"} register += {"SIUL2_GPDI309", "SIUL2_GPDI310", "SIUL2_GPDI311", "SIUL2_GPDI312"} register += {"SIUL2_GPDI313", "SIUL2_GPDI314", "SIUL2_GPDI315", "SIUL2_GPDI316"} register += {"SIUL2_GPDI317", "SIUL2_GPDI318", "SIUL2_GPDI319", "SIUL2_GPDI320"} register += {"SIUL2_GPDI321", "SIUL2_GPDI322", "SIUL2_GPDI323", "SIUL2_GPDI324"} register += {"SIUL2_GPDI325", "SIUL2_GPDI326", "SIUL2_GPDI327", "SIUL2_GPDI328"} register += {"SIUL2_GPDI329", "SIUL2_GPDI330", "SIUL2_GPDI331", "SIUL2_GPDI332"} register += {"SIUL2_GPDI333", "SIUL2_GPDI334", "SIUL2_GPDI335", "SIUL2_GPDI336"} register += {"SIUL2_GPDI337", "SIUL2_GPDI338", "SIUL2_GPDI339", "SIUL2_GPDI340"} register += {"SIUL2_GPDI341", "SIUL2_GPDI342", "SIUL2_GPDI343", "SIUL2_GPDI344"} register += {"SIUL2_GPDI345", "SIUL2_GPDI346", "SIUL2_GPDI347", "SIUL2_GPDI348"} register += {"SIUL2_GPDI349", "SIUL2_GPDI350", "SIUL2_GPDI351", "SIUL2_GPDI352"} register += {"SIUL2_GPDI353", "SIUL2_GPDI354", "SIUL2_GPDI355", "SIUL2_GPDI356"} register += {"SIUL2_GPDI357", "SIUL2_GPDI358", "SIUL2_GPDI359", "SIUL2_GPDI360"} register += {"SIUL2_GPDI361", "SIUL2_GPDI362", "SIUL2_GPDI363", "SIUL2_GPDI364"} register += {"SIUL2_GPDI365", "SIUL2_GPDI366", "SIUL2_GPDI367", "SIUL2_GPDI368"} register += {"SIUL2_GPDI369", "SIUL2_GPDI370", "SIUL2_GPDI371", "SIUL2_GPDI372"} register += {"SIUL2_GPDI373", "SIUL2_GPDI374", "SIUL2_GPDI375", "SIUL2_GPDI376"} register += {"SIUL2_GPDI377", "SIUL2_GPDI378", "SIUL2_GPDI379", "SIUL2_GPDI380"} register += {"SIUL2_GPDI381", "SIUL2_GPDI382", "SIUL2_GPDI383", "SIUL2_GPDI384"} register += {"SIUL2_GPDI385", "SIUL2_GPDI386", "SIUL2_GPDI387", "SIUL2_GPDI388"} register += {"SIUL2_GPDI389", "SIUL2_GPDI390", "SIUL2_GPDI391", "SIUL2_GPDI392"} register += {"SIUL2_GPDI393", "SIUL2_GPDI394", "SIUL2_GPDI395", "SIUL2_GPDI396"} register += {"SIUL2_GPDI397", "SIUL2_GPDI398", "SIUL2_GPDI399", "SIUL2_GPDI400"} register += {"SIUL2_GPDI401", "SIUL2_GPDI402", "SIUL2_GPDI403", "SIUL2_GPDI404"} register += {"SIUL2_GPDI405", "SIUL2_GPDI406", "SIUL2_GPDI407", "SIUL2_GPDI408"} register += {"SIUL2_GPDI409", "SIUL2_GPDI410", "SIUL2_GPDI411", "SIUL2_GPDI412"} register += {"SIUL2_GPDI413", "SIUL2_GPDI414", "SIUL2_GPDI415", "SIUL2_GPDI416"} register += {"SIUL2_GPDI417", "SIUL2_GPDI418", "SIUL2_GPDI419", "SIUL2_GPDI420"} register += {"SIUL2_GPDI421", "SIUL2_GPDI422", "SIUL2_GPDI423", "SIUL2_GPDI424"} register += {"SIUL2_GPDI425", "SIUL2_GPDI426", "SIUL2_GPDI427", "SIUL2_GPDI428"} register += {"SIUL2_GPDI429", "SIUL2_GPDI430", "SIUL2_GPDI431", "SIUL2_GPDI432"} register += {"SIUL2_GPDI433", "SIUL2_GPDI434", "SIUL2_GPDI435", "SIUL2_GPDI436"} register += {"SIUL2_GPDI437", "SIUL2_GPDI438", "SIUL2_GPDI439", "SIUL2_GPDI440"} register += {"SIUL2_GPDI441", "SIUL2_GPDI442", "SIUL2_GPDI443", "SIUL2_GPDI444"} register += {"SIUL2_GPDI445", "SIUL2_GPDI446", "SIUL2_GPDI447", "SIUL2_GPDI448"} register += {"SIUL2_GPDI449", "SIUL2_GPDI450", "SIUL2_GPDI451", "SIUL2_GPDI452"} register += {"SIUL2_GPDI453", "SIUL2_GPDI454", "SIUL2_GPDI455", "SIUL2_GPDI456"} register += {"SIUL2_GPDI457", "SIUL2_GPDI458", "SIUL2_GPDI459", "SIUL2_GPDI460"} register += {"SIUL2_GPDI461", "SIUL2_GPDI462", "SIUL2_GPDI463", "SIUL2_GPDI464"} register += {"SIUL2_GPDI465", "SIUL2_GPDI466", "SIUL2_GPDI467", "SIUL2_GPDI468"} register += {"SIUL2_GPDI469", "SIUL2_GPDI470", "SIUL2_GPDI471", "SIUL2_GPDI472"} register += {"SIUL2_GPDI473", "SIUL2_GPDI474", "SIUL2_GPDI475", "SIUL2_GPDI476"} register += {"SIUL2_GPDI477", "SIUL2_GPDI478", "SIUL2_GPDI479", "SIUL2_GPDI480"} register += {"SIUL2_GPDI481", "SIUL2_GPDI482", "SIUL2_GPDI483", "SIUL2_GPDI484"} register += {"SIUL2_GPDI485", "SIUL2_GPDI486", "SIUL2_GPDI487", "SIUL2_GPDI488"} register += {"SIUL2_GPDI489", "SIUL2_GPDI490", "SIUL2_GPDI491", "SIUL2_GPDI492"} register += {"SIUL2_GPDI493", "SIUL2_GPDI494", "SIUL2_GPDI495", "SIUL2_GPDI496"} register += {"SIUL2_GPDI497", "SIUL2_GPDI498", "SIUL2_GPDI499", "SIUL2_GPDI500"} register += {"SIUL2_GPDI501", "SIUL2_GPDI502", "SIUL2_GPDI503", "SIUL2_GPDI504"} register += {"SIUL2_GPDI505", "SIUL2_GPDI506", "SIUL2_GPDI507", "SIUL2_GPDI508"} register += {"SIUL2_GPDI509", "SIUL2_GPDI510", "SIUL2_GPDI511", "SIUL2_PGPDO0_1"} register += {"SIUL2_PGPDO2_3", "SIUL2_PGPDO4_5", "SIUL2_PGPDO6_7", "SIUL2_PGPDO8_9"} register += {"SIUL2_PGPDO10_11", "SIUL2_PGPDO12_13", "SIUL2_PGPDO14_15", "SIUL2_PGPDO16_17"} register += {"SIUL2_PGPDO18_19", "SIUL2_PGPDO20_21", "SIUL2_PGPDO22_23", "SIUL2_PGPDO24_25"} register += {"SIUL2_PGPDO26_27", "SIUL2_PGPDO28_29", "SIUL2_PGPDO30_31", "SIUL2_PGPDI0_1"} register += {"SIUL2_PGPDI2_3", "SIUL2_PGPDI4_5", "SIUL2_PGPDI6_7", "SIUL2_PGPDI8_9"} register += {"SIUL2_PGPDI10_11", "SIUL2_PGPDI12_13", "SIUL2_PGPDI14_15", "SIUL2_PGPDI16_17"} register += {"SIUL2_PGPDI18_19", "SIUL2_PGPDI20_21", "SIUL2_PGPDI22_23", "SIUL2_PGPDI24_25"} register += {"SIUL2_PGPDI26_27", "SIUL2_PGPDI28_29", "SIUL2_PGPDI30_31", "SIUL2_MPGPDO0"} register += {"SIUL2_MPGPDO1", "SIUL2_MPGPDO2", "SIUL2_MPGPDO3", "SIUL2_MPGPDO4"} register += {"SIUL2_MPGPDO5", "SIUL2_MPGPDO6", "SIUL2_MPGPDO7", "SIUL2_MPGPDO8"} register += {"SIUL2_MPGPDO9", "SIUL2_MPGPDO10", "SIUL2_MPGPDO11", "SIUL2_MPGPDO12"} register += {"SIUL2_MPGPDO13", "SIUL2_MPGPDO14", "SIUL2_MPGPDO15", "SIUL2_MPGPDO16"} register += {"SIUL2_MPGPDO17", "SIUL2_MPGPDO18", "SIUL2_MPGPDO19", "SIUL2_MPGPDO20"} register += {"SIUL2_MPGPDO21", "SIUL2_MPGPDO22", "SIUL2_MPGPDO23", "SIUL2_MPGPDO24"} register += {"SIUL2_MPGPDO25", "SIUL2_MPGPDO26", "SIUL2_MPGPDO27", "SIUL2_MPGPDO28"} register += {"SIUL2_MPGPDO29", "SIUL2_MPGPDO30", "SIUL2_MPGPDO31"} } SMPU_0 { sn = "SMPU_0" ln = "SMPU_0" hk = "SMPU_0" collapse = true register += {"SMPU_0_CESR0", "SMPU_0_CESR1", "SMPU_0_EAR0", "SMPU_0_EDR0", "SMPU_0_EAR1"} register += {"SMPU_0_EDR1", "SMPU_0_EAR2", "SMPU_0_EDR2", "SMPU_0_EAR3", "SMPU_0_EDR3"} register += {"SMPU_0_EAR4", "SMPU_0_EDR4", "SMPU_0_EAR5", "SMPU_0_EDR5", "SMPU_0_EAR6"} register += {"SMPU_0_EDR6", "SMPU_0_EAR7", "SMPU_0_EDR7", "SMPU_0_EAR8", "SMPU_0_EDR8"} register += {"SMPU_0_EAR9", "SMPU_0_EDR9", "SMPU_0_EAR10", "SMPU_0_EDR10", "SMPU_0_EAR11"} register += {"SMPU_0_EDR11", "SMPU_0_EAR12", "SMPU_0_EDR12", "SMPU_0_EAR13", "SMPU_0_EDR13"} register += {"SMPU_0_EAR14", "SMPU_0_EDR14", "SMPU_0_EAR15", "SMPU_0_EDR15"} register += {"SMPU_0_RGD0_WORD0", "SMPU_0_RGD0_WORD1", "SMPU_0_RGD0_WORD2_FMT0"} register += {"SMPU_0_RGD0_WORD2_FMT1", "SMPU_0_RGD0_WORD3", "SMPU_0_RGD1_WORD0"} register += {"SMPU_0_RGD1_WORD1", "SMPU_0_RGD1_WORD2_FMT0", "SMPU_0_RGD1_WORD2_FMT1"} register += {"SMPU_0_RGD1_WORD3", "SMPU_0_RGD2_WORD0", "SMPU_0_RGD2_WORD1"} register += {"SMPU_0_RGD2_WORD2_FMT0", "SMPU_0_RGD2_WORD2_FMT1", "SMPU_0_RGD2_WORD3"} register += {"SMPU_0_RGD3_WORD0", "SMPU_0_RGD3_WORD1", "SMPU_0_RGD3_WORD2_FMT0"} register += {"SMPU_0_RGD3_WORD2_FMT1", "SMPU_0_RGD3_WORD3", "SMPU_0_RGD4_WORD0"} register += {"SMPU_0_RGD4_WORD1", "SMPU_0_RGD4_WORD2_FMT0", "SMPU_0_RGD4_WORD2_FMT1"} register += {"SMPU_0_RGD4_WORD3", "SMPU_0_RGD5_WORD0", "SMPU_0_RGD5_WORD1"} register += {"SMPU_0_RGD5_WORD2_FMT0", "SMPU_0_RGD5_WORD2_FMT1", "SMPU_0_RGD5_WORD3"} register += {"SMPU_0_RGD6_WORD0", "SMPU_0_RGD6_WORD1", "SMPU_0_RGD6_WORD2_FMT0"} register += {"SMPU_0_RGD6_WORD2_FMT1", "SMPU_0_RGD6_WORD3", "SMPU_0_RGD7_WORD0"} register += {"SMPU_0_RGD7_WORD1", "SMPU_0_RGD7_WORD2_FMT0", "SMPU_0_RGD7_WORD2_FMT1"} register += {"SMPU_0_RGD7_WORD3", "SMPU_0_RGD8_WORD0", "SMPU_0_RGD8_WORD1"} register += {"SMPU_0_RGD8_WORD2_FMT0", "SMPU_0_RGD8_WORD2_FMT1", "SMPU_0_RGD8_WORD3"} register += {"SMPU_0_RGD9_WORD0", "SMPU_0_RGD9_WORD1", "SMPU_0_RGD9_WORD2_FMT0"} register += {"SMPU_0_RGD9_WORD2_FMT1", "SMPU_0_RGD9_WORD3", "SMPU_0_RGD10_WORD0"} register += {"SMPU_0_RGD10_WORD1", "SMPU_0_RGD10_WORD2_FMT0", "SMPU_0_RGD10_WORD2_FMT1"} register += {"SMPU_0_RGD10_WORD3", "SMPU_0_RGD11_WORD0", "SMPU_0_RGD11_WORD1"} register += {"SMPU_0_RGD11_WORD2_FMT0", "SMPU_0_RGD11_WORD2_FMT1", "SMPU_0_RGD11_WORD3"} } SRX_0 { sn = "SRX_0" ln = "SRX_0" hk = "SRX_0" collapse = true register += {"SRX_0_GBL_CTRL", "SRX_0_CHNL_EN", "SRX_0_GBL_STATUS", "SRX_0_FMSG_RDY"} register += {"SRX_0_SMSG_RDY", "SRX_0_DATA_CTRL1", "SRX_0_DATA_CTRL2", "SRX_0_FDMA_CTRL"} register += {"SRX_0_SDMA_CTRL", "SRX_0_FRDY_IE", "SRX_0_SRDY_IE", "SRX_0_DMA_FMSG_DATA"} register += {"SRX_0_DMA_FMSG_CRC", "SRX_0_DMA_FMSG_TS", "SRX_0_DMA_SMSG_BIT3"} register += {"SRX_0_DMA_SMSG_BIT2", "SRX_0_DMA_SMSG_TS", "SRX_0_CH0_CLK_CTRL"} register += {"SRX_0_CH0_STATUS", "SRX_0_CH0_CONFIG", "SRX_0_CH1_CLK_CTRL"} register += {"SRX_0_CH1_STATUS", "SRX_0_CH1_CONFIG", "SRX_0_CH2_CLK_CTRL"} register += {"SRX_0_CH2_STATUS", "SRX_0_CH2_CONFIG", "SRX_0_CH3_CLK_CTRL"} register += {"SRX_0_CH3_STATUS", "SRX_0_CH3_CONFIG", "SRX_0_CH0_FMSG_DATA"} register += {"SRX_0_CH0_FMSG_CRC", "SRX_0_CH0_FMSG_TS", "SRX_0_CH0_SMSG_BIT3"} register += {"SRX_0_CH0_SMSG_BIT2", "SRX_0_CH0_SMSG_TS", "SRX_0_CH1_FMSG_DATA"} register += {"SRX_0_CH1_FMSG_CRC", "SRX_0_CH1_FMSG_TS", "SRX_0_CH1_SMSG_BIT3"} register += {"SRX_0_CH1_SMSG_BIT2", "SRX_0_CH1_SMSG_TS", "SRX_0_CH2_FMSG_DATA"} register += {"SRX_0_CH2_FMSG_CRC", "SRX_0_CH2_FMSG_TS", "SRX_0_CH2_SMSG_BIT3"} register += {"SRX_0_CH2_SMSG_BIT2", "SRX_0_CH2_SMSG_TS", "SRX_0_CH3_FMSG_DATA"} register += {"SRX_0_CH3_FMSG_CRC", "SRX_0_CH3_FMSG_TS", "SRX_0_CH3_SMSG_BIT3"} register += {"SRX_0_CH3_SMSG_BIT2", "SRX_0_CH3_SMSG_TS"} } SSCM { sn = "SSCM" ln = "SSCM" hk = "SSCM" collapse = true register += {"SSCM_STATUS", "SSCM_MEMCONFIG", "SSCM_ERROR", "SSCM_PSA", "SSCM_LCSTAT"} } STM_2 { sn = "STM_2" ln = "STM_2" hk = "STM_2" collapse = true register += {"STM_2_CR", "STM_2_CNT", "STM_2_CCR0", "STM_2_CIR0", "STM_2_CMP0", "STM_2_CCR1"} register += {"STM_2_CIR1", "STM_2_CMP1", "STM_2_CCR2", "STM_2_CIR2", "STM_2_CMP2"} register += {"STM_2_CCR3", "STM_2_CIR3", "STM_2_CMP3"} } SWT_2 { sn = "SWT_2" ln = "SWT_2" hk = "SWT_2" collapse = true register += {"SWT_2_CR", "SWT_2_IR", "SWT_2_TO", "SWT_2_WN", "SWT_2_SR", "SWT_2_CO"} register += {"SWT_2_SK"} } SWT_3 { sn = "SWT_3" ln = "SWT_3" hk = "SWT_3" collapse = true register += {"SWT_3_CR", "SWT_3_IR", "SWT_3_TO", "SWT_3_WN", "SWT_3_SR", "SWT_3_CO"} register += {"SWT_3_SK"} } WKPU { sn = "WKPU" ln = "WKPU" hk = "WKPU" collapse = true register += {"WKPU_NSR", "WKPU_NCR", "WKPU_WISR", "WKPU_IRER", "WKPU_WIREER", "WKPU_WIFEER"} } XBAR_0 { sn = "XBAR_0" ln = "XBAR_0" hk = "XBAR_0" collapse = true register += {"XBAR_0_PRS0", "XBAR_0_CRS0", "XBAR_0_PRS1", "XBAR_0_CRS1", "XBAR_0_PRS2"} register += {"XBAR_0_CRS2"} } XOSC { sn = "XOSC" ln = "XOSC" hk = "XOSC" collapse = true register += {"XOSC_CTL"} } eDMA_0 { sn = "eDMA_0" ln = "eDMA_0" hk = "eDMA_0" collapse = true register += {"eDMA_0_CR", "eDMA_0_ES", "eDMA_0_ERQL", "eDMA_0_EEIL", "eDMA_0_SERQ"} register += {"eDMA_0_CERQ", "eDMA_0_SEEI", "eDMA_0_CEEI", "eDMA_0_CINT", "eDMA_0_CERR"} register += {"eDMA_0_SSRT", "eDMA_0_CDNE", "eDMA_0_INTL", "eDMA_0_ERRL", "eDMA_0_HRSL"} register += {"eDMA_0_DCHPRI0", "eDMA_0_DCHPRI1", "eDMA_0_DCHPRI2", "eDMA_0_DCHPRI3"} register += {"eDMA_0_DCHPRI4", "eDMA_0_DCHPRI5", "eDMA_0_DCHPRI6", "eDMA_0_DCHPRI7"} register += {"eDMA_0_DCHPRI8", "eDMA_0_DCHPRI9", "eDMA_0_DCHPRI10", "eDMA_0_DCHPRI11"} register += {"eDMA_0_DCHPRI12", "eDMA_0_DCHPRI13", "eDMA_0_DCHPRI14", "eDMA_0_DCHPRI15"} register += {"eDMA_0_DCHMID0", "eDMA_0_DCHMID1", "eDMA_0_DCHMID2", "eDMA_0_DCHMID3"} register += {"eDMA_0_DCHMID4", "eDMA_0_DCHMID5", "eDMA_0_DCHMID6", "eDMA_0_DCHMID7"} register += {"eDMA_0_DCHMID8", "eDMA_0_DCHMID9", "eDMA_0_DCHMID10", "eDMA_0_DCHMID11"} register += {"eDMA_0_DCHMID12", "eDMA_0_DCHMID13", "eDMA_0_DCHMID14", "eDMA_0_DCHMID15"} register += {"eDMA_0_TCD0_SADDR", "eDMA_0_TCD0_ATTR", "eDMA_0_TCD0_SOFF"} register += {"eDMA_0_TCD0_NBYTES_MLNO", "eDMA_0_TCD0_NBYTES_MLOFFNO"} register += {"eDMA_0_TCD0_NBYTES_MLOFFYES", "eDMA_0_TCD0_SLAST", "eDMA_0_TCD0_DADDR"} register += {"eDMA_0_TCD0_CITER_ELINKYES", "eDMA_0_TCD0_CITER_ELINKNO", "eDMA_0_TCD0_DOFF"} register += {"eDMA_0_TCD0_DLASTSGA", "eDMA_0_TCD0_BITER_ELINKYES"} register += {"eDMA_0_TCD0_BITER_ELINKNO", "eDMA_0_TCD0_CSR", "eDMA_0_TCD1_SADDR"} register += {"eDMA_0_TCD1_ATTR", "eDMA_0_TCD1_SOFF", "eDMA_0_TCD1_NBYTES_MLNO"} register += {"eDMA_0_TCD1_NBYTES_MLOFFNO", "eDMA_0_TCD1_NBYTES_MLOFFYES"} register += {"eDMA_0_TCD1_SLAST", "eDMA_0_TCD1_DADDR", "eDMA_0_TCD1_CITER_ELINKYES"} register += {"eDMA_0_TCD1_CITER_ELINKNO", "eDMA_0_TCD1_DOFF", "eDMA_0_TCD1_DLASTSGA"} register += {"eDMA_0_TCD1_BITER_ELINKYES", "eDMA_0_TCD1_BITER_ELINKNO", "eDMA_0_TCD1_CSR"} register += {"eDMA_0_TCD2_SADDR", "eDMA_0_TCD2_ATTR", "eDMA_0_TCD2_SOFF"} register += {"eDMA_0_TCD2_NBYTES_MLNO", "eDMA_0_TCD2_NBYTES_MLOFFNO"} register += {"eDMA_0_TCD2_NBYTES_MLOFFYES", "eDMA_0_TCD2_SLAST", "eDMA_0_TCD2_DADDR"} register += {"eDMA_0_TCD2_CITER_ELINKYES", "eDMA_0_TCD2_CITER_ELINKNO", "eDMA_0_TCD2_DOFF"} register += {"eDMA_0_TCD2_DLASTSGA", "eDMA_0_TCD2_BITER_ELINKYES"} register += {"eDMA_0_TCD2_BITER_ELINKNO", "eDMA_0_TCD2_CSR", "eDMA_0_TCD3_SADDR"} register += {"eDMA_0_TCD3_ATTR", "eDMA_0_TCD3_SOFF", "eDMA_0_TCD3_NBYTES_MLNO"} register += {"eDMA_0_TCD3_NBYTES_MLOFFNO", "eDMA_0_TCD3_NBYTES_MLOFFYES"} register += {"eDMA_0_TCD3_SLAST", "eDMA_0_TCD3_DADDR", "eDMA_0_TCD3_CITER_ELINKYES"} register += {"eDMA_0_TCD3_CITER_ELINKNO", "eDMA_0_TCD3_DOFF", "eDMA_0_TCD3_DLASTSGA"} register += {"eDMA_0_TCD3_BITER_ELINKYES", "eDMA_0_TCD3_BITER_ELINKNO", "eDMA_0_TCD3_CSR"} register += {"eDMA_0_TCD4_SADDR", "eDMA_0_TCD4_ATTR", "eDMA_0_TCD4_SOFF"} register += {"eDMA_0_TCD4_NBYTES_MLNO", "eDMA_0_TCD4_NBYTES_MLOFFNO"} register += {"eDMA_0_TCD4_NBYTES_MLOFFYES", "eDMA_0_TCD4_SLAST", "eDMA_0_TCD4_DADDR"} register += {"eDMA_0_TCD4_CITER_ELINKYES", "eDMA_0_TCD4_CITER_ELINKNO", "eDMA_0_TCD4_DOFF"} register += {"eDMA_0_TCD4_DLASTSGA", "eDMA_0_TCD4_BITER_ELINKYES"} register += {"eDMA_0_TCD4_BITER_ELINKNO", "eDMA_0_TCD4_CSR", "eDMA_0_TCD5_SADDR"} register += {"eDMA_0_TCD5_ATTR", "eDMA_0_TCD5_SOFF", "eDMA_0_TCD5_NBYTES_MLNO"} register += {"eDMA_0_TCD5_NBYTES_MLOFFNO", "eDMA_0_TCD5_NBYTES_MLOFFYES"} register += {"eDMA_0_TCD5_SLAST", "eDMA_0_TCD5_DADDR", "eDMA_0_TCD5_CITER_ELINKYES"} register += {"eDMA_0_TCD5_CITER_ELINKNO", "eDMA_0_TCD5_DOFF", "eDMA_0_TCD5_DLASTSGA"} register += {"eDMA_0_TCD5_BITER_ELINKYES", "eDMA_0_TCD5_BITER_ELINKNO", "eDMA_0_TCD5_CSR"} register += {"eDMA_0_TCD6_SADDR", "eDMA_0_TCD6_ATTR", "eDMA_0_TCD6_SOFF"} register += {"eDMA_0_TCD6_NBYTES_MLNO", "eDMA_0_TCD6_NBYTES_MLOFFNO"} register += {"eDMA_0_TCD6_NBYTES_MLOFFYES", "eDMA_0_TCD6_SLAST", "eDMA_0_TCD6_DADDR"} register += {"eDMA_0_TCD6_CITER_ELINKYES", "eDMA_0_TCD6_CITER_ELINKNO", "eDMA_0_TCD6_DOFF"} register += {"eDMA_0_TCD6_DLASTSGA", "eDMA_0_TCD6_BITER_ELINKYES"} register += {"eDMA_0_TCD6_BITER_ELINKNO", "eDMA_0_TCD6_CSR", "eDMA_0_TCD7_SADDR"} register += {"eDMA_0_TCD7_ATTR", "eDMA_0_TCD7_SOFF", "eDMA_0_TCD7_NBYTES_MLNO"} register += {"eDMA_0_TCD7_NBYTES_MLOFFNO", "eDMA_0_TCD7_NBYTES_MLOFFYES"} register += {"eDMA_0_TCD7_SLAST", "eDMA_0_TCD7_DADDR", "eDMA_0_TCD7_CITER_ELINKYES"} register += {"eDMA_0_TCD7_CITER_ELINKNO", "eDMA_0_TCD7_DOFF", "eDMA_0_TCD7_DLASTSGA"} register += {"eDMA_0_TCD7_BITER_ELINKYES", "eDMA_0_TCD7_BITER_ELINKNO", "eDMA_0_TCD7_CSR"} register += {"eDMA_0_TCD8_SADDR", "eDMA_0_TCD8_ATTR", "eDMA_0_TCD8_SOFF"} register += {"eDMA_0_TCD8_NBYTES_MLNO", "eDMA_0_TCD8_NBYTES_MLOFFNO"} register += {"eDMA_0_TCD8_NBYTES_MLOFFYES", "eDMA_0_TCD8_SLAST", "eDMA_0_TCD8_DADDR"} register += {"eDMA_0_TCD8_CITER_ELINKYES", "eDMA_0_TCD8_CITER_ELINKNO", "eDMA_0_TCD8_DOFF"} register += {"eDMA_0_TCD8_DLASTSGA", "eDMA_0_TCD8_BITER_ELINKYES"} register += {"eDMA_0_TCD8_BITER_ELINKNO", "eDMA_0_TCD8_CSR", "eDMA_0_TCD9_SADDR"} register += {"eDMA_0_TCD9_ATTR", "eDMA_0_TCD9_SOFF", "eDMA_0_TCD9_NBYTES_MLNO"} register += {"eDMA_0_TCD9_NBYTES_MLOFFNO", "eDMA_0_TCD9_NBYTES_MLOFFYES"} register += {"eDMA_0_TCD9_SLAST", "eDMA_0_TCD9_DADDR", "eDMA_0_TCD9_CITER_ELINKYES"} register += {"eDMA_0_TCD9_CITER_ELINKNO", "eDMA_0_TCD9_DOFF", "eDMA_0_TCD9_DLASTSGA"} register += {"eDMA_0_TCD9_BITER_ELINKYES", "eDMA_0_TCD9_BITER_ELINKNO", "eDMA_0_TCD9_CSR"} register += {"eDMA_0_TCD10_SADDR", "eDMA_0_TCD10_ATTR", "eDMA_0_TCD10_SOFF"} register += {"eDMA_0_TCD10_NBYTES_MLNO", "eDMA_0_TCD10_NBYTES_MLOFFNO"} register += {"eDMA_0_TCD10_NBYTES_MLOFFYES", "eDMA_0_TCD10_SLAST", "eDMA_0_TCD10_DADDR"} register += {"eDMA_0_TCD10_CITER_ELINKYES", "eDMA_0_TCD10_CITER_ELINKNO"} register += {"eDMA_0_TCD10_DOFF", "eDMA_0_TCD10_DLASTSGA", "eDMA_0_TCD10_BITER_ELINKYES"} register += {"eDMA_0_TCD10_BITER_ELINKNO", "eDMA_0_TCD10_CSR", "eDMA_0_TCD11_SADDR"} register += {"eDMA_0_TCD11_ATTR", "eDMA_0_TCD11_SOFF", "eDMA_0_TCD11_NBYTES_MLNO"} register += {"eDMA_0_TCD11_NBYTES_MLOFFNO", "eDMA_0_TCD11_NBYTES_MLOFFYES"} register += {"eDMA_0_TCD11_SLAST", "eDMA_0_TCD11_DADDR", "eDMA_0_TCD11_CITER_ELINKYES"} register += {"eDMA_0_TCD11_CITER_ELINKNO", "eDMA_0_TCD11_DOFF", "eDMA_0_TCD11_DLASTSGA"} register += {"eDMA_0_TCD11_BITER_ELINKYES", "eDMA_0_TCD11_BITER_ELINKNO", "eDMA_0_TCD11_CSR"} register += {"eDMA_0_TCD12_SADDR", "eDMA_0_TCD12_ATTR", "eDMA_0_TCD12_SOFF"} register += {"eDMA_0_TCD12_NBYTES_MLNO", "eDMA_0_TCD12_NBYTES_MLOFFNO"} register += {"eDMA_0_TCD12_NBYTES_MLOFFYES", "eDMA_0_TCD12_SLAST", "eDMA_0_TCD12_DADDR"} register += {"eDMA_0_TCD12_CITER_ELINKYES", "eDMA_0_TCD12_CITER_ELINKNO"} register += {"eDMA_0_TCD12_DOFF", "eDMA_0_TCD12_DLASTSGA", "eDMA_0_TCD12_BITER_ELINKYES"} register += {"eDMA_0_TCD12_BITER_ELINKNO", "eDMA_0_TCD12_CSR", "eDMA_0_TCD13_SADDR"} register += {"eDMA_0_TCD13_ATTR", "eDMA_0_TCD13_SOFF", "eDMA_0_TCD13_NBYTES_MLNO"} register += {"eDMA_0_TCD13_NBYTES_MLOFFNO", "eDMA_0_TCD13_NBYTES_MLOFFYES"} register += {"eDMA_0_TCD13_SLAST", "eDMA_0_TCD13_DADDR", "eDMA_0_TCD13_CITER_ELINKYES"} register += {"eDMA_0_TCD13_CITER_ELINKNO", "eDMA_0_TCD13_DOFF", "eDMA_0_TCD13_DLASTSGA"} register += {"eDMA_0_TCD13_BITER_ELINKYES", "eDMA_0_TCD13_BITER_ELINKNO", "eDMA_0_TCD13_CSR"} register += {"eDMA_0_TCD14_SADDR", "eDMA_0_TCD14_ATTR", "eDMA_0_TCD14_SOFF"} register += {"eDMA_0_TCD14_NBYTES_MLNO", "eDMA_0_TCD14_NBYTES_MLOFFNO"} register += {"eDMA_0_TCD14_NBYTES_MLOFFYES", "eDMA_0_TCD14_SLAST", "eDMA_0_TCD14_DADDR"} register += {"eDMA_0_TCD14_CITER_ELINKYES", "eDMA_0_TCD14_CITER_ELINKNO"} register += {"eDMA_0_TCD14_DOFF", "eDMA_0_TCD14_DLASTSGA", "eDMA_0_TCD14_BITER_ELINKYES"} register += {"eDMA_0_TCD14_BITER_ELINKNO", "eDMA_0_TCD14_CSR", "eDMA_0_TCD15_SADDR"} register += {"eDMA_0_TCD15_ATTR", "eDMA_0_TCD15_SOFF", "eDMA_0_TCD15_NBYTES_MLNO"} register += {"eDMA_0_TCD15_NBYTES_MLOFFNO", "eDMA_0_TCD15_NBYTES_MLOFFYES"} register += {"eDMA_0_TCD15_SLAST", "eDMA_0_TCD15_DADDR", "eDMA_0_TCD15_CITER_ELINKYES"} register += {"eDMA_0_TCD15_CITER_ELINKNO", "eDMA_0_TCD15_DOFF", "eDMA_0_TCD15_DLASTSGA"} register += {"eDMA_0_TCD15_BITER_ELINKYES", "eDMA_0_TCD15_BITER_ELINKNO", "eDMA_0_TCD15_CSR"} } DMAMUX { sn = "DMAMUX" ln = "DMAMUX" hk = "DMAMUX" collapse = true group += {"DMAMUX_0", "DMAMUX_1"} } SWT { sn = "SWT" ln = "SWT" hk = "SWT" collapse = true group += {"SWT_2", "SWT_3"} } LINFlexD { sn = "LINFlexD" ln = "LINFlexD" hk = "LINFlexD" collapse = true group += {"LINFlexD_0", "LINFlexD_1", "LINFlexD_14"} } M_CAN { sn = "M_CAN" ln = "M_CAN" hk = "M_CAN" collapse = true group += {"M_CAN_1", "M_CAN_2"} } SARADC { sn = "SARADC" ln = "SARADC" hk = "SARADC" collapse = true group += {"SARADC_0", "SARADC_4"} } PIT { sn = "PIT" ln = "PIT" hk = "PIT" collapse = true group += {"PIT_0", "PIT_1"} } DSPI { sn = "DSPI" ln = "DSPI" hk = "DSPI" collapse = true group += {"DSPI_0", "DSPI_4"} } } group { 572L64 { ln = "572L64" desc = "572L64 Memory-mapped registers" hk = "572L64 Memory-mapped registers" top_level_index = 100 collapse = "false" group += {"CMU_PLL", "DECFILTER", "DMAMUX", "DSPI", "DTS", "eDMA_0", "EIM", "ERM", "FEC"} group += {"GTMINT", "INTC_0", "IRCOSC", "LFAST_0", "LINFlexD", "M_CAN", "MC_CGM", "MC_ME"} group += {"MC_PCU", "MC_RGM", "MP55", "PASS", "PBRIDGE_A", "PFLASH", "PIT", "PLLDIG"} group += {"PMCDIG", "PRAMC", "SARADC", "SARADC_B", "SDADC_3", "SIPI_0", "SIUL2", "SMPU_0"} group += {"SRX_0", "SSCM", "STM_2", "SWT", "WKPU", "XBAR_0", "XOSC"} } }