Cmsemicon BAT32G135 Cmsemicon BAT32G135 Device Family Pack http://www.mcu.com.cn/pack/ Add DataFlash Programming Algorithm Add VBGR A/D conversion value Change system_BAT32G135.c to compatible with AC5 and AC6 Change the name and address of TSCDR1 and TSCDR2 TSCDR1 --> TSN25, TSCDR2 --> TSN85 ¦ Change the Dvendor with Keil official assigned code Change the vendor from CMS to Cmsemicon Fix the function of PORT_SetBit and PORT_CLrBit modify the UART1_Stop function delete NVIC_EnableIRQ and add NVIC_ClearPendingIRQ Modify BAT32G135GE.FLM Add DMAIFx registers defination in BAT32G135.h Modify gpio.c and gpio.h Add spiNorFlash Example Modify the functions of sci.c and sci_user.c Add spi11MasterSendReceive, spi00SlaveSendReceive, spi11NorFlash Examples Add UID defination in SVD and BAT32G135.h SCKI00PCFG --> SCLKI00PCFG in SVD and BAT32G135.h SCKI20PCFG --> SCLKI20PCFG in SVD and BAT32G135.h Defination each function of UART0/SPI00/SPI01/IIC00/IIC01 Defination each function of UART1/SPI10/SPI11/IIC10/IIC11 Defination each function of UART2/SPI20/SPI21/IIC20/IIC21 Add selection of fIL as system clock in clk.c Initial Version Cmsemicon BAT32G135 The BAT32G135 device family contains an ARM Cortex-M0+ processor, running up to 64 MHz with a versatile set of on-chip peripherals. Code Flash: 64KB, Data Flash: 1.5KB, RAM: 8KB Package: 48-lead LQFP(7x7mm, 0.5mm pitch) Code Flash: 64KB, Data Flash: 1.5KB, RAM: 8KB Package: 40-lead QFN(5x5mm, 0.4mm pitch) Code Flash: 64KB, Data Flash: 1.5KB, RAM: 8KB Package: 32-lead LQFP(7x7mm, 0.8mm pitch) Sample project Cmsemicon BAT32G135 Series devices and CMSIS-CORE Startup assembler file for ARMCC Startup assembler file for GCC Startup assembler file for IAR System Startup for Cmsemicon BAT32G135 Series