J-Link/J-Trace User's Guide: J-Link/J-Trace User's Guide

Keil, An ARM® Company J-Link/J-Trace User's Guide

This document describes the Segger's J-Link and J-Trace debugger adapters and how they can be configured in µVision for debugging, tracing, and programming Flash on Cortex-M processor-based devices.

  • Introduction gives an overview of the requirements, adapter models, and features.
  • CoreSight Technology describes the debugging and tracing features of Cortex-M processor-based devices, and the connectors that support the features best.
  • Install J-Link/J-Trace Driver explains how to install the J-Link/J-Trace driver.
  • Configure µVision describes the configuration steps needed to use the adapter for downloading to Flash, for debugging, and for tracing.
  • Use J-Link/J-Trace describes downloading, debugging, and tracing steps, and explains how devices can be chained.
  • Configure Cortex-M Devices for Tracing describes how to configure µVision, J-Link/J-Trace, and devices to capture data.
  • µVision Windows describes the windows to view debug messages and variable values.

Revision History

August 2015:Options for Target - Debug - updated description for RESET methods.
  • February 2013:
    Trace Exceptions window updated.
    Event Counters window updated.
  • March 2010: Initial revision.

Copyright © Keil, An ARM Company. All rights reserved.


J-Link/J-Trace User's Guide: Atmel AT91SAM3 Devices

Atmel AT91SAM3 Devices

Atmel AT91SAM3 devices support all standard CoreSight features. ETM trace is not included. No additional target resources are needed for debugging. By default, AT91SAM3 devices debug in JTAG mode, and can be switched to Serial Wire mode. AT91SAM3 devices offer ITM and DWT trace data.

To use the CoreSight trace functionalities, the debugger adapter and connector, as well as µVision have to be configured properly:

  • Enable Serial Wire Trace

For additional information, refer to the AT91 ARM Cortex-M based Microcontrollers - SAM3U Series manual.


J-Link/J-Trace User's Guide: Enable Serial Wire Trace

Enable Serial Wire Trace

To enable Serial Wire Trace on Atmel AT91SAM3 devices:

  • Connect J-Link/J-Trace to the board's Cortex Debug connector and to the host computer.
  • Configure µVision to capture Serial Wire Trace data.

Configure µVision to capture Serial Wire Trace data

  1. Open the dialog Options for Target — Debug.

    Select the debugger adapter

  2. Enable Use, select Cortex-M/R J-LINK/J-Trace, and click Settings to open the Target Driver Setup dialog.

    Configure the Serial Wire Debug mode

  3. Select SW.
  4. Click the Trace tab.

    Configure Atmel SAM3x devices for Serial Wire Trace

  5. Set Enable, to start tracing.
  6. Set the Trace Port to Serial Wire Output - UART/NRZ and enable Autodetect max SWO Clk.
  7. The Core Clock must correspond to the device configuration.

Start the debugging session and verify the captured trace data with a µVision window.


J-Link/J-Trace User's Guide: Configure Cortex-M Devices for Tracing

Configure Cortex-M Devices for Tracing

The examples below explain how to configure µVision, the J-Link anadpter, and the target system for tracing:

  • Atmel AT91SAM3 Devices
  • Luminary LM3S Devices
  • NXP LPC17xx Devices
  • STMicroelectronics STM32F10xxx Devices
  • Toshiba TMPM330 Devices

Note

  • To control the trace output, refer to Trace Settings.
  • The device's data sheet or user manual provides information for the configuration.


J-Link/J-Trace User's Guide: Chain Devices

Chain Devices

Chaining devices, or target chaining, is the ability to connect more target systems to one JTAG bus and to a single debugger adapter. J-Link/J-Trace can reach chained devices, and program the Flash memory, debug, and trace each target individually.

Each device within the chain has to support:

  • BYPASSS register.
  • The IDCODE instruction must immediately follow a reset of the Test Access Port (TAP).
  • Bit 0 of ID Code must be 1.
  • In CAPTURE-IR state, the fixed value 1 must be loaded into the IR.

J-Link/J-Trace scans for the target IDCODE, device name, and IR length, and sets up the targets automatically. The scan results are shown in the JTAG Device Chain section of the Target Driver Setup dialog (Project — Options for Target — Debug — Settings).

To chain devices:

  • Connect the control signals in parallel (TMS and TCLK) .
  • Connect the data signals in series to form a bus (TDO to TDI).
  • A maximum of 8 chained devices are supported.


J-Link/J-Trace User's Guide: J-Link/J-Trace Adapter

J-Link/J-Trace Adapter

The J-Link/J-Trace Adapter section shows information about your debugger adapter. The debug port can be configured, the communication speed set, and information about the adapter are shown.

  • SN: — displays the identification number of the adapter. If more than one adapter is connected, you can choose the adapter from the drop-down list. The selected adapter will be used for all actions, including downloading, debugging, and tracing.
  • USB# — displays the USB port-number of the connected adapter. J-Link/J-Trace adapters are also identified through the USB port number, which rank from 0..3. The adapter can be allocated to another USB port through this drop-down list. Select a new number and follow the instructions on the screen.
  • Device, HW, FW, and dll — these fields show the driver version installed, the name, hardware, firmware, and dll version of the selected J-Link/J-Trace adapter.
  • Port: — sets the debug mode. You can switch between JTAG and Serial Wire (SW) mode. Serial Wire mode must be supported by both the debug adapter and the target device.
  • Max Clock: — sets the debug connection speed. If debugging is not working properly, manually reduce the JTAG or Serial Wire debugging speed here.
  • Auto Clk: — use this button to detect the supported maximum speed.

Some applications require to start with a lower JTAG Clock from RESET and have to switch to higher clock rates when debugging. Use the VTREG DEBUG_CLOCK to alter the clock rate from scripts.

/*-------------------------------------------------------------------------
  The function sets the JTAG Debug Clock to 2MHz
  after the Main Clock has been enabled and selected.
-------------------------------------------------------------------------*/
FUNC void setJTAGClock()  {
  enableMainClock();         // add your code to switch on the Main Clock

  DEBUG_CLOCK = 2000000;     // Set JTAG Debug Clock to 2MHz
  _sleep_(10);

  enableMainPLL();           // add your code to enable the main PLL
  _sleep_(100);
}


J-Link/J-Trace User's Guide: Debug

Debug

The Debug section controls the connect and reset behavior, cache options, and download options that are applied each time a debug session starts.

Target Driver Setup — Debug

The Connect & Reset Options controls how µVision establishes a connection to the target device.

The Connect selection controls what happens when the µVision debugger connects to the target device.

  • Normal — just stops the CPU at the currently executed instruction after connecting.
  • with Pre–reset — applies a hardware reset(HW RESET) before connecting to the device.
  • under Reset — holds the hardware reset(HW RESET) signal active while connecting to the device. You may use this option when the user program mistakenly disables the JTAG/SW interface.

Reset after Connect, if enabled, performs a reset operation as defined in the Reset drop-down list (see below), after connecting to the target. If disabled, the debugger just stops the CPU at the currently executed instruction after connecting.

The Reset selection controls the target device reset operation. All reset options apply to Cortex-M processor-based devices, are available in JTAG and SWD mode, and halt the CPU after the reset.

  • Normal — selects one of the reset methods based on the target device and might perform some special handling if necessary. For example, when devices have a ROM bootloader that needs to run after reset and before the user application is started. Specifically, if the debug interface is disabled after reset and needs to be enabled by the ROM bootloader.
  • Core - performs a reset of the Cortex-M core only by setting the VECTRESET bit. On—chip peripherals are not reset. For some Cortex—M devices, this reset method is the only way they may be reset. However, in most cases this method is not recommended, because most target applications rely of the reset state of some peripherals (PLL, External memory interface etc.) and may be confused if they boot up, but the peripherals are already configured.
  • ResetPin - J-Link pulls its RESET pin low to reset the core and peripherals. Normally, this causes the CPU RESET pin of the device to go low as well, resulting in a reset of the CPU and peripherals. This reset method will fail if the RESET pin of the target device is not pulled low.
  • Connect under Reset - connects to the target while keeping Reset active. This is the recommended method for STM32 devices, and has been designed for cases where communication with the core is not possible in normal mode.
  • Halt after Bootloader - selects one of the reset methods based on the target device, but (contrary to Normal) the bootloader is always executed. Use this method for MCUs/CPUs that have a bootloader located in ROM and which needs to run at first, after reset. When using this method, the bootloader runs after reset, the target is halted immediately after the bootloader and before the target application starts. This is the recommended reset strategy for LPC11xx and LPC13xx devices.
  • Halt before Bootloader - performs a reset of the core and peripherals, and halts the CPU immediately after reset. The ROM bootloader is NOT executed.
  • Kinetis - performs a reset via strategy Normal. Resets the core and peripherals, and halts the CPU immediately after reset. After the CPU halted, the watchdog is disabled, because the watchdog runs after reset by default. If the target application does not feed the watchdog, J-Link loses connection to the device.
  • ADI Halt after Kernel - performs a reset of the core and peripherals by setting the SYSRESETREQ bit. The core can perform the ADI kernel (which enables the debug interface), but is halted before the first instruction after kernel execution. This ensures that no user application code is performed after reset.
  • Core and Peripherals - J-Link tries to reset both, the core and peripherals by setting the SYSRESETREQ bit. VC_CORERESET in the DEMCR is also set to ensure sure that the CPU is halted immediately after reset and before executing any instruction.

    This type of reset may fail if:

    • J-Link has no connection to the debug interface of the CPU because it is in a low power mode.
    • The debug interface is disabled after reset and needs to be enabled by a device internal bootloader. This would cause J-Link to lose communication after reset since the CPU is halted before it can execute the internal bootlader.
  • LPC1200 — On NXP LPC1200 devices, the watchdog is enabled after reset and not disabled by the bootloader, if a valid application is in the flash memory. Moreover, the watchdog keeps counting if the CPU is in debug mode. When using this reset method, J-Link performs a reset of the CPU and peripherals, using the SYSRESETREQ bit and halts the CPU after the bootloader has been performed and before the first instruction of the user code is executed. Then, the watchdog of the LPC1200 device is disabled. This reset method is guaranteed to work only on "modern" J-Links (J-Link V8, J-Link Pro, J-link ULTRA, J-Trace for Cortex-M, J-Link Lite) and if a SWD speed of min. 1 MHz is used. It should also work for J-Links with hardware version 6, but it can not be guaranteed that these J-Links are always fast enough in disabling the watchdog.

The Cache Options improve the performance of the µVision Debugger during target debugging by caching target memory areas in the PC memory. By default, caching options are enabled to get maximum performance.

  • Cache Code — informs the debugger that the downloaded program code will not change. When this option is set, µVision never reads the program code from the target system. Disable this option if you are using self—modifying code or if you suspect that your program code is being overwritten.
  • Cache Memory — determines whether memory displays are updated during a program stop. When this option is set, the debugger does not update memory displays until the next single step, procedure step, or go command executes. Disable this option if you want to see the actual memory content (e.g. the data content of memory mapped peripherals) when the debugger is halted.

The Download Options control the downloading of code to the target system when the debugger starts.

  • Verify Code Download compares the content of the target memory with the application program loaded in the debugger for each new debug session. Enable this option to ensure program correlation between the image loaded in target system and the image loaded in the µVision debugger. This prevents debugging the wrong code when working with various targets or more instances of µVision.
  • Download to Flash — downloads code to all memory regions. When disabled, the debugger does not download code to the Memory Address Ranges defined under Flash Download Setup.


J-Link/J-Trace User's Guide: Device Chain

Device Chain

The section, JTAG Device Chain, SW Device respectively, shows the selected debugging devices found on the target hardware, their IDCODE, and, where possible, their IR length.

JTAG Device Chain

The connected device is marked with a dot and a circle. When debugging in JTAG mode, devices can be chained, and you can switch among those device.

Only one device can be connected in Serial Wire mode. Consequently, chaining is not supported in this mode.


J-Link/J-Trace User's Guide: Interface and TCP/IP

Interface and TCP/IP

Up to 4 devices can be connected concurrently through the USB interface. The adapter identification numbers are displayed in the Serial No drop-down list of the JLINK USB - JTAG/SW Adapter section.

USB - Interface

Click Scan whenever a new J-Link/J-Trace adapter has been connected.

State: shows the scan and connect progress.

TCP/IP Network Settings

TCP/IP offers LAN connection possibilities. Connect to a J-Link Pro, which has an Ethernet connector, or to the Segger TCP/IP Server, which offers Ethernet support for a J-Link that is connected via USB.

USB - Interface

When TCP/IP is selected, the driver does not scan for an IP address automatically. Enter the adapter's IP address manually, and click Connect. If the Port number is zero, the driver connects to the standard J-Link port.

Ping is enabled when TCP/IP is selected. Click this button to ping the IP-Address. The result is shown in an extra window.

Click Autodetect to display a list of available J-Link adapters. Double-click a line in that list to enable the adapter.

USB - Interface


J-Link/J-Trace User's Guide: Misc

Misc

The Misc section consists of two buttons.

Click J-Link Info to show information about the connected J-Link adapter, supported interfaces, or supported commands. An excerpt is shown below.

Click J-Link Cmd to start the J-Link Commander, which is a command line tool from Segger, and is delivered with the installation package of µVision.


J-Link/J-Trace User's Guide: Flash Download

Flash Download

To configure the J-Link/J-Trace adapter for Flash download:

  1. Choose Flash — Configure Flash Tools ... from the menu, to open the Project — Options for Target — Utilities dialog.

    Configure Flash Download

  2. Enable Use Target Driver for Flash Programming and select Cortex-M/R J-LINK/J-Trace.
  3. Optionally, enable Update Target before Debugging to program the Flash ROM whenever the debugger is started. The download is processed only when the binary was updated since the last Flash programming step (this feature is to avoid unnecessary reprogramming sequences).

    • When switching between µVision instances, use the explicit "Load" button to ensure that the image of the current target is downloaded to Flash.
    • When disabled and the application was not downloaded manually to Flash, you can enable the option Options for Target - Debug - Settings - Debug - Verify Code Download to ensure program correlation between the target system and the µVision debugger.
  4. Click Settings to open the Target Driver Setup dialog. Available configuration options are explained in Target Driver Settings section in µVision User's Guide.


J-Link/J-Trace User's Guide: Configure µVision

Configure µVision

A few steps are needed to configure µVision to work with J-Link/J-Trace adapters:

  1. Flash Download describes the options to configure the download to Flash memory.
  2. Debug Settings describes configuration options for debugging with a J-Link /J-Trace adapter.
  3. Trace Settings describes the settings needed to trace information with a J-Link/J-Trace adapter.

Notes

  • The J-Link/J-Trace has to be connected to the host and to the target system prior to start configuring µVision.


J-Link/J-Trace User's Guide: Connectors

Connectors

Several target connectors can be installed on the circuit board to access an ARM target system. You can physically plug in units, such as J-Link or J-Trace, to program, debug, and trace hardware systems.

The following units work in JTAG as well as in Serial Wire mode:

  • Cortex Debug Connector (10-pins, 0.05")
  • Cortex Debug+ETM Connector (20-pins, 0.05")
  • ARM Standard JTAG Connector (20-pins, 0.10")

Cortex Debug Connector (10-pins, 0.05")

This 10-pin Cortex Debug connector offers ITM and DWT trace information. Two pins (SWD) are used for debugging, where one bi-directional pin (SWDIO) is used to transfer the information and the second pin (SWDCLK) is used for the clock. A third pin (SWO) delivers the trace data at minimum system cost. The Serial Wire and JTAG pins are shared.

10-pin Cortex Debug Connector Pin Layout of 10-pin Cortex Debug Connector

Note

  • Position 7 has no pin and serves only as a key to properly orient the connector.
  • The 10-pin connector is a Samtec 10-pin: FTSH-105-01-L-DV-007-K connector. It's dimensions are: 0.25" x 0.188" (6.35mm x 4.78mm).

Cortex Debug+ETM Connector (20-pins, 0.05")

This connector offers debug features, ITM and DWT trace data, as well as ETM instruction trace. ETM signals are output on additional four pins (TRACEDATA). A fifth pin is used for the trace clock (TRACECLK). This way, ETM can be used in either SW or JTAG mode. This connector is a super set of the 10-pin Cortex Debug connector. The first 10 pins on both connectors are identical.

20-pin Cortex Debug+ETM Connector Pin Layout of Cortex Debug+ETM Connector

Note

  • Pin 7 is keyed and is removed from the connector.
  • The 20-pin connector is a Samtec 20-pin: FTSH-110-01-L-DV-007-K connector. It's dimensions are: 0.50" x 0.188" (12.70mm x 4.78mm).

ARM Standard JTAG Connector (20-pins, 0.10")

This JTAG connector delivers the same functionalities as the 10-pin Cortex Debug connector.

ARM Standard JTAG Connector

Note

  • The header (e.g. a Samtec TST-110-01-L-D) is a 20-Pin, 0.10" (2.54 mm) pitch connector with these these dimensions: 1.3" x 0.365" (33 mm x 9.27mm).


J-Link/J-Trace User's Guide: Debug Settings

Debug Settings

To configure the J-Link/J-Trace adapter for debugging:

  1. Target Options Open the Options for Target ... — Debug dialog of µVision.
  2. Enable Use and select Cortex-M/R J-LINK/J-Trace.

  3. Click Settings to open the Target Driver Setup dialog.

    Debug - Target Driver Setup

  4. Select SW (Serial Wire) for the debug Port, and click Auto Clk to set the debugging communication speed.

This screen consists of the following sections:

  • J-Link/J-Trace Adapter configures the debugging mode and speed.
  • Device Chain displays the device or device-chain detected.
  • Debug configures the device behavior during connect, reset, and download.
  • Interface and TCP/IP selects the J-Link/J-Trace connection port.
  • Misc offers buttons to extract information about the adapter, and to open the J-Link Commander.


J-Link/J-Trace User's Guide: Trace Settings

Trace Settings

To configure the J-Link/J-Trace adapter for tracing:

  1. Target Options Open the Options for Target ... — Debug dialog of µVision.
  2. Enable Use and select Cortex-M/R J-LINK/J-Trace.

  3. Click Settings to open the Target Driver Setup dialog, and choose the Trace tab.

    Trace - Target Driver Setup

  4. Set Enable. The Core Clock must correspond to the device configuration.
  5. Set Autodetect max SWO Clk.

The Trace Settings screen consists of the following sections:

  • General Settings determine the over all behavior while tracing data.
  • Trace Port defines the trace channel and tracing speed.
  • Instruction Trace enables program counters and ETM tracing.
  • Timestamps allows time information to be sent along with trace events.
  • Trace Events obtains information on specific CPU events.
  • ITM Stimulus Ports can steer debugging or program-specific information from the target device.
  • Quick Help shows hints when the mouse is hovered over the screen items.

Note

  • Some applications reset the CPU Core Clock in the startup code. When debugging such applications, stop the program execution before the clock rate gets configured, and modify Core Clock to match the new clock rate. Use the menu Debug — Debug Settings ... or assign the new value to the VTREG CORE_CLK.


J-Link/J-Trace User's Guide: CoreSight Technology

CoreSight Technology

CoreSight™ is an on-chip debugging and tracing technology designed by ARM. The device manufacturer can implement CoreSight features in various combinations.

CoreSight features can be accessed through a JTAG or Serial Wire interface. Debugging in JTAG and Serial Wire mode at the same time is not possible. Cortex-M processor-based devices can include a:

Debug Interface

The debug interface offers two modes:

  • JTAG Debug is the industry-standard interface that allows device chaining.
  • Serial Wire Debug is a 2-pin interface with an optional Serial Wire Trace Output. In contrast to JTAG, devices cannot be chained.

The Debug Interface communicates with the following units:

  • Run Control: allows to start, stop, and single-step through the source code.
  • Breakpoint Unit: allows to set breakpoints even while the processor is running.
  • Memory Access Unit: allows to read or write to memory and peripheral registers even while the program is running.

Trace Port Interface

The Trace Port Interface encodes and provides trace information via two possible interfaces:

  • The Serial Wire Trace Output pin (SWO) can be used in Serial Wire Debug mode only.
  • The 4-Pin Trace Output has a greater bandwidth than Serial Wire Trace Output and uses 5 functional pins. It is the only way to output ETM trace data.

The Trace Port Interface communicates with the following units:

  • Embedded Trace Macrocell (ETM): can be used for instruction tracing to debug historical sequences, for software profiling, and code coverage analysis. ETM data are output through an extra 4-bit interface.
  • Instrumentation Trace Macrocell (ITM): provides application information like debug printf, RTOS information, unit test, or UML annotation.
  • Data Watchpoint & Trace Unit (DWT): provides PC sampling, event counters, timing, and interrupt execution information. In addition, it allows access-breakpoints for up to four memory addresses.

Serial Wire-JTAG Switch (SWJ)

J-Link/J-Trace generate sequences to automatically switch between Serial Wire Debug and JTAG Debug mode.

Connectors

Two standard connectors are available:

  • 10-pin Cortex Debug for JTAG or Serial Wire Debug and Trace.
  • 20-pin Cortex Debug+ETM connector adds to the Cortex Debug connector ETM trace pins.

Note

  • Check the manufacturer's device data sheet to read which CoreSight features have been implemented.


J-Link/J-Trace User's Guide: Debug Target

Debug Target

After µVision and J-Link/J-Trace have been configured for debugging, and the program has been downloaded to Flash, start the debugging session.

  1. Click the Start/Stop Debug Session toolbar button.
  2. Use the run-control buttons of the toolbar to single-step through the code.

Note

  • Refer to the µVision User's Guide Debugging topic and the Getting Started User's Guide Start Debugging chapter for further details.


J-Link/J-Trace User's Guide: Download to Flash

Download to Flash

To program Flash memory on the target systems with J-Link/J-Trace adapters:

  1. Configure the Flash download behavior.
  2. Download to Flash Button Click the Download to Flash toolbar button to start downloading the program to Flash.

Monitor the download result in the Build Output window.

Target Download Status

The J-Link/J-Trace adapter can also be used to debug the application on target.


J-Link/J-Trace User's Guide: Install J-Link/J-Trace Driver

Install J-Link/J-Trace Driver

The J-Link/J-Trace driver, located in the folder ..\ARM\Segger of the Keil MDK-ARM, supports the J-Link/J-Trace adapters. When you connect the J-Link/J-Trace adapter for the first time, Windows will display the Found New Hardware wizard, which allows you to install the driver. You need Administrator rights to install the driver.

  1. Click I don't have the disk. Show me other options.

    J-Link Driver install

  2. Click Browse my computer for driver software (advanced).

    J-Link Driver install

  3. Enter ..\ARM\Segger\USBDriver and click Next.

  4. When installed successfully, a confirmation screen is displayed.

When installation issues arise, perform these steps:

  1. Open the Windows Device Manager (you may use devmgmt.msc in the command prompt).
  2. Expand Universal Serial Bus controllers. One devices should have the name J-Linkm driver. Where m is a number from 1 to 3; zero is not displayed.
  3. Right click the device name and select Update Driver Software...


J-Link/J-Trace User's Guide: Introduction

Introduction

With Segger's J-Link/J-Trace debugger adapters and the OEM Versions you can debug and trace applications on ARM7, ARM9, and Cortex-M processor-based devices. µVision runs with all J-Link/J-Trace adapters that are not IDE-dependent.

Minimum requirements to use J-Link/J-Trace are:

  • Keil MDK-ARM, version 4.10 or higher.
  • Segger J-Link driver for Windows.

Common features of J-Link/J-Trace are:

  • Examine memory and registers.
  • Programming Flash Memory.
  • Debugging in JTAG and Serial Wire mode.
  • Single-stepping through programs and inserting multiple breakpoints.
  • Supporting Segger's Flash Breakpoint feature, which allows more breakpoints than the hardware can actually handle.

Adapter specific features are listed below:

  • J-Link is a JTAG emulator that connects to the ARM standard JTAG 20-pin connector.
  • J-Link Pro is fully compatible to J-Link, and adds Ethernet connection possibilities.
  • J-Trace Cortex–M is fully compatible to J-Link, supports debugging and tracing on Cortex-M processor-based devices, and debugging on ARM7 and ARM9 processor-based devices. This adapter connects to the Cortex Debug+ETM 20-pin connector.
  • J-Trace is an emulator that supports the Embedded Trace Macrocell (ETM) for ARM7 and ARM9 processor-based devices.
 | J-Link | J-Link Pro | J-Trace Cortex-M | J-Trace
USB | yes | yes | yes | yes
Ethernet | no | yes | no | no
Supported Cores | Cortex-M ARM7, ARM9 | Cortex-M ARM7, ARM9 | Cortex-M ARM7, ARM9 - no tracing | ARM7, ARM9
JTAG | yes | yes | yes | yes
SWD | yes | yes | yes | no
SWO | yes | yes | yes | no
ETM Trace | no | no | yes | yes


J-Link/J-Trace User's Guide: Luminary LM3Sx Devices

Luminary LM3Sx Devices

Luminary Stellaris® LM3Sx devices support all standard CoreSight features. ETM trace is not included. No additional target resources are needed for debugging. By default, LM3Sx devices debug in JTAG mode, and can be switched to Serial Wire mode. LM3Sx devices offer ITM and DWT trace data.

To use the CoreSight trace functionalities, the debugger adapter and connector, as well as µVision have to be configured properly:

  • Enable Serial Wire Trace

For additional information, refer to the Stellaris data sheets.


J-Link/J-Trace User's Guide: Enable Serial Wire Trace

Enable Serial Wire Trace

To enable Serial Wire Trace on Luminary LM3Sx devices:

  • Connect J-Link/J-Trace to the board's Cortex Debug connector and to the host computer.
  • Configure µVision to capture Serial Wire Trace data.

Configure µVision to capture Serial Wire Trace data

  1. Open the dialog Options for Target — Debug.

    Select J-Link/J-Trace as the debugger adapter

  2. Enable Use, select Cortex-M/R J-LINK/J-Trace, and click Settings to open the Target Driver Setup dialog.

    Configure the Serial Wire Debug mode

  3. Select SW.
  4. Click the Trace tab.

    Configure Luminary devices for Serial Wire Trace

  5. Set Enable.
  6. Set the Trace Port to Serial Wire Output - UART/NRZ and enable Autodetect.
  7. The Core Clock must correspond to the device configuration.

Start the debugging session and verify the captured trace data with a µVision window.

Note

  • Use the examples delivered with the Luminary board ek-lm3s6965 as a reference.


J-Link/J-Trace User's Guide: NXP LPC17xx Devices

NXP LPC17xx Devices

NXP LPC17xx devices support all CoreSight features including ETM trace. No additional target resources are needed for debugging. By default, LPC17xx devices debug in JTAG mode, and can be switched to Serial Wire mode. LPC17xx devices offer ETM, ITM, and DWT trace data.

To use the CoreSight trace functionalities, the LPC17xx device, the debugger adapter and connector, as well as µVision have to be configured properly:

  • Enable 4-Pin Trace (ETM)
  • Enable Serial Wire Trace

Note

  • While debugging, the LPC17xx cannot wake up in the usual way from deep-sleep and power-down modes. Preferably avoid to use these modes during debugging.
  • Also, while debugging, the SYSTICK timer and the Repetitive Interrupt Timer (RIT) are stopped automatically whenever the CPU is stopped. Other peripherals are not affected.
  • If the Repetitive Interrupt Timers is configured such that its PLCK is lower than the CPU clock rate, it might not increment predictably during single-stepping operations.
  • Debugging is disabled when Code Read Protection (CRP) is enabled.


J-Link/J-Trace User's Guide: Enable 4-Pin Trace (ETM)

Enable 4-Pin Trace (ETM)

To enable CoreSight ETM tracing on NXP LPC17xx devices:

  • Connect J-Trace for Cortex to the board's Cortex Debug+ETM connector and to the host computer.
  • Enable the Trace Port Interface as described in the LPC17xx User Manual chapter LPC17xx Pin Connect Block.
  • Configure µVision to capture ETM trace data.

Enable the Trace Port Interface

  1. Create a text file, for example conf_LPC17xx.ini, and enter the following code:
    /*-------------------------------------------------------------------
** Define the function to enable the trace port
**-----------------------------------------------------------------*/
FUNC void EnableTPIU(void) {

  _WDWORD(0x4002C028, 0x00000008);         // Enable TPIU in PINSEL10
}

/*-------------------------------------------------------------------
** Invoke the function at debugger startup
**-----------------------------------------------------------------*/
EnableTPIU();

    ETM TRACEDATA[0..3] are output on the pins P2.5 through P2.2. The trace clock is configured on pin P2.6. PINSEL10.3 enables the trace functions for all trace pins P2.2 through P2.6. When PINSEL10.3 is set, it overwrites the configuration settings of PINSEL4 of the pin connect block.

    Use the _WDWORD command to configure the register, PINSEL10.3: _WDWORD(0x4002C028, 0x00000008);

  2. Open the dialog Options for Target — Debug, and insert conf_LPC17xx.ini into the Initialization File field.

    Enable trace on LPC17xx

Configure µVision to capture ETM trace data

  1. Enable Use, select Cortex-M/R J-LINK/J-Trace, and click Settings to open the Target Driver Setup dialog.

    Enable trace on LPC17xx

  2. Click the Trace tab.

    Options for ETM trace

  3. Set Enable and ETM Trace Enable.
  4. Set Trace Port to Sync Trace Port with 4-bit Data.
  5. The Core Clock must correspond to the device configuration.

Start the debugging session and verify the captured trace data with a µVision window.

Note

  • Use the examples delivered with the Keil board MCB1700 as a reference.
  • ETM tracing works in Serial Wire Debug as well as in JTAG Debug mode.


J-Link/J-Trace User's Guide: Enable Serial Wire Trace

Enable Serial Wire Trace

To enable Serial Wire Trace on an NXP LPC17xx device:

  • Connect the J-Link/J-Trace debugger adapter with the board's Cortex Debug connector and with the host computer.
  • Configure µVision to capture Serial Wire Trace data.

Configure µVision to capture Serial Wire Trace data

  1. Open the dialog Options for Target — Debug.

    Enable trace on LPC17xx

  2. Enable Use, select Cortex-M/R J-LINK/J-Trace, and click Settings to open the Target Driver Setup dialog.

    Configure LPC17xx for Serial Wire Trace

  3. Select SW.
  4. Click the Trace tab.

    Configure LPC17xx for Serial Wire Trace

  5. Set Enable.
  6. Under Trace Port set Serial Wire Output - UART/NRZ and enable Autodetect max SWO Clk.
  7. The Core Clock must correspond to the device configuration.

Start the debugging session and verify the captured trace data with a µVision window.

Note

  • Use the examples delivered with the Keil board MCB1700 as a reference.


J-Link/J-Trace User's Guide: OEM Versions

OEM Versions

All OEM versions of J-Link use basically identical hardware, but some are limited in speed, some can only be used with certain chips, and some have add-on features enabled. Support is provided by the respective OEM.

SEGGER J-Link Lite is a fully functional OEM version of Segger J-Link ARM, sold by SEGGER.
  • JTAG speed is limited to 4 MHz.
  • No licenses are included.
  • J-Link ARM Lite is only delivered and supported as part of Starter Kits.
mIDASLink is an OEM version of J-Link, sold by Analog Devices.
  • Works with Analog Devices devices only.
  • Licenses for RDI, J-Link ARM FlashDL, and FlashBP are included.
SAM–ICE is an OEM version of J-Link, sold by Atmel.
  • Works with Atmel devices only.
  • Licenses for RDI and GDB Server are included.
Digi JTAG Link is an OEM version of J-Link, sold by Digi International.
  • Works with Digi International devices only.
  • Licenses for GDB Server is included.
J-Link Lite LPC Edition is an OEM version of J-Link, sold by NXP.
  • Works with NXP devices only.
  • No licenses are included.

J-Link On Board

J-Link OBs (J-Link On Board) are single chip versions of J-Link used on various evaluation boards.


J-Link/J-Trace User's Guide: STMicroelectronics STM32F10xxx Devices

STMicroelectronics STM32F10xxx Devices

STMicroelectronics STM32F10xxx devices support all CoreSight features including ETM trace. No additional target resources are needed for debugging. By default, STM32F10xxx devices debug in JTAG mode, and can be switched to Serial Wire Debug mode. STM32F10xxx devices offer ETM, ITM, and DWT trace data.

To use CoreSight trace functionalities, the STM32F10xxx device, the debugger adapter and connector, as well as µVision have to be configured properly:

  • Enable 4-Pin Trace (ETM)
  • Enable Serial Wire Trace

Note

  • When debugging in low-power modes, configure the DBG_SLEEP or DBG_STOP bit of the DBGMCU_CR register first. Otherwise, the debug connection is lost.


J-Link/J-Trace User's Guide: Enable 4-Pin Trace (ETM)

Enable 4-Pin Trace (ETM)

To enable CoreSight ETM tracing on STMicroelectronics STM32F10xxx devices:

  • Connect J-Trace for Cortex to the board's Cortex Debug+ETM connector and to the host computer.
  • Enable the Trace Port Interface as described in the STM32F103xx Reference Manual chapter TRACE Pin Assignment.
  • Configure µVision to capture ETM trace data.

Enable the Trace Port Interface

  1. Create a text file, for example conf_STM32F10xxx.ini, and enter the following code:
    /*-------------------------------------------------------------------
** Define the function to enable the trace port
**-----------------------------------------------------------------*/
FUNC void EnableTPIU(void) {

  _WDWORD(0xE0042004, 0x000000E0);    // Set 4-pin tracing via DBGMCU_CR
}

/*-------------------------------------------------------------------
** Invoke the function at debugger startup
**-----------------------------------------------------------------*/
EnableTPIU();

    TRACED[0..3] are output on the pins PE3 through PE6. The trace clock, TRACECK, is configured on pin PE2. By default, these pins are not assigned and need to be configured using the TRACE_IOEN and TRACE_MODE bits of the DBGMCU_CR register.

    Use the _WDWORD command to configure the DBGMCU_CR register: _WDWORD(0xE0042004, 0x000000E0);

  2. Open the dialog Options for Target — Debug and insert conf_STM32F10xxx.ini into the Initialization File field.

    Configure the device for tracing

Configure µVision to capture ETM trace data

  1. Enable Use, select Cortex-M/R J-LINK/J-Trace, and click Settings to open the Target Driver Setup dialog.

    Select J-Link/J-Trace as the debugger adapter

  2. Click the Trace tab.

    Set ETM trace options

  3. Set Enable and ETM Trace Enable.
  4. Set Trace Port to Sync Trace Port with 4-bit Data.
  5. The Core Clock must correspond to the device configuration.

Start the debugging session and verify the captured trace data with a µVision window.

Note

  • Always synchronize the settings in the *.ini file with the settings in the Target Driver Setup - Trace Port dialog.
  • ETM tracing works in Serial Wire Debug as well as in JTAG Debug mode.
  • Use the examples delivered with the Keil board MCBSTM32E as a reference.


J-Link/J-Trace User's Guide: Enable Serial Wire Trace

Enable Serial Wire Trace

To enable Serial Wire Trace on STMicroelectronics STM32F10xxx devices:

  • Connect J-Link/J-Trace to the board's Cortex Debug connector and to the host computer.
  • Enable the Trace Port Interface as described in the STM32F103xx Reference Manual, chapters Pinout and Debug Port Pins and TRACE Pin Assignment.
  • Configure µVision to capture trace data.

Enable the Trace Port Interface

  1. Create a text file, for example conf_STM32F10xxx.ini, and enter the following code:
    /*-------------------------------------------------------------------
** Define the function to enable the trace port
**-----------------------------------------------------------------*/
FUNC void EnableTPIU(void) {

  _WDWORD(0xE0042004, 0x000000E0);    // Set 4-pin tracing via DBGMCU_CR
}

/*-------------------------------------------------------------------
** Invoke the function at debugger startup
**-----------------------------------------------------------------*/
EnableTPIU();

    Use the _WDWORD command to configure the TRACE_IOEN and TRACE_MODE bits of the DBGMCU_CR register:
    _WDWORD(0xE0042004, 0x00000020);

  2. Open the dialog Options for Target — Debug and insert conf_STM32F10xxx.ini into the Initialization File field.

    Configure the device for tracing

Configure µVision to capture Serial Wire Trace data

  1. Open the dialog Options for Target — Debug.

    Select J-Link/J-Trace as the debugger adapter

  2. Enable Use, select Cortex-M/R J-LINK/J-Trace , and click Settings to open the Target Driver Setup dialog.

    Configure the Serial Wire Debug mode

  3. Select SW.
  4. Click the Trace tab.

    Set the Serial Wire Trace options

  5. Set Enable.
  6. Set Trace Port to Serial Wire Output - UART/NRZ and enable Autodetect max SWO Clk.
  7. The Core Clock must correspond to the device configuration.

Start the debugging session and verify the captured trace data with a µVision window.

Note

  • Always synchronize the settings in the *.ini file with the settings in the Target Driver Setup - Trace Port dialog.
  • Use the examples delivered with the Keil board MCBSTM32E as a reference.


J-Link/J-Trace User's Guide: Toshiba TMPM330 Devices

Toshiba TMPM330 Devices

Toshiba TMPM330 devices support all CoreSight features including ETM trace. No additional target resources are needed for debugging. By default, TMPM330 devices debugged in JTAG mode, and can be switched to Serial Wire Debug mode. TMPM330 devices offer ETM, ITM, and DWT trace data.

To use the CoreSight trace functionalities, the TMPM330 device, the debugger adapter and connector, as well as µVision have to be configured properly:

  • Enable 4-Pin Trace (ETM)
  • Enable Serial Wire Trace

Note

  • Debug and trace operations are prohibited when the device's Security Function is enabled.
  • The watchdog timer stops in debug mode.
  • When PA0 and PB0 are configured as debug pins, output is enabled even in STOP mode, regardless of the SYSCR2<DRVE> or STBYCR2<DRVE> bit setting.
  • When PA1 is configured as a debug pin, low-power mode is not fully effective. Configure PA1 as a general-purpose port, if the debug function is not used.


J-Link/J-Trace User's Guide: Enable 4-Pin Trace (ETM)

Enable 4-Pin Trace (ETM)

To enable CoreSight ETM tracing on Toshiba TMPM330 devices:

  • Connect J-Trace for Cortex to the board's Cortex Debug+ETM connector and to the host computer.
  • Enable the Trace Port Interface as described in the manual 32-bit RISC Microprocessor - TMPM330 Family chapter Port A (PA0-PA7).
  • Configure µVision to capture ETM trace data.

Enable the Trace Port Interface

  1. Create a text file, for example conf_TMPM330.ini, and enter the following code:
    /*-------------------------------------------------------------------
** Define the function to enable the trace port
**-----------------------------------------------------------------*/
FUNC void EnableTPIU(void) {

  _WDWORD(0x40000008, 0x0000007F);     // Configure port A pins as trace output using PAFR1.
  _WDWORD(0x40000004, 0x0000007D);     // Enable output on port A using PACR.
}

/*-------------------------------------------------------------------
** Invoke the function at debugger startup
**-----------------------------------------------------------------*/
EnableTPIU();

    On TMPM330 devices, port A is used for debugging and tracing. RESET configures PA0 and PA1 as debug pins, and PA2 through PA7 as general-purpose port pins.

    ETM TRACEDATA[0..3] are output on the pins PA3 through PA6. The trace clock is configured on pin PA2. The Port Function Register, PAFR1, selects the port function, whereas the Port Control Register, PACR, enables port A pins as output or input pins. These pins have to be reprogrammed after each RESET.

    Use the _WDWORD command to configure the PAFR1 and PACR registers.

  2. Open the dialog Options for Target — Debug and insert conf_TMPM330.ini into the field Initialization File.

    Configure the device for tracing

Configure µVision to capture ETM trace data

  1. Enable Use, select Cortex-M/R J-LINK/J-Trace, and click Settings to open the Target Driver Setup dialog.

    Select J-Link/J-Trace as the debugger adapter

  2. Click the Trace tab.

    Options for ETM trace

  3. Set Enable and ETM Trace Enable.
  4. Set Trace Port to Sync Trace Port with 4-bit Data.
  5. The Core Clock must correspond to the device configuration.

Start the debugging session and verify the captured trace data with a µVision window.

Note

  • Use the examples delivered with the Keil board MCBTMPM330 as a reference.
  • ETM tracing works in Serial Wire Debug as well as in JTAG Debug mode.


J-Link/J-Trace User's Guide: Enable Serial Wire Trace

Enable Serial Wire Trace

To enable Serial Wire Trace on Toshiba TMPM330 devices:

  • Connect the J-Link/J-Trace debugger adapter with the board's Cortex Debug connector and with the host computer.
  • Configure µVision to capture Serial Wire Trace data as described in the manual 32-bit RISC Microprocessor - TMPM330 Family, chapters Port A (PA0-PA7), and Port B (PB0-PB7).

Configure µVision to capture Serial Wire Trace data

  1. Open the dialog Options for Target — Debug.

    Select J-Link/J-Trace as the debugger adapter

  2. Enable Use, select Cortex-M/R J-LINK/J-Trace , and click Settings open the Target Driver Setup dialog.

    Set the Serial Wire Trace options

  3. Select SW.
  4. Click the Trace tab.

    Configure the Serial Wire Debug mode

  5. Set Enable.
  6. Set the Trace Port to Serial Wire Output - UART/NRZ.
  7. Enable Autodetect max SWO Clk.
  8. The Core Clock must correspond to the device configuration.

Start the debugging session and verify the captured trace data with a µVision window.

Note

  • Use the examples delivered with the Keil board MCBTMPM330 as a reference.


J-Link/J-Trace User's Guide: Toshiba TMPM360 Devices

Toshiba TMPM360 Devices

Toshiba TMPM360 devices support all CoreSight features including ETM trace. No additional target resources are needed for debugging. By default, TMPM360 devices debug in Serial Wire mode. JTAG debug mode is not supported. TMPM360 devices offer ETM, ITM, and DWT trace data.

To use the CoreSight trace functionalities, the TMPM360 device, the debugger adapter and connector, as well as µVision have to be configured properly:

  • Enable 4-Pin Trace (ETM)
  • Enable Serial Wire Trace

Note

  • The debug interface pins can also be used as general-purpose ports (PF0-PF4). After reset, the pins are configured as general-purpose ports.


J-Link/J-Trace User's Guide: Enable 4-Pin Trace (ETM)

Enable 4-Pin Trace (ETM)

To enable CoreSight ETM tracing on Toshiba TMPM360 devices:

  • Connect J-Trace for Cortex to the board's Cortex Debug+ETM connector and to the host computer.
  • Enable the Trace Port Interface.
  • Configure µVision to capture ETM trace data.

Enable the Trace Port Interface

  1. Create a text file, for example TMPM360_TP.ini, and enter the following code:
    /*-------------------------------------------------------------------
** Define the function to enable the trace port
**-----------------------------------------------------------------*/
FUNC void EnableTPIU(void) {

  _WDWORD(0x400C0508, 0x1F);   // Configure Port F pins for tracing using PFFR1.
  _WDWORD(0x400C0504, 0x1F);   // Enable output on port F using PFCR.
}

/*-------------------------------------------------------------------
** Invoke the function at debugger startup
**-----------------------------------------------------------------*/
EnableTPIU();

    On TMPM360 devices, port F is used for tracing. After reset, the pins PF0-PF4 are set to general I/O ports.

    ETM TRACEDATA[0..3] are output on the pins PF1 through PF4. The trace clock is configured on pin PF0. The Port Function Register, PFFR1, selects the port function, whereas the Port Control Register, PFCR, enables port F pins as output or input pins. These pins have to be reprogrammed after each RESET.

    Use the _WDWORD command to configure the PFFR1 and PFCR registers.

  2. Open the dialog Options for Target — Debug and insert conf_TMPM360_TP.ini into the field Initialization File.

Configure µVision to capture ETM trace data

  1. Enable Use, select Cortex-M/R J-LINK/J-Trace, and click Settings to open the Target Driver Setup dialog.

    Select J-Link/J-Trace as the debugger adapter

  2. Click the Trace tab.
  3. Set Enable and ETM Trace Enable.
  4. Set Trace Port to Sync Trace Port with 4-bit Data.
  5. The Core Clock must correspond to the device configuration.

Start the debugging session and verify the captured trace data with a µVision window.

Note

  • Use the examples delivered with the Keil board MCBTMPM360 as a reference.


J-Link/J-Trace User's Guide: Enable Serial Wire Trace

Enable Serial Wire Trace

To enable Serial Wire Trace on Toshiba TMPM360 devices:

  • Connect J-Link/J-Trace to the board's Cortex Debug connector and to the host computer.
  • Enable the Serial Wire Trace Output Port.
  • Configure µVision to capture Serial Wire Trace data.

Enable the Serial Wire Trace Output Port

  1. Create a text file, for example TMPM360_SWV.ini, and enter the following code:
    /*-------------------------------------------------------------------
** Define the function to enable the trace port
**-----------------------------------------------------------------*/
FUNC void EnableTPIU(void) {

  _WDWORD(0x400C0508, 0x03);   // Configure Port F pins for tracing using PFFR1.
  _WDWORD(0x400C0504, 0x02);   // Enable output on port F using PFCR.
}

/*-------------------------------------------------------------------
** Invoke the function at debugger startup
**-----------------------------------------------------------------*/
EnableTPIU();

    On TMPM360 devices, port F is used for tracing. After reset, the pins PF0-PF4 are set to general I/O ports.

    The Serial Wire Trace Output pin is PF1 and has to be configureda after each reset. The trace clock on PF0 has to be enabled as well.The Port Function Register, PFFR1, selects the port function, whereas the Port Control Register, PFCR, enables port F pins as output or input pins. These pins have to be reprogrammed after each RESET.

    Use the _WDWORD command to configure the PFFR1 and PFCR registers.

  2. Open the dialog Options for Target — Debug and insert TMPM360_SWV.ini into the field Initialization File.

Configure µVision to capture Serial Wire Trace data

  1. Open the dialog Options for Target — Debug.

    Select J-Link/J-Trace as the debugger adapter

  2. Enable Use, select Cortex-M/R J-LINK/J-Trace , and click Settings open the Target Driver Setup dialog.

    Set the Serial Wire Trace options

  3. Select SW.
  4. Click the Trace tab.
  5. Set Enable.
  6. Set the Trace Port to Serial Wire Output - UART/NRZ.
  7. Enable Autodetect max SWO Clk.
  8. The Core Clock must correspond to the device configuration.

Start the debugging session and verify the captured trace data with a µVision window.

Note

  • Use the examples delivered with the Keil board MCBTMPM360 as a reference.


J-Link/J-Trace User's Guide: Event Counters Window

Event Counters Window

The Event Counters window displays cumulative numbers, which show how often an event triggered. Open this window through View - Trace - Event Counters.

To display data in this window:

  • Enable Tracing outside this window.
  • Enable the event counters in the window. (Is identical to setting the the option in Trace Events.)

Event Counters Window

Event counters are performance indicators and can be used as follows:

  • CPICNT : Cycles per Instruction: can be used to indicate Flash wait states. This counter increments on each additional cycle required to execute a multi-cycle instruction, except for those instructions recorded by LSUCNT. It does not count the first cycle required to execute any instruction. The counter also increments on each cycle of any instruction fetch stall.
  • EXCCNT : Exception Overhead: indicates exception frequency. The counter increments on each cycle associated with exception entry or return. That is, it counts the cycles associated with entry stacking, return unstacking, preemption, and other exception-related processes.
  • SLEEPCNT : Sleep Cycles: indicates the time spend in sleep mode. The counter increments on each cycle associated with power saving, whether initiated by a WFI or WFE instruction, or by the sleep-on-exit functionality.
  • LSUCNT : Load Store Unit Cycles: general indication of memory wait states. This counter increments on each additional cycle required to execute a multi-cycle load-store instruction. It does not count the first cycle required to execute any instruction.
  • FOLDCNT : Folded Instructions: indicates instructions that execute in zero cycles. For example, an IT instruction is folded and does not use any cycles.

Using the Window

  • Click Save to store the result in a comma-separated (*.csv) or tab-delimited (*.tab) file.
  • Click Clear to reset all counters.
  • Use the context menu for additional options.
  • Sort the rows by clicking the column header.
  • Hover the mouse over the counter name for name extensions.

Note

  • The values are accurate, provided there are no trace errors.
  • Counters that jump from higher to lower values indicate a trace error. Stop debugging and adjust the trace configuration or the trace speed. Refer to Trace Settings. The Status Bar displays additional information.


J-Link/J-Trace User's Guide: Trace Exceptions Window

Trace Exceptions Window

The Exception Trace window shows statistical data of the exceptions captured in the trace buffer. Open the window through View - Trace - Trace Exceptions.

To display data in this window:

  • Enable Tracing outside this window.
  • Enable EXCTRC: Exception Tracing. (Is identical to setting the option in Trace Events.)
  • Enable Timestamps Enable. (Is identical to setting the option in Timestamps.)

Exception Trace Records Window

The columns have the following meaning:

Exception Data | Description
Num | Exception Number (0..15 – Core Exceptions; 16.. – External Interrupts).
Name | Exception Name.
Count | Number of times an exception triggered.
Total Time | Total Time spent in this exception.
Min & Max Time In | Minimum and maximum time spent in this exception.
Min & Max Time Out | Minimum and maximum time spent out of this exception.
First Time | The time this exception triggered first.
Last Time | The time this exception triggered last.

Using the Window

  • Click Save to store the result in a comma-separated (*.csv) or tab-delimited (*.tab) file.
  • Click Clear to reset all counters.
  • Use the context menu for additional options.
  • Sort the rows by clicking the column header.
  • Hover the mouse over the counter name for name extensions.

Note

  • The Count, Total Time, and Min & Max Time In values do not include elapse times caused by higher priority interrupts interfering with lower priority interrupts. The time of the higher priority interrupt is accumulated in its own statistics.
  • Exception Tracing can cause huge traffic if the MCU runs high frequency interrupts. The Status Bar displays additional information.


J-Link/J-Trace User's Guide: Instruction Trace Window

Instruction Trace Window

The Instruction Trace window shows a history of executed instructions. Double-click a line in the Instruction Trace window to open the Disassembly window. Click the right mouse button to open a context menu.

Instruction Trace Window

The column names have the following meaning:

Column Name | Description
Nr. | A sequential number, assigned to each executed instruction.
Ovf | An X" indicates an overflow. This means that the previous trace record was lost, because the information could not be sent fast enough.
Address | The accessed memory address.
Opcode | The assembly language op-code in hex.
INT | The interrupt number that triggered.
Instruction | The assembly code.
Source Code | The high-level source code line.


J-Link/J-Trace User's Guide: Debug (printf) Viewer

Debug (printf) Viewer

The Debug (printf) Viewer window displays data streams that are transmitted sequentially through the ITM Stimulus Port 0. Enable ITM Stimulus Port 0.

Debug Viewer Window

To use the Debug (printf) Viewer for tracing:

  1. Add ITM Port register definitions to your source code.
    #define ITM_Port8(n)    (*((volatile unsigned char *)(0xE0000000+4*n)))
#define ITM_Port16(n)   (*((volatile unsigned short*)(0xE0000000+4*n)))
#define ITM_Port32(n)   (*((volatile unsigned long *)(0xE0000000+4*n)))

#define DEMCR           (*((volatile unsigned long *)(0xE000EDFC)))
#define TRCENA          0x01000000
  2. Add an fputc function to your source code that writes to the ITM Port 0 register. The fputc function enables printf to output messages.
    struct __FILE { int handle; /* Add whatever you need here */ };
FILE __stdout;
FILE __stdin;

int fputc(int ch, FILE *f) {
  if (DEMCR & TRCENA) {
    while (ITM_Port32(0) == 0);
    ITM_Port8(0) = ch;
  }
  return(ch);
}
  3. Add your debugging trace messages to your source code using printf.
    printf("AD value = 0x%04X\r\n", AD_value);
  4. Set the ITM Port 0 to capture the information. Clear the Port 7..0 privilege bit to access ITM Port 0 from User mode.

    ITM Stimulus Port 0

  5. Open the View - Serial Windows - Debug (printf) Viewer window.

Note

  • ITM Stimulus Ports can be monitored in the Instruction Trace Window, where ITM Port 0 is shown as well.
  • Consult Configure Cortex-M Target of the MDK-Primer for information on how to retarget the output.


J-Link/J-Trace User's Guide: Logic Analyzer Window

Logic Analyzer Window

The Logic Analyzer is a time-based graph that:

  • Shows maximum 4 variables when connected to the target. Watchpoints, also known as Access Breakpoints, reduce the number of variables that can be monitored.
  • Shows global and static variables only. Automatic variables inside a function are not shown. For details refer to Restrictions.
  • Expects a stable trace connection. Lost trace packets lead to incomplete data. Refer to Status Bar for information about trace errors.

To display variables in the Logic Analyzer:

  1. Enable Timestamps in the Target Driver Setup - Trace dialog, and select an appropriate Prescaler value to define the granularity of the timestamps.
  2. Drag and drop variables you want to watch to the Logic Analyzer.

Logic Analyzer Capture

Notes

  • Variables defined for the Logic Analyzer configure the trace options automatically, and invoke data read/write events for those variables. These events can be viewed in the Instruction Trace window.


J-Link/J-Trace User's Guide: Kernel Awareness

Kernel Awareness

Kernel awareness windows display information about the system state and threads.

The window Event Viewer shows the thread-switching history of an application on a time graph. Refer to Event Viewer in the µVision User's Guide for details.

The window System and Thread Viewer displays system state and threads. Refer to System and Thread Viewer in the µVision User's Guide for details.


J-Link/J-Trace User's Guide: Status Bar

Status Bar

The Status Bar displays error and trace messages whenever the trace functionality is active. Additional information is available in the general description of the Status Bar for CPUs that have enabled TrustZone for ARMv8-M.

Trace Status Bar

The trace status area:

  • Displays progress and error messages when the target processor is running.
  • Refreshes the Running... message every 3 seconds during error-free operations.
  • Is blank, when tracing is stopped without an error.
  • Displays the error message, when the target stopped with an error.
  • Keeps the error message displayed until tracing is restarted.

Trace Status Messages

Message | Description
Communication Error | An invalid communication has been detected. Incorrect clock settings or hardware problems can cause this message. See Note below.
HW Buffer Overrun | The USB port cannot accept data at the speed the adapter is sending them. Turn off trace events you do not need, or skip PC Sampling.
SW Buffer Overrun | Internal SW buffer overrun on the PC. Adjust the prescaler values or the clock settings for the trace port or debug port.
No Synchronization | Synchronization packets are not received from the target. The trace hardware is either not connected or configured improperly. Check the device data sheet. Additional help can be found in Configure Cortex-M Devices for Tracing.
Data Stream Error | Errors are detected in the Trace Data Stream.
Data Overflow | The Trace Port was too busy, and not all trace packets could be transmitted. This happens when too many trace data are captured. The Instruction Trace Window shows when the overflow occurred.
Running ... | The target and tracing are both running without errors.
<no message> | The target stopped without errors.

Note

  • Applications that change the Core Clock in the main() program may throw the Communication Error message, since trace data are captured incorrectly. This error message disappears once the Core Clock has been adjusted to the system settings.


J-Link/J-Trace User's Guide: Trace Information

Trace Information

To capture trace data with J-Link/J-Trace adapters:

  1. Configure the trace port.
  2. Start the debugging session and verify the captured data with a trace window.


J-Link/J-Trace User's Guide: Trace Events

Trace Events

Trace Events defines the events that are generated and captured while tracing. The window Event Counters shows the result.

CPI: Cycles per Instruction A general counter for instruction cycle count estimation. This counter increments on each additional cycle required to execute a multi-cycle instruction. The counter also increments on each cycle of any instruction fetch stall. The first cycle of an instruction and those recorded by the LSU are not counted.

EXC: Exception Overhead The counter increments on each cycle associated with exception entry or return. That is, it counts the cycles associated with entry stacking, return unstacking, preemption, and other exception-related processes.

SLEEP: Sleep Cycles The counter increments on each cycle associated with power saving, whether initiated by a WFI or WFE instruction, or by the sleep-on-exit functionality.

LSU: Load Store Unit Cycles This counter increments on each additional cycle required to execute a multi-cycle load-store instruction. It does not count the first cycle required to execute any instruction.

FOLD: Folded Instructions The counter increments on any instruction that executes in zero cycles (for example, an IT instruction is folded and does not use any cycles).

EXCTRC: Exception Tracing The counter increments on exceptions, interrupt entries, and interrupt exits. The window Trace Exceptions shows the statistics and the Event Viewer their execution over time.


J-Link/J-Trace User's Guide: General Settings

General Settings

Within the general section, tracing can be enabled, the core clock frequency can be adjusted, and the caching behavior defined.

General Target Settings
  • Enable defines whether tracing is turned on or off.
  • Core Clock has to correspond to the system settings, otherwise the captured data might not be valid.
  • Trace Cache Size reserves this RAM space on the host PC to store captured data temporarily.
  • Use Cache File ( max 1GB) extends the trace buffer and creates a file on the hard disk. If µVision stops, the data are flushed and shown in trace windows. If the 1GB limit is reached, the device is stopped and the trace must be cleared. Right-click in the Instruction Trace Window for a context menu.

Note

  • Some applications reset the CPU Core Clock in the startup code. When debugging such applications, stop the program execution before the clock rate gets configured, and modify Core Clock to match the new clock rate. Use the menu Debug — Debug Settings ... or assign the new value to the VTREG CORE_CLK.


J-Link/J-Trace User's Guide: Instruction Trace

Instruction Trace

This section defines the interval at which instrumentation trace data are generated.

Instruction Trace Settings

PC Sampling controls the sample generation.

Prescaler sets the interval value, with respect to the Core Clock, used to generate periodic PC Sampling.

Periodic enables sampling at regular intervals based on the Prescaler.

Period shows the actual period used for PC sampling. The value is calculated through the Prescaler.

on Data R/W Sample enables PC sampling for memory reads and writes.

ETM Trace enables instruction tracing through the Embedded Trace Macrocell module. This option can be used together with the Sync Trace Port with n-bit Data configuration only.


J-Link/J-Trace User's Guide: ITM Stimulus Ports

ITM Stimulus Ports

The ITM Stimulus Ports section controls access to the Instrumentation Trace Macrocell (ITM) Stimulus Ports.

ITM Stimulus Ports

The Enable check boxes enable or disable the ITM Stimulus Ports 0..31 individually.
Enable Port 0 to view the output of printf() in the Debug printf() Viewer window.
Enable Port 31 to view RTOS system tasks and events through the menu Debug — OS Support.

The Privilege check boxes set the access rights for ITM Stimulus Port groups. It can protect ports from being accessed through the user code. When unchecked, access to port groups in User Mode is not allowed. Nevertheless, ports are always accessible when in Privileged Mode.


J-Link/J-Trace User's Guide: Trace Port

Trace Port

The Trace Port section sets the port and the speed used for tracing.

Serial Wire Trace Output

Trace Port Options

Serial Wire Output – UART/NRZ sets the Serial Wire Trace Output pin (SWO) for tracing. When selecting this option, also set the debug Port to SW in the Debug - J-Link/J-Trace Adapter section.

SWO Settings define the communication speed when Serial Wire Output has been selected as the trace channel.

Prescaler defines the divider that is used to calculate the SWO Clock. Values, from 1 to 8192, can be entered when Autodetect max SWO Clk is unchecked.

Clock shows the communication frequency.

Autodetect max SWO Clk configures the prescaler automatically for the highest possible Clock frequency that J-Link/J-Trace supports.

Errors detected are displayed below Autodetect max SWO Clk.

Sync Trace Port

ETM Trace Port Options

Sync Trace Port with n-bit Data directs the debugger to accept Instruction Trace data in 1, 2, or 4-bit format. When ETM Trace is enabled, make sure these settings match the settings specified in the Initialization File. Consult Configure Cortex-M Devices for Tracing.

Note

  • You must choose one of the Sync Trace Port formats when using ETM.


J-Link/J-Trace User's Guide: Timestamps

Timestamps

The Timestamps section controls the global generation of timestamp information.

Enable set this control to append timestamp information to Trace packets. You have to enable this control to view signals in the Logic Analyzer.

Prescaler configures the timestamp interval and granularity with respect to the Core Clock.


J-Link/J-Trace User's Guide: Use J-Link/J-Trace

Use J-Link/J-Trace

After the J-Link/J-Trace driver has been installed and µVision configured:

  • Download to Flash shows how to download the program to Flash memory.
  • Debug Target shows debugging steps and controls.
  • Trace Information captures and shows messages from the target.
  • Chain Devices handles multiple devices in the debugging chain.


J-Link/J-Trace User's Guide: µVision Windows

µVision Windows

Captured trace data and information are displayed in µVision Windows:

  • Status Bar continuously displays status messages.
  • Logic Analyzer Window displays up to 4 global or static variables on a time-graph.
  • Kernel Awareness shows aspects of the RTX kernel and the application tasks.

Detailed trace information for Cortex-M3 and Cortex-M4 processor-based devices can be viewed using the following windows:

  • Debug (printf) Viewer shows debugging or program-specific information.
  • Instruction Trace Window monitors and logs the processor activity.
  • Trace Exceptions Window shows statistical data of the processor exceptions.
  • Event Counters Window shows counters of user-selectable events.

Note

  • Trace Settings explains trace output configuration options.
  • Configure Cortex-M Devices for Tracing explains how to configure individual devices.
  • Core Clock is vital for delivering correct and consistent data.