target jr
target t 1..8 rw ctigate 0xf
target gh 1..8
halt
target t 1..8 rw pstate                0xc8
target t 1..8 rw hcr_el2 0x0000000080000000
target t 1..8 rw fpcr            0x06000000

target rw sctlr_el2 0x00000000
target t 1..8 clop inval d * *
target t 1..8 clop inval i * *
target t 1..8 rw tlbi_alle2is 0
target t 1..8 rw tlbi_alle1is 0
target clop inval 2 * *

// Use the SRAM at 0x1d000000 to build a page table that maps 1GiB 1:1 at
// 0x40:00000000 and 4KiB at 0x1d003000
target mw 8 0x1d000000 0x000000001d001003
target mf 0x1d000008 0x7f8 0
target mw 8 0x1d000800 0x0000004000000661
target mf 0x1d000808 0xf38 0
target mw 8 0x1d001740 0x000000001d002003
target mf 0x1d001748 0x8d0 0
target mw 8 0x1d002018 0x000000001d003663
target mf 0x1d002020 0xfe0 0

// Set up a dummy vector table
target rw vbar_el1 0x1d003000
target rw vbar_el2 0x1d003000
target mf 0x1d003000 0x1000 0x14000000

target t 1..8 rw ttbr0_el2 0x1d000000
target t 1..8 rw tcr_el2   0x00020019
target t 1..8 rw mair_el2  0x000000ff
target t 1..8 rw sctlr_el2 0x30c51835