# The CPUID registers defined by ARMv7

enum {
    id_pfr0_state3 {
	"ThumbEE Not Implemented" { value = 0 }
	"ThumbEE Implemented"     { value = 1 }
    }
    id_pfr0_state2 {
	"Jazelle Not Implemented"                                { value = 0 }
	"Jazelle implemented; JOSCR.CV not cleared on exception" { value = 1 }
	"Jazelle implemented; JOSCR.CV cleared on exception"     { value = 2 }
    }
    id_pfr0_state1 {
	"Thumb instruction set not implemented" { value = 0 }
	"Thumb-1 implemented"                   { value = 1 }
	"Thumb-2 implemented"                   { value = 3 }
    }
    id_pfr0_state0 {
	"ARM Instruction Set not implemented" { value = 0 }
	"ARM Instruction Set implemented"     { value = 1 }
    }
}

bitfield {
    id_pfr0_bitfield {
	State0 { loc = "0..3";   type = "id_pfr0_state0" }
	State1 { loc = "4..7";   type = "id_pfr0_state1" }
	State2 { loc = "8..11";  type = "id_pfr0_state2" }
	State3 { loc = "12..15"; type = "id_pfr0_state3"}
    }
    id_pfr1_bitfield {
	GenericTimerExtension    { loc = "16..19" }
	VirtualizationExtensions { loc = "12..15" }
	M_profile                { loc = "8..11"  }
	SecurityExtensions       { loc = "4..7"   }
	ProgrammersModel         { loc = "0..3"   }
    }
    id_dfr0_bitfield {
	PerformanceMonitorExtension { loc = "24..27" }
	DebugModel_M                { loc = "20..23" }
	MemoryMappedTraceModel      { loc = "16..19" }
	CoprocessorTraceModel       { loc = "12..15" }
	MemoryMappedDebugModel      { loc = "8..11"  }
	CoprocessorSecureDebugModel { loc = "4..7"   }
	CoprocessorDebugModel       { loc = "0..3"   }
    }
    id_isar0_bitfield {
	Divide_instrs    { loc = "24..27" }
	Debug_instrs     { loc = "23..20" }
	Coproc_instrs    { loc = "16..19" }
	CmpBrnach_instrs { loc = "12..15" }
	Bitfield_intsrs  { loc = "8..11"  }
	BitCount_instrs  { loc = "4..7"   }
	Swap_instrs      { loc = "0..3"   }
    }
    id_isar1_bitfield {
	Jazelle_instrs   { loc = "28..31" }
	Interwork_instrs { loc = "24..27" }
	Immediate_instrs { loc = "20..23" }
	IfRThen_instrs   { loc = "16..19" }
	Extend_instrs    { loc = "12..15" }
	Except_AR_instrs { loc = "8..11"  }
	Except_intrs     { loc = "4..7"   }
	Endian_instrs    { loc = "0..3"   }
    }
    id_isar2_bitfield {
	Reversal_instrs       { loc = "23..31" }
	PSR_AR_instrs         { loc = "24..27" }
	MultU_instrs          { loc = "20..23" }
	MultS_instrs          { loc = "16..19" }
	Mult_instrs           { loc = "12..15" }
	MultiAccessInt_instrs { loc = "8..11"  }
	MemHint_instrs        { loc = "4..7"   }
	LoadStore_instrs      { loc = "0..3"   }
    }
    id_isar3_bitfield {
	ThumbEE_extn_instrs { loc = "31..28" }
	TrueNOP_instrs      { loc = "27..24" }
	ThumbCopy_instrs    { loc = "23..20" }
	TabBranch_instrs    { loc = "19..16" }
	SynchPrim_instrs    { loc = "15..12" }
	SVC_instrs          { loc = "11..8"  }
	SIMD_instrs         { loc = "7..4"   }
	Saturate_instrs     { loc = "3..0"   }
    }
    id_isar4_bitfield {
	SWP_frac              { loc = "31..28" }
	PSR_M_instrs          { loc = "27..24" }
	SynchPrim_instrs_frac { loc = "23..20" }
	Barrier_instrs        { loc = "19..16" }
	SMC_instrs            { loc = "15..12" }
	Writeback_instrs      { loc = "11..8"  }
	WithShifts_instrs     { loc = "7..4"   }
	Unpriv_instrs         { loc = "3..0"   }
    }
    id_isar5_bitfield {
	Reserved { loc = "0..31" }
    }
    id_mmfr0_bitfield {
	Innermost_shareability { loc = "31..28" }
	FCSE_support           { loc = "27..24" }
	Auxiliary_registers    { loc = "23..20" }
	TCM_support            { loc = "19..16" }
	Shareability_levels    { loc = "15..12" }
	Outermost_shareability { loc = "11..8"  }
	PMSA_support           { loc = "7..4"   }
	VMSA_support           { loc = "3..0"   }
    }
    id_mmfr1_bitfield {
	Branch_predictor         { loc = "31..28" }
	L1_unified_cache         { loc = "23..20" }
	L1_Harvard_cache         { loc = "19..16" }
	L1_unified_cache_set_way { loc = "15..12" }
	L1_Harvard_cache_set_way { loc = "11..8"  }
	L1_unified_cache_VA      { loc = "7..4"   }
	L1_Harvard_cache_VA      { loc = "3..0"   }
    }
    id_mmfr2_bitfield {
	HW_Access_flag      { loc = "31..28" }
	WFI_stall           { loc = "27..24" }
	Mem_barrier         { loc = "23..20" }
	Unified_TLB         { loc = "19..16" }
	Harvard_TLB         { loc = "15..12" }
	L1_Harvard_range    { loc = "11..8"  }
	L1_Harvard_bg_fetch { loc = "7..4"   }
	L1_Harvard_fg_fetch { loc = "3..0"   }
    }
    id_mmfr3_bitfield {
	Supersection_support { loc = "31..28" }
	Cached_memory_size { loc = "27..24" }
	Coherent_walk { loc = "23..20" }
	Maintenance_broadcast { loc = "15..12" }
	BP_maintain { loc = "11..8" }
	Cache_maintain_set_way { loc = "7..4" }
	Cache_maintain_MVA { loc = "3..0" }
    }
}

register {
    ID_PFR0  { address=699; type="id_pfr0_bitfield"  }
    ID_PFR1  { address=700; type="id_pfr1_bitfield"  }
    ID_DFR0  { address=701; type="id_dfr0_bitfield"  }
    ID_AFR0  { address=702                           }
    ID_MMFR0 { address=703; type="id_mmfr0_bitfield" }
    ID_MMFR1 { address=704; type="id_mmfr1_bitfield" }
    ID_MMFR2 { address=705; type="id_mmfr2_bitfield" }
    ID_MMFR3 { address=706; type="id_mmfr3_bitfield" }
    ID_ISAR0 { address=707; type="id_isar0_bitfield" }
    ID_ISAR1 { address=708; type="id_isar1_bitfield" }
    ID_ISAR2 { address=709; type="id_isar2_bitfield" }
    ID_ISAR3 { address=710; type="id_isar3_bitfield" }
    ID_ISAR4 { address=711; type="id_isar4_bitfield" }
    ID_ISAR5 { address=712; type="id_isar5_bitfield" }
}