# Core Module Registers for the ARM INTEGRATOR/AP
%include "os_constants.grd"

enum {
    "cm_id_arch" { "AHB interface, 64-bit SDRAM" {value = 0x1a}}
    "cm_id_fpga" { "XCV600 or XCV600E" {value = 0x3}}
    "cm_id_revision" { "Rev A" { value = 0 }; "Rev B" { value = 1 } }
    "cm_control_remap" {
	"boot ROM or flash" {
	    value = 0;
	    desc = "The boot ROM or flash on the motherboard is mapped into the address range 0x00000000. The SDRAM is accessible from 0x00100000"
	}
	"SSRAM" { value = 1; desc = "The SSRAM is mapped to the address range 0x00000000   (as one 1MB block)" }
    }
    "cm_control_detect" {
	"mounted on motherboard" { value = 0 }
	"standalone" {value = 1 }
    }
    "cm_control_led" { "OFF" { value = 0 }; "ON" {value = 1 }}
    "cm_control_ebi_wp" {
	"0" { value = 0; desc = "flash write protected" }
	"1" { value = 1; desc = "flash can be written to" }
    }
    "cm_control_lcd_biten" {
	"24bit" { value = 0; desc = "24bit VGA" }
	"18bit" { value = 1; desc = "18bit VGA" }
    }
    "cm_control_lcd_muxsel" {
	"Generic" {value = 1; desc = "Generic LCD connector, 24-bit mode" }
	"Sharp011" {value = 3; desc = "Sharp LCD panel" }
	"Sharp100" {value = 4; desc = "Sharp LCD panel" }
	"24bit" {value = 7; desc = "24-bit VGA" }
    }
    "cm_status_si_id" {
	"unknown or socket fitted" { value = 0 }
%if (_TARGET==ARM_926)
	"TI 1533C035.1" { value = 1; desc = "TI 1533C035.1 ARM926EJ-S r0p3 (1V5 core)" }
%elif (_TARGET==ARM_946 || _TARGET==ARM_966)
	"Lucent M-1291" { value = 1; desc = "Lucent M-1291 AM ARM966E-S r0 (3V3 core)" }
	"LSI L9A0225" { value = 2; desc = "LSI L9A0225 ARM966E-S r0 (2V5 core)" }
	"LSI L9A231" { value = 3; desc = "LSI L9A231 ARM966E-S r0 (1V8 core)" }
	"TI F741823/AX" { value = 4; desc = "TI F741823/AX ARM966E-S r0 (1V8 core)" }
	"LSI L9A267" { value = 5; desc = "LSI L9A267 ARM946E-S r0a (2V5 core)" }
	"NEC 14212901" { value = 6; desc = "NEC 14212901 ARM946E-S r1 (1V5 core)" }
%endif
    }
    "cm_status_ssramsize" { "1MB" { value = 0x10} }
    "cm_status_id" {
	"core module 0" { value = 0 }
	"core module 1" { value = 1 }
	"core module 2" { value = 2 }
	"core module 3" { value = 3 }
	"invalid or no motherboard attached" { value = 0xff }
    }
    "cm_lock_locked" { "unlocked" {value = 0}; "locked" {value = 1}}
    "cm_sdram_spdok" {
	"ready" { value = 1; desc = "SPD data ready" }
	"not available" { value = 0; desc = "SPD data not available" }
    }
    "cm_sdram_memsize" {
	"16MB" {value = 0}
	"32MB" {value = 1}
	"64MB" {value = 2}
	"128MB" {value = 3}
	"256MB" {value = 4}
    }
    "cm_sdram_caslat" {
	"2 cycles (default)" { value = 2 }
	"3 cycles" { value = 3 }
    }
}
	
bitfield {
    cm_id_bitfield {
        "MAN"  { loc = "24..31"; desc = "Manufacturer"; type = "manufacturer" }
        "ARCH"  { loc = "16..23"; desc = "Architecture"; type = "cm_id_arch" }
        "FPGA"  { loc = "12..15"; desc = "FPGA type"; type = "cm_id_fpga" }
        "BUILD"  { loc = "4..15"; desc = "Build value (FPGA build)" }
        "REV"  { loc = "0..3"; desc = "Revision"; type = "cm_id_revision" }
    }
    cm_oscillator_bitfield {
        "BMODE"  { loc = "23..24"; desc = "Bus mode: always b10" }
        "PLL_VDW"  { loc = "0..7"; desc = "Core clock VCO divider word: b01001000 = 80MHz (default)." }
    }
    cm_control_bitfield {
# the following are only for Integrator CP
%if (0)
#	"USR_LEDs" { loc = "24..31"; desc = "writing a 1 to a bit illuminates the associated LED" }
	"LED7" { loc = "31"; desc = "User LED"; type = "cm_control_led" }
	"LED6" { loc = "30"; desc = "User LED"; type = "cm_control_led" }
	"LED5" { loc = "29"; desc = "User LED"; type = "cm_control_led" }
	"LED4" { loc = "28"; desc = "User LED"; type = "cm_control_led" }
	"LED3" { loc = "27"; desc = "User LED"; type = "cm_control_led" }
	"LED2" { loc = "26"; desc = "User LED"; type = "cm_control_led" }
	"LED1" { loc = "25"; desc = "User LED"; type = "cm_control_led" }
	"LED0" { loc = "24"; desc = "User LED"; type = "cm_control_led" }
	"Reserved1" { sn = "Reserved"; loc = "21..23"; desc = "Reserved" }
	"EBI_WP" { loc = "20"; desc = "Write power signal to the core module user flash in EBI[1] and EBI[2]"; type = "cm_control_ebi_wp" }
#	"LCD" { sn = "LCD"; loc = "8..19"; desc = "LCD Control" }
	"n24BITEN" { loc = "19"; desc = "VGA depth. Must be 1 to enabled BIAS control"; type = "cm_control_lcd_biten" }
	"STATIC" { loc = "18"; desc = "No connection on Sharp panel" }
	"STATIC2" { loc = "17"; desc = "Up/down axis flip on Sharp panel" }
	"STATIC1" { loc = "16"; desc = "Right/left axis flip on Sharp panel" }
	"Enable LCD1" { sn = "LCD1"; loc = "15"; desc = "Enable, active high" }
	"Enable LCD0" { sn = "LCD0"; loc = "14"; desc = "Enable, active high" }
	"LCDMUXSEL" { sn = "MUXSEL"; loc = "11..13"; type = "cm_control_lcd_muxsel" }
	"LCDBIASDN" { sn = "BIASDN"; loc = "10"; desc = "Low to high transition decreases LCD bias voltage (dimmer)" }
	"LCDBIASUP" { sn = "BIASUP"; loc = "9"; desc = "Low to high transition increases LCD bias voltage (brighter)" }
	"LCDBIASEN" { sn = "BIASEN"; loc = "8"; desc = "Enable LCD bias supply" }
	"Reserved2" { sn = "Reserved"; loc = "4..7"; desc = "Reserved" }
%endif
# the following are for both Integrator AP and CP
	"RESET" { loc = "3"; desc = "reset the core module by writing a 1" }
	"REMAP" { loc = "2"; desc = "mapping of the boot ROM on the motherboard"; type = "cm_control_remap" }
	"nMBDET" { loc = "1"; desc = "core module detection"; type = "cm_control_detect" }
	"LED" { loc = "0"; desc = "MISC LED"; type = "cm_control_led" }
    }
    cm_status_bitfield {
        "SSRAMSIZE"  { loc = "16..23"; desc = "SSRAM size"; type = "cm_status_ssramsize" }
        "SI_ID"  { loc = "8..15"; desc = "Silicon manufacturer identification"; type = "cm_status_si_id" }
        "ID"  { loc = "0..7"; desc = "Card number in stack"; type = "cm_status_id" }
    }
    cm_lock_bitfield {
        "LOCKED"  { loc = "16..16"; desc = "CM_OSC/CM-INIT/CM_AUXOSC register"; type = "cm_lock_locked" }
        "LOCKVAL"  { loc = "0..15"; desc = "Write 0xa05f to unlock CM_OSC"; type="hex" }
    }
    cm_sdram_bitfield {
        "NBANKS"  { loc = "16..19"; desc = "Number of SDRAM banks. Must be set to the same value as byte 5 of SPD EEPROM."; type = "unsigned" }
        "NCOLS"  { loc = "12..15"; desc = "Number of SDRAM columns. Must be set to the same value as byte 4 of SPD EEPROM."; type="unsigned" }
        "NROWS"  { loc = "8..11"; desc = "Number of SDRAM rows. Must be set to the same value as byte 3 of SPD EEPROM."; type="unsigned" }
        "SPDOK"  { loc = "5..5"; desc = "automatic copying of the SPD data"; type="cm_sdram_spdok" }
        "MEMSIZE"  { loc = "2..4"; desc = "SDRAM size"; type="cm_sdram_memsize" }
        "CASLAT"  { loc = "0..1"; desc = "CAS latency"; type="cm_sdram_caslat" }
    }
    cm_voltage0_bitfield {
        "VDDCORE_DIFF1"  { loc = "20..31"; desc = "Value proportional to the current to VDDCORE1"}
        "VDDCORE"  { loc = "8..19"; desc = "Value proportional to the core voltage (voltage is measured before the sense resistors)"}
        "CoreDAC"  { loc = "0..7"; desc = "Positive or negative offset to the default power-on voltage ( is the default value)"}
    }
    cm_voltage1_bitfield {
        "VDDCORE_DIFF2"  { loc = "20..31"; desc = "Value proportional to the current to VDDCORE2"}
        "VDDIO"  { loc = "8..19"; desc = "Value proportional to the I/O voltage"}
        "Reserved"  { loc = "0..7"; desc = "Writes as 0. Reads undefined."}
    }
    cm_voltage2_bitfield {
        "VDDCORE_DIFF3"  { loc = "20..31"; desc = "Value proportional to the current to VDDCORE3"}
        "VDDLEVEL"  { loc = "8..19"; desc = "Value proportional to the logic-level voltage"}
        "Reserved"  { loc = "0..7"; desc = "Writes as 0. Reads undefined."}
    }
    cm_voltage3_bitfield {
        "VDDCORE_DIFF4"  { loc = "20..31"; desc = "Value proportional to the current to VDDCORE4"}
        "VDDPLL"  { loc = "8..19"; desc = "Value proportional to the I/O voltage"}
        "Reserved"  { loc = "0..7"; desc = "Writes as 0. Reads undefined."}
    }
}

%define CM_BASE 0x10000000
register {
    cm_id {
	sn = "id"; ln = "Core module ID register"
	access = "memorymapped"
	address = "${CM_BASE}"
	width = 32
	type = "cm_id_bitfield"
	permission = "write/none"
    }
    cm_processor {
	sn = "processor"; ln = "Core module processor register"
	access = "memorymapped"
	address = "${CM_BASE} + 0x4"
	width = 32
	permission = "write/none"
    }
    cm_oscillator {
	sn = "oscillator"; ln = "Core module oscillator register"
	access = "memorymapped"
	address = "${CM_BASE} + 0x8"
	width = 32
	type = "cm_oscillator_bitfield"
    }
    cm_control {
	sn = "control"; ln = "Core module control register"
	access = "memorymapped"
	address = "${CM_BASE} + 0xc"
	width = 32
	type = "cm_control_bitfield"
    }
    cm_status {
	sn = "status"; ln = "Core module status register"
	access = "memorymapped"
	address = "${CM_BASE} + 0x10"
	width = 32
	type = "cm_status_bitfield"
	permission = "write/none"
    }
    cm_lock {
	sn = "lock"; ln = "Core module lock register"
	access = "memorymapped"
	address = "${CM_BASE} + 0x14"
	width = 32
	type = "cm_lock_bitfield"
	cache_value = false;
    }
    cm_lmbuscnt {
	sn = "lmbuscnt"; ln = "Core module local memory bus cycle counter"
	access = "memorymapped"
	address = "${CM_BASE} + 0x18"
	width = 32
    }
    cm_aux_oscillator {
	sn = "auxosc"; ln = "Core module auxiliary oscillator register"
	access = "memorymapped"
	address = "${CM_BASE} + 0x1c"
	width = 32
    }
    cm_sdram {
	sn = "sdram"; ln = "SDRAM status and control register"
	access = "memorymapped"
	address = "${CM_BASE} + 0x20"
	width = 32
	type = "cm_sdram_bitfield"
    }
    cm_init {
	sn = "init"; ln = "Core module initialization register"
	access = "memorymapped"
	address = "${CM_BASE} + 0x24"
	width = 32
    }
    cm_refcnt {
	sn = "refcnt"; ln = "Core module reference clock cycle counter"
	access = "memorymapped"
	address = "${CM_BASE} + 0x28"
	width = 32
    }
    cm_flags {
	sn = "flags"; ln = "Core module flag register"
	access = "memorymapped"
	address = "${CM_BASE} + 0x30"
	width = 32
    }
    cm_flagss {
	sn = "flagss"; ln = "Core module flag set register"
	access = "memorymapped"
	address = "${CM_BASE} + 0x30"
	width = 32
    }
    cm_flagsc {
	sn = "flagsc"; ln = "Core module flag clear register"
	access = "memorymapped"
	address = "${CM_BASE} + 0x34"
	width = 32
    }
    cm_nvflags {
	sn = "nvflags"; ln = "Core module nonvolatile flag register"
	access = "memorymapped"
	address = "${CM_BASE} + 0x38"
	width = 32
    }
    cm_nvflagss {
	sn = "nvflagss"; ln = "Core module nonvolatile flag set register"
	access = "memorymapped"
	address = "${CM_BASE} + 0x38"
	width = 32
    }
    cm_nvflagsc {
	sn = "nvflagsc"; ln = "Core module nonvolatile flag clear register"
	access = "memorymapped"
	address = "${CM_BASE} + 0x3c"
	width = 32
    }
    cm_irq_stat {
	sn = "irq_stat"; ln = "Core module IRQ status register"
	access = "memorymapped"
	address = "${CM_BASE} + 0x40"
	width = 32
	permission = "write/none"
    }
    cm_irq_rstat {
	sn = "irq_rstat"; ln = "Core module IRQ raw status register"
	access = "memorymapped"
	address = "${CM_BASE} + 0x44"
	width = 32
	permission = "write/none"
    }
    cm_irq_enset {
	sn = "irq_enset"; ln = "Core module IRQ enable set register"
	access = "memorymapped"
	address = "${CM_BASE} + 0x48"
	width = 32
    }
    cm_irq_enclr {
	sn = "irq_enclr"; ln = "Core module IRQ enable clear register"
	access = "memorymapped"
	address = "${CM_BASE} + 0x4c"
	width = 32
    }
    cm_soft_intset {
	sn = "soft_intset"; ln = "Core module software interrupt set"
	access = "memorymapped"
	address = "${CM_BASE} + 0x50"
	width = 32
    }
    cm_soft_intclr {
	sn = "soft_intclr"; ln = "Core module software interrupt clear"
	access = "memorymapped"
	address = "${CM_BASE} + 0x54"
	width = 32
    }
    cm_fiq_stat {
	sn = "fiq_stat"; ln = "Core module FIQ status register"
	access = "memorymapped"
	address = "${CM_BASE} + 0x60"
	width = 32
	permission = "write/none"
    }
    cm_fiq_rstat {
	sn = "fiq_rstat"; ln = "Core module FIQ raw status register"
	access = "memorymapped"
	address = "${CM_BASE} + 0x64"
	width = 32
	permission = "write/none"
    }
    cm_fiq_enset {
	sn = "fiq_enset"; ln = "Core module FIQ enable set register"
	access = "memorymapped"
	address = "${CM_BASE} + 0x68"
	width = 32
    }
    cm_fiq_enclr {
	sn = "fiq_enclr"; ln = "Core module FIQ enable clear register"
	access = "memorymapped"
	address = "${CM_BASE} + 0x6c"
	width = 32
    }
    cm_voltage_ctl0 {
	sn = "voltage_ctl0"; ln = "Core module voltage-control register 0"
	access = "memorymapped"
	address = "${CM_BASE} + 0x80"
	width = 32
	type = "cm_voltage0_bitfield"
	permission = "write/none"
    }
    cm_voltage_ctl1 {
	sn = "voltage_ctl1"; ln = "Core module voltage-control register 1"
	access = "memorymapped"
	address = "${CM_BASE} + 0x84"
	width = 32
	type = "cm_voltage1_bitfield"
	permission = "write/none"
    }
    cm_voltage_ctl2 {
	sn = "voltage_ctl2"; ln = "Core module voltage-control register 2"
	access = "memorymapped"
	address = "${CM_BASE} + 0x88"
	width = 32
	type = "cm_voltage2_bitfield"
	permission = "write/none"
    }
    cm_voltage_ctl3 {
	sn = "voltage_ctl3"; ln = "Core module voltage-control register 3"
	access = "memorymapped"
	address = "${CM_BASE} + 0x8c"
	width = 32
	type = "cm_voltage3_bitfield"
    }
}

enum {
    "sc_id_arch" {
	"ASB little-endian" {value = 0x00}
	"AHB little-endian" {value = 0x01}
    }
    "sc_id_fpga" {
	"XC4062" {value = 1} #AP
	"XC4085" {value = 2} #AP
	"EPM7256AE" {value = 4} #CP
    }
    "sc_id_revision" { "Revision A" { value = 0 }; "Revision B" { value = 1 } }
    "sc_osc_div" { "33MHz (default)" { value = 0 }; "25MHz" { value = 1 } }
    "sc_ctrl_uart" { "HIGH (default)" { value = 0 }; "LOW" { value = 1 } }
    "sc_ctrl_wp" { "protected (default)" { value = 0 }; "unprotected" { value = 1 } }
    "sc_ctrl_vpp" { "disabled (default)" { value = 0 }; "enabled" { value = 1 } }
    "sc_dec_module" {
	"no modules fitted" { value = 0 }
	"module 0 fitted" { value = 1 }
	"module 1 and 0 fitted" { value = 3 }
	"module 2, 1 and 0 fitted" { value = 7 }
	"module 3, 2, 1, and 0 fitted" { value = 15 }
    }
    "sc_pci_en" { "disabled (default)" { value = 0 }; "enabled" { value = 1 } }
    "sc_lock" { "unlocked" { value = 0 }; "locked" { value = 1 } }
    "sc_lbf_dir" {
	"data in, PCI (or V3 DMA) write to AMBA" { value = 0 }
	"data out, AMBA write to PCI" { value = 1 }
	"data out, PCI (or V3 DMA) read from AMBA" { value = 2 }
	"data in, AMBA read from PCI" { value = 3 }
    }
}

bitfield {
    sc_id_bitfield {
        "MAN"  { loc = "24..31"; desc = "Manufacturer"; type = "manufacturer" }
        "ARCH"  { loc = "16..23"; desc = "Architecture"; type = "sc_id_arch" }
        "FPGA"  { loc = "12..15"; desc = "System controller FPGA type"; type = "sc_id_fpga" }
        "BUILD"  { loc = "4..15"; desc = "Build value" }
        "REV"  { loc = "0..3"; desc = "Revision"; type = "sc_id_revision" }
    }
    sc_osc_bitfield {
	"DIVX/Y" { loc = "8..8"; desc = "Frequency of the PCI bus clock signal CP_CLK."; type = "sc_osc_div" }
	"S_VDW" { loc = "0..7"; desc = "Frequncy of the system bug clock signal SYSCLK.\nThey control the value of the lower 8 VCO divider bits within the clock generator chip.\nThe range of values is 4-192 (giving 3-50MHz in 0.25Mz steps)"; type = "unsigned" }
    }
    sc_ctrl_bitfield {
	"UART1DTR" { loc = "7..7"; desc = "Controls the UART1 DTR line (active LOW)"; type = "sc_ctrl_uart" }
	"UART1RTS" { loc = "6..6"; desc = "Controls the UART1 RTS line (active LOW)"; type = "sc_ctrl_uart" }
	"UART0DTR" { loc = "5..5"; desc = "Controls the UART0 DTR line (active LOW)"; type = "sc_ctrl_uart" }
	"UART0RTS" { loc = "4..4"; desc = "Controls the UART0 RTS line (active LOW)"; type = "sc_ctrl_uart" }
	"RSVD" { loc = "3..3"; desc = "Reserved" }
	"FLASHWP" { loc = "2..2"; desc = "Flash write-protection"; type = "sc_ctrl_wp" }
	"FLASHVPP" { loc = "1..1"; desc = "Flash Vpp enable"; type = "sc_ctrl_vpp" }
	"SOFTRESET" { loc = "0..0"; desc = "Software reset.\nA 1 written to this bit resets the system."}
    }
    sc_dec_bitfield {
	"EPRES" { loc = "4..7"; desc = "Module present on EXP connectors"; type = "sc_dec_module" }
	"PPRES" { loc = "0..3"; desc = "Module present on HDR connectors"; type = "sc_dec_module" }
    }
    sc_arb_bitfield {
	"CCOUNT" { loc = "8..19"; desc = "Cycle counter load value (default 0x000)" }
	"RSVD" { loc = "5..7"; desc = "Reserved" }
	"TCOUNT" { loc = "0..4"; desc = "Transaction counter load value (default 0x08)" }
    }
    sc_pci_bitfield {
    	"PCILBINT_CLR" { loc = "1..1"; desc = "Clear PCILBINT: Always reads 0; Write 1 to clear an interrupt" }
	"PCIEN" { loc = "0..0"; desc = "PCI interface enable"; type = "sc_pci_en" }
    }
    sc_lock_bitfield {
	"LOCKED" { loc = "16..16"; desc = "SC_OSC register lock bit"; type = "sc_lock" }
	"KEY" { loc = "0..15"; desc = "Lock key. Write 0xA05F to unlock SC_OSC register; Write any other value to lock."; type = "hex" }
    }
    sc_lbf_bitfield {
	"BEN3" { loc = "7..7"; desc = "Byte enable 3. Indicates that data bits 31:24 were being accessed." }
	"BEN2" { loc = "6..6"; desc = "Byte enable 2. Indicates that data bits 23:16 were being accessed." }
	"BEN1" { loc = "5..5"; desc = "Byte enable 1. Indicates that data bits 15:8 were being accessed." }
	"BEN0" { loc = "4..4"; desc = "Byte enable 0. Indicates that data bits 7:0 were being accessed." }
	"LBURST" { loc = "3..3"; desc = "Burst was in progress." }
	"LREAD/MASTER" { loc = "1..2"; desc = "Direction of transfer as viewed by the current master."; type = "sc_lbf_dir" }
	"RLBFINT" { loc = "0..0"; desc = "Raw PCI local bus fault interrupt status." }
    }
    
    
}

%define SC_BASE 0x11000000
register {
    SC_ID { sn = "ID"; ln = "System controller identification";
	access = "memorymapped"
	address = "${SC_BASE}"; type = "sc_id_bitfield"
	permission = "write/none"
    }
    SC_OSC { sn = "OSC"; ln = "Oscillator divisors";
	access = "memorymapped"
	address = "${SC_BASE} + 0x4"; type = "sc_osc_bitfield"
    }
    SC_CTRLS { sn = "CTRLS"; ln = "Control register set";
	access = "memorymapped"; width = 8
	address = "${SC_BASE} + 0x8"; type = "sc_ctrl_bitfield"
    }
    SC_CTRLC { sn = "CTRLC"; ln = "Control register clear";
	access = "memorymapped"; width = 8
	address = "${SC_BASE} + 0xC"; type = "sc_ctrl_bitfield"
    }
    SC_DEC { sn = "DEC"; ln = "Decoder status";
	access = "memorymapped"; width = 8
	address = "${SC_BASE} + 0x10"; type = "sc_dec_bitfield"
	permission = "write/none"
    }
    SC_ARB { sn = "ARB"; ln = "Arbiter time-out values";
	access = "memorymapped"
	address = "${SC_BASE} + 0x14"; type = "sc_arb_bitfield"
    }
    SC_PCI { sn = "PCI"; ln = "PCI control";
	access = "memorymapped"
	address = "${SC_BASE} + 0x18"; type = "sc_pci_bitfield"
    }
    SC_LOCK { sn = "LOCK"; ln = "Lock";
	access = "memorymapped"
	address = "${SC_BASE} + 0x1C"; type = "sc_lock_bitfield"
	cache_value = false;
    }
    SC_LBFADDR { sn = "LBFADDR"; ln = "PCI local bus fault address";
	access = "memorymapped"
	address = "${SC_BASE} + 0x20"
    }
    SC_LBFCODE { sn = "LBFCODE"; ln = "PCI local bus fault code";
	access = "memorymapped"
	address = "${SC_BASE} + 0x24"; type = "sc_lbf_bitfield"
    }
    SC_FLAGS { sn = "FLAGS"; ln = "Flag register";
	access = "memorymapped"
	address = "${SC_BASE} + 0x30"
    }
    SC_FLAGSET { sn = "FLAGSET"; ln = "Flag set register";
	access = "memorymapped"
	address = "${SC_BASE} + 0x30"
    }
    SC_FLAGSCLR { sn = "FLAGSCLR"; ln = "Flag clear register";
	access = "memorymapped"
	address = "${SC_BASE} + 0x34"
    }
    SC_NVFLAGS { sn = "NVFLAGS"; ln = "Nonvolatile flag register";
	access = "memorymapped"
	address = "${SC_BASE} + 0x38"
    }
    SC_NVFLAGSET { sn = "NVFLAGSET"; ln = "Nonvolatile flag set register";
	access = "memorymapped"
	address = "${SC_BASE} + 0x38"
    }
    SC_NVFLAGSCLR { sn = "NVFLAGSCLR"; ln = "Nonvolatile flag clear register";
	access = "memorymapped"
	address = "${SC_BASE} + 0x3C"
    }
}

enum {
    "ebi_wait" {
	"0 cycles" {value = 0x0}
	"1 cycles" {value = 0x1}
	"2 cycles" {value = 0x2}
	"3 cycles" {value = 0x3}
	"4 cycles" {value = 0x4}
	"5 cycles" {value = 0x5}
	"6 cycles" {value = 0x6}
	"7 cycles" {value = 0x7}
	"8 cycles" {value = 0x8}
	"9 cycles" {value = 0x9}
	"10 cycles" {value = 0xA}
	"11 cycles" {value = 0xB}
	"12 cycles" {value = 0xC}
	"13 cycles" {value = 0xD}
	"13 cycles" {value = 0xE}
	"13 cycles" {value = 0xF}
    }
    "ebi_ssram" { "asynchronous memory" { value = 0 }; "synchronous memory" { value = 1 } }
    "ebi_wren" { "writes disabled" { value = 0 }; "writes enabled" { value = 1 } }
    "ebi_memsize" {
	"8 bit" { value = 0 }
	"16 bit" { value = 1 }
	"32 bit" { value = 2 }
	"reserved" { value = 3 }
    }
    "ebi_lock" { "unlocked" { value = 0 }; "locked" { value = 1 } }
}

bitfield {
    ebi_bitfield {
        "WAIT"  { loc = "4..7"; desc = "Wait states"; type = "ebi_wait" }
        "SSRAM"  { loc = "3..3"; desc = "Synchronous SRAM"; type = "ebi_ssram" }
        "WREN"  { loc = "2..2"; desc = "Write enable"; type = "ebi_wren" }
        "MEMSIZE"  { loc = "0..1"; desc = "Memory size"; type = "ebi_memsize" }
    }
    ebi_lock_bitfield {
	"LOCKED" { loc = "16..16"; desc = "EBI_CSRx registers lock bit"; type = "ebi_lock" }
	"KEY" { loc = "0..15"; desc = "Lock key. Write 0xA05F to unlock EBI_CSRx registers; Write any other value to lock."; type = "hex" }
    }
}

%define EBI_BASE 0x12000000
register {
    EBI_CSR0 { sn = "CSR0"; ln = "Chip select 0 configuration (boot ROM)";
	access = "memorymapped"; width = 8
	address = "${EBI_BASE}"; type = "ebi_bitfield"
    }
    EBI_CSR1 { sn = "CSR1"; ln = "Chip select 1 configuration (flash)";
	access = "memorymapped"; width = 8
	address = "${EBI_BASE} + 0x4"; type = "ebi_bitfield"
    }
    EBI_CSR2 { sn = "CSR2"; ln = "Chip select 2 configuration (SSRAM)";
	access = "memorymapped"; width = 8
	address = "${EBI_BASE} + 0x8"; type = "ebi_bitfield"
    }
    EBI_CSR3 { sn = "CSR3"; ln = "Chip select 3 configuration (EXPM)";
	access = "memorymapped"; width = 8
	address = "${EBI_BASE} + 0xC"; type = "ebi_bitfield"
    }
    EBI_LOCK { sn = "LOCK"; ln = "EBI lock register";
	access = "memorymapped"
	address = "${EBI_BASE} + 0x20"; type = "ebi_lock_bitfield"
	cache_value = false;
    }
}


enum {
    "timer_enable" { "disabled" { value = 0 }; "enabled" { value = 1 } }
    "timer_mode" {
	"free running" { value = 0; desc = "counts once and then wraps to 0xFFFF" }
	"periodic" { value = 1; desc = "reloads from load register at the end of each count" }
    }
    "timer_divisor" { "none" { value = 0 }; "divide by 16" { value = 1 }; "divide by 256" { value = 2 }; "undefined" { value = 3 } }
}

bitfield {
    timer_ctrl_bitfield {
        "ENABLE"  { loc = "7..7"; desc = "Timer enable"; type = "timer_enable" }
        "MODE"  { loc = "6..6"; desc = "Timer mode"; type = "timer_mode" }
        "Unused1"  { sn = "Unused"; loc = "4..5"; desc = "Unused, always write as 0's" }
        "PRESCALE"  { loc = "2..3"; desc = "Prescale divisor"; type = "timer_divisor" }
        "Unused2"  { sn = "Unused"; loc = "0..1"; desc = "Unused, always write as 0's"}
    }
    timer_clr_bitfield {
        "Clear"  { loc = "0..0"; desc = "Clear interrupt for this timer" }
    }
}

%define TIMER_BASE 0x13000000
register {
    TIMER0_LOAD { sn = "LOAD 0"; ln = "Timer 0 load";
	access = "memorymapped"; width = 16
	address = "${TIMER_BASE}"
    }
    TIMER0_VALUE { sn = "VALUE 0"; ln = "Timer 0 current value";
	access = "memorymapped"; width = 16
	address = "${TIMER_BASE} + 0x4"
    }
    TIMER0_CTRL { sn = "CTRL 0"; ln = "Timer 0 control";
	access = "memorymapped"; width = 16
	address = "${TIMER_BASE} + 0x8"; type = "timer_ctrl_bitfield"
    }
    TIMER0_CLR { sn = "CLR 0"; ln = "Timer 0 clear";
	access = "memorymapped"; width = 1; type = "timer_clr_bitfield"
	address = "${TIMER_BASE} + 0xC"
    }
    TIMER1_LOAD { sn = "LOAD 1"; ln = "Timer 1 load";
	access = "memorymapped"; width = 16
	address = "${TIMER_BASE} + 0x100"
    }
    TIMER1_VALUE { sn = "VALUE 1"; ln = "Timer 1 current value";
	access = "memorymapped"; width = 16
	address = "${TIMER_BASE} + 0x104"
    }
    TIMER1_CTRL { sn = "CTRL 1"; ln = "Timer 1 control";
	access = "memorymapped"; width = 16
	address = "${TIMER_BASE} + 0x108"; type = "timer_ctrl_bitfield"
    }
    TIMER1_CLR { sn = "CLR 1"; ln = "Timer 1 clear";
	access = "memorymapped"; width = 1; type = "timer_clr_bitfield"
	address = "${TIMER_BASE} + 0x10C"
    }
    TIMER2_LOAD { sn = "LOAD 2"; ln = "Timer 2 load";
	access = "memorymapped"; width = 16
	address = "${TIMER_BASE} + 0x200"
    }
    TIMER2_VALUE { sn = "VALUE 2"; ln = "Timer 2 current value";
	access = "memorymapped"; width = 16
	address = "${TIMER_BASE} + 0x204"
    }
    TIMER2_CTRL { sn = "CTRL 2"; ln = "Timer 2 control";
	access = "memorymapped"; width = 16
	address = "${TIMER_BASE} + 0x208"; type = "timer_ctrl_bitfield"
    }
    TIMER2_CLR { sn = "CLR 2"; ln = "Timer 2 clear";
	access = "memorymapped"; width = 1; type = "timer_clr_bitfield"
	address = "${TIMER_BASE} + 0x20C"
    }
}

%define INT_CTRL_BASE 0x14000000
register {
    IRQ0_STATUS { sn = "IRQ0_STATUS"; ln = "IRQ0 status";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE}"
    }
    IRQ0_RAWSTATUS { sn = "IRQ0_RAWSTATUS"; ln = "IRQ0 interrupt request status";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0x4"
    }
    IRQ0_ENABLESET { sn = "IRQ0_ENABLESET"; ln = "IRQ0 enable set";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0x8"
    }
    IRQ0_ENABLECLEAR { sn = "IRQ0_ENABLECLEAR"; ln = "IRQ0 enable clear";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0xc"
    }
    INT_SOFTSET0 { ln = "Software interrupt set";
	access = "memorymapped"; width = 16
	address = "${INT_CTRL_BASE} + 0x10"
    }
    INT_SOFTCLEAR0 { ln = "Software interrupt set";
	access = "memorymapped"; width = 16
	address = "${INT_CTRL_BASE} + 0x14"
    }
    IRQ1_STATUS { sn = "IRQ1_STATUS"; ln = "IRQ1 status";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0x40"
    }
    IRQ1_RAWSTATUS { sn = "IRQ1_RAWSTATUS"; ln = "IRQ1 interrupt request status";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0x44"
    }
    IRQ1_ENABLESET { sn = "IRQ1_ENABLESET"; ln = "IRQ1 enable set";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0x48"
    }
    IRQ1_ENABLECLEAR { sn = "IRQ1_ENABLECLEAR"; ln = "IRQ1 enable clear";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0x4c"
    }
    INT_SOFTSET0 { ln = "Software interrupt set";
	access = "memorymapped"; width = 16
	address = "${INT_CTRL_BASE} + 0x50"
    }
    INT_SOFTCLEAR0 { ln = "Software interrupt set";
	access = "memorymapped"; width = 16
	address = "${INT_CTRL_BASE} + 0x54"
    }
    IRQ2_STATUS { sn = "IRQ2_STATUS"; ln = "IRQ2 status";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0x80"
    }
    IRQ2_RAWSTATUS { sn = "IRQ2_RAWSTATUS"; ln = "IRQ2 interrupt request status";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0x84"
    }
    IRQ2_ENABLESET { sn = "IRQ2_ENABLESET"; ln = "IRQ2 enable set";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0x88"
    }
    IRQ2_ENABLECLEAR { sn = "IRQ2_ENABLECLEAR"; ln = "IRQ2 enable clear";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0x8c"
    }
    INT_SOFTSET2 { ln = "Software interrupt set";
	access = "memorymapped"; width = 16
	address = "${INT_CTRL_BASE} + 0x90"
    }
    INT_SOFTCLEAR2 { ln = "Software interrupt set";
	access = "memorymapped"; width = 16
	address = "${INT_CTRL_BASE} + 0x94"
    }
    IRQ3_STATUS { sn = "IRQ3_STATUS"; ln = "IRQ3 status";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0xc0"
    }
    IRQ3_RAWSTATUS { sn = "IRQ3_RAWSTATUS"; ln = "IRQ3 interrupt request status";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0xc4"
    }
    IRQ3_ENABLESET { sn = "IRQ3_ENABLESET"; ln = "IRQ3 enable set";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0xc8"
    }
    IRQ3_ENABLECLEAR { sn = "IRQ3_ENABLECLEAR"; ln = "IRQ3 enable clear";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0xcc"
    }
    INT_SOFTSET3 { ln = "Software interrupt set";
	access = "memorymapped"; width = 16
	address = "${INT_CTRL_BASE} + 0xd0"
    }
    INT_SOFTCLEAR3 { ln = "Software interrupt set";
	access = "memorymapped"; width = 16
	address = "${INT_CTRL_BASE} + 0xd4"
    }

    FIQ0_STATUS { sn = "FIQ0_STATUS"; ln = "FIQ0 status";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0x20"
    }
    FIQ0_RAWSTATUS { sn = "FIQ0_RAWSTATUS"; ln = "FIQ0 interrupt request status";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0x24"
    }
    FIQ0_ENABLESET { sn = "FIQ0_ENABLESET"; ln = "FIQ0 enable set";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0x28"
    }
    FIQ0_ENABLECLEAR { sn = "FIQ0_ENABLECLEAR"; ln = "FIQ0 enable clear";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0x2c"
    }
    FIQ1_STATUS { sn = "FIQ1_STATUS"; ln = "FIQ1 status";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0x60"
    }
    FIQ1_RAWSTATUS { sn = "FIQ1_RAWSTATUS"; ln = "FIQ1 interrupt request status";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0x64"
    }
    FIQ1_ENABLESET { sn = "FIQ1_ENABLESET"; ln = "FIQ1 enable set";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0x68"
    }
    FIQ1_ENABLECLEAR { sn = "FIQ1_ENABLECLEAR"; ln = "FIQ1 enable clear";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0x6c"
    }
    FIQ2_STATUS { sn = "FIQ2_STATUS"; ln = "FIQ2 status";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0xa0"
    }
    FIQ2_RAWSTATUS { sn = "FIQ2_RAWSTATUS"; ln = "FIQ2 interrupt request status";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0xa4"
    }
    FIQ2_ENABLESET { sn = "FIQ2_ENABLESET"; ln = "FIQ2 enable set";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0xa8"
    }
    FIQ2_ENABLECLEAR { sn = "FIQ2_ENABLECLEAR"; ln = "FIQ2 enable clear";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0xac"
    }
    FIQ3_STATUS { sn = "FIQ3_STATUS"; ln = "FIQ3 status";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0xe0"
    }
    FIQ3_RAWSTATUS { sn = "FIQ3_RAWSTATUS"; ln = "FIQ3 interrupt request status";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0xe4"
    }
    FIQ3_ENABLESET { sn = "FIQ3_ENABLESET"; ln = "FIQ3 enable set";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0xe8"
    }
    FIQ3_ENABLECLEAR { sn = "FIQ3_ENABLECLEAR"; ln = "FIQ3 enable clear";
	access = "memorymapped"; width = 22
	address = "${INT_CTRL_BASE} + 0xec"
    }
}

enum {
    "uart_wlen" {
	"8 bits" { value = 3 }; "7 bits" { value = 2 };
	"6 bits" { value = 1 }; "5 bits" { value = 0 };
    }
    "uart_parity" {
	"Even" { value = 3 }; "None" { value = 2 };
	"Odd" { value = 1 }; "None" { value = 0 };
    }
}

bitfield {
    uart_rsr_bitfield {
        "OE"  { loc = "3"; desc = "Overrun Error" }
        "BE"  { loc = "2"; desc = "Break Error" }
        "PE"  { loc = "1"; desc = "Parity Error" }
        "FE"  { loc = "0"; desc = "Framing Error" }
    }
    uart_lcrh_bitfield {
        "Reserved"  { loc = "7"; desc = "Reserved, read as 0" }
        "WLEN"  { loc = "5..6"; desc = "Word length"; type = "uart_wlen" }
        "FEN"  { loc = "4"; desc = "Enable FIFOs" }
        "STP2"  { loc = "3"; desc = "Two Stop Bits Select" }
	"EPS|PEN" { loc = "1..2"; desc = "Even Parity Select | Parity Enable"; type = "uart_parity" }
#        "EPS"  { loc = "2"; desc = "Even Parity Select" }
#        "PEN"  { loc = "1"; desc = "Parity Enable" }
        "BRK"  { loc = "0"; desc = "Send Break" }
    }
    uart_cr_bitfield {
        "LBE"  { loc = "7"; desc = "Loop Back Enable" }
        "RTIE"  { loc = "6"; desc = "Receive Timeout Interrupt Enable" }
        "TIE"  { loc = "5"; desc = "Transmit Interrupt Enable" }
        "RIE"  { loc = "4"; desc = "Receive Interrupt Enable" }
        "MSIE"  { loc = "3"; desc = "Modem Status Interrupt Enable" }
        "Reserved1"  { sn = "Reserved"; ln = "Reserved for IrDA encoding mode"; loc = "2"; desc = "Unused, Always write with 0" }
        "Reserved2"  { sn = "Reserved"; ln = "Reserved for SIR enable bit"; loc = "1"; desc = "Unused, Always write with 0" }
        "UARTEN"  { loc = "0"; desc = "UART Enable" }
    }
    uart_fr_bitfield {
        "TXFE"  { loc = "7"; desc = "Transmit FIFO Empty" }
        "RXFF"  { loc = "6"; desc = "Receive FIFO Full" }
        "TXFF"  { loc = "5"; desc = "Transmit FIFO Full" }
        "RXFE"  { loc = "4"; desc = "Receive FIFO Empty" }
        "BUSY"  { loc = "3"; desc = "UART Busy" }
        "DCD"  { loc = "2"; desc = "Data Carrier Detect" }
        "DSR"  { loc = "1"; desc = "Data Set Ready" }
        "CTS"  { loc = "0"; desc = "Clear To Send" }
    }
    uart_iir_bitfield {
        "Reserved"  { loc = "4..7"; desc = "Reserved, unpredictable when read" }
        "RTIS"  { loc = "3"; desc = "Receive Timeout Interrupt Status" }
        "TIS"  { loc = "2"; desc = "Transmit Interrupt Status" }
        "RIS"  { loc = "1"; desc = "Receive Interrupt Status" }
        "MIS"  { loc = "0"; desc = "Modem Interrupt Status" }
    }
}
%define UART0_BASE 0x16000000
register {
    UART0_RSR { sn = "UART0_RSR"; ln = "UART0 Receive status register";
	access = "memorymapped"; width = 8
	address = "${UART0_BASE} + 0x4"
	type = "uart_rsr_bitfield"
	permission = "write/none"
    }
    UART0_ECR { sn = "UART0_ECR"; ln = "UART0 Error clear register";
	access = "memorymapped"; width = 8
	address = "${UART0_BASE} + 0x4"
    }
    UART0_LCRH { sn = "UART0_LCRH"; ln = "UART0 Line control register, high byte";
	access = "memorymapped"; width = 8
	address = "${UART0_BASE} + 0x8"
	type = "uart_lcrh_bitfield"
    }
    UART0_LCRM { sn = "UART0_LCRM"; ln = "UART0 Line control register, middle byte";
	access = "memorymapped"; width = 8
	address = "${UART0_BASE} + 0xc"
    }
    UART0_LCRL { sn = "UART0_LCRL"; ln = "UART0 Line control register, low byte";
	access = "memorymapped"; width = 8
	address = "${UART0_BASE} + 0x10"
    }
    UART0_CR { sn = "UART0_CR"; ln = "UART0 Control register";
	access = "memorymapped"; width = 8
	address = "${UART0_BASE} + 0x14"
	type = "uart_cr_bitfield"
    }
    UART0_FR { sn = "UART0_FR"; ln = "UART0 Flag register";
	access = "memorymapped"; width = 8
	address = "${UART0_BASE} + 0x18"
	type = "uart_fr_bitfield"
	permission = "write/none"
    }
    UART0_IIR { sn = "UART0_IIR"; ln = "UART0 Interrupt identification register";
	access = "memorymapped"; width = 8
	address = "${UART0_BASE} + 0x1c"
	type = "uart_iir_bitfield"
	permission = "write/none"
    }
    UART0_ICR { sn = "UART0_ICR"; ln = "UART0 Interrupt clear register";
	access = "memorymapped"; width = 8
	address = "${UART0_BASE} + 0x1c"
    }
}

%define UART1_BASE 0x17000000
register {
    UART1_RSR { sn = "UART1_RSR"; ln = "UART1 Receive status register";
	access = "memorymapped"; width = 8
	address = "${UART1_BASE} + 0x4"
	permission = "write/none"
    }
    UART1_ECR { sn = "UART1_ECR"; ln = "UART1 Error clear register";
	access = "memorymapped"; width = 8
	address = "${UART1_BASE} + 0x4"
    }
    UART1_LCRH { sn = "UART1_LCRH"; ln = "UART1 Line control register, high byte";
	access = "memorymapped"; width = 8
	address = "${UART1_BASE} + 0x8"
    }
    UART1_LCRM { sn = "UART1_LCRM"; ln = "UART1 Line control register, middle byte";
	access = "memorymapped"; width = 8
	address = "${UART1_BASE} + 0xc"
    }
    UART1_LCRL { sn = "UART1_LCRL"; ln = "UART1 Line control register, low byte";
	access = "memorymapped"; width = 8
	address = "${UART1_BASE} + 0x10"
    }
    UART1_CR { sn = "UART1_CR"; ln = "UART1 Control register";
	access = "memorymapped"; width = 8
	address = "${UART1_BASE} + 0x14"
    }
    UART1_FR { sn = "UART1_FR"; ln = "UART1 Flag register";
	access = "memorymapped"; width = 8
	address = "${UART1_BASE} + 0x18"
	permission = "write/none"
    }
    UART1_IIR { sn = "UART1_IIR"; ln = "UART1 Interrupt identification register";
	access = "memorymapped"; width = 8
	address = "${UART1_BASE} + 0x1c"
	permission = "write/none"
    }
    UART1_ICR { sn = "UART1_ICR"; ln = "UART1 Interrupt clear register";
	access = "memorymapped"; width = 8
	address = "${UART1_BASE} + 0x1c"
    }
}

enum {
    "led_status" { "idle" { value = 0 }; "busy" { value = 1 } }
    "led" { "OFF" { value = 0 }; "ON" { value = 1 } }
}

bitfield {
    led_alpha_bitfield {
#        "CHARACTERS"  { loc = "1..30"; desc = "Bit patters that form characters on the display" }
        "A1"  { loc = "15..15"; desc = "A1" }; "A2"  { loc = "1..1"; desc = "A2" }
        "B1"  { loc = "16..16"; desc = "B1" }; "B2"  { loc = "2..2"; desc = "B2" }
        "C1"  { loc = "17..17"; desc = "C1" }; "C2"  { loc = "3..3"; desc = "C2" }
        "D1"  { loc = "18..18"; desc = "D1" }; "D2"  { loc = "4..4"; desc = "D2" }
        "E1"  { loc = "19..19"; desc = "E1" }; "E2"  { loc = "5..5"; desc = "E2" }
        "F1"  { loc = "20..20"; desc = "F1" }; "F2"  { loc = "6..6"; desc = "F2" }
        "G1"  { loc = "21..21"; desc = "G1" }; "G2"  { loc = "7..7"; desc = "G2" }
        "H1"  { loc = "22..22"; desc = "H1" }; "H2"  { loc = "8..8"; desc = "H2" }
        "K1"  { loc = "23..23"; desc = "K1" }; "K2"  { loc = "9..9"; desc = "K2" }
        "M1"  { loc = "24..24"; desc = "M1" }; "M2"  { loc = "10..10"; desc = "M2" }
        "N1"  { loc = "25..25"; desc = "N1" }; "N2"  { loc = "11..11"; desc = "N2" }
        "R1"  { loc = "26..26"; desc = "R1" }; "R2"  { loc = "12..12"; desc = "R2" }
        "S1"  { loc = "27..27"; desc = "S1" }; "S2"  { loc = "13..13"; desc = "S2" }
        "T1"  { loc = "28..28"; desc = "T1" }; "T2"  { loc = "14..14"; desc = "T2" }
        "DP1"  { loc = "29..29"; desc = "DP1" }; "DP2"  { loc = "30..30"; desc = "DP2" }
	"STATUS"  { loc = "0..0"; desc = "Display status"; type = "led_status" }
    }
    led_lights_bitfield {
	"LED3" { loc = "3..3"; desc = "D10 (green)"; type = "led" }
	"LED2" { loc = "2..2"; desc = "D9 (red)"; type = "led"  }
	"LED1" { loc = "1..1"; desc = "D8 (yellow)"; type = "led"  }
	"LED0" { loc = "0..0"; desc = "D7 (green)"; type = "led"  }
    }
    led_switches_bitfield {
	"S1-4" { loc = "3..3"; desc = "Switch pole 4 (S1-4)"; type = "led" }
	"S1-3" { loc = "2..2"; desc = "Switch pole 3 (S1-3)"; type = "led" }
	"S1-2" { loc = "1..1"; desc = "Switch pole 2 (S1-2)"; type = "led" }
	"S1-1" { loc = "0..0"; desc = "Switch pole 1 (S1-1)"; type = "led" }
    }
}

%define LED_BASE 0x1A000000
register {
    LED_ALPHA { sn = "ALPHA"; ln = "Alphanumeric characters register";
	access = "memorymapped"; width = 32
	address = "${LED_BASE}"; type = "led_alpha_bitfield"
    }
    LED_LIGHTS { sn = "LIGHTS"; ln = "LED control register";
	access = "memorymapped"; width = 4
	address = "${LED_BASE} + 0x4"; type = "led_lights_bitfield"
    }
    LED_SWITCHES { sn = "SWITCHES"; ln = "DIP switch register";
	access = "memorymapped"; width = 4
	address = "${LED_BASE} + 0x8"; type = "led_switches_bitfield"
	permission = "write/none"
    }
}

%define SPD_BASE 0x10000100
register {
    SPD_TYPE {sn = "type"; access = "memorymapped"; width = 8;
	address = "${SPD_BASE} + 2"
    }
    SPD_NROWS {sn = "nrows"; access = "memorymapped"; width = 8;
	address = "${SPD_BASE} + 3"
    }
    SPD_NCOLS {sn = "ncols"; access = "memorymapped"; width = 8;
	address = "${SPD_BASE} + 4"
    }
    SPD_NBANKS {sn = "nbanks"; access = "memorymapped"; width = 8;
	address = "${SPD_BASE} + 5"
    }
    SPD_DENSITY {sn = "density"; access = "memorymapped"; width = 8;
	address = "${SPD_BASE} + 31"
	ln = "Module bank density (MB divided by 4)"
    }
    SPD_CASLAT {sn = "CAS latencies"; access = "memorymapped"; width = 8;
	address = "${SPD_BASE} + 18"
    }
    SPD_CHECKSUM {sn = "Checksum"; access = "memorymapped"; width = 8;
	address = "${SPD_BASE} + 63"
    }
#    SPD_MAN {sn = "Manufacturer"; access = "memorymapped"; width = 64;
#	address = "${SPD_BASE} + 64"; type = "ascii"
#    }
#    SPD_PART {sn = "part number"; access = "memorymapped"; width = 64;
#	address = "${SPD_BASE} + 73"; type = "ascii"
#    }
}


group {
    arm_integrator_CM {
	sn = "CM"
	register += {"cm_id", "cm_processor", "cm_oscillator"}
	register += {"cm_control", "cm_status", "cm_lock", "cm_lmbuscnt"}
	register += {"cm_aux_oscillator", "cm_sdram"}
	register += {"cm_init", "cm_refcnt"}
	register += {"cm_flags", "cm_flagss", "cm_flagsc"}
	register += {"cm_nvflags", "cm_nvflagss", "cm_nvflagsc"}
	register += {"cm_irq_stat", "cm_irq_rstat", "cm_irq_enset", "cm_irq_enclr"}
	register += {"cm_soft_intset", "cm_soft_intclr", "cm_fiq_stat", "cm_fiq_rstat"}
	register += {"cm_fiq_enset", "cm_fiq_enclr"}
	register += {"cm_voltage_ctl0", "cm_voltage_ctl1"}
	register += {"cm_voltage_ctl2", "cm_voltage_ctl3"}
    }
    arm_integrator_SC {
	sn = "SC"
	register += {"SC_ID", "SC_OSC", "SC_CTRLS", "SC_CTRLC"}
	register += {"SC_DEC", "SC_ARB", "SC_PCI", "SC_LOCK"}
	register += {"SC_LBFADDR", "SC_LBFCODE"}
	register += {"SC_FLAGS", "SC_FLAGSET", "SC_FLAGSCLR"}
	register += {"SC_NVFLAGS", "SC_NVFLAGSET", "SC_NVFLAGSCLR"}
    }
    arm_integrator_EBI {
	sn = "EBI"
	register += {"EBI_CSR0", "EBI_CSR1", "EBI_CSR2", "EBI_CSR3"}
	register += {"EBI_LOCK"}
    }
    arm_integrator_TIMER {
	sn = "TIMER"
	register += {"TIMER0_LOAD", "TIMER0_VALUE", "TIMER0_CTRL", "TIMER0_CLR"}
	register += {"TIMER1_LOAD", "TIMER1_VALUE", "TIMER1_CTRL", "TIMER1_CLR"}
	register += {"TIMER2_LOAD", "TIMER2_VALUE", "TIMER2_CTRL", "TIMER2_CLR"}
    }
    arm_integrator_INT_CTL {
	sn = "INT_CTL"
	register += {"IRQ0_STATUS", "IRQ0_RAWSTATUS", "IRQ0_ENABLESET", "IRQ0_ENABLECLEAR"}
	register += {"INT_SOFTSET0", "INT_SOFTCLEAR0"}
	register += {"IRQ1_STATUS", "IRQ1_RAWSTATUS", "IRQ1_ENABLESET", "IRQ1_ENABLECLEAR"}
	register += {"INT_SOFTSET1", "INT_SOFTCLEAR1"}
	register += {"IRQ2_STATUS", "IRQ2_RAWSTATUS", "IRQ2_ENABLESET", "IRQ2_ENABLECLEAR"}
	register += {"INT_SOFTSET2", "INT_SOFTCLEAR2"}
	register += {"IRQ3_STATUS", "IRQ3_RAWSTATUS", "IRQ3_ENABLESET", "IRQ3_ENABLECLEAR"}
	register += {"INT_SOFTSET3", "INT_SOFTCLEAR3"}
	register += {"FIQ0_STATUS", "FIQ0_RAWSTATUS", "FIQ0_ENABLESET", "FIQ0_ENABLECLEAR"}
	register += {"FIQ1_STATUS", "FIQ1_RAWSTATUS", "FIQ1_ENABLESET", "FIQ1_ENABLECLEAR"}
	register += {"FIQ2_STATUS", "FIQ2_RAWSTATUS", "FIQ2_ENABLESET", "FIQ2_ENABLECLEAR"}
	register += {"FIQ3_STATUS", "FIQ3_RAWSTATUS", "FIQ3_ENABLESET", "FIQ3_ENABLECLEAR"}
    }
    arm_integrator_UART0 {
	sn = "UART0"
	register += {"UART0_RSR", "UART0_ECR"}
	register += {"UART0_LCRH", "UART0_LCRM", "UART0_LCRL"}
	register += {"UART0_CR", "UART0_FR", "UART0_IIR", "UART0_ICR"}
    }
    arm_integrator_UART1 {
	sn = "UART1"
	register += {"UART1_RSR", "UART1_ECR"}
	register += {"UART1_LCRH", "UART1_LCRM", "UART1_LCRL"}
	register += {"UART1_CR", "UART1_FR", "UART1_IIR", "UART1_ICR"}
    }
    arm_integrator_LED {
	sn = "LED"
	register += {"LED_ALPHA", "LED_LIGHTS", "LED_SWITCHES"}
    }
    arm_integrator_SPD {
	sn = "SPD"
	register += {"SPD_TYPE", "SPD_NROWS", "SPD_NCOLS", "SPD_NBANKS"}
	register += {"SPD_DENSITY", "SPD_CASLAT", "SPD_CHECKSUM"}
#	register += {"SPD_MAN", "SPD_PART"}
    }
}