# ARM940T Coprocessor 15 (system coprocessor) registers

# Register definitions
register {
    id {
	sn="id"
	ln="ID Code Register c0"
	address=191
	type="id_bitfield"
    }
    cachetype {
	sn="cachetype"
	ln="Cache Type Register c0"
	address=192
	type="cachetype_bitfield"
    }
    control {
	sn="control"
	ln="Control Register c1"
	address=193
	type="control_bitfield"
    }
    cacheable_i {sn="cacheable_i"; address=194}
    cacheable_d {sn="cacheable_d"; address=195}
    wbcontrol {sn="wbcontrol"; address=196}
    inst_perms {sn="inst_perms"; address=197}
    data_perms {sn="data_perms"; address=198}
    iregion0 {sn="iregion0"; address=199}
    iregion1 {sn="iregion1"; address=200}
    iregion2 {sn="iregion2"; address=201}
    iregion3 {sn="iregion3"; address=202}
    iregion4 {sn="iregion4"; address=203}
    iregion5 {sn="iregion5"; address=204}
    iregion6 {sn="iregion6"; address=205}
    iregion7 {sn="iregion7"; address=206}
    dregion0 {sn="dregion0"; address=207}
    dregion1 {sn="dregion1"; address=208}
    dregion2 {sn="dregion2"; address=209}
    dregion3 {sn="dregion3"; address=210}
    dregion4 {sn="dregion4"; address=211}
    dregion5 {sn="dregion5"; address=212}
    dregion6 {sn="dregion6"; address=213}
    dregion7 {sn="dregion7"; address=214}
    ic_lock {sn="ic_lock"; address=334}
    dc_lock {sn="dc_lock"; address=335}
    test {sn="test"; address=215}
}

# Group definitions
group {
    arm940_CP15 {
        sn = "CP15"
        top_level_index = 200
        register += {"id", "cachetype", "control", "cacheable_i", "cacheable_d"}
	register += {"wbcontrol", "inst_perms", "data_perms"}
	register += {"iregion0", "iregion1", "iregion2", "iregion3"}
	register += {"iregion4", "iregion5", "iregion6", "iregion7"}
	register += {"dregion0", "dregion1", "dregion2", "dregion3"}
	register += {"dregion4", "dregion5", "dregion6", "dregion7"}
	register += {"ic_lock", "dc_lock", "test"}
    }
}