# ARM1136J-S Coprocessor 15 (system coprocessor) registers

# Register definitions
register {
    id {
	sn="id"
	ln="ID Code Register c0"
	address=338
	type="id_bitfield"
	permission = "write/none"
    }
    cache_type {
	sn="cache_type"
	ln="Cache Type Register c0"
	address=339
	type="cachetype_bitfield"
	permission = "write/none"
    }
    tcm_status {
	sn="tcm_status"
	ln="TCM Status Register c0"
	address=340
	type="tcmstatus_bitfield"
	permission = "write/none"
    }
    tlb_type {
	sn="tlb_type"
	ln="TLB Type Register c0"
	address=341
	type="tlbtype_bitfield"
	permission = "write/none"
    }
    control {
	sn="control"
	ln="Control Register c1"
	address=342
	type="control_bitfield"
    }
    aux_control {
	sn="aux_control"
	ln="Auxiliary Control Register c1"
	address=343
    }
    cp_access {
	sn="cp_access"
	ln="Coprocessor Access Control Register c1"
	address=344
    }
    ttbase0 {
	sn="ttbase0"
	ln="Translation Table Base Register 0 c2"
	address=345
	type="ttbase_bitfield"
    }
    ttbase1 {
	sn="ttbase1"
	ln="Translation Table Base Register 1 c2"
	address=346
	type="ttbase_bitfield"
    }
    ttbase_ctrl {
	sn="ttbase_ctrl"
	ln="Translation Table Base Control Register c2"
	address=347
    }
    dactl {
	sn="dactl"
	ln="Domain Access Control Register c3"
	address=348
	type="dactl_bitfield"
    }
    dfsr {
	sn="dfsr"
	ln="Data Fault Status Register c5"
	address=349
	type="faultstatus_bitfield"
    }
    ifsr {
	sn="ifsr"
	ln="Instruction Fault Status Register c5"
	address=350
	type="faultstatus_bitfield"
    }
    far {
	sn="far"
	ln="Fault Address Register c6"
	desc="Contains the Modified Virtual Address of the data access being attempted when a Data Abort occurred."
	address=351
    }
    wfar {
	sn="wfar"
	ln="Watchpoint Fault Address Register c6"
	desc="Contains the Modified Virtual Address of the instruction access being attempted when a Data Abort occurred."
	address=352
    }
    dcache_lock {
	sn="dcache_lock"
	ln="Instruction Cache Lockdown Register c9"
	address=353
	type="cachelock_bitfield"
    }
    icache_lock {
	sn="icache_lock"
	ln="Data Cache Lockdown Register c9"
	address=354
	type="cachelock_bitfield"
    }
    dtcmregion {
	sn="dtcmregion"
	ln="Data TCM Region Register c9"
	address=355
	type="tcmregion_bitfield"
    }
    itcmregion {
	sn="itcmregion"
	ln="Instruction TCM Region Register c9"
	address=356
	type="tcmregion_bitfield"
    }
    tlb_lock {
	sn="tlb_lock"
	ln="TLB Lockdown Register c10"
	address=357
	type="tlblock_bitfield"
    }
    dma_st_present {
	sn="dma_st_present"
	ln="DMA Present"
	permission = "write/none"
	address=358
    }
    dma_st_queued {
	sn="dma_st_queued"
	ln="DMA Queued"
	permission = "write/none"
	address=359
    }
    dma_st_running {
	sn="dma_st_running"
	ln="DMA Running"
	permission = "write/none"
	address=360
    }
    dma_st_interrupting {
	sn="dma_st_interrupting"
	ln="DMA Interrupting"
	permission = "write/none"
	address=361
    }
    dma_user_access {
	sn="dma_user_access"
	ln="DMA User Accessibility"
	address=362
    }
    dma_ch_number {
	sn="dma_ch_number"
	ln="DMA Channel Number"
	address=363
    }
    dma_enable_stop {
	sn="dma_enable_stop"
	ln="DMA Enable Stop"
	permission = "read/none"
	address=364
    }
    dma_enable_start {
	sn="dma_enable_start"
	ln="DMA Enable Start"
	permission = "read/none"
	address=365
    }
    dma_enable_clear {
	sn="dma_enable_clear"
	ln="DMA Enable Clear"
	permission = "read/none"
	address=366
    }
    dma_control	{ address=367 }
    dma_istart	{ address=368 }
    dma_estart	{ address=369 }
    dma_iend	{ address=370 }
    dma_status	{ address=371; permission = "write/none" }
    dma_contextid	{ address=372 }
    pid {
	sn="pid"
	ln="Fast Context Switch Extension (FCSE) Process Identifier (PID) Register c13"
	address=373
	type="pid_bitfield"
    }
    contextid {
	sn="contextid"
	ln="Context ID Register c13"
	address=374
    }
    dm_remap		{ address=375 }
    im_remap		{ address=376 }
    dma_remap		{ address=377 }
    periph_remap	{ address=378 }
    perfmon_ctrl	{ address=379 }
    cycle_count		{ address=380 }
    count0		{ address=381 }
    count1		{ address=382 }
    dcache_debug	{ address=383; permission = "write/none" }
    icache_debug	{ address=384; permission = "write/none" }
    dtag_read_op	{ address=385 }
    itag_read_op	{ address=386 }
    icache_read_op	{ address=387 }
    icache_mvr		{ address=388 }
    iscache_mvr		{ address=389 }
    dcache_mvr		{ address=390 }
    dscache_mvr		{ address=391 }
    dmicrotlb_entry_op	{ address=392; permission = "read/none" }
    imicrotlb_entry_op	{ address=393; permission = "read/none" }
    read_maintlb_entry	{ address=394 }
    write_maintlb_entry	{ address=395 }
    dmicrotlb_va	{ address=396; permission = "write/none" }
    imicrotlb_va	{ address=397; permission = "write/none" }
    maintlb_va		{ address=398 }
    dmicrotlb_pa	{ address=399; permission = "write/none" }
    imicrotlb_pa	{ address=400; permission = "write/none" }
    maintlb_pa		{ address=401 }
    dmicrotlb_attrib	{ address=402; permission = "write/none" }
    imicrotlb_attrib	{ address=403; permission = "write/none" }
    maintlb_attrib	{ address=404 }
    maintlb_mvr		{ address=405 }
    cache_debug_ctrl	{ address=406 }
    tlb_debug_ctrl	{ address=407 }
}


# Group definitions
group {
    arm1136_CP15_DMA {
        sn = "CP15_DMA"
	register += { "dma_st_present", "dma_st_queued", "dma_st_running", "dma_st_interrupting" }
	register += { "dma_user_access", "dma_ch_number" }
	register += { "dma_enable_stop", "dma_enable_start", "dma_enable_clear" }
	register += { "dma_control", "dma_istart", "dma_estart" }
	register += { "dma_iend", "dma_status", "dma_contextid" }
    }
    arm1136_CP15_C15 {
	sn = "CP15_C15"
	register += { "dm_remap", "im_remap", "dma_remap", "periph_remap" }
	register += { "perfmon_ctrl", "cycle_count", "count0", "count1" }
	register += { "dcache_debug", "icache_debug" }
	register += { "dtag_read_op", "itag_read_op", "icache_read_op" }
	register += { "icache_mvr", "iscache_mvr", "dcache_mvr", "dscache_mvr" }
	register += { "dmicrotlb_entry_op", "imicrotlb_entry_op" }
	register += { "read_maintlb_entry", "write_maintlb_entry" }	
	register += { "dmicrotlb_va", "imicrotlb_va", "maintlb_va" }		
	register += { "dmicrotlb_pa", "imicrotlb_pa", "maintlb_pa" }		
	register += { "dmicrotlb_attrib", "imicrotlb_attrib", "maintlb_attrib" }
	register += { "maintlb_mvr", "cache_debug_ctrl", "tlb_debug_ctrl" }
    }
    arm1136_CP15 {
        sn = "CP15"
        register += { "id", "cache_type", "tcm_status", "tlb_type" }
	register += { "control", "aux_control", "cp_access" }
	register += { "ttbase0", "ttbase1", "ttbase_ctrl" }
	register += { "dactl", "dfsr", "ifsr", "far", "wfar" }
	register += { "dcache_lock", "icache_lock", "dtcmregion", "itcmregion" }
	register += { "tlb_lock" }
	register += { "pid", "contextid" }
	group += { "arm1136_CP15_DMA", "arm1136_CP15_C15" }
    }
}