/*********************************************************************************//*! * \file T1_config.c * * \brief Application-specific configuration of T1 * * $Author: jialinli $ * * $Revision: 27 $ * * \copyright GLIWA GmbH embedded systems, Weilheim i.OB. All rights reserved *************************************************************************************/ /*----------------------------------------------------------------------------------*/ /*--- header includes --------------------------------------------------------------*/ /*----------------------------------------------------------------------------------*/ /* * The following define is REQUIRED for MPC5xxx and SPC5xx. Only if T1.flex and * debugger coexistence is supported by the hardware this may be omitted. */ /* #define T1_FLEX_DISABLE_WITH_DEBUGGER (1) */ #define T1_OVERRIDE_SYNCTOTRACETIMERPC (1) /* Backwards compatibility */ #include "T1_AppInterface.h" T1_EXTERN void Os_Hard_Fault_Exception_Handler(void); /*----------------------------------------------------------------------------------*/ /*--- Local macros ----------------------------------------------------------------*/ /*----------------------------------------------------------------------------------*/ #if ! defined T1_GET_TRACE_TIME_UMPC /*! * If we can invoke #T1_GET_TRACE_TIME_PC in user mode then we can map * #T1_GET_TRACE_TIME_UMPC directly to #T1_GET_TRACE_TIME_PC. Otherwise the integrator * must define #T1_GET_TRACE_TIME_UMPC to safely read the trace timer in user mode. * \returns the trace timer count register scaled to trace timer ticks */ # define T1_GET_TRACE_TIME_UMPC( coreId_ ) T1_GET_TRACE_TIME_PC( coreId_ ) #endif /* ! defined T1_GET_TRACE_TIME_UMPC */ #if ! defined T1_CONT_CPU_LOAD_EXTRAS # define T1_CONT_CPU_LOAD_EXTRAS( coreId_, cpuLoadFrac_, cpuLoadThreshold_ ) (void)0 #endif /* ! defined T1_CONT_CPU_LOAD_EXTRAS */ /*----------------------------------------------------------------------------------*/ /*--- Optimization pragmas for uniform code generation -----------------------------*/ /*----------------------------------------------------------------------------------*/ #if defined __ghs__ # pragma ghs O #elif defined __TASKING__ # pragma optimize 2 #elif defined __GNUC__ && ! defined __TI_COMPILER_VERSION__ && ! defined __clang__ # pragma GCC optimize "O2" #endif #if defined T1_ENABLE /*----------------------------------------------------------------------------------*/ /*--- T1.base configuration --------------------------------------------------------*/ /*----------------------------------------------------------------------------------*/ # define T1_START_SEC_CONST_32 # include "T1_MemMap.h" T1_ALLOCATE_PLUGIN_TABLE( T1_pluginTable ) # define T1_STOP_SEC_CONST_32 # include "T1_MemMap.h" # if ! defined T1_DISABLE_T1_CONT && defined T1_CONT_REMOTE # define T1_START_SEC_VAR_CLEARED_32 # include "T1_MemMap.h" /*! \brief Shared data for remote core T1.cont pairs of cores. */ T1_bakery_t T1_SEC_VAR_CLEARED_32 T1_contRemoteSemPC[T1_NOF_CORES][2]; # define T1_STOP_SEC_VAR_CLEARED_32 # include "T1_MemMap.h" # endif /* ! defined T1_DISABLE_T1_CONT && defined T1_CONT_REMOTE */ # define T1_START_SEC_CODE # include "T1_MemMap.h" void T1_CODE T1_SuspendAllInterruptsPC( T1_uint8Least_t coreId ) { /* May be replaced by a call to AUTOSAR OS SuspendAllInterrupts( ) */ T1_SuspendAllInterruptsPC_( coreId ); } void T1_CODE T1_ResumeAllInterruptsPC( T1_uint8Least_t coreId ) { /* May be replaced by a call to AUTOSAR OS ResumeAllInterrupts( ) */ T1_ResumeAllInterruptsPC_( coreId ); } void T1_CODE T1_DisableT1HandlerPC( T1_uint8Least_t coreId ) { # if ! defined T1_DISABLE_T1_CONT && defined T1_CONT_REMOTE (void)T1_GetSpinlockPC( T1_CONT_RC_UNMAP( coreId ), T1_contRemoteSemPC[coreId], 1u, 2u, T1_FALSE ); # else /* May be replaced by a call to AUTOSAR OS GetResource( ) */ T1_SuspendAllInterruptsPC( coreId ); # endif /* ! defined T1_DISABLE_T1_CONT && defined T1_CONT_REMOTE */ } void T1_CODE T1_EnableT1HandlerPC( T1_uint8Least_t coreId ) { # if ! defined T1_DISABLE_T1_CONT && defined T1_CONT_REMOTE T1_ReleaseSpinlockPC( T1_CONT_RC_UNMAP( coreId ), T1_contRemoteSemPC[coreId], 1u, T1_FALSE ); # else /* May be replaced by a call to AUTOSAR OS ReleaseResource( ) */ T1_ResumeAllInterruptsPC( coreId ); # endif /* ! defined T1_DISABLE_T1_CONT && defined T1_CONT_REMOTE */ } # define T1_STOP_SEC_CODE # include "T1_MemMap.h" /*----------------------------------------------------------------------------------*/ /*--- T1.cont configuration --------------------------------------------------------*/ /*----------------------------------------------------------------------------------*/ # if ! defined T1_DISABLE_T1_CONT # if defined T1_CONT_REMOTE && defined T1_ENABLE_WRITE_TIME # error T1_CONT_REMOTE and T1_ENABLE_WRITE_TIME are not compatible # endif /* defined T1_CONT_REMOTE && defined T1_ENABLE_WRITE_TIME */ # define T1_START_SEC_CODE # include "T1_MemMap.h" void T1_NOINLINE T1_CODE T1_ContCsrnCallbackNoSuspPC( T1_uint8Least_t coreId, T1_UNUSED( T1_resultTime_t result ), T1_UNUSED( T1_csrnIdx_t idx ), T1_nofEntries_t afterXevnts ) { (void)coreId; /* Suppress warnings if T1_CONT_RC_UNMAP does not use coreId */ if( T1_IsFeatureEnabled( T1_AF_ALLOW_TRIGGER ) ) { # if 1 < T1_NOF_CORES T1_afterXevents = (T1_uint16_t)afterXevnts; ++T1_coreTriggerCounter[T1_CONT_RC_UNMAP( coreId )]; # else /* single core */ (void)T1_SetStopTrigger( afterXevnts ); # endif /* 1 < T1_NOF_CORES */ } } void T1_CODE T1_ContCsrnCallbackPC( T1_uint8Least_t coreId, T1_resultTime_t result, T1_csrnIdx_t idx, T1_nofEntries_t afterXevnts ) { /* No interrupt protection is required for default T1_ContCsrnCallbackNoSuspPC. */ T1_ContCsrnCallbackNoSuspPC( coreId, result, idx, afterXevnts ); } void T1_CODE T1_ContCPULoadCallbackPC( T1_uint8Least_t coreId, T1_uint32_t cpuLoadFrac, T1_uint8Least_t cpuLoadThreshold, T1_nofEntries_t afterXevnts ) { /* CPU load denominator (Nenner) in the range [0x8000..0xFFFF] */ T1_uint16Least_t const to = (T1_uint16Least_t)(cpuLoadFrac >> 16); /* CPU load numerator (Zaehler) in the range [0x0000..to] */ T1_uint16Least_t const te = (T1_uint16Least_t)(cpuLoadFrac & 0xFFFFu); (void)coreId; /* Suppress warnings if T1_CONT_RC_UNMAP does not use coreId */ T1_SuspendAllInterruptsPC( T1_CONT_RC_UNMAP( coreId ) ); if( T1_CONT_CPU_OVERLOAD( to, te, cpuLoadThreshold ) ) { T1_uint8Least_t const cpuLoadPercent = (T1_uint8Least_t)((te * 200uL + 1) / to) / 2u; if( T1_IsFeatureEnabled( T1_AF_ALLOW_TRIGGER ) ) { T1_AppSetStopTriggerAllCores( T1_CONT_RC_UNMAP( coreId ), afterXevnts ); } # if 1 == T1_NOF_CORES T1_TraceEventNoSuspUMPC( 0u, T1_COMBINE_EVENT_INFO( T1_UE_CPU_LOAD_CALLBACK_CORE0, cpuLoadPercent ) ); # else /* 1 < T1_NOF_CORES */ T1_TraceEventNoSuspUMPC( T1_CONT_RC_UNMAP( coreId ), T1_COMBINE_EVENT_INFO( T1_UE_CPU_LOAD_CALLBACK_CORE0 + coreId, cpuLoadPercent ) ); # endif /* 1 == T1_NOF_CORES */ } T1_ResumeAllInterruptsPC( T1_CONT_RC_UNMAP( coreId ) ); T1_CONT_CPU_LOAD_EXTRAS( coreId, cpuLoadFrac, cpuLoadThreshold ); } void T1_CODE T1_ContErrCallbackPC( T1_uint8Least_t coreId, T1_uint8Least_t errMask, T1_uint8Least_t triggerMask, T1_nofEntries_t afterXevnts ) { (void)coreId; /* Suppress warnings if T1_CONT_RC_UNMAP does not use coreId */ INC_T1_ERROR_COUNT( coreId ); # if 1 == T1_NOF_CORES T1_TraceEventUMPC( 0u, T1_COMBINE_EVENT_INFO( T1_UE_T1_CONT_ERR_CORE0, errMask ) ); # else /* 1 < T1_NOF_CORES */ T1_TraceEventUMPC( T1_CONT_RC_UNMAP( coreId ), T1_COMBINE_EVENT_INFO( T1_UE_T1_CONT_ERR_CORE0 + coreId, errMask ) ); # endif /* 1 == T1_NOF_CORES */ if( T1_IsFeatureEnabled( T1_AF_ALLOW_TRIGGER ) && (0 != (errMask & triggerMask)) ) { T1_AppSetStopTriggerAllCores( T1_CONT_RC_UNMAP( coreId ), afterXevnts ); } } void T1_CODE T1_ContOHCallbackPC( T1_uint8Least_t coreId, T1_uint8Least_t errMask ) { (void)coreId; /* Suppress warnings if T1_CONT_RC_UNMAP does not use coreId */ if( 0u == (T1_INF_OVERHEADS_UPDATED & errMask) ) { /* Overheads were not updated */ INC_T1_ERROR_COUNT( coreId ); } /* Free T1.cont event chains used for calibration */ T1_CONT_STOP_CALIBRATION_PC( coreId ); T1_ContResetResultsPC( coreId ); } T1_resultTime_t T1_CODE T1_ContStartStopCETPC( T1_UNUSED( T1_uint8Least_t coreId ), T1_UNUSED( T1_taskIdx_t taskIdx ) ) { /* T1_START_STOP is not used */ return 0uL; } # if ! defined T1_70618 void T1_CODE T1_49672( T1_UNUSED( T1_uint8Least_t coreId ), T1_UNUSED( T1_taskIdx_t taskIdx ), T1_UNUSED( T1_resultTime_t taskCET ) ) { } void T1_CODE T1_84399( T1_UNUSED( T1_uint8Least_t coreId ), T1_UNUSED( T1_longTime_t now ) ) { } # endif /* ! defined T1_70618 */ # define T1_STOP_SEC_CODE # include "T1_MemMap.h" # endif /* ! defined T1_DISABLE_T1_CONT */ /*----------------------------------------------------------------------------------*/ /*--- T1.scope configuration -------------------------------------------------------*/ /*----------------------------------------------------------------------------------*/ # if ! defined T1_DISABLE_T1_SCOPE # define T1_START_SEC_VAR_CLEARED_32 # include "T1_MemMap.h" /*! \brief Shared data for serializing calibration with Lamport's Bakery algorithm. */ T1_bakery_t T1_SEC_VAR_CLEARED_32 T1_calibrationSemPC[T1_NOF_CORES]; # define T1_STOP_SEC_VAR_CLEARED_32 # include "T1_MemMap.h" # define T1_START_SEC_CODE_FAST # include "T1_MemMap.h" # if defined __ghs__ /* Green Hills __noinline keyword can be disabled, so use the pragma instead. */ # pragma ghs startnoinline # endif /* defined __ghs__ */ T1_CODE_FAST( T1_tickUint_t ) T1_NOINLINE T1_CODE_OPT T1_TraceEventNoSusp__( T1_scopeConsts_t *pScopeConsts, T1_eventInfo_t eventInfo ) { # if defined T1_FG_CONT && ! defined T1_DISABLE_T1_CONT T1_uint8Least_t handlerIdx; T1_FG_CONT_GET_HANDLER_IDX( eventInfo, handlerIdx ); return T1_Dispatch2_( pScopeConsts, eventInfo, handlerIdx << 1 ); # else /* ! defined T1_FG_CONT || defined T1_DISABLE_T1_CONT */ return T1_TRACE_EVENT_NOSUSP_TIME( pScopeConsts, eventInfo, T1_GET_TRACE_TIME_PC( pScopeConsts->coreId ) ); # endif /* defined T1_FG_CONT && ! defined T1_DISABLE_T1_CONT */ } # if defined T1_NEAR_CODE_FAST T1_tickUint_t T1_NOINLINE T1_NEAR_CODE_FAST __attribute__((alias("T1_TraceEventNoSusp__"))) T1_NearTraceEventNoSusp__( T1_scopeConsts_t *pScopeConsts, T1_eventInfo_t eventInfo ); # endif /* defined T1_NEAR_CODE_FAST */ # if defined __ghs__ # pragma ghs endnoinline # endif /* defined __ghs__ */ # define T1_STOP_SEC_CODE_FAST # include "T1_MemMap.h" # define T1_START_SEC_CODE # include "T1_MemMap.h" T1_tickUint_t T1_CODE T1_TraceEventNoSuspUMPC( T1_uint8Least_t coreId, T1_eventInfo_t eventInfo ) { (void)coreId; /* Suppress warnings if coreId is not used */ # if defined T1_FLEX_UM_TRACE if( T1_IsT1FlexEnabledPC( coreId ) ) { return T1_FlexTraceEventPC_( coreId, eventInfo ); } # endif /* defined T1_FLEX_UM_TRACE */ # if defined T1_FG_CONT && ! defined T1_DISABLE_T1_CONT { T1_uint8Least_t handlerIdx; T1_FG_CONT_GET_HANDLER_IDX( eventInfo, handlerIdx ); return T1_DispatchTimePC( coreId, eventInfo, handlerIdx << 1, T1_GET_TRACE_TIME_UMPC( coreId ) ); } # else /* ! defined T1_FG_CONT || defined T1_DISABLE_T1_CONT */ return T1_FAR_TRACE_EVENT_NOSUSP_TIME( T1_CORE_ID_TO_SCOPE_CONSTS( coreId ), eventInfo, T1_GET_TRACE_TIME_UMPC( coreId ) ); # endif /* defined T1_FG_CONT && ! defined T1_DISABLE_T1_CONT */ } void T1_CODE T1_TraceEventUMPC( T1_uint8Least_t coreId, T1_eventInfo_t eventInfo ) { # if defined T1_FLEX_UM_TRACE if( T1_IsT1FlexEnabledPC( coreId ) ) { (void)T1_FlexTraceEventPC_( coreId, eventInfo ); return; } # endif /* defined T1_FLEX_UM_TRACE */ T1_SuspendAllInterruptsPC( coreId ); (void)T1_TraceEventNoSuspUMPC( coreId, eventInfo ); T1_ResumeAllInterruptsPC( coreId ); } T1_tickUint_t T1_CODE T1_GetTraceTime( void ) { # if ! defined T1_GET_RAW_TIME || ! defined T1_RAW_TO_TRACE_TIME T1_uint8Least_t const coreId = T1_GetCoreIdOffset( ); # endif /* ! defined T1_GET_RAW_TIME || ! defined T1_RAW_TO_TRACE_TIME */ return T1_GET_TRACE_TIME_PC( coreId ); } T1_tickUint_t T1_CODE T1_GetTraceTimeUM( void ) { # if ! defined T1_GET_RAW_TIME || ! defined T1_RAW_TO_TRACE_TIME T1_uint8Least_t coreId = T1_GetCoreIdOffset( ); # endif /* ! defined T1_GET_RAW_TIME || ! defined T1_RAW_TO_TRACE_TIME */ return T1_GET_TRACE_TIME_UMPC( coreId ); } # if defined __ghs__ /* Green Hills __noinline keyword can be disabled, so use the pragma instead. */ # pragma ghs startnoinline # endif /* defined __ghs__ */ void T1_NOINLINE T1_CODE T1_GetTraceAndSyncTimeNoSuspPC( T1_uint8Least_t coreId, T1_syncTimerBase_t *pSyncTimerBase ) { T1_uint32_t syncTime; T1_tickUint_t traceTime; # if /* always defined to 0 or 1 */ T1_ALL_TRACE_TIMERS_ARE_SYNC_TIMER (void)coreId; /* Suppress warnings since coreId is not actually used */ syncTime = T1_GET_SYNC_TIME( ); traceTime = syncTime; # else /* at least one trace timer is not the sync timer */ # if defined T1_GET_RAW_TIME && defined T1_RAW_TO_TRACE_TIME syncTime = T1_GET_SYNC_TIME( ); traceTime = T1_RAW_TO_TRACE_TIME( T1_GET_RAW_TIME( ) ); # else /* different timer/speeds for different cores */ switch( coreId ) { # if ! T1_TRACE_TIMER_IS_SYNC_TIMER_CORE0 case 0u: syncTime = T1_GET_SYNC_TIME( ); traceTime = T1_RAW_TO_TRACE_TIME_CORE0( T1_GET_RAW_TIME_CORE0( ) ); break; # endif /* ! T1_TRACE_TIMER_IS_SYNC_TIMER_CORE0 */ # if 2 <= T1_NOF_CORES && ! T1_TRACE_TIMER_IS_SYNC_TIMER_CORE1 case 1u: syncTime = T1_GET_SYNC_TIME( ); traceTime = T1_RAW_TO_TRACE_TIME_CORE1( T1_GET_RAW_TIME_CORE1( ) ); break; # endif /* 2 <= T1_NOF_CORES && ! T1_TRACE_TIMER_IS_SYNC_TIMER_CORE1 */ # if 3 <= T1_NOF_CORES && ! T1_TRACE_TIMER_IS_SYNC_TIMER_CORE2 case 2u: syncTime = T1_GET_SYNC_TIME( ); traceTime = T1_RAW_TO_TRACE_TIME_CORE2( T1_GET_RAW_TIME_CORE2( ) ); break; # endif /* 3 <= T1_NOF_CORES && ! T1_TRACE_TIMER_IS_SYNC_TIMER_CORE2 */ # if 4 <= T1_NOF_CORES && ! T1_TRACE_TIMER_IS_SYNC_TIMER_CORE3 case 3u: syncTime = T1_GET_SYNC_TIME( ); traceTime = T1_RAW_TO_TRACE_TIME_CORE3( T1_GET_RAW_TIME_CORE3( ) ); break; # endif /* 4 <= T1_NOF_CORES && ! T1_TRACE_TIMER_IS_SYNC_TIMER_CORE3 */ # if 5 <= T1_NOF_CORES && ! T1_TRACE_TIMER_IS_SYNC_TIMER_CORE4 case 4u: syncTime = T1_GET_SYNC_TIME( ); traceTime = T1_RAW_TO_TRACE_TIME_CORE4( T1_GET_RAW_TIME_CORE4( ) ); break; # endif /* 5 <= T1_NOF_CORES && ! T1_TRACE_TIMER_IS_SYNC_TIMER_CORE4 */ # if 6 <= T1_NOF_CORES && ! T1_TRACE_TIMER_IS_SYNC_TIMER_CORE5 case 5u: syncTime = T1_GET_SYNC_TIME( ); traceTime = T1_RAW_TO_TRACE_TIME_CORE5( T1_GET_RAW_TIME_CORE5( ) ); break; # endif /* 6 <= T1_NOF_CORES && ! T1_TRACE_TIMER_IS_SYNC_TIMER_CORE5 */ default: syncTime = T1_GET_SYNC_TIME( ); traceTime = syncTime; break; } # endif /* defined T1_GET_RAW_TIME && defined T1_RAW_TO_TRACE_TIME */ # endif /* T1_ALL_TRACE_TIMERS_ARE_SYNC_TIMER */ # if T1_SYNC_TIMER_WIDTH_BITS < 32 /* Extend sync timer to 32-bit value */ syncTime = pSyncTimerBase->syncTime + T1_TRUNC_SYNC_GET(syncTime - pSyncTimerBase->syncTime); # endif /* T1_SYNC_TIMER_WIDTH_BITS < 32 */ pSyncTimerBase->syncTime = syncTime; pSyncTimerBase->traceTime = traceTime; } # if defined __ghs__ # pragma ghs endnoinline # endif /* defined __ghs__ */ void T1_CODE T1_GetTraceAndSyncTimeNoSuspUMPC( T1_uint8Least_t coreId, T1_syncTimerBase_t *pSyncTimerBase ) { T1_GetTraceAndSyncTimeNoSuspPC( coreId, pSyncTimerBase ); } void T1_CODE T1_ScopeOverheadSequenceUMPC( T1_uint8Least_t coreId ) { T1_SuspendAllInterruptsPC( coreId ); T1_ScopeOverheadSequenceNoSuspPC( coreId ); T1_ResumeAllInterruptsPC( coreId ); } # define T1_STOP_SEC_CODE # include "T1_MemMap.h" # if defined T1_DISABLE_T1_FLEX # define T1_START_SEC_CODE # include "T1_MemMap.h" void T1_CODE T1_FlexOHAddrPC( T1_uint8Least_t coreId, T1_uint32_t pAddrStart ) { /* Empty function to allow linkage when T1.flex is disabled. */ } # define T1_STOP_SEC_CODE # include "T1_MemMap.h" # endif /* defined T1_DISABLE_T1_FLEX */ # endif /* ! defined T1_DISABLE_T1_SCOPE */ /*----------------------------------------------------------------------------------*/ /*--- T1.flex configuration --------------------------------------------------------*/ /*----------------------------------------------------------------------------------*/ # if ! defined T1_DISABLE_T1_FLEX # define T1_START_SEC_CONST_32 # include "T1_MemMap.h" void (* const T1_pAppHardFaultHandler)( void ) T1_SEC_CONST_32 = Os_Hard_Fault_Exception_Handler; # define T1_STOP_SEC_CONST_32 # include "T1_MemMap.h" # define T1_START_SEC_CODE # include "T1_MemMap.h" T1_bool_t T1_CODE T1_FlexAllowExternalDebug( void ) { # if defined T1_TRICORE && ! defined T1_FLEX_DISABLE_WITH_DEBUGGER return T1_TRUE; # elif defined T1_MPC5XXX && ! defined T1_FLEX_DISABLE_WITH_DEBUGGER return T1_FlexAllowMPCExternalDebug( ); # else /* defined T1_FLEX_DISABLE_WITH_DEBUGGER */ return T1_FALSE; # endif /* defined T1_TRICORE && ! defined T1_FLEX_DISABLE_WITH_DEBUGGER */ } # define T1_STOP_SEC_CODE # include "T1_MemMap.h" /*----------------------------------------------------------------------------------*/ # if defined T1_MPC5XXX # define T1_START_SEC_CODE_FAST # include "T1_MemMap.h" T1_EXTERN T1_CODE_FAST( void ) T1_CODE_OPT T1_ExceptionHandler( T1_uint32_t param1, T1_uint32_t param2, T1_uint32_t param3, T1_uint32_t param4, T1_flexGlobals_t *pFlexGlobals ); T1_EXTERN T1_CODE_FAST( void ) T1_CODE_OPT T1_PreExceptionHandler( T1_uint32_t param1, T1_uint32_t param2, T1_uint32_t param3, T1_uint32_t param4 ); /*! \brief T1 helper function. Do not edit. */ T1_CODE_FAST( void ) T1_CODE_OPT T1_PreExceptionHandler( T1_uint32_t param1, T1_uint32_t param2, T1_uint32_t param3, T1_uint32_t param4 ) { T1_ExceptionHandler( param1, param2, param3, param4, # if 1 == T1_NOF_CORES T1_P_FLEX_GLOBALS0 ); # elif 2 == T1_NOF_CORES /* For exactly two cores it is faster to use the ?: operator */ ( 0u == T1_GetCoreIdOffset( ) ) ? T1_P_FLEX_GLOBALS0 : T1_P_FLEX_GLOBALS1 ); # else /* More than 2 cores */ T1_flexGlobalsPC[T1_GetCoreIdOffset( )] ); # endif /* T1_NOF_CORES */ } # define T1_STOP_SEC_CODE_FAST # include "T1_MemMap.h" # elif /* ! defined T1_MPC5XXX && */ defined T1_ARM7R || defined T1_ARM8R /*----------------------------------------------------------------------------------*/ # define T1_START_SEC_CODE_FAST # include "T1_MemMap.h" T1_EXTERN # if defined T1_NEAR_CODE_FAST void T1_NEAR_CODE_FAST # else T1_CODE_FAST( void ) # endif /* defined T1_NEAR_CODE_FAST */ T1_ExceptionHandlerCode( T1_uint32_t param1, T1_uint32_t param2, T1_flexGlobals_t *pFlexGlobals, T1_uint32_t param3 ); T1_EXTERN T1_CODE_FAST( void ) T1_CODE_OPT T1_PreExceptionHandlerCode( T1_uint32_t param1, T1_uint32_t param2, T1_uint32_t unused, T1_uint32_t param3 ); /*! \brief T1 helper function. Do not edit. */ T1_CODE_FAST( void ) T1_CODE_OPT T1_PreExceptionHandlerCode( T1_uint32_t param1, T1_uint32_t param2, T1_UNUSED( T1_uint32_t unused ), T1_uint32_t param3 ) { T1_ExceptionHandlerCode( param1, param2, # if 1 == T1_NOF_CORES T1_P_FLEX_GLOBALS0, # elif 2 == T1_NOF_CORES /* For exactly two cores it is faster to use the ?: operator */ ( 0u == T1_GetCoreIdOffset( ) ) ? T1_P_FLEX_GLOBALS0 : T1_P_FLEX_GLOBALS1, # else /* More than 2 cores */ T1_flexGlobalsPC[T1_GetCoreIdOffset( )], # endif /* T1_NOF_CORES */ param3 ); } /*----------------------------------------------------------------------------------*/ T1_EXTERN # if defined T1_NEAR_CODE_FAST void T1_NEAR_CODE_FAST # else T1_CODE_FAST( void ) # endif /* defined T1_NEAR_CODE_FAST */ T1_ExceptionHandlerData( T1_uint32_t param1, T1_uint32_t param2, T1_flexGlobals_t *pFlexGlobals ); T1_EXTERN T1_CODE_FAST( void ) T1_CODE_OPT T1_PreExceptionHandlerData( T1_uint32_t param1, T1_uint32_t param2 ); /*! \brief T1 helper function. Do not edit. */ T1_CODE_FAST( void ) T1_CODE_OPT T1_PreExceptionHandlerData( T1_uint32_t param1, T1_uint32_t param2 ) { T1_ExceptionHandlerData( param1, param2, # if 1 == T1_NOF_CORES T1_P_FLEX_GLOBALS0 ); # elif 2 == T1_NOF_CORES /* For exactly two cores it is faster to use the ?: operator */ ( 0u == T1_GetCoreIdOffset( ) ) ? T1_P_FLEX_GLOBALS0 : T1_P_FLEX_GLOBALS1 ); # else /* More than 2 cores */ T1_flexGlobalsPC[T1_GetCoreIdOffset( )] ); # endif /* T1_NOF_CORES */ } # define T1_STOP_SEC_CODE_FAST # include "T1_MemMap.h" # elif /* ! defined T1_MPC5XXX && ! defined T1_ARM7R && ! defined T1_ARM8R && */ defined T1_ARM7M /*----------------------------------------------------------------------------------*/ # define T1_START_SEC_CODE_FAST # include "T1_MemMap.h" /*! \brief T1 helper function. Do not edit. */ T1_CODE_FAST( void ) T1_CODE_OPT T1_DebugMonitorHandler( void ) { # if defined T1_NEAR_CODE_FAST void T1_NEAR_CODE_FAST # else T1_CODE_FAST( void ) # endif /* defined T1_NEAR_CODE_FAST */ T1_CODE_OPT T1_DebugMonitorHandler_( T1_flexGlobals_t *pFlexGlobals ); T1_DebugMonitorHandler_( # if 1 == T1_NOF_CORES T1_P_FLEX_GLOBALS0 ); # elif 2 == T1_NOF_CORES /* For exactly two cores it is faster to use the ?: operator */ ( 0u == T1_GetCoreIdOffset( ) ) ? T1_P_FLEX_GLOBALS0 : T1_P_FLEX_GLOBALS1 ); # else /* More than 2 cores */ T1_flexGlobalsPC[T1_GetCoreIdOffset( )] ); # endif /* 1 == T1_NOF_CORES */ } # define T1_STOP_SEC_CODE_FAST # include "T1_MemMap.h" # endif /* defined T1_MPC5XXX */ # endif /* ! defined T1_DISABLE_T1_FLEX */ #endif /* defined T1_ENABLE */ #if ! defined T1_ENABLE || defined T1_DISABLE_T1_FLEX # define T1_START_SEC_CODE_FAST # include "T1_MemMap.h" /* * TODO * If T1.flex is integrated in the vector table, define the T1.flex exception handler * entry point(s), to allow linking when T1.flex is disabled to forward the exception * to an existing handler, as a jump to either * (a) the unexpected exception handler, or * (b) the handler to which T1.flex would have forwarded a non-T1 exception, cf. * ARM-7R T1_pAppHandlers * If there is really no suitable, existing handler, use an infinite loop to * demonstrate that this code is never reached. */ void T1_CODE T1_DebugMonitorHandler( void ) { /* Loop forever if HFSR contains only DEBUGEVT. */ while(0uL == (*(volatile T1_uint32_t *)0xE000ED2CuL<<1)) ; # if defined __GNUC__ /* Force "far" jump. */ __asm( "bx %0" : : "r"(Os_Hard_Fault_Exception_Handler) ); # else /* * Check that compiler jumps to HardFaultHandler * (B/BX not BL/BLX) cf. tail-call optimization */ Os_Hard_Fault_Exception_Handler( ); # endif } # define T1_STOP_SEC_CODE_FAST # include "T1_MemMap.h" #endif /* ! defined T1_ENABLE || defined T1_DISABLE_T1_FLEX */ /*----------------------------------------------------------------------------------*/ /*--- documentation ----------------------------------------------------------------*/ /*----------------------------------------------------------------------------------*/ #if defined T1_DOXYGEN_ONLY /*! * \def T1_GET_TRACE_TIME_PC * This macro is generated in T1_config.h depending on the timers configuration. * \returns the trace timer count register scaled to trace timer ticks */ /*! * \brief Disable the plug-in T1.cont, see \ref SWITCH_PLUGINS. */ #define T1_DISABLE_T1_CONT (1) /*! * \brief Disable the plug-in T1.flex, see \ref SWITCH_PLUGINS. */ #define T1_DISABLE_T1_FLEX (1) /*! * \brief Disable the plug-in T1.delay, see \ref SWITCH_PLUGINS. */ #define T1_DISABLE_T1_DELAY (1) /*! * \brief Disable the plug-in T1.mod, see \ref SWITCH_PLUGINS. */ #define T1_DISABLE_T1_MOD (1) /*! * \brief Enable preemption counting to enhance T1.flex restricted measurements. * By counting preemption levels and comparing the current level with that * at the start of the restriction, T1.flex restricted measurements can discount * accesses that occur not within the restriction function itself but within tasks and * ISRs that preempt the restriction function. * This macro must be defined globally, for example before all includes in * T1_AppInterface.h. * This macro is not relevant to foreground T1.cont, which considers pre-emption (with * no additional overhead), see #T1_FG_CONT. * If this macro is not defined at compile time, there is no additional overhead at * T1_TraceStart(), T1_TraceStop(), T1_TraceResume() and T1_TraceWait(). */ #define T1_COUNT_PREEMPTION (1) /*! * \brief Enable remote T1.cont * Macro defined if the invocation parameter -contRunsOnCore is set on * any core. This indicates to the T1-TARGET-SW that one core is running the * T1_ContBgHandlerPC() of another core. * T1_DisableT1HandlerPC() and T1_EnableT1HandlerPC() must be implemented to allow * mutual exclusion between T1_HandlerPC() on one core and T1_ContBgHandlerPC() on the * other. * Note that remote core T1.cont cannot be used simultaneously with foreground * T1.cont, see #T1_FG_CONT. */ #define T1_CONT_REMOTE (1) /*! * \brief Enable foreground T1.cont. * Note that foreground T1.cont cannot be used simultaneously with remote core * T1.cont, see #T1_CONT_REMOTE. */ #define T1_FG_CONT (1) /*! * \brief Enable the T1-TARGET-SW, see \ref SWITCH. */ #define T1_ENABLE (1) /*! * \brief Support timer overflow with \ref FOREGROUND_CONT. * Indicates that foreground T1.cont should fully support any interval that can * be measured with the full trace timer. For example, if the trace timer has 24 * counting bits, any interval less than 2^24 will be correctly handled both by * foreground T1.cont and by T1.scope in the downloaded or streamed traces. * Such long intervals are handled by inserting #T1_EMPTY events into the trace, * consuming execution time and trace memory proportional to the number of * additional events required. */ #define T1_SUPPORT_TIMER_OVERFLOW (1) /*! * \brief Check for timer overflow with \ref FOREGROUND_CONT. * Indicates that foreground T1.cont should just check for an interval greater than * or equal to 2^16 . If such a long interval is encountered, a discontinuity event * will be inserted in order to prevent any incorrect results being reported by * T1.scope. This check has a minimal overhead, typically 2 or 3 instructions, and * the discontinuity has no impact on foreground T1.cont. It does, inevitably, * result in a gap in the analysis for T1.scope. If the small additional overhead * can be tolerated, this is an attractive option for a new integration using * foreground T1.cont. */ #define T1_DETECT_TIMER_OVERFLOW (1) #endif /* T1_DOXYGEN_ONLY */