/*********************************************************************************//*!
*   \file           T1_MemMap.h
*
*   \brief          This header selects the T1-TARGET-SW sections for
*                   the GHS compiler.
*
*   \par Visibility
*                   External
*
*   \author         Generated file
*
*   \version 3.3.0.1 r53468
*
*   \copyright GLIWA GmbH embedded systems, Weilheim i.OB. All rights reserved
*************************************************************************************/

#if 0

#elif defined T1_START_SEC_CODE
#   undef T1_START_SEC_CODE
#   pragma ghs section text=".T1_code"
#elif defined T1_STOP_SEC_CODE
#   undef T1_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_CORE0_START_SEC_CODE
#   undef T1_CORE0_START_SEC_CODE
#   pragma ghs section text=".T1_codeCore0"
#elif defined T1_CORE0_STOP_SEC_CODE
#   undef T1_CORE0_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_CORE1_START_SEC_CODE
#   undef T1_CORE1_START_SEC_CODE
#   pragma ghs section text=".T1_codeCore1"
#elif defined T1_CORE1_STOP_SEC_CODE
#   undef T1_CORE1_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_CORE2_START_SEC_CODE
#   undef T1_CORE2_START_SEC_CODE
#   pragma ghs section text=".T1_codeCore2"
#elif defined T1_CORE2_STOP_SEC_CODE
#   undef T1_CORE2_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_CORE3_START_SEC_CODE
#   undef T1_CORE3_START_SEC_CODE
#   pragma ghs section text=".T1_codeCore3"
#elif defined T1_CORE3_STOP_SEC_CODE
#   undef T1_CORE3_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_CORE4_START_SEC_CODE
#   undef T1_CORE4_START_SEC_CODE
#   pragma ghs section text=".T1_codeCore4"
#elif defined T1_CORE4_STOP_SEC_CODE
#   undef T1_CORE4_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_CORE5_START_SEC_CODE
#   undef T1_CORE5_START_SEC_CODE
#   pragma ghs section text=".T1_codeCore5"
#elif defined T1_CORE5_STOP_SEC_CODE
#   undef T1_CORE5_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_CORE6_START_SEC_CODE
#   undef T1_CORE6_START_SEC_CODE
#   pragma ghs section text=".T1_codeCore6"
#elif defined T1_CORE6_STOP_SEC_CODE
#   undef T1_CORE6_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_CORE7_START_SEC_CODE
#   undef T1_CORE7_START_SEC_CODE
#   pragma ghs section text=".T1_codeCore7"
#elif defined T1_CORE7_STOP_SEC_CODE
#   undef T1_CORE7_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_CORE8_START_SEC_CODE
#   undef T1_CORE8_START_SEC_CODE
#   pragma ghs section text=".T1_codeCore8"
#elif defined T1_CORE8_STOP_SEC_CODE
#   undef T1_CORE8_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_CORE9_START_SEC_CODE
#   undef T1_CORE9_START_SEC_CODE
#   pragma ghs section text=".T1_codeCore9"
#elif defined T1_CORE9_STOP_SEC_CODE
#   undef T1_CORE9_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_CORE10_START_SEC_CODE
#   undef T1_CORE10_START_SEC_CODE
#   pragma ghs section text=".T1_codeCore10"
#elif defined T1_CORE10_STOP_SEC_CODE
#   undef T1_CORE10_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_CORE11_START_SEC_CODE
#   undef T1_CORE11_START_SEC_CODE
#   pragma ghs section text=".T1_codeCore11"
#elif defined T1_CORE11_STOP_SEC_CODE
#   undef T1_CORE11_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_CORE12_START_SEC_CODE
#   undef T1_CORE12_START_SEC_CODE
#   pragma ghs section text=".T1_codeCore12"
#elif defined T1_CORE12_STOP_SEC_CODE
#   undef T1_CORE12_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_CORE13_START_SEC_CODE
#   undef T1_CORE13_START_SEC_CODE
#   pragma ghs section text=".T1_codeCore13"
#elif defined T1_CORE13_STOP_SEC_CODE
#   undef T1_CORE13_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_CORE14_START_SEC_CODE
#   undef T1_CORE14_START_SEC_CODE
#   pragma ghs section text=".T1_codeCore14"
#elif defined T1_CORE14_STOP_SEC_CODE
#   undef T1_CORE14_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_DMS_START_SEC_CODE
#   undef T1_DMS_START_SEC_CODE
#   pragma ghs section text=".T1_codeDMS"
#elif defined T1_DMS_STOP_SEC_CODE
#   undef T1_DMS_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_DMS_CORE0_START_SEC_CODE
#   undef T1_DMS_CORE0_START_SEC_CODE
#   pragma ghs section text=".T1_codeDMSCore0"
#elif defined T1_DMS_CORE0_STOP_SEC_CODE
#   undef T1_DMS_CORE0_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_DMS_CORE1_START_SEC_CODE
#   undef T1_DMS_CORE1_START_SEC_CODE
#   pragma ghs section text=".T1_codeDMSCore1"
#elif defined T1_DMS_CORE1_STOP_SEC_CODE
#   undef T1_DMS_CORE1_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_DMS_CORE2_START_SEC_CODE
#   undef T1_DMS_CORE2_START_SEC_CODE
#   pragma ghs section text=".T1_codeDMSCore2"
#elif defined T1_DMS_CORE2_STOP_SEC_CODE
#   undef T1_DMS_CORE2_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_DMS_CORE3_START_SEC_CODE
#   undef T1_DMS_CORE3_START_SEC_CODE
#   pragma ghs section text=".T1_codeDMSCore3"
#elif defined T1_DMS_CORE3_STOP_SEC_CODE
#   undef T1_DMS_CORE3_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_DMS_CORE4_START_SEC_CODE
#   undef T1_DMS_CORE4_START_SEC_CODE
#   pragma ghs section text=".T1_codeDMSCore4"
#elif defined T1_DMS_CORE4_STOP_SEC_CODE
#   undef T1_DMS_CORE4_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_DMS_CORE5_START_SEC_CODE
#   undef T1_DMS_CORE5_START_SEC_CODE
#   pragma ghs section text=".T1_codeDMSCore5"
#elif defined T1_DMS_CORE5_STOP_SEC_CODE
#   undef T1_DMS_CORE5_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_DMS_CORE6_START_SEC_CODE
#   undef T1_DMS_CORE6_START_SEC_CODE
#   pragma ghs section text=".T1_codeDMSCore6"
#elif defined T1_DMS_CORE6_STOP_SEC_CODE
#   undef T1_DMS_CORE6_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_DMS_CORE7_START_SEC_CODE
#   undef T1_DMS_CORE7_START_SEC_CODE
#   pragma ghs section text=".T1_codeDMSCore7"
#elif defined T1_DMS_CORE7_STOP_SEC_CODE
#   undef T1_DMS_CORE7_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_DMS_CORE8_START_SEC_CODE
#   undef T1_DMS_CORE8_START_SEC_CODE
#   pragma ghs section text=".T1_codeDMSCore8"
#elif defined T1_DMS_CORE8_STOP_SEC_CODE
#   undef T1_DMS_CORE8_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_DMS_CORE9_START_SEC_CODE
#   undef T1_DMS_CORE9_START_SEC_CODE
#   pragma ghs section text=".T1_codeDMSCore9"
#elif defined T1_DMS_CORE9_STOP_SEC_CODE
#   undef T1_DMS_CORE9_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_DMS_CORE10_START_SEC_CODE
#   undef T1_DMS_CORE10_START_SEC_CODE
#   pragma ghs section text=".T1_codeDMSCore10"
#elif defined T1_DMS_CORE10_STOP_SEC_CODE
#   undef T1_DMS_CORE10_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_DMS_CORE11_START_SEC_CODE
#   undef T1_DMS_CORE11_START_SEC_CODE
#   pragma ghs section text=".T1_codeDMSCore11"
#elif defined T1_DMS_CORE11_STOP_SEC_CODE
#   undef T1_DMS_CORE11_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_DMS_CORE12_START_SEC_CODE
#   undef T1_DMS_CORE12_START_SEC_CODE
#   pragma ghs section text=".T1_codeDMSCore12"
#elif defined T1_DMS_CORE12_STOP_SEC_CODE
#   undef T1_DMS_CORE12_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_DMS_CORE13_START_SEC_CODE
#   undef T1_DMS_CORE13_START_SEC_CODE
#   pragma ghs section text=".T1_codeDMSCore13"
#elif defined T1_DMS_CORE13_STOP_SEC_CODE
#   undef T1_DMS_CORE13_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_DMS_CORE14_START_SEC_CODE
#   undef T1_DMS_CORE14_START_SEC_CODE
#   pragma ghs section text=".T1_codeDMSCore14"
#elif defined T1_DMS_CORE14_STOP_SEC_CODE
#   undef T1_DMS_CORE14_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_DMS_CLONE_START_SEC_CODE
#   undef T1_DMS_CLONE_START_SEC_CODE
#   pragma ghs section text=".T1_codeDMSClone"
#elif defined T1_DMS_CLONE_STOP_SEC_CODE
#   undef T1_DMS_CLONE_STOP_SEC_CODE
#   pragma ghs section text=default

#elif defined T1_START_SEC_CODE_FAST
#   undef T1_START_SEC_CODE_FAST
#   pragma ghs section text=".T1_codeFast"
#elif defined T1_STOP_SEC_CODE_FAST
#   undef T1_STOP_SEC_CODE_FAST
#   pragma ghs section text=default

#elif defined T1_START_SEC_CONST_8
#   undef T1_START_SEC_CONST_8
#   pragma ghs section rodata=".T1_const"
#   pragma ghs startdata
#elif defined T1_STOP_SEC_CONST_8
#   undef T1_STOP_SEC_CONST_8
#   pragma ghs section rodata=default
#   pragma ghs enddata

#elif defined T1_START_SEC_CONST_16
#   undef T1_START_SEC_CONST_16
#   pragma ghs section rodata=".T1_const"
#   pragma ghs startdata
#elif defined T1_STOP_SEC_CONST_16
#   undef T1_STOP_SEC_CONST_16
#   pragma ghs section rodata=default
#   pragma ghs enddata

#elif defined T1_START_SEC_CONST_32
#   undef T1_START_SEC_CONST_32
#   pragma ghs section rodata=".T1_const"
#   pragma ghs startdata
#elif defined T1_STOP_SEC_CONST_32
#   undef T1_STOP_SEC_CONST_32
#   pragma ghs section rodata=default
#   pragma ghs enddata

#elif defined T1_CORE0_START_SEC_CONST_32
#   undef T1_CORE0_START_SEC_CONST_32
#   pragma ghs section rodata=".T1_constCore0"
#   pragma ghs startdata
#elif defined T1_CORE0_STOP_SEC_CONST_32
#   undef T1_CORE0_STOP_SEC_CONST_32
#   pragma ghs section rodata=default
#   pragma ghs enddata

#elif defined T1_CORE1_START_SEC_CONST_32
#   undef T1_CORE1_START_SEC_CONST_32
#   pragma ghs section rodata=".T1_constCore1"
#   pragma ghs startdata
#elif defined T1_CORE1_STOP_SEC_CONST_32
#   undef T1_CORE1_STOP_SEC_CONST_32
#   pragma ghs section rodata=default
#   pragma ghs enddata

#elif defined T1_CORE2_START_SEC_CONST_32
#   undef T1_CORE2_START_SEC_CONST_32
#   pragma ghs section rodata=".T1_constCore2"
#   pragma ghs startdata
#elif defined T1_CORE2_STOP_SEC_CONST_32
#   undef T1_CORE2_STOP_SEC_CONST_32
#   pragma ghs section rodata=default
#   pragma ghs enddata

#elif defined T1_CORE3_START_SEC_CONST_32
#   undef T1_CORE3_START_SEC_CONST_32
#   pragma ghs section rodata=".T1_constCore3"
#   pragma ghs startdata
#elif defined T1_CORE3_STOP_SEC_CONST_32
#   undef T1_CORE3_STOP_SEC_CONST_32
#   pragma ghs section rodata=default
#   pragma ghs enddata

#elif defined T1_CORE4_START_SEC_CONST_32
#   undef T1_CORE4_START_SEC_CONST_32
#   pragma ghs section rodata=".T1_constCore4"
#   pragma ghs startdata
#elif defined T1_CORE4_STOP_SEC_CONST_32
#   undef T1_CORE4_STOP_SEC_CONST_32
#   pragma ghs section rodata=default
#   pragma ghs enddata

#elif defined T1_CORE5_START_SEC_CONST_32
#   undef T1_CORE5_START_SEC_CONST_32
#   pragma ghs section rodata=".T1_constCore5"
#   pragma ghs startdata
#elif defined T1_CORE5_STOP_SEC_CONST_32
#   undef T1_CORE5_STOP_SEC_CONST_32
#   pragma ghs section rodata=default
#   pragma ghs enddata

#elif defined T1_CORE6_START_SEC_CONST_32
#   undef T1_CORE6_START_SEC_CONST_32
#   pragma ghs section rodata=".T1_constCore6"
#   pragma ghs startdata
#elif defined T1_CORE6_STOP_SEC_CONST_32
#   undef T1_CORE6_STOP_SEC_CONST_32
#   pragma ghs section rodata=default
#   pragma ghs enddata

#elif defined T1_CORE7_START_SEC_CONST_32
#   undef T1_CORE7_START_SEC_CONST_32
#   pragma ghs section rodata=".T1_constCore7"
#   pragma ghs startdata
#elif defined T1_CORE7_STOP_SEC_CONST_32
#   undef T1_CORE7_STOP_SEC_CONST_32
#   pragma ghs section rodata=default
#   pragma ghs enddata

#elif defined T1_CORE8_START_SEC_CONST_32
#   undef T1_CORE8_START_SEC_CONST_32
#   pragma ghs section rodata=".T1_constCore8"
#   pragma ghs startdata
#elif defined T1_CORE8_STOP_SEC_CONST_32
#   undef T1_CORE8_STOP_SEC_CONST_32
#   pragma ghs section rodata=default
#   pragma ghs enddata

#elif defined T1_CORE9_START_SEC_CONST_32
#   undef T1_CORE9_START_SEC_CONST_32
#   pragma ghs section rodata=".T1_constCore9"
#   pragma ghs startdata
#elif defined T1_CORE9_STOP_SEC_CONST_32
#   undef T1_CORE9_STOP_SEC_CONST_32
#   pragma ghs section rodata=default
#   pragma ghs enddata

#elif defined T1_CORE10_START_SEC_CONST_32
#   undef T1_CORE10_START_SEC_CONST_32
#   pragma ghs section rodata=".T1_constCore10"
#   pragma ghs startdata
#elif defined T1_CORE10_STOP_SEC_CONST_32
#   undef T1_CORE10_STOP_SEC_CONST_32
#   pragma ghs section rodata=default
#   pragma ghs enddata

#elif defined T1_CORE11_START_SEC_CONST_32
#   undef T1_CORE11_START_SEC_CONST_32
#   pragma ghs section rodata=".T1_constCore11"
#   pragma ghs startdata
#elif defined T1_CORE11_STOP_SEC_CONST_32
#   undef T1_CORE11_STOP_SEC_CONST_32
#   pragma ghs section rodata=default
#   pragma ghs enddata

#elif defined T1_CORE12_START_SEC_CONST_32
#   undef T1_CORE12_START_SEC_CONST_32
#   pragma ghs section rodata=".T1_constCore12"
#   pragma ghs startdata
#elif defined T1_CORE12_STOP_SEC_CONST_32
#   undef T1_CORE12_STOP_SEC_CONST_32
#   pragma ghs section rodata=default
#   pragma ghs enddata

#elif defined T1_CORE13_START_SEC_CONST_32
#   undef T1_CORE13_START_SEC_CONST_32
#   pragma ghs section rodata=".T1_constCore13"
#   pragma ghs startdata
#elif defined T1_CORE13_STOP_SEC_CONST_32
#   undef T1_CORE13_STOP_SEC_CONST_32
#   pragma ghs section rodata=default
#   pragma ghs enddata

#elif defined T1_CORE14_START_SEC_CONST_32
#   undef T1_CORE14_START_SEC_CONST_32
#   pragma ghs section rodata=".T1_constCore14"
#   pragma ghs startdata
#elif defined T1_CORE14_STOP_SEC_CONST_32
#   undef T1_CORE14_STOP_SEC_CONST_32
#   pragma ghs section rodata=default
#   pragma ghs enddata

#elif defined T1_CLONE_START_SEC_CONST_32
#   undef T1_CLONE_START_SEC_CONST_32
#   pragma ghs section rodata=".T1_constClone"
#   pragma ghs startdata
#elif defined T1_CLONE_STOP_SEC_CONST_32
#   undef T1_CLONE_STOP_SEC_CONST_32
#   pragma ghs section rodata=default
#   pragma ghs enddata

#elif defined T1_START_SEC_VAR_CLEARED_32
#   undef T1_START_SEC_VAR_CLEARED_32
#   pragma ghs section bss=".T1_clear"
#   pragma ghs startdata
#elif defined T1_STOP_SEC_VAR_CLEARED_32
#   undef T1_STOP_SEC_VAR_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=".T1_sbss"
#   pragma ghs startsda
#elif defined T1_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE0_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE0_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=".T1_sbssCore0"
#   pragma ghs startsda
#elif defined T1_CORE0_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE0_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE1_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE1_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=".T1_sbssCore1"
#   pragma ghs startsda
#elif defined T1_CORE1_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE1_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE2_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE2_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=".T1_sbssCore2"
#   pragma ghs startsda
#elif defined T1_CORE2_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE2_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE3_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE3_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=".T1_sbssCore3"
#   pragma ghs startsda
#elif defined T1_CORE3_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE3_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE4_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE4_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=".T1_sbssCore4"
#   pragma ghs startsda
#elif defined T1_CORE4_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE4_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE5_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE5_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=".T1_sbssCore5"
#   pragma ghs startsda
#elif defined T1_CORE5_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE5_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE6_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE6_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=".T1_sbssCore6"
#   pragma ghs startsda
#elif defined T1_CORE6_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE6_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE7_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE7_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=".T1_sbssCore7"
#   pragma ghs startsda
#elif defined T1_CORE7_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE7_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE8_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE8_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=".T1_sbssCore8"
#   pragma ghs startsda
#elif defined T1_CORE8_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE8_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE9_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE9_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=".T1_sbssCore9"
#   pragma ghs startsda
#elif defined T1_CORE9_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE9_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE10_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE10_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=".T1_sbssCore10"
#   pragma ghs startsda
#elif defined T1_CORE10_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE10_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE11_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE11_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=".T1_sbssCore11"
#   pragma ghs startsda
#elif defined T1_CORE11_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE11_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE12_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE12_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=".T1_sbssCore12"
#   pragma ghs startsda
#elif defined T1_CORE12_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE12_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE13_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE13_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=".T1_sbssCore13"
#   pragma ghs startsda
#elif defined T1_CORE13_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE13_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE14_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE14_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=".T1_sbssCore14"
#   pragma ghs startsda
#elif defined T1_CORE14_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE14_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE_COMMS_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE_COMMS_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=".T1_sbssCoreComms"
#   pragma ghs startsda
#elif defined T1_CORE_COMMS_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CORE_COMMS_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CLONE_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CLONE_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=".T1_sbssClone"
#   pragma ghs startsda
#elif defined T1_CLONE_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   undef T1_CLONE_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_8
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=".T1_sbss"
#   pragma ghs startsda
#elif defined T1_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE0_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE0_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=".T1_sbssCore0"
#   pragma ghs startsda
#elif defined T1_CORE0_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE0_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE1_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE1_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=".T1_sbssCore1"
#   pragma ghs startsda
#elif defined T1_CORE1_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE1_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE2_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE2_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=".T1_sbssCore2"
#   pragma ghs startsda
#elif defined T1_CORE2_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE2_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE3_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE3_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=".T1_sbssCore3"
#   pragma ghs startsda
#elif defined T1_CORE3_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE3_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE4_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE4_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=".T1_sbssCore4"
#   pragma ghs startsda
#elif defined T1_CORE4_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE4_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE5_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE5_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=".T1_sbssCore5"
#   pragma ghs startsda
#elif defined T1_CORE5_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE5_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE6_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE6_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=".T1_sbssCore6"
#   pragma ghs startsda
#elif defined T1_CORE6_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE6_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE7_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE7_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=".T1_sbssCore7"
#   pragma ghs startsda
#elif defined T1_CORE7_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE7_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE8_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE8_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=".T1_sbssCore8"
#   pragma ghs startsda
#elif defined T1_CORE8_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE8_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE9_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE9_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=".T1_sbssCore9"
#   pragma ghs startsda
#elif defined T1_CORE9_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE9_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE10_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE10_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=".T1_sbssCore10"
#   pragma ghs startsda
#elif defined T1_CORE10_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE10_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE11_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE11_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=".T1_sbssCore11"
#   pragma ghs startsda
#elif defined T1_CORE11_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE11_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE12_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE12_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=".T1_sbssCore12"
#   pragma ghs startsda
#elif defined T1_CORE12_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE12_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE13_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE13_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=".T1_sbssCore13"
#   pragma ghs startsda
#elif defined T1_CORE13_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE13_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE14_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE14_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=".T1_sbssCore14"
#   pragma ghs startsda
#elif defined T1_CORE14_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE14_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE_COMMS_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE_COMMS_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=".T1_sbssCoreComms"
#   pragma ghs startsda
#elif defined T1_CORE_COMMS_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CORE_COMMS_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CLONE_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CLONE_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=".T1_sbssClone"
#   pragma ghs startsda
#elif defined T1_CLONE_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   undef T1_CLONE_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_16
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=".T1_sbss"
#   pragma ghs startsda
#elif defined T1_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE0_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE0_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=".T1_sbssCore0"
#   pragma ghs startsda
#elif defined T1_CORE0_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE0_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE1_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE1_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=".T1_sbssCore1"
#   pragma ghs startsda
#elif defined T1_CORE1_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE1_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE2_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE2_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=".T1_sbssCore2"
#   pragma ghs startsda
#elif defined T1_CORE2_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE2_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE3_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE3_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=".T1_sbssCore3"
#   pragma ghs startsda
#elif defined T1_CORE3_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE3_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE4_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE4_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=".T1_sbssCore4"
#   pragma ghs startsda
#elif defined T1_CORE4_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE4_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE5_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE5_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=".T1_sbssCore5"
#   pragma ghs startsda
#elif defined T1_CORE5_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE5_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE6_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE6_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=".T1_sbssCore6"
#   pragma ghs startsda
#elif defined T1_CORE6_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE6_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE7_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE7_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=".T1_sbssCore7"
#   pragma ghs startsda
#elif defined T1_CORE7_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE7_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE8_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE8_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=".T1_sbssCore8"
#   pragma ghs startsda
#elif defined T1_CORE8_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE8_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE9_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE9_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=".T1_sbssCore9"
#   pragma ghs startsda
#elif defined T1_CORE9_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE9_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE10_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE10_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=".T1_sbssCore10"
#   pragma ghs startsda
#elif defined T1_CORE10_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE10_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE11_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE11_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=".T1_sbssCore11"
#   pragma ghs startsda
#elif defined T1_CORE11_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE11_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE12_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE12_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=".T1_sbssCore12"
#   pragma ghs startsda
#elif defined T1_CORE12_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE12_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE13_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE13_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=".T1_sbssCore13"
#   pragma ghs startsda
#elif defined T1_CORE13_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE13_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE14_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE14_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=".T1_sbssCore14"
#   pragma ghs startsda
#elif defined T1_CORE14_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE14_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CORE_COMMS_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE_COMMS_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=".T1_sbssCoreComms"
#   pragma ghs startsda
#elif defined T1_CORE_COMMS_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CORE_COMMS_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_CLONE_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CLONE_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=".T1_sbssClone"
#   pragma ghs startsda
#elif defined T1_CLONE_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   undef T1_CLONE_STOP_SEC_VAR_NEAR_POWER_ON_CLEARED_32
#   pragma ghs section sbss=default
#   pragma ghs endsda

#elif defined T1_START_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_START_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=".T1_bss"
#   pragma ghs startdata
#elif defined T1_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE0_START_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE0_START_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=".T1_bssCore0"
#   pragma ghs startdata
#elif defined T1_CORE0_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE0_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE1_START_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE1_START_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=".T1_bssCore1"
#   pragma ghs startdata
#elif defined T1_CORE1_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE1_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE2_START_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE2_START_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=".T1_bssCore2"
#   pragma ghs startdata
#elif defined T1_CORE2_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE2_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE3_START_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE3_START_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=".T1_bssCore3"
#   pragma ghs startdata
#elif defined T1_CORE3_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE3_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE4_START_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE4_START_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=".T1_bssCore4"
#   pragma ghs startdata
#elif defined T1_CORE4_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE4_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE5_START_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE5_START_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=".T1_bssCore5"
#   pragma ghs startdata
#elif defined T1_CORE5_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE5_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE6_START_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE6_START_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=".T1_bssCore6"
#   pragma ghs startdata
#elif defined T1_CORE6_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE6_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE7_START_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE7_START_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=".T1_bssCore7"
#   pragma ghs startdata
#elif defined T1_CORE7_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE7_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE8_START_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE8_START_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=".T1_bssCore8"
#   pragma ghs startdata
#elif defined T1_CORE8_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE8_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE9_START_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE9_START_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=".T1_bssCore9"
#   pragma ghs startdata
#elif defined T1_CORE9_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE9_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE10_START_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE10_START_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=".T1_bssCore10"
#   pragma ghs startdata
#elif defined T1_CORE10_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE10_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE11_START_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE11_START_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=".T1_bssCore11"
#   pragma ghs startdata
#elif defined T1_CORE11_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE11_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE12_START_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE12_START_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=".T1_bssCore12"
#   pragma ghs startdata
#elif defined T1_CORE12_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE12_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE13_START_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE13_START_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=".T1_bssCore13"
#   pragma ghs startdata
#elif defined T1_CORE13_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE13_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE14_START_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE14_START_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=".T1_bssCore14"
#   pragma ghs startdata
#elif defined T1_CORE14_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE14_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE_COMMS_START_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE_COMMS_START_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=".T1_bssCoreComms"
#   pragma ghs startdata
#elif defined T1_CORE_COMMS_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CORE_COMMS_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CLONE_START_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CLONE_START_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=".T1_bssClone"
#   pragma ghs startdata
#elif defined T1_CLONE_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   undef T1_CLONE_STOP_SEC_VAR_POWER_ON_CLEARED_8
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_START_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_START_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=".T1_bss"
#   pragma ghs startdata
#elif defined T1_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE0_START_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE0_START_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=".T1_bssCore0"
#   pragma ghs startdata
#elif defined T1_CORE0_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE0_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE1_START_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE1_START_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=".T1_bssCore1"
#   pragma ghs startdata
#elif defined T1_CORE1_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE1_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE2_START_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE2_START_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=".T1_bssCore2"
#   pragma ghs startdata
#elif defined T1_CORE2_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE2_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE3_START_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE3_START_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=".T1_bssCore3"
#   pragma ghs startdata
#elif defined T1_CORE3_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE3_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE4_START_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE4_START_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=".T1_bssCore4"
#   pragma ghs startdata
#elif defined T1_CORE4_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE4_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE5_START_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE5_START_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=".T1_bssCore5"
#   pragma ghs startdata
#elif defined T1_CORE5_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE5_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE6_START_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE6_START_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=".T1_bssCore6"
#   pragma ghs startdata
#elif defined T1_CORE6_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE6_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE7_START_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE7_START_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=".T1_bssCore7"
#   pragma ghs startdata
#elif defined T1_CORE7_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE7_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE8_START_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE8_START_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=".T1_bssCore8"
#   pragma ghs startdata
#elif defined T1_CORE8_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE8_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE9_START_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE9_START_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=".T1_bssCore9"
#   pragma ghs startdata
#elif defined T1_CORE9_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE9_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE10_START_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE10_START_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=".T1_bssCore10"
#   pragma ghs startdata
#elif defined T1_CORE10_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE10_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE11_START_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE11_START_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=".T1_bssCore11"
#   pragma ghs startdata
#elif defined T1_CORE11_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE11_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE12_START_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE12_START_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=".T1_bssCore12"
#   pragma ghs startdata
#elif defined T1_CORE12_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE12_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE13_START_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE13_START_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=".T1_bssCore13"
#   pragma ghs startdata
#elif defined T1_CORE13_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE13_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE14_START_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE14_START_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=".T1_bssCore14"
#   pragma ghs startdata
#elif defined T1_CORE14_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE14_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE_COMMS_START_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE_COMMS_START_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=".T1_bssCoreComms"
#   pragma ghs startdata
#elif defined T1_CORE_COMMS_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CORE_COMMS_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CLONE_START_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CLONE_START_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=".T1_bssClone"
#   pragma ghs startdata
#elif defined T1_CLONE_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   undef T1_CLONE_STOP_SEC_VAR_POWER_ON_CLEARED_16
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bss"
#   pragma ghs startdata
#elif defined T1_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE0_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE0_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCore0"
#   pragma ghs startdata
#elif defined T1_CORE0_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE0_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE1_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE1_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCore1"
#   pragma ghs startdata
#elif defined T1_CORE1_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE1_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE2_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE2_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCore2"
#   pragma ghs startdata
#elif defined T1_CORE2_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE2_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE3_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE3_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCore3"
#   pragma ghs startdata
#elif defined T1_CORE3_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE3_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE4_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE4_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCore4"
#   pragma ghs startdata
#elif defined T1_CORE4_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE4_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE5_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE5_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCore5"
#   pragma ghs startdata
#elif defined T1_CORE5_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE5_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE6_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE6_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCore6"
#   pragma ghs startdata
#elif defined T1_CORE6_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE6_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE7_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE7_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCore7"
#   pragma ghs startdata
#elif defined T1_CORE7_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE7_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE8_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE8_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCore8"
#   pragma ghs startdata
#elif defined T1_CORE8_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE8_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE9_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE9_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCore9"
#   pragma ghs startdata
#elif defined T1_CORE9_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE9_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE10_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE10_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCore10"
#   pragma ghs startdata
#elif defined T1_CORE10_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE10_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE11_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE11_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCore11"
#   pragma ghs startdata
#elif defined T1_CORE11_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE11_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE12_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE12_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCore12"
#   pragma ghs startdata
#elif defined T1_CORE12_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE12_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE13_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE13_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCore13"
#   pragma ghs startdata
#elif defined T1_CORE13_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE13_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE14_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE14_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCore14"
#   pragma ghs startdata
#elif defined T1_CORE14_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE14_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CORE_COMMS_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE_COMMS_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCoreComms"
#   pragma ghs startdata
#elif defined T1_CORE_COMMS_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CORE_COMMS_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CLONE_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CLONE_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssClone"
#   pragma ghs startdata
#elif defined T1_CLONE_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CLONE_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_DCX_START_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_START_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=".T1_bssDCX"
#   pragma ghs startdata
#elif defined T1_DCX_STOP_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_STOP_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_DCX_CORE0_START_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE0_START_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=".T1_bssDCXCore0"
#   pragma ghs startdata
#elif defined T1_DCX_CORE0_STOP_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE0_STOP_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_DCX_CORE1_START_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE1_START_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=".T1_bssDCXCore1"
#   pragma ghs startdata
#elif defined T1_DCX_CORE1_STOP_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE1_STOP_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_DCX_CORE2_START_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE2_START_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=".T1_bssDCXCore2"
#   pragma ghs startdata
#elif defined T1_DCX_CORE2_STOP_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE2_STOP_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_DCX_CORE3_START_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE3_START_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=".T1_bssDCXCore3"
#   pragma ghs startdata
#elif defined T1_DCX_CORE3_STOP_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE3_STOP_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_DCX_CORE4_START_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE4_START_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=".T1_bssDCXCore4"
#   pragma ghs startdata
#elif defined T1_DCX_CORE4_STOP_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE4_STOP_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_DCX_CORE5_START_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE5_START_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=".T1_bssDCXCore5"
#   pragma ghs startdata
#elif defined T1_DCX_CORE5_STOP_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE5_STOP_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_DCX_CORE6_START_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE6_START_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=".T1_bssDCXCore6"
#   pragma ghs startdata
#elif defined T1_DCX_CORE6_STOP_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE6_STOP_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_DCX_CORE7_START_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE7_START_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=".T1_bssDCXCore7"
#   pragma ghs startdata
#elif defined T1_DCX_CORE7_STOP_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE7_STOP_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_DCX_CORE8_START_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE8_START_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=".T1_bssDCXCore8"
#   pragma ghs startdata
#elif defined T1_DCX_CORE8_STOP_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE8_STOP_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_DCX_CORE9_START_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE9_START_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=".T1_bssDCXCore9"
#   pragma ghs startdata
#elif defined T1_DCX_CORE9_STOP_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE9_STOP_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_DCX_CORE10_START_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE10_START_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=".T1_bssDCXCore10"
#   pragma ghs startdata
#elif defined T1_DCX_CORE10_STOP_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE10_STOP_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_DCX_CORE11_START_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE11_START_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=".T1_bssDCXCore11"
#   pragma ghs startdata
#elif defined T1_DCX_CORE11_STOP_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE11_STOP_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_DCX_CORE12_START_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE12_START_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=".T1_bssDCXCore12"
#   pragma ghs startdata
#elif defined T1_DCX_CORE12_STOP_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE12_STOP_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_DCX_CORE13_START_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE13_START_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=".T1_bssDCXCore13"
#   pragma ghs startdata
#elif defined T1_DCX_CORE13_STOP_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE13_STOP_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_DCX_CORE14_START_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE14_START_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=".T1_bssDCXCore14"
#   pragma ghs startdata
#elif defined T1_DCX_CORE14_STOP_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CORE14_STOP_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_DCX_CLONE_START_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CLONE_START_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=".T1_bssDCXClone"
#   pragma ghs startdata
#elif defined T1_DCX_CLONE_STOP_SEC_VAR_POWER_ON_CLEARED
#   undef T1_DCX_CLONE_STOP_SEC_VAR_POWER_ON_CLEARED
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CHECKED_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssChecked"
#   pragma ghs startdata
#elif defined T1_CHECKED_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CHECKED_CORE0_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE0_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCheckedCore0"
#   pragma ghs startdata
#elif defined T1_CHECKED_CORE0_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE0_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CHECKED_CORE1_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE1_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCheckedCore1"
#   pragma ghs startdata
#elif defined T1_CHECKED_CORE1_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE1_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CHECKED_CORE2_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE2_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCheckedCore2"
#   pragma ghs startdata
#elif defined T1_CHECKED_CORE2_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE2_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CHECKED_CORE3_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE3_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCheckedCore3"
#   pragma ghs startdata
#elif defined T1_CHECKED_CORE3_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE3_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CHECKED_CORE4_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE4_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCheckedCore4"
#   pragma ghs startdata
#elif defined T1_CHECKED_CORE4_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE4_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CHECKED_CORE5_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE5_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCheckedCore5"
#   pragma ghs startdata
#elif defined T1_CHECKED_CORE5_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE5_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CHECKED_CORE6_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE6_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCheckedCore6"
#   pragma ghs startdata
#elif defined T1_CHECKED_CORE6_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE6_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CHECKED_CORE7_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE7_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCheckedCore7"
#   pragma ghs startdata
#elif defined T1_CHECKED_CORE7_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE7_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CHECKED_CORE8_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE8_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCheckedCore8"
#   pragma ghs startdata
#elif defined T1_CHECKED_CORE8_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE8_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CHECKED_CORE9_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE9_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCheckedCore9"
#   pragma ghs startdata
#elif defined T1_CHECKED_CORE9_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE9_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CHECKED_CORE10_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE10_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCheckedCore10"
#   pragma ghs startdata
#elif defined T1_CHECKED_CORE10_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE10_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CHECKED_CORE11_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE11_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCheckedCore11"
#   pragma ghs startdata
#elif defined T1_CHECKED_CORE11_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE11_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CHECKED_CORE12_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE12_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCheckedCore12"
#   pragma ghs startdata
#elif defined T1_CHECKED_CORE12_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE12_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CHECKED_CORE13_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE13_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCheckedCore13"
#   pragma ghs startdata
#elif defined T1_CHECKED_CORE13_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE13_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CHECKED_CORE14_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE14_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCheckedCore14"
#   pragma ghs startdata
#elif defined T1_CHECKED_CORE14_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CORE14_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_CHECKED_CLONE_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CLONE_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_bssCheckedClone"
#   pragma ghs startdata
#elif defined T1_CHECKED_CLONE_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_CHECKED_CLONE_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_TRACEBUFFER_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_traceBuffer"
#   pragma ghs startdata
#elif defined T1_TRACEBUFFER_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_TRACEBUFFER_CORE0_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE0_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_traceBufferCore0"
#   pragma ghs startdata
#elif defined T1_TRACEBUFFER_CORE0_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE0_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_TRACEBUFFER_CORE1_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE1_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_traceBufferCore1"
#   pragma ghs startdata
#elif defined T1_TRACEBUFFER_CORE1_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE1_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_TRACEBUFFER_CORE2_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE2_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_traceBufferCore2"
#   pragma ghs startdata
#elif defined T1_TRACEBUFFER_CORE2_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE2_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_TRACEBUFFER_CORE3_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE3_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_traceBufferCore3"
#   pragma ghs startdata
#elif defined T1_TRACEBUFFER_CORE3_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE3_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_TRACEBUFFER_CORE4_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE4_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_traceBufferCore4"
#   pragma ghs startdata
#elif defined T1_TRACEBUFFER_CORE4_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE4_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_TRACEBUFFER_CORE5_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE5_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_traceBufferCore5"
#   pragma ghs startdata
#elif defined T1_TRACEBUFFER_CORE5_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE5_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_TRACEBUFFER_CORE6_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE6_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_traceBufferCore6"
#   pragma ghs startdata
#elif defined T1_TRACEBUFFER_CORE6_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE6_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_TRACEBUFFER_CORE7_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE7_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_traceBufferCore7"
#   pragma ghs startdata
#elif defined T1_TRACEBUFFER_CORE7_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE7_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_TRACEBUFFER_CORE8_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE8_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_traceBufferCore8"
#   pragma ghs startdata
#elif defined T1_TRACEBUFFER_CORE8_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE8_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_TRACEBUFFER_CORE9_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE9_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_traceBufferCore9"
#   pragma ghs startdata
#elif defined T1_TRACEBUFFER_CORE9_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE9_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_TRACEBUFFER_CORE10_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE10_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_traceBufferCore10"
#   pragma ghs startdata
#elif defined T1_TRACEBUFFER_CORE10_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE10_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_TRACEBUFFER_CORE11_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE11_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_traceBufferCore11"
#   pragma ghs startdata
#elif defined T1_TRACEBUFFER_CORE11_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE11_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_TRACEBUFFER_CORE12_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE12_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_traceBufferCore12"
#   pragma ghs startdata
#elif defined T1_TRACEBUFFER_CORE12_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE12_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_TRACEBUFFER_CORE13_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE13_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_traceBufferCore13"
#   pragma ghs startdata
#elif defined T1_TRACEBUFFER_CORE13_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE13_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_TRACEBUFFER_CORE14_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE14_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_traceBufferCore14"
#   pragma ghs startdata
#elif defined T1_TRACEBUFFER_CORE14_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CORE14_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#elif defined T1_TRACEBUFFER_CLONE_START_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CLONE_START_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=".T1_traceBufferClone"
#   pragma ghs startdata
#elif defined T1_TRACEBUFFER_CLONE_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   undef T1_TRACEBUFFER_CLONE_STOP_SEC_VAR_POWER_ON_CLEARED_32
#   pragma ghs section bss=default
#   pragma ghs enddata

#else
#   error "T1_MemMap.h: no valid section define used."
#endif

#if defined T1_DOXYGEN_ONLY
/*! \brief Code (in flash) shared by all cores */
#   define T1_START_SEC_CODE
/*! \brief Code (in flash) for T1 logical core 0 */
#   define T1_CORE0_START_SEC_CODE
/*! \brief Code (in flash) for T1 logical core 1 */
#   define T1_CORE1_START_SEC_CODE
/*! \brief Code (in flash) for T1 logical core 2 */
#   define T1_CORE2_START_SEC_CODE
/*! \brief Code (in flash) for T1 logical core 3 */
#   define T1_CORE3_START_SEC_CODE
/*! \brief Code (in flash) for T1 logical core 4 */
#   define T1_CORE4_START_SEC_CODE
/*! \brief Code (in flash) for T1 logical core 5 */
#   define T1_CORE5_START_SEC_CODE
/*! \brief Code (in flash) for T1 logical core 6 */
#   define T1_CORE6_START_SEC_CODE
/*! \brief Code (in flash) for T1 logical core 7 */
#   define T1_CORE7_START_SEC_CODE
/*! \brief Code (in flash) for T1 logical core 8 */
#   define T1_CORE8_START_SEC_CODE
/*! \brief Code (in flash) for T1 logical core 9 */
#   define T1_CORE9_START_SEC_CODE
/*! \brief Code (in flash) for T1 logical core 10 */
#   define T1_CORE10_START_SEC_CODE
/*! \brief Code (in flash) for T1 logical core 11 */
#   define T1_CORE11_START_SEC_CODE
/*! \brief Code (in flash) for T1 logical core 12 */
#   define T1_CORE12_START_SEC_CODE
/*! \brief Code (in flash) for T1 logical core 13 */
#   define T1_CORE13_START_SEC_CODE
/*! \brief Code (in flash) for T1 logical core 14 */
#   define T1_CORE14_START_SEC_CODE
/*! \brief Code for TriCore debug monitor (T1.flex) shared by all cores */
#   define T1_DMS_START_SEC_CODE
/*! \brief Code for TriCore debug monitor (T1.flex) for T1 logical core 0 */
#   define T1_DMS_CORE0_START_SEC_CODE
/*! \brief Code for TriCore debug monitor (T1.flex) for T1 logical core 1 */
#   define T1_DMS_CORE1_START_SEC_CODE
/*! \brief Code for TriCore debug monitor (T1.flex) for T1 logical core 2 */
#   define T1_DMS_CORE2_START_SEC_CODE
/*! \brief Code for TriCore debug monitor (T1.flex) for T1 logical core 3 */
#   define T1_DMS_CORE3_START_SEC_CODE
/*! \brief Code for TriCore debug monitor (T1.flex) for T1 logical core 4 */
#   define T1_DMS_CORE4_START_SEC_CODE
/*! \brief Code for TriCore debug monitor (T1.flex) for T1 logical core 5 */
#   define T1_DMS_CORE5_START_SEC_CODE
/*! \brief Code for TriCore debug monitor (T1.flex) for T1 logical core 6 */
#   define T1_DMS_CORE6_START_SEC_CODE
/*! \brief Code for TriCore debug monitor (T1.flex) for T1 logical core 7 */
#   define T1_DMS_CORE7_START_SEC_CODE
/*! \brief Code for TriCore debug monitor (T1.flex) for T1 logical core 8 */
#   define T1_DMS_CORE8_START_SEC_CODE
/*! \brief Code for TriCore debug monitor (T1.flex) for T1 logical core 9 */
#   define T1_DMS_CORE9_START_SEC_CODE
/*! \brief Code for TriCore debug monitor (T1.flex) for T1 logical core 10 */
#   define T1_DMS_CORE10_START_SEC_CODE
/*! \brief Code for TriCore debug monitor (T1.flex) for T1 logical core 11 */
#   define T1_DMS_CORE11_START_SEC_CODE
/*! \brief Code for TriCore debug monitor (T1.flex) for T1 logical core 12 */
#   define T1_DMS_CORE12_START_SEC_CODE
/*! \brief Code for TriCore debug monitor (T1.flex) for T1 logical core 13 */
#   define T1_DMS_CORE13_START_SEC_CODE
/*! \brief Code for TriCore debug monitor (T1.flex) for T1 logical core 14 */
#   define T1_DMS_CORE14_START_SEC_CODE
/*! \brief Code for TriCore debug monitor (T1.flex) duplicated for each core */
#   define T1_DMS_CLONE_START_SEC_CODE
/*! \brief Code relevant to T1-TARGET-SW overheads shared by all cores */
#   define T1_START_SEC_CODE_FAST
/*! \brief Constant data (in flash or write-protected RAM) aligned for 8-bit accesses shared by all cores */
#   define T1_START_SEC_CONST_8
/*! \brief Constant data (in flash or write-protected RAM) aligned for 16-bit accesses shared by all cores */
#   define T1_START_SEC_CONST_16
/*! \brief Constant data (in flash or write-protected RAM) aligned for 32-bit accesses shared by all cores */
#   define T1_START_SEC_CONST_32
/*! \brief Constant data (in flash or write-protected RAM) aligned for 32-bit accesses for T1 logical core 0 */
#   define T1_CORE0_START_SEC_CONST_32
/*! \brief Constant data (in flash or write-protected RAM) aligned for 32-bit accesses for T1 logical core 1 */
#   define T1_CORE1_START_SEC_CONST_32
/*! \brief Constant data (in flash or write-protected RAM) aligned for 32-bit accesses for T1 logical core 2 */
#   define T1_CORE2_START_SEC_CONST_32
/*! \brief Constant data (in flash or write-protected RAM) aligned for 32-bit accesses for T1 logical core 3 */
#   define T1_CORE3_START_SEC_CONST_32
/*! \brief Constant data (in flash or write-protected RAM) aligned for 32-bit accesses for T1 logical core 4 */
#   define T1_CORE4_START_SEC_CONST_32
/*! \brief Constant data (in flash or write-protected RAM) aligned for 32-bit accesses for T1 logical core 5 */
#   define T1_CORE5_START_SEC_CONST_32
/*! \brief Constant data (in flash or write-protected RAM) aligned for 32-bit accesses for T1 logical core 6 */
#   define T1_CORE6_START_SEC_CONST_32
/*! \brief Constant data (in flash or write-protected RAM) aligned for 32-bit accesses for T1 logical core 7 */
#   define T1_CORE7_START_SEC_CONST_32
/*! \brief Constant data (in flash or write-protected RAM) aligned for 32-bit accesses for T1 logical core 8 */
#   define T1_CORE8_START_SEC_CONST_32
/*! \brief Constant data (in flash or write-protected RAM) aligned for 32-bit accesses for T1 logical core 9 */
#   define T1_CORE9_START_SEC_CONST_32
/*! \brief Constant data (in flash or write-protected RAM) aligned for 32-bit accesses for T1 logical core 10 */
#   define T1_CORE10_START_SEC_CONST_32
/*! \brief Constant data (in flash or write-protected RAM) aligned for 32-bit accesses for T1 logical core 11 */
#   define T1_CORE11_START_SEC_CONST_32
/*! \brief Constant data (in flash or write-protected RAM) aligned for 32-bit accesses for T1 logical core 12 */
#   define T1_CORE12_START_SEC_CONST_32
/*! \brief Constant data (in flash or write-protected RAM) aligned for 32-bit accesses for T1 logical core 13 */
#   define T1_CORE13_START_SEC_CONST_32
/*! \brief Constant data (in flash or write-protected RAM) aligned for 32-bit accesses for T1 logical core 14 */
#   define T1_CORE14_START_SEC_CONST_32
/*! \brief Constant data (in flash or write-protected RAM) aligned for 32-bit accesses duplicated for each core */
#   define T1_CLONE_START_SEC_CONST_32
/*! \brief Shared zeroed RAM aligned for 32-bit accesses shared by all cores */
#   define T1_START_SEC_VAR_CLEARED_32
/*! \brief Near uninitialized RAM aligned for 8-bit accesses shared by all cores */
#   define T1_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
/*! \brief Near uninitialized RAM aligned for 8-bit accesses for T1 logical core 0 */
#   define T1_CORE0_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
/*! \brief Near uninitialized RAM aligned for 8-bit accesses for T1 logical core 1 */
#   define T1_CORE1_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
/*! \brief Near uninitialized RAM aligned for 8-bit accesses for T1 logical core 2 */
#   define T1_CORE2_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
/*! \brief Near uninitialized RAM aligned for 8-bit accesses for T1 logical core 3 */
#   define T1_CORE3_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
/*! \brief Near uninitialized RAM aligned for 8-bit accesses for T1 logical core 4 */
#   define T1_CORE4_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
/*! \brief Near uninitialized RAM aligned for 8-bit accesses for T1 logical core 5 */
#   define T1_CORE5_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
/*! \brief Near uninitialized RAM aligned for 8-bit accesses for T1 logical core 6 */
#   define T1_CORE6_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
/*! \brief Near uninitialized RAM aligned for 8-bit accesses for T1 logical core 7 */
#   define T1_CORE7_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
/*! \brief Near uninitialized RAM aligned for 8-bit accesses for T1 logical core 8 */
#   define T1_CORE8_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
/*! \brief Near uninitialized RAM aligned for 8-bit accesses for T1 logical core 9 */
#   define T1_CORE9_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
/*! \brief Near uninitialized RAM aligned for 8-bit accesses for T1 logical core 10 */
#   define T1_CORE10_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
/*! \brief Near uninitialized RAM aligned for 8-bit accesses for T1 logical core 11 */
#   define T1_CORE11_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
/*! \brief Near uninitialized RAM aligned for 8-bit accesses for T1 logical core 12 */
#   define T1_CORE12_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
/*! \brief Near uninitialized RAM aligned for 8-bit accesses for T1 logical core 13 */
#   define T1_CORE13_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
/*! \brief Near uninitialized RAM aligned for 8-bit accesses for T1 logical core 14 */
#   define T1_CORE14_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
/*! \brief Near uninitialized RAM aligned for 8-bit accesses for T1 communications core */
#   define T1_CORE_COMMS_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
/*! \brief Near uninitialized RAM aligned for 8-bit accesses duplicated for each core */
#   define T1_CLONE_START_SEC_VAR_NEAR_POWER_ON_CLEARED_8
/*! \brief Near uninitialized RAM aligned for 16-bit accesses shared by all cores */
#   define T1_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
/*! \brief Near uninitialized RAM aligned for 16-bit accesses for T1 logical core 0 */
#   define T1_CORE0_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
/*! \brief Near uninitialized RAM aligned for 16-bit accesses for T1 logical core 1 */
#   define T1_CORE1_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
/*! \brief Near uninitialized RAM aligned for 16-bit accesses for T1 logical core 2 */
#   define T1_CORE2_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
/*! \brief Near uninitialized RAM aligned for 16-bit accesses for T1 logical core 3 */
#   define T1_CORE3_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
/*! \brief Near uninitialized RAM aligned for 16-bit accesses for T1 logical core 4 */
#   define T1_CORE4_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
/*! \brief Near uninitialized RAM aligned for 16-bit accesses for T1 logical core 5 */
#   define T1_CORE5_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
/*! \brief Near uninitialized RAM aligned for 16-bit accesses for T1 logical core 6 */
#   define T1_CORE6_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
/*! \brief Near uninitialized RAM aligned for 16-bit accesses for T1 logical core 7 */
#   define T1_CORE7_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
/*! \brief Near uninitialized RAM aligned for 16-bit accesses for T1 logical core 8 */
#   define T1_CORE8_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
/*! \brief Near uninitialized RAM aligned for 16-bit accesses for T1 logical core 9 */
#   define T1_CORE9_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
/*! \brief Near uninitialized RAM aligned for 16-bit accesses for T1 logical core 10 */
#   define T1_CORE10_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
/*! \brief Near uninitialized RAM aligned for 16-bit accesses for T1 logical core 11 */
#   define T1_CORE11_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
/*! \brief Near uninitialized RAM aligned for 16-bit accesses for T1 logical core 12 */
#   define T1_CORE12_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
/*! \brief Near uninitialized RAM aligned for 16-bit accesses for T1 logical core 13 */
#   define T1_CORE13_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
/*! \brief Near uninitialized RAM aligned for 16-bit accesses for T1 logical core 14 */
#   define T1_CORE14_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
/*! \brief Near uninitialized RAM aligned for 16-bit accesses for T1 communications core */
#   define T1_CORE_COMMS_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
/*! \brief Near uninitialized RAM aligned for 16-bit accesses duplicated for each core */
#   define T1_CLONE_START_SEC_VAR_NEAR_POWER_ON_CLEARED_16
/*! \brief Near uninitialized RAM aligned for 32-bit accesses shared by all cores */
#   define T1_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
/*! \brief Near uninitialized RAM aligned for 32-bit accesses for T1 logical core 0 */
#   define T1_CORE0_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
/*! \brief Near uninitialized RAM aligned for 32-bit accesses for T1 logical core 1 */
#   define T1_CORE1_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
/*! \brief Near uninitialized RAM aligned for 32-bit accesses for T1 logical core 2 */
#   define T1_CORE2_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
/*! \brief Near uninitialized RAM aligned for 32-bit accesses for T1 logical core 3 */
#   define T1_CORE3_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
/*! \brief Near uninitialized RAM aligned for 32-bit accesses for T1 logical core 4 */
#   define T1_CORE4_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
/*! \brief Near uninitialized RAM aligned for 32-bit accesses for T1 logical core 5 */
#   define T1_CORE5_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
/*! \brief Near uninitialized RAM aligned for 32-bit accesses for T1 logical core 6 */
#   define T1_CORE6_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
/*! \brief Near uninitialized RAM aligned for 32-bit accesses for T1 logical core 7 */
#   define T1_CORE7_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
/*! \brief Near uninitialized RAM aligned for 32-bit accesses for T1 logical core 8 */
#   define T1_CORE8_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
/*! \brief Near uninitialized RAM aligned for 32-bit accesses for T1 logical core 9 */
#   define T1_CORE9_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
/*! \brief Near uninitialized RAM aligned for 32-bit accesses for T1 logical core 10 */
#   define T1_CORE10_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
/*! \brief Near uninitialized RAM aligned for 32-bit accesses for T1 logical core 11 */
#   define T1_CORE11_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
/*! \brief Near uninitialized RAM aligned for 32-bit accesses for T1 logical core 12 */
#   define T1_CORE12_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
/*! \brief Near uninitialized RAM aligned for 32-bit accesses for T1 logical core 13 */
#   define T1_CORE13_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
/*! \brief Near uninitialized RAM aligned for 32-bit accesses for T1 logical core 14 */
#   define T1_CORE14_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
/*! \brief Near uninitialized RAM aligned for 32-bit accesses for T1 communications core */
#   define T1_CORE_COMMS_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
/*! \brief Near uninitialized RAM aligned for 32-bit accesses duplicated for each core */
#   define T1_CLONE_START_SEC_VAR_NEAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM aligned for 8-bit accesses shared by all cores */
#   define T1_START_SEC_VAR_POWER_ON_CLEARED_8
/*! \brief Uninitialized RAM aligned for 8-bit accesses for T1 logical core 0 */
#   define T1_CORE0_START_SEC_VAR_POWER_ON_CLEARED_8
/*! \brief Uninitialized RAM aligned for 8-bit accesses for T1 logical core 1 */
#   define T1_CORE1_START_SEC_VAR_POWER_ON_CLEARED_8
/*! \brief Uninitialized RAM aligned for 8-bit accesses for T1 logical core 2 */
#   define T1_CORE2_START_SEC_VAR_POWER_ON_CLEARED_8
/*! \brief Uninitialized RAM aligned for 8-bit accesses for T1 logical core 3 */
#   define T1_CORE3_START_SEC_VAR_POWER_ON_CLEARED_8
/*! \brief Uninitialized RAM aligned for 8-bit accesses for T1 logical core 4 */
#   define T1_CORE4_START_SEC_VAR_POWER_ON_CLEARED_8
/*! \brief Uninitialized RAM aligned for 8-bit accesses for T1 logical core 5 */
#   define T1_CORE5_START_SEC_VAR_POWER_ON_CLEARED_8
/*! \brief Uninitialized RAM aligned for 8-bit accesses for T1 logical core 6 */
#   define T1_CORE6_START_SEC_VAR_POWER_ON_CLEARED_8
/*! \brief Uninitialized RAM aligned for 8-bit accesses for T1 logical core 7 */
#   define T1_CORE7_START_SEC_VAR_POWER_ON_CLEARED_8
/*! \brief Uninitialized RAM aligned for 8-bit accesses for T1 logical core 8 */
#   define T1_CORE8_START_SEC_VAR_POWER_ON_CLEARED_8
/*! \brief Uninitialized RAM aligned for 8-bit accesses for T1 logical core 9 */
#   define T1_CORE9_START_SEC_VAR_POWER_ON_CLEARED_8
/*! \brief Uninitialized RAM aligned for 8-bit accesses for T1 logical core 10 */
#   define T1_CORE10_START_SEC_VAR_POWER_ON_CLEARED_8
/*! \brief Uninitialized RAM aligned for 8-bit accesses for T1 logical core 11 */
#   define T1_CORE11_START_SEC_VAR_POWER_ON_CLEARED_8
/*! \brief Uninitialized RAM aligned for 8-bit accesses for T1 logical core 12 */
#   define T1_CORE12_START_SEC_VAR_POWER_ON_CLEARED_8
/*! \brief Uninitialized RAM aligned for 8-bit accesses for T1 logical core 13 */
#   define T1_CORE13_START_SEC_VAR_POWER_ON_CLEARED_8
/*! \brief Uninitialized RAM aligned for 8-bit accesses for T1 logical core 14 */
#   define T1_CORE14_START_SEC_VAR_POWER_ON_CLEARED_8
/*! \brief Uninitialized RAM aligned for 8-bit accesses for T1 communications core */
#   define T1_CORE_COMMS_START_SEC_VAR_POWER_ON_CLEARED_8
/*! \brief Uninitialized RAM aligned for 8-bit accesses duplicated for each core */
#   define T1_CLONE_START_SEC_VAR_POWER_ON_CLEARED_8
/*! \brief Uninitialized RAM aligned for 16-bit accesses shared by all cores */
#   define T1_START_SEC_VAR_POWER_ON_CLEARED_16
/*! \brief Uninitialized RAM aligned for 16-bit accesses for T1 logical core 0 */
#   define T1_CORE0_START_SEC_VAR_POWER_ON_CLEARED_16
/*! \brief Uninitialized RAM aligned for 16-bit accesses for T1 logical core 1 */
#   define T1_CORE1_START_SEC_VAR_POWER_ON_CLEARED_16
/*! \brief Uninitialized RAM aligned for 16-bit accesses for T1 logical core 2 */
#   define T1_CORE2_START_SEC_VAR_POWER_ON_CLEARED_16
/*! \brief Uninitialized RAM aligned for 16-bit accesses for T1 logical core 3 */
#   define T1_CORE3_START_SEC_VAR_POWER_ON_CLEARED_16
/*! \brief Uninitialized RAM aligned for 16-bit accesses for T1 logical core 4 */
#   define T1_CORE4_START_SEC_VAR_POWER_ON_CLEARED_16
/*! \brief Uninitialized RAM aligned for 16-bit accesses for T1 logical core 5 */
#   define T1_CORE5_START_SEC_VAR_POWER_ON_CLEARED_16
/*! \brief Uninitialized RAM aligned for 16-bit accesses for T1 logical core 6 */
#   define T1_CORE6_START_SEC_VAR_POWER_ON_CLEARED_16
/*! \brief Uninitialized RAM aligned for 16-bit accesses for T1 logical core 7 */
#   define T1_CORE7_START_SEC_VAR_POWER_ON_CLEARED_16
/*! \brief Uninitialized RAM aligned for 16-bit accesses for T1 logical core 8 */
#   define T1_CORE8_START_SEC_VAR_POWER_ON_CLEARED_16
/*! \brief Uninitialized RAM aligned for 16-bit accesses for T1 logical core 9 */
#   define T1_CORE9_START_SEC_VAR_POWER_ON_CLEARED_16
/*! \brief Uninitialized RAM aligned for 16-bit accesses for T1 logical core 10 */
#   define T1_CORE10_START_SEC_VAR_POWER_ON_CLEARED_16
/*! \brief Uninitialized RAM aligned for 16-bit accesses for T1 logical core 11 */
#   define T1_CORE11_START_SEC_VAR_POWER_ON_CLEARED_16
/*! \brief Uninitialized RAM aligned for 16-bit accesses for T1 logical core 12 */
#   define T1_CORE12_START_SEC_VAR_POWER_ON_CLEARED_16
/*! \brief Uninitialized RAM aligned for 16-bit accesses for T1 logical core 13 */
#   define T1_CORE13_START_SEC_VAR_POWER_ON_CLEARED_16
/*! \brief Uninitialized RAM aligned for 16-bit accesses for T1 logical core 14 */
#   define T1_CORE14_START_SEC_VAR_POWER_ON_CLEARED_16
/*! \brief Uninitialized RAM aligned for 16-bit accesses for T1 communications core */
#   define T1_CORE_COMMS_START_SEC_VAR_POWER_ON_CLEARED_16
/*! \brief Uninitialized RAM aligned for 16-bit accesses duplicated for each core */
#   define T1_CLONE_START_SEC_VAR_POWER_ON_CLEARED_16
/*! \brief Uninitialized RAM aligned for 32-bit accesses shared by all cores */
#   define T1_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM aligned for 32-bit accesses for T1 logical core 0 */
#   define T1_CORE0_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM aligned for 32-bit accesses for T1 logical core 1 */
#   define T1_CORE1_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM aligned for 32-bit accesses for T1 logical core 2 */
#   define T1_CORE2_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM aligned for 32-bit accesses for T1 logical core 3 */
#   define T1_CORE3_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM aligned for 32-bit accesses for T1 logical core 4 */
#   define T1_CORE4_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM aligned for 32-bit accesses for T1 logical core 5 */
#   define T1_CORE5_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM aligned for 32-bit accesses for T1 logical core 6 */
#   define T1_CORE6_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM aligned for 32-bit accesses for T1 logical core 7 */
#   define T1_CORE7_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM aligned for 32-bit accesses for T1 logical core 8 */
#   define T1_CORE8_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM aligned for 32-bit accesses for T1 logical core 9 */
#   define T1_CORE9_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM aligned for 32-bit accesses for T1 logical core 10 */
#   define T1_CORE10_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM aligned for 32-bit accesses for T1 logical core 11 */
#   define T1_CORE11_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM aligned for 32-bit accesses for T1 logical core 12 */
#   define T1_CORE12_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM aligned for 32-bit accesses for T1 logical core 13 */
#   define T1_CORE13_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM aligned for 32-bit accesses for T1 logical core 14 */
#   define T1_CORE14_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM aligned for 32-bit accesses for T1 communications core */
#   define T1_CORE_COMMS_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM aligned for 32-bit accesses duplicated for each core */
#   define T1_CLONE_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM for TriCore debug context save (T1.flex) aligned for 32-bit accesses shared by all cores */
#   define T1_DCX_START_SEC_VAR_POWER_ON_CLEARED
/*! \brief Uninitialized RAM for TriCore debug context save (T1.flex) aligned for 32-bit accesses for T1 logical core 0 */
#   define T1_DCX_CORE0_START_SEC_VAR_POWER_ON_CLEARED
/*! \brief Uninitialized RAM for TriCore debug context save (T1.flex) aligned for 32-bit accesses for T1 logical core 1 */
#   define T1_DCX_CORE1_START_SEC_VAR_POWER_ON_CLEARED
/*! \brief Uninitialized RAM for TriCore debug context save (T1.flex) aligned for 32-bit accesses for T1 logical core 2 */
#   define T1_DCX_CORE2_START_SEC_VAR_POWER_ON_CLEARED
/*! \brief Uninitialized RAM for TriCore debug context save (T1.flex) aligned for 32-bit accesses for T1 logical core 3 */
#   define T1_DCX_CORE3_START_SEC_VAR_POWER_ON_CLEARED
/*! \brief Uninitialized RAM for TriCore debug context save (T1.flex) aligned for 32-bit accesses for T1 logical core 4 */
#   define T1_DCX_CORE4_START_SEC_VAR_POWER_ON_CLEARED
/*! \brief Uninitialized RAM for TriCore debug context save (T1.flex) aligned for 32-bit accesses for T1 logical core 5 */
#   define T1_DCX_CORE5_START_SEC_VAR_POWER_ON_CLEARED
/*! \brief Uninitialized RAM for TriCore debug context save (T1.flex) aligned for 32-bit accesses for T1 logical core 6 */
#   define T1_DCX_CORE6_START_SEC_VAR_POWER_ON_CLEARED
/*! \brief Uninitialized RAM for TriCore debug context save (T1.flex) aligned for 32-bit accesses for T1 logical core 7 */
#   define T1_DCX_CORE7_START_SEC_VAR_POWER_ON_CLEARED
/*! \brief Uninitialized RAM for TriCore debug context save (T1.flex) aligned for 32-bit accesses for T1 logical core 8 */
#   define T1_DCX_CORE8_START_SEC_VAR_POWER_ON_CLEARED
/*! \brief Uninitialized RAM for TriCore debug context save (T1.flex) aligned for 32-bit accesses for T1 logical core 9 */
#   define T1_DCX_CORE9_START_SEC_VAR_POWER_ON_CLEARED
/*! \brief Uninitialized RAM for TriCore debug context save (T1.flex) aligned for 32-bit accesses for T1 logical core 10 */
#   define T1_DCX_CORE10_START_SEC_VAR_POWER_ON_CLEARED
/*! \brief Uninitialized RAM for TriCore debug context save (T1.flex) aligned for 32-bit accesses for T1 logical core 11 */
#   define T1_DCX_CORE11_START_SEC_VAR_POWER_ON_CLEARED
/*! \brief Uninitialized RAM for TriCore debug context save (T1.flex) aligned for 32-bit accesses for T1 logical core 12 */
#   define T1_DCX_CORE12_START_SEC_VAR_POWER_ON_CLEARED
/*! \brief Uninitialized RAM for TriCore debug context save (T1.flex) aligned for 32-bit accesses for T1 logical core 13 */
#   define T1_DCX_CORE13_START_SEC_VAR_POWER_ON_CLEARED
/*! \brief Uninitialized RAM for TriCore debug context save (T1.flex) aligned for 32-bit accesses for T1 logical core 14 */
#   define T1_DCX_CORE14_START_SEC_VAR_POWER_ON_CLEARED
/*! \brief Uninitialized RAM for TriCore debug context save (T1.flex) aligned for 32-bit accesses duplicated for each core */
#   define T1_DCX_CLONE_START_SEC_VAR_POWER_ON_CLEARED
/*! \brief Uninitialized RAM with protection against corruption aligned for 32-bit accesses shared by all cores */
#   define T1_CHECKED_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM with protection against corruption aligned for 32-bit accesses for T1 logical core 0 */
#   define T1_CHECKED_CORE0_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM with protection against corruption aligned for 32-bit accesses for T1 logical core 1 */
#   define T1_CHECKED_CORE1_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM with protection against corruption aligned for 32-bit accesses for T1 logical core 2 */
#   define T1_CHECKED_CORE2_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM with protection against corruption aligned for 32-bit accesses for T1 logical core 3 */
#   define T1_CHECKED_CORE3_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM with protection against corruption aligned for 32-bit accesses for T1 logical core 4 */
#   define T1_CHECKED_CORE4_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM with protection against corruption aligned for 32-bit accesses for T1 logical core 5 */
#   define T1_CHECKED_CORE5_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM with protection against corruption aligned for 32-bit accesses for T1 logical core 6 */
#   define T1_CHECKED_CORE6_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM with protection against corruption aligned for 32-bit accesses for T1 logical core 7 */
#   define T1_CHECKED_CORE7_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM with protection against corruption aligned for 32-bit accesses for T1 logical core 8 */
#   define T1_CHECKED_CORE8_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM with protection against corruption aligned for 32-bit accesses for T1 logical core 9 */
#   define T1_CHECKED_CORE9_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM with protection against corruption aligned for 32-bit accesses for T1 logical core 10 */
#   define T1_CHECKED_CORE10_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM with protection against corruption aligned for 32-bit accesses for T1 logical core 11 */
#   define T1_CHECKED_CORE11_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM with protection against corruption aligned for 32-bit accesses for T1 logical core 12 */
#   define T1_CHECKED_CORE12_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM with protection against corruption aligned for 32-bit accesses for T1 logical core 13 */
#   define T1_CHECKED_CORE13_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM with protection against corruption aligned for 32-bit accesses for T1 logical core 14 */
#   define T1_CHECKED_CORE14_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Uninitialized RAM with protection against corruption aligned for 32-bit accesses duplicated for each core */
#   define T1_CHECKED_CLONE_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Trace buffer RAM aligned for 32-bit accesses shared by all cores */
#   define T1_TRACEBUFFER_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Trace buffer RAM aligned for 32-bit accesses for T1 logical core 0 */
#   define T1_TRACEBUFFER_CORE0_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Trace buffer RAM aligned for 32-bit accesses for T1 logical core 1 */
#   define T1_TRACEBUFFER_CORE1_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Trace buffer RAM aligned for 32-bit accesses for T1 logical core 2 */
#   define T1_TRACEBUFFER_CORE2_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Trace buffer RAM aligned for 32-bit accesses for T1 logical core 3 */
#   define T1_TRACEBUFFER_CORE3_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Trace buffer RAM aligned for 32-bit accesses for T1 logical core 4 */
#   define T1_TRACEBUFFER_CORE4_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Trace buffer RAM aligned for 32-bit accesses for T1 logical core 5 */
#   define T1_TRACEBUFFER_CORE5_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Trace buffer RAM aligned for 32-bit accesses for T1 logical core 6 */
#   define T1_TRACEBUFFER_CORE6_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Trace buffer RAM aligned for 32-bit accesses for T1 logical core 7 */
#   define T1_TRACEBUFFER_CORE7_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Trace buffer RAM aligned for 32-bit accesses for T1 logical core 8 */
#   define T1_TRACEBUFFER_CORE8_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Trace buffer RAM aligned for 32-bit accesses for T1 logical core 9 */
#   define T1_TRACEBUFFER_CORE9_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Trace buffer RAM aligned for 32-bit accesses for T1 logical core 10 */
#   define T1_TRACEBUFFER_CORE10_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Trace buffer RAM aligned for 32-bit accesses for T1 logical core 11 */
#   define T1_TRACEBUFFER_CORE11_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Trace buffer RAM aligned for 32-bit accesses for T1 logical core 12 */
#   define T1_TRACEBUFFER_CORE12_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Trace buffer RAM aligned for 32-bit accesses for T1 logical core 13 */
#   define T1_TRACEBUFFER_CORE13_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Trace buffer RAM aligned for 32-bit accesses for T1 logical core 14 */
#   define T1_TRACEBUFFER_CORE14_START_SEC_VAR_POWER_ON_CLEARED_32
/*! \brief Trace buffer RAM aligned for 32-bit accesses duplicated for each core */
#   define T1_TRACEBUFFER_CLONE_START_SEC_VAR_POWER_ON_CLEARED_32
#endif /* defined T1_DOXYGEN_ONLY */