//----------------------------------------------------------------------------- /// \file CddStp8381Types.c /// /// \brief STP driver NSD-8381 com configuration /// /// \author jiangweih /// //----------------------------------------------------------------------------- #include "CddStp8381Drv.h" #include "Spi_Cfg.h" #include "Spi_Types.h" #include "SPI.h" //============================================================================= // variables //============================================================================= // usage of global definitions #define CDDSTP_COM_SCHED_CYCLE_START_INDEX 11 // mirror of DRV8381 registers tisCddStp8381Com_DataMirror CddStp8381Com_DataMirror[CFA_CNT_STP] = {{0,0,0,0,0}}; uint16 CddStp8381Com_ucTxZero[CFA_CNT_STP] = {0}; uint16 CddStp8381Com_ucAllDefault[CFA_CNT_STP] = {0}; uint16 CddStp8381Com_TX_ClearSTA1[CFA_CNT_STP] = {0}; uint16 CddStp8381Com_RX_ClearSTA1[CFA_CNT_STP] = {0}; uint16 CddStp8381Com_TX_ClearSTA2[CFA_CNT_STP] = {0}; uint16 CddStp8381Com_RX_ClearSTA2[CFA_CNT_STP] = {0}; uint16 CddStp8381Com_ucRxInvalid[CFA_CNT_STP] = {0}; static uint8 CddStp8381Com_aucSchedIndex[CFA_CNT_STP] = {CDDSTP8381_SPI_SCHED_START_IDX_ZERO}; // index to schedule table CddStp8381Com_SpiSchedTable static uint32 CddStp8381Com_aunTxData[CFA_CNT_STP] = {0}; // filled in fct 'CddStp_SpiRx' and used in fct 'CddStp_SpiTx' //============================================================================= // defines //============================================================================= // usage of Schedule #define DRV_STA_TX_STA1 &CddStp8381Com_DataMirror[0].StaTx.aSTAReg1.ucRaw #define DRV_STA_TX_STA2 &CddStp8381Com_DataMirror[0].StaTx.aSTAReg2.ucRaw #define DRV_CTRL_TX_CR1 &CddStp8381Com_DataMirror[0].CtrlTx.aCReg1.ucRaw #define DRV_CTRL_TX_CR2 &CddStp8381Com_DataMirror[0].CtrlTx.aCReg2.ucRaw #define DRV_CTRL_TX_CR3 &CddStp8381Com_DataMirror[0].CtrlTx.aCReg3.ucRaw #define DRV_CTRL_TX_CR4 &CddStp8381Com_DataMirror[0].CtrlTx.aCReg4.ucRaw #define DRV_CTRL_TX_CR5 &CddStp8381Com_DataMirror[0].CtrlTx.aCReg5.ucRaw #define DRV_CTRL_TX_CR6 &CddStp8381Com_DataMirror[0].CtrlTx.aCReg6.ucRaw #define DRV_CTRL_TX_CR7 &CddStp8381Com_DataMirror[0].CtrlTx.aCReg7.ucRaw #define DRV_CTRL_TX_CR8 &CddStp8381Com_DataMirror[0].CtrlTx.aCReg8.ucRaw #define DRV_CTRL_TX_CR9 &CddStp8381Com_DataMirror[0].CtrlTx.aCReg9.ucRaw #define DRV_CTRL_TX_CVLLB &CddStp8381Com_DataMirror[0].CtrlTx.aCVLLBReg.ucRaw #define DRV_CTRL_TX_CVLLA &CddStp8381Com_DataMirror[0].CtrlTx.aCVLLAReg.ucRaw #define DRV_CTRL_TX_CVUL &CddStp8381Com_DataMirror[0].CtrlTx.aCVULReg.ucRaw #define DRV_STAT_RX_GSB &CddStp8381Com_DataMirror[0].GloStaRx.aGLOBSTAT.ucRaw #define DRV_STA_RX_STA1 &CddStp8381Com_DataMirror[0].StaRx.aSTAReg1.ucRaw #define DRV_STA_RX_STA2 &CddStp8381Com_DataMirror[0].StaRx.aSTAReg2.ucRaw #define DRV_CTRL_RX_CR1 &CddStp8381Com_DataMirror[0].CtrlRx.aCReg1.ucRaw #define DRV_CTRL_RX_CR2 &CddStp8381Com_DataMirror[0].CtrlRx.aCReg2.ucRaw #define DRV_CTRL_RX_CR3 &CddStp8381Com_DataMirror[0].CtrlRx.aCReg3.ucRaw #define DRV_CTRL_RX_CR4 &CddStp8381Com_DataMirror[0].CtrlRx.aCReg4.ucRaw #define DRV_CTRL_RX_CR5 &CddStp8381Com_DataMirror[0].CtrlRx.aCReg5.ucRaw #define DRV_CTRL_RX_CR6 &CddStp8381Com_DataMirror[0].CtrlRx.aCReg6.ucRaw #define DRV_CTRL_RX_CR7 &CddStp8381Com_DataMirror[0].CtrlRx.aCReg7.ucRaw #define DRV_CTRL_RX_CR8 &CddStp8381Com_DataMirror[0].CtrlRx.aCReg8.ucRaw #define DRV_CTRL_RX_CR9 &CddStp8381Com_DataMirror[0].CtrlRx.aCReg9.ucRaw #define DRV_CTRL_RX_CVA &CddStp8381Com_DataMirror[0].CtrlRx.aCVAReg.ucRaw #define DRV_CTRL_RX_CVB &CddStp8381Com_DataMirror[0].CtrlRx.aCVBReg.ucRaw #define DRV_CTRL_RX_CVB &CddStp8381Com_DataMirror[0].CtrlRx.aCVBReg.ucRaw #define DRV_CTRL_RX_CVC &CddStp8381Com_DataMirror[0].CtrlRx.aCVCReg.ucRaw #define DRV_CTRL_RX_CVD &CddStp8381Com_DataMirror[0].CtrlRx.aCVDReg.ucRaw #define DRV_CTRL_RX_CVLLB &CddStp8381Com_DataMirror[0].CtrlRx.aCVLLBReg.ucRaw #define DRV_CTRL_RX_CVLLA &CddStp8381Com_DataMirror[0].CtrlRx.aCVLLAReg.ucRaw #define DRV_CTRL_RX_CVUL &CddStp8381Com_DataMirror[0].CtrlRx.aCVULReg.ucRaw #define DRV_Rx_Invalid &CddStp8381Com_ucRxInvalid[0] #define DRV_Tx_ZERO &CddStp8381Com_ucTxZero[0] #define Drv_CTRl_TX_ALLDEFAULT &CddStp8381Com_ucAllDefault[0] #define DRV_STA_TX_CLEARSTA1 &CddStp8381Com_TX_ClearSTA1[0] #define DRV_STA_RX_CLEARSTA1 &CddStp8381Com_RX_ClearSTA1[0] #define DRV_STA_TX_CLEARSTA2 &CddStp8381Com_TX_ClearSTA2[0] #define DRV_STA_RX_CLEARSTA2 &CddStp8381Com_RX_ClearSTA2[0] // SPI address for writing #define DRV8381_wALLDEFAULT (ADDR_INVALID|WRITE_OP) #define DRV8381_wCR1 (ADDR_CTRL1|WRITE_OP) #define DRV8381_wCR2 (ADDR_CTRL2|WRITE_OP) #define DRV8381_wCR3 (ADDR_CTRL3|WRITE_OP) #define DRV8381_wCR4 (ADDR_CTRL4|WRITE_OP) #define DRV8381_wCR5 (ADDR_CTRL5|WRITE_OP) #define DRV8381_wCR6 (ADDR_CTRL6|WRITE_OP) #define DRV8381_wCR7 (ADDR_CTRL7|WRITE_OP) #define DRV8381_wCR8 (ADDR_CTRL8|WRITE_OP) #define DRV8381_wCR9 (ADDR_CTRL9|WRITE_OP) #define DRV8381_wCVLLB (ADDR_CVLLB|WRITE_OP) #define DRV8381_wCVLLA (ADDR_CVLLA|WRITE_OP) #define DRV8381_wCVUL (ADDR_CVUL|WRITE_OP) // SPI address for reading #define DRV8381_rCR1 (ADDR_CTRL1|READ_OP) #define DRV8381_rCR2 (ADDR_CTRL2|READ_OP) #define DRV8381_rCR3 (ADDR_CTRL3|READ_OP) #define DRV8381_rCR4 (ADDR_CTRL4|READ_OP) #define DRV8381_rCR5 (ADDR_CTRL5|READ_OP) #define DRV8381_rCR6 (ADDR_CTRL6|READ_OP) #define DRV8381_rCR7 (ADDR_CTRL7|READ_OP) #define DRV8381_rCR8 (ADDR_CTRL8|READ_OP) #define DRV8381_rCR9 (ADDR_CTRL9|READ_OP) #define DRV8381_rCVLLB (ADDR_CVLLB|READ_OP) #define DRV8381_rCVLLA (ADDR_CVLLA|READ_OP) #define DRV8381_rCVUL (ADDR_CVUL|READ_OP) #define DRV8381_rCVA (ADDR_CVA|READ_OP) #define DRV8381_rCVB (ADDR_CVB|READ_OP) #define DRV8381_rCVC (ADDR_CVC|READ_OP) #define DRV8381_rCVD (ADDR_CVD|READ_OP) #define DRV8381_rSTA1 (ADDR_SAT1|READ_AND_CLEAR_OP) #define DRV8381_rSTA2 (ADDR_SAT2|READ_AND_CLEAR_OP) //============================================================================= // constants //============================================================================= // SPI schedule table // one line represents one SPI transmit/receive sequence // tisCddStp8381Com_SpiSchedTable: uint8 ucNextEntry; | uint8 ucAddr; | const uint8* pu16CtrlTx; | uint8* pu16RxDataByte; | uint8* pucRxDummy; static const tisCddStp8381Com_SpiSchedTable CddStp8381Com_SpiSchedTable[19u] = { // ucNextEntry | ucAddr | pu16CtrlTx | pu16RxDataByte | pucRxDummy // idx of next schdlTbl-Entry | SPI addr | SPI ctrl-reg-data for transm. | SPI ctrl/state-reg data for reception | SPI global status byte for reception // TX: SPI register address TX: control reg. RX: ctrl/stat r. RX: status reg. table // data byte 2 data byte 2 data byte 1 index //--------------------------------------------------------------------------------------------------------------------------------------------------------------------- //-------------------------------------------------------------------------Init---------------------------------------------------------------------------------------- { 1u, DRV8381_rSTA1, DRV_STA_TX_STA1, DRV_Rx_Invalid, DRV_STAT_RX_GSB }, // 0 { 2u, DRV8381_rSTA2, DRV_STA_TX_STA2, DRV_STA_RX_STA1, DRV_STAT_RX_GSB }, // 1 { 3u, DRV8381_wCR3, DRV_CTRL_TX_CR3, DRV_STA_RX_STA2, DRV_STAT_RX_GSB }, // 2 { 4u, DRV8381_wCR1, DRV_CTRL_TX_CR1, DRV_CTRL_RX_CR3, DRV_STAT_RX_GSB }, // 3 { 5u, DRV8381_wCR4, DRV_CTRL_TX_CR4, DRV_CTRL_RX_CR1, DRV_STAT_RX_GSB }, // 4 { 6u, DRV8381_wCR6, DRV_CTRL_TX_CR6, DRV_CTRL_RX_CR4, DRV_STAT_RX_GSB }, // 5 { 7u, DRV8381_wCR8, DRV_CTRL_TX_CR8, DRV_CTRL_RX_CR6, DRV_STAT_RX_GSB }, // 6 { 8u, DRV8381_wCVLLB, DRV_CTRL_TX_CVLLB, DRV_CTRL_RX_CR8, DRV_STAT_RX_GSB }, // 7 { 9u, DRV8381_wCVLLA, DRV_CTRL_TX_CVLLA, DRV_CTRL_RX_CVLLB, DRV_STAT_RX_GSB }, // 8 { 10u, DRV8381_wCVUL, DRV_CTRL_TX_CVUL, DRV_CTRL_RX_CVLLA, DRV_STAT_RX_GSB }, // 9 { 11u, DRV8381_rSTA1, DRV_STA_TX_CLEARSTA1, DRV_CTRL_RX_CVUL, DRV_STAT_RX_GSB }, // 10 { 12u, DRV8381_wCR5, DRV_CTRL_TX_CR5, DRV_STA_RX_CLEARSTA1, DRV_STAT_RX_GSB }, // 11 //--------------------------------------------------------------------------------------------------------------------------------------------------------------------- //-------------------------------------------------------------------------TASK---------------------------------------------------------------------------------------- { 13u, DRV8381_wCR3, DRV_CTRL_TX_CR3, DRV_CTRL_RX_CR5, DRV_STAT_RX_GSB }, // 12 { 14u, DRV8381_rSTA1, DRV_STA_TX_STA1, DRV_CTRL_RX_CR3, DRV_STAT_RX_GSB }, // 13 { 15u, DRV8381_rSTA2, DRV_STA_TX_STA2, DRV_STA_RX_STA1, DRV_STAT_RX_GSB }, // 14 { 12u, DRV8381_wCR5, DRV_CTRL_TX_CR5, DRV_STA_RX_STA2, DRV_STAT_RX_GSB }, // 15 { 11u, DRV8381_rSTA1, DRV_STA_TX_CLEARSTA1, DRV_STA_RX_STA2, DRV_STAT_RX_GSB } // 16 }; //----------------------------------------------------------------------------- /// \brief Called after reception of a SPI frame /// /// \descr The function reads the content of CddStp-DataMirror /// CB-Handling config by CddSpi_Cfg.h /// /// \param unIx index of stepper /// /// \return uint32 : Tx data //----------------------------------------------------------------------------- uint32 CddStp_SpiTx(const uint16 unIx) { uint32 ulreturn = 0; if( unIx < CFA_CNT_STP ) { ulreturn = CddStp8381Com_aunTxData[unIx]; } return ulreturn; } //----------------------------------------------------------------------------- /// \brief Called between reception of SPI telegram and /// transmission of next SPI telegram /// /// \descr This function gets raw SPI RX data and stores the contents /// in CddStp8381Com_DataMirror. Then the function determines the /// next SPI telegram. Now the contents of the CddStp8381Com_DataMirror /// are read to start data transmission. /// /// \param uint16 unIx: index to DRV8381 chip /// uint32 unData: 32 bit raw RX data /// /// \return - //----------------------------------------------------------------------------- void CddStp_SpiRx(const uint16 unIx, const uint32 ulData) { uint16 ucLoByte = 0; uint16 ucHiByte = 0; uint8 ucglobalstatus = 0; static uint8 ucPreCmdIdx = 0; static volatile const tisCddStp8381Com_SpiSchedTable* pTabEntry; if( unIx < CFA_CNT_STP ) { if( CddStp8381Com_aucSchedIndex[unIx] >= CDDSTP_COM_SCHED_CYCLE_START_INDEX ) { CddStp_ActAll.sLwrActual.sStatusError.boIsReady = 1u; //Hardware is ready } else { CddStp_ActAll.sLwrActual.sStatusError.boIsReady = 0u; //Hardware is not ready } // prepare for processing index 15 schedule, but boStallFlag == TRUE, change to index 16 to clear stall status in register. if( (TRUE == boStallFlag) && (15 == CddStp8381Com_aucSchedIndex[unIx]) ) { CddStp8381Com_aucSchedIndex[unIx] = 16; } if(( ucPreCmdIdx < CDDSTP_COM_SCHED_CYCLE_START_INDEX ) && ( CddStp8381Com_aucSchedIndex[unIx] >= CDDSTP_COM_SCHED_CYCLE_START_INDEX )) { teStpState = STP_STATE_REF_POINT; } ucPreCmdIdx = CddStp8381Com_aucSchedIndex[unIx]; pTabEntry = &CddStp8381Com_SpiSchedTable[CddStp8381Com_aucSchedIndex[unIx]]; //Pointer to actual schedule table entry ucglobalstatus = (uint8)((0xFF00u & ulData) >> 8u); //Get global status byte form SPI RX ucHiByte = (uint16)((0xFF0000u & ulData) >> 8u); //Get receive data high form SPI RX ucLoByte = (uint16)((0xFF000000u & ulData) >> 24u); //Get receive data low form SPI RX * pTabEntry->pucRxDummy = ucglobalstatus; //Map global status byte to actual schedule * pTabEntry->pu16RxDataByte = ucHiByte | ucLoByte; //Map receive data to actual schedule /* after SAT1 reading, check stall flag */ if(14u == CddStp8381Com_aucSchedIndex[unIx]) { CddStp8381_CheckSteperStall(); } CddStp8381Com_aunTxData[unIx] = (((uint32)(* pTabEntry->pu16CtrlTx & 0xFFu) << 16u)| \ (uint32)(* pTabEntry->pu16CtrlTx & 0xFF00u)| \ (uint32)(pTabEntry->ucAddr)) << 8u; CddStp8381Com_aucSchedIndex[unIx] = pTabEntry->ucNextEntry; //Switch to next schedule table entry } } //----------------------------------------------------------------------------- /// \brief CddStp8381_SpiGetConfig /// /// \descr Provides device population footprint to CddSpi /// to handle transmissions with Stps /// /// \param punData: Data pointer to provide footprint /// /// \return boolean /// TRUE : Footprint data valid /// FALSE: Footprint data invalid /// //----------------------------------------------------------------------------- boolean CddStp8381_SpiGetConfig(uint16* punData) { boolean boRetVal = FALSE; *punData = 0u; if ( CDDSTP8381_EftDataValid() != FALSE ) // end of line data available { for (uint32 ulDevice = 0u; ulDevice < CDDNSD8381_Cfg_NbOfDevices; ulDevice++) { uint32 ulMask = (CDDSTP8381_ECUVARCFG_ucDrvType(ulDevice) != 0u) ? 1u : 0u; *punData |= (uint16)(ulMask << ulDevice); } boRetVal = TRUE; } return boRetVal; } void CddStp8381Com_ResetScheduleIndex(void) { uint8 ucTmpIdx; for ( ucTmpIdx=0; ucTmpIdx < CFA_CNT_STP; ucTmpIdx++ ) { CddStp8381Com_aucSchedIndex[ucTmpIdx] = CDDSTP8381_SPI_SCHED_START_IDX_ZERO; } }