#ifndef PORT_2020_06_08_H_ #define PORT_2020_06_08_H_ //============================================================================= // GPIO CONFIG (CYPRESS TRAVEO II) //============================================================================= //============================================================================= // includes //============================================================================= #include "Std_Types.h" //============================================================================= // types //============================================================================= /* HSIOM Connections */ typedef enum { /* Generic HSIOM connections */ HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ /* P0.0 */ P0_0_GPIO = 0, /* GPIO controls 'out' */ P0_0_AMUXA = 4, /* Analog mux bus A */ P0_0_AMUXB = 5, /* Analog mux bus B */ P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P0_0_TCPWM0_LINE18 = 8, /* Digital Active - tcpwm[0].line[18]:1 */ P0_0_TCPWM0_LINE_COMPL22 = 9, /* Digital Active - tcpwm[0].line_compl[22]:1 */ P0_0_TCPWM0_TR_ONE_CNT_IN54 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[54]:1 */ P0_0_TCPWM0_TR_ONE_CNT_IN67 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[67]:1 */ P0_0_SCB0_UART_RX = 17, /* Digital Active - scb[0].uart_rx:0 */ P0_0_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:2 */ P0_0_LIN0_LIN_RX1 = 20, /* Digital Active - lin[0].lin_rx[1]:0 */ P0_0_SCB0_SPI_MISO = 30, /* Digital Deep Sleep - scb[0].spi_miso:0 */ /* P0.1 */ P0_1_GPIO = 0, /* GPIO controls 'out' */ P0_1_AMUXA = 4, /* Analog mux bus A */ P0_1_AMUXB = 5, /* Analog mux bus B */ P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P0_1_TCPWM0_LINE17 = 8, /* Digital Active - tcpwm[0].line[17]:1 */ P0_1_TCPWM0_LINE_COMPL18 = 9, /* Digital Active - tcpwm[0].line_compl[18]:1 */ P0_1_TCPWM0_TR_ONE_CNT_IN51 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[51]:1 */ P0_1_TCPWM0_TR_ONE_CNT_IN55 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[55]:1 */ P0_1_SCB0_UART_TX = 17, /* Digital Active - scb[0].uart_tx:0 */ P0_1_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:2 */ P0_1_LIN0_LIN_TX1 = 20, /* Digital Active - lin[0].lin_tx[1]:0 */ P0_1_SCB0_SPI_MOSI = 30, /* Digital Deep Sleep - scb[0].spi_mosi:0 */ /* P0.2 */ P0_2_GPIO = 0, /* GPIO controls 'out' */ P0_2_AMUXA = 4, /* Analog mux bus A */ P0_2_AMUXB = 5, /* Analog mux bus B */ P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P0_2_TCPWM0_LINE14 = 8, /* Digital Active - tcpwm[0].line[14]:1 */ P0_2_TCPWM0_LINE_COMPL17 = 9, /* Digital Active - tcpwm[0].line_compl[17]:1 */ P0_2_TCPWM0_TR_ONE_CNT_IN42 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[42]:1 */ P0_2_TCPWM0_TR_ONE_CNT_IN52 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[52]:1 */ P0_2_SCB0_I2C_SCL = 14, /* Digital Deep Sleep - scb[0].i2c_scl:0 */ P0_2_SCB0_UART_RTS = 17, /* Digital Active - scb[0].uart_rts:0 */ P0_2_LIN0_LIN_EN1 = 20, /* Digital Active - lin[0].lin_en[1]:0 */ P0_2_CANFD0_TTCAN_TX1 = 21, /* Digital Active - canfd[0].ttcan_tx[1]:0 */ P0_2_SCB0_SPI_CLK = 30, /* Digital Deep Sleep - scb[0].spi_clk:0 */ /* P0.3 */ P0_3_GPIO = 0, /* GPIO controls 'out' */ P0_3_AMUXA = 4, /* Analog mux bus A */ P0_3_AMUXB = 5, /* Analog mux bus B */ P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P0_3_TCPWM0_LINE13 = 8, /* Digital Active - tcpwm[0].line[13]:1 */ P0_3_TCPWM0_LINE_COMPL14 = 9, /* Digital Active - tcpwm[0].line_compl[14]:1 */ P0_3_TCPWM0_TR_ONE_CNT_IN39 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[39]:1 */ P0_3_TCPWM0_TR_ONE_CNT_IN43 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[43]:1 */ P0_3_SCB0_I2C_SDA = 14, /* Digital Deep Sleep - scb[0].i2c_sda:0 */ P0_3_SCB0_UART_CTS = 17, /* Digital Active - scb[0].uart_cts:0 */ P0_3_CANFD0_TTCAN_RX1 = 21, /* Digital Active - canfd[0].ttcan_rx[1]:0 */ P0_3_SCB0_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[0].spi_select0:0 */ /* P2.0 */ P2_0_GPIO = 0, /* GPIO controls 'out' */ P2_0_AMUXA = 4, /* Analog mux bus A */ P2_0_AMUXB = 5, /* Analog mux bus B */ P2_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P2_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P2_0_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:1 */ P2_0_TCPWM0_LINE_COMPL8 = 9, /* Digital Active - tcpwm[0].line_compl[8]:1 */ P2_0_TCPWM0_TR_ONE_CNT_IN21 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[21]:1 */ P2_0_TCPWM0_TR_ONE_CNT_IN25 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[25]:1 */ P2_0_TCPWM0_TR_ONE_CNT_IN1548 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1548]:0 */ P2_0_SCB7_UART_RX = 17, /* Digital Active - scb[7].uart_rx:0 */ P2_0_SCB7_SPI_MISO = 19, /* Digital Active - scb[7].spi_miso:0 */ P2_0_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:0 */ P2_0_CANFD0_TTCAN_TX0 = 21, /* Digital Active - canfd[0].ttcan_tx[0]:0 */ P2_0_PERI_TR_IO_INPUT2 = 26, /* Digital Active - peri.tr_io_input[2]:0 */ P2_0_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn:0 */ P2_0_SCB0_SPI_SELECT1 = 30, /* Digital Deep Sleep - scb[0].spi_select1:0 */ /* P2.1 */ P2_1_GPIO = 0, /* GPIO controls 'out' */ P2_1_AMUXA = 4, /* Analog mux bus A */ P2_1_AMUXB = 5, /* Analog mux bus B */ P2_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P2_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P2_1_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:1 */ P2_1_TCPWM0_LINE_COMPL7 = 9, /* Digital Active - tcpwm[0].line_compl[7]:1 */ P2_1_TCPWM0_TR_ONE_CNT_IN18 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[18]:1 */ P2_1_TCPWM0_TR_ONE_CNT_IN22 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[22]:1 */ P2_1_TCPWM0_TR_ONE_CNT_IN1551 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1551]:0 */ P2_1_SCB7_UART_TX = 17, /* Digital Active - scb[7].uart_tx:0 */ P2_1_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:0 */ P2_1_SCB7_SPI_MOSI = 19, /* Digital Active - scb[7].spi_mosi:0 */ P2_1_LIN0_LIN_TX0 = 20, /* Digital Active - lin[0].lin_tx[0]:0 */ P2_1_CANFD0_TTCAN_RX0 = 21, /* Digital Active - canfd[0].ttcan_rx[0]:0 */ P2_1_PERI_TR_IO_INPUT3 = 26, /* Digital Active - peri.tr_io_input[3]:0 */ P2_1_SCB0_SPI_SELECT2 = 30, /* Digital Deep Sleep - scb[0].spi_select2:0 */ /* P2.2 */ P2_2_GPIO = 0, /* GPIO controls 'out' */ P2_2_AMUXA = 4, /* Analog mux bus A */ P2_2_AMUXB = 5, /* Analog mux bus B */ P2_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P2_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P2_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:1 */ P2_2_TCPWM0_LINE_COMPL6 = 9, /* Digital Active - tcpwm[0].line_compl[6]:1 */ P2_2_TCPWM0_TR_ONE_CNT_IN15 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[15]:1 */ P2_2_TCPWM0_TR_ONE_CNT_IN19 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[19]:1 */ P2_2_TCPWM0_TR_ONE_CNT_IN1554 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1554]:0 */ P2_2_SCB7_UART_RTS = 17, /* Digital Active - scb[7].uart_rts:0 */ P2_2_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:0 */ P2_2_SCB7_SPI_CLK = 19, /* Digital Active - scb[7].spi_clk:0 */ P2_2_LIN0_LIN_EN0 = 20, /* Digital Active - lin[0].lin_en[0]:0 */ P2_2_PERI_TR_IO_INPUT4 = 26, /* Digital Active - peri.tr_io_input[4]:0 */ P2_2_SCB0_SPI_SELECT3 = 30, /* Digital Deep Sleep - scb[0].spi_select3:0 */ /* P2.3 */ P2_3_GPIO = 0, /* GPIO controls 'out' */ P2_3_AMUXA = 4, /* Analog mux bus A */ P2_3_AMUXB = 5, /* Analog mux bus B */ P2_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P2_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P2_3_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:1 */ P2_3_TCPWM0_LINE_COMPL5 = 9, /* Digital Active - tcpwm[0].line_compl[5]:1 */ P2_3_TCPWM0_TR_ONE_CNT_IN12 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[12]:1 */ P2_3_TCPWM0_TR_ONE_CNT_IN16 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[16]:1 */ P2_3_TCPWM0_TR_ONE_CNT_IN1557 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1557]:0 */ P2_3_SCB7_UART_CTS = 17, /* Digital Active - scb[7].uart_cts:0 */ P2_3_SCB7_SPI_SELECT0 = 19, /* Digital Active - scb[7].spi_select0:0 */ P2_3_LIN0_LIN_RX5 = 20, /* Digital Active - lin[0].lin_rx[5]:1 */ P2_3_PERI_TR_IO_INPUT5 = 26, /* Digital Active - peri.tr_io_input[5]:0 */ /* P3.0 */ P3_0_GPIO = 0, /* GPIO controls 'out' */ P3_0_AMUXA = 4, /* Analog mux bus A */ P3_0_AMUXB = 5, /* Analog mux bus B */ P3_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P3_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P3_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ P3_0_TCPWM0_LINE_COMPL2 = 9, /* Digital Active - tcpwm[0].line_compl[2]:1 */ P3_0_TCPWM0_TR_ONE_CNT_IN3 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:1 */ P3_0_TCPWM0_TR_ONE_CNT_IN7 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[7]:1 */ P3_0_TCPWM0_LINE_COMPL518 = 16, /* Digital Active - tcpwm[0].line_compl[518]:0 */ P3_0_SCB6_UART_RX = 17, /* Digital Active - scb[6].uart_rx:0 */ P3_0_SCB6_SPI_MISO = 19, /* Digital Active - scb[6].spi_miso:0 */ P3_0_CANFD0_TTCAN_TX3 = 21, /* Digital Active - canfd[0].ttcan_tx[3]:0 */ P3_0_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:0 */ /* P3.1 */ P3_1_GPIO = 0, /* GPIO controls 'out' */ P3_1_AMUXA = 4, /* Analog mux bus A */ P3_1_AMUXB = 5, /* Analog mux bus B */ P3_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P3_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P3_1_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ P3_1_TCPWM0_LINE_COMPL1 = 9, /* Digital Active - tcpwm[0].line_compl[1]:1 */ P3_1_TCPWM0_TR_ONE_CNT_IN0 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:1 */ P3_1_TCPWM0_TR_ONE_CNT_IN4 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[4]:1 */ P3_1_TCPWM0_LINE_COMPL519 = 16, /* Digital Active - tcpwm[0].line_compl[519]:0 */ P3_1_SCB6_UART_TX = 17, /* Digital Active - scb[6].uart_tx:0 */ P3_1_SCB6_I2C_SDA = 18, /* Digital Active - scb[6].i2c_sda:0 */ P3_1_SCB6_SPI_MOSI = 19, /* Digital Active - scb[6].spi_mosi:0 */ P3_1_CANFD0_TTCAN_RX3 = 21, /* Digital Active - canfd[0].ttcan_rx[3]:0 */ P3_1_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:0 */ /* P5.0 */ P5_0_GPIO = 0, /* GPIO controls 'out' */ P5_0_AMUXA = 4, /* Analog mux bus A */ P5_0_AMUXB = 5, /* Analog mux bus B */ P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P5_0_TCPWM0_LINE9 = 8, /* Digital Active - tcpwm[0].line[9]:0 */ P5_0_TCPWM0_LINE_COMPL8 = 9, /* Digital Active - tcpwm[0].line_compl[8]:0 */ P5_0_TCPWM0_TR_ONE_CNT_IN27 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[27]:0 */ P5_0_TCPWM0_TR_ONE_CNT_IN25 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[25]:0 */ P5_0_SCB5_SPI_SELECT2 = 19, /* Digital Active - scb[5].spi_select2:0 */ P5_0_LIN0_LIN_RX7 = 20, /* Digital Active - lin[0].lin_rx[7]:0 */ /* P5.1 */ P5_1_GPIO = 0, /* GPIO controls 'out' */ P5_1_AMUXA = 4, /* Analog mux bus A */ P5_1_AMUXB = 5, /* Analog mux bus B */ P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P5_1_TCPWM0_LINE10 = 8, /* Digital Active - tcpwm[0].line[10]:0 */ P5_1_TCPWM0_LINE_COMPL9 = 9, /* Digital Active - tcpwm[0].line_compl[9]:0 */ P5_1_TCPWM0_TR_ONE_CNT_IN30 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[30]:0 */ P5_1_TCPWM0_TR_ONE_CNT_IN28 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[28]:0 */ P5_1_LIN0_LIN_TX7 = 20, /* Digital Active - lin[0].lin_tx[7]:0 */ /* P5.2 */ P5_2_GPIO = 0, /* GPIO controls 'out' */ P5_2_AMUXA = 4, /* Analog mux bus A */ P5_2_AMUXB = 5, /* Analog mux bus B */ P5_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P5_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P5_2_TCPWM0_LINE11 = 8, /* Digital Active - tcpwm[0].line[11]:0 */ P5_2_TCPWM0_LINE_COMPL10 = 9, /* Digital Active - tcpwm[0].line_compl[10]:0 */ P5_2_TCPWM0_TR_ONE_CNT_IN33 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[33]:0 */ P5_2_TCPWM0_TR_ONE_CNT_IN31 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[31]:0 */ P5_2_LIN0_LIN_EN7 = 20, /* Digital Active - lin[0].lin_en[7]:0 */ /* P5.3 */ P5_3_GPIO = 0, /* GPIO controls 'out' */ P5_3_AMUXA = 4, /* Analog mux bus A */ P5_3_AMUXB = 5, /* Analog mux bus B */ P5_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P5_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P5_3_TCPWM0_LINE12 = 8, /* Digital Active - tcpwm[0].line[12]:0 */ P5_3_TCPWM0_LINE_COMPL11 = 9, /* Digital Active - tcpwm[0].line_compl[11]:0 */ P5_3_TCPWM0_TR_ONE_CNT_IN36 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[36]:0 */ P5_3_TCPWM0_TR_ONE_CNT_IN34 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[34]:0 */ P5_3_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:0 */ /* P6.0 */ P6_0_GPIO = 0, /* GPIO controls 'out' */ P6_0_AMUXA = 4, /* Analog mux bus A */ P6_0_AMUXB = 5, /* Analog mux bus B */ P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P6_0_TCPWM0_LINE256 = 8, /* Digital Active - tcpwm[0].line[256]:0 */ P6_0_TCPWM0_LINE_COMPL14 = 9, /* Digital Active - tcpwm[0].line_compl[14]:0 */ P6_0_TCPWM0_TR_ONE_CNT_IN768 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[768]:0 */ P6_0_TCPWM0_TR_ONE_CNT_IN43 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[43]:0 */ P6_0_SCB4_UART_RX = 17, /* Digital Active - scb[4].uart_rx:0 */ P6_0_SCB4_SPI_MISO = 19, /* Digital Active - scb[4].spi_miso:0 */ P6_0_LIN0_LIN_RX3 = 20, /* Digital Active - lin[0].lin_rx[3]:0 */ /* P6.1 */ P6_1_GPIO = 0, /* GPIO controls 'out' */ P6_1_AMUXA = 4, /* Analog mux bus A */ P6_1_AMUXB = 5, /* Analog mux bus B */ P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P6_1_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ P6_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:0 */ P6_1_TCPWM0_TR_ONE_CNT_IN0 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:0 */ P6_1_TCPWM0_TR_ONE_CNT_IN769 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[769]:0 */ P6_1_SCB4_UART_TX = 17, /* Digital Active - scb[4].uart_tx:0 */ P6_1_SCB4_I2C_SDA = 18, /* Digital Active - scb[4].i2c_sda:0 */ P6_1_SCB4_SPI_MOSI = 19, /* Digital Active - scb[4].spi_mosi:0 */ P6_1_LIN0_LIN_TX3 = 20, /* Digital Active - lin[0].lin_tx[3]:0 */ /* P6.2 */ P6_2_GPIO = 0, /* GPIO controls 'out' */ P6_2_AMUXA = 4, /* Analog mux bus A */ P6_2_AMUXB = 5, /* Analog mux bus B */ P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P6_2_TCPWM0_LINE257 = 8, /* Digital Active - tcpwm[0].line[257]:0 */ P6_2_TCPWM0_LINE_COMPL0 = 9, /* Digital Active - tcpwm[0].line_compl[0]:0 */ P6_2_TCPWM0_TR_ONE_CNT_IN771 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[771]:0 */ P6_2_TCPWM0_TR_ONE_CNT_IN1 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:0 */ P6_2_SCB4_UART_RTS = 17, /* Digital Active - scb[4].uart_rts:0 */ P6_2_SCB4_I2C_SCL = 18, /* Digital Active - scb[4].i2c_scl:0 */ P6_2_SCB4_SPI_CLK = 19, /* Digital Active - scb[4].spi_clk:0 */ P6_2_LIN0_LIN_EN3 = 20, /* Digital Active - lin[0].lin_en[3]:0 */ P6_2_CANFD0_TTCAN_TX2 = 21, /* Digital Active - canfd[0].ttcan_tx[2]:0 */ /* P6.3 */ P6_3_GPIO = 0, /* GPIO controls 'out' */ P6_3_AMUXA = 4, /* Analog mux bus A */ P6_3_AMUXB = 5, /* Analog mux bus B */ P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P6_3_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ P6_3_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:0 */ P6_3_TCPWM0_TR_ONE_CNT_IN3 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:0 */ P6_3_TCPWM0_TR_ONE_CNT_IN772 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[772]:0 */ P6_3_SCB4_UART_CTS = 17, /* Digital Active - scb[4].uart_cts:0 */ P6_3_SCB4_SPI_SELECT0 = 19, /* Digital Active - scb[4].spi_select0:0 */ P6_3_LIN0_LIN_RX4 = 20, /* Digital Active - lin[0].lin_rx[4]:0 */ P6_3_CANFD0_TTCAN_RX2 = 21, /* Digital Active - canfd[0].ttcan_rx[2]:0 */ P6_3_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:0 */ /* P6.4 */ P6_4_GPIO = 0, /* GPIO controls 'out' */ P6_4_AMUXA = 4, /* Analog mux bus A */ P6_4_AMUXB = 5, /* Analog mux bus B */ P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P6_4_TCPWM0_LINE258 = 8, /* Digital Active - tcpwm[0].line[258]:0 */ P6_4_TCPWM0_LINE_COMPL1 = 9, /* Digital Active - tcpwm[0].line_compl[1]:0 */ P6_4_TCPWM0_TR_ONE_CNT_IN774 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[774]:0 */ P6_4_TCPWM0_TR_ONE_CNT_IN4 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[4]:0 */ P6_4_SCB4_SPI_SELECT1 = 19, /* Digital Active - scb[4].spi_select1:0 */ P6_4_LIN0_LIN_TX4 = 20, /* Digital Active - lin[0].lin_tx[4]:0 */ /* P6.5 */ P6_5_GPIO = 0, /* GPIO controls 'out' */ P6_5_AMUXA = 4, /* Analog mux bus A */ P6_5_AMUXB = 5, /* Analog mux bus B */ P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P6_5_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ P6_5_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:0 */ P6_5_TCPWM0_TR_ONE_CNT_IN6 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[6]:0 */ P6_5_TCPWM0_TR_ONE_CNT_IN775 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[775]:0 */ P6_5_SCB4_SPI_SELECT2 = 19, /* Digital Active - scb[4].spi_select2:0 */ P6_5_LIN0_LIN_EN4 = 20, /* Digital Active - lin[0].lin_en[4]:0 */ /* P7.0 */ P7_0_GPIO = 0, /* GPIO controls 'out' */ P7_0_AMUXA = 4, /* Analog mux bus A */ P7_0_AMUXB = 5, /* Analog mux bus B */ P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P7_0_TCPWM0_LINE260 = 8, /* Digital Active - tcpwm[0].line[260]:0 */ P7_0_TCPWM0_LINE_COMPL3 = 9, /* Digital Active - tcpwm[0].line_compl[3]:0 */ P7_0_TCPWM0_TR_ONE_CNT_IN780 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[780]:0 */ P7_0_TCPWM0_TR_ONE_CNT_IN10 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[10]:0 */ P7_0_SCB5_UART_RX = 17, /* Digital Active - scb[5].uart_rx:1 */ P7_0_SCB5_SPI_MISO = 19, /* Digital Active - scb[5].spi_miso:1 */ P7_0_LIN0_LIN_RX4 = 20, /* Digital Active - lin[0].lin_rx[4]:1 */ P7_0_CXPI0_CXPI_RX0 = 22, /* Digital Active - cxpi[0].cxpi_rx[0]:0 */ /* P7.1 */ P7_1_GPIO = 0, /* GPIO controls 'out' */ P7_1_AMUXA = 4, /* Analog mux bus A */ P7_1_AMUXB = 5, /* Analog mux bus B */ P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P7_1_TCPWM0_LINE15 = 8, /* Digital Active - tcpwm[0].line[15]:0 */ P7_1_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:0 */ P7_1_TCPWM0_TR_ONE_CNT_IN45 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[45]:0 */ P7_1_TCPWM0_TR_ONE_CNT_IN781 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[781]:0 */ P7_1_SCB5_UART_TX = 17, /* Digital Active - scb[5].uart_tx:1 */ P7_1_SCB5_I2C_SDA = 18, /* Digital Active - scb[5].i2c_sda:1 */ P7_1_SCB5_SPI_MOSI = 19, /* Digital Active - scb[5].spi_mosi:1 */ P7_1_LIN0_LIN_TX4 = 20, /* Digital Active - lin[0].lin_tx[4]:1 */ P7_1_CXPI0_CXPI_TX0 = 22, /* Digital Active - cxpi[0].cxpi_tx[0]:0 */ /* P7.2 */ P7_2_GPIO = 0, /* GPIO controls 'out' */ P7_2_AMUXA = 4, /* Analog mux bus A */ P7_2_AMUXB = 5, /* Analog mux bus B */ P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P7_2_TCPWM0_LINE261 = 8, /* Digital Active - tcpwm[0].line[261]:0 */ P7_2_TCPWM0_LINE_COMPL15 = 9, /* Digital Active - tcpwm[0].line_compl[15]:0 */ P7_2_TCPWM0_TR_ONE_CNT_IN783 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[783]:0 */ P7_2_TCPWM0_TR_ONE_CNT_IN46 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[46]:0 */ P7_2_SCB5_UART_RTS = 17, /* Digital Active - scb[5].uart_rts:1 */ P7_2_SCB5_I2C_SCL = 18, /* Digital Active - scb[5].i2c_scl:1 */ P7_2_SCB5_SPI_CLK = 19, /* Digital Active - scb[5].spi_clk:1 */ P7_2_LIN0_LIN_EN4 = 20, /* Digital Active - lin[0].lin_en[4]:1 */ P7_2_CXPI0_CXPI_EN0 = 22, /* Digital Active - cxpi[0].cxpi_en[0]:0 */ /* P7.3 */ P7_3_GPIO = 0, /* GPIO controls 'out' */ P7_3_AMUXA = 4, /* Analog mux bus A */ P7_3_AMUXB = 5, /* Analog mux bus B */ P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P7_3_TCPWM0_LINE16 = 8, /* Digital Active - tcpwm[0].line[16]:0 */ P7_3_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:0 */ P7_3_TCPWM0_TR_ONE_CNT_IN48 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[48]:0 */ P7_3_TCPWM0_TR_ONE_CNT_IN784 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[784]:0 */ P7_3_SCB5_UART_CTS = 17, /* Digital Active - scb[5].uart_cts:1 */ P7_3_SCB5_SPI_SELECT0 = 19, /* Digital Active - scb[5].spi_select0:1 */ /* P7.4 */ P7_4_GPIO = 0, /* GPIO controls 'out' */ P7_4_AMUXA = 4, /* Analog mux bus A */ P7_4_AMUXB = 5, /* Analog mux bus B */ P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P7_4_TCPWM0_LINE262 = 8, /* Digital Active - tcpwm[0].line[262]:0 */ P7_4_TCPWM0_LINE_COMPL16 = 9, /* Digital Active - tcpwm[0].line_compl[16]:0 */ P7_4_TCPWM0_TR_ONE_CNT_IN786 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[786]:0 */ P7_4_TCPWM0_TR_ONE_CNT_IN49 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[49]:0 */ P7_4_SCB5_SPI_SELECT1 = 19, /* Digital Active - scb[5].spi_select1:1 */ /* P7.5 */ P7_5_GPIO = 0, /* GPIO controls 'out' */ P7_5_AMUXA = 4, /* Analog mux bus A */ P7_5_AMUXB = 5, /* Analog mux bus B */ P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P7_5_TCPWM0_LINE17 = 8, /* Digital Active - tcpwm[0].line[17]:0 */ P7_5_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:0 */ P7_5_TCPWM0_TR_ONE_CNT_IN51 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[51]:0 */ P7_5_TCPWM0_TR_ONE_CNT_IN787 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[787]:0 */ P7_5_SCB5_SPI_SELECT2 = 19, /* Digital Active - scb[5].spi_select2:1 */ P7_5_LIN0_LIN_RX10 = 20, /* Digital Active - lin[0].lin_rx[10]:0 */ /* P8.0 */ P8_0_GPIO = 0, /* GPIO controls 'out' */ P8_0_AMUXA = 4, /* Analog mux bus A */ P8_0_AMUXB = 5, /* Analog mux bus B */ P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P8_0_TCPWM0_LINE19 = 8, /* Digital Active - tcpwm[0].line[19]:0 */ P8_0_TCPWM0_LINE_COMPL18 = 9, /* Digital Active - tcpwm[0].line_compl[18]:0 */ P8_0_TCPWM0_TR_ONE_CNT_IN57 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[57]:0 */ P8_0_TCPWM0_TR_ONE_CNT_IN55 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[55]:0 */ P8_0_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:1 */ P8_0_CANFD0_TTCAN_TX0 = 21, /* Digital Active - canfd[0].ttcan_tx[0]:1 */ /* P8.1 */ P8_1_GPIO = 0, /* GPIO controls 'out' */ P8_1_AMUXA = 4, /* Analog mux bus A */ P8_1_AMUXB = 5, /* Analog mux bus B */ P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P8_1_TCPWM0_LINE20 = 8, /* Digital Active - tcpwm[0].line[20]:0 */ P8_1_TCPWM0_LINE_COMPL19 = 9, /* Digital Active - tcpwm[0].line_compl[19]:0 */ P8_1_TCPWM0_TR_ONE_CNT_IN60 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[60]:0 */ P8_1_TCPWM0_TR_ONE_CNT_IN58 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[58]:0 */ P8_1_LIN0_LIN_TX2 = 20, /* Digital Active - lin[0].lin_tx[2]:1 */ P8_1_CANFD0_TTCAN_RX0 = 21, /* Digital Active - canfd[0].ttcan_rx[0]:1 */ P8_1_PERI_TR_IO_INPUT14 = 26, /* Digital Active - peri.tr_io_input[14]:0 */ /* P8.2 */ P8_2_GPIO = 0, /* GPIO controls 'out' */ P8_2_AMUXA = 4, /* Analog mux bus A */ P8_2_AMUXB = 5, /* Analog mux bus B */ P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P8_2_TCPWM0_LINE21 = 8, /* Digital Active - tcpwm[0].line[21]:0 */ P8_2_TCPWM0_LINE_COMPL20 = 9, /* Digital Active - tcpwm[0].line_compl[20]:0 */ P8_2_TCPWM0_TR_ONE_CNT_IN63 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[63]:0 */ P8_2_TCPWM0_TR_ONE_CNT_IN61 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[61]:0 */ P8_2_LIN0_LIN_EN2 = 20, /* Digital Active - lin[0].lin_en[2]:1 */ P8_2_PERI_TR_IO_INPUT15 = 26, /* Digital Active - peri.tr_io_input[15]:0 */ /* P11.0 */ P11_0_GPIO = 0, /* GPIO controls 'out' */ P11_0_AMUXA = 4, /* Analog mux bus A */ P11_0_AMUXB = 5, /* Analog mux bus B */ P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ /* P11.1 */ P11_1_GPIO = 0, /* GPIO controls 'out' */ P11_1_AMUXA = 4, /* Analog mux bus A */ P11_1_AMUXB = 5, /* Analog mux bus B */ P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ /* P11.2 */ P11_2_GPIO = 0, /* GPIO controls 'out' */ P11_2_AMUXA = 4, /* Analog mux bus A */ P11_2_AMUXB = 5, /* Analog mux bus B */ P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ /* P12.0 */ P12_0_GPIO = 0, /* GPIO controls 'out' */ P12_0_AMUXA = 4, /* Analog mux bus A */ P12_0_AMUXB = 5, /* Analog mux bus B */ P12_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P12_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P12_0_TCPWM0_LINE36 = 8, /* Digital Active - tcpwm[0].line[36]:0 */ P12_0_TCPWM0_LINE_COMPL35 = 9, /* Digital Active - tcpwm[0].line_compl[35]:0 */ P12_0_TCPWM0_TR_ONE_CNT_IN108 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[108]:0 */ P12_0_TCPWM0_TR_ONE_CNT_IN106 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[106]:0 */ P12_0_CANFD0_TTCAN_TX2 = 21, /* Digital Active - canfd[0].ttcan_tx[2]:1 */ P12_0_PERI_TR_IO_INPUT20 = 26, /* Digital Active - peri.tr_io_input[20]:0 */ /* P12.1 */ P12_1_GPIO = 0, /* GPIO controls 'out' */ P12_1_AMUXA = 4, /* Analog mux bus A */ P12_1_AMUXB = 5, /* Analog mux bus B */ P12_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P12_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P12_1_TCPWM0_LINE37 = 8, /* Digital Active - tcpwm[0].line[37]:0 */ P12_1_TCPWM0_LINE_COMPL36 = 9, /* Digital Active - tcpwm[0].line_compl[36]:0 */ P12_1_TCPWM0_TR_ONE_CNT_IN111 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[111]:0 */ P12_1_TCPWM0_TR_ONE_CNT_IN109 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[109]:0 */ P12_1_LIN0_LIN_EN6 = 20, /* Digital Active - lin[0].lin_en[6]:0 */ P12_1_CANFD0_TTCAN_RX2 = 21, /* Digital Active - canfd[0].ttcan_rx[2]:1 */ P12_1_PERI_TR_IO_INPUT21 = 26, /* Digital Active - peri.tr_io_input[21]:0 */ /* P12.2 */ P12_2_GPIO = 0, /* GPIO controls 'out' */ P12_2_AMUXA = 4, /* Analog mux bus A */ P12_2_AMUXB = 5, /* Analog mux bus B */ P12_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P12_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P12_2_TCPWM0_LINE38 = 8, /* Digital Active - tcpwm[0].line[38]:0 */ P12_2_TCPWM0_LINE_COMPL37 = 9, /* Digital Active - tcpwm[0].line_compl[37]:0 */ P12_2_TCPWM0_TR_ONE_CNT_IN114 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[114]:0 */ P12_2_TCPWM0_TR_ONE_CNT_IN112 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[112]:0 */ P12_2_PASS0_SAR_EXT_MUX_EN1 = 16, /* Digital Active - pass[0].sar_ext_mux_en[1] */ P12_2_LIN0_LIN_RX6 = 20, /* Digital Active - lin[0].lin_rx[6]:0 */ /* P12.3 */ P12_3_GPIO = 0, /* GPIO controls 'out' */ P12_3_AMUXA = 4, /* Analog mux bus A */ P12_3_AMUXB = 5, /* Analog mux bus B */ P12_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P12_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P12_3_TCPWM0_LINE39 = 8, /* Digital Active - tcpwm[0].line[39]:0 */ P12_3_TCPWM0_LINE_COMPL38 = 9, /* Digital Active - tcpwm[0].line_compl[38]:0 */ P12_3_TCPWM0_TR_ONE_CNT_IN117 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[117]:0 */ P12_3_TCPWM0_TR_ONE_CNT_IN115 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[115]:0 */ P12_3_PASS0_SAR_EXT_MUX_SEL3 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[3] */ P12_3_LIN0_LIN_TX6 = 20, /* Digital Active - lin[0].lin_tx[6]:0 */ /* P12.4 */ P12_4_GPIO = 0, /* GPIO controls 'out' */ P12_4_AMUXA = 4, /* Analog mux bus A */ P12_4_AMUXB = 5, /* Analog mux bus B */ P12_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P12_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P12_4_TCPWM0_LINE40 = 8, /* Digital Active - tcpwm[0].line[40]:0 */ P12_4_TCPWM0_LINE_COMPL39 = 9, /* Digital Active - tcpwm[0].line_compl[39]:0 */ P12_4_TCPWM0_TR_ONE_CNT_IN120 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[120]:0 */ P12_4_TCPWM0_TR_ONE_CNT_IN118 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[118]:0 */ P12_4_PASS0_SAR_EXT_MUX_SEL4 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[4] */ /* P13.0 */ P13_0_GPIO = 0, /* GPIO controls 'out' */ P13_0_AMUXA = 4, /* Analog mux bus A */ P13_0_AMUXB = 5, /* Analog mux bus B */ P13_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P13_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P13_0_TCPWM0_LINE264 = 8, /* Digital Active - tcpwm[0].line[264]:0 */ P13_0_TCPWM0_LINE_COMPL43 = 9, /* Digital Active - tcpwm[0].line_compl[43]:0 */ P13_0_TCPWM0_TR_ONE_CNT_IN792 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[792]:0 */ P13_0_TCPWM0_TR_ONE_CNT_IN130 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[130]:0 */ P13_0_PASS0_SAR_EXT_MUX_SEL6 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[6] */ P13_0_SCB3_UART_RX = 17, /* Digital Active - scb[3].uart_rx:0 */ P13_0_SCB3_SPI_MISO = 19, /* Digital Active - scb[3].spi_miso:0 */ P13_0_LIN0_LIN_RX3 = 20, /* Digital Active - lin[0].lin_rx[3]:1 */ P13_0_CXPI0_CXPI_RX1 = 22, /* Digital Active - cxpi[0].cxpi_rx[1]:0 */ /* P13.1 */ P13_1_GPIO = 0, /* GPIO controls 'out' */ P13_1_AMUXA = 4, /* Analog mux bus A */ P13_1_AMUXB = 5, /* Analog mux bus B */ P13_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P13_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P13_1_TCPWM0_LINE44 = 8, /* Digital Active - tcpwm[0].line[44]:0 */ P13_1_TCPWM0_LINE_COMPL264 = 9, /* Digital Active - tcpwm[0].line_compl[264]:0 */ P13_1_TCPWM0_TR_ONE_CNT_IN132 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[132]:0 */ P13_1_TCPWM0_TR_ONE_CNT_IN793 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[793]:0 */ P13_1_PASS0_SAR_EXT_MUX_SEL7 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[7] */ P13_1_SCB3_UART_TX = 17, /* Digital Active - scb[3].uart_tx:0 */ P13_1_SCB3_I2C_SDA = 18, /* Digital Active - scb[3].i2c_sda:0 */ P13_1_SCB3_SPI_MOSI = 19, /* Digital Active - scb[3].spi_mosi:0 */ P13_1_LIN0_LIN_TX3 = 20, /* Digital Active - lin[0].lin_tx[3]:1 */ P13_1_CXPI0_CXPI_TX1 = 22, /* Digital Active - cxpi[0].cxpi_tx[1]:0 */ /* P13.2 */ P13_2_GPIO = 0, /* GPIO controls 'out' */ P13_2_AMUXA = 4, /* Analog mux bus A */ P13_2_AMUXB = 5, /* Analog mux bus B */ P13_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P13_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P13_2_TCPWM0_LINE265 = 8, /* Digital Active - tcpwm[0].line[265]:0 */ P13_2_TCPWM0_LINE_COMPL44 = 9, /* Digital Active - tcpwm[0].line_compl[44]:0 */ P13_2_TCPWM0_TR_ONE_CNT_IN795 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[795]:0 */ P13_2_TCPWM0_TR_ONE_CNT_IN133 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[133]:0 */ P13_2_PASS0_SAR_EXT_MUX_SEL8 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[8] */ P13_2_SCB3_UART_RTS = 17, /* Digital Active - scb[3].uart_rts:0 */ P13_2_SCB3_I2C_SCL = 18, /* Digital Active - scb[3].i2c_scl:0 */ P13_2_SCB3_SPI_CLK = 19, /* Digital Active - scb[3].spi_clk:0 */ P13_2_LIN0_LIN_EN3 = 20, /* Digital Active - lin[0].lin_en[3]:1 */ P13_2_CXPI0_CXPI_EN1 = 22, /* Digital Active - cxpi[0].cxpi_en[1]:0 */ /* P13.3 */ P13_3_GPIO = 0, /* GPIO controls 'out' */ P13_3_AMUXA = 4, /* Analog mux bus A */ P13_3_AMUXB = 5, /* Analog mux bus B */ P13_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P13_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P13_3_TCPWM0_LINE45 = 8, /* Digital Active - tcpwm[0].line[45]:0 */ P13_3_TCPWM0_LINE_COMPL265 = 9, /* Digital Active - tcpwm[0].line_compl[265]:0 */ P13_3_TCPWM0_TR_ONE_CNT_IN135 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[135]:0 */ P13_3_TCPWM0_TR_ONE_CNT_IN796 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[796]:0 */ P13_3_PASS0_SAR_EXT_MUX_EN2 = 16, /* Digital Active - pass[0].sar_ext_mux_en[2] */ P13_3_SCB3_UART_CTS = 17, /* Digital Active - scb[3].uart_cts:0 */ P13_3_SCB3_SPI_SELECT0 = 19, /* Digital Active - scb[3].spi_select0:0 */ /* P13.4 */ P13_4_GPIO = 0, /* GPIO controls 'out' */ P13_4_AMUXA = 4, /* Analog mux bus A */ P13_4_AMUXB = 5, /* Analog mux bus B */ P13_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P13_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P13_4_TCPWM0_LINE266 = 8, /* Digital Active - tcpwm[0].line[266]:0 */ P13_4_TCPWM0_LINE_COMPL45 = 9, /* Digital Active - tcpwm[0].line_compl[45]:0 */ P13_4_TCPWM0_TR_ONE_CNT_IN798 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[798]:0 */ P13_4_TCPWM0_TR_ONE_CNT_IN136 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[136]:0 */ P13_4_TCPWM0_LINE516 = 16, /* Digital Active - tcpwm[0].line[516]:1 */ P13_4_SCB3_SPI_SELECT1 = 19, /* Digital Active - scb[3].spi_select1:0 */ P13_4_LIN0_LIN_RX8 = 20, /* Digital Active - lin[0].lin_rx[8]:0 */ /* P13.5 */ P13_5_GPIO = 0, /* GPIO controls 'out' */ P13_5_AMUXA = 4, /* Analog mux bus A */ P13_5_AMUXB = 5, /* Analog mux bus B */ P13_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P13_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P13_5_TCPWM0_LINE46 = 8, /* Digital Active - tcpwm[0].line[46]:0 */ P13_5_TCPWM0_LINE_COMPL266 = 9, /* Digital Active - tcpwm[0].line_compl[266]:0 */ P13_5_TCPWM0_TR_ONE_CNT_IN138 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[138]:0 */ P13_5_TCPWM0_TR_ONE_CNT_IN799 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[799]:0 */ P13_5_TCPWM0_LINE_COMPL516 = 16, /* Digital Active - tcpwm[0].line_compl[516]:1 */ P13_5_SCB3_SPI_SELECT2 = 19, /* Digital Active - scb[3].spi_select2:0 */ P13_5_LIN0_LIN_TX8 = 20, /* Digital Active - lin[0].lin_tx[8]:0 */ P13_5_CXPI0_CXPI_RX2 = 22, /* Digital Active - cxpi[0].cxpi_rx[2]:0 */ /* P13.6 */ P13_6_GPIO = 0, /* GPIO controls 'out' */ P13_6_AMUXA = 4, /* Analog mux bus A */ P13_6_AMUXB = 5, /* Analog mux bus B */ P13_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P13_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P13_6_TCPWM0_LINE267 = 8, /* Digital Active - tcpwm[0].line[267]:0 */ P13_6_TCPWM0_LINE_COMPL46 = 9, /* Digital Active - tcpwm[0].line_compl[46]:0 */ P13_6_TCPWM0_TR_ONE_CNT_IN801 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[801]:0 */ P13_6_TCPWM0_TR_ONE_CNT_IN139 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[139]:0 */ P13_6_TCPWM0_LINE517 = 16, /* Digital Active - tcpwm[0].line[517]:1 */ P13_6_SCB3_SPI_SELECT3 = 19, /* Digital Active - scb[3].spi_select3:0 */ P13_6_LIN0_LIN_EN8 = 20, /* Digital Active - lin[0].lin_en[8]:0 */ P13_6_CXPI0_CXPI_TX2 = 22, /* Digital Active - cxpi[0].cxpi_tx[2]:0 */ P13_6_PERI_TR_IO_INPUT22 = 26, /* Digital Active - peri.tr_io_input[22]:0 */ /* P13.7 */ P13_7_GPIO = 0, /* GPIO controls 'out' */ P13_7_AMUXA = 4, /* Analog mux bus A */ P13_7_AMUXB = 5, /* Analog mux bus B */ P13_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P13_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P13_7_TCPWM0_LINE47 = 8, /* Digital Active - tcpwm[0].line[47]:0 */ P13_7_TCPWM0_LINE_COMPL267 = 9, /* Digital Active - tcpwm[0].line_compl[267]:0 */ P13_7_TCPWM0_TR_ONE_CNT_IN141 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[141]:0 */ P13_7_TCPWM0_TR_ONE_CNT_IN802 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[802]:0 */ P13_7_TCPWM0_LINE_COMPL517 = 16, /* Digital Active - tcpwm[0].line_compl[517]:1 */ P13_7_CXPI0_CXPI_EN2 = 22, /* Digital Active - cxpi[0].cxpi_en[2]:0 */ P13_7_PERI_TR_IO_INPUT23 = 26, /* Digital Active - peri.tr_io_input[23]:0 */ /* P14.0 */ P14_0_GPIO = 0, /* GPIO controls 'out' */ P14_0_AMUXA = 4, /* Analog mux bus A */ P14_0_AMUXB = 5, /* Analog mux bus B */ P14_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P14_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P14_0_TCPWM0_LINE48 = 8, /* Digital Active - tcpwm[0].line[48]:0 */ P14_0_TCPWM0_LINE_COMPL47 = 9, /* Digital Active - tcpwm[0].line_compl[47]:0 */ P14_0_TCPWM0_TR_ONE_CNT_IN144 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[144]:0 */ P14_0_TCPWM0_TR_ONE_CNT_IN142 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[142]:0 */ P14_0_TCPWM0_LINE518 = 16, /* Digital Active - tcpwm[0].line[518]:1 */ P14_0_SCB2_UART_RX = 17, /* Digital Active - scb[2].uart_rx:0 */ P14_0_SCB2_SPI_MISO = 19, /* Digital Active - scb[2].spi_miso:0 */ P14_0_CANFD1_TTCAN_TX0 = 21, /* Digital Active - canfd[1].ttcan_tx[0]:0 */ /* P14.1 */ P14_1_GPIO = 0, /* GPIO controls 'out' */ P14_1_AMUXA = 4, /* Analog mux bus A */ P14_1_AMUXB = 5, /* Analog mux bus B */ P14_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P14_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P14_1_TCPWM0_LINE49 = 8, /* Digital Active - tcpwm[0].line[49]:0 */ P14_1_TCPWM0_LINE_COMPL48 = 9, /* Digital Active - tcpwm[0].line_compl[48]:0 */ P14_1_TCPWM0_TR_ONE_CNT_IN147 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[147]:0 */ P14_1_TCPWM0_TR_ONE_CNT_IN145 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[145]:0 */ P14_1_TCPWM0_LINE_COMPL518 = 16, /* Digital Active - tcpwm[0].line_compl[518]:1 */ P14_1_SCB2_UART_TX = 17, /* Digital Active - scb[2].uart_tx:0 */ P14_1_SCB2_I2C_SDA = 18, /* Digital Active - scb[2].i2c_sda:0 */ P14_1_SCB2_SPI_MOSI = 19, /* Digital Active - scb[2].spi_mosi:0 */ P14_1_CANFD1_TTCAN_RX0 = 21, /* Digital Active - canfd[1].ttcan_rx[0]:0 */ /* P14.2 */ P14_2_GPIO = 0, /* GPIO controls 'out' */ P14_2_AMUXA = 4, /* Analog mux bus A */ P14_2_AMUXB = 5, /* Analog mux bus B */ P14_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P14_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P14_2_TCPWM0_LINE50 = 8, /* Digital Active - tcpwm[0].line[50]:0 */ P14_2_TCPWM0_LINE_COMPL49 = 9, /* Digital Active - tcpwm[0].line_compl[49]:0 */ P14_2_TCPWM0_TR_ONE_CNT_IN150 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[150]:0 */ P14_2_TCPWM0_TR_ONE_CNT_IN148 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[148]:0 */ P14_2_TCPWM0_LINE519 = 16, /* Digital Active - tcpwm[0].line[519]:1 */ P14_2_SCB2_UART_RTS = 17, /* Digital Active - scb[2].uart_rts:0 */ P14_2_SCB2_I2C_SCL = 18, /* Digital Active - scb[2].i2c_scl:0 */ P14_2_SCB2_SPI_CLK = 19, /* Digital Active - scb[2].spi_clk:0 */ P14_2_LIN0_LIN_RX6 = 20, /* Digital Active - lin[0].lin_rx[6]:1 */ /* P14.3 */ P14_3_GPIO = 0, /* GPIO controls 'out' */ P14_3_AMUXA = 4, /* Analog mux bus A */ P14_3_AMUXB = 5, /* Analog mux bus B */ P14_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P14_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P14_3_TCPWM0_LINE51 = 8, /* Digital Active - tcpwm[0].line[51]:0 */ P14_3_TCPWM0_LINE_COMPL50 = 9, /* Digital Active - tcpwm[0].line_compl[50]:0 */ P14_3_TCPWM0_TR_ONE_CNT_IN153 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[153]:0 */ P14_3_TCPWM0_TR_ONE_CNT_IN151 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[151]:0 */ P14_3_TCPWM0_LINE_COMPL519 = 16, /* Digital Active - tcpwm[0].line_compl[519]:1 */ P14_3_SCB2_UART_CTS = 17, /* Digital Active - scb[2].uart_cts:0 */ P14_3_SCB2_SPI_SELECT0 = 19, /* Digital Active - scb[2].spi_select0:0 */ P14_3_LIN0_LIN_TX6 = 20, /* Digital Active - lin[0].lin_tx[6]:1 */ /* P17.0 */ P17_0_GPIO = 0, /* GPIO controls 'out' */ P17_0_AMUXA = 4, /* Analog mux bus A */ P17_0_AMUXB = 5, /* Analog mux bus B */ P17_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P17_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P17_0_TCPWM0_LINE61 = 8, /* Digital Active - tcpwm[0].line[61]:1 */ P17_0_TCPWM0_LINE_COMPL62 = 9, /* Digital Active - tcpwm[0].line_compl[62]:1 */ P17_0_TCPWM0_TR_ONE_CNT_IN183 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[183]:1 */ P17_0_TCPWM0_TR_ONE_CNT_IN187 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[187]:1 */ P17_0_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:0 */ /* P17.1 */ P17_1_GPIO = 0, /* GPIO controls 'out' */ P17_1_AMUXA = 4, /* Analog mux bus A */ P17_1_AMUXB = 5, /* Analog mux bus B */ P17_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P17_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P17_1_TCPWM0_LINE60 = 8, /* Digital Active - tcpwm[0].line[60]:1 */ P17_1_TCPWM0_LINE_COMPL61 = 9, /* Digital Active - tcpwm[0].line_compl[61]:1 */ P17_1_TCPWM0_TR_ONE_CNT_IN180 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[180]:1 */ P17_1_TCPWM0_TR_ONE_CNT_IN184 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[184]:1 */ P17_1_TCPWM0_LINE514 = 16, /* Digital Active - tcpwm[0].line[514]:1 */ P17_1_SCB3_UART_RX = 17, /* Digital Active - scb[3].uart_rx:1 */ P17_1_SCB3_SPI_MISO = 19, /* Digital Active - scb[3].spi_miso:1 */ P17_1_CANFD1_TTCAN_RX1 = 21, /* Digital Active - canfd[1].ttcan_rx[1]:0 */ /* P17.2 */ P17_2_GPIO = 0, /* GPIO controls 'out' */ P17_2_AMUXA = 4, /* Analog mux bus A */ P17_2_AMUXB = 5, /* Analog mux bus B */ P17_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P17_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P17_2_TCPWM0_LINE59 = 8, /* Digital Active - tcpwm[0].line[59]:1 */ P17_2_TCPWM0_LINE_COMPL60 = 9, /* Digital Active - tcpwm[0].line_compl[60]:1 */ P17_2_TCPWM0_TR_ONE_CNT_IN177 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[177]:1 */ P17_2_TCPWM0_TR_ONE_CNT_IN181 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[181]:1 */ P17_2_TCPWM0_LINE_COMPL514 = 16, /* Digital Active - tcpwm[0].line_compl[514]:1 */ P17_2_SCB3_UART_TX = 17, /* Digital Active - scb[3].uart_tx:1 */ P17_2_SCB3_I2C_SDA = 18, /* Digital Active - scb[3].i2c_sda:1 */ P17_2_SCB3_SPI_MOSI = 19, /* Digital Active - scb[3].spi_mosi:1 */ /* P18.0 */ P18_0_GPIO = 0, /* GPIO controls 'out' */ P18_0_AMUXA = 4, /* Analog mux bus A */ P18_0_AMUXB = 5, /* Analog mux bus B */ P18_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P18_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P18_0_TCPWM0_LINE262 = 8, /* Digital Active - tcpwm[0].line[262]:1 */ P18_0_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:1 */ P18_0_TCPWM0_TR_ONE_CNT_IN786 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[786]:1 */ P18_0_TCPWM0_TR_ONE_CNT_IN784 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[784]:1 */ P18_0_TCPWM0_LINE512 = 16, /* Digital Active - tcpwm[0].line[512]:0 */ P18_0_SCB1_UART_RX = 17, /* Digital Active - scb[1].uart_rx:0 */ P18_0_SCB1_SPI_MISO = 19, /* Digital Active - scb[1].spi_miso:0 */ P18_0_CPUSS_FAULT_OUT0 = 27, /* Digital Active - cpuss.fault_out[0]:0 */ /* P18.1 */ P18_1_GPIO = 0, /* GPIO controls 'out' */ P18_1_AMUXA = 4, /* Analog mux bus A */ P18_1_AMUXB = 5, /* Analog mux bus B */ P18_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P18_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P18_1_TCPWM0_LINE263 = 8, /* Digital Active - tcpwm[0].line[263]:1 */ P18_1_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:1 */ P18_1_TCPWM0_TR_ONE_CNT_IN789 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[789]:1 */ P18_1_TCPWM0_TR_ONE_CNT_IN787 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[787]:1 */ P18_1_TCPWM0_LINE_COMPL512 = 16, /* Digital Active - tcpwm[0].line_compl[512]:0 */ P18_1_SCB1_UART_TX = 17, /* Digital Active - scb[1].uart_tx:0 */ P18_1_SCB1_I2C_SDA = 18, /* Digital Active - scb[1].i2c_sda:0 */ P18_1_SCB1_SPI_MOSI = 19, /* Digital Active - scb[1].spi_mosi:0 */ P18_1_CPUSS_FAULT_OUT1 = 27, /* Digital Active - cpuss.fault_out[1]:0 */ /* P18.2 */ P18_2_GPIO = 0, /* GPIO controls 'out' */ P18_2_AMUXA = 4, /* Analog mux bus A */ P18_2_AMUXB = 5, /* Analog mux bus B */ P18_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P18_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P18_2_TCPWM0_LINE55 = 8, /* Digital Active - tcpwm[0].line[55]:1 */ P18_2_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:1 */ P18_2_TCPWM0_TR_ONE_CNT_IN165 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[165]:1 */ P18_2_TCPWM0_TR_ONE_CNT_IN790 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[790]:1 */ P18_2_TCPWM0_LINE513 = 16, /* Digital Active - tcpwm[0].line[513]:0 */ P18_2_SCB1_UART_RTS = 17, /* Digital Active - scb[1].uart_rts:0 */ P18_2_SCB1_I2C_SCL = 18, /* Digital Active - scb[1].i2c_scl:0 */ P18_2_SCB1_SPI_CLK = 19, /* Digital Active - scb[1].spi_clk:0 */ /* P18.3 */ P18_3_GPIO = 0, /* GPIO controls 'out' */ P18_3_AMUXA = 4, /* Analog mux bus A */ P18_3_AMUXB = 5, /* Analog mux bus B */ P18_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P18_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P18_3_TCPWM0_LINE54 = 8, /* Digital Active - tcpwm[0].line[54]:1 */ P18_3_TCPWM0_LINE_COMPL55 = 9, /* Digital Active - tcpwm[0].line_compl[55]:1 */ P18_3_TCPWM0_TR_ONE_CNT_IN162 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[162]:1 */ P18_3_TCPWM0_TR_ONE_CNT_IN166 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[166]:1 */ P18_3_TCPWM0_LINE_COMPL513 = 16, /* Digital Active - tcpwm[0].line_compl[513]:0 */ P18_3_SCB1_UART_CTS = 17, /* Digital Active - scb[1].uart_cts:0 */ P18_3_SCB1_SPI_SELECT0 = 19, /* Digital Active - scb[1].spi_select0:0 */ P18_3_CPUSS_TRACE_CLOCK = 27, /* Digital Active - cpuss.trace_clock:0 */ /* P18.4 */ P18_4_GPIO = 0, /* GPIO controls 'out' */ P18_4_AMUXA = 4, /* Analog mux bus A */ P18_4_AMUXB = 5, /* Analog mux bus B */ P18_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P18_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P18_4_TCPWM0_LINE53 = 8, /* Digital Active - tcpwm[0].line[53]:1 */ P18_4_TCPWM0_LINE_COMPL54 = 9, /* Digital Active - tcpwm[0].line_compl[54]:1 */ P18_4_TCPWM0_TR_ONE_CNT_IN159 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[159]:1 */ P18_4_TCPWM0_TR_ONE_CNT_IN163 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[163]:1 */ P18_4_TCPWM0_LINE514 = 16, /* Digital Active - tcpwm[0].line[514]:0 */ P18_4_SCB1_SPI_SELECT1 = 19, /* Digital Active - scb[1].spi_select1:0 */ P18_4_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ /* P18.5 */ P18_5_GPIO = 0, /* GPIO controls 'out' */ P18_5_AMUXA = 4, /* Analog mux bus A */ P18_5_AMUXB = 5, /* Analog mux bus B */ P18_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P18_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P18_5_TCPWM0_LINE52 = 8, /* Digital Active - tcpwm[0].line[52]:1 */ P18_5_TCPWM0_LINE_COMPL53 = 9, /* Digital Active - tcpwm[0].line_compl[53]:1 */ P18_5_TCPWM0_TR_ONE_CNT_IN156 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[156]:1 */ P18_5_TCPWM0_TR_ONE_CNT_IN160 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[160]:1 */ P18_5_TCPWM0_LINE_COMPL514 = 16, /* Digital Active - tcpwm[0].line_compl[514]:0 */ P18_5_SCB1_SPI_SELECT2 = 19, /* Digital Active - scb[1].spi_select2:0 */ P18_5_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ /* P18.6 */ P18_6_GPIO = 0, /* GPIO controls 'out' */ P18_6_AMUXA = 4, /* Analog mux bus A */ P18_6_AMUXB = 5, /* Analog mux bus B */ P18_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P18_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P18_6_TCPWM0_LINE51 = 8, /* Digital Active - tcpwm[0].line[51]:1 */ P18_6_TCPWM0_LINE_COMPL52 = 9, /* Digital Active - tcpwm[0].line_compl[52]:1 */ P18_6_TCPWM0_TR_ONE_CNT_IN153 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[153]:1 */ P18_6_TCPWM0_TR_ONE_CNT_IN157 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[157]:1 */ P18_6_TCPWM0_LINE515 = 16, /* Digital Active - tcpwm[0].line[515]:0 */ P18_6_SCB1_SPI_SELECT3 = 19, /* Digital Active - scb[1].spi_select3:0 */ P18_6_CANFD1_TTCAN_TX2 = 21, /* Digital Active - canfd[1].ttcan_tx[2]:0 */ P18_6_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ /* P18.7 */ P18_7_GPIO = 0, /* GPIO controls 'out' */ P18_7_AMUXA = 4, /* Analog mux bus A */ P18_7_AMUXB = 5, /* Analog mux bus B */ P18_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P18_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P18_7_TCPWM0_LINE50 = 8, /* Digital Active - tcpwm[0].line[50]:1 */ P18_7_TCPWM0_LINE_COMPL51 = 9, /* Digital Active - tcpwm[0].line_compl[51]:1 */ P18_7_TCPWM0_TR_ONE_CNT_IN150 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[150]:1 */ P18_7_TCPWM0_TR_ONE_CNT_IN154 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[154]:1 */ P18_7_TCPWM0_LINE_COMPL515 = 16, /* Digital Active - tcpwm[0].line_compl[515]:0 */ P18_7_CANFD1_TTCAN_RX2 = 21, /* Digital Active - canfd[1].ttcan_rx[2]:0 */ P18_7_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ /* P19.0 */ P19_0_GPIO = 0, /* GPIO controls 'out' */ P19_0_AMUXA = 4, /* Analog mux bus A */ P19_0_AMUXB = 5, /* Analog mux bus B */ P19_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P19_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P19_0_TCPWM0_LINE259 = 8, /* Digital Active - tcpwm[0].line[259]:2 */ P19_0_TCPWM0_LINE_COMPL50 = 9, /* Digital Active - tcpwm[0].line_compl[50]:1 */ P19_0_TCPWM0_TR_ONE_CNT_IN777 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[777]:2 */ P19_0_TCPWM0_TR_ONE_CNT_IN151 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[151]:1 */ P19_0_TCPWM0_TR_ONE_CNT_IN1536 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1536]:0 */ P19_0_SCB2_UART_RX = 17, /* Digital Active - scb[2].uart_rx:1 */ P19_0_SCB2_SPI_MISO = 19, /* Digital Active - scb[2].spi_miso:1 */ P19_0_CANFD1_TTCAN_TX3 = 21, /* Digital Active - canfd[1].ttcan_tx[3]:0 */ P19_0_CPUSS_FAULT_OUT2 = 27, /* Digital Active - cpuss.fault_out[2]:0 */ /* P19.1 */ P19_1_GPIO = 0, /* GPIO controls 'out' */ P19_1_AMUXA = 4, /* Analog mux bus A */ P19_1_AMUXB = 5, /* Analog mux bus B */ P19_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P19_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P19_1_TCPWM0_LINE26 = 8, /* Digital Active - tcpwm[0].line[26]:1 */ P19_1_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:2 */ P19_1_TCPWM0_TR_ONE_CNT_IN78 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[78]:1 */ P19_1_TCPWM0_TR_ONE_CNT_IN778 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[778]:2 */ P19_1_TCPWM0_TR_ONE_CNT_IN1537 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1537]:0 */ P19_1_SCB2_UART_TX = 17, /* Digital Active - scb[2].uart_tx:1 */ P19_1_SCB2_I2C_SDA = 18, /* Digital Active - scb[2].i2c_sda:1 */ P19_1_SCB2_SPI_MOSI = 19, /* Digital Active - scb[2].spi_mosi:1 */ P19_1_CANFD1_TTCAN_RX3 = 21, /* Digital Active - canfd[1].ttcan_rx[3]:0 */ P19_1_CXPI0_CXPI_RX3 = 22, /* Digital Active - cxpi[0].cxpi_rx[3]:0 */ P19_1_CPUSS_FAULT_OUT3 = 27, /* Digital Active - cpuss.fault_out[3]:0 */ /* P19.2 */ P19_2_GPIO = 0, /* GPIO controls 'out' */ P19_2_AMUXA = 4, /* Analog mux bus A */ P19_2_AMUXB = 5, /* Analog mux bus B */ P19_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P19_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P19_2_TCPWM0_LINE27 = 8, /* Digital Active - tcpwm[0].line[27]:2 */ P19_2_TCPWM0_LINE_COMPL26 = 9, /* Digital Active - tcpwm[0].line_compl[26]:1 */ P19_2_TCPWM0_TR_ONE_CNT_IN81 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[81]:2 */ P19_2_TCPWM0_TR_ONE_CNT_IN79 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[79]:1 */ P19_2_TCPWM0_TR_ONE_CNT_IN1539 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1539]:0 */ P19_2_SCB2_UART_RTS = 17, /* Digital Active - scb[2].uart_rts:1 */ P19_2_SCB2_I2C_SCL = 18, /* Digital Active - scb[2].i2c_scl:1 */ P19_2_SCB2_SPI_CLK = 19, /* Digital Active - scb[2].spi_clk:1 */ P19_2_CXPI0_CXPI_TX3 = 22, /* Digital Active - cxpi[0].cxpi_tx[3]:0 */ P19_2_PERI_TR_IO_INPUT28 = 26, /* Digital Active - peri.tr_io_input[28]:0 */ /* P19.3 */ P19_3_GPIO = 0, /* GPIO controls 'out' */ P19_3_AMUXA = 4, /* Analog mux bus A */ P19_3_AMUXB = 5, /* Analog mux bus B */ P19_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P19_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P19_3_TCPWM0_LINE28 = 8, /* Digital Active - tcpwm[0].line[28]:2 */ P19_3_TCPWM0_LINE_COMPL27 = 9, /* Digital Active - tcpwm[0].line_compl[27]:2 */ P19_3_TCPWM0_TR_ONE_CNT_IN84 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[84]:2 */ P19_3_TCPWM0_TR_ONE_CNT_IN82 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[82]:2 */ P19_3_TCPWM0_TR_ONE_CNT_IN1540 = 16, /* Digital Active - tcpwm[0].tr_one_cnt_in[1540]:0 */ P19_3_SCB2_UART_CTS = 17, /* Digital Active - scb[2].uart_cts:1 */ P19_3_SCB2_SPI_SELECT0 = 19, /* Digital Active - scb[2].spi_select0:1 */ P19_3_CXPI0_CXPI_EN3 = 22, /* Digital Active - cxpi[0].cxpi_en[3]:0 */ P19_3_PERI_TR_IO_INPUT29 = 26, /* Digital Active - peri.tr_io_input[29]:0 */ /* P21.0 */ P21_0_GPIO = 0, /* GPIO controls 'out' */ P21_0_AMUXA = 4, /* Analog mux bus A */ P21_0_AMUXB = 5, /* Analog mux bus B */ P21_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P21_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P21_0_TCPWM0_LINE42 = 8, /* Digital Active - tcpwm[0].line[42]:1 */ P21_0_TCPWM0_LINE_COMPL43 = 9, /* Digital Active - tcpwm[0].line_compl[43]:1 */ P21_0_TCPWM0_TR_ONE_CNT_IN126 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[126]:1 */ P21_0_TCPWM0_TR_ONE_CNT_IN130 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[130]:1 */ P21_0_SCB1_SPI_SELECT2 = 19, /* Digital Active - scb[1].spi_select2:1 */ /* P21.1 */ P21_1_GPIO = 0, /* GPIO controls 'out' */ P21_1_AMUXA = 4, /* Analog mux bus A */ P21_1_AMUXB = 5, /* Analog mux bus B */ P21_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P21_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P21_1_TCPWM0_LINE41 = 8, /* Digital Active - tcpwm[0].line[41]:1 */ P21_1_TCPWM0_LINE_COMPL42 = 9, /* Digital Active - tcpwm[0].line_compl[42]:1 */ P21_1_TCPWM0_TR_ONE_CNT_IN123 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[123]:1 */ P21_1_TCPWM0_TR_ONE_CNT_IN127 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[127]:1 */ /* P21.2 */ P21_2_GPIO = 0, /* GPIO controls 'out' */ P21_2_AMUXA = 4, /* Analog mux bus A */ P21_2_AMUXB = 5, /* Analog mux bus B */ P21_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P21_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P21_2_TCPWM0_LINE40 = 8, /* Digital Active - tcpwm[0].line[40]:1 */ P21_2_TCPWM0_LINE_COMPL41 = 9, /* Digital Active - tcpwm[0].line_compl[41]:1 */ P21_2_TCPWM0_TR_ONE_CNT_IN120 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[120]:1 */ P21_2_TCPWM0_TR_ONE_CNT_IN124 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[124]:1 */ P21_2_SRSS_EXT_CLK = 26, /* Digital Active - srss.ext_clk:0 */ P21_2_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:2 */ P21_2_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ /* P21.3 */ P21_3_GPIO = 0, /* GPIO controls 'out' */ P21_3_AMUXA = 4, /* Analog mux bus A */ P21_3_AMUXB = 5, /* Analog mux bus B */ P21_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P21_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P21_3_TCPWM0_LINE39 = 8, /* Digital Active - tcpwm[0].line[39]:1 */ P21_3_TCPWM0_LINE_COMPL40 = 9, /* Digital Active - tcpwm[0].line_compl[40]:1 */ P21_3_TCPWM0_TR_ONE_CNT_IN117 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[117]:1 */ P21_3_TCPWM0_TR_ONE_CNT_IN121 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[121]:1 */ /* P21.5 */ P21_5_GPIO = 0, /* GPIO controls 'out' */ P21_5_AMUXA = 4, /* Analog mux bus A */ P21_5_AMUXB = 5, /* Analog mux bus B */ P21_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P21_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P21_5_TCPWM0_LINE37 = 8, /* Digital Active - tcpwm[0].line[37]:1 */ P21_5_TCPWM0_LINE_COMPL38 = 9, /* Digital Active - tcpwm[0].line_compl[38]:1 */ P21_5_TCPWM0_TR_ONE_CNT_IN111 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[111]:1 */ P21_5_TCPWM0_TR_ONE_CNT_IN115 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[115]:1 */ P21_5_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:1 */ /* P22.0 */ P22_0_GPIO = 0, /* GPIO controls 'out' */ P22_0_AMUXA = 4, /* Analog mux bus A */ P22_0_AMUXB = 5, /* Analog mux bus B */ P22_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P22_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P22_0_TCPWM0_LINE34 = 8, /* Digital Active - tcpwm[0].line[34]:1 */ P22_0_TCPWM0_LINE_COMPL35 = 9, /* Digital Active - tcpwm[0].line_compl[35]:1 */ P22_0_TCPWM0_TR_ONE_CNT_IN102 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[102]:1 */ P22_0_TCPWM0_TR_ONE_CNT_IN106 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[106]:1 */ P22_0_SCB6_UART_RX = 17, /* Digital Active - scb[6].uart_rx:1 */ P22_0_SCB6_SPI_MISO = 19, /* Digital Active - scb[6].spi_miso:1 */ P22_0_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:1 */ P22_0_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ /* P22.1 */ P22_1_GPIO = 0, /* GPIO controls 'out' */ P22_1_AMUXA = 4, /* Analog mux bus A */ P22_1_AMUXB = 5, /* Analog mux bus B */ P22_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P22_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P22_1_TCPWM0_LINE33 = 8, /* Digital Active - tcpwm[0].line[33]:1 */ P22_1_TCPWM0_LINE_COMPL34 = 9, /* Digital Active - tcpwm[0].line_compl[34]:1 */ P22_1_TCPWM0_TR_ONE_CNT_IN99 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[99]:1 */ P22_1_TCPWM0_TR_ONE_CNT_IN103 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[103]:1 */ P22_1_SCB6_UART_TX = 17, /* Digital Active - scb[6].uart_tx:1 */ P22_1_SCB6_I2C_SDA = 18, /* Digital Active - scb[6].i2c_sda:1 */ P22_1_SCB6_SPI_MOSI = 19, /* Digital Active - scb[6].spi_mosi:1 */ P22_1_CANFD1_TTCAN_RX1 = 21, /* Digital Active - canfd[1].ttcan_rx[1]:1 */ P22_1_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ /* P22.2 */ P22_2_GPIO = 0, /* GPIO controls 'out' */ P22_2_AMUXA = 4, /* Analog mux bus A */ P22_2_AMUXB = 5, /* Analog mux bus B */ P22_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P22_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P22_2_TCPWM0_LINE32 = 8, /* Digital Active - tcpwm[0].line[32]:1 */ P22_2_TCPWM0_LINE_COMPL33 = 9, /* Digital Active - tcpwm[0].line_compl[33]:1 */ P22_2_TCPWM0_TR_ONE_CNT_IN96 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[96]:1 */ P22_2_TCPWM0_TR_ONE_CNT_IN100 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[100]:1 */ P22_2_SCB6_UART_RTS = 17, /* Digital Active - scb[6].uart_rts:1 */ P22_2_SCB6_I2C_SCL = 18, /* Digital Active - scb[6].i2c_scl:1 */ P22_2_SCB6_SPI_CLK = 19, /* Digital Active - scb[6].spi_clk:1 */ P22_2_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ /* P22.3 */ P22_3_GPIO = 0, /* GPIO controls 'out' */ P22_3_AMUXA = 4, /* Analog mux bus A */ P22_3_AMUXB = 5, /* Analog mux bus B */ P22_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P22_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P22_3_TCPWM0_LINE31 = 8, /* Digital Active - tcpwm[0].line[31]:1 */ P22_3_TCPWM0_LINE_COMPL32 = 9, /* Digital Active - tcpwm[0].line_compl[32]:1 */ P22_3_TCPWM0_TR_ONE_CNT_IN93 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[93]:1 */ P22_3_TCPWM0_TR_ONE_CNT_IN97 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[97]:1 */ P22_3_SCB6_UART_CTS = 17, /* Digital Active - scb[6].uart_cts:1 */ P22_3_SCB6_SPI_SELECT0 = 19, /* Digital Active - scb[6].spi_select0:1 */ P22_3_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ /* P23.3 */ P23_3_GPIO = 0, /* GPIO controls 'out' */ P23_3_AMUXA = 4, /* Analog mux bus A */ P23_3_AMUXB = 5, /* Analog mux bus B */ P23_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P23_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P23_3_TCPWM0_LINE267 = 8, /* Digital Active - tcpwm[0].line[267]:1 */ P23_3_TCPWM0_LINE_COMPL266 = 9, /* Digital Active - tcpwm[0].line_compl[266]:1 */ P23_3_TCPWM0_TR_ONE_CNT_IN801 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[801]:1 */ P23_3_TCPWM0_TR_ONE_CNT_IN799 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[799]:1 */ P23_3_SCB7_UART_CTS = 17, /* Digital Active - scb[7].uart_cts:1 */ P23_3_SCB7_SPI_SELECT0 = 19, /* Digital Active - scb[7].spi_select0:1 */ P23_3_PERI_TR_IO_INPUT30 = 26, /* Digital Active - peri.tr_io_input[30]:0 */ P23_3_CPUSS_FAULT_OUT3 = 27, /* Digital Active - cpuss.fault_out[3]:1 */ P23_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ /* P23.4 */ P23_4_GPIO = 0, /* GPIO controls 'out' */ P23_4_AMUXA = 4, /* Analog mux bus A */ P23_4_AMUXB = 5, /* Analog mux bus B */ P23_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P23_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P23_4_TCPWM0_LINE25 = 8, /* Digital Active - tcpwm[0].line[25]:1 */ P23_4_TCPWM0_LINE_COMPL267 = 9, /* Digital Active - tcpwm[0].line_compl[267]:1 */ P23_4_TCPWM0_TR_ONE_CNT_IN75 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[75]:1 */ P23_4_TCPWM0_TR_ONE_CNT_IN802 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[802]:1 */ P23_4_SCB7_SPI_SELECT1 = 19, /* Digital Active - scb[7].spi_select1:1 */ P23_4_PERI_TR_IO_INPUT31 = 26, /* Digital Active - peri.tr_io_input[31]:0 */ P23_4_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:2 */ P23_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo:0 */ P23_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ /* P23.5 */ P23_5_GPIO = 0, /* GPIO controls 'out' */ P23_5_AMUXA = 4, /* Analog mux bus A */ P23_5_AMUXB = 5, /* Analog mux bus B */ P23_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P23_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P23_5_TCPWM0_LINE24 = 8, /* Digital Active - tcpwm[0].line[24]:1 */ P23_5_TCPWM0_LINE_COMPL25 = 9, /* Digital Active - tcpwm[0].line_compl[25]:1 */ P23_5_TCPWM0_TR_ONE_CNT_IN72 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[72]:1 */ P23_5_TCPWM0_TR_ONE_CNT_IN76 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[76]:1 */ P23_5_SCB7_SPI_SELECT2 = 19, /* Digital Active - scb[7].spi_select2:1 */ P23_5_LIN0_LIN_RX9 = 20, /* Digital Active - lin[0].lin_rx[9]:0 */ P23_5_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ /* P23.6 */ P23_6_GPIO = 0, /* GPIO controls 'out' */ P23_6_AMUXA = 4, /* Analog mux bus A */ P23_6_AMUXB = 5, /* Analog mux bus B */ P23_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P23_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P23_6_TCPWM0_LINE23 = 8, /* Digital Active - tcpwm[0].line[23]:1 */ P23_6_TCPWM0_LINE_COMPL24 = 9, /* Digital Active - tcpwm[0].line_compl[24]:1 */ P23_6_TCPWM0_TR_ONE_CNT_IN69 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[69]:1 */ P23_6_TCPWM0_TR_ONE_CNT_IN73 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[73]:1 */ P23_6_LIN0_LIN_TX9 = 20, /* Digital Active - lin[0].lin_tx[9]:0 */ P23_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms:0 */ /* P23.7 */ P23_7_GPIO = 0, /* GPIO controls 'out' */ P23_7_AMUXA = 4, /* Analog mux bus A */ P23_7_AMUXB = 5, /* Analog mux bus B */ P23_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ P23_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ P23_7_TCPWM0_LINE22 = 8, /* Digital Active - tcpwm[0].line[22]:1 */ P23_7_TCPWM0_LINE_COMPL23 = 9, /* Digital Active - tcpwm[0].line_compl[23]:1 */ P23_7_TCPWM0_TR_ONE_CNT_IN66 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[66]:1 */ P23_7_TCPWM0_TR_ONE_CNT_IN70 = 11, /* Digital Active - tcpwm[0].tr_one_cnt_in[70]:1 */ P23_7_LIN0_LIN_EN9 = 20, /* Digital Active - lin[0].lin_en[9]:0 */ P23_7_SRSS_EXT_CLK = 26, /* Digital Active - srss.ext_clk:1 */ P23_7_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:2 */ P23_7_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi:0 */ P23_7_SRSS_DDFT_PIN_IN0 = 31 /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ } en_hsiom_sel_t; #define P_DUMMY (0x00UL) // Dummy value #define P_LOW (0x00UL) // Output value low #define P_HIGH (0x01UL) // Output value high #define P_DM_ANALOG (0x00UL) // Analog High-Z. Input buffer off #define P_DM_PULLUP_IN_OFF (0x02UL) // Resistive Pull-Up. Input buffer off #define P_DM_PULLDOWN_IN_OFF (0x03UL) // Resistive Pull-Down. Input buffer off #define P_DM_OD_DRIVESLOW_IN_OFF (0x04UL) // Open Drain, Drives Low. Input buffer off #define P_DM_OD_DRIVESHIGH_IN_OFF (0x05UL) // Open Drain, Drives High. Input buffer off #define P_DM_STRONG_IN_OFF (0x06UL) // Strong Drive. Input buffer off #define P_DM_PULLUP_DOWN_IN_OFF (0x07UL) // Resistive Pull-Up/Down. Input buffer off #define P_DM_HIGHZ (0x08UL) // Digital High-Z. Input buffer on #define P_DM_PULLUP (0x0AUL) // Resistive Pull-Up. Input buffer on #define P_DM_PULLDOWN (0x0BUL) // Resistive Pull-Down. Input buffer on #define P_DM_OD_DRIVESLOW (0x0CUL) // Open Drain, Drives Low. Input buffer on #define P_DM_OD_DRIVESHIGH (0x0DUL) // Open Drain, Drives High. Input buffer on #define P_DM_STRONG (0x0EUL) // Strong Drive. Input buffer on #define P_DM_PULLUP_DOWN (0x0FUL) // Resistive Pull-Up/Down. Input buffer on #define P_SLEW_FAST (0x00UL) // Fast slew rate #define P_SLEW_SLOW (0x01UL) // Slow slew rate #define P_DRIVE_FULL (0x00UL) // Full drive strength: Max drive current #define P_DRIVE_1_2 (0x01UL) // 1/2 drive strength: 1/2 drive current #define P_DRIVE_1_4 (0x02UL) // 1/4 drive strength: 1/4 drive current #define P_DRIVE_1_8 (0x03UL) // 1/8 drive strength: 1/8 drive current #define PORT_GPIO_OUT_MASK (0x01UL) // Single pin mask for OUT register #define PORT_GPIO_IN_MASK (0x01UL) // Single pin mask for IN register #define PORT_GPIO_CFG_DM_MASK (0x0FUL) // Single pin mask for drive mode in CFG register #define PORT_GPIO_HSIOM_MASK (0x1FUL) // HSIOM selection mask #define PORT_GPIO_DRIVE_MODE_OFFSET (2UL) // Offset for Drive mode #define PORT_GPIO_HSIOM_OFFSET (3UL) // Offset for HSIOM #define PORT_GPIO_CFG_OUT_SLOW_MASK (0x01UL) // Single pin mask for slew rate in CFG OUT register #define PORT_GPIO_CFG_OUT_DRIVE_SEL_MASK (0x03UL) // Single pin mask for drive strength in CFG OUT register #define PORT_GPIO_CFG_OUT_DRIVE_OFFSET (16UL) // Offset for drive strength #define PORT_GPIO_PRT_HALF (4UL) // Half-way point of a GPIO port #define PORT_GPIO_ZERO (0UL) // Constant zero /* Gpio configuration structure */ typedef struct { uint32 outVal; // Pin output state uint32 driveMode; // Drive mode en_hsiom_sel_t hsiom; // HSIOM selection uint32 intEdge; // Interrupt Edge type uint32 intMask; // Interrupt enable mask uint32 vtrip; // Input buffer voltage trip type uint32 slewRate; // Output buffer slew rate uint32 driveSel; // Drive strength uint32 vregEn; // SIO pair output buffer mode uint32 ibufMode; // SIO pair input buffer mode uint32 vtripSel; // SIO pair input buffer trip point uint32 vrefSel; // SIO pair reference voltage for input buffer trip point uint32 vohSel; // SIO pair regulated voltage output level } Port_gpioConfigType; /* Pin configuration structure */ typedef struct { Port_gpioConfigType gpioConfig; // Gpio pin configuration uint32 portBaseAddr; // Port base address uint32 portNb; // Port number uint32 pin; // Pin number uint32 hsiomBaseAddr; // HSIOM base address } Port_pinConfigType; #endif //PORT_2020_06_08_H_