//***************************************************************************** // (C) Automotive Lighting Reutlingen GmbH // Tuebinger Strasse 123, 72762 Reutlingen, Germany // // Automotive Lighting Reutlingen GmbH owns all the rights to this work. // This work shall not be copied, reproduced, used, modified, transferred // or its information shall not be disclosed without the prior written // authorization of Automotive Lighting Reutlingen GmbH. //***************************************************************************** //----------------------------------------------------------------------------- /// \file CddMlcInd8308_.c /// /// \brief device driver for the Ind8308 chip /// /// \descr Implementation of Mlc /// /// \author Bodian Bianca ALRO-CJ (F40898C) /// mailTo:bianca-dorina.bodian[at]magnetimarelli.com /// //----------------------------------------------------------------------------- //============================================================================= // includes //============================================================================= #include "CddMlcInd8308Uart.h" #include #include "CddMlcInd8308.h" //#include //#include #include #if (CDDMLCInd8308_MEASURE_CYCLE_TIME == CDD_LMM_FEATURE_ON) #include #endif //#include "Rte_ctadCddMlc.h" //============================================================================= // local defines //============================================================================= // Number of commands: Number of chips x WrWidth, 1 x Broadcast, 1 x WrPhase, 1 x RdADC, 1 x RdFAULT, 1 x WrFAULT STATIC_AL uint8 CddMlcGen3Dev; #define CDDMLCInd8308_OFFSETADDR 32U #define CDDMLCInd8308_CMD_IDX_READ_CNFG (CddMlc8308_ConnectedDevices) #define CDDMLCInd8308_CMD_IDX_READ_ADCS (CDDMLCInd8308_CMD_IDX_READ_CNFG + 1U) #define CDDMLCInd8308_CMD_IDX_READ_FLTS (CDDMLCInd8308_CMD_IDX_READ_ADCS + 1U) //#define CDDMLCInd8308_COMMANDS (CDDMLCInd8308_CMD_IDX_READ_FLTS + 1U) #define CDDMLCInd8308_COMMANDS (CFG_MAX_NO_OF_MLC + 3U) //polynomial used for CRC calculation #define CDDMLCInd8308_CRC_POLY 0xA001u //Init value for FAULT register #define CDDMLCInd8308_FAULT_STATUS_INIT 0x0000u //Init value for ADCs #define CDDMLCInd8308_ADC_INIT_VALUE 0x00u //Init value for CRC register #define CDDMLCInd8308_COM_CRC_FLT_INIT 0x00u //Init value for timout counter #define CDDMLCInd8308_COM_TIMEOUT_INIT 0x00u //Init value for Matrix ICID #define CDDMLCInd8308_MATRIX_ICID_INIT 0x00u //Length of ADCID Addressing broadcast write command - not applicable for 664 family #define CDDMLCInd8308_N_TX_ADCID (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_01_BYTE + CDD_LMM_N_CRC_BYTES) //Length of SYSCFG/CMWTAP/PWMTICK broadcast command #define CDDMLCInd8308_N_TX_DEF_CFG (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_03_BYTES + CDD_LMM_N_CRC_BYTES) // If PWM Synchronization Type is exclusive Sofware - Broadcast SSYNC Command #if (CDDMLCInd8308_SYNC_TYPE == CDDMLCInd8308_SYNC_SW_BROADCAST_CMD) //Length of SOFTSYNC->SSYNC broadcast command //Length of SOFTSYNC->SSYNC broadcast command + add the PWR set in this command ( reason: it's the next register) #define CDDMLCInd8308_N_TX_SSYNC (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_02_BYTES + CDD_LMM_N_CRC_BYTES) #else #define CDDMLCInd8308_N_TX_SSYNC 0u #endif //step 1) Configure basic communication broadcast command #define CDDMLCInd8308_N_TX_CFG_COM (/*CDDMLCInd8308_N_TX_DEF_CFG +*/ CDDMLCInd8308_N_TX_SSYNC) #define CDDMLCInd8308_N_RX_CFG_COM (CDDMLCInd8308_N_TX_CFG_COM + CDDMLCInd8308_N_ACK) #define CDD_LMM_N_TX_resRev (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_CRC_BYTES) //#define CDD_LMM_N_RX_resRev (CDD_LMM_N_TX_resRev + CDD_LMM_N_04_BYTES + CDD_LMM_N_CRC_BYTES) //Write Command #define CDD_LMM_N_TX_break CDD_LMM_N_01_BYTE #define CDD_LMM_N_TX_EnablePWMs (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_02_BYTES + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_TX_DisableWDT (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_01_BYTE + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_TX_WDTimeout (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_02_BYTES + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_TX_ExitLimpHome (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_04_BYTES + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_TX_ConfigDefwidth1 (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_04_BYTES + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_TX_ConfigDefwidth2 (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_02_BYTES + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_TX_AddressModeConfig (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_04_BYTES + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_TX_SAR (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_12_BYTES + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_TX_ADC_Address (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_12_BYTES + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_TX_StartADC2A0 (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_02_BYTES + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_TX_StartADCconvert (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_01_BYTE + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_TX_SetPWMs (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_25_BYTES + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_TX_IO_Config (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_01_BYTE + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_TX_SlewRate (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_01_BYTE + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_TX_CfgACK (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_01_BYTE + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_TX_ConfigPWMs (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_01_BYTE + CDD_LMM_N_CRC_BYTES) //clear Command #define CDD_LMM_N_TX_ClearOpenShortErrors (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_04_BYTES + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_TX_ClearChargePumpErrors (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_01_BYTE + CDD_LMM_N_CRC_BYTES) //read COMMAND #define CDD_LMM_N_TX_GetPwmFreqPhase (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_TX_GetRev (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_TX_GetErrorsStatus (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_TX_GetOpenShortStatus (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_TX_GetTemperatureStatus (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_TX_GetIOconfig (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_TX_GetChargePumpStatus (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_TX_GetPWMConfig (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_TX_GetADCData (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_CRC_BYTES) //RX #define CDD_LMM_N_RX_SetPWMs (CDD_LMM_N_TX_SetPWMs + CDD_LMM_N_ACK) #define CDD_LMM_N_RX_ExitLimpHome (CDD_LMM_N_TX_ExitLimpHome + CDD_LMM_N_ACK) #define CDD_LMM_N_RX_resPwmFreqPhase (CDD_LMM_N_TX_GetPwmFreqPhase + CDD_LMM_N_01_BYTE + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_RX_resRev (CDD_LMM_N_TX_GetRev + CDD_LMM_N_02_BYTES + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_RX_resGetErrorsStatus (CDD_LMM_N_TX_GetErrorsStatus + CDD_LMM_N_02_BYTES + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_RX_resGetOpenShortStatus (CDD_LMM_N_TX_GetOpenShortStatus + CDD_LMM_N_04_BYTES + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_RX_resGetTemperatureStatus (CDD_LMM_N_TX_GetTemperatureStatus + CDD_LMM_N_04_BYTES + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_RX_resIOconfig (CDD_LMM_N_TX_GetIOconfig + CDD_LMM_N_01_BYTE + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_RX_resGetChargePumpStatus (CDD_LMM_N_TX_GetChargePumpStatus + CDD_LMM_N_04_BYTES + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_RX_resGetPWMConfig (CDD_LMM_N_TX_GetPWMConfig + CDD_LMM_N_01_BYTE + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_RX_resGetADCData (CDD_LMM_N_TX_GetADCData + CDD_LMM_N_04_BYTES + CDD_LMM_N_CRC_BYTES) #define CDD_LMM_N_RX_StartADCconvert (CDD_LMM_N_TX_StartADCconvert + CDD_LMM_N_ACK) //Length of Clear FAULT broadcast write command #define CDDMLCInd8308_N_TX_CLRFLT (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_04_BYTES + CDD_LMM_N_CRC_BYTES) #define CDDMLCInd8308_N_TX_ConfigPWMs (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_01_BYTE + CDD_LMM_N_CRC_BYTES) //step 2) Configure Chip configuration write command #define CDDMLCInd8308_N_TX_CFG_CHIP (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_03_BYTES + CDD_LMM_N_CRC_BYTES) #define CDDMLCInd8308_N_RX_CFG_CHIP (CDDMLCInd8308_N_TX_CFG_CHIP + CDDMLCInd8308_N_ACK) //step 3) Configure Phase Shifts settings write command #define CDDMLCInd8308_N_TX_CFG_4BYTES_PHASE (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_04_BYTES + CDD_LMM_N_CRC_BYTES) #define CDDMLCInd8308_N_TX_CFG_16BYTES_PHASE (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_16_BYTES + CDD_LMM_N_CRC_BYTES) #define CDDMLCInd8308_N_RX_CFG_4BYTES_PHASE (CDDMLCInd8308_N_TX_CFG_4BYTES_PHASE + CDDMLCInd8308_N_ACK) #define CDDMLCInd8308_N_RX_CFG_16BYTES_PHASE (CDDMLCInd8308_N_TX_CFG_16BYTES_PHASE + CDDMLCInd8308_N_ACK) //step 4) Configure LED segments settings write command #define CDDMLCInd8308_N_TX_CFG_2BYTES_STRING (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_02_BYTES + CDD_LMM_N_CRC_BYTES) #define CDDMLCInd8308_N_TX_CFG_16BYTES_STRING (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_16_BYTES + CDD_LMM_N_CRC_BYTES) #define CDDMLCInd8308_N_RX_CFG_2BYTES_STRING (CDDMLCInd8308_N_TX_CFG_2BYTES_STRING + CDDMLCInd8308_N_ACK) #define CDDMLCInd8308_N_RX_CFG_16BYTES_STRING (CDDMLCInd8308_N_TX_CFG_16BYTES_STRING + CDDMLCInd8308_N_ACK) //step 5) Configure write command to exit failsafe #define CDDMLCInd8308_N_TX_CFG_01BYTE_EXITFAILSAFE (CDD_LMM_N_HEADER_BYTES_ALAD + CDD_LMM_N_01_BYTE + CDD_LMM_N_CRC_BYTES) #define CDDMLCInd8308_N_RX_CFG_01BYTE_EXITFAILSAFE (CDDMLCInd8308_N_TX_CFG_01BYTE_EXITFAILSAFE + CDDMLCInd8308_N_ACK) //Reception lengths: Tx + Header + Payload + CRC #define CDDMLCInd8308_N_RX_4BYTES_WIDTH (CDDMLCInd8308_N_TX_4BYTES_WIDTH + CDDMLCInd8308_N_ACK) #define CDDMLCInd8308_N_RX_16BYTES_WIDTH (CDDMLCInd8308_N_TX_16BYTES_WIDTH + CDDMLCInd8308_N_ACK) #define CDDMLCInd8308_N_RX_ICID (CDDMLCInd8308_N_TX_ICID + CDD_LMM_N_01_BYTE + CDD_LMM_N_CRC_BYTES) // simulation interface (activated by compiler switch only) #if (CddMlcInd8308_Cfg_Simulation == 1u) #define MLC_Sim_ElectricalErrors 0x5A5AA5A5u STATIC_AL volatile uint32 CddMlcGen_ulTesterHookActivation = 0u; STATIC_AL volatile tsCddMlcInd8308_SimulationData CddMlcInd8308_sSimulationData; #endif //============================================================================= // local type definitions //============================================================================= // Access MLC Coding structure //extern sCddMlcGenCodingData CddMlcGenCodingDataValue; // Access MLC Coding structure #ifndef UNIT_TEST extern sCddMlcGenCodingData CddMlcGenCodingDataValue; #else sCddMlcGenCodingData CddMlcGenCodingDataValue; #endif //============================================================================= // STATIC_AL variables //============================================================================= /* The Counter of Clear LED Segments Faults Command to be sent */ STATIC_AL uint8 CddMlcInd8308_ucClearFaults = CDDMLCInd8308_CFG_CLR_FLT_CNT; /* The Mlc device picked in current cycle multiplexed commands */ STATIC_AL uint8 CddMlcInd8308_ucChipNbr = 0u; /* Mlc Register configuration for each chip */ STATIC_AL tsCddMlcInd8308_RegisterConfig CddMlcInd8308_aucChipSysConfig_List[CFG_MAX_NO_OF_MLC]; STATIC_AL tuCddMlcInd8308_StatusRegister CddMlcInd8308_aucChipStatus[CFG_MAX_NO_OF_MLC]; /* ADC Result including Quality Factor for each chip */ STATIC_AL tsCddMlcInd8308_AdcResult CddMlcInd8308_asAdcResult_List[CFG_MAX_NO_OF_MLC]; /* Led status for each Mlc chip */ STATIC_AL tsCddMlcInd8308_LedStatus CddMlcInd8308_asLedStatus_List[CFG_MAX_NO_OF_MLC]; /* Global Mlc communication status */ STATIC_AL tsCddMlcInd8308_ComStatus CddMlcInd8308_ComStatus; /* Global Mlc System Mode - Initial mode is Inactive */ STATIC_AL teCddMlcInd8308_SystemMode CddMlcInd8308_SystemMode = CddMlcInd8308_SystemMode_Inactive; /* Global Mlc System Mode - Initial mode is Inactive */ STATIC_AL teCddMlcInd8308_SystemMode CddMlcInd8308_LastSystemMode = CddMlcInd8308_SystemMode_Inactive; /* buffer step 1 ) Broadcast Adressing Scheme + Basic Communication command */ STATIC_AL uint8 CddMlcInd8308_aucCmdBroadcastCfgComm_List[CFG_MAX_NO_OF_MLC][CDDMLCInd8308_N_TX_CFG_COM]; /* Broadcast Adressing Scheme + Basic Communication response */ STATIC_AL uint8 CddMlcInd8308_aucResBroadcastCfgComm_List[CFG_MAX_NO_OF_MLC][CDDMLCInd8308_N_RX_CFG_COM]; /* Break response command, in ZhiXin platform, break field is sent by uart-can driver */ STATIC_AL uint8 CddLmm_ucResBreak_List[CDD_LMM_N_01_BYTE]; /* Broadcast Clear Faults Command */ STATIC_AL uint8 CddMlcInd8308_aucCmdBroadcastFault_List[CDDMLCInd8308_N_TX_CLRFLT]; /* Broadcast Clear Faults Response */ STATIC_AL uint8 CddMlcInd8308_aucResBroadcastFault_List[CDDMLCInd8308_N_TX_CLRFLT]; /* TX Read Command of one chips */ STATIC_AL uint8 CddMlcInd8308_aucCommand_List[CFG_MAX_NO_OF_MLC][CDDMLCInd8308_N_TX_CFG_CHIP]; //Ind. Chip Command STATIC_AL uint8 CddMlcInd8308_aucResponse_List[CFG_MAX_NO_OF_MLC][CDDMLCInd8308_N_RX_CFG_CHIP]; //Ind. Chip Response /* Single Chip Read LED Segments Faults command and response buffer */ STATIC_AL uint8 CddMlcInd8308_aucCmdRdFault_List[CDD_LMM_N_TX_GetOpenShortStatus]; //Read Fault Command STATIC_AL uint8 CddMlcInd8308_aucResRdFault_List[CDD_LMM_N_RX_resGetOpenShortStatus]; //Read Fault Response /* Single Chip Read Configuration Registers command and response buffer */ STATIC_AL uint8 CddMlcInd8308_aucCmdRdStatus[CDD_LMM_N_TX_GetErrorsStatus]; //Read Status Command STATIC_AL uint8 CddMlcInd8308_aucResRdStatus[CDD_LMM_N_RX_resGetErrorsStatus]; //Read Status Response /* Single Chip Read ADC Results command and response buffer */ STATIC_AL uint8 CddMlcInd8308_aucCmdRdADC_List[CDD_LMM_N_TX_GetADCData]; //Read ADCs Command STATIC_AL uint8 CddMlcInd8308_aucResRdADC_List[CDD_LMM_N_RX_resGetADCData]; //Read ADCs Response /* Write/boardcast Command */ STATIC_AL uint8 CddLmm_ucStartADCconvert_List[CFG_MAX_NO_OF_MLC][CDD_LMM_N_TX_StartADCconvert]; STATIC_AL uint8 CddLmm_reStartADCconvert_List[CFG_MAX_NO_OF_MLC][CDD_LMM_N_RX_StartADCconvert]; STATIC_AL uint8 CddLmm_ucBreak_List[CDD_LMM_N_TX_break]; STATIC_AL uint8 CddLmm_ucCmdEnablePWMs_List[CDD_LMM_N_TX_EnablePWMs]; STATIC_AL uint8 CddLmm_ucDisableWDT_List[CDD_LMM_N_TX_DisableWDT]; STATIC_AL uint8 CddLmm_ucWDTimeout_List[CDD_LMM_N_TX_WDTimeout]; STATIC_AL uint8 CddLmm_ucAddressModeConfig_List[CDD_LMM_N_TX_AddressModeConfig]; STATIC_AL uint8 CddLmm_ucExitLimpHome_List[CDD_LMM_N_TX_ExitLimpHome]; STATIC_AL uint8 CddLmm_ucSAR_List280[CDD_LMM_N_TX_SAR]; STATIC_AL uint8 CddLmm_ucADC_Address_list[CDD_LMM_N_TX_ADC_Address]; STATIC_AL uint8 CddLmm_ucStartADC_List2A0[CDD_LMM_N_TX_StartADC2A0]; STATIC_AL uint8 CddLmm_ucIO_Config_List[CDD_LMM_N_TX_IO_Config]; STATIC_AL uint8 CddLmm_ucSlewRate_List[CDD_LMM_N_TX_SlewRate]; STATIC_AL uint8 CddLmm_ucALAD_CfgACK_List[CDD_LMM_N_TX_CfgACK]; STATIC_AL uint8 CddLmm_ucConfigPWMs_List[CDD_LMM_N_TX_ConfigPWMs]; STATIC_AL uint8 CddLmm_ucConfigDefwidth1_List[CDD_LMM_N_TX_ConfigDefwidth1]; STATIC_AL uint8 CddLmm_ucConfigDefwidth2_List[CDD_LMM_N_TX_ConfigDefwidth2]; /* set PWM Chip commands and responses buffer */ STATIC_AL uint8 CddLmm_ucSetPwm_List[CFG_MAX_NO_OF_MLC][CDD_LMM_N_TX_SetPWMs]; //Ind. Chip Command send STATIC_AL uint8 CddLmm_reSetPwm_List[CFG_MAX_NO_OF_MLC][CDD_LMM_N_RX_SetPWMs]; //Ind. Chip Command recieve /* Pointer to UART Command Status */ STATIC_AL tCddMlcInd8308Uart_Status *CddMlcInd8308_psCommmandStatus[CDDMLCInd8308_COMMANDS]; // PRQA S 1504 // The variable is STATIC_AL and used in this module STATIC_AL uint8 CddLmm_ucAddrMode_Config_List[CDD_LMM_N_TX_IO_Config]; STATIC_AL uint8 CddLmm_ucInit_Config_List[CDD_LMM_N_TX_AddressModeConfig]; /* Current Target Duty Cycles - Input Width */ STATIC_AL uint16 CddMlcInd8308_aunTargetLedWidths_List[/*CFG_MAX_NO_OF_MLC*/][CDDMLCInd8308_LEDS] = CDDMLCInd8308_DUTY_CYCLE_INIT; // PRQA S 1504 // The variable is static and used in this module /* Current Actual Duty Cycles - Output Width */ STATIC_AL uint16 CddMlcInd8308_aunActualLedWidths_List[/*CFG_MAX_NO_OF_MLC*/][CDDMLCInd8308_LEDS] = CDDMLCInd8308_DUTY_CYCLE_INIT; // PRQA S 1504 // The variable is static and used in this module /* Mlc chip hardware DeviceID mapping */ STATIC_AL uint8 CddMlcInd8308_aucDevIdTable_List[CFG_MAX_NO_OF_MLC]; STATIC_AL uint8 CddMlcInd8308_aucDevIdTableIdx_List[CFG_MAX_NO_OF_MLC]; /* Mlc chips physical addresses */ STATIC_AL CONST_AL uint8 CddMlcInd8308_aucAddress[2u * CFG_MAX_NO_OF_ADDRS_MLC] = { CDDMLCInd8308_DEV_ID00, CDDMLCInd8308_DEV_ID01, CDDMLCInd8308_DEV_ID02, CDDMLCInd8308_DEV_ID03, CDDMLCInd8308_DEV_ID04, CDDMLCInd8308_DEV_ID05, CDDMLCInd8308_DEV_ID06, CDDMLCInd8308_DEV_ID07, \ CDDMLCInd8308_DEV_ID08, CDDMLCInd8308_DEV_ID09, CDDMLCInd8308_DEV_ID10, CDDMLCInd8308_DEV_ID11, CDDMLCInd8308_DEV_ID12, CDDMLCInd8308_DEV_ID13, CDDMLCInd8308_DEV_ID14, CDDMLCInd8308_DEV_ID15 }; /* used to store the collected Error information */ STATIC_AL boolean CddMlcInd8308_aboDevComError[CFG_MAX_NO_OF_MLC] = { FALSE }; STATIC_AL boolean CddMlcInd8308_boBusComError = FALSE; STATIC_AL boolean CddMlcInd8308_aboDeviceResponse[CFG_MAX_NO_OF_MLC] = { FALSE }; // mark the chip responded with ACK byte /* Cdd Mlc transmit error counter */ STATIC_AL uint8 CddMlcInd8308_TxErrCnt = 0u; STATIC_AL uint32 CddMlcInd8308_ulBusErrMask = 0u; /* ind83080 device number */ STATIC_AL uint8 CddMlc8308_ConnectedDevices = 0u; STATIC_AL teCddMlcInd8308_DEVIDByte_WithParity eBroadcastDevAddr = CDDMLCInd8308_DEV_ID00; #if (CDDMLCInd8308_LOOKUP_TABLE_CRC == CDD_LMM_FEATURE_ON) /* Use LookUpTable for 0xA001 Polynom 16 bit CRC Computation */ STATIC_AL CONST_AL uint16 CddMlcInd8308_unCrc16_List[256u] = { 0x0000u, 0xc0c1u, 0xc181u, 0x0140u, 0xc301u, 0x03c0u, 0x0280u, 0xc241u, 0xc601u, 0x06c0u, 0x0780u, 0xc741u, 0x0500u, 0xc5c1u, 0xc481u, 0x0440u, 0xcc01u, 0x0cc0u, 0x0d80u, 0xcd41u, 0x0f00u, 0xcfc1u, 0xce81u, 0x0e40u, 0x0a00u, 0xcac1u, 0xcb81u, 0x0b40u, 0xc901u, 0x09c0u, 0x0880u, 0xc841u, 0xd801u, 0x18c0u, 0x1980u, 0xd941u, 0x1b00u, 0xdbc1u, 0xda81u, 0x1a40u, 0x1e00u, 0xdec1u, 0xdf81u, 0x1f40u, 0xdd01u, 0x1dc0u, 0x1c80u, 0xdc41u, 0x1400u, 0xd4c1u, 0xd581u, 0x1540u, 0xd701u, 0x17c0u, 0x1680u, 0xd641u, 0xd201u, 0x12c0u, 0x1380u, 0xd341u, 0x1100u, 0xd1c1u, 0xd081u, 0x1040u, 0xf001u, 0x30c0u, 0x3180u, 0xf141u, 0x3300u, 0xf3c1u, 0xf281u, 0x3240u, 0x3600u, 0xf6c1u, 0xf781u, 0x3740u, 0xf501u, 0x35c0u, 0x3480u, 0xf441u, 0x3c00u, 0xfcc1u, 0xfd81u, 0x3d40u, 0xff01u, 0x3fc0u, 0x3e80u, 0xfe41u, 0xfa01u, 0x3ac0u, 0x3b80u, 0xfb41u, 0x3900u, 0xf9c1u, 0xf881u, 0x3840u, 0x2800u, 0xe8c1u, 0xe981u, 0x2940u, 0xeb01u, 0x2bc0u, 0x2a80u, 0xea41u, 0xee01u, 0x2ec0u, 0x2f80u, 0xef41u, 0x2d00u, 0xedc1u, 0xec81u, 0x2c40u, 0xe401u, 0x24c0u, 0x2580u, 0xe541u, 0x2700u, 0xe7c1u, 0xe681u, 0x2640u, 0x2200u, 0xe2c1u, 0xe381u, 0x2340u, 0xe101u, 0x21c0u, 0x2080u, 0xe041u, 0xa001u, 0x60c0u, 0x6180u, 0xa141u, 0x6300u, 0xa3c1u, 0xa281u, 0x6240u, 0x6600u, 0xa6c1u, 0xa781u, 0x6740u, 0xa501u, 0x65c0u, 0x6480u, 0xa441u, 0x6c00u, 0xacc1u, 0xad81u, 0x6d40u, 0xaf01u, 0x6fc0u, 0x6e80u, 0xae41u, 0xaa01u, 0x6ac0u, 0x6b80u, 0xab41u, 0x6900u, 0xa9c1u, 0xa881u, 0x6840u, 0x7800u, 0xb8c1u, 0xb981u, 0x7940u, 0xbb01u, 0x7bc0u, 0x7a80u, 0xba41u, 0xbe01u, 0x7ec0u, 0x7f80u, 0xbf41u, 0x7d00u, 0xbdc1u, 0xbc81u, 0x7c40u, 0xb401u, 0x74c0u, 0x7580u, 0xb541u, 0x7700u, 0xb7c1u, 0xb681u, 0x7640u, 0x7200u, 0xb2c1u, 0xb381u, 0x7340u, 0xb101u, 0x71c0u, 0x7080u, 0xb041u, 0x5000u, 0x90c1u, 0x9181u, 0x5140u, 0x9301u, 0x53c0u, 0x5280u, 0x9241u, 0x9601u, 0x56c0u, 0x5780u, 0x9741u, 0x5500u, 0x95c1u, 0x9481u, 0x5440u, 0x9c01u, 0x5cc0u, 0x5d80u, 0x9d41u, 0x5f00u, 0x9fc1u, 0x9e81u, 0x5e40u, 0x5a00u, 0x9ac1u, 0x9b81u, 0x5b40u, 0x9901u, 0x59c0u, 0x5880u, 0x9841u, 0x8801u, 0x48c0u, 0x4980u, 0x8941u, 0x4b00u, 0x8bc1u, 0x8a81u, 0x4a40u, 0x4e00u, 0x8ec1u, 0x8f81u, 0x4f40u, 0x8d01u, 0x4dc0u, 0x4c80u, 0x8c41u, 0x4400u, 0x84c1u, 0x8581u, 0x4540u, 0x8701u, 0x47c0u, 0x4680u, 0x8641u, 0x8201u, 0x42c0u, 0x4380u, 0x8341u, 0x4100u, 0x81c1u, 0x8081u, 0x4040u }; #endif /* Cyclic Task Time Measurement variables */ #if (CDDMLCInd8308_MEASURE_CYCLE_TIME == CDD_LMM_FEATURE_ON) STATIC_AL tFTimer CddMlcInd8308_udStartTime, CddMlcInd8308_udEndTime; STATIC_AL tFTimer CddMlcInd8308_udDeltaT = 0u; STATIC_AL tFTimer CddMlcInd8308_udMovAverT = 0u; STATIC_AL tFTimer CddMlcInd8308_udMeanT = 0u; STATIC_AL tFTimer CddMlcInd8308_udMinT = 0xFFFFFFFFu; STATIC_AL tFTimer CddMlcInd8308_udMaxT = 0u; #endif //============================================================================= // local function prototypes //============================================================================= STATIC_AL void CddMlcInd8308_ResetVars(void); STATIC_AL void CddMlcInd8308_ExitFailSafe(void); STATIC_AL void CddLmm_Broadcast_Config_Addr_Mode(void); STATIC_AL void CddMlcInd8308_WritePWMs(uint8 ucFamDevNbr); STATIC_AL void CddMlcInd8308_MuxCommands(void); //STATIC_AL void CddMlcInd8308_DriverTest(void); STATIC_AL void CddMlcInd8308_InterpretResponses(void); STATIC_AL void CddMlcInd8308_StepToNextChip(void); STATIC_AL void CddMlcInd8308_ScheduleCommands(void); STATIC_AL void CddMlcInd8308_CommandSuccess(uint8 ucCmdIdx); STATIC_AL void CddMlcInd8308_CommandFailed(uint8 ucCmdIdx); STATIC_AL void CddMlcInd8308_ResponseHandler(uint8 ucDevNbr); /* Diagnosis */ STATIC_AL void CddMlcInd8308_ResetCommunicationFaults(void); STATIC_AL void CddMlcInd8308_SDReadRespHandler(uint8 ucDevNbr); STATIC_AL void CddMlcInd8308_CheckCRC(uint8 ucDevNbr, uint8 *ucPtrData, uint8 ucLength); #if (CDDMLCInd8308_RTE_INTERFACES == CDD_LMM_FEATURE_ON) STATIC_AL void CddMlcInd8308_RteSync(void); #endif STATIC_AL uint8 CddMlcInd8308_GetMlcPhysicalAddress(void); #if 0 STATIC_AL uint8 CddMlcInd8308_GetMlcIndexNumber(uint8 address); // #endif //============================================================================= // functions //============================================================================= //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_GetMlcPhysicalAddress /// /// \descr store the address for each MLC device read from coding data /// /// \param - /// /// \return void //----------------------------------------------------------------------------- STATIC_AL uint8 CddMlcInd8308_GetMlcPhysicalAddress(void) { uint8 ucDeviceConnected = 0U; uint32 ulDeviceIdx = 0U; for (ulDeviceIdx = 0; ulDeviceIdx < CDDMLC_SUPPORTED_MLCs; ulDeviceIdx++) { if ((uint8)CDD_MLC_PHY_CHIP_ID[ulDeviceIdx] != MLC_DEV_ADDR_NOT_CONNECTED) { CddMlcInd8308_aucDevIdTable_List[ucDeviceConnected] = CddMlcInd8308_aucAddress[CddMlcGenCodingDataValue.ucMlcCanUartAddress[ulDeviceIdx]];// (uint8)CDDMLCInd8308_PHY_CHIP_ID[ulDeviceIdx]; // take ulDeviceIdx because it corresponds to the index from coding data for address // CddMlcInd8308_aucDevIdTableIdx_List[ucDeviceConnected] = CddMlcGenCodingDataValue.ucMlcCanUartAddress[ulDeviceIdx]; CddMlcInd8308_aucDevIdTableIdx_List[ucDeviceConnected] = (uint8)ulDeviceIdx; ucDeviceConnected++; } else { // do nothing; the chip is not connected } } return ucDeviceConnected; } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_GetMlcIndexNumber /// /// \descr get the MLC index number /// /// \param address : physical chip address /// /// \return uint8 : chip index //----------------------------------------------------------------------------- #if 0 // this function will be used when implementing error detection uint8 CddMlcInd8308_GetMlcIndexNumber(uint8 address) { uint8 ucDeviceIdx; for (ucDeviceIdx = 0U; ucDeviceIdx < CDDMLCInd8308_CODING_DATA_CONNECTED_DEVICES; ucDeviceIdx++) { if (address == CddMlcInd8308_aucDevIdTable_List[ucDeviceIdx]) { break; } } return (ucDeviceIdx); } #endif //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_GetTargetBufAddress /// /// \descr return the target values for pixels /// /// \param - /// /// \return uint16 * //----------------------------------------------------------------------------- // PRQA S 1505,3408 ++ //The Function is called from external modules uint16* CddMlcInd8308_GetTargetBufAddress(void) { return((uint16*)(&CddMlcInd8308_aunTargetLedWidths_List[0u][0u])); } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_Init /// /// \descr The function trigger UART driver initalization /// and initializes the Led Matrix Manager driver /// /// \param none /// /// \return none //----------------------------------------------------------------------------- void CddMlcInd8308_Init(void) { //create a bit mask used for checking bus error (all MLC's are faulty) for (uint32 ulPos= 0u; ulPos < CDD_MLC_CHIPS; ulPos++) { CddMlcInd8308_ulBusErrMask |= (uint32)((uint32)1u << ulPos); } // Do hardware device mapping of MLC chip addresses CddMlc8308_ConnectedDevices = CddMlcInd8308_GetMlcPhysicalAddress(); // Open the UART channel for communication with the Mlc UartCan1_Init(); // Reset Internal Variables such as Communication Status, LED Fault Status, ADC Results CddMlcInd8308_ResetVars(); #if (CDDMLCInd8308_START_AT_POWERUP == CDD_LMM_FEATURE_ON) // Cyclic Transmission is started CddMlcInd8308_SystemMode = CddMlcInd8308_SystemMode_CfgComm; // Cyclic Transmission is started CddMlcInd8308_LastSystemMode = CddMlcInd8308_SystemMode_CfgComm; #endif } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_Cycle /// /// \descr Led Matrix Manager Cyclic Handler /// /// \param none /// /// \return none //----------------------------------------------------------------------------- void CddMlcInd8308_Cycle(void) { #if (CDDMLCInd8308_MEASURE_CYCLE_TIME == CDD_LMM_FEATURE_ON) CddMlcInd8308_udStartTime = TimerGetTick(); #endif // The Mlc transmission should be active? if (CddMlcInd8308_SystemMode != CddMlcInd8308_SystemMode_Inactive) { // 1. Handle responses and statuses CddMlcInd8308_InterpretResponses(); // once one chip comm error, retry to send boradcast command to set addr mode if ( (CddMlcInd8308_ComStatus.ulMlcStatus & 0xffffffff) != 0u ) { CddLmm_Broadcast_Config_Addr_Mode(); } #if (CDDMLCInd8308_RTE_INTERFACES == CDD_LMM_FEATURE_ON) // Save the results of the executed commands, then load the input values for new commands. CddMlcInd8308_RteSync(); #endif // 2. Point to next chip index for multiplexed commands CddMlcInd8308_StepToNextChip(); // recover mechanism if (CddMlcInd8308_ComStatus.ulPowerCycleOccurred > 0U) { CddMlcInd8308_ComStatus.ulPowerCycleOccurred = 0u; CddMlcInd8308_SetTransmissionToNormal(); } // 3. Update and schedule commands CddMlcInd8308_ScheduleCommands(); } else { // Mlc driver transmission is OFF // Send the MLC driver state to the application //(void)Rte_Write_ppaseCddMlcMxSwitchStatusError0_eMlcComStatus(0); } #if (CDDMLCInd8308_MEASURE_CYCLE_TIME == CDD_LMM_FEATURE_ON) // Get Time at Mlc Cycle End CddMlcInd8308_udEndTime = TimerGetTick(); // Compute Difference CddMlcInd8308_udDeltaT = (tFTimer)CddMlcInd8308_udEndTime - CddMlcInd8308_udStartTime; // Compute Moving Average CddMlcInd8308_udMovAverT += CddMlcInd8308_udDeltaT; CddMlcInd8308_udMovAverT -= (CddMlcInd8308_udMovAverT >> CDDMLCInd8308_MOVING_AVERAGE_BITS); CddMlcInd8308_udMeanT = CddMlcInd8308_udMovAverT >> CDDMLCInd8308_MOVING_AVERAGE_BITS; (void)CddMlcInd8308_udMeanT; // The variable is used on developer mode for computing the average mean time of cyclic task // Compute Min-Max CddMlcInd8308_udMaxT = (CddMlcInd8308_udDeltaT > CddMlcInd8308_udMaxT) ? CddMlcInd8308_udDeltaT : CddMlcInd8308_udMaxT; CddMlcInd8308_udMinT = (CddMlcInd8308_udDeltaT < CddMlcInd8308_udMinT) ? CddMlcInd8308_udDeltaT : CddMlcInd8308_udMinT; #endif } #if (CDDMLCInd8308_RTE_INTERFACES == CDD_LMM_FEATURE_ON) //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_RteSync /// /// \descr The function save previous command results in RTE interfaces and /// load new values for new commands to be sent from RTE interfaces. /// /// \param none /// /// \return none //----------------------------------------------------------------------------- STATIC_AL void CddMlcInd8308_RteSync(void) { // Save the results of the executed commands //CddMlcInd8308_RteWrite_SystemMode(&CddMlcInd8308_SystemMode); //CddMlcInd8308_RteWrite_ComStatus(&CddMlcInd8308_ComStatus); //CddMlcInd8308_RteWrite_LedStatus(&CddMlcInd8308_asLedStatus_List[0u]); //CddMlcInd8308_RteWrite_AdcResult(&CddMlcInd8308_asAdcResult_List[0u]); //CddMlcInd8308_RteWrite_AckLedPwms(&CddMlcInd8308_aunActualLedWidths_List[0u][0u]); // Load the input values for new commands. //CddMlcInd8308_RteRead_TgtLedPwms(&CddMlcInd8308_aunTargetLedWidths_List[0u][0u]); // Writeback the received input values to the RTE. //CddMlcInd8308_RteWrite_TgtLedPwms(&CddMlcInd8308_aunTargetLedWidths_List[0u][0u]); } #endif //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_SetTransmissionActive /// /// \descr Set the Mlc transmission to desired state /// /// \param boolean Transmission Active Flag /// /// \return none //----------------------------------------------------------------------------- void CddMlcInd8308_SetTransmissionActive(boolean boDriverActive) { // Set the driver System Mode according to desired transmission state CddMlcInd8308_SystemMode = (TRUE == boDriverActive) ? CddMlcInd8308_SystemMode_CfgComm : CddMlcInd8308_SystemMode_Inactive; } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_SetTransmissionToInactive /// /// \descr The function disables transmission /// /// \param - /// /// \return void //----------------------------------------------------------------------------- void CddMlcInd8308_SetTransmissionToInactive(void) { // Set the driver System Mode to inactive CddMlcInd8308_SystemMode = CddMlcInd8308_SystemMode_Inactive; } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_SetTransmissionToNormal /// /// \descr The function enables transmission /// /// \param - /// /// \return void //----------------------------------------------------------------------------- void CddMlcInd8308_SetTransmissionToNormal(void) { // Set the driver System Mode to normal CddMlcInd8308_SystemMode = CddMlcInd8308_SystemMode_CfgComm; } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_InterpretResponses /// /// \descr The function decodes the responses from previuos commands cycle, /// saves the values of ADCs, FAULT registers etc and /// updates the global status depending of the commands status. /// /// \param none /// /// \return none //----------------------------------------------------------------------------- STATIC_AL void CddMlcInd8308_InterpretResponses(void) { uint8 ucCmdIdx; static uint32 u32FailureCunt = 0; static uint32 u32SuccessCunt = 0; //parse each message command sent for (ucCmdIdx = 0u; ucCmdIdx < (uint8)CDDMLCInd8308_COMMANDS; ucCmdIdx++) { //pointer valid? if (CddMlcInd8308_psCommmandStatus[ucCmdIdx] != NULL_PTR) { //current status successful? if (1u == (uint8)CddMlcInd8308_psCommmandStatus[ucCmdIdx]->boRxSuccess) { // Command received successfully -> collect results and reset timeout counters CddMlcInd8308_CommandSuccess(ucCmdIdx); u32SuccessCunt = ( u32SuccessCunt + 1 ) % 0xFFFFFFF0u; } else { // Command Failed -> update timeout counters CddMlcInd8308_CommandFailed(ucCmdIdx); u32FailureCunt = ( u32FailureCunt + 1 ) % 0xFFFFFFF0u; } // // The Entry is sill used -> Command not set in Mlc cycle AND Tx Commands Overrun Counter did not reached maximum // if ((1u == (uint8)CddMlcInd8308_psCommmandStatus[ucCmdIdx]->boEntryUsed) && // (CddMlcInd8308_ComStatus.ulTxCommandOverrun < 0xFFFFFFFFu)) // { // // Increment Tx Commands Overrun // CddMlcInd8308_ComStatus.ulTxCommandOverrun++; // } // else // { // // No action // } // // if Uart Error occurred during command/response execution AND UART Errors Counter did not reached maximum // if (((1u == (uint8)CddMlcInd8308_psCommmandStatus[ucCmdIdx]->boBitError) || // (1u == (uint8)CddMlcInd8308_psCommmandStatus[ucCmdIdx]->boFramingError) || // (1u == (uint8)CddMlcInd8308_psCommmandStatus[ucCmdIdx]->boOverrunError)) && // (CddMlcInd8308_ComStatus.ulUartErrorsOccurred < 0xFFFFFFFFu)) // { // // Increment UART Errors Counter // CddMlcInd8308_ComStatus.ulUartErrorsOccurred++; // } // else // { // // No action // } // Invalidate Command Status after command processing CddMlcInd8308_psCommmandStatus[ucCmdIdx] = (tCddMlcInd8308Uart_Status*)NULL_PTR; } else { // Pointer CddMlcInd8308_psCommmandStatus is not valid/initialised // Command Failed -> update timeout counters CddMlcInd8308_CommandFailed(ucCmdIdx); } }// end main for } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_CommandSuccess /// /// \descr The function decodes the responses from previuos commands cycle, /// saves the values of ADCs, FAULT registers etc and /// updates the global status depending of the commands status. /// /// \param uint8 /// /// \return none //----------------------------------------------------------------------------- STATIC_AL void CddMlcInd8308_CommandSuccess(uint8 ucCmdIdx) { // first commands are addressed to each chip if (ucCmdIdx < CddMlc8308_ConnectedDevices /*CDD_MLC_CHIPS*/) { //reset timeout counter on each device CddMlcInd8308_ComStatus.aucTimeoutCounter_List[ucCmdIdx] = 0u; //Remove the Timeout flag from current Mlc chip CddMlcInd8308_ComStatus.ulMlcStatus &= (~((uint32)1u << ucCmdIdx)); CddMlcInd8308_boBusComError = ((CddMlcInd8308_ComStatus.ulMlcStatus & CddMlcInd8308_ulBusErrMask) == CddMlcInd8308_ulBusErrMask) ? TRUE : FALSE; //Evaluate received bytes and save results CddMlcInd8308_ResponseHandler(ucCmdIdx); } else if ((uint8)CDDMLCInd8308_CMD_IDX_READ_CNFG == ucCmdIdx) // Read Configuration Command Index { // Succeded reading Segment Configuration Registers => Save the current values CddMlcInd8308_aucChipStatus[CddMlcInd8308_ucChipNbr].ucStatusRegister = CddMlcInd8308_aucResRdStatus[CDD_LMM_N_TX_GetErrorsStatus + 0u]|(CddMlcInd8308_aucResRdStatus[CDD_LMM_N_TX_GetErrorsStatus + 1u]<<8); //If wotch dog Register is not set if (0X01 != (CddMlcInd8308_aucChipStatus[CddMlcInd8308_ucChipNbr].BitStatus.WDT_RUNNING) || 0X01 != (CddMlcInd8308_aucChipStatus[CddMlcInd8308_ucChipNbr].BitStatus.PWM_RUNNING)) { // Mark the PowerCycle flag to current Mlc chip CddMlcInd8308_ComStatus.ulPowerCycleOccurred |= ((uint32)1u << CddMlcInd8308_ucChipNbr); } else { // Reset the PowerCycle flag from current Mlc chip CddMlcInd8308_ComStatus.ulPowerCycleOccurred &= (~((uint32)1u << CddMlcInd8308_ucChipNbr)); } } else if ((uint8)CDDMLCInd8308_CMD_IDX_READ_ADCS == ucCmdIdx) { // Succeded reading ADC values => Save the current values CddMlcInd8308_asAdcResult_List[CddMlcInd8308_aucDevIdTableIdx_List[CddMlcInd8308_ucChipNbr]].ucADC1Value =(uint16)((CddMlcInd8308_aucResRdADC_List[CDD_LMM_N_TX_GetADCData + 0u] | (CddMlcInd8308_aucResRdADC_List[CDD_LMM_N_TX_GetADCData + 1u]<<8))); CddMlcInd8308_asAdcResult_List[CddMlcInd8308_aucDevIdTableIdx_List[CddMlcInd8308_ucChipNbr]].ucADC2Value = (uint16)((CddMlcInd8308_aucResRdADC_List[CDD_LMM_N_TX_GetADCData + 2u] | (CddMlcInd8308_aucResRdADC_List[CDD_LMM_N_TX_GetADCData + 3u]<<8))); // Validate the ADC result flag CddMlcInd8308_asAdcResult_List[CddMlcInd8308_aucDevIdTableIdx_List[CddMlcInd8308_ucChipNbr]].eQlty = CDDMLCInd8308_QLTY_VALID; } else if ((uint8)CDDMLCInd8308_CMD_IDX_READ_FLTS == ucCmdIdx) { //OK on device CddMlcInd8308_ChipNbr => save current received Led fault status and Crc error counter values CddMlcInd8308_asLedStatus_List[CddMlcInd8308_aucDevIdTableIdx_List[CddMlcInd8308_ucChipNbr]].unLedFaultOpen = (((uint16)CddMlcInd8308_aucResRdFault_List[CDD_LMM_N_TX_GetOpenShortStatus + 0u] << 0u) & 0x00FFu); // save the FAULTL value for the 0-7 LEDs CddMlcInd8308_asLedStatus_List[CddMlcInd8308_aucDevIdTableIdx_List[CddMlcInd8308_ucChipNbr]].unLedFaultOpen |= (((uint16)CddMlcInd8308_aucResRdFault_List[CDD_LMM_N_TX_GetOpenShortStatus + 1u] << 8u) & 0xFF00u); // save the FAULTH value for the 8-15 LEDs CddMlcInd8308_asLedStatus_List[CddMlcInd8308_aucDevIdTableIdx_List[CddMlcInd8308_ucChipNbr]].unLedFaultShort = (((uint16)CddMlcInd8308_aucResRdFault_List[CDD_LMM_N_TX_GetOpenShortStatus + 2u] << 0u) & 0x00FFu); // save the FAULTL value for the 0-7 LEDs CddMlcInd8308_asLedStatus_List[CddMlcInd8308_aucDevIdTableIdx_List[CddMlcInd8308_ucChipNbr]].unLedFaultShort |= (((uint16)CddMlcInd8308_aucResRdFault_List[CDD_LMM_N_TX_GetOpenShortStatus + 3u] << 8u) & 0xFF00u); // save the FAULTH value for the 8-15 LEDs // CddMlcInd8308_ComStatus.aucCrcFltOccurrence_List[CddMlcInd8308_aucDevIdTableIdx_List[CddMlcInd8308_ucChipNbr]] = CddMlcInd8308_aucResRdFault_List[CDDMLCInd8308_N_TX_FAULT + 2u]; // save the CERRCNT value for the CRC Error Count #if (CddMlcInd8308_Cfg_Simulation == 1u) //compiler swicth in case developer hook is active; overwrite the values if (CddMlcGen_ulTesterHookActivation == MLC_Sim_ElectricalErrors) { /* CddMlcInd8308_sSimulationData.ucMlcChipNumber shall be in the range 0 ... CDDMLCInd8308_CHIPS*/ CddMlcInd8308_asLedStatus_List[CddMlcInd8308_aucDevIdTableIdx_List[CddMlcInd8308_sSimulationData.ucMlcChipNumber]].unLedFault = (((uint16)CddMlcInd8308_sSimulationData.ucLowByteFault << 0u) & 0x00FFu); // save the FAULTL value for the 0-7 LEDs CddMlcInd8308_asLedStatus_List[CddMlcInd8308_aucDevIdTableIdx_List[CddMlcInd8308_sSimulationData.ucMlcChipNumber]].unLedFault |= (((uint16)CddMlcInd8308_sSimulationData.ucHighByteFault << 8u) & 0x0F00u); // save the FAULTH value for the 8-11 LEDs } #endif } else { // Commands out of interest to be handled } } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_CommandFailed /// /// \descr The function updates the Mlc chips communication status /// /// \param none /// /// \return none //----------------------------------------------------------------------------- STATIC_AL void CddMlcInd8308_CommandFailed(uint8 ucCmdIdx) { // First commands are Widths if (ucCmdIdx < CddMlc8308_ConnectedDevices /*CDD_MLC_CHIPS*/) { // Error on device idx if (CddMlcInd8308_ComStatus.aucTimeoutCounter_List[ucCmdIdx] < CDDMLCInd8308_TIMEOUT_THD) { CddMlcInd8308_ComStatus.aucTimeoutCounter_List[ucCmdIdx]++; } else { //Add the Timeout flag for current Mlc chip CddMlcInd8308_ComStatus.ulMlcStatus |= ((uint32)1u << ucCmdIdx); CddMlcInd8308_boBusComError = ((CddMlcInd8308_ComStatus.ulMlcStatus & CddMlcInd8308_ulBusErrMask) == CddMlcInd8308_ulBusErrMask) ? TRUE : FALSE; } } else if ((uint8)CDDMLCInd8308_CMD_IDX_READ_ADCS == ucCmdIdx) { //Timeout not reached? if (CddMlcInd8308_ComStatus.aucTimeoutCounter_List[CddMlcInd8308_ucChipNbr] < CDDMLCInd8308_TIMEOUT_THD) { // Set ADC Quality flag to SignalNotAvailable - last value kept CddMlcInd8308_asAdcResult_List[CddMlcInd8308_ucChipNbr].eQlty = CDDMLCInd8308_QLTY_SNA; } else { // Set ADC Quality flag to invalid CddMlcInd8308_asAdcResult_List[CddMlcInd8308_ucChipNbr].eQlty = CDDMLCInd8308_QLTY_INVALID; } } else if ((uint8)CDDMLCInd8308_CMD_IDX_READ_FLTS == ucCmdIdx) { // Previous values are kept for Led Status and CRC Fault Occurence } else { // No action needed on other commands } } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_StepToNextChip /// /// \descr The function jump to the next Mlc chip for multiplexed commands /// /// \param none /// /// \return none //----------------------------------------------------------------------------- STATIC_AL void CddMlcInd8308_StepToNextChip(void) { #if (CFG_MAX_NO_OF_MLC > 1) // More than 1 Mlc? // Is next chip number in range? if ((CddMlcInd8308_ucChipNbr + 1u) < (CddMlc8308_ConnectedDevices /*CDD_MLC_CHIPS*/)) { // Jump to next chip CddMlcInd8308_ucChipNbr++; } else #endif { // Jump to first chip CddMlcInd8308_ucChipNbr = 0u; } } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_ScheduleCommands /// /// \descr The function prepare/update the Mlc command messages and then, /// add them to UART queue buffer and store their reference status /// /// \param none /// /// \return none //----------------------------------------------------------------------------- STATIC_AL void CddMlcInd8308_ScheduleCommands(void) { CddMlcInd8308_LastSystemMode = CddMlcInd8308_SystemMode; // Save the last system mode switch (CddMlcInd8308_SystemMode) { case CddMlcInd8308_SystemMode_CfgComm: CddMlcInd8308_Broadcast_CfgPWMs(); // INIT Pwm Config CddLmm_Broadcast_EnablePWMs_ALAD(); CddMlcInd8308_SystemMode = CddMlcInd8308_SystemMode_CfgChips; // Step to Chip Configuration Mode break; case CddMlcInd8308_SystemMode_CfgChips: // Configure Chip Settings CddLmm_Broadcast_EnableCfgAcess_ALAD(); // unlock LMM Must write 0x7078A0A8 after reset to enable config CddLmm_Broadcast_IOCfg_ALAD(); // config address adc quality coefficient CddLmm_Broadcast_SlewRate_ALAD(); // config LED slew rate threshold #if (CDD_LMM_WDT_ENABLED == CDD_LMM_FEATURE_ON) CddLmm_Broadcast_DisableWDT_ALAD(); //The lamp does not light up after communication is cut off #endif CddLmm_Broadcast_WDTimeout_ALAD(); // timeout config CddMlcInd8308_SystemMode = CddMlcInd8308_SystemMode_CfgPhases; // Step to Phase Shifts Configuration Mode break; case CddMlcInd8308_SystemMode_CfgPhases: // Configure Phase Shifts CddLmm_Broadcast_SARCfg_ALAD(); // config SRACfg regist CddLmm_Broadcast_SARInit_ALAD(); // config SARInit regist CddLmm_Broadcast_ADC_Ctrl_Init(); CddMlcInd8308_SystemMode = CddMlcInd8308_SystemMode_ExitFailSafe; // Step to LED Segments Configuration Mode break; case CddMlcInd8308_SystemMode_ExitFailSafe: #if (CDD_LMM_LH_POS_ENABLED == CDD_LMM_FEATURE_ON) CddLmm_Broadcast_ConfigDefwidth_ALAD(); //The lamp keep POS after communication is cut off (limp-home mode) #endif CddLmm_Broadcast_ExitLPH_ALAD(); // Exit LimpHome mode CddLmm_Broadcast_CfgBaudrateACK_ALAD(); // Enable respone CddMlcInd8308_SystemMode = CddMlcInd8308_SystemMode_Normal; // Step to cyclic mode break; case CddMlcInd8308_SystemMode_Normal: // Normal operation CddMlcInd8308_WritePWMs(CddMlc8308_ConnectedDevices); // Update PWM Control Commands CddMlcInd8308_MuxCommands(); // Update Multiplexed Commands break; default: // Do nothing on all other modes break; } } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_ResponseHandler /// /// \descr The function decodes the responses of the individual chip commands /// from previuos commands cycle based on last System Mode. /// /// \param none /// /// \return none //----------------------------------------------------------------------------- STATIC_AL void CddMlcInd8308_ResponseHandler(uint8 ucDevNbr) { uint32 ulTemp; uint16 *unSrcPtr, *unDestPtr; switch (CddMlcInd8308_LastSystemMode) { case CddMlcInd8308_SystemMode_CfgComm: // Set default communication Settings, CddMlcInd8308_ComStatus.aucMatrixIcID_List[ucDevNbr] = CddMlcInd8308_aucResponse_List[ucDevNbr][CDDMLCInd8308_N_TX_CFG_CHIP]; // Invalidate ICID byte after processing CddMlcInd8308_aucResponse_List[ucDevNbr][CDDMLCInd8308_N_TX_CFG_CHIP] = 0x00u; break; case CddMlcInd8308_SystemMode_CfgChips: // Configure Chip Settings, /* ulTemp = (CDDMLCInd8308_ACK_BYTE == CddMlcInd8308_aucResponse_List[ucDevNbr][CDDMLCInd8308_N_TX_CFG_CHIP]) ? 1u : 0u; // Mark the Chip Settings Acknowledge bit of current Mlc chip CddMlcInd8308_ComStatus.ulAckChipSetting |= (ulTemp << ucDevNbr); // no need to Invalidate ACK byte after processing, because separated buffers are used */ break; case CddMlcInd8308_SystemMode_CfgPhases: // Configure Phase Shifts, // ulTemp = ((CDDMLCInd8308_ACK_BYTE == CddMlcInd8308_aucResponse16BytesCfgPhases[ucDevNbr][CDDMLCInd8308_N_TX_CFG_16BYTES_PHASE]) && // (CDDMLCInd8308_ACK_BYTE == CddMlcInd8308_aucResponse4BytesCfgPhases[ucDevNbr][CDDMLCInd8308_N_TX_CFG_4BYTES_PHASE])) ? 1u : 0u; // Mark the Phase Shifts Acknowledge bit of current Mlc chip CddMlcInd8308_ComStatus.ulAckPhaseShifts |= (ulTemp << ucDevNbr); // no need to Invalidate ACK byte after processing, because separated buffers are used break; //case CddMlcInd8308_SystemMode_CfgLeds: // Configure LED Settings, // ulTemp = ((CDDMLCInd8308_ACK_BYTE == CddMlcInd8308_aucResponse2BytesCfgLeds[ucDevNbr][CDDMLCInd8308_N_TX_CFG_2BYTES_STRING]) && // (CDDMLCInd8308_ACK_BYTE == CddMlcInd8308_aucResponse16BytesCfgLeds[ucDevNbr][CDDMLCInd8308_N_TX_CFG_16BYTES_STRING])) ? 1u : 0u; // Mark the LED Segments Acknowledge bit of current Mlc chip // CddMlcInd8308_ComStatus.ulAckLedSegments |= (ulTemp << ucDevNbr); // no need to Invalidate ACK byte after processing, because separated buffers are used // break; case CddMlcInd8308_SystemMode_ExitFailSafe: // ulTemp = (CDDMLCInd8308_ACK_BYTE == CddMlcInd8308_aucResponse1ByteFailsafe[ucDevNbr][CDDMLCInd8308_N_TX_CFG_01BYTE_EXITFAILSAFE]) ? 1u : 0u; // Mark the Exit Failsafe Configuration bit of current Mlc chip CddMlcInd8308_ComStatus.ulAckExitFailsafe |= (ulTemp << ucDevNbr); // no need to Invalidate ACK byte after processing, because separated buffers are used break; case CddMlcInd8308_SystemMode_Normal: //If ACK Byte received on SET WIDTH for the current chip? ulTemp = ((/*CDDMLCInd8308_ACK_BYTE ==*/0x60 == (CddLmm_reSetPwm_List[ucDevNbr][CDD_LMM_N_TX_SetPWMs] & 0xE0))/*&& (CDDMLCInd8308_ACK_BYTE == CddMlcInd8308_aucResponse4BytesPWM[ucDevNbr][CDDMLCInd8308_N_TX_4BYTES_WIDTH])*/ ) ? 1u : 0u; if (ulTemp == 1u) //ACK was received { // Copy the acknowledged target segment value to the actual segment value unSrcPtr = CddMlcInd8308_aunTargetLedWidths_List[ucDevNbr]; unDestPtr = CddMlcInd8308_aunActualLedWidths_List[ucDevNbr]; // for each LED segment (16 segments) of the current chip *unDestPtr++ = *unSrcPtr++; *unDestPtr++ = *unSrcPtr++; *unDestPtr++ = *unSrcPtr++; *unDestPtr++ = *unSrcPtr++; *unDestPtr++ = *unSrcPtr++; *unDestPtr++ = *unSrcPtr++; *unDestPtr++ = *unSrcPtr++; *unDestPtr++ = *unSrcPtr++; *unDestPtr++ = *unSrcPtr++; *unDestPtr++ = *unSrcPtr++; *unDestPtr++ = *unSrcPtr++; *unDestPtr = *unSrcPtr; //Fastest method CddMlcInd8308_aboDeviceResponse[ucDevNbr] = TRUE; } else { // ACK Byte not received - last values are kept CddMlcInd8308_aboDeviceResponse[ucDevNbr] = FALSE; } // Invalidate ACK byte after processing CddLmm_reSetPwm_List[ucDevNbr][CDD_LMM_N_TX_SetPWMs] = 0xFFu; // CddMlcInd8308_aucResponse4BytesPWM[ucDevNbr][CDDMLCInd8308_N_TX_4BYTES_WIDTH] = 0x00u; //check CRC rate CddMlcInd8308_SDReadRespHandler(ucDevNbr); break; default: break; }//switch } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_SetTargetValues /// /// \descr Set the LED intensities for the current Mlc chip /// /// \param uint8 Mlc device number /// \param uint16 pointer to the desired PWM DutyCycles buffer /// /// \return none //--------------------------------------------------------------------------// PRQA S 1505 //The Function is called from external modules void CddMlcInd8308_SetTargetValues(uint8 ucDevNbr, uint16 unTargetWidths_List[]) // PRQA S 1505 //The Function is called from external modules { // PRQA S 1505 //The Function is called from external modules uint8 ucSegNbr; // Parse each LED segment for (ucSegNbr = 0u; ucSegNbr < CDDMLCInd8308_LEDS; ucSegNbr++) { // Store internally the Target Values CddMlcInd8308_aunTargetLedWidths_List[ucDevNbr][ucSegNbr] = unTargetWidths_List[ucSegNbr]; } } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_GetActualValues /// /// \descr Get the LED intensities for the current Mlc chip /// /// \param uint8 Mlc device number /// \param uint16 pointer to the desired PWM DutyCycles buffer /// /// \return pointer to the actual PWM DutyCycles buffer //--------------------------------------------------------------------------// PRQA S 1505 //The Function is called from external modules void CddMlcInd8308_GetActualValues(uint8 ucDevNbr, uint16 unActualWidths_List[]) { uint8 ucSegNbr; // Parse each LED segment for (ucSegNbr = 0u; ucSegNbr < CDDMLCInd8308_LEDS; ucSegNbr++) { // Read out the Actual Values unActualWidths_List[ucSegNbr] = CddMlcInd8308_aunActualLedWidths_List[ucDevNbr][ucSegNbr]; } } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_Add_CRC /// /// \descr The function calculates the CRC-16-IBM for the array provided in the /// parameter and adds it to the array /// /// \param uint8[] the data buffer for which the CRC must be calculated /// \param uint8 the length of the data buffer /// /// \return none //--------------------------------------------------------------------------// PRQA S 1505 // The function can be called from external module void CddMlcInd8308_Add_CRC(uint8* ucPtrData, uint8 ucLength) // PRQA S 1505 // The function can be called from external module { uint16 unCrc = 0u; uint16 wTableNo = 0; //Skip last two bytes reserved to 16bit CRC ucLength -= 3u; ucPtrData++; while (ucLength--) // PRQA S 3344 // Intentionally no modification of existing code { #if (CDDMLCInd8308_LOOKUP_TABLE_CRC == CDD_LMM_FEATURE_ON) // Fastest execution time using CRC16 LookUpTable wTableNo = (uint16)((unCrc & (uint16)0xff) ^ (uint16)(*ucPtrData & (uint8)0xff)); unCrc = ((unCrc >> 8) & 0x00ff); unCrc ^= CddMlcInd8308_unCrc16_List[wTableNo]; ucPtrData++; #else unCrc ^= *(ucPtrData++); // Faster execution time rather than using a for loop unCrc = (unCrc >> 1u) ^ ((unCrc & 1u) ? CDDMLCInd8308_CRC_POLY : 0u); unCrc = (unCrc >> 1u) ^ ((unCrc & 1u) ? CDDMLCInd8308_CRC_POLY : 0u); unCrc = (unCrc >> 1u) ^ ((unCrc & 1u) ? CDDMLCInd8308_CRC_POLY : 0u); unCrc = (unCrc >> 1u) ^ ((unCrc & 1u) ? CDDMLCInd8308_CRC_POLY : 0u); unCrc = (unCrc >> 1u) ^ ((unCrc & 1u) ? CDDMLCInd8308_CRC_POLY : 0u); unCrc = (unCrc >> 1u) ^ ((unCrc & 1u) ? CDDMLCInd8308_CRC_POLY : 0u); unCrc = (unCrc >> 1u) ^ ((unCrc & 1u) ? CDDMLCInd8308_CRC_POLY : 0u); unCrc = (unCrc >> 1u) ^ ((unCrc & 1u) ? CDDMLCInd8308_CRC_POLY : 0u); #endif } // load the CRC into the final 2 bytes of the packet *ucPtrData++ = (uint8)(unCrc & 0xFFu);// LSByte of CRC *ucPtrData = (uint8)(unCrc >> 8u); // MSByte of CRC } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_Broadcast_CfgPWMs_ALAD /// /// \descr The function computes two broadcast commands for basic communication: /// 1. /// 2. /// 3. /// /// \param none /// /// \return none //----------------------------------------------------------------------------- STATIC_AL void CddMlcInd8308_Broadcast_CfgPWMs(void) { //uint8 ucDevNbr; uint8 Datalength=CddLmm_DATA_LEN_1BYTES; //Function which interrogates the ICID register and retrieves the specific device identification number //for (ucDevNbr = 0; ucDevNbr < ucFamDevNbr /*CDD_MLC_CHIPS*/; ucDevNbr++) { CddLmm_ucConfigPWMs_List[0u] = CDD_LMM_SYNC_DATA; // Sync Field CddLmm_ucConfigPWMs_List[1u] = (uint8) ((Datalength <<3) | CddLmm_CMD_TYPE_BROADCAST_WRITE); // CMD Field (inclued:P1 1bit +P2 1bit + datalenth 3bit + CMD_CODE 3bit).CMD_CODE 3bit CddLmm_ucConfigPWMs_List[1u] = Parity_check(CddLmm_ucConfigPWMs_List[1u]); // CMD Field Parity_check CddLmm_ucConfigPWMs_List[2u] = (eBroadcastDevAddr<<3)|(uint8)(CDDMLCInd8308_PWM_CTRL >> 8);// DEVID Field (DEVID+REGADDR); CddLmm_ucConfigPWMs_List[3u] = (uint8)CDDMLCInd8308_PWM_CTRL; // REGADDR Field CddLmm_ucConfigPWMs_List[4u] = (uint8)((CDDMLCInd8308_CFG_PWMTICK << 4) | CDDMLCInd8308_CFG_PHASE_SHIFT); // Configure the Pulse Width Modulation Tick Period CddMlcInd8308_Add_CRC(CddLmm_ucConfigPWMs_List, CDDMLCInd8308_N_TX_ConfigPWMs); // calculate CRC bits //send break //CddLmm_SendBreak_ALAD(); // Add the Message to UART Queue and store the command status reference; (void)CddMlcInd8308Uart_AddMessage(CddLmm_ucConfigPWMs_List, CDDMLCInd8308_N_TX_ConfigPWMs, CddLmm_ucConfigPWMs_List, CDDMLCInd8308_N_TX_ConfigPWMs); } } //----------------------------------------------------------------------------- /// \brief CddLmm_Broadcast_EnablePWMs_ALAD /// /// \descr The function computes CHIP Enable PWM broadcast commands for basic communication: /// 1. Broadcast Write Enable PWMs register(0x110) /// 2. Sync Field(1Byte) + CMD Field(1Byte) +DEVID Field(1Byte) + REG ADDR(1Byte) + N Data Byte(s) + CRC16(2Bytes) /// \param None /// /// \return none //----------------------------------------------------------------------------- STATIC_AL void CddLmm_Broadcast_EnablePWMs_ALAD(void) { //uint8 ucDevNbr; uint8 Datalength=CddLmm_DATA_LEN_2BYTES; //Function which interrogates the ICID register and retrieves the specific device identification number //for (ucDevNbr = 0u; ucDevNbr < ucFamDevNbr /*CDD_MLC_CHIPS*/; ucDevNbr++) { CddLmm_ucCmdEnablePWMs_List[0u] = CDD_LMM_SYNC_DATA; // Sync Field CddLmm_ucCmdEnablePWMs_List[1u] = (uint8) ((Datalength <<3) | CddLmm_CMD_TYPE_BROADCAST_WRITE); // CMD Field (inclued:P1 1bit +P2 1bit + datalenth 3bit + CMD_CODE 3bit).CMD_CODE 3bit CddLmm_ucCmdEnablePWMs_List[1u] = Parity_check(CddLmm_ucCmdEnablePWMs_List[1u]); // CMD Field Parity_check CddLmm_ucCmdEnablePWMs_List[2u] = (eBroadcastDevAddr<<3)|(uint8)(CDDMLCInd8308_ENA_REQ_STS >> 8);// DEVID Field (DEVID+REGADDR); CddLmm_ucCmdEnablePWMs_List[3u] = (uint8)CDDMLCInd8308_ENA_REQ_STS; // REGADDR Field CddLmm_ucCmdEnablePWMs_List[4u] = (uint8)CDD_LMM_Enable_All_PWMS; CddLmm_ucCmdEnablePWMs_List[5u] = (uint8)(CDD_LMM_Enable_All_PWMS >> 8); CddMlcInd8308_Add_CRC(CddLmm_ucCmdEnablePWMs_List, CDD_LMM_N_TX_EnablePWMs); // calculate CRC bits //send break //CddLmm_SendBreak_ALAD(); // Add the Message to UART Queue and store the command status reference; (void)CddMlcInd8308Uart_AddMessage(CddLmm_ucCmdEnablePWMs_List, CDD_LMM_N_TX_EnablePWMs, CddLmm_ucCmdEnablePWMs_List, CDD_LMM_N_TX_EnablePWMs); } } //----------------------------------------------------------------------------- /// \brief CddLmm_Broadcast_CfgBaudrateACK_ALAD /// /// \descr The function config CHIP reply ACK broadcast commands for basic communication: /// 1. broadcast Enable PWMs register /// 2. Sync Field(1Byte) + CMD Field(1Byte) +DEVID Field(1Byte) + REG ADDR(1Byte) + N Data Byte(s) + CRC16(2Bytes) /// /// \param None /// /// \return none //----------------------------------------------------------------------------- STATIC_AL void CddLmm_Broadcast_CfgBaudrateACK_ALAD(void) { //uint8 ucDevNbr; uint8 Datalength=CddLmm_DATA_LEN_1BYTES; //Function which interrogates the ICID register and retrieves the specific device identification number //for (ucDevNbr = 0u; ucDevNbr < ucFamDevNbr /*CDD_MLC_CHIPS*/; ucDevNbr++) { CddLmm_ucALAD_CfgACK_List[0u] = CDD_LMM_SYNC_DATA; // Sync Field CddLmm_ucALAD_CfgACK_List[1u] = (uint8) ((Datalength <<3) | CddLmm_CMD_TYPE_BROADCAST_WRITE); // CMD Field (inclued:P1 1bit +P2 1bit + datalenth 3bit + CMD_CODE 3bit).CMD_CODE 3bit CddLmm_ucALAD_CfgACK_List[1u] = Parity_check(CddLmm_ucALAD_CfgACK_List[1u]); // CMD Field Parity_check CddLmm_ucALAD_CfgACK_List[2u] = (eBroadcastDevAddr<<3)|(uint8)(CDD_LMM_CTRL >> 8);// DEVID Field (DEVID+REGADDR); CddLmm_ucALAD_CfgACK_List[3u] = (uint8)CDD_LMM_CTRL; // REGADDR Field CddLmm_ucALAD_CfgACK_List[4u] = (uint8)CDD_LMM_CFG_ACK_BaudRate; CddMlcInd8308_Add_CRC(CddLmm_ucALAD_CfgACK_List, CDD_LMM_N_TX_CfgACK); // calculate CRC bits //send break //CddLmm_SendBreak_ALAD(); // Add the Message to UART Queue and store the command status reference; (void)CddMlcInd8308Uart_AddMessage(CddLmm_ucALAD_CfgACK_List, CDD_LMM_N_TX_CfgACK, CddLmm_ucALAD_CfgACK_List, CDD_LMM_N_TX_CfgACK); } } //test existed lmm uint8 iND8308X_CHECK_EXISTED_DEVICES(uint8 ucDevNbr) { uint8 dv_id; uint8 Datalength=CddLmm_DATA_LEN_4BYTES; CddMlcInd8308_aucCommand_List[0][0u] = CDD_LMM_SYNC_DATA; // Sync Field CddMlcInd8308_aucCommand_List[0][1u] = (uint8) ((Datalength <<3) | CddLmm_CMD_TYPE_READ); // CMD Field (inclued:P1 1bit +P2 1bit + datalenth 3bit + CMD_CODE 3bit).CMD_CODE 3bit CddMlcInd8308_aucCommand_List[0][1u] = Parity_check(CddMlcInd8308_aucCommand_List[0][1u]); // CMD Field Parity_check CddMlcInd8308_aucCommand_List[0][2u] = (ucDevNbr/*CddMlcInd8308_aucDevIdTable_List[ucDevNbr]*/<<3)|(uint8)(iND8308X_GET_DEVICE_NAME_ADDR >> 8);// DEVID Field (DEVID+REGADDR); CddMlcInd8308_aucCommand_List[0][3u] = (uint8)iND8308X_GET_DEVICE_NAME_ADDR; // REGADDR Field CddMlcInd8308_Add_CRC(CddMlcInd8308_aucCommand_List[0], CDD_LMM_N_TX_resRev); // calculate CRC bits //send break //CddLmm_SendBreak_ALAD(); // Add the Message to UART Queue and store the command status reference; CddMlcInd8308_psCommmandStatus[0] = CddMlcInd8308Uart_AddMessage(CddMlcInd8308_aucCommand_List[0], CDD_LMM_N_TX_resRev, CddMlcInd8308_aucResponse_List[0], CDD_LMM_N_RX_resRev); return TRUE; } //----------------------------------------------------------------------------- /// \brief CddLmm_Broadcast_EnableCfgAcess_ALAD /// /// \descr The function Enable config access: /// 1. broadcast CONFIG_EN 0x328 register /// 2. Must write 0x7078A0A8 after reset to enable config /// /// \param None /// /// \return none //----------------------------------------------------------------------------- STATIC_AL void CddLmm_Broadcast_EnableCfgAcess_ALAD(void) { //uint8 ucDevNbr; uint8 Datalength=CddLmm_DATA_LEN_4BYTES; //for (ucDevNbr = 0u; ucDevNbr < ucFamDevNbr /*CDD_MLC_CHIPS*/; ucDevNbr++) { CddLmm_ucAddressModeConfig_List[0u] = CDD_LMM_SYNC_DATA; // Sync Field CddLmm_ucAddressModeConfig_List[1u] = (uint8) ((Datalength <<3) | CddLmm_CMD_TYPE_BROADCAST_WRITE); // CMD Field (inclued:P1 1bit +P2 1bit + datalenth 3bit + CMD_CODE 3bit).CMD_CODE 3bit CddLmm_ucAddressModeConfig_List[1u] = Parity_check(CddLmm_ucAddressModeConfig_List[1u]); // CMD Field Parity_check CddLmm_ucAddressModeConfig_List[2u] = (eBroadcastDevAddr<<3)|(uint8)(CDD_LMM_Enable_CfgAcess >> 8); // DEVID Field (DEVID+REGADDR); CddLmm_ucAddressModeConfig_List[3u] = (uint8)CDD_LMM_Enable_CfgAcess; // REGADDR Field CddLmm_ucAddressModeConfig_List[4u] = (uint8)(CDD_LMM_ENABLE_CFG_FIXED >> 0); // data CddLmm_ucAddressModeConfig_List[5u] = (uint8)(CDD_LMM_ENABLE_CFG_FIXED >> 8); // data CddLmm_ucAddressModeConfig_List[6u] = (uint8)(CDD_LMM_ENABLE_CFG_FIXED >> 16); // data CddLmm_ucAddressModeConfig_List[7u] = (uint8)(CDD_LMM_ENABLE_CFG_FIXED >> 24); // data CddMlcInd8308_Add_CRC(CddLmm_ucAddressModeConfig_List, CDD_LMM_N_TX_AddressModeConfig); // calculate CRC bits //send break //CddLmm_SendBreak_ALAD(); // Add the Message to UART Queue and store the command status reference; (void)CddMlcInd8308Uart_AddMessage(CddLmm_ucAddressModeConfig_List, CDD_LMM_N_TX_AddressModeConfig, CddLmm_ucAddressModeConfig_List, CDD_LMM_N_TX_AddressModeConfig); } } //----------------------------------------------------------------------------- /// \brief CddLmm_Broadcast_IOCfg_ALAD /// /// \descr The function IO Configuration parameter: /// 1. broadcast IO_CFG 0x2C0 /// 2. Device Address Setting,When ADDR_MODE bit is set to 1,ADDR[2:0] are digital inputs(need tie to GND or VDD5P0), /// ADDR0 is the LSB of address bit, andthe network supports up to 8 devices in a single bus in this case. /// When ADDR_MODE bit is set to 0,up to 32 devices can be connected in a single bus in this mode. /// /// \param None /// /// \return none //----------------------------------------------------------------------------- STATIC_AL void CddLmm_Broadcast_IOCfg_ALAD(void) { //uint8 ucDevNbr; uint8 Datalength=CddLmm_DATA_LEN_1BYTES; //for (ucDevNbr = 0u; ucDevNbr < ucFamDevNbr /*CDD_MLC_CHIPS*/; ucDevNbr++) { CddLmm_ucIO_Config_List[0u] = CDD_LMM_SYNC_DATA; // Sync Field CddLmm_ucIO_Config_List[1u] = (uint8) ((Datalength <<3) | CddLmm_CMD_TYPE_BROADCAST_WRITE); // CMD Field (inclued:P1 1bit +P2 1bit + datalenth 3bit + CMD_CODE 3bit).CMD_CODE 3bit CddLmm_ucIO_Config_List[1u] = Parity_check(CddLmm_ucIO_Config_List[1u]); // CMD Field Parity_check CddLmm_ucIO_Config_List[2u] = (eBroadcastDevAddr<<3)|(uint8)(CDD_LMM_IO_CfgParameter >> 8); // DEVID Field (DEVID+REGADDR); CddLmm_ucIO_Config_List[3u] = (uint8)CDD_LMM_IO_CfgParameter; // REGADDR Field CddLmm_ucIO_Config_List[4u] = (uint8)CDD_LMM_ADDR_MODE; // data CddMlcInd8308_Add_CRC(CddLmm_ucIO_Config_List, CDD_LMM_N_TX_IO_Config); // calculate CRC bits //send break //CddLmm_SendBreak_ALAD(); // Add the Message to UART Queue and store the command status reference; (void)CddMlcInd8308Uart_AddMessage(CddLmm_ucIO_Config_List, CDD_LMM_N_TX_IO_Config, CddLmm_ucIO_Config_List, CDD_LMM_N_TX_IO_Config); } } //----------------------------------------------------------------------------- /// \brief CddLmm_Broadcast_Config_Addr_Mode /// /// \descr The function IO Configuration parameter: /// ---> need unlock register firstly /// 1. broadcast IO_CFG 0x2C0 /// 2. Device Address Setting,When ADDR_MODE bit is set to 1, ADDR[2:0] are digital inputs(need tie to GND or VDD5P0), /// ADDR0 is the LSB of address bit, andthe network supports up to 8 devices in a single bus in this case. /// When ADDR_MODE bit is set to 0,up to 32 devices can be connected in a single bus in this mode. /// /// \param None /// /// \return none //----------------------------------------------------------------------------- STATIC_AL void CddLmm_Broadcast_Config_Addr_Mode(void) { uint8 Datalength=CddLmm_DATA_LEN_4BYTES; // unlock register firstly CddLmm_ucInit_Config_List[0u] = CDD_LMM_SYNC_DATA; // Sync Field CddLmm_ucInit_Config_List[1u] = (uint8) ((Datalength <<3) | CddLmm_CMD_TYPE_BROADCAST_WRITE); // CMD Field (inclued:P1 1bit +P2 1bit + datalenth 3bit + CMD_CODE 3bit).CMD_CODE 3bit CddLmm_ucInit_Config_List[1u] = Parity_check(CddLmm_ucInit_Config_List[1u]); // CMD Field Parity_check CddLmm_ucInit_Config_List[2u] = (eBroadcastDevAddr<<3)|(uint8)(CDD_LMM_Enable_CfgAcess >> 8); // DEVID Field (DEVID+REGADDR); CddLmm_ucInit_Config_List[3u] = (uint8)CDD_LMM_Enable_CfgAcess; // REGADDR Field CddLmm_ucInit_Config_List[4u] = (uint8)(CDD_LMM_ENABLE_CFG_FIXED >> 0); // data CddLmm_ucInit_Config_List[5u] = (uint8)(CDD_LMM_ENABLE_CFG_FIXED >> 8); // data CddLmm_ucInit_Config_List[6u] = (uint8)(CDD_LMM_ENABLE_CFG_FIXED >> 16); // data CddLmm_ucInit_Config_List[7u] = (uint8)(CDD_LMM_ENABLE_CFG_FIXED >> 24); // data CddMlcInd8308_Add_CRC(CddLmm_ucInit_Config_List, CDD_LMM_N_TX_AddressModeConfig); // calculate CRC bits //send break //CddLmm_SendBreak_ALAD(CMD_BAUD_RATE_1M); // Add the Message to UART Queue; (void)CddMlcInd8308Uart_AddMessage(CddLmm_ucInit_Config_List, CDD_LMM_N_TX_AddressModeConfig, CddLmm_ucInit_Config_List, CDD_LMM_N_TX_AddressModeConfig); // boradcast to set addr mode register Datalength=CddLmm_DATA_LEN_1BYTES; CddLmm_ucAddrMode_Config_List[0u] = CDD_LMM_SYNC_DATA; // Sync Field CddLmm_ucAddrMode_Config_List[1u] = (uint8) ((Datalength <<3) | CddLmm_CMD_TYPE_BROADCAST_WRITE); // CMD Field (inclued:P1 1bit +P2 1bit + datalenth 3bit + CMD_CODE 3bit).CMD_CODE 3bit CddLmm_ucAddrMode_Config_List[1u] = Parity_check(CddLmm_ucAddrMode_Config_List[1u]); // CMD Field Parity_check CddLmm_ucAddrMode_Config_List[2u] = (eBroadcastDevAddr<<3)|(uint8)(CDD_LMM_IO_CfgParameter >> 8); // DEVID Field (DEVID+REGADDR); CddLmm_ucAddrMode_Config_List[3u] = (uint8)CDD_LMM_IO_CfgParameter; // REGADDR Field CddLmm_ucAddrMode_Config_List[4u] = (uint8)CDD_LMM_ADDR_MODE; // data CddMlcInd8308_Add_CRC(CddLmm_ucAddrMode_Config_List, CDD_LMM_N_TX_IO_Config); // calculate CRC bits //send break //CddLmm_SendBreak_ALAD(CMD_BAUD_RATE_1M); // Add the Message to UART Queue; (void)CddMlcInd8308Uart_AddMessage(CddLmm_ucAddrMode_Config_List, CDD_LMM_N_TX_IO_Config, \ CddLmm_ucAddrMode_Config_List, CDD_LMM_N_TX_IO_Config); } //----------------------------------------------------------------------------- /// \brief CddLmm_Broadcast_SlewRate_ALAD /// /// \descr The function config LED slew rate threshold: /// 1. broadcast SR_CFG 0x33D register /// /// \param None /// /// \return none //----------------------------------------------------------------------------- STATIC_AL void CddLmm_Broadcast_SlewRate_ALAD(void) { //uint8 ucDevNbr; uint8 Datalength=CddLmm_DATA_LEN_1BYTES; //for (ucDevNbr = 0u; ucDevNbr < ucFamDevNbr /*CDD_MLC_CHIPS*/; ucDevNbr++) { CddLmm_ucSlewRate_List[0u] = CDD_LMM_SYNC_DATA; // Sync Field CddLmm_ucSlewRate_List[1u] = (uint8) ((Datalength <<3) | CddLmm_CMD_TYPE_BROADCAST_WRITE); // CMD Field (inclued:P1 1bit +P2 1bit + datalenth 3bit + CMD_CODE 3bit).CMD_CODE 3bit CddLmm_ucSlewRate_List[1u] = Parity_check(CddLmm_ucSlewRate_List[1u]); // CMD Field Parity_check CddLmm_ucSlewRate_List[2u] = (eBroadcastDevAddr<<3)|(uint8)(CDD_LMM_OV_SR_CFG >> 8);// DEVID Field (DEVID+REGADDR); CddLmm_ucSlewRate_List[3u] = (uint8)CDD_LMM_OV_SR_CFG; // REGADDR Field CddLmm_ucSlewRate_List[4u] = (uint8)CDD_LMM_SLEWRATE_CFG; // data CddMlcInd8308_Add_CRC(CddLmm_ucSlewRate_List, CDD_LMM_N_TX_SlewRate); // calculate CRC bits //send break //CddLmm_SendBreak_ALAD(); // Add the Message to UART Queue and store the command status reference; (void)CddMlcInd8308Uart_AddMessage(CddLmm_ucSlewRate_List, CDD_LMM_N_TX_SlewRate, CddLmm_ucSlewRate_List, CDD_LMM_N_TX_SlewRate); } } //----------------------------------------------------------------------------- /// \brief CddLmm_Broadcast_DisableWDT_ALAD /// /// \descr The function config CHIP Disable watch dog broadcast commands for basic communication: /// 1. broadcast Enable PWMs register /// 2. Sync Field(1Byte) + CMD Field(1Byte) +DEVID Field(1Byte) + REG ADDR(1Byte) + N Data Byte(s) + CRC16(2Bytes) /// \param None /// /// \return none //----------------------------------------------------------------------------- STATIC_AL void CddLmm_Broadcast_DisableWDT_ALAD(void) { //uint8 ucDevNbr; uint8 Datalength=CddLmm_DATA_LEN_1BYTES; //for (ucDevNbr = 0u; ucDevNbr < ucFamDevNbr /*CDD_MLC_CHIPS*/; ucDevNbr++) { CddLmm_ucDisableWDT_List[0u] = CDD_LMM_SYNC_DATA; // Sync Field CddLmm_ucDisableWDT_List[1u] = (uint8) ((Datalength <<3) | CddLmm_CMD_TYPE_BROADCAST_WRITE); // CMD Field (inclued:P1 1bit +P2 1bit + datalenth 3bit + CMD_CODE 3bit).CMD_CODE 3bit CddLmm_ucDisableWDT_List[1u] = Parity_check(CddLmm_ucDisableWDT_List[1u]); // CMD Field Parity_check CddLmm_ucDisableWDT_List[2u] = (eBroadcastDevAddr<<3)|(uint8)(CDD_LMM_Watchdog_CTRL >> 8);// DEVID Field (DEVID+REGADDR); CddLmm_ucDisableWDT_List[3u] = (uint8)CDD_LMM_Watchdog_CTRL; // REGADDR Field CddLmm_ucDisableWDT_List[4u] = (uint8)CDD_LMM_DISABLE_WATCHDOG; // data CddMlcInd8308_Add_CRC(CddLmm_ucDisableWDT_List, CDD_LMM_N_TX_DisableWDT); // calculate CRC bits //send break //CddLmm_SendBreak_ALAD(); // Add the Message to UART Queue and store the command status reference; (void)CddMlcInd8308Uart_AddMessage(CddLmm_ucDisableWDT_List, CDD_LMM_N_TX_DisableWDT, CddLmm_ucDisableWDT_List, CDD_LMM_N_TX_DisableWDT); } } //----------------------------------------------------------------------------- /// \brief CddLmm_Broadcast_WDTimeout_ALAD /// /// \descr The function config CHIP watch dog timeout broadcast commands for basic communication: /// 1. broadcast Enable PWMs register /// /// \param None /// /// \return none //----------------------------------------------------------------------------- STATIC_AL void CddLmm_Broadcast_WDTimeout_ALAD(void) { //uint8 ucDevNbr; uint8 Datalength=CddLmm_DATA_LEN_2BYTES; //for (ucDevNbr = 0u; ucDevNbr < ucFamDevNbr /*CDD_MLC_CHIPS*/; ucDevNbr++) { CddLmm_ucWDTimeout_List[0u] = CDD_LMM_SYNC_DATA; // Sync Field CddLmm_ucWDTimeout_List[1u] = (uint8) ((Datalength <<3) | CddLmm_CMD_TYPE_BROADCAST_WRITE); // CMD Field (inclued:P1 1bit +P2 1bit + datalenth 3bit + CMD_CODE 3bit).CMD_CODE 3bit CddLmm_ucWDTimeout_List[1u] = Parity_check(CddLmm_ucWDTimeout_List[1u]); // CMD Field Parity_check CddLmm_ucWDTimeout_List[2u] = (eBroadcastDevAddr<<3)|(uint8)(CDD_LMM_CP_CTRL >> 8);// DEVID Field (DEVID+REGADDR); CddLmm_ucWDTimeout_List[3u] = (uint8)CDD_LMM_CP_CTRL; // REGADDR Field CddLmm_ucWDTimeout_List[4u] = (uint8)CDD_LMM_CFG_WATCHDOG_TIMEOUT; // data CddLmm_ucWDTimeout_List[5u] = (uint8)CDD_LMM_WATCHDOG_UPDATE; // data CddMlcInd8308_Add_CRC(CddLmm_ucWDTimeout_List, CDD_LMM_N_TX_WDTimeout); // calculate CRC bits //send break //CddLmm_SendBreak_ALAD(); // Add the Message to UART Queue and store the command status reference; (void)CddMlcInd8308Uart_AddMessage(CddLmm_ucWDTimeout_List, CDD_LMM_N_TX_WDTimeout, CddLmm_ucWDTimeout_List, CDD_LMM_N_TX_WDTimeout); } } //----------------------------------------------------------------------------- /// \brief CddLmm_Broadcast_ConfigDefwidth_ALAD /// /// \descr The function config CHIP default PWM width in LimpHome by broadcast commands for basic communication: /// 1. broadcast PWM default width in LimpHome 0x164~0x169 register /// /// \param None /// /// \return none //----------------------------------------------------------------------------- STATIC_AL void CddLmm_Broadcast_ConfigDefwidth_ALAD(void) { //uint8 ucDevNbr; uint8 Datalength=CddLmm_DATA_LEN_4BYTES; //for (ucDevNbr = 0u; ucDevNbr < ucFamDevNbr /*CDD_MLC_CHIPS*/; ucDevNbr++) { CddLmm_ucConfigDefwidth1_List[0u] = CDD_LMM_SYNC_DATA; // Sync Field CddLmm_ucConfigDefwidth1_List[1u] = (uint8) ((Datalength << 3) | CddLmm_CMD_TYPE_BROADCAST_WRITE); // CMD Field (inclued:P1 1bit +P2 1bit + datalenth 3bit + CMD_CODE 3bit).CMD_CODE 3bit CddLmm_ucConfigDefwidth1_List[1u] = Parity_check(CddLmm_ucConfigDefwidth1_List[1u]); // CMD Field Parity_check CddLmm_ucConfigDefwidth1_List[2u] = (eBroadcastDevAddr << 3)|(uint8)(CDD_LMM_DEFWIDTH_1_0 >> 8); // DEVID Field (DEVID+REGADDR); CddLmm_ucConfigDefwidth1_List[3u] = (uint8)CDD_LMM_DEFWIDTH_1_0; // REGADDR Field CddLmm_ucConfigDefwidth1_List[4u] = (uint8)((CDD_LMM_DEFWIDTH_273 << 4) | CDD_LMM_DEFWIDTH_273); // data CddLmm_ucConfigDefwidth1_List[5u] = (uint8)((CDD_LMM_DEFWIDTH_273 << 4) | CDD_LMM_DEFWIDTH_273); // data CddLmm_ucConfigDefwidth1_List[6u] = (uint8)((CDD_LMM_DEFWIDTH_273 << 4) | CDD_LMM_DEFWIDTH_273); // data CddLmm_ucConfigDefwidth1_List[7u] = (uint8)((CDD_LMM_DEFWIDTH_273 << 4) | CDD_LMM_DEFWIDTH_273); // data CddMlcInd8308_Add_CRC(CddLmm_ucConfigDefwidth1_List, CDD_LMM_N_TX_ConfigDefwidth1); // calculate CRC bits // Add the Message to UART Queue; (void)CddMlcInd8308Uart_AddMessage(CddLmm_ucConfigDefwidth1_List, CDD_LMM_N_TX_ConfigDefwidth1, CddLmm_ucConfigDefwidth1_List, CDD_LMM_N_TX_ConfigDefwidth1); } Datalength=CddLmm_DATA_LEN_2BYTES; //for (ucDevNbr = 0u; ucDevNbr < ucFamDevNbr /*CDD_MLC_CHIPS*/; ucDevNbr++) { CddLmm_ucConfigDefwidth2_List[0u] = CDD_LMM_SYNC_DATA; // Sync Field CddLmm_ucConfigDefwidth2_List[1u] = (uint8) ((Datalength << 3) | CddLmm_CMD_TYPE_BROADCAST_WRITE); // CMD Field (inclued:P1 1bit +P2 1bit + datalenth 3bit + CMD_CODE 3bit).CMD_CODE 3bit CddLmm_ucConfigDefwidth2_List[1u] = Parity_check(CddLmm_ucConfigDefwidth2_List[1u]); // CMD Field Parity_check CddLmm_ucConfigDefwidth2_List[2u] = (eBroadcastDevAddr << 3)|(uint8)(CDD_LMM_DEFWIDTH_9_8 >> 8); // DEVID Field (DEVID+REGADDR); CddLmm_ucConfigDefwidth2_List[3u] = (uint8)CDD_LMM_DEFWIDTH_9_8; // REGADDR Field CddLmm_ucConfigDefwidth2_List[4u] = (uint8)((CDD_LMM_DEFWIDTH_273 << 4) | CDD_LMM_DEFWIDTH_273); // data CddLmm_ucConfigDefwidth2_List[5u] = (uint8)((CDD_LMM_DEFWIDTH_273 << 4) | CDD_LMM_DEFWIDTH_273); // data CddMlcInd8308_Add_CRC(CddLmm_ucConfigDefwidth2_List, CDD_LMM_N_TX_ConfigDefwidth2); // calculate CRC bits // Add the Message to UART Queue; (void)CddMlcInd8308Uart_AddMessage(CddLmm_ucConfigDefwidth2_List, CDD_LMM_N_TX_ConfigDefwidth2, CddLmm_ucConfigDefwidth2_List, CDD_LMM_N_TX_ConfigDefwidth2); } } //----------------------------------------------------------------------------- /// \brief CddLmm_Broadcast_ExitLPH_ALAD /// /// \descr The function config CHIP Exit LimpHome broadcast commands for basic communication: /// 1. broadcast Exit LimpHome 0x334 register /// /// \param None /// /// \return none //----------------------------------------------------------------------------- STATIC_AL void CddLmm_Broadcast_ExitLPH_ALAD(void) { //uint8 ucDevNbr; uint8 Datalength=CddLmm_DATA_LEN_4BYTES; //for (ucDevNbr = 0u; ucDevNbr < ucFamDevNbr /*CDD_MLC_CHIPS*/; ucDevNbr++) { CddLmm_ucExitLimpHome_List[0u] = CDD_LMM_SYNC_DATA; // Sync Field CddLmm_ucExitLimpHome_List[1u] = (uint8) ((Datalength <<3) | CddLmm_CMD_TYPE_BROADCAST_WRITE); // CMD Field (inclued:P1 1bit +P2 1bit + datalenth 3bit + CMD_CODE 3bit).CMD_CODE 3bit CddLmm_ucExitLimpHome_List[1u] = Parity_check(CddLmm_ucExitLimpHome_List[1u]); // CMD Field Parity_check CddLmm_ucExitLimpHome_List[2u] = (eBroadcastDevAddr<<3)|(uint8)(CDD_LMM_LHM_DEACTIVE >> 8); // DEVID Field (DEVID+REGADDR); CddLmm_ucExitLimpHome_List[3u] = (uint8)CDD_LMM_LHM_DEACTIVE; // REGADDR Field CddLmm_ucExitLimpHome_List[4u] = (uint8)(CDD_LMM_DEACTIVE_LHM_CODE >> 0); // data CddLmm_ucExitLimpHome_List[5u] = (uint8)(CDD_LMM_DEACTIVE_LHM_CODE >> 8); // data CddLmm_ucExitLimpHome_List[6u] = 0x1;// (uint8)(CDD_LMM_DEACTIVE_LHM >> 0); // data CddLmm_ucExitLimpHome_List[7u] = 0x0;// (uint8)(CDD_LMM_DEACTIVE_LHM >> 8); // data CddMlcInd8308_Add_CRC(CddLmm_ucExitLimpHome_List, CDD_LMM_N_TX_ExitLimpHome); // calculate CRC bits //send break //CddLmm_SendBreak_ALAD(); // Add the Message to UART Queue and store the command status reference; (void)CddMlcInd8308Uart_AddMessage(CddLmm_ucExitLimpHome_List, CDD_LMM_N_TX_ExitLimpHome, CddLmm_ucExitLimpHome_List, CDD_LMM_N_TX_ExitLimpHome); } } //----------------------------------------------------------------------------- /// \brief CddLmm_Broadcast_SARCfg_ALAD /// /// \descr The function config CHIP start SAR Register broadcast commands for basic communication: /// 1. broadcast Start SAR 0x280~0x288 register /// /// \param None /// /// /// \return none //----------------------------------------------------------------------------- STATIC_AL void CddLmm_Broadcast_SARCfg_ALAD(void) { //uint8 ucDevNbr; uint8 Datalength = CddLmm_DATA_LEN_12BYTES; //ADC register configuration start.Default configuration//280 register uint32 Temp_SAR_CTRL = (CDD_LMM_Enable << 0) + (CDD_LMM_Enable << 1) + (CDD_LMM_Enable << 2) + (CDD_LMM_Enable << 3) + (CDD_LMM_Enable << 9) + (CDD_LMM_AVER_SEL4 << 12) + (CDD_LMM_Enable << 14); //284 register uint32 Temp_SAR_CFGL = (CDD_LMM_ADC_VREF_SEL2 << 0) + (CDD_LMM_SAR_INPUT_GAIN1 << 2) + (CDD_LMM_SEL_OT_DBNC_128us << 10) + (CDD_LMM_SAMPCYC_7Cycle << 12) + (CDD_LMM_TRIG_DLY << 16); //288 register uint32 Temp_SAR_CHAN_CONF = (CDD_LMM_CHAN_SEQ_NUM3 << 0) + (CDD_LMM_SEL1 << 4) + (CDD_LMM_SEL2 << 8) + (CDD_LMM_SEL3 << 12) + (CDD_LMM_SEL4 << 16); //ADC register configuration end //for (ucDevNbr = 0u; ucDevNbr < ucFamDevNbr /*CDD_MLC_CHIPS*/; ucDevNbr++) { CddLmm_ucSAR_List280[0u] = CDD_LMM_SYNC_DATA; // Sync Field CddLmm_ucSAR_List280[1u] = (uint8) ((Datalength <<3) | CddLmm_CMD_TYPE_BROADCAST_WRITE); // CMD Field (inclued:P1 1bit +P2 1bit + datalenth 3bit + CMD_CODE 3bit).CMD_CODE 3bit CddLmm_ucSAR_List280[1u] = Parity_check(CddLmm_ucSAR_List280[1u]); // CMD Field Parity_check CddLmm_ucSAR_List280[2u] = (eBroadcastDevAddr<<3)|(uint8)(CDD_LMM_SAR_CTRL >> 8); // DEVID Field (DEVID+REGADDR); CddLmm_ucSAR_List280[3u] = (uint8)CDD_LMM_SAR_CTRL; // REGADDR Field CddLmm_ucSAR_List280[4u] = (uint8)(Temp_SAR_CTRL >> 0); // data CddLmm_ucSAR_List280[5u] = (uint8)(Temp_SAR_CTRL >> 8); // data CddLmm_ucSAR_List280[6u] = (uint8)(Temp_SAR_CTRL >> 16); // data CddLmm_ucSAR_List280[7u] = (uint8)(Temp_SAR_CTRL >> 24); // data CddLmm_ucSAR_List280[8u] = (uint8)(Temp_SAR_CFGL >> 0); // data CddLmm_ucSAR_List280[9u] = (uint8)(Temp_SAR_CFGL >> 8); // data CddLmm_ucSAR_List280[10u] = (uint8)(Temp_SAR_CFGL >> 16); // data CddLmm_ucSAR_List280[11u] = (uint8)(Temp_SAR_CFGL >> 24); // data CddLmm_ucSAR_List280[12u] = (uint8)(Temp_SAR_CHAN_CONF >> 0); // data CddLmm_ucSAR_List280[13u] = (uint8)(Temp_SAR_CHAN_CONF >> 8); // data CddLmm_ucSAR_List280[14u] = (uint8)(Temp_SAR_CHAN_CONF >> 16); // data CddLmm_ucSAR_List280[15u] = (uint8)(Temp_SAR_CHAN_CONF >> 24); // data CddMlcInd8308_Add_CRC(CddLmm_ucSAR_List280, CDD_LMM_N_TX_SAR); // calculate CRC bits //send break //CddLmm_SendBreak_ALAD(); // Add the Message to UART Queue and store the command status reference; (void)CddMlcInd8308Uart_AddMessage(CddLmm_ucSAR_List280, CDD_LMM_N_TX_SAR, CddLmm_ucSAR_List280, CDD_LMM_N_TX_SAR); } } //----------------------------------------------------------------------------- /// \brief CddLmm_Broadcast_SARInit_ALAD /// /// \descr The function config CHIP SAR Interrupts for basic communication: /// 1. broadcast SAR Init 0x2A0 register /// 2. Contains the enable, status and clear for the SAR interrupt sources. /// /// \param None /// /// \return none //----------------------------------------------------------------------------- STATIC_AL void CddLmm_Broadcast_SARInit_ALAD(void) { //uint8 ucDevNbr; uint8 Datalength =CddLmm_DATA_LEN_2BYTES; //for (ucDevNbr = 0u; ucDevNbr < ucFamDevNbr /*CDD_MLC_CHIPS*/; ucDevNbr++) { CddLmm_ucStartADC_List2A0[0u] = CDD_LMM_SYNC_DATA; // Sync Field CddLmm_ucStartADC_List2A0[1u] = (uint8) ((Datalength <<3) | CddLmm_CMD_TYPE_BROADCAST_WRITE); // CMD Field (inclued:P1 1bit +P2 1bit + datalenth 3bit + CMD_CODE 3bit).CMD_CODE 3bit CddLmm_ucStartADC_List2A0[1u] = Parity_check(CddLmm_ucStartADC_List2A0[1u]); // CMD Field Parity_check CddLmm_ucStartADC_List2A0[2u] = (eBroadcastDevAddr<<3)|(uint8)(CDD_LMM_FLAG_SAR_INT >> 8); // DEVID Field (DEVID+REGADDR); CddLmm_ucStartADC_List2A0[3u] = (uint8)CDD_LMM_FLAG_SAR_INT; // REGADDR Field REGADDR:0x2A0 CddLmm_ucStartADC_List2A0[4u] = (uint8)0x02; // data CddLmm_ucStartADC_List2A0[5u] = (uint8)0x03; // data CddMlcInd8308_Add_CRC(CddLmm_ucStartADC_List2A0, CDD_LMM_N_TX_StartADC2A0); // calculate CRC bits //send break //CddLmm_SendBreak_ALAD(); // Add the Message to UART Queue and store the command status reference; (void)CddMlcInd8308Uart_AddMessage(CddLmm_ucStartADC_List2A0, CDD_LMM_N_TX_StartADC2A0, CddLmm_ucStartADC_List2A0, CDD_LMM_N_TX_StartADC2A0); } } //----------------------------------------------------------------------------- /// \brief CddLmm_Broadcast_ADC_Ctrl_Init /// /// \descr The function config CHIP ADC address initialization broadcast commands for basic communication: /// 1. broadcast config ADC 0x280 register /// /// \param None /// /// \return none //----------------------------------------------------------------------------- STATIC_AL void CddLmm_Broadcast_ADC_Ctrl_Init(void) { uint8 ucDevNbr; uint8 Datalength = CddLmm_DATA_LEN_12BYTES; //for (ucDevNbr = 0u; ucDevNbr < ucFamDevNbr /*CDD_MLC_CHIPS*/; ucDevNbr++) { CddLmm_ucADC_Address_list[0u] = CDD_LMM_SYNC_DATA; // Sync Field CddLmm_ucADC_Address_list[1u] = (uint8) ((Datalength <<3) | CddLmm_CMD_TYPE_BROADCAST_WRITE); // CMD Field (inclued:P1 1bit +P2 1bit + datalenth 3bit + CMD_CODE 3bit).CMD_CODE 3bit CddLmm_ucADC_Address_list[1u] = Parity_check(CddLmm_ucADC_Address_list[1u]); // CMD Field Parity_check CddLmm_ucADC_Address_list[2u] = (eBroadcastDevAddr<<3)|(uint8)(CDD_LMM_SAR_CTRL >> 8); // DEVID Field (DEVID+REGADDR); CddLmm_ucADC_Address_list[3u] = (uint8)CDD_LMM_SAR_CTRL; // REGADDR Field REGADDR:0x280 CddLmm_ucADC_Address_list[4u] = CDD_LMM_SAR_AFE_EN|CDD_LMM_SAR_PREAMP_EN|CDD_LMM_SAR_ENA_REQ; // adc pre-amp enable.|SAR ADC Enable. CddLmm_ucADC_Address_list[5u] = CDD_LMM_SAR_CONTIOUS|CDD_LMM_SAR_AUTO_EN|((uint8)iND8308X_SAR_CLK_3P3M<<2)|((uint8)iND8308X_SAR_ADC_AVER_8<<4)|CDD_LMM_SAR_AVER_EN; CddLmm_ucADC_Address_list[6u] = 0x00; CddLmm_ucADC_Address_list[7u] = 0x00; CddLmm_ucADC_Address_list[8u] = (((uint8)iND8308X_ADC_GAIN_31_32<<2) | (uint8)iND8308X_ADC_VREF_VDD5P0); CddLmm_ucADC_Address_list[9u] = ((0x07<<4)|((uint8)iND8308X_OT_DEBOUNCE_128US<<2)); //sampling time range: 1~15, 7 used in demo CddLmm_ucADC_Address_list[10u] = 0x15; //delay clock range: 1~255 CddLmm_ucADC_Address_list[11u] = (uint8)iND8308X_OT_160_DEGREE; CddLmm_ucADC_Address_list[12u] = (uint8)((iND8308X_CHANNEL_PAD_ADC1<<4)|iND8308X_CH1_CH2_CH3_CH4); CddLmm_ucADC_Address_list[13u] = (uint8)((iND8308X_CHANNEL_ADC_TSP<<4)|iND8308X_CHANNEL_PAD_ADC2); CddLmm_ucADC_Address_list[14u] = (uint8)(iND8308X_CHANNEL_ADC_TSN); CddLmm_ucADC_Address_list[15u] = 0x00; CddMlcInd8308_Add_CRC(CddLmm_ucADC_Address_list, CDD_LMM_N_TX_ADC_Address); // calculate CRC bits //send break //CddLmm_SendBreak_ALAD(); // Add the Message to UART Queue and store the command status reference; (void)CddMlcInd8308Uart_AddMessage(CddLmm_ucADC_Address_list, CDD_LMM_N_TX_ADC_Address, CddLmm_ucADC_Address_list, CDD_LMM_N_TX_ADC_Address); } Datalength = CddLmm_DATA_LEN_1BYTES; for (ucDevNbr = 0u; ucDevNbr < CddMlc8308_ConnectedDevices /*CDD_MLC_CHIPS*/; ucDevNbr++) { CddLmm_ucStartADCconvert_List[ucDevNbr][0u] = CDD_LMM_SYNC_DATA; // Sync Field CddLmm_ucStartADCconvert_List[ucDevNbr][1u] = (uint8) ((Datalength <<3) | CddLmm_CMD_TYPE_WRITE); // CMD Field (inclued:P1 1bit +P2 1bit + datalenth 3bit + CMD_CODE 3bit).CMD_CODE 3bit CddLmm_ucStartADCconvert_List[ucDevNbr][1u] = Parity_check(CddLmm_ucStartADCconvert_List[ucDevNbr][1u]); // CMD Field Parity_check CddLmm_ucStartADCconvert_List[ucDevNbr][2u] = (CddMlcInd8308_aucDevIdTable_List[ucDevNbr]<<3)|(uint8)(CDD_LMM_SAR_CTRL >> 8);// DEVID Field (DEVID+REGADDR); CddLmm_ucStartADCconvert_List[ucDevNbr][3u] = (uint8)CDD_LMM_SAR_CTRL; // REGADDR Field REGADDR:0x280 // adc pre-amp enable.|SAR ADC Enable. CddLmm_ucStartADCconvert_List[ucDevNbr][4u] = CDD_LMM_SAR_CONVERT| CDD_LMM_SAR_AFE_EN|CDD_LMM_SAR_PREAMP_EN|CDD_LMM_SAR_ENA_REQ; CddMlcInd8308_Add_CRC(CddLmm_ucStartADCconvert_List[ucDevNbr], CDD_LMM_N_TX_StartADCconvert); // calculate CRC bits //send break //CddLmm_SendBreak_ALAD(); // Add the Message to UART Queue and store the command status reference; (void)CddMlcInd8308Uart_AddMessage(CddLmm_ucStartADCconvert_List[ucDevNbr], CDD_LMM_N_TX_StartADCconvert, CddLmm_reStartADCconvert_List[ucDevNbr], CDD_LMM_N_RX_StartADCconvert); } } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_ExitFailSafe /// /// \descr This command write a '1' to the FS_PIN bit to exit /// failsafe(pre comms) mode and begin normal operation.This /// would typically be done after power is applied and an operation /// configuration has been loaded from the UART or MTP. /// Also, write a 1' to the CLKDIV2 bit to divide the system clock /// by two for 500kbps /// /// \param - /// /// \return STATIC_AL void //----------------------------------------------------------------------------- STATIC_AL void CddMlcInd8308_ExitFailSafe(void) { } //----------------------------------------------------------------------------- /// \brief CddLmm_RegulateIntensity_ALAD /// /// \descr The function regulate intensity. /// /// \param intensity intensity of channel from application [0, 255] /// /// \return target duty cycle[0, 4095] //----------------------------------------------------------------------------- STATIC_AL uint16 CddLmm_RegulateIntensity_ALAD(uint8 Device,uint8 chanle,uint16 intensity) { uint16 duty ; boolean CddLmm_Charging_IntensityUpdate = FALSE; duty = 0; duty = CddLmm_Intensity4095Duty(intensity); //Brightness 65535 converted to 4095 if (duty <= CDD_LMM_MIN_PWM_THD_ALAD) duty = CDD_LMM_MIN_PWM_VAL; //Minimum brightness if (duty >= CDD_LMM_MAX_PWM_THD_ALAD) duty = CDD_LMM_PHASE_MAX_ALAD; //Maximum brightness return duty; } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_WritePWMs /// /// \descr The function computes the width write commands for each Mlc Chip /// and add them to UART queue buffer and store their reference status. /// /// \param none /// /// \return none //----------------------------------------------------------------------------- STATIC_AL void CddMlcInd8308_WritePWMs(uint8 ucFamDevNbr) { uint8 ucDevNbr; // chip number uint8 Datalength = CddLmm_DATA_LEN_25BYTES; // Data lenth uint8 CMD_Field; // CMD Field uint8 ucIdx; // chip channels uint8 *ucDesPtr; // pointer to CddLmm_ucCommand_List uint16 *unSrcPtr; // pointer to 10-bit PWM widths values uint16 unSrcPWM[CDDMLCInd8308_LEDS]; // pointer to 10-bit target PWM widths values static boolean bSwitchFlag = FALSE; CMD_Field = (uint8) ((Datalength <<3) | CddLmm_CMD_TYPE_WRITE); // CMD Field (inclued:P1 1bit +P2 1bit + datalenth 3bit + CMD_CODE 3bit).CMD_CODE 3bit CMD_Field = Parity_check(CMD_Field); // CMD Field Parity_check for (ucDevNbr = 0u; ucDevNbr < ucFamDevNbr; ucDevNbr++) //for each Mlc chip of the Matrix { #if 0 // @jiangtao test code should deleta for (ucIdx = 0; ucIdx < (CDDMLCInd8308_LEDS/2); ucIdx++) { // Store internally the Target Values CddMlcInd8308_aunTargetLedWidths_List[CddMlcInd8308_aucDevIdTableIdx_List[ucDevNbr]][ucIdx+6] = 0; CddMlcInd8308_aunTargetLedWidths_List[CddMlcInd8308_aucDevIdTableIdx_List[ucDevNbr]][ucIdx] = 0; } #endif //@jiangtao end test // Point to the target led widths for the current chip unSrcPtr = &(CddMlcInd8308_aunTargetLedWidths_List[CddMlcInd8308_aucDevIdTableIdx_List[ucDevNbr]][0]); // Update data or not ucDesPtr = CddLmm_ucSetPwm_List[ucDevNbr]; // Point to the start of the command // set PWM data start *(ucDesPtr++) = CDD_LMM_SYNC_DATA; // Sync Field *(ucDesPtr++) = CMD_Field; // CMD Field (CMD_CODE) *(ucDesPtr++) = (uint8)(((CddMlcInd8308_aucDevIdTable_List[ucDevNbr]) << 3) | (uint8)(CDD_LMM_PWMWIDTH0 >> 8)); // DEVID Field (DEVID+REGADDR) REGADDR:0x114 *(ucDesPtr++) = (uint8)CDD_LMM_PWMWIDTH0; // DEVID Field (DEVID+REGADDR) REGADDR:0x114 for (ucIdx = 0u; ucIdx < CDD_LMM_N_12_BYTES; ucIdx++) { // target duty cycle[0, 4095] //unSrcPWM[ucIdx] = CddLmm_RegulateIntensity_ALAD(ucDevNbr, ucIdx, unSrcPtr[ucIdx]); *(ucDesPtr++) = (uint8)(unSrcPtr[ucIdx] >> 0); // expand from intensity (1-bit)to(8-bit)PWM *(ucDesPtr++) = (uint8)(unSrcPtr[ucIdx] >> 8); // expand from intensity (9-bit)to(12-bit)PWM } // Add the CRC to Write Phase Command CddMlcInd8308_Add_CRC(CddLmm_ucSetPwm_List[ucDevNbr], CDD_LMM_N_TX_SetPWMs); //send break //CddLmm_SendBreak_ALAD(); // Add the Message to UART Queue and store the command status reference; CddMlcInd8308_psCommmandStatus[ucDevNbr] = CddMlcInd8308Uart_AddMessage(CddLmm_ucSetPwm_List[ucDevNbr], CDD_LMM_N_TX_SetPWMs, CddLmm_reSetPwm_List[ucDevNbr], CDD_LMM_N_RX_SetPWMs); } } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_MuxCommands /// /// \descr Function which interrogates on a multiplexed mode each Mlc chip: /// 1. the ADC results registers, retrieves the converted ADC values and stores them in local variables /// 2. the LED status registers, retrieves and stores the Fault and CRC Error Count Registers in local variables /// 3. the SLEWRATE, OVLMT, PARLED, the six DEFWIDTH registers as segment configuration /// and the SYSCFG, CMWTAP, PWMTICK, ADCID as chip register configuration. /// /// \param none /// /// \return none //----------------------------------------------------------------------------- STATIC_AL void CddMlcInd8308_MuxCommands(void) { uint8 Datalength = CddLmm_DATA_LEN_4BYTES; if (CddMlcInd8308_aboDeviceResponse[CddMlcInd8308_ucChipNbr] != FALSE) { //read 0x340 register ,open and short status CddMlcInd8308_aucCmdRdFault_List[0u] = CDD_LMM_SYNC_DATA; // Sync Field CddMlcInd8308_aucCmdRdFault_List[1u] = (uint8) ((Datalength <<3) | CddLmm_CMD_TYPE_READ); // CMD Field (inclued:P1 1bit +P2 1bit + datalenth 3bit + CMD_CODE 3bit).CMD_CODE 3bit CddMlcInd8308_aucCmdRdFault_List[1u] = Parity_check(CddMlcInd8308_aucCmdRdFault_List[1u]); // CMD Field Parity_check CddMlcInd8308_aucCmdRdFault_List[2u] = ((CddMlcInd8308_aucDevIdTable_List[CddMlcInd8308_ucChipNbr] << 3) | (uint8)(CDD_LMM_FLAG_OV_SC >> 8)); // DEVID Field (DEVID+REGADDR) REGADDR:0x340 CddMlcInd8308_aucCmdRdFault_List[3u] = (uint8)CDD_LMM_FLAG_OV_SC; // REGADDR Field CddMlcInd8308_Add_CRC(CddMlcInd8308_aucCmdRdFault_List, CDD_LMM_N_TX_GetOpenShortStatus); // calculate CRC bits //CddLmm_SendBreak_ALAD(); //send break // Add the Message to UART Queue and store the command status reference; CddMlcInd8308_psCommmandStatus[CDDMLCInd8308_CMD_IDX_READ_FLTS] = CddMlcInd8308Uart_AddMessage(CddMlcInd8308_aucCmdRdFault_List, CDD_LMM_N_TX_GetOpenShortStatus, CddMlcInd8308_aucResRdFault_List, CDD_LMM_N_RX_resGetOpenShortStatus); Datalength = CddLmm_DATA_LEN_4BYTES; CddMlcInd8308_aucCmdBroadcastFault_List[0u] = CDD_LMM_SYNC_DATA; // Sync Field CddMlcInd8308_aucCmdBroadcastFault_List[1u] = (uint8) ((Datalength <<3) | CddLmm_CMD_TYPE_BROADCAST_WRITE); // CMD Field CddMlcInd8308_aucCmdBroadcastFault_List[1u] = Parity_check(CddMlcInd8308_aucCmdBroadcastFault_List[1u]); // CMD Field Parity_check CddMlcInd8308_aucCmdBroadcastFault_List[2u] = ((CddMlcInd8308_aucDevIdTable_List[CddMlcInd8308_ucChipNbr] << 3) | (uint8)(CDD_LMM_FLAG_OV_SC >> 8)); // DEVID Field (DEVID+REGADDR) REGADDR:0x340 CddMlcInd8308_aucCmdBroadcastFault_List[3u] = (uint8)CDD_LMM_FLAG_OV_SC; // Reset FLT_OPEN_OR_DRVL data CddMlcInd8308_aucCmdBroadcastFault_List[4u] = 0xFF; // Reset FLT_OPEN_OR_DRVLH data CddMlcInd8308_aucCmdBroadcastFault_List[5u] = 0xFF; // Reset FAULT_SHORTL data CddMlcInd8308_aucCmdBroadcastFault_List[6u] = 0xFF; // Reset FAULT_SHORTh data CddMlcInd8308_aucCmdBroadcastFault_List[7u] = (0x1F + ((uint8)CddLmm_SHORT_TIME_256us << 5)); // data CddMlcInd8308_Add_CRC(CddMlcInd8308_aucCmdBroadcastFault_List, CDD_LMM_N_TX_ClearOpenShortErrors); // calculate CRC bits //CddLmm_SendBreak_ALAD(); //send break (void)CddMlcInd8308Uart_AddMessage(CddMlcInd8308_aucCmdBroadcastFault_List, CDD_LMM_N_TX_ClearOpenShortErrors, CddMlcInd8308_aucCmdBroadcastFault_List, CDD_LMM_N_TX_ClearOpenShortErrors); } if (CddMlcInd8308_aboDeviceResponse[CddMlcInd8308_ucChipNbr] != FALSE) { //obsolete : Section which interrogates the SLEWRATE, OVLMT, PARLED, the six DEFWIDTH registers as segment configuration and SYSCFG, CMWTAP, PWMTICK, ADCID as chip register configuration. Datalength = CddLmm_DATA_LEN_2BYTES; CddMlcInd8308_aucCmdRdStatus[0u] = CDD_LMM_SYNC_DATA; // Sync Field CddMlcInd8308_aucCmdRdStatus[1u] = (uint8) ((Datalength <<3) | CddLmm_CMD_TYPE_READ); // CMD Field CddMlcInd8308_aucCmdRdStatus[1u] = Parity_check(CddMlcInd8308_aucCmdRdStatus[1u]); // CMD Field Parity_check CddMlcInd8308_aucCmdRdStatus[2u] = ((CddMlcInd8308_aucDevIdTable_List[CddMlcInd8308_ucChipNbr] << 3) | (uint8)(CDD_LMM_SYS_STATUS >> 8)); // DEVID Field (DEVID+REGADDR) REGADDR:0x340 CddMlcInd8308_aucCmdRdStatus[3u] = (uint8)CDD_LMM_SYS_STATUS; // Reset FLT_OPEN_OR_DRVL data CddMlcInd8308_Add_CRC(CddMlcInd8308_aucCmdRdStatus, CDD_LMM_N_TX_GetErrorsStatus); // calculate CRC bits //CddLmm_SendBreak_ALAD(); //send break CddMlcInd8308_psCommmandStatus[CDDMLCInd8308_CMD_IDX_READ_CNFG] = CddMlcInd8308Uart_AddMessage(CddMlcInd8308_aucCmdRdStatus, CDD_LMM_N_TX_GetErrorsStatus, CddMlcInd8308_aucResRdStatus, CDD_LMM_N_RX_resGetErrorsStatus); //Section which interrogates the ADC registers, retrieves the converted ADC values and stores them in local variables Datalength = CddLmm_DATA_LEN_4BYTES; CddMlcInd8308_aucCmdRdADC_List[0u] = CDD_LMM_SYNC_DATA; // Sync Field CddMlcInd8308_aucCmdRdADC_List[1u] = (uint8) ((Datalength <<3) | CddLmm_CMD_TYPE_READ); // CMD Field CddMlcInd8308_aucCmdRdADC_List[1u] = Parity_check(CddMlcInd8308_aucCmdRdADC_List[1u]); // CMD Field Parity_check CddMlcInd8308_aucCmdRdADC_List[2u] = ((CddMlcInd8308_aucDevIdTable_List[CddMlcInd8308_ucChipNbr] << 3) | (uint8)(CDD_LMM_ADC_DATA0 >> 8)); // DEVID Field (DEVID+REGADDR) REGADDR:0x340 CddMlcInd8308_aucCmdRdADC_List[3u] = (uint8)CDD_LMM_ADC_DATA0; // Reset FLT_OPEN_OR_DRVL data CddMlcInd8308_Add_CRC(CddMlcInd8308_aucCmdRdADC_List, CDD_LMM_N_TX_GetADCData); // calculate CRC bits //CddLmm_SendBreak_ALAD(); //send break CddMlcInd8308_psCommmandStatus[CDDMLCInd8308_CMD_IDX_READ_ADCS] = CddMlcInd8308Uart_AddMessage(CddMlcInd8308_aucCmdRdADC_List, CDD_LMM_N_TX_GetADCData, CddMlcInd8308_aucResRdADC_List, CDD_LMM_N_RX_resGetADCData); } } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_GetChipConfig /// /// \descr Returns the Chip Register Configuration of selected Mlc device /// /// \param uint8 Mlc device number /// \param uint8 pointer to the desired buffer to save data /// /// \return none //----------------------------------------------------------------------------// PRQA S 1505,3408 ++ //The Function is called from external modules tsCddMlcInd8308_RegisterConfig CddMlcInd8308_GetChipConfig(uint8 ucDevNbr) { return CddMlcInd8308_aucChipSysConfig_List[ucDevNbr]; } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_GetADCResult /// /// \descr Returns the ADC results and quality flag on selected Mlc device /// /// \param uint8 Mlc device number /// /// \return CddMlcInd8308_asAdcResult_List the value of ADC1, ADC2 and the quality flag //----------------------------------------------------------------------------- tsCddMlcInd8308_AdcResult CddMlcInd8308_GetADCResult(uint8 ucDevNbr) { return CddMlcInd8308_asAdcResult_List[ucDevNbr]; } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_GetLedsStatus /// /// \descr Returns the status of LEDs on selected Mlc device /// /// \param uint8 device number /// /// \return CddMlcInd8308_asLedStatus the status of selected LED device //----------------------------------------------------------------------------- tsCddMlcInd8308_LedStatus CddMlcInd8308_GetLedsStatus(uint8 ucDevNbr) { return CddMlcInd8308_asLedStatus_List[ucDevNbr]; } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_GetComStatus /// /// \descr Returns the communication status of all Mlc chips /// /// \param none /// /// \return CddMlcInd8308_ComStatus the communication status of all Mlcs //----------------------------------------------------------------------------- tsCddMlcInd8308_ComStatus CddMlcInd8308_GetComStatus(void) { return CddMlcInd8308_ComStatus; } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_GetActualState /// /// \descr Returns the state of Mlc Driver /// /// \param none /// /// \return CddMlcInd8308_SystemMode the Status of the Mlc driver //----------------------------------------------------------------------------- teCddMlcInd8308_SystemMode CddMlcInd8308_GetActualState(void) { return CddMlcInd8308_SystemMode; } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_ClearLedsStatus /// /// \descr Function trigger reseting of LED Fault Status registers /// and CRC Error Count Registers for all Mlc chips /// /// \param none /// /// \return none //----------------------------------------------------------------------------- void CddMlcInd8308_ClearLedsStatus(void) { uint8 ucDevNbr; // Reset the Fault Status Flag for all configured Mlc chips for (ucDevNbr = 0u; ucDevNbr < CddMlc8308_ConnectedDevices /*CDD_MLC_CHIPS*/; ucDevNbr++) { // set Led Status to init values for each device CddMlcInd8308_asLedStatus_List[ucDevNbr].unLedFaultOpen = CDDMLCInd8308_FAULT_STATUS_INIT; CddMlcInd8308_asLedStatus_List[ucDevNbr].unLedFaultShort = CDDMLCInd8308_FAULT_STATUS_INIT; } // Clear LED Segments Faults for all Mlc Chips CddMlcInd8308_ucClearFaults = CDDMLCInd8308_CFG_CLR_FLT_CNT; if (CddMlcInd8308_ucClearFaults == CDDMLCInd8308_CFG_CLR_FLT_CNT) { //do nothing //F82099D : needed to remove GHS warning } } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_ResetMlcSettings /// /// \descr Function triggers to broadcast the configuration settings for all Mlc chips /// /// \param none /// /// \return none //----------------------------------------------------------------------------- void CddMlcInd8308_ResetMlcSettings(void) { // Reset Internal Variables CddMlcInd8308_ResetVars(); // Cyclic Transmission is started CddMlcInd8308_SystemMode = CddMlcInd8308_SystemMode_CfgComm; } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_ResetVars /// /// \descr The function initializes internal variables such as /// Communication Status, LED Fault Status and ADC Results /// /// \param none /// /// \return none //----------------------------------------------------------------------------- STATIC_AL void CddMlcInd8308_ResetVars(void) { uint8 ucDevNbr; //Clearing LED Status CddMlcInd8308_ClearLedsStatus(); //Init Global Communication Status for each Mlc device CddMlcInd8308_ComStatus.ulMlcStatus = 0u; //Init Global Power Cycle Flag for each Mlc device CddMlcInd8308_ComStatus.ulPowerCycleOccurred = 0u; //Init UART Communication Errors Occurrence Counter CddMlcInd8308_ComStatus.ulUartErrorsOccurred = 0u; //Init Tx Overrun Counter CddMlcInd8308_ComStatus.ulTxCommandOverrun = 0u; //Init the Variant Chip Settings flag CddMlcInd8308_ComStatus.ulAckChipSetting = 0u; //Init the Variant Phase Shifts flag CddMlcInd8308_ComStatus.ulAckPhaseShifts = 0u; //Init the Variant LED Segments flag CddMlcInd8308_ComStatus.ulAckLedSegments = 0u; // set the system configuration register for all configured Mlc chips for (ucDevNbr = 0u; ucDevNbr < CFG_MAX_NO_OF_MLC; ucDevNbr++) { // Set ADC Values to init value CddMlcInd8308_asAdcResult_List[ucDevNbr].ucADC1Value = CDDMLCInd8308_ADC_INIT_VALUE; CddMlcInd8308_asAdcResult_List[ucDevNbr].ucADC2Value = CDDMLCInd8308_ADC_INIT_VALUE; // Set ADC Quality flag to invalid CddMlcInd8308_asAdcResult_List[ucDevNbr].eQlty = CDDMLCInd8308_QLTY_INVALID; // set Led Status to init values for each device CddMlcInd8308_asLedStatus_List[ucDevNbr].unLedFaultOpen = CDDMLCInd8308_FAULT_STATUS_INIT; CddMlcInd8308_asLedStatus_List[ucDevNbr].unLedFaultShort = CDDMLCInd8308_FAULT_STATUS_INIT; //Init the Matrix IC ID for each device CddMlcInd8308_ComStatus.aucMatrixIcID_List[ucDevNbr] = CDDMLCInd8308_MATRIX_ICID_INIT; //Init Rx Timeout Counter CddMlcInd8308_ComStatus.aucTimeoutCounter_List[ucDevNbr] = CDDMLCInd8308_COM_TIMEOUT_INIT; //Init CRC Fault Counter CddMlcInd8308_ComStatus.aucCrcFltOccurrence_List[ucDevNbr] = CDDMLCInd8308_COM_CRC_FLT_INIT; // Init Chip Configuration Register for each device CddMlcInd8308_aucChipSysConfig_List[ucDevNbr].SLEWRATE = 0x00u;//{SLEWRATE} CddMlcInd8308_aucChipSysConfig_List[ucDevNbr].OVLMT = 0x00u;//{OVLMT} CddMlcInd8308_aucChipSysConfig_List[ucDevNbr].PARLED = 0x00u;//{PARLED} CddMlcInd8308_aucChipSysConfig_List[ucDevNbr].DEFWIDTH02_01 = 0x00u;//{DEFWIDTH02_01} CddMlcInd8308_aucChipSysConfig_List[ucDevNbr].DEFWIDTH04_03 = 0x00u;//{DEFWIDTH04_03} CddMlcInd8308_aucChipSysConfig_List[ucDevNbr].DEFWIDTH06_05 = 0x00u;//{DEFWIDTH06_05} CddMlcInd8308_aucChipSysConfig_List[ucDevNbr].DEFWIDTH08_07 = 0x00u;//{DEFWIDTH08_07} CddMlcInd8308_aucChipSysConfig_List[ucDevNbr].DEFWIDTH10_09 = 0x00u;//{DEFWIDTH10_09} CddMlcInd8308_aucChipSysConfig_List[ucDevNbr].DEFWIDTH12_11 = 0x00u;//{DEFWIDTH12_11} CddMlcInd8308_aucChipSysConfig_List[ucDevNbr].SYSCFG = 0x00u;//{SYSCFG} CddMlcInd8308_aucChipSysConfig_List[ucDevNbr].CMWTAP = 0x00u;//{CMWTAP} CddMlcInd8308_aucChipSysConfig_List[ucDevNbr].PWMTICK = 0x00u;//{PWMTICK} CddMlcInd8308_aucChipSysConfig_List[ucDevNbr].ADCID = 0x00u;//{ADCID}\ CddMlcInd8308_aucChipStatus[ucDevNbr].ucStatusRegister = 0x00u; } CddMlcInd8308_ResetCommunicationFaults(); } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_ResetCommunicationFaults /// /// \descr This functions resets communication faults /// /// \param - /// /// \return STATIC_AL void //----------------------------------------------------------------------------- STATIC_AL void CddMlcInd8308_ResetCommunicationFaults(void) { for (uint8 device = 0U; device < CddMlc8308_ConnectedDevices /*CDD_MLC_CHIPS*/; device++) { //Error with one device on the bus CddMlcInd8308_aboDevComError[device] &= (uint8)0xFE; // for comm error reset } //Bus Error CddMlcInd8308_boBusComError = FALSE; } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_GetSensorInfo /// /// \descr Get External resistor value (NTC and BIN) /// /// \param psExternalResistor /// \param ucDevCnt /// /// \return void //----------------------------------------------------------------------------- void CddMlcInd8308_GetSensorInfo(tisMlcSensorInput* pucExtResistor, uint8 ucDevCnt) { //ToDo: Use generic macro CFG_MAX_NO_OF_MLC if (ucDevCnt <= CDD_MLC_CHIPS) { for (uint8 ucIdx = 0U; ucIdx < CddMlc8308_ConnectedDevices; ucIdx++) { pucExtResistor[CddMlcInd8308_aucDevIdTableIdx_List[ucIdx]].ucADC1Raw = (uint16)CddMlcInd8308_asAdcResult_List[CddMlcInd8308_aucDevIdTableIdx_List[ucIdx]].ucADC1Value; pucExtResistor[CddMlcInd8308_aucDevIdTableIdx_List[ucIdx]].eADC1RawQty = (CddMlcInd8308_asAdcResult_List[CddMlcInd8308_aucDevIdTableIdx_List[ucIdx]].eQlty == CDDMLCInd8308_QLTY_INVALID) ? SIG_INVALID : \ (CddMlcInd8308_asAdcResult_List[CddMlcInd8308_aucDevIdTableIdx_List[ucIdx]].eQlty == CDDMLCInd8308_QLTY_SNA) ? SIG_SNA : SIG_VALID; pucExtResistor[CddMlcInd8308_aucDevIdTableIdx_List[ucIdx]].ucADC2Raw = (uint16)CddMlcInd8308_asAdcResult_List[CddMlcInd8308_aucDevIdTableIdx_List[ucIdx]].ucADC2Value; pucExtResistor[CddMlcInd8308_aucDevIdTableIdx_List[ucIdx]].eADC2RawQty = pucExtResistor[CddMlcInd8308_aucDevIdTableIdx_List[ucIdx]].eADC1RawQty; //take the same Qlty flag because eQlty is processed for ucADC1Value and ucADC2Value together } } } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_GetBusComError /// /// \descr /// /// \param - /// /// \return boolean //----------------------------------------------------------------------------- boolean CddMlcInd8308_GetBusComError(void) { return CddMlcInd8308_boBusComError; } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_GetDeviceStatusFault /// /// \descr Provides Fault status of connected MLC device /// /// \param pusDevStatusFault /// \param ucDevCnt /// /// \return void //----------------------------------------------------------------------------- void CddMlcInd8308_GetDeviceStatusFault(tsCddMlcDeviceStatusFault* pusDevStatusFault, uint8 ucDevCnt) { if (ucDevCnt <= CDD_MLC_CHIPS ) { for (uint8 ucIdx = 0U; ucIdx < CddMlc8308_ConnectedDevices; ucIdx++) { pusDevStatusFault[CddMlcInd8308_aucDevIdTableIdx_List[ucIdx]].boCommunicationError = ((CddMlcInd8308_ComStatus.ulMlcStatus & ((uint32)1u << ucIdx) ) != 0u) ? TRUE : FALSE;// FLT_SNA; //pusDevStatusFault[ucIdx].boTemperatureWarning = ((CddMlcInd8308_sAdcResult_List[ucIdx].ucADC1Value || CddMlcInd8308_sAdcResult_List[ucIdx].ucADC2Value) > ADC_TRESHOLD) ? TRUE : FALSE; pusDevStatusFault[CddMlcInd8308_aucDevIdTableIdx_List[ucIdx]].boTemperatureWarning = FLT_SNA; pusDevStatusFault[CddMlcInd8308_aucDevIdTableIdx_List[ucIdx]].boReset = ((CddMlcInd8308_SystemMode == CddMlcInd8308_SystemMode_CfgComm) || (CddMlcInd8308_SystemMode == CddMlcInd8308_SystemMode_Inactive)) ? TRUE : FALSE; } } } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_GetSwitchsFault /// /// \descr This function detects OC and SC for each segment (individual pixel) for /// MLC TI chip TPS92662 ( TODO: both chips) /// /// \param pusSwitchFault /// \param ucDevCnt /// \param ucSwitchCnt /// /// \return void //----------------------------------------------------------------------------- void CddMlcInd8308_GetSwitchsFault(tsCddMlcSwitchFaultArray asSwitchFaultArray, uint8 ucDevCnt, uint8 ucSwitchCnt) { if ((ucDevCnt <= CDD_MLC_CHIPS) && (ucSwitchCnt <= CDDMLCInd8308_MAX_SWITCHS_PER_DEVICE)) { for (uint8 ucDevIdx = 0; ucDevIdx < CddMlc8308_ConnectedDevices; ucDevIdx++) { //Open Circuit - Short Circuit detection for every Segment. TPS92662A supports 12 segments out of 16 (max by the generic driver) for (uint8 ucSwitchIdx = 0; ucSwitchIdx < ucSwitchCnt; ucSwitchIdx++) { asSwitchFaultArray[CddMlcInd8308_aucDevIdTableIdx_List[ucDevIdx]][ucSwitchIdx].boOpenCircuit = (uint16)(CddMlcInd8308_asLedStatus_List[CddMlcInd8308_aucDevIdTableIdx_List[ucDevIdx]].unLedFaultOpen & (uint16)((uint16)1U << (uint16)(ucSwitchIdx))) != (uint16)0U ? TRUE : FALSE; asSwitchFaultArray[CddMlcInd8308_aucDevIdTableIdx_List[ucDevIdx]][ucSwitchIdx].boShortCircuit = (uint16)(CddMlcInd8308_asLedStatus_List[CddMlcInd8308_aucDevIdTableIdx_List[ucDevIdx]].unLedFaultShort & (uint16)((uint16)1U << (uint16)(ucSwitchIdx))) != (uint16)0U ? TRUE : FALSE; } } } }//PRQA S 5336 1 // HIS metrics violation: STMIF exceeds threshold 4 //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_CheckCRC /// /// \descr Calculate and Check CRC and updating Transmit Error counter /// /// \param ucDevNbr /// \param *ucPtrData /// \param ucLength /// /// \return void //----------------------------------------------------------------------------- STATIC_AL void CddMlcInd8308_CheckCRC(uint8 ucDevNbr, uint8 *ucPtrData, uint8 ucLength) // PRQA S 1505 // The function can be called from external module { uint16 unCrc = 0u; uint16 unCalCrc = 0u; while (ucLength--) // PRQA S 3344 // Intentionally no modification of existing code { // Fastest execution time using CRC16 LookUpTable unCalCrc = CddMlcInd8308_unCrc16_List[(uint8)(unCrc ^ (*ucPtrData++))] ^ (unCrc >> 8u); } unCrc = *ucPtrData++; unCrc = unCrc | (((uint16)*ucPtrData << 8u) & 0xFF00U); if (unCalCrc == unCrc) { if (CddMlcInd8308_TxErrCnt != 0u) { CddMlcInd8308_TxErrCnt--; } } else { CddMlcInd8308_TxErrCnt++; } if (CddMlcInd8308_TxErrCnt > 3u/*CddMlcGenCodingDataValue.mlc_crc_error_rate_limit*/) { CddMlcInd8308_aboDevComError[ucDevNbr] |= (uint8)0x02; } else { CddMlcInd8308_aboDevComError[ucDevNbr] &= (uint8)0xFD; } } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_SDReadRespHandler /// /// \descr Single Device read response handler /// /// \param ucDevNbr /// /// \return void //----------------------------------------------------------------------------- STATIC_AL void CddMlcInd8308_SDReadRespHandler(uint8 ucDevNbr) { //CddMlcInd8308_CheckCRC(ucDevNbr, &CddMlcInd8308_aucResRdADC_List[CDDMLCInd8308_N_TX_ADC], CDD_LMM_N_02_BYTES); //ddMlcInd8308_CheckCRC(ucDevNbr, &CddMlcInd8308_aucResRdFault_List[CDDMLCInd8308_N_TX_FAULT], CDD_LMM_N_03_BYTES); //CddMlcTI_CheckCRC(ucDevNbr, &CddMlcInd8308_aucResRdConfig_List[CDDMLCInd8308_N_TX_CONFIG], CDDMLCInd8308_N_32_BYTES); //CddMlcInd8308_CheckCRC(ucDevNbr, &CddMlcInd8308_aucResRdStatus[CDDMLCInd8308_N_TX_CONFIG], CDD_LMM_N_01_BYTE); } //----------------------------------------------------------------------------- /// \brief CddMlcInd8308_GetFamilyDevConnected /// /// \descr This function collects the identification family part number read in /// the broadcast command and based on the response, it gets the /// number of devices connected from the same family to adjust /// the number of commands to be sent /// /// \param - /// /// \return uint8 : number of devices identified as GEN3 family : Ind8308/5/7 //----------------------------------------------------------------------------- uint8 CddMlcInd8308_GetFamilyDevConnected(void) { uint8 ucCountGen3Dev = 0u; uint8 ucDevIdenICID = 0u; static boolean boUpdate[CFG_MAX_NO_OF_MLC] ; for (uint8 ucDevNbr = 0u; ucDevNbr < CDD_MLC_CHIPS; ucDevNbr++) { //ucDevIdenICID = CddMlcInd8308_aucResponse_List[ucDevNbr][CDDMLCInd8308_N_TX_ICID]; ucDevIdenICID = CddMlcInd8308_ComStatus.aucMatrixIcID_List[ucDevNbr]; if ((ucDevIdenICID >= Ind8308_DEV) && (ucDevIdenICID <= TPS92667_DEV)) { ucCountGen3Dev++; boUpdate[ucDevNbr] = TRUE; } else { boUpdate[ucDevNbr] = FALSE; } } CddMlcGen3Dev = ucCountGen3Dev; return ucCountGen3Dev; } //----------------------------------------------------------------------------- /// \brief CddLmm_SendBreak_ALAD /// /// \descr The function send 0x07 massage for baudrate change, /// /// /// \param none /// /// \return none //----------------------------------------------------------------------------- void CddLmm_SendBreak_ALAD(void) { CddLmm_ucBreak_List[0]= CDD_LMM_BREAK_DATA; (void)CddMlcInd8308Uart_AddMessage(CddLmm_ucBreak_List, CDD_LMM_N_01_BYTE, CddLmm_ucResBreak_List, CDD_LMM_N_01_BYTE); } // EOF