//***************************************************************************** // (C) Automotive Lighting Reutlingen GmbH // Tuebinger Strasse 123, 72762 Reutlingen, Germany // // Automotive Lighting Reutlingen GmbH owns all the rights to this work. // This work shall not be copied, reproduced, used, modified, transferred // or its information shall not be disclosed without the prior written // authorization of Automotive Lighting Reutlingen GmbH. //***************************************************************************** //----------------------------------------------------------------------------- /// \file CddCPSQ5352_Sched.h /// /// \brief Schedule table for CPSQ5352 /// /// \author OTT, Peter ALDE-RT/EES6 //----------------------------------------------------------------------------- #ifndef CDD_CPSQ5352_SCHED_2021_01_21_H_ #define CDD_CPSQ5352_SCHED_2021_01_21_H_ //----------------------------------------------------------------------------- // Includes //----------------------------------------------------------------------------- #include #include <../Gen/CddCPSQ5352_Types.h> #include <../Cfg/CddCPSQ5352_Cfg.h> //----------------------------------------------------------------------------- // Defines //----------------------------------------------------------------------------- // Actions executed synchrone with SPI schedule Table before a SPI Tx #define CDDCPSQ5352_NO_ACT 0u #define CDDCPSQ5352_ST_CHECK_START 1u //SYSCFG1 register coonfiguration #define CDDCPSQ5352_Cfg_CH1INTPWM CDDCPSQ5352_INTPWM_NotUsed //Internal PWM generator not used #define CDDCPSQ5352_Cfg_CH2INTPWM CDDCPSQ5352_INTPWM_NotUsed //Internal PWM generator not used #define CDDCPSQ5352_Cfg_PWMPH CDDCPSQ5352_INTPWM_PhaseShift_0 //SYSCFG2 register coonfiguration #define CDDCPSQ5352_Cfg_IFT CDDCPSQ5352_IFT_FaultTimer_32ms #define CDDCPSQ5352_Cfg_CH1TSFL CDDCPSQ5352_TSFL_ThermalShutdown_AutoRestart #define CDDCPSQ5352_Cfg_CH2TSFL CDDCPSQ5352_TSFL_ThermalShutdown_AutoRestart //Communication watchdog timer (CMWTAP) register configuration #define CDDCPSQ5352_Cfg_CMWTAP CDDCPSQ5352_CMWTAP_ComWatchdogPerdiod_1670ms //Thermal warning limit (TWLMT) register configuration #define CDDCPSQ5352_Cfg_TWLMT 147u // Thermal warning limit : Tj = 0,7168�C * 147d * 4 - 271,51�C = 150�C //Internal PWM clock divider (PWMDIV) register configuration #define CDDCPSQ5352_Cfg_PWMDIV CDDCPSQ5352_PWMDIV_InternalPWMFreq_610Hz //Buck ON-time and freqauency for channel 1 (CH1TON) register configuration #define CDDCPSQ5352_Cfg_CH1TON CDDCPSQ5352_CHxTON_BuckFreq_400kHz //Buck ON-time and frequency for channel 2 (CH2TON) register configuration #define CDDCPSQ5352_Cfg_CH2TON CDDCPSQ5352_CHxTON_BuckFreq_400kHz //Limp home internal or external current reference set point. #define CDDCPSQ5352_Cfg_LHEXTIADJ CDDCPSQ5352_LHEXTIADJ_OFF //Limp home internal or external PWM for LED current duty cycle #define CDDCPSQ5352_Cfg_LH1INTPM CDDCPSQ5352_LHxINTPWM_ON #define CDDCPSQ5352_Cfg_LH2INTPM CDDCPSQ5352_LHxINTPWM_ON #define CDDCPSQ5352_Cfg_LHPWMPH CDDCPSQ5352_LHPWMPH_PhaseShift_0 //Limp home Buck ON-time and frequency register configuration #define CDDCPSQ5352_Cfg_LH1TON CDDCPSQ5352_LHxTON_BuckFreq_400kHz #define CDDCPSQ5352_Cfg_LH2TON CDDCPSQ5352_LHxTON_BuckFreq_400kHz // Limp home counter limit for the ILIM fault timer #define CDDCPSQ5352_Cfg_LHIFT CDDCPSQ5352_LHIFT_32ms // Dim_on Short and BSTUV Blank time #define CDDCPSQ5352_Cfg_BLANK CDDCPSQ5352_BLANK_100US //----------------------------------------------------------------------------- // SPI scheduling configuration //----------------------------------------------------------------------------- #if (CDDBUCK_CHIP_ERROR_HAND == CDDBUCk_CHIP_CPSQ5352) #define CDDCPSQ5352_Cfg_SpiSchedTableLen 140u #define CDDCPSQ5352_Cfg_SpiSchedTable_Init \ { \ /* next Optional Read/Write Register Data Data */ \ /* index state action command address to transmit to receive */ \ /*--------------------------------- Init sequence -----------------------------------------------------------------------------------------------------------*/ \ /* 0 */ { 1u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrRESET_Tx, CDDCPSQ5352_RESET_Tx, CDDCPSQ5352_Dummy_Rx }, \ /* 1 */ { 2u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSYSCFG1_Tx, CDDCPSQ5352_SYSCFG1_Tx, CDDCPSQ5352_Dummy_Rx }, \ /* 2 */ { 3u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS3_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_SYSCFG1_Rx }, \ /* 3 */ { 4u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSYSCFG2_Tx, CDDCPSQ5352_SYSCFG2_Tx, CDDCPSQ5352_STATUS3_Rx }, \ /* 4 */ { 5u, CDDCPSQ5352_ST_CHECK_START, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCMWTAP_Tx, CDDCPSQ5352_CMWTAP_Tx, CDDCPSQ5352_SYSCFG2_Rx }, \ /* 5 */ { 6u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrTWLMT_Tx, CDDCPSQ5352_TWLMT_Tx, CDDCPSQ5352_CMWTAP_Rx }, \ /* 6 */ { 7u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSLEEP_Tx, CDDCPSQ5352_SLEEP_Tx, CDDCPSQ5352_TWLMT_Rx }, \ /* 7 */ { 8u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1IADJH_Tx, CDDCPSQ5352_CH1IADJH_Tx, CDDCPSQ5352_SLEEP_Rx }, \ /* 8 */ { 9u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1IADJL_Tx, CDDCPSQ5352_CH1IADJL_Tx, CDDCPSQ5352_CH1IADJH_Rx }, \ /* 9 */ { 10u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2IADJH_Tx, CDDCPSQ5352_CH2IADJH_Tx, CDDCPSQ5352_CH1IADJL_Rx }, \ /* 10 */ { 11u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2IADJL_Tx, CDDCPSQ5352_CH2IADJL_Tx, CDDCPSQ5352_CH2IADJH_Rx }, \ /* 11 */ { 12u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrPWMDIV_Tx, CDDCPSQ5352_PMWDIV_Tx, CDDCPSQ5352_CH2IADJL_Rx }, \ /* 12 */ { 13u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1PWMH_Tx, CDDCPSQ5352_CH1PWMH_Tx, CDDCPSQ5352_PMWDIV_Rx }, \ /* 13 */ { 14u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1PWML_Tx, CDDCPSQ5352_CH1PWML_Tx, CDDCPSQ5352_CH1PWMH_Rx }, \ /* 14 */ { 15u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2PWMH_Tx, CDDCPSQ5352_CH2PWMH_Tx, CDDCPSQ5352_CH1PWML_Rx }, \ /* 15 */ { 16u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2PWML_Tx, CDDCPSQ5352_CH2PWML_Tx, CDDCPSQ5352_CH2PWMH_Rx }, \ /* 16 */ { 17u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1TON_Tx, CDDCPSQ5352_CH1TON_Tx, CDDCPSQ5352_CH2PWML_Rx }, \ /* 17 */ { 18u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2TON_Tx, CDDCPSQ5352_CH2TON_Tx, CDDCPSQ5352_CH1TON_Rx }, \ /* 18 */ { 19u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VIN_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2TON_Rx }, \ /* 19 */ { 20u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VIN_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VIN_Rx }, \ /* 20 */ { 21u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLED_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VIN_Rx }, \ /* 21 */ { 22u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLED_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLED_Rx }, \ /* 22 */ { 23u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLEDON_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VLED_Rx }, \ /* 23 */ { 24u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLEDON_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLEDON_Rx }, \ /* 24 */ { 25u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLEDOFF_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VLEDON_Rx }, \ /* 25 */ { 26u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLEDOFF_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLEDOFF_Rx }, \ /* 26 */ { 27u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrTEMPL_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VLEDOFF_Rx }, \ /* 27 */ { 28u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrTEMPH_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_TEMPL_Rx }, \ /* 28 */ { 29u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrV5D_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_TEMPH_Rx }, \ /* 29 */ { 30u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrLHCFG1_Tx, CDDCPSQ5352_LHCFG1_Tx, CDDCPSQ5352_V5D_Rx }, \ /* 30 */ { 31u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrLHCFG2_Tx, CDDCPSQ5352_LHCFG2_Tx, CDDCPSQ5352_LHCFG1_Rx }, \ /* 31 */ { 32u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrLHIL_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_LHCFG2_Rx }, \ /* 32 */ { 33u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrLHIH_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_LHIL_Rx }, \ /* 33 */ { 34u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrLHIFILTL_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_LHIH_Rx }, \ /* 34 */ { 35u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrLHIFILTH_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_LHIFILTL_Rx }, \ /* 35 */ { 36u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrLH1IADJH_Tx, CDDCPSQ5352_LH1IADJH_Tx, CDDCPSQ5352_LHIFILTH_Rx }, \ /* 36 */ { 37u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrLH1IADJL_Tx, CDDCPSQ5352_LH1IADJL_Tx, CDDCPSQ5352_LH1IADJH_Rx }, \ /* 37 */ { 38u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrLH2IADJH_Tx, CDDCPSQ5352_LH2IADJH_Tx, CDDCPSQ5352_LH1IADJL_Rx }, \ /* 38 */ { 39u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrLH2IADJL_Tx, CDDCPSQ5352_LH2IADJL_Tx, CDDCPSQ5352_LH2IADJH_Rx }, \ /* 39 */ { 40u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrLHCH1PWMH_Tx, CDDCPSQ5352_LHCH1PWMH_Tx, CDDCPSQ5352_LH2IADJL_Rx }, \ /* 40 */ { 41u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrLHCH1PWML_Tx, CDDCPSQ5352_LHCH1PWML_Tx, CDDCPSQ5352_LHCH1PWMH_Rx }, \ /* 41 */ { 42u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrLHCH2PWMH_Tx, CDDCPSQ5352_LHCH2PWMH_Tx, CDDCPSQ5352_LHCH1PWML_Rx }, \ /* 42 */ { 43u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrLHCH2PWML_Tx, CDDCPSQ5352_LHCH2PWML_Tx, CDDCPSQ5352_LHCH2PWMH_Rx }, \ /* 43 */ { 44u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrLH1TON_Tx, CDDCPSQ5352_LH1TON_Tx, CDDCPSQ5352_LHCH2PWML_Rx }, \ /* 44 */ { 45u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrLH2TON_Tx, CDDCPSQ5352_LH2TON_Tx, CDDCPSQ5352_LH1TON_Rx }, \ /* 45 */ { 46u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSYSCFG3_Tx, CDDCPSQ5352_SYSCFG3_Tx, CDDCPSQ5352_SYSCFG3_Rx }, \ /* 46 */ { 47u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS1_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_LH2TON_Rx }, \ /* 47 */ { 48u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS2_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_STATUS1_Rx }, \ /* 48 */ { 49u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS3_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_STATUS2_Rx }, \ /* 49 */ { 50u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLEDOFF_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_STATUS3_Rx }, \ /*---------------------------- Cyclic 0ms -------------------------------------------------------------------------------------------------------------------*/ \ /* 50 */ { 51u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLEDOFF_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_Dummy_Rx }, \ /* 51 */ { 52u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSYSCFG1_Tx, CDDCPSQ5352_SYSCFG1_Tx, CDDCPSQ5352_CH2VLEDOFF_Rx }, \ /* 52 */ { 53u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1IADJH_Tx, CDDCPSQ5352_CH1IADJH_Tx, CDDCPSQ5352_SYSCFG1_Rx }, \ /* 53 */ { 54u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1IADJL_Tx, CDDCPSQ5352_CH1IADJL_Tx, CDDCPSQ5352_CH1IADJH_Rx }, \ /* 54 */ { 55u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2IADJH_Tx, CDDCPSQ5352_CH2IADJH_Tx, CDDCPSQ5352_CH1IADJL_Rx }, \ /* 55 */ { 56u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2IADJL_Tx, CDDCPSQ5352_CH2IADJL_Tx, CDDCPSQ5352_CH2IADJH_Rx }, \ /* 56 */ { 57u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS1_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2IADJL_Rx }, \ /* 57 */ { 58u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS2_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_STATUS1_Rx }, \ /* 58 */ { 59u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrTEMPL_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_STATUS2_Rx }, \ /* 59 */ { 60u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrTEMPH_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_TEMPL_Rx }, \ /*---------------------------- Cyclic 10ms ------------------------------------------------------------------------------------------------------------------*/ \ /* 60 */ { 61u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrTEMPH_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_Dummy_Rx }, \ /* 61 */ { 62u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSLEEP_Tx, CDDCPSQ5352_SLEEP_Tx, CDDCPSQ5352_TEMPH_Rx }, \ /* 62 */ { 63u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSYSCFG1_Tx, CDDCPSQ5352_SYSCFG1_Tx, CDDCPSQ5352_SLEEP_Rx }, \ /* 63 */ { 64u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS3_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_SYSCFG1_Rx }, \ /* 64 */ { 65u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VIN_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_STATUS3_Rx }, \ /* 65 */ { 66u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLED_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VIN_Rx }, \ /* 66 */ { 67u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLEDON_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLED_Rx }, \ /* 67 */ { 68u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLEDOFF_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLEDON_Rx }, \ /* 68 */ { 69u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VIN_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLEDOFF_Rx }, \ /* 69 */ { 70u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLED_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VIN_Rx }, \ /*---------------------------- Cyclic 20ms ------------------------------------------------------------------------------------------------------------------*/ \ /* 70 */ { 71u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLED_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_Dummy_Rx }, \ /* 71 */ { 72u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLEDON_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VLED_Rx }, \ /* 72 */ { 73u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLEDOFF_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VLEDON_Rx }, \ /* 73 */ { 74u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSYSCFG1_Tx, CDDCPSQ5352_SYSCFG1_Tx, CDDCPSQ5352_CH2VLEDOFF_Rx }, \ /* 74 */ { 75u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1IADJH_Tx, CDDCPSQ5352_CH1IADJH_Tx, CDDCPSQ5352_SYSCFG1_Rx }, \ /* 75 */ { 76u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1IADJL_Tx, CDDCPSQ5352_CH1IADJL_Tx, CDDCPSQ5352_CH1IADJH_Rx }, \ /* 76 */ { 77u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2IADJH_Tx, CDDCPSQ5352_CH2IADJH_Tx, CDDCPSQ5352_CH1IADJL_Rx }, \ /* 77 */ { 78u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2IADJL_Tx, CDDCPSQ5352_CH2IADJL_Tx, CDDCPSQ5352_CH2IADJH_Rx }, \ /* 78 */ { 79u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS1_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2IADJL_Rx }, \ /* 79 */ { 80u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSYSCFG2_Tx, CDDCPSQ5352_SYSCFG2_Tx, CDDCPSQ5352_STATUS1_Rx }, \ /*---------------------------- Cyclic 30ms ------------------------------------------------------------------------------------------------------------------*/ \ /* 80 */ { 81u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSYSCFG2_Tx, CDDCPSQ5352_SYSCFG2_Tx, CDDCPSQ5352_Dummy_Rx }, \ /* 81 */ { 82u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS2_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_SYSCFG2_Rx }, \ /* 82 */ { 83u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCMWTAP_Tx, CDDCPSQ5352_CMWTAP_Tx, CDDCPSQ5352_STATUS2_Rx }, \ /* 83 */ { 84u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSLEEP_Tx, CDDCPSQ5352_SLEEP_Tx, CDDCPSQ5352_CMWTAP_Rx }, \ /* 84 */ { 85u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSYSCFG1_Tx, CDDCPSQ5352_SYSCFG1_Tx, CDDCPSQ5352_SLEEP_Rx }, \ /* 85 */ { 86u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS3_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_SYSCFG1_Rx }, \ /* 86 */ { 87u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VIN_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_STATUS3_Rx }, \ /* 87 */ { 88u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLED_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VIN_Rx }, \ /* 88 */ { 89u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLEDON_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLED_Rx }, \ /* 89 */ { 90u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLEDOFF_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLEDON_Rx }, \ /*---------------------------- Cyclic 40ms ------------------------------------------------------------------------------------------------------------------*/ \ /* 90 */ { 91u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLEDOFF_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_Dummy_Rx }, \ /* 91 */ { 92u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VIN_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLEDOFF_Rx }, \ /* 92 */ { 93u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLED_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VIN_Rx }, \ /* 93 */ { 94u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLEDON_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VLED_Rx }, \ /* 94 */ { 95u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLEDOFF_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VLEDON_Rx }, \ /* 95 */ { 96u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSYSCFG1_Tx, CDDCPSQ5352_SYSCFG1_Tx, CDDCPSQ5352_CH2VLEDOFF_Rx }, \ /* 96 */ { 97u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1IADJH_Tx, CDDCPSQ5352_CH1IADJH_Tx, CDDCPSQ5352_SYSCFG1_Rx }, \ /* 97 */ { 98u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1IADJL_Tx, CDDCPSQ5352_CH1IADJL_Tx, CDDCPSQ5352_CH1IADJH_Rx }, \ /* 98 */ { 99u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2IADJH_Tx, CDDCPSQ5352_CH2IADJH_Tx, CDDCPSQ5352_CH1IADJL_Rx }, \ /* 99 */ { 100u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2IADJL_Tx, CDDCPSQ5352_CH2IADJL_Tx, CDDCPSQ5352_CH2IADJH_Rx }, \ /*---------------------------- Cyclic 50ms ------------------------------------------------------------------------------------------------------------------*/ \ /* 100 */ { 101u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2IADJL_Tx, CDDCPSQ5352_CH2IADJL_Tx, CDDCPSQ5352_Dummy_Rx }, \ /* 101 */ { 102u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS1_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2IADJL_Rx }, \ /* 102 */ { 103u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS2_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_STATUS1_Rx }, \ /* 103 */ { 104u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrTWLMT_Tx, CDDCPSQ5352_TWLMT_Tx, CDDCPSQ5352_STATUS2_Rx }, \ /* 104 */ { 105u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrLHCFG1_Tx, CDDCPSQ5352_LHCFG1_Tx, CDDCPSQ5352_TWLMT_Rx }, \ /* 105 */ { 106u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSLEEP_Tx, CDDCPSQ5352_SLEEP_Tx, CDDCPSQ5352_LHCFG1_Rx }, \ /* 106 */ { 107u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSYSCFG1_Tx, CDDCPSQ5352_SYSCFG1_Tx, CDDCPSQ5352_SLEEP_Rx }, \ /* 107 */ { 108u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS3_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_SYSCFG1_Rx }, \ /* 108 */ { 109u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VIN_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_STATUS3_Rx }, \ /* 109 */ { 110u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLED_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VIN_Rx }, \ /*---------------------------- Cyclic 60ms ------------------------------------------------------------------------------------------------------------------*/ \ /* 110 */ { 111u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLED_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_Dummy_Rx }, \ /* 111 */ { 112u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLEDON_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLED_Rx }, \ /* 112 */ { 113u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLEDOFF_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLEDON_Rx }, \ /* 113 */ { 114u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VIN_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLEDOFF_Rx }, \ /* 114 */ { 115u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLED_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VIN_Rx }, \ /* 115 */ { 116u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLEDON_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VLED_Rx }, \ /* 116 */ { 117u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLEDOFF_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VLEDON_Rx }, \ /* 117 */ { 118u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSYSCFG1_Tx, CDDCPSQ5352_SYSCFG1_Tx, CDDCPSQ5352_CH2VLEDOFF_Rx }, \ /* 118 */ { 119u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1IADJH_Tx, CDDCPSQ5352_CH1IADJH_Tx, CDDCPSQ5352_SYSCFG1_Rx }, \ /* 119 */ { 120u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1IADJL_Tx, CDDCPSQ5352_CH1IADJL_Tx, CDDCPSQ5352_CH1IADJH_Rx }, \ /*---------------------------- Cyclic 70ms ------------------------------------------------------------------------------------------------------------------*/ \ /* 120 */ { 121u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1IADJL_Tx, CDDCPSQ5352_CH1IADJL_Tx, CDDCPSQ5352_Dummy_Rx }, \ /* 121 */ { 122u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2IADJH_Tx, CDDCPSQ5352_CH2IADJH_Tx, CDDCPSQ5352_CH1IADJL_Rx }, \ /* 122 */ { 123u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2IADJL_Tx, CDDCPSQ5352_CH2IADJL_Tx, CDDCPSQ5352_CH2IADJH_Rx }, \ /* 123 */ { 124u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS1_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2IADJL_Rx }, \ /* 124 */ { 125u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS2_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_STATUS1_Rx }, \ /* 125 */ { 126u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1TON_Tx, CDDCPSQ5352_CH1TON_Tx, CDDCPSQ5352_STATUS2_Rx }, \ /* 126 */ { 127u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2TON_Tx, CDDCPSQ5352_CH2TON_Tx, CDDCPSQ5352_CH1TON_Rx }, \ /* 127 */ { 128u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSLEEP_Tx, CDDCPSQ5352_SLEEP_Tx, CDDCPSQ5352_CH2TON_Rx }, \ /* 128 */ { 129u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSYSCFG1_Tx, CDDCPSQ5352_SYSCFG1_Tx, CDDCPSQ5352_SLEEP_Rx }, \ /* 129 */ { 130u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrV5D_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_SYSCFG1_Rx }, \ /*---------------------------- Cyclic 80ms ------------------------------------------------------------------------------------------------------------------*/ \ /* 130 */ { 131u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrV5D_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_Dummy_Rx }, \ /* 131 */ { 132u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS3_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_V5D_Rx }, \ /* 132 */ { 133u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VIN_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_STATUS3_Rx }, \ /* 133 */ { 134u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLED_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VIN_Rx }, \ /* 134 */ { 135u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLEDON_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLED_Rx }, \ /* 135 */ { 136u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLEDOFF_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLEDON_Rx }, \ /* 136 */ { 137u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VIN_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLEDOFF_Rx }, \ /* 137 */ { 138u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLED_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VIN_Rx }, \ /* 138 */ { 139u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLEDON_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VLED_Rx }, \ /* 139 */ { 50u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLEDOFF_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VLEDON_Rx } \ /*---------------------------- Cyclic 90ms ------------------------------------------------------------------------------------------------------------------*/ \ } #else #define CDDCPSQ5352_Cfg_SpiSchedTableLen 130u #define CDDCPSQ5352_Cfg_SpiSchedTable_Init \ { \ /* next Optional Read/Write Register Data Data */ \ /* index state action command address to transmit to receive */ \ /*--------------------------------- Init sequence -----------------------------------------------------------------------------------------------------------*/ \ /* 0 */ { 1u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrRESET_Tx, CDDCPSQ5352_RESET_Tx, CDDCPSQ5352_Dummy_Rx }, \ /* 1 */ { 2u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSYSCFG1_Tx, CDDCPSQ5352_SYSCFG1_Tx, CDDCPSQ5352_Dummy_Rx }, \ /* 2 */ { 3u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS3_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_SYSCFG1_Rx }, \ /* 3 */ { 4u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSYSCFG2_Tx, CDDCPSQ5352_SYSCFG2_Tx, CDDCPSQ5352_STATUS3_Rx }, \ /* 4 */ { 5u, CDDCPSQ5352_ST_CHECK_START, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCMWTAP_Tx, CDDCPSQ5352_CMWTAP_Tx, CDDCPSQ5352_SYSCFG2_Rx }, \ /* 5 */ { 6u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrTWLMT_Tx, CDDCPSQ5352_TWLMT_Tx, CDDCPSQ5352_CMWTAP_Rx }, \ /* 6 */ { 7u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSLEEP_Tx, CDDCPSQ5352_SLEEP_Tx, CDDCPSQ5352_TWLMT_Rx }, \ /* 7 */ { 8u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1IADJH_Tx, CDDCPSQ5352_CH1IADJH_Tx, CDDCPSQ5352_SLEEP_Rx }, \ /* 8 */ { 9u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1IADJL_Tx, CDDCPSQ5352_CH1IADJL_Tx, CDDCPSQ5352_CH1IADJH_Rx }, \ /* 9 */ { 10u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2IADJH_Tx, CDDCPSQ5352_CH2IADJH_Tx, CDDCPSQ5352_CH1IADJL_Rx }, \ /* 10 */ { 11u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2IADJL_Tx, CDDCPSQ5352_CH2IADJL_Tx, CDDCPSQ5352_CH2IADJH_Rx }, \ /* 11 */ { 12u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrPWMDIV_Tx, CDDCPSQ5352_PMWDIV_Tx, CDDCPSQ5352_CH2IADJL_Rx }, \ /* 12 */ { 13u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1PWMH_Tx, CDDCPSQ5352_CH1PWMH_Tx, CDDCPSQ5352_PMWDIV_Rx }, \ /* 13 */ { 14u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1PWML_Tx, CDDCPSQ5352_CH1PWML_Tx, CDDCPSQ5352_CH1PWMH_Rx }, \ /* 14 */ { 15u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2PWMH_Tx, CDDCPSQ5352_CH2PWMH_Tx, CDDCPSQ5352_CH1PWML_Rx }, \ /* 15 */ { 16u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2PWML_Tx, CDDCPSQ5352_CH2PWML_Tx, CDDCPSQ5352_CH2PWMH_Rx }, \ /* 16 */ { 17u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1TON_Tx, CDDCPSQ5352_CH1TON_Tx, CDDCPSQ5352_CH2PWML_Rx }, \ /* 17 */ { 18u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2TON_Tx, CDDCPSQ5352_CH2TON_Tx, CDDCPSQ5352_CH1TON_Rx }, \ /* 18 */ { 19u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VIN_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2TON_Rx }, \ /* 19 */ { 20u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VIN_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VIN_Rx }, \ /* 20 */ { 21u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLED_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VIN_Rx }, \ /* 21 */ { 22u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLED_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLED_Rx }, \ /* 22 */ { 23u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLEDON_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VLED_Rx }, \ /* 23 */ { 24u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLEDON_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLEDON_Rx }, \ /* 24 */ { 25u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLEDOFF_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VLEDON_Rx }, \ /* 25 */ { 26u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLEDOFF_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLEDOFF_Rx }, \ /* 26 */ { 27u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrTEMPL_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VLEDOFF_Rx }, \ /* 27 */ { 28u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrTEMPH_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_TEMPL_Rx }, \ /* 28 */ { 29u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrV5D_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_TEMPH_Rx }, \ /* 29 */ { 30u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrLHCFG1_Tx, CDDCPSQ5352_LHCFG1_Tx, CDDCPSQ5352_V5D_Rx }, \ /* 30 */ { 31u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrLHCFG2_Tx, CDDCPSQ5352_LHCFG2_Tx, CDDCPSQ5352_LHCFG1_Rx }, \ /* 31 */ { 32u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrLHIL_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_LHCFG2_Rx }, \ /* 32 */ { 33u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrLHIH_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_LHIL_Rx }, \ /* 33 */ { 34u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrLHIFILTL_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_LHIH_Rx }, \ /* 34 */ { 35u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrLHIFILTH_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_LHIFILTL_Rx }, \ /* 35 */ { 36u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrLH1IADJH_Tx, CDDCPSQ5352_LH1IADJH_Tx, CDDCPSQ5352_LHIFILTH_Rx }, \ /* 36 */ { 37u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrLH1IADJL_Tx, CDDCPSQ5352_LH1IADJL_Tx, CDDCPSQ5352_LH1IADJH_Rx }, \ /* 37 */ { 38u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrLH2IADJH_Tx, CDDCPSQ5352_LH2IADJH_Tx, CDDCPSQ5352_LH1IADJL_Rx }, \ /* 38 */ { 39u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrLH2IADJL_Tx, CDDCPSQ5352_LH2IADJL_Tx, CDDCPSQ5352_LH2IADJH_Rx }, \ /* 39 */ { 40u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrLHCH1PWMH_Tx, CDDCPSQ5352_LHCH1PWMH_Tx, CDDCPSQ5352_LH2IADJL_Rx }, \ /* 40 */ { 41u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrLHCH1PWML_Tx, CDDCPSQ5352_LHCH1PWML_Tx, CDDCPSQ5352_LHCH1PWMH_Rx }, \ /* 41 */ { 42u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrLHCH2PWMH_Tx, CDDCPSQ5352_LHCH2PWMH_Tx, CDDCPSQ5352_LHCH1PWML_Rx }, \ /* 42 */ { 43u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrLHCH2PWML_Tx, CDDCPSQ5352_LHCH2PWML_Tx, CDDCPSQ5352_LHCH2PWMH_Rx }, \ /* 43 */ { 44u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrLH1TON_Tx, CDDCPSQ5352_LH1TON_Tx, CDDCPSQ5352_LHCH2PWML_Rx }, \ /* 44 */ { 45u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrLH2TON_Tx, CDDCPSQ5352_LH2TON_Tx, CDDCPSQ5352_LH1TON_Rx }, \ /* 45 */ { 46u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSYSCFG3_Tx, CDDCPSQ5352_SYSCFG3_Tx, CDDCPSQ5352_SYSCFG3_Rx }, \ /* 46 */ { 47u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS1_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_LH2TON_Rx }, \ /* 47 */ { 48u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS2_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_STATUS1_Rx }, \ /* 48 */ { 49u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS3_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_STATUS2_Rx }, \ /* 49 */ { 50u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLEDOFF_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_STATUS3_Rx }, \ /*---------------------------- Cyclic 0ms -------------------------------------------------------------------------------------------------------------------*/ \ /* 50 */ { 51u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSYSCFG1_Tx, CDDCPSQ5352_SYSCFG1_Tx, CDDCPSQ5352_CH2VLEDOFF_Rx }, \ /* 51 */ { 52u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1IADJH_Tx, CDDCPSQ5352_CH1IADJH_Tx, CDDCPSQ5352_SYSCFG1_Rx }, \ /* 52 */ { 53u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1IADJL_Tx, CDDCPSQ5352_CH1IADJL_Tx, CDDCPSQ5352_CH1IADJH_Rx }, \ /* 53 */ { 54u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2IADJH_Tx, CDDCPSQ5352_CH2IADJH_Tx, CDDCPSQ5352_CH1IADJL_Rx }, \ /* 54 */ { 55u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2IADJL_Tx, CDDCPSQ5352_CH2IADJL_Tx, CDDCPSQ5352_CH2IADJH_Rx }, \ /* 55 */ { 56u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS1_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2IADJL_Rx }, \ /* 56 */ { 57u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS2_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_STATUS1_Rx }, \ /* 57 */ { 58u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrTEMPL_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_STATUS2_Rx }, \ /* 58 */ { 59u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrTEMPH_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_TEMPL_Rx }, \ /* 59 */ { 60u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSLEEP_Tx, CDDCPSQ5352_SLEEP_Tx, CDDCPSQ5352_TEMPH_Rx }, \ /*---------------------------- Cyclic 10ms ------------------------------------------------------------------------------------------------------------------*/ \ /* 60 */ { 61u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSYSCFG1_Tx, CDDCPSQ5352_SYSCFG1_Tx, CDDCPSQ5352_SLEEP_Rx }, \ /* 61 */ { 62u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS3_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_SYSCFG1_Rx }, \ /* 62 */ { 63u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VIN_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_STATUS3_Rx }, \ /* 63 */ { 64u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLED_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VIN_Rx }, \ /* 64 */ { 65u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLEDON_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLED_Rx }, \ /* 65 */ { 66u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLEDOFF_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLEDON_Rx }, \ /* 66 */ { 67u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VIN_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLEDOFF_Rx }, \ /* 67 */ { 68u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLED_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VIN_Rx }, \ /* 68 */ { 69u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLEDON_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VLED_Rx }, \ /* 69 */ { 70u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLEDOFF_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VLEDON_Rx }, \ /*---------------------------- Cyclic 20ms ------------------------------------------------------------------------------------------------------------------*/ \ /* 70 */ { 71u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSYSCFG1_Tx, CDDCPSQ5352_SYSCFG1_Tx, CDDCPSQ5352_CH2VLEDOFF_Rx }, \ /* 71 */ { 72u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1IADJH_Tx, CDDCPSQ5352_CH1IADJH_Tx, CDDCPSQ5352_SYSCFG1_Rx }, \ /* 72 */ { 73u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1IADJL_Tx, CDDCPSQ5352_CH1IADJL_Tx, CDDCPSQ5352_CH1IADJH_Rx }, \ /* 73 */ { 74u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2IADJH_Tx, CDDCPSQ5352_CH2IADJH_Tx, CDDCPSQ5352_CH1IADJL_Rx }, \ /* 74 */ { 75u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2IADJL_Tx, CDDCPSQ5352_CH2IADJL_Tx, CDDCPSQ5352_CH2IADJH_Rx }, \ /* 75 */ { 76u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS1_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2IADJL_Rx }, \ /* 76 */ { 77u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS2_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_STATUS1_Rx }, \ /* 77 */ { 78u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSYSCFG2_Tx, CDDCPSQ5352_SYSCFG2_Tx, CDDCPSQ5352_STATUS2_Rx }, \ /* 78 */ { 79u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCMWTAP_Tx, CDDCPSQ5352_CMWTAP_Tx, CDDCPSQ5352_SYSCFG2_Rx }, \ /* 79 */ { 80u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSLEEP_Tx, CDDCPSQ5352_SLEEP_Tx, CDDCPSQ5352_CMWTAP_Rx }, \ /*---------------------------- Cyclic 30ms ------------------------------------------------------------------------------------------------------------------*/ \ /* 80 */ { 81u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSYSCFG1_Tx, CDDCPSQ5352_SYSCFG1_Tx, CDDCPSQ5352_SLEEP_Rx }, \ /* 81 */ { 82u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS3_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_SYSCFG1_Rx }, \ /* 82 */ { 83u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VIN_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_STATUS3_Rx }, \ /* 83 */ { 84u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLED_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VIN_Rx }, \ /* 84 */ { 85u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLEDON_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLED_Rx }, \ /* 85 */ { 86u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLEDOFF_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLEDON_Rx }, \ /* 86 */ { 87u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VIN_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLEDOFF_Rx }, \ /* 87 */ { 88u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLED_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VIN_Rx }, \ /* 88 */ { 89u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLEDON_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VLED_Rx }, \ /* 89 */ { 90u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLEDOFF_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VLEDON_Rx }, \ /*---------------------------- Cyclic 40ms ------------------------------------------------------------------------------------------------------------------*/ \ /* 90 */ { 91u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSYSCFG1_Tx, CDDCPSQ5352_SYSCFG1_Tx, CDDCPSQ5352_CH2VLEDOFF_Rx }, \ /* 91 */ { 92u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1IADJH_Tx, CDDCPSQ5352_CH1IADJH_Tx, CDDCPSQ5352_SYSCFG1_Rx }, \ /* 92 */ { 93u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1IADJL_Tx, CDDCPSQ5352_CH1IADJL_Tx, CDDCPSQ5352_CH1IADJH_Rx }, \ /* 93 */ { 94u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2IADJH_Tx, CDDCPSQ5352_CH2IADJH_Tx, CDDCPSQ5352_CH1IADJL_Rx }, \ /* 94 */ { 95u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2IADJL_Tx, CDDCPSQ5352_CH2IADJL_Tx, CDDCPSQ5352_CH2IADJH_Rx }, \ /* 95 */ { 96u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS1_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2IADJL_Rx }, \ /* 96 */ { 97u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS2_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_STATUS1_Rx }, \ /* 97 */ { 98u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrTWLMT_Tx, CDDCPSQ5352_TWLMT_Tx, CDDCPSQ5352_STATUS2_Rx }, \ /* 98 */ { 99u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrLHCFG1_Tx, CDDCPSQ5352_LHCFG1_Tx, CDDCPSQ5352_TWLMT_Rx }, \ /* 99 */ { 100u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSLEEP_Tx, CDDCPSQ5352_SLEEP_Tx, CDDCPSQ5352_LHCFG1_Rx }, \ /*---------------------------- Cyclic 50ms ------------------------------------------------------------------------------------------------------------------*/ \ /* 100 */ { 101u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSYSCFG1_Tx, CDDCPSQ5352_SYSCFG1_Tx, CDDCPSQ5352_SLEEP_Rx }, \ /* 101 */ { 102u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS3_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_SYSCFG1_Rx }, \ /* 102 */ { 103u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VIN_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_STATUS3_Rx }, \ /* 103 */ { 104u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLED_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VIN_Rx }, \ /* 104 */ { 105u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLEDON_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLED_Rx }, \ /* 105 */ { 106u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLEDOFF_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLEDON_Rx }, \ /* 106 */ { 107u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VIN_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLEDOFF_Rx }, \ /* 107 */ { 108u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLED_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VIN_Rx }, \ /* 108 */ { 109u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLEDON_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VLED_Rx }, \ /* 109 */ { 110u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLEDOFF_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VLEDON_Rx }, \ /*---------------------------- Cyclic 60ms ------------------------------------------------------------------------------------------------------------------*/ \ /* 110 */ { 111u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSYSCFG1_Tx, CDDCPSQ5352_SYSCFG1_Tx, CDDCPSQ5352_CH2VLEDOFF_Rx }, \ /* 111 */ { 112u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1IADJH_Tx, CDDCPSQ5352_CH1IADJH_Tx, CDDCPSQ5352_SYSCFG1_Rx }, \ /* 112 */ { 113u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1IADJL_Tx, CDDCPSQ5352_CH1IADJL_Tx, CDDCPSQ5352_CH1IADJH_Rx }, \ /* 113 */ { 114u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2IADJH_Tx, CDDCPSQ5352_CH2IADJH_Tx, CDDCPSQ5352_CH1IADJL_Rx }, \ /* 114 */ { 115u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2IADJL_Tx, CDDCPSQ5352_CH2IADJL_Tx, CDDCPSQ5352_CH2IADJH_Rx }, \ /* 115 */ { 116u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS1_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2IADJL_Rx }, \ /* 116 */ { 117u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS2_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_STATUS1_Rx }, \ /* 117 */ { 118u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH1TON_Tx, CDDCPSQ5352_CH1TON_Tx, CDDCPSQ5352_STATUS2_Rx }, \ /* 118 */ { 119u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrCH2TON_Tx, CDDCPSQ5352_CH2TON_Tx, CDDCPSQ5352_CH1TON_Rx }, \ /* 119 */ { 120u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSLEEP_Tx, CDDCPSQ5352_SLEEP_Tx, CDDCPSQ5352_CH2TON_Rx }, \ /*---------------------------- Cyclic 70ms ------------------------------------------------------------------------------------------------------------------*/ \ /* 120 */ { 121u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_WriteCmdBit_Tx, CDDCPSQ5352_AddrSYSCFG1_Tx, CDDCPSQ5352_SYSCFG1_Tx, CDDCPSQ5352_SLEEP_Rx }, \ /* 121 */ { 122u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrSTATUS3_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_SYSCFG1_Rx }, \ /* 122 */ { 123u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VIN_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_STATUS3_Rx }, \ /* 123 */ { 124u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLED_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VIN_Rx }, \ /* 124 */ { 125u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLEDON_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLED_Rx }, \ /* 125 */ { 126u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH1VLEDOFF_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLEDON_Rx }, \ /* 126 */ { 127u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VIN_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH1VLEDOFF_Rx }, \ /* 127 */ { 128u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLED_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VIN_Rx }, \ /* 128 */ { 129u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLEDON_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VLED_Rx }, \ /* 129 */ { 50u, CDDCPSQ5352_NO_ACT, CDDCPSQ5352_ReadCmdBit_Tx, CDDCPSQ5352_AddrCH2VLEDOFF_Tx, CDDCPSQ5352_Zero_Tx, CDDCPSQ5352_CH2VLEDON_Rx } \ /*---------------------------- Cyclic 80ms ------------------------------------------------------------------------------------------------------------------*/ \ } #endif #endif // CDD_CPSQ5352_SCHED_2021_01_21_H_