//***************************************************************************** // (C) Automotive Lighting Reutlingen GmbH // Tuebinger Strasse 123, 72762 Reutlingen, Germany // // Automotive Lighting Reutlingen GmbH owns all the rights to this work. // This work shall not be copied, reproduced, used, modified, transferred // or its information shall not be disclosed without the prior written // authorization of Automotive Lighting Reutlingen GmbH. //***************************************************************************** //----------------------------------------------------------------------------- /// \file CddCpsq5453_Com.c /// /// \brief /// /// \author OTT, Peter ALDE-RT/EES6 //----------------------------------------------------------------------------- //----------------------------------------------------------------------------- // Includes //----------------------------------------------------------------------------- // standard includes #include #include // module API (include path) #include #include // module includes (relative to API) #include <../Cfg/CddCpsq5453_Cfg.h> #include <../Cfg/CddCpsq5453_RoutCfg.h> #include <../Gen/CddCpsq5453_Types.h> #include <../Gen/CddCpsq5453_Com.h> #include <../Gen/CddCpsq5453_Sched.h> // adapter #include <../Adapter/CddBoost_Adapter.h> //----------------------------------------------------------------------------- // Defines and Typedef //----------------------------------------------------------------------------- #define CDDCPSQ5453_InitZeroReg {.unRaw=0x0000u} #define CDDCPSQ5453_Reg0x00_Init {.Bit= \ {.biFPINRST = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biSYNCEN = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH2MAXDEN = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biCH1MAXDEN = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biCH2PDRVEN = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH1PDRVEN = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH2EN = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH1EN = CDDCPSQ5453_CFG_BOOST_BIT_0} } #define CDDCPSQ5453_Reg0x01_Init {.Bit= \ {.biPWMPH = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biINTPWM = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .bi2PH = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biLH = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biCH2HG = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH1HG = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH2CV = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biCH1CV = CDDCPSQ5453_CFG_BOOST_BIT_1}} #define CDDCPSQ5453_Reg0x02_Init {.Bit= \ {.biCH2LEB = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH1LEB = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biRSVD1 = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH2FILT1 = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biRSVD2 = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH1FILT1 = CDDCPSQ5453_CFG_BOOST_BIT_1}} #define CDDCPSQ5453_Reg0x03_Init {.Bit= \ {.biRSVD = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH2DIV = CDDCPSQ5453_CFG_BOOST_BIT_1,\ .biCH1DIV = CDDCPSQ5453_CFG_BOOST_BIT_1}} #define CDDCPSQ5453_Reg0x04_Init {.Bit= \ {.biRSVD1 = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH2ISLP = CDDCPSQ5453_CFG_BOOST_BIT_5, \ .biRSVD2 = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH1ISLP = CDDCPSQ5453_CFG_BOOST_BIT_5} } #define CDDCPSQ5453_Reg0x05_Init {.Bit= \ {.biRSVD = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biFMMAG = CDDCPSQ5453_CFG_BOOST_BIT_2, \ .biFMFREQ = CDDCPSQ5453_CFG_BOOST_BIT_8} } #define CDDCPSQ5453_Reg0x06_Init {.Bit= \ {.biCH2SS = 0xC, \ .biCH1SS = 0xC} } #define CDDCPSQ5453_Reg0x07_Init {.Bit={ .biCH1IADJ = 0XF5} } #define CDDCPSQ5453_Reg0x08_Init {.Bit={ .biCH2IADJ = 0XF5} } #define CDDCPSQ5453_Reg0x09_Init {.Bit= \ {.biRSVD = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biPWMDIV = CDDCPSQ5453_CFG_BOOST_BIT_0} } #define CDDCPSQ5453_Reg0x0A_Init {.Bit={ .biCH1PWM = 0xFF} } #define CDDCPSQ5453_Reg0x0B_Init {.Bit= \ {.biRSVD = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH1PWM = CDDCPSQ5453_CFG_BOOST_BIT_3} } #define CDDCPSQ5453_Reg0x0C_Init {.Bit={ .biCH2PWM = 0xFF} } #define CDDCPSQ5453_Reg0x0D_Init {.Bit= \ {.biRSVD = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH2PWM = 0x03} } #define CDDCPSQ5453_Reg0x0E_Init {.Bit= \ {.biCH2ILIMCNT = CDDCPSQ5453_CFG_BOOST_BIT_2, \ .biCH1ILIMCNT = CDDCPSQ5453_CFG_BOOST_BIT_2, \ .biCH2ILIM = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biCH1ILIM = CDDCPSQ5453_CFG_BOOST_BIT_1}} #define CDDCPSQ5453_Reg0x0F_Init {.Bit= \ {.biRSVD = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH2IFT = CDDCPSQ5453_CFG_BOOST_BIT_2, \ .biCH1IFT = CDDCPSQ5453_CFG_BOOST_BIT_2} } #define CDDCPSQ5453_Reg0x10_Init {.Bit= \ {.biCH2MFT = CDDCPSQ5453_CFG_BOOST_BIT_5, \ .biCH2MFT = CDDCPSQ5453_CFG_BOOST_BIT_5} } #define CDDCPSQ5453_Reg0x11_Init {.Bit= \ {.biRTO = CDDCPSQ5453_CFG_BOOST_UNDEFINE, \ .biRSVD = CDDCPSQ5453_CFG_BOOST_UNDEFINE, \ .biPC = CDDCPSQ5453_CFG_BOOST_UNDEFINE, \ .biTW = CDDCPSQ5453_CFG_BOOST_UNDEFINE, \ .biCH2OV = CDDCPSQ5453_CFG_BOOST_UNDEFINE, \ .biCH1OV = CDDCPSQ5453_CFG_BOOST_UNDEFINE, \ .biCH2UV = CDDCPSQ5453_CFG_BOOST_UNDEFINE, \ .biCH1UV = CDDCPSQ5453_CFG_BOOST_UNDEFINE}} #define CDDCPSQ5453_Reg0x12_Init {.Bit= \ {.biCH2UC = CDDCPSQ5453_CFG_BOOST_UNDEFINE, \ .biCH1UC = CDDCPSQ5453_CFG_BOOST_UNDEFINE, \ .biCH2OC = CDDCPSQ5453_CFG_BOOST_UNDEFINE, \ .biCH1OC = CDDCPSQ5453_CFG_BOOST_UNDEFINE, \ .biCH2ILIM = CDDCPSQ5453_CFG_BOOST_UNDEFINE, \ .biCH1ILIM = CDDCPSQ5453_CFG_BOOST_UNDEFINE, \ .biCH2ISO = CDDCPSQ5453_CFG_BOOST_UNDEFINE, \ .biCH1ISO = CDDCPSQ5453_CFG_BOOST_UNDEFINE}} #define CDDCPSQ5453_Reg0x13_Init {.Bit= \ {.biCH2RFEN = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biCH1RFEN = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biCH2FBOEN = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biCH1FBOEN = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biCH2OVEN = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biCH1OVEN = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biCH2UVEN = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biCH1UVEN = CDDCPSQ5453_CFG_BOOST_BIT_1}} #define CDDCPSQ5453_Reg0x14_Init {.Bit= \ {.biOVOPT = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biRSVD = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH2OCEN = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH1OCEN = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH2ILIMEN = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biCH1ILIMEN = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biCH2ISOEN = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biCH1ISOEN = CDDCPSQ5453_CFG_BOOST_BIT_1}} #define CDDCPSQ5453_Reg0x15_Init {.Bit= \ {.biCH2ILIMFL = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH1ILIMFL = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH2OCFL = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH1OCFL = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH2OVFL = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH1OVFL = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH2UVFL = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH1UVFL = CDDCPSQ5453_CFG_BOOST_BIT_0} } #define CDDCPSQ5453_Reg0x16_Init {.Bit= \ {.biRSVD1 = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH2OV = CDDCPSQ5453_CFG_BOOST_BIT_2, \ .biRSVD2 = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH1OV = CDDCPSQ5453_CFG_BOOST_BIT_2} } #define CDDCPSQ5453_Reg0x17_Init {.Bit= \ {.biLHPWMPH = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biLHINTPWM = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biLHCH2MAXDEN = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biLHCH1MAXDEN = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biLHCH2PDRVEN = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biLHCH1PDRVEN = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biLHCH2EN = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biLHCH1EN = CDDCPSQ5453_CFG_BOOST_BIT_1}} #define CDDCPSQ5453_Reg0x18_Init {.Bit={ .biLHCH1IADJ = 0XF5} } #define CDDCPSQ5453_Reg0x19_Init {.Bit={ .biLHCH2IADJ = 0XF5} } #define CDDCPSQ5453_Reg0x1A_Init {.Bit={ .biLHCH1PWM = 0XFF} } #define CDDCPSQ5453_Reg0x1B_Init {.Bit= \ {.biRSVD = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biLHCH1PWM = CDDCPSQ5453_CFG_BOOST_BIT_3} } #define CDDCPSQ5453_Reg0x1C_Init {.Bit={ .biLHCH2PWM = 0XFF} } #define CDDCPSQ5453_Reg0x1D_Init {.Bit= \ {.biRSVD = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biLHCH2PWM = CDDCPSQ5453_CFG_BOOST_BIT_3} } #define CDDCPSQ5453_Reg0x1E_Init {.Bit= \ {.biLHCH2ILIMCNT= CDDCPSQ5453_CFG_BOOST_BIT_2, \ .biLHCH1ILIMCNT= CDDCPSQ5453_CFG_BOOST_BIT_2, \ .biLHCH2ILIM = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biLHCH1ILIM = CDDCPSQ5453_CFG_BOOST_BIT_1}} #define CDDCPSQ5453_Reg0x1F_Init {.Bit= \ {.biRSVD = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biLHCH2IFT = CDDCPSQ5453_CFG_BOOST_BIT_2, \ .biLHCH1IFT = CDDCPSQ5453_CFG_BOOST_BIT_2} } #define CDDCPSQ5453_Reg0x20_Init {.Bit= \ {.biLHCH2MFT = CDDCPSQ5453_CFG_BOOST_BIT_5, \ .biLHCH1MFT = CDDCPSQ5453_CFG_BOOST_BIT_5} } #define CDDCPSQ5453_Reg0x21_Init {.Bit= \ {.biLHCH2RFEN = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biLHCH1RFEN = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biLHCH2FBOEN = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biLHCH1FBOEN = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biLHCH2OVEN = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biLHCH1OVEN = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biLHCH2UVEN = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biLHCH1UVEN = CDDCPSQ5453_CFG_BOOST_BIT_1}} #define CDDCPSQ5453_Reg0x22_Init {.Bit= \ {.biRSVD = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biLHCH2OCEN = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biLHCH1OCEN = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biLHCH2ILIMEN = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biLHCH1ILIMEN = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biLHCH2ISOEN = CDDCPSQ5453_CFG_BOOST_BIT_1, \ .biLHCH1ISOEN = CDDCPSQ5453_CFG_BOOST_BIT_1}} #define CDDCPSQ5453_Reg0x23_Init {.Bit= \ {.biLHCH2ILIMFL = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biLHCH1ILIMFL = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biLHCH2OCFL = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biLHCH1OCFL = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biLHCH2OVFL = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biLHCH1OVFL = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biLHCH2UVFL = CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biLHCH1UVFL = CDDCPSQ5453_CFG_BOOST_BIT_0} } #define CDDCPSQ5453_Reg0x24_Init {.Bit= \ {.biRSVD1 =CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biLHCH2OV =CDDCPSQ5453_CFG_BOOST_BIT_2, \ .biRSVD2 =CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biLHCH1OV =CDDCPSQ5453_CFG_BOOST_BIT_2} } #define CDDCPSQ5453_Reg0x25_Init {.Bit= \ {.biCH2CAL =CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH2GOFF =CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH1CAL =CDDCPSQ5453_CFG_BOOST_BIT_0, \ .biCH1GOFF =CDDCPSQ5453_CFG_BOOST_BIT_0} } #define CDDCPSQ5453_DataMirror_Init \ { \ { /* CtrlTx */ \ CDDCPSQ5453_Reg0x00_Init, \ CDDCPSQ5453_Reg0x01_Init, \ CDDCPSQ5453_Reg0x02_Init, \ CDDCPSQ5453_Reg0x03_Init, \ CDDCPSQ5453_Reg0x04_Init, \ CDDCPSQ5453_Reg0x05_Init, \ CDDCPSQ5453_Reg0x06_Init, \ CDDCPSQ5453_Reg0x07_Init, \ CDDCPSQ5453_Reg0x08_Init, \ CDDCPSQ5453_Reg0x09_Init, \ CDDCPSQ5453_Reg0x0A_Init, \ CDDCPSQ5453_Reg0x0B_Init, \ CDDCPSQ5453_Reg0x0C_Init, \ CDDCPSQ5453_Reg0x0D_Init, \ CDDCPSQ5453_Reg0x0E_Init, \ CDDCPSQ5453_Reg0x0F_Init, \ CDDCPSQ5453_Reg0x10_Init, \ CDDCPSQ5453_Reg0x13_Init, \ CDDCPSQ5453_Reg0x14_Init, \ CDDCPSQ5453_Reg0x15_Init, \ CDDCPSQ5453_Reg0x16_Init, \ }, \ { /* CtrlRx */ \ CDDCPSQ5453_InitZeroReg, \ CDDCPSQ5453_InitZeroReg, \ CDDCPSQ5453_InitZeroReg, \ CDDCPSQ5453_InitZeroReg, \ CDDCPSQ5453_InitZeroReg, \ CDDCPSQ5453_InitZeroReg, \ CDDCPSQ5453_InitZeroReg, \ CDDCPSQ5453_InitZeroReg, \ CDDCPSQ5453_InitZeroReg, \ CDDCPSQ5453_InitZeroReg, \ CDDCPSQ5453_InitZeroReg, \ CDDCPSQ5453_InitZeroReg, \ CDDCPSQ5453_InitZeroReg, \ CDDCPSQ5453_InitZeroReg, \ CDDCPSQ5453_InitZeroReg, \ CDDCPSQ5453_InitZeroReg, \ CDDCPSQ5453_InitZeroReg, \ CDDCPSQ5453_InitZeroReg, \ CDDCPSQ5453_InitZeroReg, \ CDDCPSQ5453_InitZeroReg, \ CDDCPSQ5453_InitZeroReg, \ }, \ { /* StatRx */ \ CDDCPSQ5453_InitZeroReg, \ CDDCPSQ5453_InitZeroReg, \ } \ } #define CDDCPSQ5453_Reg0x00_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x00.unRaw #define CDDCPSQ5453_Reg0x01_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x01.unRaw #define CDDCPSQ5453_Reg0x02_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x02.unRaw #define CDDCPSQ5453_Reg0x03_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x03.unRaw #define CDDCPSQ5453_Reg0x04_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x04.unRaw #define CDDCPSQ5453_Reg0x05_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x05.unRaw #define CDDCPSQ5453_Reg0x06_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x06.unRaw #define CDDCPSQ5453_Reg0x07_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x07.unRaw #define CDDCPSQ5453_Reg0x08_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x08.unRaw #define CDDCPSQ5453_Reg0x09_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x09.unRaw #define CDDCPSQ5453_Reg0x0A_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x0A.unRaw #define CDDCPSQ5453_Reg0x0B_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x0B.unRaw #define CDDCPSQ5453_Reg0x0C_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x0C.unRaw #define CDDCPSQ5453_Reg0x0D_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x0D.unRaw #define CDDCPSQ5453_Reg0x0E_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x0E.unRaw #define CDDCPSQ5453_Reg0x0F_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x0F.unRaw #define CDDCPSQ5453_Reg0x10_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x10.unRaw #define CDDCPSQ5453_Reg0x13_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x13.unRaw #define CDDCPSQ5453_Reg0x14_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x14.unRaw #define CDDCPSQ5453_Reg0x15_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x15.unRaw #define CDDCPSQ5453_Reg0x16_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x16.unRaw #define CDDCPSQ5453_Reg0x17_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x17.unRaw #define CDDCPSQ5453_Reg0x18_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x18.unRaw #define CDDCPSQ5453_Reg0x19_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x19.unRaw #define CDDCPSQ5453_Reg0x20_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x20.unRaw #define CDDCPSQ5453_Reg0x21_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x21.unRaw #define CDDCPSQ5453_Reg0x22_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x22.unRaw #define CDDCPSQ5453_Reg0x23_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x23.unRaw #define CDDCPSQ5453_Reg0x24_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x24.unRaw #define CDDCPSQ5453_Reg0x25_Tx &CddCpsq5453_DataMirror.CtrlTx.Reg0x25.unRaw #define CDDCPSQ5453_Reg0x00_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x00.unRaw #define CDDCPSQ5453_Reg0x01_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x01.unRaw #define CDDCPSQ5453_Reg0x02_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x02.unRaw #define CDDCPSQ5453_Reg0x03_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x03.unRaw #define CDDCPSQ5453_Reg0x04_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x04.unRaw #define CDDCPSQ5453_Reg0x05_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x05.unRaw #define CDDCPSQ5453_Reg0x06_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x06.unRaw #define CDDCPSQ5453_Reg0x07_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x07.unRaw #define CDDCPSQ5453_Reg0x08_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x08.unRaw #define CDDCPSQ5453_Reg0x09_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x09.unRaw #define CDDCPSQ5453_Reg0x0A_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x0A.unRaw #define CDDCPSQ5453_Reg0x0B_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x0B.unRaw #define CDDCPSQ5453_Reg0x0C_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x0C.unRaw #define CDDCPSQ5453_Reg0x0D_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x0D.unRaw #define CDDCPSQ5453_Reg0x0E_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x0E.unRaw #define CDDCPSQ5453_Reg0x0F_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x0F.unRaw #define CDDCPSQ5453_Reg0x10_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x10.unRaw #define CDDCPSQ5453_Reg0x13_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x13.unRaw #define CDDCPSQ5453_Reg0x14_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x14.unRaw #define CDDCPSQ5453_Reg0x15_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x15.unRaw #define CDDCPSQ5453_Reg0x16_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x16.unRaw #define CDDCPSQ5453_Reg0x17_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x17.unRaw #define CDDCPSQ5453_Reg0x18_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x18.unRaw #define CDDCPSQ5453_Reg0x19_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x19.unRaw #define CDDCPSQ5453_Reg0x20_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x20.unRaw #define CDDCPSQ5453_Reg0x21_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x21.unRaw #define CDDCPSQ5453_Reg0x22_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x22.unRaw #define CDDCPSQ5453_Reg0x23_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x23.unRaw #define CDDCPSQ5453_Reg0x24_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x24.unRaw #define CDDCPSQ5453_Reg0x25_Rx &CddCpsq5453_DataMirror.CtrlRx.Reg0x25.unRaw #define CDDCPSQ5453_Reg0x11_Rx &CddCpsq5453_DataMirror.StatRx.Reg0x11.unRaw #define CDDCPSQ5453_Reg0x12_Rx &CddCpsq5453_DataMirror.StatRx.Reg0x12.unRaw #define CDDCPSQ5453_Zero_Tx &CddCpsq5453_aunZero #define CDDCPSQ5453_Dummy_Rx &CddCpsq5453_aunDummy #define CDDCPSQ5453_BSTSYNC_DUTY_50 0x4000u // SPI schedule table entry datatype typedef struct tCddCpsq5453_SpiSchedTable { uint8 ucNextEntry; // index of next schedule table entry uint8 ucAction; // index of action function done after Rx --> TODO change as function pointer ? uint16 unCmd; // Read/Write Command to send uint16 unAddr; // SPI address (combination of low and high nibble) const uint16* punTx; // SPI control register data for transmission - offset related to 1st address of stuct uint16* punRx; // SPI status register data for reception - offset related to 1st address of stuct } tCddCpsq5453_SpiSchedTable; //----------------------------------------------------------------------------- // Start definitions of initialized 16 bit variables //----------------------------------------------------------------------------- #define ctadCddBoost_START_SEC_VAR_INIT_16 #include <../Cfg/CddCpsq5453_MemMap.h> #if (CDDBUCK_CHIP_ERROR_HAND == CDDBUCk_CHIP_CPSQ5352) STATIC_AL uint16 CddCpsq5453_unSchedIx_Rx = 20u; // pointer to schedule table for receiving frames STATIC_AL uint16 CddCpsq5453_unSchedIx_Tx = 20u; // pointer to schedule table for sending frames STATIC_AL uint8 CddCpsq5453_cycleSpi = 0; #else STATIC_AL uint16 CddCpsq5453_unSchedIx_Rx = 0u; // pointer to schedule table for receiving frames STATIC_AL uint16 CddCpsq5453_unSchedIx_Tx = 0u; // pointer to schedule table for sending frames #endif STATIC_AL uint16 CddCpsq5453_aunDummy = 0u; // for dummy recieve Spi Frames extern tCddCpsq5453_Boost_Sts CddCpsq5453_Boost_Sts; #define ctadCddBoost_STOP_SEC_VAR_INIT_16 #include <../Cfg/CddCpsq5453_MemMap.h> //----------------------------------------------------------------------------- // End definitions of initialized 16 bit variables //----------------------------------------------------------------------------- //----------------------------------------------------------------------------- // Start definitions of initialized structures and unions or arrays variables //----------------------------------------------------------------------------- #define ctadCddBoost_START_SEC_VAR_INIT_UNSPECIFIED #include <../Cfg/CddCpsq5453_MemMap.h> STATIC_AL tCddCpsq5453_DataMirror CddCpsq5453_DataMirror = CDDCPSQ5453_DataMirror_Init; #define ctadCddBoost_STOP_SEC_VAR_INIT_UNSPECIFIED #include <../Cfg/CddCpsq5453_MemMap.h> //----------------------------------------------------------------------------- // End definitions of initialized structures and unions or arrays variables //----------------------------------------------------------------------------- //----------------------------------------------------------------------------- // Start definitions of 16 bit const //----------------------------------------------------------------------------- /* #define ctadCddBoost_START_SEC_CONST_ROM_16BIT */ #define ctadCddBoost_START_SEC_CONST_16 //for UAP BSW #include <../Cfg/CddCpsq5453_MemMap.h> STATIC_AL CONST_AL uint16 CddCpsq5453_aunZero = 0; /*#define ctadCddBoost_STOP_SEC_CONST_ROM_16BIT*/ #define ctadCddBoost_STOP_SEC_CONST_16 //for UAP BSW #include <../Cfg/CddCpsq5453_MemMap.h> //----------------------------------------------------------------------------- // End definitions of 16 bit const //----------------------------------------------------------------------------- //----------------------------------------------------------------------------- // Start definitions of const structures and unions or arrays variables //----------------------------------------------------------------------------- /*#define ctadCddBoost_START_SEC_CONST_ROM_UNSPECIFIED*/ #define ctadCddBoost_START_SEC_CONST_UNSPECIFIED //for UAP BSW #include <../Cfg/CddCpsq5453_MemMap.h> STATIC_AL CONST_AL tCddCpsq5453_SpiSchedTable aCddCpsq5453_SpiSchedTable[CDDCPSQ5453_Cfg_SpiSchedTableLen] = CDDCPSQ5453_Cfg_SpiSchedTable_Init; \ /*#define ctadCddBoost_STOP_SEC_CONST_ROM_UNSPECIFIED*/ #define ctadCddBoost_STOP_SEC_CONST_UNSPECIFIED //for UAP BSW #include <../Cfg/CddCpsq5453_MemMap.h> //----------------------------------------------------------------------------- // End definitions of const structures and unions or arrays variables //----------------------------------------------------------------------------- //----------------------------------------------------------------------------- // Start declaration or definitions of functions //----------------------------------------------------------------------------- #define ctadCddBoost_START_SEC_CODE #include <../Cfg/CddCpsq5453_MemMap.h> //----------------------------------------------------------------------------- // Function prototypes //----------------------------------------------------------------------------- STATIC_AL uint16 CddCpsq5453_AssembleSPICmd(const uint16 unCmd, const uint16 unAddr, const uint16 unData); STATIC_AL boolean CddCpsq5453_StAction(const uint8 ucAction); //----------------------------------------------------------------------------- /// \brief Set the Booster Voltage output /// /// \descr Set the Booster voltage output sent via SPI. /// /// \param ucBoostVsetpoint /// /// \return void //----------------------------------------------------------------------------- void CddCpsq5453_SetBoostOutput(const uint8 ucBoostVOutput) { CddCpsq5453_DataMirror.CtrlTx.Reg0x07.Bit.biCH1IADJ = ucBoostVOutput; } //----------------------------------------------------------------------------- /// \brief Get the RTO: RT pin is open /// /// \descr Get the RTO: RT pin is open /// /// \param pucRTO /// /// \return boolean: TRUE - data are valid /// FALSE - data shall be discard //----------------------------------------------------------------------------- boolean CddCpsq5453_GetRTO(uint8* pucRTO) { if (pucRTO != NULL_PTR) { *pucRTO = CddCpsq5453_DataMirror.StatRx.Reg0x11.Bit.biRTO; } // return SPI Error status bit return ((CddCpsq5453_DataMirror.StatRx.Reg0x11.unRaw & CDDCPSQ5453_SPE) != CDDCPSQ5453_SPE) ? TRUE : FALSE; } //----------------------------------------------------------------------------- /// \brief Get the Power Cycled bit /// /// \descr Get the Power Cycled bit /// /// \param pucPowerCycled /// /// \return boolean: TRUE - data are valid /// FALSE - data shall be discard //----------------------------------------------------------------------------- boolean CddCpsq5453_GetPowerCycled(uint8* pucPowerCycled) { if (pucPowerCycled != NULL_PTR) { *pucPowerCycled = CddCpsq5453_DataMirror.StatRx.Reg0x11.Bit.biPC; } // return SPI Error status bit return ((CddCpsq5453_DataMirror.StatRx.Reg0x11.unRaw & CDDCPSQ5453_SPE) != CDDCPSQ5453_SPE) ? TRUE : FALSE; } //----------------------------------------------------------------------------- /// \brief Get the Thermal Warning /// /// \descr Get the Thermal Warning /// /// \param pucThermalWarning /// /// \return boolean: TRUE - data are valid /// FALSE - data shall be discard //----------------------------------------------------------------------------- boolean CddCpsq5453_GetThermalWarning(uint8* pucThermalWarning) { if (pucThermalWarning != NULL_PTR) { *pucThermalWarning = CddCpsq5453_DataMirror.StatRx.Reg0x11.Bit.biTW; } // return SPI Error status bit return ((CddCpsq5453_DataMirror.StatRx.Reg0x11.unRaw & CDDCPSQ5453_SPE) != CDDCPSQ5453_SPE) ? TRUE : FALSE; } //----------------------------------------------------------------------------- /// \brief Get the output overvoltage fault /// /// \descr Get the output overvoltage fault /// /// \param pucCHXOV /// /// \return boolean: TRUE - data are valid /// FALSE - data shall be discard //----------------------------------------------------------------------------- boolean CddCpsq5453_GetCHXOV(uint8* pucCHXOV) { if (pucCHXOV != NULL_PTR) { *pucCHXOV = CddCpsq5453_DataMirror.StatRx.Reg0x11.Bit.biCH1OV;//CH2OV is disabled if 2PH is set to '1' } // return SPI Error status bit return ((CddCpsq5453_DataMirror.StatRx.Reg0x11.unRaw & CDDCPSQ5453_SPE) != CDDCPSQ5453_SPE) ? TRUE : FALSE; } //----------------------------------------------------------------------------- /// \brief Get the output overvoltage fault /// /// \descr Get the output overvoltage fault /// /// \param pucCHXUV /// /// \return boolean: TRUE - data are valid /// FALSE - data shall be discard //----------------------------------------------------------------------------- boolean CddCpsq5453_GetCHXUV(uint8* pucCHXUV) { if (pucCHXUV != NULL_PTR) { *pucCHXUV = CddCpsq5453_DataMirror.StatRx.Reg0x11.Bit.biCH1UV;//CH2UV is disabled if 2PH is set to '1' } // return SPI Error status bit return ((CddCpsq5453_DataMirror.StatRx.Reg0x11.unRaw & CDDCPSQ5453_SPE) != CDDCPSQ5453_SPE) ? TRUE : FALSE; } //----------------------------------------------------------------------------- /// \brief CHx output current less than 0.5 times of the set value (CH2UC is disabled if 2PH is set to '1'). /// /// \descr CHx output current less than 0.5 times of the set value (CH2UC is disabled if 2PH is set to '1'). /// /// \param pucCHXUC /// /// \return boolean: TRUE - data are valid /// FALSE - data shall be discard //----------------------------------------------------------------------------- boolean CddCpsq5453_GetCHXUC(uint8* pucCHXUC) { if (pucCHXUC != NULL_PTR) { *pucCHXUC = CddCpsq5453_DataMirror.StatRx.Reg0x12.Bit.biCH1UC;//CH2UC is disabled if 2PH is set to '1' } // return SPI Error status bit return ((CddCpsq5453_DataMirror.StatRx.Reg0x12.unRaw & CDDCPSQ5453_SPE) != CDDCPSQ5453_SPE) ? TRUE : FALSE; } //----------------------------------------------------------------------------- /// \brief CHx output current more then 1.5 times of the set value /// /// \descr CHx output current more then 1.5 times of the set value /// /// \param pucCHXOC /// /// \return boolean: TRUE - data are valid /// FALSE - data shall be discard //----------------------------------------------------------------------------- boolean CddCpsq5453_GetCHXOC(uint8* pucCHXOC) { if (pucCHXOC != NULL_PTR) { *pucCHXOC = CddCpsq5453_DataMirror.StatRx.Reg0x12.Bit.biCH1OC;//CH2OC is disabled if 2PH is set to '1' } // return SPI Error status bit return ((CddCpsq5453_DataMirror.StatRx.Reg0x12.unRaw & CDDCPSQ5453_SPE) != CDDCPSQ5453_SPE) ? TRUE : FALSE; } //----------------------------------------------------------------------------- /// \brief ILIM bit is only set after CHxILIMCNT counter has reached the programmed value /// /// \descr ILIM bit is only set after CHxILIMCNT counter has reached the programmed value /// /// \param pucCHXILIM /// /// \return boolean: TRUE - data are valid /// FALSE - data shall be discard //----------------------------------------------------------------------------- boolean CddCpsq5453_GetCHXILIM(uint8* pucCHXILIM) { if (pucCHXILIM != NULL_PTR) { *pucCHXILIM = CddCpsq5453_DataMirror.StatRx.Reg0x12.Bit.biCH1ILIM;//CH2OC is disabled if 2PH is set to '1' } // return SPI Error status bit return ((CddCpsq5453_DataMirror.StatRx.Reg0x12.unRaw & CDDCPSQ5453_SPE) != CDDCPSQ5453_SPE) ? TRUE : FALSE; } //----------------------------------------------------------------------------- /// \brief ILIM bit is only set after CHxILIMCNT counter has reached the programmed value /// /// \descr ILIM bit is only set after CHxILIMCNT counter has reached the programmed value /// /// \param pucCHXILIM /// /// \return boolean: TRUE - data are valid /// FALSE - data shall be discard //----------------------------------------------------------------------------- boolean CddCpsq5453_GetCHXISO(uint8* pucCHXISO) { if (pucCHXISO != NULL_PTR) { *pucCHXISO = CddCpsq5453_DataMirror.StatRx.Reg0x12.Bit.biCH1ISO;//CH2OC is disabled if 2PH is set to '1' } // return SPI Error status bit return ((CddCpsq5453_DataMirror.StatRx.Reg0x12.unRaw & CDDCPSQ5453_SPE) != CDDCPSQ5453_SPE) ? TRUE : FALSE; } //----------------------------------------------------------------------------- // Function definitions //----------------------------------------------------------------------------- //----------------------------------------------------------------------------- /// \brief get content of status register FLT1 /// /// \descr /// /// \param ulChnIdx : channel index /// \param pFLT1 :content of status register FLT1(REG0x11) /// /// \return boolean: TRUE - data are valid /// FALSE - data shall be discard //----------------------------------------------------------------------------- boolean CddCpsq5453_GetFLT1(tCddCpsq5453_Reg0x11* pFLT1) { *pFLT1 = CddCpsq5453_DataMirror.StatRx.Reg0x11; // return SPI Error bit status return ((CddCpsq5453_DataMirror.StatRx.Reg0x11.unRaw & CDDCPSQ5453_SPE) != CDDCPSQ5453_SPE) ? TRUE : FALSE; } //----------------------------------------------------------------------------- // Function definitions //----------------------------------------------------------------------------- //----------------------------------------------------------------------------- /// \brief get content of status register FLT2 /// /// \descr /// /// \param ulChnIdx : channel index /// \param pFLT2 : content of status register FLT2(REG0x12) /// /// \return boolean: TRUE - data are valid /// FALSE - data shall be discard //----------------------------------------------------------------------------- boolean CddCpsq5453_GetFLT2(tCddCpsq5453_Reg0x12* pFLT2) { *pFLT2 = CddCpsq5453_DataMirror.StatRx.Reg0x12; // return SPI Error bit status return ((CddCpsq5453_DataMirror.StatRx.Reg0x12.unRaw & CDDCPSQ5453_SPE) != CDDCPSQ5453_SPE) ? TRUE : FALSE; } //----------------------------------------------------------------------------- // Function definitions //----------------------------------------------------------------------------- //----------------------------------------------------------------------------- /// \brief CddCpsq5453_UpdateBoostSts /// /// \descr /// /// \param - /// /// \return - //----------------------------------------------------------------------------- void CddCpsq5453_UpdateBoostSts(void) { boolean boSpiErrReg12 = FALSE; boolean boSpiErrReg11 = FALSE; /* Boost cycle-by-cycle current limit */ boSpiErrReg12 = CddCpsq5453_GetCHXILIM(&CddCpsq5453_Boost_Sts.ucBoostILIM); if( TRUE != boSpiErrReg12 ) // FALSE : SPI error, TRUE: SPI OK { CddCpsq5453_Boost_Sts.ucBoostILIM = CDDCPSQ5453_BOOST_STATE_INVALID; } /* Boost IS open */ boSpiErrReg12 = CddCpsq5453_GetCHXISO(&CddCpsq5453_Boost_Sts.ucBoostISO); if( TRUE != boSpiErrReg12 ) // FALSE : SPI error, TRUE: SPI OK { CddCpsq5453_Boost_Sts.ucBoostISO = CDDCPSQ5453_BOOST_STATE_INVALID; } /* Boost output over voltage */ boSpiErrReg11 = CddCpsq5453_GetCHXOV(&CddCpsq5453_Boost_Sts.ucBoostOV); if( TRUE != boSpiErrReg11 ) // FALSE : SPI error, TRUE: SPI OK { CddCpsq5453_Boost_Sts.ucBoostOV = CDDCPSQ5453_BOOST_STATE_INVALID; } /* Boost power cycle */ boSpiErrReg11 = CddCpsq5453_GetPowerCycled(&CddCpsq5453_Boost_Sts.ucBoostPC); if( TRUE != boSpiErrReg11 ) // FALSE : SPI error, TRUE: SPI OK { CddCpsq5453_Boost_Sts.ucBoostPC = CDDCPSQ5453_BOOST_STATE_INVALID; } /* Boost RT open */ boSpiErrReg11 = CddCpsq5453_GetRTO(&CddCpsq5453_Boost_Sts.ucBoostRTO); if( TRUE != boSpiErrReg11 ) // FALSE : SPI error, TRUE: SPI OK { CddCpsq5453_Boost_Sts.ucBoostRTO = CDDCPSQ5453_BOOST_STATE_INVALID; } /* Boost thermal warning */ boSpiErrReg11 = CddCpsq5453_GetThermalWarning(&CddCpsq5453_Boost_Sts.ucBoostTW); if( TRUE != boSpiErrReg11 ) // FALSE : SPI error, TRUE: SPI OK { CddCpsq5453_Boost_Sts.ucBoostTW = CDDCPSQ5453_BOOST_STATE_INVALID; } /* Boost output under voltage */ boSpiErrReg11 = CddCpsq5453_GetCHXUV(&CddCpsq5453_Boost_Sts.ucBoostUV); if( TRUE != boSpiErrReg11 ) // FALSE : SPI error, TRUE: SPI OK { CddCpsq5453_Boost_Sts.ucBoostUV = CDDCPSQ5453_BOOST_STATE_INVALID; } if( (TRUE != boSpiErrReg12) || (TRUE != boSpiErrReg11) ) // FALSE : SPI error, TRUE: SPI OK { CddCpsq5453_Boost_Sts.ucBoostSpiErr = TRUE; } else { CddCpsq5453_Boost_Sts.ucBoostSpiErr = FALSE; } } //----------------------------------------------------------------------------- /// \brief Calculate odd parity bit based on 15 bits (Cmd, Addr, Data) and /// add it to bit position 8 /// /// \descr Concatenate Command bit, Address register and Data /// Calculate parity bit based on Cmd, Addr and data /// Add parity bit in order to have an odd parity on SPI Tx frame /// /// \param unCmd : Read or Write command bit shifted at the bit15 /// \param unAddr : Register address shifted at the bit position 9 /// \param unData : Data shifted at the bit position 0 /// /// \return uint16 : complete SPI command frame (Cmd, Addr, Parity Bit, Data) //----------------------------------------------------------------------------- STATIC_AL uint16 CddCpsq5453_AssembleSPICmd(const uint16 unCmd, const uint16 unAddr, const uint16 unData) { uint16 assembledCmd = 0; // Build this to shift through parity calculation uint16 parity = 0; // Parity bit calculated here uint16 packet = 0; // This will be what we send if(CDDCPSQ5453_WriteCmd == unCmd) { assembledCmd |= 0x8000; // Set CMD = 1 } assembledCmd |= (((unAddr << 9) & 0x7E00) | (uint16)(unData & 0x00FF)); packet = assembledCmd; // Calculate parity while(assembledCmd > 0) { // Count the number of 1s in the LSb if(assembledCmd & 0x0001) { parity++; } // Shift right assembledCmd >>= 1; } // If the LSb is a 0 (even # of 1s), we need to add the odd parity bit if(!(parity & 0x0001)) { packet |= (1 << 8); } return(packet); } //----------------------------------------------------------------------------- /// \brief Action executed synchronously with schedule Table /// /// \descr /// /// \param ucAction /// /// \return boolean //----------------------------------------------------------------------------- STATIC_AL boolean CddCpsq5453_StAction(const uint8 ucAction) { boolean boRestart = FALSE; switch (ucAction) { case CDDCPSQ5453_ST_ACT_DIS_BOOST_GPIO: CddCpsq5453_SetBoostEnableGpio(FALSE); break; case CDDCPSQ5453_ST_ACT_EN_BOOST_GPIO: CddCpsq5453_SetBoostEnableGpio(TRUE); break; case CDDCPSQ5453_ST_ACT_DIS_BOOST_LH_GPIO: CddCpsq5453_SetBoostLimpHomeGpio(FALSE); break; case CDDCPSQ5453_ST_ACT_EN_BOOST_REG: CddCpsq5453_DataMirror.CtrlTx.Reg0x00.Bit.biCH1EN = 1; CddCpsq5453_DataMirror.CtrlTx.Reg0x00.Bit.biCH2EN = 1; CddCpsq5453_DataMirror.CtrlTx.Reg0x00.Bit.biCH1PDRVEN = 0; CddCpsq5453_DataMirror.CtrlTx.Reg0x00.Bit.biCH2PDRVEN = 1; CddCpsq5453_DataMirror.CtrlTx.Reg0x00.Bit.biCH1MAXDEN = 0; CddCpsq5453_DataMirror.CtrlTx.Reg0x00.Bit.biCH2MAXDEN = 0; CddCpsq5453_DataMirror.CtrlTx.Reg0x00.Bit.biSYNCEN = 0; CddCpsq5453_DataMirror.CtrlTx.Reg0x00.Bit.biFPINRST = 0; break; case CDDCPSQ5453_ST_ACT_DIS_BOOST_REG: break; case CDDCPSQ5453_ST_ACT_EN_BOOST_PWM: CddCpsq5453_SetBoostDuty(TRUE); break; case CDDCPSQ5453_ST_ACT_DIS_BOOST_PWM: CddCpsq5453_SetBoostDuty(FALSE); break; case CDDCPSQ5453_ST_ACT_READ_BOOST_FLT1: if (CddCpsq5453_DataMirror.StatRx.Reg0x11.Bit.biPC == 1) { boRestart = TRUE; } break; default: //Do nothing break; } return boRestart; } //----------------------------------------------------------------------------- /// \brief Called after reception of a SPI frame /// /// \descr The function reads the content of SPI Rx data provided by SPI and /// store data in CddCpsq5453_DataMirror. /// /// \param unIx /// \param ulData : SPI Rx data (only 16 LSB valid) /// /// \return void //----------------------------------------------------------------------------- void CddCpsq5453_SpiRx(const uint16 unIx, const uint32 ulData) { boolean boSchTableRestart = FALSE; #if (CDDBUCK_CHIP_ERROR_HAND == CDDBUCk_CHIP_CPSQ5352) /* polling first frame processing - Send then Receive */ if(CddCpsq5453_cycleSpi == 0u) { CddCpsq5453_cycleSpi = 1u; } else { // calculate pointer to actual schedule table entry const tCddCpsq5453_SpiSchedTable* pTabEntry = &aCddCpsq5453_SpiSchedTable[CddCpsq5453_unSchedIx_Rx]; pTabEntry->punRx[unIx] = (uint16) ulData; // store RX data (only 16 LSB are relevant) if ( 20u == CddCpsq5453_unSchedIx_Rx ) { CddCpsq5453_UpdateBoostSts(); } // set index to next schedule table entry CddCpsq5453_unSchedIx_Rx = pTabEntry->ucNextEntry; CddCpsq5453_unSchedIx_Tx = pTabEntry->ucNextEntry; // make copy to ensure synchronism of RX and TX // calculate pointer to actual schedule table entry (read next TX entry to check action) pTabEntry = &aCddCpsq5453_SpiSchedTable[CddCpsq5453_unSchedIx_Tx]; if (pTabEntry->ucAction != CDDCPSQ5453_ST_NO_ACT) { boSchTableRestart = CddCpsq5453_StAction(pTabEntry->ucAction); if (boSchTableRestart != FALSE) { CddCpsq5453_unSchedIx_Rx = 0u; CddCpsq5453_unSchedIx_Tx = 0u; } } } #else // calculate pointer to actual schedule table entry const tCddCpsq5453_SpiSchedTable* pTabEntry = &aCddCpsq5453_SpiSchedTable[CddCpsq5453_unSchedIx_Rx]; pTabEntry->punRx[unIx] = (uint16) ulData; // store RX data (only 16 LSB are relevant) // set index to next schedule table entry CddCpsq5453_unSchedIx_Rx = pTabEntry->ucNextEntry; CddCpsq5453_unSchedIx_Tx = pTabEntry->ucNextEntry; // make copy to ensure synchronism of RX and TX // calculate pointer to actual schedule table entry (read next TX entry to check action) pTabEntry = &aCddCpsq5453_SpiSchedTable[CddCpsq5453_unSchedIx_Tx]; if (pTabEntry->ucAction != CDDCPSQ5453_ST_NO_ACT) { boSchTableRestart = CddCpsq5453_StAction(pTabEntry->ucAction); if (boSchTableRestart != FALSE) { CddCpsq5453_unSchedIx_Rx = 0u; CddCpsq5453_unSchedIx_Tx = 0u; } } #endif } //----------------------------------------------------------------------------- /// \brief Called before transmission of SPI telegram /// /// \descr The function reads the content of CddCpsq5453_DataMirror /// and adds the odd parity bit. /// /// \param unIx /// /// \return uint32 : Tx data (16 LSB are valid) //----------------------------------------------------------------------------- uint32 CddCpsq5453_SpiTx(const uint16 unIx) { // calculate pointer to actual schedule table entry const tCddCpsq5453_SpiSchedTable* pSchedEntry = &aCddCpsq5453_SpiSchedTable[CddCpsq5453_unSchedIx_Tx]; (void)unIx; // switch to next schedule table entry for next transmission CddCpsq5453_unSchedIx_Tx = pSchedEntry->ucNextEntry; // get SPI command (read or write), register address and contents of control register for next SPI frame // update parity bit according to control register data return (uint32) CddCpsq5453_AssembleSPICmd(pSchedEntry->unCmd, pSchedEntry->unAddr, *(pSchedEntry->punTx)); } #if (CDDBUCK_CHIP_ERROR_HAND == CDDBUCk_CHIP_CPSQ5352) //----------------------------------------------------------------------------- /// \brief Boost Chip Initialization - SPI Setup /// /// \descr This function sends SPI frames for initializing the boost /// - 20 frames of data in total /// /// \param void /// /// \return void : //----------------------------------------------------------------------------- void CddCpsq5453_SpiInit(void) { uint32 TransferCnt= 0ul; uint32 ulTxData = 0ul; uint8 ucDevIdx = 0u; uint8 ucRxBuff[2]; uint8 ucTxBuff[2]; const tCddCpsq5453_SpiSchedTable* pTabEntry_Init; /* Send initialization data */ for(ucDevIdx = 0u; ucDevIdx < CDDCPSQ5453_Cfg_SpiinitSchedTableLen; ucDevIdx++) { /* calculate pointer to actual schedule table entry */ pTabEntry_Init = &aCddCpsq5453_SpiSchedTable[ucDevIdx]; ulTxData = CddCpsq5453_AssembleSPICmd(pTabEntry_Init->unCmd, pTabEntry_Init->unAddr, *(pTabEntry_Init->punTx)); ucTxBuff[0] = ulTxData & 0x00FF; ucTxBuff[1] = ulTxData >> 8; /* Send operation */ Spi_SetAsyncMode(SPI_INTERRUPT_MODE); Spi_SetupEB(SpiConf_SpiChannel_SpiChl_Boost,ucTxBuff, ucRxBuff, 2u); Spi_AsyncTransmit(SpiConf_SpiChannel_SpiChl_Boost); /* Waiting for sending to complete */ TransferCnt = 0ul; while ((Spi_GetJobResult(SpiConf_SpiChannel_SpiChl_Boost) != 0) && (TransferCnt < 30000ul)) { TransferCnt++; } *pTabEntry_Init->punRx = ucRxBuff[0] | (ucRxBuff[1]<<8); /* */ if(ucDevIdx < CDDCPSQ5453_Cfg_SpiinitSchedTableLen - 1) { pTabEntry_Init = &aCddCpsq5453_SpiSchedTable[ucDevIdx+1]; if (pTabEntry_Init->ucAction != CDDCPSQ5453_ST_NO_ACT) { (void) CddCpsq5453_StAction(pTabEntry_Init->ucAction); } else{} } else{} } } #endif #if 0 //----------------------------------------------------------------------------- /// \brief Called before SBC sleep /// /// \descr The function disables the booster /// /// \param void /// /// \return void //----------------------------------------------------------------------------- void CddCpsq5453_SetBoostSleep(void) { uint16 unCmdAddrData = CddCpsq5453_CalculateAndAddOddParityBit(CDDCPSQ5453_WriteCmd, CDDCPSQ5453_WriteReg0x06Addr, 0u); (void)CDDBOOST_TransferMsg((uint8)CDDSPI_DEVICE(BOOST), &unCmdAddrData); } #endif #define ctadCddBoost_STOP_SEC_CODE #include <../Cfg/CddCpsq5453_MemMap.h> //----------------------------------------------------------------------------- // End declaration or definitions of functions //-----------------------------------------------------------------------------